Semiconductor device and manufacturing method for the same

Abstract

To improve the performance of a semiconductor device.SOLUTION: An electrode pad PD included in a semiconductor chip CP includes, in a plan view, a region R1 including a center of an exposed part, a region R2 existing around the region R1, and a region R3 existing around the region R1 and between the region R1 and the region R2. On a semiconductor substrate, a groove TR1 that separates a plurality of semiconductor elements Q1 formed in the semiconductor substrate from each other is formed. The semiconductor substrate includes a region R4 overlapping with the region R3 and not overlapping with the regions R1 and R2, and a region R5 overlapping with the region R1 and not overlapping with the region R3. The groove TR1 is not formed in the region R4 and is formed in the region R5 on the semiconductor substrate.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] JP 2023-11445 A (Patent Document 1) describes a semiconductor device in which a groove is formed on the upper surface of a semiconductor substrate at a position that overlaps with an electrode pad formed on the upper surface of the semiconductor substrate and is spaced from an element isolation prohibited area that overlaps with an end of a ball portion of a copper wire joined to the electrode pad. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-11445 A Summary of the Invention [Problem to be solved by the invention]

[0004] As in Patent Document 1, a semiconductor substrate is formed with an isolation trench for isolating a plurality of elements from one another. When the isolation trench is formed in a position of the semiconductor substrate that overlaps with an electrode pad formed on the upper surface of the semiconductor substrate, the periphery of the isolation trench may be damaged due to stress generated when bonding the ball portion of the wire to the electrode pad.

[0005] On the other hand, as part of efforts to improve the performance of a semiconductor device, from the viewpoint of reducing the planar size of the semiconductor device, it is preferable to form elements on the semiconductor substrate constituting the semiconductor device in positions that overlap with electrode pads that also constitute the semiconductor device.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] The electrode pad of the semiconductor device according to one embodiment includes, in a plan view, a first region including a center of an exposed portion, a second region located around the first region, and a third region located around the first region and between the first region and the second region. A first groove is formed in the semiconductor substrate to separate a plurality of semiconductor elements formed in the semiconductor substrate from each other. The semiconductor substrate includes a fourth region overlapping the third region and not overlapping the first region and the second region, and a fifth region overlapping the first region and not overlapping the third region. The first groove is not formed in the fourth region of the semiconductor substrate, and is formed in the fifth region. Effect of the Invention

[0008] According to the above embodiment, the performance of the semiconductor device can be improved. [Brief description of the drawings]

[0009] [Figure 1] 1 is a top view of a semiconductor device according to an embodiment; [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] 2 is a perspective plan view showing the internal structure of a semiconductor package seen through the sealing body shown in FIG. [Figure 4] 4 is an enlarged plan view showing one of a plurality of electrode pads included in the semiconductor chip shown in FIG. 3. [Diagram 5] 5 is an enlarged plan view showing the electrode pad before the wire shown in FIG. 4 is joined. [Figure 6] FIG. 6 is an enlarged cross-sectional view taken along line BB in FIG. 5. [Figure 7] 7 is an enlarged plan view showing a portion of the semiconductor substrate shown in FIG. 6 that overlaps with the enlarged plan view shown in FIG. 5. [Figure 8]1 is an enlarged plan view showing a schematic diagram of the vibration direction of ultrasonic waves applied in a wire bonding process and the positional relationship with a DTI. [Figure 9] 8 is an enlarged plan view showing a first modified example of the semiconductor substrate shown in FIG. 7. [Figure 10] 8 is an enlarged plan view showing a second modified example of the semiconductor substrate shown in FIG. 7. [Figure 11] 7 is an enlarged cross-sectional view showing a modification of the element isolation trench shown in FIG. 6. [Figure 12] 7 is an enlarged cross-sectional view showing a modified example of a groove formed in the semiconductor substrate shown in FIG. 6. [Figure 13] 1 is an explanatory diagram showing an assembly flow of a semiconductor package according to an embodiment; [Figure 14] 14 is an enlarged plan view showing a state in which a semiconductor chip is mounted on a die pad of a lead frame in the semiconductor chip mounting step shown in FIG. 13. [Figure 15] FIG. 4 is an enlarged cross-sectional view showing details of a wire bonding process. [Figure 16] FIG. 16 is an enlarged cross-sectional view showing the details of the wire bonding step following FIG. [Figure 17] FIG. 5 is an enlarged plan view showing a modification of FIG. [Figure 18] 18 is an enlarged plan view showing a portion of a semiconductor substrate included in the semiconductor chip shown in FIG. 17 that overlaps with the enlarged plan view shown in FIG. 17. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] (Description format, basic terms and usage in this application) In this application, the description of the embodiment is conveniently divided into multiple sections, etc., as necessary, but unless otherwise specified, these are not mutually independent and separate, and regardless of the description, each part of a single example, one is a partial detail of the other, or a partial or complete modified example, etc. In addition, as a general rule, repeated explanations of similar parts will be omitted. In addition, each component in the embodiment is not essential, unless otherwise specified, when it is theoretically limited to that number, or when it is clearly not from the context.

[0011] Similarly, in the description of the embodiments, when a material, composition, etc. is described as "X made of A," it does not exclude those containing elements other than A, unless otherwise specified or clearly indicated from the context. For example, when it comes to components, it means "X containing A as a main component." For example, when it comes to "silicon components," it goes without saying that it is not limited to pure silicon, but also includes SiGe (silicon germanium) alloys and other multi-component alloys whose main component is silicon, and components containing other additives. In addition, when it comes to gold plating, Cu layer, nickel plating, etc., it includes not only pure ones, but also components whose main components are gold, Cu, nickel, etc., unless otherwise specified.

[0012] Furthermore, even when a specific number or quantity is mentioned, unless otherwise specified, it may be a number greater than that specific number, or a number less than that specific number, unless it is theoretically limited to that number or unless it is clearly different from the context.

[0013] In addition, in each drawing of the embodiment, the same or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions thereof will not be repeated as a general rule.

[0014] In the accompanying drawings, hatching and the like may be omitted even in cross sections if it would be too complicated or if the distinction from voids is clear. In relation to this, the background contour lines may be omitted even in the case of holes that are closed in plan view if it is clear from the explanation, etc. Furthermore, hatching or dot patterns may be added even if the drawing is not a cross section in order to clearly indicate that it is not a void or to clearly indicate the boundaries of the area.

[0015] In this application, a semiconductor device is a device including a plurality of elements (semiconductor elements) formed on a semiconductor substrate and a wiring layer that electrically connects the plurality of elements. In the following description, a semiconductor chip will be distinguished from a semiconductor package in which a semiconductor chip is mounted on a chip mounting portion and sealed. Both the semiconductor chip and the semiconductor package are classified as semiconductor devices.

[0016] <Semiconductor packages> First, an outline of the configuration of a semiconductor package PKG1 according to the present embodiment will be described with reference to Fig. 1 to Fig. 3. Fig. 1 is a top view of the semiconductor package according to the present embodiment. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1. Fig. 3 is a perspective plan view showing the internal structure of the semiconductor package seen through the sealing body shown in Fig. 1.

[0017] In Figs. 1 to 3, either the X direction, the Y direction (see Figs. 1 and 3), or the Z direction (see Fig. 2) is shown. The Y direction is a side that intersects with the X direction, and in the following description, the X direction and the Y direction are perpendicular to each other. The Z direction is a direction perpendicular to each of the X direction and the Y direction. In other words, the Z direction is a normal direction to the XY plane that includes the X direction and the Y direction. In the following description, "thickness" basically means the length in the Z direction. In addition, in the following description, "planar view" basically means a planar view of the XY plane.

[0018] The technology described in the following embodiments is widely applicable to semiconductor packages in which wires or stud bumps (bumps in which a ball portion is formed at the tip of a wire, the ball portion is bonded to an electrode pad, and then the wire portion is cut off) are connected to electrode pads exposed on the surface of a semiconductor chip. In this embodiment, a lead frame type semiconductor package is taken up and described as an example of a semiconductor package in which wires are connected to electrode pads of a semiconductor chip. In the case of a lead frame type semiconductor package, a semiconductor chip mounted on a die pad of a lead frame and each of a plurality of leads arranged around the die pad are electrically connected via wires.

[0019] As shown in Figures 1 to 3, the semiconductor package PKG1 has a semiconductor chip CP (see Figures 2 and 3), a plurality of leads (terminals, external terminals) LD that are external terminals arranged around the semiconductor chip CP, and a plurality of wires BW (see Figures 2 and 3) that are conductive members that electrically connect the semiconductor chip CP and the plurality of leads LD. The semiconductor chip CP and the plurality of wires BW are sealed in a sealing body (resin body) MR. The inner lead parts ILD (see Figures 2 and 3) of each of the plurality of leads LD are sealed in the sealing body MR, and the outer lead parts OLD of each of the plurality of leads LD are exposed from the sealing body MR.

[0020] As shown in Fig. 1, the planar shape of the sealing body MR included in the semiconductor package PKG1 is a rectangle. The sealing body MR has a top surface MRt, a bottom surface (back surface, mounted surface) MRb (see Fig. 2) opposite to the top surface MRt, and a plurality of side surfaces MRs (four in Fig. 1) located between the top surface MRt and the bottom surface MRb.

[0021] In the semiconductor package PKG1, a plurality of leads LD are arranged along each of the four side surfaces MRs of the sealing body MR having a rectangular planar shape. The plurality of leads LD are made of metal, and in this embodiment, for example, are metal members mainly composed of copper (Cu). A semiconductor package in which a plurality of leads LD are arranged along each of the four sides of the sealing body MR as in this embodiment is called a QFP (Quad Flat Package). Although not shown, a semiconductor package in which a plurality of leads LD are arranged along two sides that are opposite to each other among the four sides of the sealing body MR and no leads LD are arranged on the other two sides is called a SOP (Small Outline Package). In this embodiment, an embodiment applied to the semiconductor package PKG1 that is a QFP will be described, but as a modified example, it may also be applied to a semiconductor package that is an SOP.

[0022] In the following embodiments, a semiconductor package PKG1 in which a semiconductor chip CP is mounted on a lead frame will be representatively described. However, the technology described below may be applied to a semiconductor package in which a semiconductor chip CP is mounted on a wiring board (not shown).

[0023] As shown in Fig. 2, the outer lead parts OLD of the multiple leads LD protrude from the side surface MRs of the sealing body MR toward the outside of the sealing body MR. In the case of QFP or SOP, the outer lead parts OLD protrude from the side surface MRs of the sealing body MR and are curved toward the mounting surface side. Although not shown, there is also a type of semiconductor package in which each of the multiple leads LD is exposed at the bottom surface MRb of the sealing body MR as a modified example of the semiconductor package PKG1. Semiconductor packages in which the leads LD are exposed at the bottom surface MRb of the sealing body MR include QFN (Quad Flat Non-leaded package) and SON (Small Outline Non-leaded package).

[0024] As shown in FIG. 2 and FIG. 3, the semiconductor chip CP is sealed inside the sealing body MR. As shown in FIG. 3, the semiconductor chip CP is rectangular in plan view and has an upper surface (main surface) CPt and a lower surface CPb (see FIG. 2) opposite to the upper surface CPt. On the upper surface CPt of the semiconductor chip CP, a plurality of electrode pads (bonding pads) PD are provided along each of the four sides constituting the outer edge of the upper surface CPt. In addition, the semiconductor chip CP (more specifically, a semiconductor substrate) is made of, for example, silicon (Si). Although not shown, a plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip CP (more specifically, a semiconductor element formation region provided on the upper surface of the semiconductor substrate of the semiconductor chip CP). The plurality of electrode pads PD are electrically connected to the semiconductor elements through wiring (not shown) formed in a wiring layer disposed inside the semiconductor chip CP (more specifically, between the upper surface CPt and a semiconductor element formation region not shown). That is, the plurality of electrode pads PD are electrically connected to a circuit formed on the semiconductor chip CP.

[0025] An insulating film is formed on the top surface CPt of the semiconductor chip CP to cover the substrate and wiring of the semiconductor chip CP, and the surfaces of the electrode pads PD are exposed from the insulating film through openings formed in the insulating film. The electrode pads PD are made of metal, and in this embodiment, are made of aluminum (Al), for example.

[0026] The semiconductor chip CP is mounted on a die pad DP which is a chip mounting portion. In the case of the semiconductor package PKG1, as shown in FIG. 3, in a plan view, a die pad (chip mounting portion) DP which is a chip mounting portion on which the semiconductor chip CP is mounted is disposed between four sides of the sealing body MR, and the semiconductor chip CP is mounted on an upper surface (front surface, main surface, chip mounting surface) DPt of the die pad DP. The upper surface DPt of the die pad DP is a rectangle whose plane area is larger than the surface area of ​​the semiconductor chip CP. However, the die pad DP is a support member which supports the semiconductor chip CP, and various modified shapes and sizes can be applied in addition to the example shown in FIG. 3. For example, the planar shape of the die pad DP may be a circle. Also, for example, the plane area of ​​the die pad DP may be smaller than the upper surface CPt of the semiconductor chip CP. In addition, in the case of the semiconductor package PKG1, the die pad DP is sealed in the sealing body MR. Although not shown, as a modified example of the semiconductor package PKG1, the lower surface of the die pad DP may be exposed from the sealing body MR at the lower surface MRb of the sealing body MR.

[0027] 2, the semiconductor chip CP is mounted on the die pad DP via a die bond material (adhesive material) DB with the bottom surface CPb facing the top surface DPt of the die pad DP. That is, the semiconductor chip CP is mounted by a so-called face-up mounting method in which the opposite surface (bottom surface CPb) of the top surface (main surface) CPt on which the multiple electrode pads PD are formed faces the chip mounting surface (top surface DPt). This die bond material DB is an adhesive material used when die-bonding the semiconductor chip CP, and is, for example, a conductive resin adhesive material containing multiple (multiple) conductive particles (for example, silver particles) in an epoxy-based thermosetting resin, or a solder material.

[0028] A plurality of leads LD are arranged around the semiconductor chip CP (in other words, around the die pad DP). A plurality of electrode pads (electrodes, pads) PD exposed on the upper surface CPt of the semiconductor chip CP are electrically connected to inner lead portions ILD of the plurality of leads LD located inside the sealing body MR via a plurality of wires (conductive members) BW. One end of the wire BW (ball portion BWb shown in FIG. 14 described later) is bonded to the electrode pad PD, and the other end is bonded to a portion (wire bonding region) of the inner lead portion ILD.

[0029] The wire BW in this embodiment is made of, for example, copper (Cu). However, the material of the wire BW is not limited to copper, and various modifications such as gold (Au) can be applied. When the wire BW is made of copper, it is preferable from the viewpoint of reducing material costs or reducing the impedance component of the transmission path formed by the wire.

[0030] Moreover, a plurality of hanging leads HL are arranged around the die pad DP as shown in Fig. 3. The hanging leads HL are members for supporting the die pad DP on a supporting portion (frame portion) of a lead frame in the manufacturing process of the semiconductor package PKG1.

[0031] <Semiconductor chip> Next, the semiconductor chip shown in FIG. 2 and FIG. 3 will be described. FIG. 4 is an enlarged plan view showing one of the electrode pads of the semiconductor chip shown in FIG. 3. FIG. 5 is an enlarged plan view showing the electrode pad before the wire is bonded as shown in FIG. 4. In FIG. 4 and FIG. 5, the outline of the electrode pad PD is shown by a dotted line to show the planar shape of the part of the electrode pad PD covered with the insulating layer PV. In FIG. 4 and FIG. 5, the boundaries of the regions R1, R2, and R3 are shown by two-dot chain lines. FIG. 6 is an enlarged cross-sectional view taken along the line BB in FIG. 5. FIG. 7 is an enlarged plan view showing a part of the semiconductor substrate shown in FIG. 6 that overlaps with the enlarged plane shown in FIG. 5. In FIG. 7, the boundaries of the regions R4, R5, and R6 are shown by two-dot chain lines. FIG. 7 is a plan view of the semiconductor substrate, but the outline of the electrode pad PD is shown by a dotted line to show the planar positional relationship between the electrode pad PD and the regions R4, R5, and R6 of the semiconductor substrate SS.

[0032] For simplicity, an example in which one insulating layer IL1 is disposed between the electrode pad PD and the semiconductor substrate SS is shown in Fig. 6. However, there are cases in which multiple wiring layers and multiple insulating layers IL1 are alternately stacked between the electrode pad PD and the semiconductor substrate SS.

[0033] 3, the semiconductor chip CP has an upper surface (main surface) CPt. The upper surface CPt of the semiconductor chip CP is quadrangular in plan view and includes a side CPs1 extending in the X direction, a side CPs2 extending along the Y direction intersecting (orthogonal to) the X direction, a side CPs3 located opposite to the side CPs1, and a side CPs4 located opposite to the side CPs2.

[0034] On the top surface CPt, there is formed an insulating layer (protective film, protective insulating film) PV shown in Figures 4 and 6. The insulating layer PV is made of, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a laminated film of these.

[0035] The electrode pad PD is formed between the insulating layer PV and the semiconductor substrate SS (more specifically, between the insulating layer PV and the insulating layer IL1) as shown in Fig. 6. A portion of the electrode pad PD is exposed from the insulating layer PV at an opening PVk formed in the insulating layer PV. A plurality of openings PVk (see Fig. 3) are formed in the insulating layer PV, and the electrode pad PD is exposed in each of the plurality of openings PVk. In other words, the electrode pad PD has an exposed portion PDE exposed in the opening PVk of the insulating layer PV, and a peripheral portion PDP located around the exposed portion PDE and covered with the insulating layer PV.

[0036] 4, the ball portion BWb of the wire BW is joined to a part of the exposed portion PDE of the electrode pad PD. In the present embodiment, the ball portion BWb of the wire BW is joined to the region R1 and the region R3 of the exposed portion PDE.

[0037] The planar shape of the exposed portion PDE of the electrode pad PD is a rectangle. This can be expressed as follows. That is, each of the multiple openings PVk formed in the insulating layer PV has multiple sides. The opening shape of the opening PVk includes a side Pks1 extending in the X direction, a side Pks2 extending along the Y direction intersecting the X direction (orthogonal in the example shown in FIG. 4), a side Pks3 located opposite to the side Pks1, and a side Pks4 located opposite to the side Pks2. The side Pks1 of the opening PVk is arranged along the side CPs1 of the semiconductor chip CP, and the side Pks2 of the opening PVk is arranged along the side CPs2 of the semiconductor chip CP. Moreover, the side Pks3 of the opening PVk is arranged along the side CPs3 of the semiconductor chip CP, and the side Pks4 of the opening PVk is arranged along the side CPs4 of the semiconductor chip CP.

[0038] In a plan view, the exposed portion PDE of the electrode pad PD has a region R1 including the center of the opening PVk, a region R2 located around the region R1, and a region R3 located around the region R1 and between the regions R1 and R2.

[0039] Region R3 is provided in a ring shape along each side of the exposed portion PDE of the electrode pad PD in a plan view so that the planar shape of region R3 is a hollow rectangle. In the example shown in Figures 4 and 5, the outer edge of region R1 (the boundary between region R1 and region R3) and the outer edge of region R3 (the boundary between region R3 and region R2) are each a rectangle. Region R2 is disposed on the outermost periphery of the exposed portion PDE, and its outer edge (the boundary between region R2 and the peripheral portion PDP) is a rectangle.

[0040] As shown in Fig. 4, the outer edge of the ball portion BWb of the wire BW overlaps with the region R3 in a plan view. In the example shown in Fig. 4, a part of the outer edge of the ball portion BWb of the wire BW overlaps with the region R3, and another part of the outer edge of the ball portion BWb of the wire BW overlaps with the region R1.

[0041] 6, the semiconductor chip CP has a semiconductor substrate SS having an upper surface SSt and an insulating layer IL1 formed on the upper surface SSt of the semiconductor substrate SS. The electrode pads PD are formed on the insulating layer IL1. The insulating layer PV is formed on the insulating layer IL1 so as to cover the peripheral portion PDP of the electrode pads PD.

[0042] For simplicity, Fig. 6 shows an example in which one insulating layer IL1 is disposed between the electrode pad PD and the semiconductor substrate SS. However, the number of insulating layers IL1 disposed between the electrode pad PD and the semiconductor substrate SS is not limited to one, and may be two or more. For example, multiple wiring layers (not shown) may be formed between the electrode pad PD and the semiconductor substrate SS, and multiple insulating layers IL1 may be disposed as interlayer insulating films between the wiring layers. The insulating layer IL1 is made of, for example, silicon oxide (SiO2).

[0043] The semiconductor substrate SS is the base material of the semiconductor chip CP, and is composed, for example, of silicon (Si) as a main component. The semiconductor element Q1 has a semiconductor region with p-type or n-type conductivity. The semiconductor region is formed by doping impurities from the top surface SSt of the semiconductor substrate SS. The bottom surface of the semiconductor element Q1, which will be described later, is defined as the surface including the position of the semiconductor region doped with impurities that is farthest from the top surface SSt in the thickness direction of the semiconductor substrate SS.

[0044] A plurality of trenches TR are formed in the semiconductor substrate SS. The plurality of trenches TR include a trench TR1. The trench TR1 is an element isolation trench (DTI: Deep Trench Isolation) for isolating a plurality of semiconductor elements Q1 formed in the semiconductor substrate SS. Each of the plurality of semiconductor elements Q1 formed on the upper surface SSt of the semiconductor substrate SS includes an element such as a transistor or a diode. As shown in Fig. 6, when the top surface SSt of the semiconductor substrate SS is taken as a reference plane, the groove TR1 extends to a position deeper than the semiconductor element Q1. In other words, when the top surface SSt of the semiconductor substrate SS is taken as a reference plane, the distance from the top surface SSt to the bottom surface of the groove TR1 is longer than the distance from the top surface SSt to the bottom surface of the semiconductor element Q1. For example, in the example shown in Fig. 6, the depth of the groove TR1 (the distance from the top surface SSt to the bottom surface of the groove TR1) is about 1 µm to 20 µm. On the other hand, the depth of the semiconductor element Q1 from the top surface SSt is about 50 nm to 100 nm. As shown in FIG. 7, the trench TR1 continuously surrounds the periphery of the semiconductor element Q1. By providing the trench TR1, which is an element isolation trench, so as to surround the periphery of the semiconductor element Q1, it is possible to prevent the semiconductor elements Q1 from interfering with each other. The width of the trench TR, i.e., the dimension of the opening located on the upper surface SSt of the semiconductor substrate SS shown in FIG. 6, is, for example, about 0.5 μm to 1.0 μm. In the following description, an element isolation trench that is arranged so as to continuously surround the periphery of the semiconductor element Q1 and extends to a position deeper than the semiconductor element Q1 with the upper surface SSt of the semiconductor substrate SS as a reference plane, like the trench TR1, may be referred to as DTI.

[0045] <Issues regarding the position of element isolation trenches> However, according to the study of the present inventors, it has been found that when the DTI is arranged at a position overlapping the electrode pad PD, a crack may occur in the insulating layer IL1, causing the insulating layer IL1 to peel off from the semiconductor substrate SS. The above-mentioned crack occurs in the wire bonding process in which the wire BW shown in Fig. 4 is bonded to the electrode pad PD. More specifically, it is considered that the crack occurs when stress generated by ultrasonic waves applied to the ball portion BWb of the wire BW in the wire bonding process is concentrated around the DTI.

[0046] The easiest way to prevent the above-mentioned cracks from occurring is to not place the DTI at a position that overlaps with the electrode pad PD. In this case, the occurrence of cracks can be prevented by increasing the distance between the electrode pad PD, through which the ultrasonic waves are propagated, and the DTI.

[0047] However, if the DTI is not disposed on the electrode pad PD, the semiconductor element Q1 (see FIG. 7) cannot be disposed at a position overlapping the electrode pad PD. In this case, the area overlapping the electrode pad PD cannot be used as an active area. Therefore, from the viewpoint of reducing the planar size of the semiconductor chip CP, it is preferable to dispose the DTI and the semiconductor element Q1 also at a position overlapping the electrode pad PD.

[0048] Therefore, the inventors of the present application further investigated the conditions for the occurrence of the above-mentioned cracks in detail and found that, depending on the positional relationship between the ball portion BWb of the wire BW and the DTI, cracks may not occur easily even if the DTI is formed at a position overlapping with the electrode pad PD. Below, the conditions for the occurrence of cracks and a method for arranging the DTI taking these conditions into consideration will be described in detail.

[0049] As shown in Fig. 4, the ball portion BWb of the wire BW is circular in plan view. According to the study by the present inventors, it was found that when a DTI is formed at a position overlapping with the outer edge of the circular ball portion BWb, cracks are likely to occur near the DTI. It was also found that a DTI arranged at a position not overlapping with the outer edge of the circular ball portion BWb is unlikely to cause cracks.

[0050] Furthermore, according to the study by the present inventors, it was found that the frequency of crack occurrence is related to the vibration direction of the ultrasonic waves applied to the wire BW during wire bonding and the extending direction of the DTI.

[0051] Fig. 8 is an enlarged plan view showing the vibration direction of the ultrasonic waves applied in the wire bonding process and the positional relationship with the DTI. In Fig. 8, the outer edge of the electrode pad PD and the outer edge of the ball part BWb of the wire BW are shown by dotted lines. In Fig. 8, the boundaries of the regions R4, R5, and R6 are shown by two-dot chain lines.

[0052] For example, a case will be described in which the vibration direction of the ultrasonic waves USW is parallel to the X direction as shown in Fig. 8. Each of the grooves TRA, TRB, and TRC shown in Fig. 8 has the same depth as the groove TR1 shown in Figs.

[0053] The groove TRA extends in a direction intersecting the vibration direction of the ultrasonic waves USW (Y direction in FIG. 8), and a part of the groove TRA overlaps with the outer edge of the ball portion BWb. The groove TRA is likely to cause cracks to occur.

[0054] The groove TRB extends along the vibration direction of the ultrasonic wave USW, and the end of the groove TRB does not overlap with the outer edge of the ball portion BWb. In this case, although a part of the groove TRB overlaps with the outer edge of the ball portion BWb, the groove TRB is unlikely to cause cracks.

[0055] The groove TRC extends along the vibration direction of the ultrasonic waves USW, and an end of the groove TRC overlaps with the outer edge of the ball portion BWb. The groove TRA is likely to cause cracks to occur.

[0056] Moreover, the depth and width (length of one side) of hole HA shown in Figure 8 are the same as the depth and width (width of the opening) of groove TR. The planar shape of hole HA is a square with sides approximately the same as the width (length in the direction intersecting the extension direction) of groove TR. Hole HA overlaps with the outer edge of ball portion BWb. However, hole HA is unlikely to cause cracks to occur.

[0057] From the above findings, the mechanism of crack generation is presumed to be as follows: When the DTI is disposed at a position overlapping with the outer edge of the ball portion BWb of the wire BW, the stress generated by the propagation of the ultrasonic wave USW tends to concentrate around the DTI.

[0058] However, when the opening area is small, such as hole HA, the value of the stress propagated to the periphery of hole HA is small, so it is considered that it is unlikely to cause cracks to occur. Note that, although Fig. 8 shows an example in which the opening shape of hole HA is square, the same applies when, for example, the opening diameter of hole HA is circular.

[0059] Furthermore, when the groove TRB extends along the vibration direction of the ultrasonic wave USW and the end of the groove TRB does not overlap with the outer edge of the ball portion BWb, it is considered that stress is less likely to concentrate at the position overlapping with the ball portion BWb, and therefore it is less likely to cause cracks.

[0060] The vibration direction of the ultrasonic USW can be set arbitrarily, but in many cases, the ultrasonic USW vibrates along the X direction or the Y direction. In the present embodiment, as shown in Fig. 7, the upper surface SSt of the semiconductor substrate SS includes a region R4 that overlaps with the region R3 (see Fig. 5) but does not overlap with the region R1 (see Fig. 5) and the region R2 (see Fig. 5), and a region R5 that overlaps with the region R1 but does not overlap with the region R3. The groove TR1 is not formed in the region R4 of the upper surface SSt of the semiconductor substrate SS, but is formed in the region R5.

[0061] In other words, in this embodiment, groove TR1 is not arranged in region R4 which is likely to overlap with the outer edge of ball portion BWb (see Figure 4) of wire BW (see Figure 4), and groove TR1 is arranged in region R5 which is unlikely to overlap with the outer edge of ball portion BWb (see Figure 4) of wire BW (see Figure 4).

[0062] In other words, in this embodiment, the region R4 that is likely to overlap with the outer edge of the ball portion BWb (see FIG. 4) of the wire BW (see FIG. 4) is set as a prohibited region for placement of an element isolation trench. According to this embodiment, the groove TR1 is not arranged in the region R4 that is likely to overlap with the outer edge of the ball portion BWb (see FIG. 4) of the wire BW (see FIG. 4), so that the occurrence of cracks due to stress concentration can be suppressed regardless of the vibration direction of the ultrasonic USW (see FIG. 8) in the wire bonding process.

[0063] Moreover, according to this embodiment, the groove TR1 is arranged in a region R5 surrounded by a region R4 among the regions overlapping with the electrode pads PD on the upper surface SSt of the semiconductor substrate SS. Therefore, it is possible to form the semiconductor element Q1 in the region R1. In this way, the region overlapping with the electrode pads PD is an active region in which the semiconductor element Q1 can be formed, and therefore the planar size of the semiconductor chip CP (see FIG. 3) can be reduced.

[0064] <Variation 1> Next, a modification of the embodiment shown in Fig. 7 will be described. Fig. 9 is an enlarged plan view showing a first modification of the semiconductor substrate shown in Fig. 7. In Fig. 9, the outer edge of the electrode pad PD and the outer edge of the ball portion BWb of the wire BW are shown by dotted lines. Also, in Fig. 9, the boundaries of the regions R4, R5, and R6 are shown by two-dot chain lines. The upper surface SSt of the semiconductor substrate SS1 shown in FIG. 9 has a region R4, a region R5, and a region R6. This is similar to the upper surface SSt of the semiconductor substrate SS shown in FIG. 7. Also, as shown in FIG. 9, the planar shape of the region R4 is a hollow rectangle. In other words, in a plan view, the outer edge of the region R4 (the boundary between the region R4 and the region R6) is a rectangle, and the region R4 is disposed so as to continuously surround the region R5. This is also similar to the upper surface SSt of the semiconductor substrate SS shown in FIG. 7. Furthermore, in a plan view, the boundary between the region R4 and the region R5 has four sides S54 and four corners C54 where any two of the four sides S54 intersect. This is also similar to the upper surface SSt of the semiconductor substrate SS shown in FIG. 7.

[0065] The upper surface SSt of the semiconductor substrate SS1 shown in Fig. 9 differs from the upper surface SSt of the semiconductor substrate SS shown in Fig. 7 in the following respects. That is, in the upper surface SSt of the semiconductor substrate SS1, holes H1 having a smaller opening area than the groove TR1 are arranged between the groove TR1 and each of the four corners C54. In the example shown in Fig. 9, four holes H1 are formed in the region R5.

[0066] As described with reference to FIG. 8, even if a hole HA with a small opening area is formed at a position overlapping with the outer edge of the ball portion BWb of the wire BW, it is unlikely to cause cracks. Similarly, each of the multiple holes H1 shown in FIG. 9 according to this modification is unlikely to cause cracks regardless of the depth of the hole H1. The diameter of the hole H1 is the same dimension as the length of one side of the hole HA, and is, for example, about 0.5 μm to 1.0 μm. The planar shape of the hole H1 is not limited to a circle, but may be a rectangle, a straight line, an L-shape, or the like. However, the width of the hole in the case of a rectangle, a straight line, or an L-shape is the same dimension as the diameter of the hole H1 shown in FIG. The width of the hole here is the length in a direction intersecting the direction in which the hole extends in a plan view.

[0067] Considering the processing accuracy in the process of joining the wire BW to the electrode pad PD, the location where the wire BW is actually joined may have an error in at least one or both of the X and Y directions from the designed joining position. Therefore, among the boundaries between the regions R4 and R5, the periphery of the four corners C54 may overlap with the ball portion BWb depending on the degree of misalignment of the wire BW.

[0068] In this modification, holes H1 that are unlikely to cause cracks are disposed near each of the four corners C54 of the region R5, which has a rectangular planar shape. Each of the holes H1 is separated from the groove TR1, which is the DTI. This makes it possible to prevent the groove TR1 from being disposed near the four corners C54. In other words, each of the four holes H1 functions as a dummy groove for preventing the groove TR1 from being disposed at a position that overlaps with the outer edge of the ball portion BWb.

[0069] Except for the above-mentioned differences, the semiconductor substrate SS1 shown in Fig. 9 is similar to the semiconductor substrate SS described with reference to Fig. 7. Therefore, a duplicated description will be omitted.

[0070] <Variation 2> Next, another modified example of the embodiment shown in Fig. 7 will be described. Fig. 10 is an enlarged plan view showing a second modified example of the semiconductor substrate shown in Fig. 7. In Fig. 10, the outer edge of the electrode pad PD and the outer edge of the ball portion BWb of the wire BW are shown by dotted lines. Also, in Fig. 10, the boundaries of the regions R4, R5, and R6 are shown by two-dot chain lines. The upper surface SSt of the semiconductor substrate SS2 shown in FIG. 10 has a region R4, a region R5, and a region R6. This is similar to the upper surface SSt of the semiconductor substrate SS shown in FIG. 7. Also, as shown in FIG. 10, the planar shape of the region R4 is a hollow rectangle. In other words, in a plan view, the outer edge of the region R4 (the boundary between the region R4 and the region R6) is a rectangle, and the region R4 is disposed so as to continuously surround the region R5. This is also similar to the upper surface SSt of the semiconductor substrate SS shown in FIG. 7. Furthermore, in a plan view, the boundary between the region R4 and the region R5 has four sides S54 and four corners C54 where any two of the four sides S54 intersect. This is also similar to the upper surface SSt of the semiconductor substrate SS shown in FIG. 7.

[0071] The upper surface SSt of the semiconductor substrate SS2 shown in Fig. 9 differs from the upper surface SSt of the semiconductor substrate SS shown in Fig. 7 in the following respects: That is, in a plan view, each of the four corners C54 forms an arc shape.

[0072] As described above, when the processing accuracy in the process of joining the wire BW to the electrode pad PD is taken into consideration, the location where the wire BW is actually joined may have an error in at least one or both of the X and Y directions from the designed joining position. Therefore, the periphery of the four corners C54 of the boundary between the region R4 and the region R5 may overlap with the ball portion BWb depending on the degree of misalignment of the wire BW.

[0073] When each of the four corners C54 has an arc shape in plan view as in this modified example, the margin between the outer edge of the ball portion BWb and the four corners C54 can be made wider than in the example shown in Fig. 9. This makes it possible to avoid locating the groove TR1 at a position that overlaps with the outer edge of the ball portion BWb.

[0074] Except for the above-mentioned differences, the semiconductor substrate SS2 shown in Fig. 10 is similar to the semiconductor substrate SS described with reference to Fig. 7. Therefore, a duplicated description will be omitted.

[0075] <Modification 3> Next, a modified example of the DTI structure will be described below. In the example shown in FIG. 11, the structure of the trench TR1, which is a DTI, differs from that shown in FIG. 7 in the following respects. That is, an insulating material layer ITR covering the inner wall of the trench TR1 and an air layer AGL surrounded by the insulating material layer ITR are arranged in the trench TR1 shown in FIG. 11. The trench TR1 including the air layer AGL shown in FIG. 11 has the following advantages compared to the trench TR1 not including the air layer AGL. That is, the withstand voltage characteristics (voltage resistance characteristics) of the semiconductor integrated circuit are improved. For example, if the withstand voltage value of the trench TR1 shown in FIG. 7 is 75V (volts), the withstand voltage value when the trench TR1 shown in FIG. 11 is used is 100V (volts).

[0076] On the other hand, according to the research of the present inventors, when focusing on the frequency of occurrence of the above-mentioned cracks, it was found that the frequency of occurrence of cracks increases significantly when the groove TR1 including the air layer AGL is formed at a position overlapping with the ball portion BWb (see Figure 8) of the wire BW (see Figure 8).

[0077] However, as described above, when the groove TR1 shown in FIG. 11 is not disposed in the region R4, the frequency of crack occurrence can be suppressed.

[0078] In this manner, according to this modification, it is possible to improve the withstand voltage characteristics of the semiconductor integrated circuit while suppressing the occurrence of cracks.

[0079] <Variation 4> Next, a modified example of the groove formed in the semiconductor substrate will be described below. Fig. 12 is an enlarged cross-sectional view showing a modified example of the groove formed in the semiconductor substrate shown in Fig. 6.

[0080] The semiconductor element Q1 may be formed by combining a plurality of semiconductor regions. For example, in the example shown in FIG. 12, the semiconductor element Q1 has a semiconductor region QR1 and a semiconductor region QR2. There are various modifications of the configuration of the semiconductor region QR1 and the semiconductor region QR2, for example, one of the semiconductor region QR1 and the semiconductor region QR2 is an n-type semiconductor region and the other is a p-type semiconductor region. A groove TR2 is formed between the semiconductor region QR1 and the semiconductor region QR2. In the modification shown in FIG. 12, the plurality of grooves TR formed on the upper surface SSt of the semiconductor substrate SS includes the groove TR2 in addition to the groove TR1.

[0081] The trench TR2 is one of a plurality of trenches TR formed in the upper surface SSt of the semiconductor substrate SS. The trench TR2 is a so-called STI (Shallow Trench Isolation) trench. The trench TR2 is disposed across two different semiconductor regions, and is an insulating region for preventing leakage current between adjacent semiconductor regions.

[0082] When the top surface SSt of the semiconductor substrate SS is taken as the reference plane, the groove TR2 is shallower than the groove TR1. In the example shown in Fig. 12, the depth of the groove TR2 (the distance from the top surface SSt to the bottom surface of the groove TR2) is about 30 nm. In the case of a shallow groove TR2 like this, it is unlikely to cause the above-mentioned cracks. Therefore, even if the groove TR2 is disposed in the region R4 shown in Fig. 7 and the outer edge of the ball portion BWb of the wire BW shown in Fig. 4 overlaps with the groove TR2 shown in Fig. 12, the frequency of crack occurrence will not increase.

[0083] <Semiconductor package manufacturing method> Next, a method for manufacturing the semiconductor package PKG1 shown in Fig. 1 will be described. The semiconductor package PKG1 of this embodiment is manufactured according to the assembly flow shown in Fig. 13. Fig. 13 is an explanatory diagram showing the assembly flow of the semiconductor package of this embodiment. In the example shown in Fig. 13, the method for manufacturing the semiconductor package of this embodiment includes a semiconductor chip preparation step, a base material preparation step, a semiconductor chip mounting step, a wire bonding step, a sealing step, and a singulation step. In the following description, when describing each component constituting the semiconductor package, each of Figs. 1 to 12 will be cited as necessary.

[0084] <Base material preparation process> In the substrate preparation step shown in Fig. 13, a lead frame (substrate) LF shown in Fig. 14 is prepared. Fig. 14 is an enlarged plan view showing a state in which a semiconductor chip is mounted on a die pad of a lead frame in the semiconductor chip mounting step shown in Fig. 13. Note that, as a modification of the present embodiment, in the case of a manufacturing method of a semiconductor package in which a semiconductor chip CP is mounted on a wiring board (not shown), a wiring board is prepared in this step instead of the lead frame LF (see Fig. 14).

[0085] As shown in Fig. 14, the leadframe LF prepared in this process includes a plurality of device forming portions LFd connected to a frame portion (frame portion) LFf. Each of the plurality of device forming portions LFd corresponds to one semiconductor package PKG1 shown in Fig. 1. The leadframe LF is a so-called multi-piece substrate in which a plurality of device forming portions LFd are arranged.

[0086] The lead frame LF is made of a metal material mainly composed of copper (Cu), for example. Each of the device formation parts LFd is connected to a frame part LFf. The frame part LFf is a support part that supports each member formed in the device formation part LFd until the lead separation process shown in FIG.

[0087] 3 are formed in the device formation portion LFd. The die pad DP is connected to the frame portion LFf via a suspension lead and is supported by the frame portion LFf. Each of the leads LD is connected to the frame portion LFf via a tie bar TB and is supported by the frame portion LFf.

[0088] <Semiconductor chip preparation process> In the semiconductor chip preparation step shown in Fig. 13, a semiconductor chip CP shown in Fig. 14 is prepared. The semiconductor chip CP prepared in this step is a semiconductor chip before the wires BW (see Fig. 3) are bonded, as shown in Fig. 14. The detailed structure of the semiconductor chip CP has already been described using Figs. 2 to 12, so a duplicated description will be omitted.

[0089] <Semiconductor chip mounting process> Next, in the semiconductor chip mounting step shown in FIG. 13, the semiconductor chip CP is mounted on the die pad DP as shown in FIG.

[0090] In this process, as shown in Fig. 2, a semiconductor chip CP is mounted on the upper surface DPt of the die pad DP via a die bond material DB. In this process, the die bond material DB is applied onto the upper surface DPt of the die pad DP, and then the semiconductor chip CP is placed on the die bond material DB. Then, the die bond material DB is hardened to fix the semiconductor chip CP and the die pad DP.

[0091] In this process, the semiconductor chip CP is mounted on the die pad DP with the bottom surface CPb of the semiconductor chip CP facing the top surface DPt of the die pad DP, as shown in Fig. 2. This makes it possible to easily bond wires BW (see Fig. 2) to each of the multiple electrode pads PD arranged on the top surface CPt of the semiconductor chip in the next wire bonding process.

[0092] <Wire bonding process> Next, in the wire bonding process shown in Fig. 13, wires are bonded to the electrode pads PD of the semiconductor chip CP as shown in Fig. 3. In the present embodiment, in the wire bonding process, the electrode pads PD of the semiconductor chip CP and the leads LD are electrically connected via wires BW. Fig. 15 and Fig. 16 are enlarged cross-sectional views showing the details of the wire bonding process.

[0093] In the following, a method of bonding a wire BW to an electrode pad PD by a ball bonding method will be described with reference to Fig. 15 and Fig. 16. When a ball portion BWb of a wire BW is bonded to an electrode pad PD by a ball bonding method as shown in Fig. 4, the bonding strength can be improved by applying high-frequency vibration such as ultrasonic vibration to the ball portion BWb. "Ultrasound" is an elastic wave having a frequency higher than the audible range of humans. In this application, a high frequency of 20 kHz or more is called "ultrasound".

[0094] In addition, in the ball bonding process, in addition to the application of ultrasonic waves, a scrubbing operation may be performed to remove the oxide film on the bonding surface between the electrode pad PD and the ball part BWb. The vibration direction of the ultrasonic USW described using Figure 8 means the vibration direction of the ultrasonic USW applied in the wire bonding process, and is distinguished from the vibration direction of the scrubbing operation.

[0095] In the wire bonding process, first, as shown in FIG. 15, the tip portion of the wire BW held by the capillary CAP is heated and melted to form a ball portion BWb.

[0096] Next, as shown in Fig. 16, the capillary CAP holding the wire BW is moved toward the electrode pad PD, and the ball part BWb is pressed against the upper surface PDt of the electrode pad PD. At this time, ultrasonic waves USW are applied via the wire BW. In the example shown in Fig. 16, the ultrasonic waves USW vibrate along the X direction. Note that, although the vibration direction of the ultrasonic waves USW is along the X direction in the example shown in Fig. 16, as a modified example, there is a case where the vibration direction of the ultrasonic waves USW is along the Y direction shown in Fig. 7.

[0097] In this process, as shown in Fig. 4, the wire BW is joined to a position where the outer edge of the ball portion BWb overlaps with the region R3 in a plan view. As shown in Fig. 6 and Fig. 16, the region R4 overlaps with the region R3 on the upper surface SSt of the semiconductor substrate SS. More specifically, as can be seen by comparing Fig. 4 with Fig. 5, the entire region R4 overlaps with the region R3. Therefore, in this process, the wire BW is joined to a position where the outer edge of the ball portion BWb overlaps with the region R4 in a plan view.

[0098] As already described, the groove TR1 that may cause cracks is not formed in the region R4. The groove TR1 is formed in the region R5, but the groove TR1 formed in the region R5 is unlikely to cause cracks. As a result, according to the manufacturing method of the semiconductor package PKG1 of the present embodiment, even if the groove TR1 that is the DTI is formed at a position overlapping the electrode pad PD, the frequency of cracks can be reduced.

[0099] Next, the wire BW is released from the state in which the capillary CAP is held as shown in Fig. 16, and the capillary CAP is moved upward. At this time, since the ball portion BWb is bonded to the electrode pad PD, the wire BW in which the ball portion BWb is bonded to the electrode pad PD is obtained.

[0100] Next, the capillary CAP is moved to the wire bonding area of ​​the lead LD shown in Fig. 3, and then the wire BW is bonded to the lead LD. After that, when the excess wire is cut off, the wire BW as shown in Figs. 2 and 3 is obtained.

[0101] As a modification of this embodiment, a stud bump may be bonded to the electrode pad PD. In this case, after the process described with reference to Fig. 16, the wire BW is cut at the top of the ball portion BWb. This leaves the ball portion BWb on the electrode pad PD, and the ball portion BWb can be used as a stud bump.

[0102] <Sealing process> Next, in the sealing process shown in Figure 13, the semiconductor chip CP, the die pad DP, the inner lead portions ILD of the multiple leads LD, and the multiple wires BW shown in Figure 2 are sealed with insulating resin to form the sealing body MR shown in Figures 1 and 2.

[0103] In this process, for example, a molding die including an upper die (first die) and a lower die (second die), not shown, is used to form the sealing body MR by a so-called transfer molding method. The lead frame LF is arranged so that the die pad DP and the multiple leads LD of the device forming part LFd shown in FIG. 14 are located within the cavity of the molding die. Then, the lead frame LF is sandwiched between the upper and lower dies. In this state, when a softened (plasticized) thermosetting resin (insulating resin) is pressed into the cavity of the molding die, the insulating resin is molded to follow the shape of the cavity.

[0104] At this time, a portion (outer lead portion OLD) of each of the leads LD is in close contact with the molding die, so that after this step, the outer lead portion OLD of each of the leads LD is exposed from the sealing body MR, as shown in FIG.

[0105] After the sealing body MR is molded, it is heated until a part of the thermosetting resin contained in the sealing body MR is hardened (called temporary hardening). When this temporary hardening makes it possible to remove the lead frame LF from the molding die, the lead frame LF is removed from the molding die. Then, it is transported to a heating furnace and further heated (cure bake). This hardens the remaining part of the thermosetting resin, and the sealing body MR is obtained.

[0106] <Singulation process> Next, in the singulation process shown in Fig. 13, the structure formed in the device formation part LFd is cut and singulated. In this process, the tip portions of the outer lead parts OLD of the tie bars TB and the multiple leads LD shown in Fig. 14 are cut. Also, in this process, the shape of the outer lead parts OLD is formed into the shape shown in Fig. 2. As a result, the semiconductor package PKG1 shown in Figs. 1 to 3 is obtained.

[0107] In the manufacturing method of the semiconductor package described with reference to FIGS. 13 to 16, any one of the modified examples 1 to 4 already described or any combination of two or more modified examples can be applied.

[0108] <Modification of manufacturing method> Next, a modified example of the semiconductor device manufacturing method described with reference to Figures 13 to 16 will be described. The modified example described below is similar to the semiconductor package manufacturing method described with reference to Figures 13 to 16, except that the ultrasonic vibration direction is predetermined and that the exposed portion of the electrode pad is divided into different regions. Therefore, the differences from the above manufacturing method will be described below.

[0109] Fig. 17 is an enlarged plan view showing a modified example of Fig. 4. Fig. 18 is an enlarged plan view showing a portion of a semiconductor substrate included in the semiconductor chip shown in Fig. 17 that overlaps with the enlarged plan view shown in Fig. 17. In Fig. 17, the boundaries between regions R1, R2, and R3 are shown by two-dot chain lines. In Fig. 18, the boundaries between regions R4, R5, and R6 are shown by two-dot chain lines. Fig. 18 is a plan view of the semiconductor substrate, and the contours of the electrode pads PD are shown by dotted lines.

[0110] The semiconductor chip CP1 of this modified example shown in FIG. 17 differs from the semiconductor chip CP shown in FIG. 4 in the following points.

[0111] 17, the exposed portion PDE of the electrode pad PD includes, in a plan view, a region R1 including the center of the opening PVk, a region R2 located around the region R1, and a plurality of regions R3 (two in FIG. 17) located on both sides of the region R1 and between the regions R1 and R2. The planar shape of the exposed portion PDE of the electrode pad PD is a rectangle, similar to the semiconductor chip CP shown in FIG.

[0112] Each of the multiple regions R3 is provided in a strip shape along one of the sides (side Pks2 and side Pks4) of the exposed portion PDE of the electrode pad PD that extends in the Y direction in plan view.

[0113] Also, as shown in FIG. 18, the upper surface SSt of the semiconductor substrate SS3 includes a plurality of regions R4 that overlap with any of the plurality of regions R3 but do not overlap with the regions R1 and R2, and a region R5 that overlaps with any of the regions R1 and R2 but do not overlap with the plurality of regions R3.

[0114] The trench TR1 formed in the upper surface SSt of the semiconductor substrate SS3 includes a trench TRY extending along the Y direction, or a trench TRX extending along the X direction intersecting the Y direction. In the example shown in Fig. 18, the trench TR1 includes both the trench TRY and the trench TRX. The trench TRY or the trench TRX is formed in the region R5. In the example shown in Fig. 17, the trench TRX is formed in the region R5.

[0115] In each of the multiple regions R4, no groove TRY is formed, and no end of the groove TRX is formed. Here, the end of the groove TRX is a portion where the extension direction of the groove TRX changes. In the example shown in FIG. 18, the groove TR1 has an endless shape. However, the grooves TRX and the grooves TRY constituting the groove TR1 intersect with each other. Each of the four intersections where the groove TRX and the groove TRY intersect is an end of the groove TRX and an end of the groove TRY. In the wire bonding process in the manufacturing method for the semiconductor package of this modified example, as in the example described using FIG. 16, ultrasonic waves USW that vibrate along the X direction are applied with the ball portion BWb at the tip of the wire BW in contact with the electrode pad PD.

[0116] As already explained with reference to Fig. 8, the groove TRB extends along the vibration direction of the ultrasonic wave USW, and the end of the groove TRB does not overlap with the outer edge of the ball portion BWb. In this case, although a part of the groove TRB overlaps with the outer edge of the ball portion BWb, the groove TRB is unlikely to cause cracks.

[0117] From this knowledge, if the vibration direction of the ultrasonic waves USW can be specified, the area of ​​the region R4 (see FIG. 18) in which the DTI placement is prohibited can be reduced. In other words, the area in which the DTI can be placed can be expanded. As a result, in the case of the semiconductor substrate SS3, the area ratio of the active region to the upper surface SSt can be improved compared to the semiconductor substrate SS shown in FIG.

[0118] In this modified example, as shown in Fig. 18, the grooves TR1 are arranged at a higher density than in the example shown in Fig. 7. However, since the above-mentioned "conditions that increase the frequency of crack occurrence" are avoided, the occurrence of cracks can be suppressed.

[0119] In the present modified example, each of the multiple grooves TR1 includes a groove TRX and a groove TRY, but the length of the groove TRX is longer than the length of the groove TRY.

[0120] 17 and 18, the case where ultrasonic waves USW vibrating in the X direction are applied has been described, similarly to the example shown in Fig. 16. However, as a modified example, ultrasonic waves USW vibrating in the Y direction may be applied.

[0121] Although not shown, in the case of a modified example in which the vibration direction of ultrasonic waves USW is along the Y direction, each of the regions R1, R2, and R3 shown in Fig. 17 is arranged in a strip shape extending in the X direction. Similarly, each of the regions R4, R5, and R6 shown in Fig. 18 is arranged in a strip shape extending in the X direction. Furthermore, in each of the multiple regions R4, no groove TRX is formed, and no end of the groove TRY is formed.

[0122] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0123] AGL Air Layer BW Wire (conductive material) BWb Ball part C54 Corner CAP Capillary CP, CP1 Semiconductor chip CPb bottom surface CPs1, CPs2, CPs3, CPs4, Pks1, Pks2, Pks3, Pks4, S54 side CPt,PDt Top surface (principal surface) DB Die bond material (adhesive) DP die pad (chip mounting area) DPt top surface (front surface, main surface, chip mounting surface) H1,HA hole HL Hanging Lead IL1 Insulation layer ILD Inner lead part ITR Insulation Layer LD lead (terminal, external terminal) LF lead frame (substrate) LFd Device Formation Department LFf Frame part MR sealing body (resin body) MRb bottom surface (back surface, mounted surface) MRs side MRt top surface OLD Outer lead part PD electrode pad (electrode, pad, bonding pad) Exposed PDE PDP peripheral area PKG1 Semiconductor package PV insulation layer (protective film, protective insulating film) PVk opening Q1 Semiconductor element QR1, QR2 Semiconductor area R1,R2,R3,R4,R5,R6 area SS, SS1, SS2, SS3 Semiconductor substrate SSt top surface TB Tie Bar TR,TR1,TR2,TRA,TRB,TRC,TRX,TRY Groove USW Ultrasonic

Claims

1. a semiconductor substrate having a first surface; a first insulating layer formed on the first surface of the semiconductor substrate; An electrode pad formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover a peripheral portion of the electrode pad; A plurality of grooves formed in the semiconductor substrate; Including, the electrode pad has an exposed portion exposed in an opening of the second insulating layer, and a peripheral portion located around the exposed portion and covered with the second insulating layer; the exposed portion of the electrode pad includes, in a plan view, a first region including a center of the opening, a second region located around the first region, and a third region located around the first region and between the first region and the second region; The exposed portion of the electrode pad has a planar shape that is rectangular, the third region is provided in an annular shape along each side of the exposed portion of the electrode pad in a plan view so that the planar shape of the third region is a hollow rectangle; the plurality of grooves include a first groove separating a plurality of semiconductor elements formed in the semiconductor substrate from each other; The semiconductor substrate is a fourth region that overlaps with the third region and does not overlap with the first region and the second region; a fifth region that overlaps with the first region and does not overlap with the third region; Including, The first trench is not formed in the fourth region of the semiconductor substrate, and is formed in the fifth region of the semiconductor substrate.

2. In claim 1, When the first surface of the semiconductor substrate is taken as a reference surface, the first trench extends to a position deeper than the semiconductor element.

3. In claim 2, In a plan view, the boundary between the fourth region and the fifth region has four sides and four corners where any two of the four sides intersect, a hole having an opening area smaller than that of the first groove is disposed between the first groove and each of the four corners on the first surface of the semiconductor substrate.

4. In claim 2, In a plan view, the boundary between the fourth region and the fifth region has four sides and four corners where any two of the four sides intersect, In a plan view, each of the four corners forms an arc shape.

5. In claim 2, The semiconductor device, wherein an insulating layer covering an inner wall of the first groove and an air space surrounded by the insulating layer are disposed within the first groove.

6. In claim 2, A semiconductor device, wherein the plurality of grooves include second grooves that are shallower than the first grooves when the first surface of the semiconductor substrate is taken as a reference surface.

7. In claim 2, a wire having a ball portion is bonded to the exposed portion of the electrode pad; In a plan view, an outer edge of the ball portion of the wire overlaps with the third region and the fourth region.

8. (a) preparing a semiconductor chip having electrode pads; (b) bonding wires to the electrode pads of the semiconductor chip; Including, The semiconductor chip comprises: a semiconductor substrate having a first surface; a first insulating layer formed on the first surface of the semiconductor substrate; The electrode pad formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover a peripheral portion of the electrode pad; A plurality of grooves formed in the semiconductor substrate; Including, the electrode pad has an exposed portion exposed in an opening of the second insulating layer, and a peripheral portion located around the exposed portion and covered with the second insulating layer; the exposed portion of the electrode pad includes, in a plan view, a first region including a center of the opening, a second region located around the first region, and a third region located around the first region and between the first region and the second region; The exposed portion of the electrode pad has a planar shape that is rectangular, the third region is provided in an annular shape along each side of the exposed portion of the electrode pad in a plan view so that the planar shape of the third region is a hollow rectangle; the plurality of grooves include a first groove separating a plurality of semiconductor elements formed in the semiconductor substrate from each other; The semiconductor substrate is a fourth region that overlaps with the third region and does not overlap with the first region and the second region; a fifth region that overlaps with the first region and does not overlap with the third region; Including, the first trench is not formed in the fourth region of the semiconductor substrate, and is formed in the fifth region of the semiconductor substrate; In the step (b), ultrasonic waves are applied while a ball portion at the tip of the wire is in contact with the electrode pad.

9. In claim 8, A method for manufacturing a semiconductor device, wherein in the step (b), the wire is joined at a position where an outer edge of the ball portion overlaps with the third region and the fourth region in a plan view.

10. In claim 8, a first surface of the semiconductor substrate being a reference surface, the first trench extending to a position deeper than the semiconductor element;

11. In claim 10, In a plan view, the boundary between the fourth region and the fifth region has four sides and four corners where any two of the four sides intersect, A method for manufacturing a semiconductor device, wherein holes having an opening area smaller than that of the first grooves are arranged between the first grooves and each of the four corners on the first surface of the semiconductor substrate.

12. In claim 10, In a plan view, the boundary between the fourth region and the fifth region has four sides and four corners where any two of the four sides intersect, A method for manufacturing a semiconductor device, wherein each of the four corners has an arc shape in a plan view.

13. In claim 10, A method for manufacturing a semiconductor device, wherein an insulating layer covering an inner wall of the first groove and an air space surrounded by the insulating layer are disposed within the first groove.

14. In claim 10, A method for manufacturing a semiconductor device, wherein the plurality of grooves include second grooves that are shallower than the first grooves when the first surface of the semiconductor substrate is taken as a reference surface.

15. (a) preparing a semiconductor chip having electrode pads; (b) bonding wires to the electrode pads of the semiconductor chip; Including, The semiconductor chip comprises: a semiconductor substrate having a first surface; a first insulating layer formed on the first surface of the semiconductor substrate; The electrode pad formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover a peripheral portion of the electrode pad; A plurality of grooves formed in the semiconductor substrate; Including, the electrode pad has an exposed portion exposed in an opening of the second insulating layer, and a peripheral portion located around the exposed portion and covered with the second insulating layer; the exposed portion of the electrode pad includes, in a plan view, a first region including a center of the opening, a second region located around the first region, and a plurality of third regions located on both sides of the first region and between the first region and the second region; The exposed portion of the electrode pad has a planar shape that is rectangular, Each of the third regions is provided in a strip shape along one of the sides of the exposed portion of the electrode pad that extends in a first direction in a plan view, the plurality of grooves include a first groove separating a plurality of semiconductor elements formed in the semiconductor substrate from each other; The semiconductor substrate is a plurality of fourth regions that overlap any one of the plurality of third regions and do not overlap the first region and the second region; a fifth region that overlaps with the first region and does not overlap with the third regions; Including, The first groove includes a first direction groove extending along the first direction or a second direction groove extending along a second direction intersecting the first direction, The first direction groove or the second direction groove is formed in the fifth region, In each of the plurality of fourth regions, the first direction groove is not formed, and an end portion of the second direction groove is not formed, In the step (b), ultrasonic waves that vibrate along the second direction are applied to the ball portion at the tip of the wire while the ball portion is in contact with the electrode pad.

16. In claim 15, A method for manufacturing a semiconductor device, wherein in the step (b), the wire is joined at a position where an outer edge of the ball portion overlaps with the third region and the fourth region in a plan view.

17. In claim 16, a first surface of the semiconductor substrate being a reference surface, the first trench extending to a position deeper than the semiconductor element;

18. In claim 16, A method for manufacturing a semiconductor device, wherein an insulating layer covering an inner wall of the first groove and an air space surrounded by the insulating layer are disposed within the first groove.

19. In claim 16, A method for manufacturing a semiconductor device, wherein the plurality of grooves include second grooves that are shallower than the first grooves when the first surface of the semiconductor substrate is taken as a reference surface.

Images