Power semiconductor module and power conversion device

Abstract

To provide a power semiconductor module and a power conversion device, which, while reducing parasitic inductance of a main current path, are excellent in heat dissipation and achieve stable operation during high-speed switching.SOLUTION: A power semiconductor module 100 includes: a conductor layer pattern 12a, a conductor layer pattern 11 and a conductor layer pattern 13a which are disposed on one surface of an insulation substrate 10 and electrically insulated from one another; power semiconductor elements 31, 32 which are electrically and thermally connected onto the conductor layer patten 12a; and lead frames 35, 36 electrically connecting between the power semiconductor elements 31, 32 and the conductor layer pattern 13a across the conductor layer pattern 11. The conductor layer patten 11 is disposed in a region between the conductor layer patten 12a and the conductor layer pattern 13a, and a direction of a transient current flowing through the conductor layer pattern 11 is opposite a direction of a current flowing through the conductor layer pattern 13a.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a power semiconductor module and a power conversion device. [Background technology]

[0002] Power semiconductor modules, which use multiple switching elements such as power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) and multiple semiconductor elements such as freewheel diodes mounted in a single module, are used for power control and motor control in industrial equipment, electric railway cars, automobiles, home appliances, and other devices.

[0003] In recent years, GaN (gallium nitride) and SiC (silicon carbide) have been used as materials for power semiconductor chips, and are beginning to take advantage of their advantages, such as faster switching speeds and higher operating temperatures, compared to semiconductor elements that use Si (silicon).Currently, because GaN and SiC elements are small in size, in order to configure a power semiconductor module that satisfies a certain current capacity, it is necessary to connect multiple power semiconductor chips in parallel and mount them on an insulating substrate within the module.

[0004] In addition, in applications where power loss in inverters such as automotive inverters affects the driving range of electric vehicles and fuel cell vehicles, it is necessary to minimize power loss generated in power semiconductor modules. For this reason, it is important for power semiconductor modules to minimize both resistive loss during conduction and transient switching loss during switching. To reduce switching loss, switching must be performed in a short time, i.e., high-speed switching, but two characteristics must be taken into consideration. The first is to perform switching operations while reducing the effects of electromagnetic fields generated by currents that flow transiently inside the power semiconductor module.

[0005] The other is to design the main current path inductance to be small in advance, since the main current increases and decreases significantly in a short time during high-speed switching. If the main current path inductance is large, unnecessary transient voltages will occur in response to transient current changes, and the voltage applied to the power semiconductor chip may temporarily exceed its withstand voltage. As a result, it becomes necessary to make the time required for switching longer and more gradual, which results in the side effect of increased switching losses.

[0006] Furthermore, when multiple power semiconductor chips are connected in parallel to configure a power semiconductor module, it is necessary to divide the current flowing through the parallel-connected power semiconductor chips evenly. If the current is uneven, heat will be concentrated in only certain power semiconductor chips, which may shorten the life of the power semiconductor module and reduce its reliability.

[0007] Patent Document 1 describes a technique for reducing the effect of an electromagnetic field generated by a transiently flowing current and a technique for reducing parasitic inductance. The device described in Patent Document 1 has a problem in that if the device is arranged so that the electromagnetic field of the main current flowing through the external connection terminals connected to the main electrode pair of the semiconductor element has a relatively large effect on the current flowing through the control signal path from the control terminal to the control electrode of the semiconductor element, the control voltage may be affected and the operating performance of the semiconductor element may be reduced. As a countermeasure technology, the device described in Patent Document 1 comprises a semiconductor module including: a first semiconductor element having a first conductor layer, a second conductor layer corresponding to the first conductor layer, a first control electrode and a first positive electrode electrically connected to the first conductor layer, and a first negative electrode electrically connected to the second conductor layer; a positive terminal provided on an edge of the first conductor layer in a first direction in a planar view; a negative terminal provided on an edge of the second conductor layer in the first direction in a planar view; a control wiring electrically connected to the first control electrode and drawn out to the outside in a second direction opposite to the first direction of the first conductor layer and the second conductor layer in a planar view; and a control terminal electrically connected to the control wiring, located outside the first conductor layer and the second conductor layer in a planar view, and having an end juxtaposed with the positive terminal and the negative terminal.

[0008] Patent Document 2 describes a half-bridge power semiconductor module capable of significantly reducing the parasitic inductance occurring in the internal main current path and a manufacturing method thereof. The half-bridge power semiconductor described in Patent Document 2 is a power module in which two power semiconductor chips are connected in series, and a half-bridge circuit with the connection midpoint serving as an output terminal is housed in one package. By adopting a configuration of "close anti-parallel current" in which current flows in opposite directions in close reciprocating wiring, an electromagnetic method for reducing the parasitic inductance of wiring is applied to reduce the parasitic inductance Ls inside the power module. This clarifies the problem that the parasitic inductance cannot be reduced as desired because a section in which the close anti-parallel current of the main current is incomplete is inevitably generated. As a countermeasure technology, the half-bridge power semiconductor described in Patent Document 2 includes an insulating substrate, a high-side power semiconductor device, a low-side power semiconductor device, a bridge terminal, a high-side terminal, and a low-side terminal, and the insulating substrate includes an insulating plate, a front wiring conductor, and a back bridge wiring conductor arranged on the front and back surfaces of the insulating plate. The back electrode of the high-side power semiconductor device is connected to the first surface wiring conductor, and the back electrode of the low-side power semiconductor device is connected to the second surface wiring conductor. The bridge terminal is connected to the back bridge wiring conductor between the power semiconductor device. The high-side terminal is ohmically connected to the first surface wiring conductor at a position between the high-side power semiconductor device and the bridge terminal, and the low-side terminal is ohmically connected to the front electrode of the low-side power semiconductor device at a position between the low-side power semiconductor device and the bridge terminal. The front electrode of the high-side power semiconductor device and the second surface wiring conductor are connected to the back bridge wiring conductor. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Patent Publication No. 2021-97145 [Patent Document 2] JP 2015-185630 A Summary of the Invention [Problem to be solved by the invention]

[0010] In the power semiconductor modules described in Patent Documents 1 and 2, a wiring structure is shown in which the control wiring is routed long and avoids areas of strong interference in order to reduce electromagnetic interference with the control wiring, but no measures for reducing the inductance of the control wiring itself are made clear, which is an issue. In addition, in the power semiconductor module equipped with the half-bridge circuit described in Patent Document 2, although a measure to reduce inductance by close anti-parallel current is explicitly stated, no measure to reduce the inductance occurring in the path where the current changes during switching is presented, which is an issue. Furthermore, in the power semiconductor module equipped with the half-bridge circuit described in Patent Document 2, in order to reduce inductance, a high potential is generated on the back conductor of the insulating substrate on which the power semiconductor chip is mounted, so another insulating layer is introduced for connection to the heat sink. In this regard, a problem that deteriorates the thermal conductivity of the heat dissipation path has become clear, but no measures to improve the problem are mentioned.

[0011] The present invention has been made in consideration of the above circumstances, and has an object to provide a power semiconductor module and a power conversion device that reduce the parasitic inductance of the main current path, have excellent heat dissipation properties, and achieve stable operation during high-speed switching. [Means for solving the problem]

[0012] In order to solve the above problems, the power semiconductor module of the present invention is a power semiconductor module including a first switch and a second switch configured using power semiconductor elements, and one or more half-bridge circuits formed by connecting the first switch and the second switch in series, wherein the half-bridge circuit includes an insulating substrate, a first conductor layer pattern, a second conductor layer pattern, and a third conductor layer pattern arranged on one side of the insulating substrate and electrically insulated from each other, the power semiconductor element electrically and thermally connected on the first conductor layer pattern, and a lead frame electrically connecting the power semiconductor element and the third conductor layer pattern across the second conductor layer pattern, the second conductor layer pattern being arranged in a region between the first conductor layer pattern and the third conductor layer pattern, and a direction of a transient current flowing through the second conductor layer pattern is opposite to a direction of a current flowing through the third conductor layer pattern. Effect of the Invention

[0013] According to the present invention, it is possible to provide a power semiconductor module and a power conversion device that reduce the parasitic inductance of the main current path, have excellent heat dissipation properties, and achieve stable operation during high-speed switching. [Brief description of the drawings]

[0014] [Figure 1] 1 is a plan view showing a schematic configuration of a power semiconductor module according to a first embodiment of the present invention. [Diagram 2] 2 is a cross-sectional view taken along the line AA' in FIG. [Diagram 3] FIG. 2 is a perspective view of a component placed on the insulating layer shown in FIG. [Figure 4] FIG. 2 is a plan view of a power semiconductor module of a comparative example viewed from above. [Diagram 5] 5 is a diagram for explaining the direction of current flow during switching in the structure of region B1' shown in FIG. 4. FIG. [Figure 6] FIG. 6 is a diagram showing an equivalent circuit obtained by simplifying the wiring structure of the <Comparative Example> shown in FIG. 5. [Figure 7] 2 is a diagram for explaining the direction of current flow during switching in the structure of region B1 shown in FIG. 1. FIG. [Figure 8] FIG. 8 is a diagram showing an electrical equivalent circuit of the circuit shown in FIG. [Figure 9A] 1 is a schematic diagram of a power semiconductor module according to a first embodiment. [Figure 9B] FIG. 6 is a schematic diagram of the power semiconductor module of the <Comparative Example> of FIG. 5. [Figure 9C] 1 is a schematic diagram of a main part of a semiconductor module of Patent Document 2. FIG. [Figure 10] FIG. 4 is a plan view showing a schematic configuration of a power semiconductor module according to a second embodiment of the present invention. [Figure 11] 11 is a cross-sectional view taken along the line AA' of FIG. 10. [Figure 12] 11 is a perspective view of the lead frame of FIG. 10 as viewed from above. FIG. [Figure 13] 11 is a perspective view of the lead frame of FIG. 10 as seen from below. [Figure 14A] 2 is a diagram for explaining the direction of current flow during switching in the structure of region B1 shown in FIG. 1 that does not have a notch. FIG. [Figure 14B] 11 is a diagram for explaining the direction of current flow during switching when the notch width is Notch-W1, in the structure of region C1 shown in FIG. 10. FIG. [Figure 14C] 11 is a diagram for explaining the direction of current flow during switching when the notch width is Notch-W2, in the structure of region C1 shown in FIG. [Figure 15] FIG. 15 is a diagram showing the results of an analysis of the magnitude of inductance in each of the current paths in FIGS. 14A to 14C. [Figure 16A] FIG. 11 is a waveform diagram showing an analysis circuit corresponding to the power semiconductor module of FIG. 10 when an inductive load is connected to the intermediate voltage main terminal and the power semiconductor element of the low-voltage side arm is switched. [Figure 16B]FIG. 16B is a characteristic diagram in which losses occurring in each power semiconductor element are calculated and plotted for the transient waveform shown in FIG. 16A. [Figure 16C] 11 is a waveform diagram showing switching transient waveforms when the width (Notch-W) of the notch in the lead frame of the power semiconductor module of FIG. 10 is optimized and the inductance of each element path is set equal. FIG. [Figure 16D] FIG. 16D is a characteristic diagram in which losses occurring in each power semiconductor element are calculated and plotted for the transient waveform shown in FIG. 16C. [Figure 17A] 2 is a diagram for explaining the direction of current flow during switching in the structure of region B1 shown in FIG. 1 that does not have a notch. FIG. [Figure 17B] 11 is a diagram for explaining the direction of current flow during switching when the notch width is Notch-Wa, in the structure of region C1 shown in FIG. [Figure 17C] 13 is a diagram for explaining the direction of current flow during switching when the notch width is Notch-Wb. FIG. [Figure 17D] It is a diagram for explaining the direction of current flow during switching when the notch width is Notch-Wc." [Figure 18] FIG. 17B is a diagram showing a comparison of the inductance values ​​of LMOS1 and LMOS2 in the current paths of each of FIGS. 17A to 17D. [Figure 19] FIG. 11 is a block diagram showing a circuit configuration of a power conversion device according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. (First embodiment) A power semiconductor module according to a first embodiment of the present invention will be described. This embodiment is an example of a power semiconductor module that is configured by connecting multiple power semiconductor chips in parallel to configure a half-bridge circuit arranged on the same substrate.

[0016] [Schematic configuration] Fig. 1 is a diagram showing a schematic configuration of a power semiconductor module 100 of a first embodiment, and is a plan view of the power semiconductor module 100 as viewed from above. Fig. 2 is a cross-sectional view taken along the line A-A' in Fig. 1. In each drawing, the same components or components having similar functions are denoted by the same reference numerals, and detailed descriptions of overlapping parts are omitted. It should also be noted that in the plan view of Figure 1, the layout of components on lower layers, which are not visible due to the presence of components on upper layers, is shown, for convenience, as if the components on the upper layers were seen through.

[0017] The areas B1 and B2 enclosed by dashed lines in FIG. 1 will be described later with reference to FIG. Moreover, a perspective view of the structure of the power semiconductor module 100 in FIG. 1 will be described later with reference to FIG.

[0018] 1, power semiconductor module 100 has a half-bridge circuit, i.e., a 2-in-1 circuit, configured on a single insulating substrate, and includes main terminals consisting of a high-voltage side main terminal 1 (high potential side main terminal), an intermediate voltage terminal 2 (intermediate potential terminal), and a low-voltage side main terminal 3 (low potential side main terminal). In addition, for operational control of power semiconductor module 100, it includes auxiliary terminals (control terminals) 4-6 of a high-voltage side arm and auxiliary terminals (control terminals) 7-9 of a low-voltage side arm.

[0019] Moreover, the high-voltage side potential refers to the voltage value applied to the high-voltage side main terminal 1, and the low-voltage side potential refers to the voltage value applied to the low-voltage side main terminal 3. The intermediate voltage refers to a voltage value intermediate between the voltages applied to the high-voltage side main terminal 1 and the low-voltage side main terminal 3, and this potential fluctuates due to switching operations.

[0020] [Main terminal connection] The connection of the main terminals will be explained using FIG. As shown in Fig. 1, high-voltage side main terminal 1, which applies a high-voltage side potential, is electrically connected to conductor layer pattern 11a (Fig. 2) (second conductor layer pattern) disposed on insulating substrate 10. Intermediate voltage terminal 2, which applies an intermediate voltage and whose potential fluctuates by switching, is electrically connected to conductor layer pattern 12b (first conductor layer pattern) of insulating substrate 10. Low-voltage side main terminal 3, which applies a low-voltage side potential, branches into and electrically connects to conductor layer pattern 13a (third conductor layer pattern) and conductor layer pattern 13b (third conductor layer pattern). The method for connecting high-voltage main terminal 1 and conductor layer patterns 13a, 13b may be by soldering, metal bonding, or the like, and is not particularly limited to this method.

[0021] [Plane configuration] 1, an example is shown in which the high-voltage side switch of the half-bridge circuit (power semiconductor module 100) is configured in parallel with four chips of power semiconductor elements 21 to 24. Hereinafter, the power semiconductor elements 21 to 24 will be described as MOSFET type transistors. In the case of devices such as SiC-MOSFETs, which require expensive semiconductor substrates to construct the devices, the device dimensions are often small in order to improve the device yield. For this reason, a method is adopted in which multiple device chips are connected in parallel to realize one switch function of a half-bridge circuit and to accommodate a wide range of current values ​​that flow through the switch. Figure 1 shows an example of four parallel connections, but the number of parallel device chips is not limited.

[0022] Conductive layer pattern 11 (second conductor layer pattern) electrically connected to high-voltage main terminal 1 branches to the left and right in the short direction of insulating substrate 10, and is electrically and thermally connected by soldering or sintering bonding to the drain electrodes provided on power semiconductor elements 21 and 22 on the left side and to the drain electrodes provided on power semiconductor elements 23 and 24 on the right side. The source electrodes of power semiconductor elements 21 and 22 are connected via conductive lead frame 25 to conductor layer patterns 12a and 12b (first conductor layer pattern) to which an intermediate voltage is applied. The conductive lead frame will hereinafter be referred to as the lead frame.

[0023] Similarly, the source electrodes of the power semiconductor elements 23 and 24 are connected to the conductor layer patterns 12a and 12b via a lead frame 26. The lead frames 25 and 26 connect the source electrodes of the power semiconductor elements and the conductor layer patterns in a bridge shape.

[0024] To control the operation of the power semiconductor elements 21-24, the gate electrodes of the power semiconductor elements 21-24 are connected to the conductor layer 14 via the bonding wires 41-44. The conductor layer 14, which is the gate control wiring of the high-voltage side arm, is electrically connected to the gate potential control pin 5 (G1 terminal; control terminal) (FIG. 3). The reference potential of the gate potential control pin 5 is the source sense potential control pin 6 (SS1 terminal; control terminal) (FIG. 3). The pin 6 (control terminal) is connected to the conductor layer pattern 12a drawn from the conductive layer (not shown) to which the source electrodes of the power semiconductor elements are connected by the lead frames 25 and 26. Furthermore, the drain sense potential control pin 4 (DS1 terminal; control terminal) (FIG. 3) is connected to the conductor layer pattern 11 in an area that does not overlap with the lead frames, the power semiconductor elements, and the bonding wires in a plan view. The above configuration realizes the switch function on the high-voltage side of the half-bridge circuit.

[0025] The conductor layer pattern 12a is connected to the drain electrodes of the power semiconductor elements 31 to 34 that perform the switching function on the low voltage side. The power semiconductor elements 31 and 32 are aligned in the longitudinal direction of the insulating substrate 10, and are arranged symmetrically with the power semiconductor elements 33 and 34 on the right side with respect to the longitudinal axis of linear symmetry. The source electrodes of the power semiconductor elements 31 and 32 are connected to the conductor layer pattern 13a (third conductor layer pattern) by a lead frame 35 (bridge portion). The source electrodes of the power semiconductor elements 33 and 34 are connected to the conductor layer pattern 13b (third conductor layer pattern) by a lead frame 36 (bridge portion). The conductor layer patterns 13a and 13b are electrically insulated patterns on the insulating substrate, and are connected via the low voltage side main terminal 3.

[0026] The gate electrodes of the power semiconductor elements 31-34 are connected to a conductor layer pattern 15, which is a gate wiring for a low-voltage side arm, via bonding wires 51-54, and the potential (voltage) is controlled by a low-voltage gate voltage control pin 8 (G2 terminal; control terminal). The operating reference potential of the G2 terminal is a conductor layer pattern 16 connected to a source sense voltage control pin 9 (SS2 terminal; control terminal). The half-bridge circuit (power semiconductor module 100) shown in FIG. 1 is connected to the source electrodes of patterned semiconductor elements 31 to 34 via arm structures for sense wiring provided on lead frames 35 and 36. In this way, the low-voltage side switch function of the half-bridge circuit is realized, and the half-bridge circuit is constituted by the conductor layer pattern and lead frame arranged on one insulating substrate 10, and the main terminal group.

[0027] [Cross-sectional structure] The power semiconductor module 100 of this embodiment uses one insulating substrate 10 and adopts a one-sided cooling structure in which a heat dissipation path via a base plate 99 is provided on one surface side. 2, gaps in which no components are shown are filled with insulating resin. In the following explanation, a description of the gaps will be omitted unless otherwise necessary. The insulating substrate 10 disposed below the power semiconductor module 100 has conductor layer patterns 11-17 (FIG. 1) on the upper surface of the insulating substrate 10 and a conductor layer pattern 18 (FIG. 2) on the lower surface. The conductor layer pattern 18 is structured to be electrically and thermally connected to a base plate 99 via a solder layer 19.

[0028] Of the multiple power semiconductor elements 31 to 34, the power semiconductor elements 32 and 34 shown in the cross-sectional view of Fig. 2 have the drain electrode arranged in the direction in which the base plate 99 is arranged, and the source and drain electrodes arranged in the direction in which the lead frame is arranged, and when current flows in the forward direction, the current flows from the drain electrode in the vertical direction of the source electrode. When current flows in the reverse direction, the current flows from the source electrode to the drain electrode. In Fig. 2, the electrode structure of the power semiconductor element is not shown. The on / off of the current is controlled by the voltage applied to the gate electrode with reference to the potential of the source electrode.

[0029] The structure of the insulating substrate 10 (insulating layer) (FIG. 1) on the lead frame side will be described. 2 has a low-voltage side arm structure, in which power semiconductor element 32 is connected above conductor layer pattern 12a via solder layer 32D, and power semiconductor element 34 is connected via solder layer 34D. The source electrode of power semiconductor element 32 is connected to lead frame 35 using solder layer 32S, and the source electrode of power semiconductor element 34 is connected to lead frame 36 using solder layer 34S. Lead frame 35 has joints (not shown) with conductor layer patterns on both sides with power semiconductor element 32 in the center. At the edge side of the insulating substrate 10, the conductor layer pattern 13a is connected by a solder layer 35M. The solder layer 35M serves as a path through which the source current of the power semiconductor element 32 flows. At the center side of the insulating substrate 10, the sense arm structure of the lead frame 35 connects to the conductor layer pattern 16 via a solder layer 35S.

[0030] Similarly, in the lead frame 36, the edge side of the insulating substrate 10 is connected to the conductor layer pattern 13b by a solder layer 36M. In the center side of the insulating substrate 10, the sense arm structure of the lead frame 36 connects to the conductor layer pattern 16 via a solder layer 36S (not shown). As is clear from the cross-sectional structure, the lead frames 35 and 36 have a so-called "double-supported" structure in which the power semiconductor element chip is arranged and connected in the central region and directly connected to the conductor layer patterns on both sides. This is a manufacturing specification in which the thicknesses of the solder layers 32D and 34D are different from the thicknesses of the solder layers 35M, 35S, 36M, and 36S arranged on both sides, and this structure prevents the lead frame from tilting during solder reflow and makes the flat portion of the lead frame as parallel as possible to the flat surface of the insulating substrate 10.

[0031] Moreover, the lead frame 35 bridges the conductor layer pattern 11a (second conductor layer pattern) and connects the conductor layer pattern 11b (FIG. 2) (first conductor layer pattern) to the adjacent and electrically insulated conductor layer pattern 13a (third conductor layer pattern) on the same plane. By using such a bridge structure, the conductor layer pattern 11a can be surrounded by a conductor structure consisting of the conductor layer pattern 12a, the power semiconductor element 32, the lead frame 35, and the conductor layer pattern 13a. Similarly, for the lead frame 36, the conductor layer pattern 11b can be surrounded by a conductor structure consisting of the conductor layer pattern 12a, the power semiconductor element 34, the lead frame 36, and the conductor layer pattern 13b. The effect of reducing parasitic inductance caused by this "surrounding" structure will be described separately.

[0032] [Perspective view structure] First, the structure and arrangement of the control terminal pins 4 to 9 (auxiliary terminals) will be described with reference to FIG. Fig. 3 is a perspective view of components arranged on the insulating substrate 10 shown in Fig. 1. The arrangement and structure of the control terminal pins are clearly shown by using the perspective view of Fig. 3. 3, the control terminal pins 4 to 6 function as control terminals for the high-voltage side arm. The auxiliary terminals (control terminal pins) 4 to 9 further include a gate potential control pin 5 and a source sense potential control pin 6. The voltage (gate-source sense voltage) generated between the gate potential control pin 5 and the source sense potential control pin 6 controls the operations of the power semiconductor elements 21 to 24. The control terminal pins 4 to 6 extend vertically on the conductor layer pattern.

[0033] As the current changes when the power semiconductor elements 21 to 24 are switched, magnetic flux is generated around the conductor layer patterns (11, 12a, 12b, 13a, 13b). When magnetic flux passes through the gap between the gate potential control pin 5 and the source sense potential control pin 6, a problem occurs in which unnecessary noise voltage is superimposed on the gate-source sense voltage due to electromagnetic induction. To suppress the generation of the noise voltage, the power semiconductor module 100 has a structure in which the gate potential control pin 5 and the source sense potential control pin 6 are arranged in close proximity to each other, thereby reducing the amount of magnetic flux linking the gap between the pins.

[0034] [Lead frame shape] Next, the shape of the lead frame will be described with reference to FIG. Lead frame 25 used in the circuit configuration of the high-voltage side arm is connected to the source electrode of power semiconductor element 21 at connection part 25P1 via a connection conductor such as solder. Connection part 25P1 has a shape that is obtained when the lead frame is half-pressed in the thickness direction. For example, the planar dimensions of the connection part are 2 x 3 mm, the lead frame thickness is 1.5 mm, and the half press is limited to about half the thickness. The surface connected to the power semiconductor elements 21-24 is the lower side surface of the connection portion 25P1 shown in Fig. 3. The connection portion 25P2 is a portion connected to the power semiconductor element 22, and the connection portion 25P3 is a portion connected to the conductor layer pattern 12a. The connection portions 25P2 and 25P3 are formed into a stepped shape by half pressing to form the connection surfaces to the power semiconductor elements.

[0035] On the other hand, the shape of the lead frame connected to the conductor layer pattern 12b is an arm shape with an obtuse angle bent portion by bending. When it is necessary to shorten the distance between the power semiconductor elements or the connection parts, a shape by half pressing that can realize a sharp shape is used, and when it is possible to lengthen the distance between the connection parts, an obtuse angle bent shape using a bending process is used. The shape of the connection parts and its manufacturing process are used according to the distance between the connection parts. This is a measure to realize the thickness of the lead frame with a thick conductor material of 1 mm or 1.5 mm. The lead frame 26 has an axisymmetric structure with the lead frame 25. Consideration is given to evenly dividing the switching current flowing through the power semiconductor elements 21 to 24 with the center of the insulating substrate 10 in the longitudinal direction as the axis of symmetry.

[0036] Lead frames 35 and 36 are used in the circuit configuration of the low-voltage side arm. Connection portion 35P1 formed by combining a recess and a protrusion is used for connection to power semiconductor element 31, and connection portion 35P2 is used for connection to the source electrode of power semiconductor element 32. Similarly, connection portion 36P1 is used for connection to power semiconductor element 33, and connection portion 36P2 is used for connection to the source electrode of power semiconductor element 34.

[0037] The connection to the conductor layer pattern 13a is made in a bending process because the distance from the connection portion can be made longer. The lead frames 35 and 36 are shaped to straddle adjacent insulated conductor layer patterns as described in FIG. 2. This arrangement makes it possible to reduce the value of the main circuit inductance generated in the switching current path of the half-bridge circuit compared to the conventional configuration. The lead frame 35 is connected to the power semiconductor elements 31 and 32 mounted on the conductor layer pattern 12a (first conductor layer pattern), straddles the conductor layer pattern 11 (second conductor layer pattern) connected to the high-voltage main terminal, and is then connected to the conductor layer pattern 13a (third conductor layer pattern) connected to the low-voltage main terminal.

[0038] In this manner, the power semiconductor module 100 of this embodiment electrically and thermally connects the source electrodes of the power semiconductor elements to the conductor layer patterns by using the lead frames 25, 26, 35, and 36. That is, in the high-voltage side arm, the power semiconductor elements 21 and 22 are connected to the conductor layer pattern 12a having an intermediate voltage by the lead frame 25, and the power semiconductor elements 23 and 24 are connected to the conductor layer pattern 12b having an intermediate voltage by the lead frame 26. In addition, in the low-voltage side arm, power semiconductor elements 31 and 32 are connected by lead frame 35 to conductor layer pattern 13a (third conductor layer pattern) having a low-voltage side potential, and power semiconductor elements 33 and 34 are connected by lead frame 36 to conductor layer pattern 13b (third conductor layer pattern) having a low-voltage side potential.

[0039] [Effects] The effects of the present embodiment will be described below. In explaining the effects of the present embodiment, a comparative example will be described.

[0040] <Comparative Example> First, a comparative example will be described with reference to FIGS. FIG. 4 is a plan view of a power semiconductor module 110 of the comparative example as viewed from above. The comparative example shown in Fig. 4 shows the structure of a power semiconductor module 110 that does not use a lead frame. The same components as those in Fig. 1, such as the insulating layer, power semiconductor element, and conductor layer pattern, have the same functions as those in Fig. 1, so their explanations are omitted. Similar to the power semiconductor module 100 in Fig. 1, the power semiconductor module 110 of the comparative example shown in Fig. 4 configures a half-bridge circuit using a plurality of conductive layers and power semiconductor elements on a single insulating substrate 10. The number of power semiconductor elements is also the same as in Fig. 1, and this is an example in which four elements are used in both the high-voltage side arm and the low-voltage side arm.

[0041] Power semiconductor module 110 of the comparative example differs from power semiconductor module 100 of FIG. 1 in the method of connection between the source electrode of the power semiconductor element and the conductor layer pattern, the associated positional relationship and shape of the conductor layer patterns, the shapes of high-voltage side main terminal 1 and low-voltage side main terminal 3, and the introduction of a conductive lead frame 37 provided between conductor layer patterns 13a and 13b connecting low-voltage side main terminal 3. Lead frame 37 electrically connects conductor layer patterns 13a and 13b via a conductive bonding material such as a solder layer, and is functionally different from lead frames 25, 26, 35, and 36 shown in Figure 1 that connect the power semiconductor elements and the conductor layer patterns.

[0042] In the power semiconductor module 110 of the comparative example, a source electrode of a power semiconductor element is connected to a conductor layer pattern, and a bonding wire 41 is used for connection for passing a main current. Taking the power semiconductor element 21 as an example, the source electrode of the power semiconductor element 21 is connected to the conductor layer pattern 12 through two paths, that is, bonding wires 41a and 41b. The gate electrode of the power semiconductor element 21 is connected to the gate wiring conductor layer pattern 14 through a bonding wire 41, similar to FIG.

[0043] Conductive layer pattern 11 electrically connected to high-voltage main terminal 1 has a pattern shape that passes through the edge of insulating substrate 10. If the short side direction of insulating substrate 10 is taken as the left-right direction, conductor layer pattern 11 connects the drain electrodes of power semiconductor elements 21 and 22 in the conductor layer pattern 11 branching out to the left, and connects the drain electrodes of power semiconductor elements 23 and 24 in the conductor layer pattern 11 branching out to the right. The source electrodes of the power semiconductor elements 21-24 are connected to the conductor layer pattern 12 by the bonding wires as described above. Here, the conductor layer pattern 14 is a gate wiring pattern for controlling the gate potentials of the power semiconductor elements 21-24. The conductor layer pattern 15 and the bonding wires 61-64 are connection paths for potential transmission that commonize the potential (voltage) of the conductor layer patterns 11 branched in the left and right directions and perform the switching operations of the power semiconductor elements 21-24 equally among the four elements.

[0044] The power semiconductor elements 31- form a low-voltage side arm. The conductor layer pattern 51 is a gate wiring pattern for controlling the gate potential (electric potential) of the power semiconductor elements 31- .

[0045] The power semiconductor elements 31 and 32 will be taken as an example for explanation. Bonding wires 51a, 51b, 52a, and 52b electrically connect the source electrodes of power semiconductor elements 31 and 32 to conductor layer pattern 13a. When the source current of power semiconductor elements 31 and 32 flows in the forward direction, it flows from the elements through conductor layer pattern 13a and through bridge lead frame 37 to conductor layer pattern 13b. In this case, switching current flows in an alternating manner from high-voltage side main terminal 1 through conductor layer pattern 11. That is, a transient current during switching flows through conductor layer pattern 11 from the high-voltage side main terminal 1 side to the power semiconductor elements 21 and 22 side, and in conductor layer pattern 13 arranged adjacent to conductor layer pattern 11, a transient current flows from power semiconductor elements 31 and 32 toward bridge lead frame 35.

[0046] It is widely known that when current flows in opposite directions between adjacent conductor layer patterns, a negative mutual inductance occurs, reducing the return path inductance of the path that travels back and forth between the two adjacent conductor layer patterns.

[0047] Fig. 5 is a diagram for explaining the direction of current flow during switching in the structure of region B1' shown in Fig. 4. Fig. 5 shows a conductor layer pattern in the vicinity of power semiconductor elements 31 and 32 corresponding to region B1 in Fig. 1. In conductor layer pattern 11, a transient current Ip flows from high-voltage side main terminal 1 (FIG. 4) toward elements 21-24 (FIG. 4) of the high-voltage side arm in the direction shown by the thin dashed arrow in FIG. 5 (from node nP1 to nP2). A transient current flowing into node nD via a power semiconductor element in the high-voltage side arm (not shown) flows in conductor layer pattern 12 in the direction shown by the thick dashed arrow in FIG. 5 as drain currents Id1 and Id2 of power semiconductor elements 31 and 32. The current that has passed through power semiconductor elements 31 and 32 flows into conductor layer pattern 13a via bonding wires 51a, 51b, 52a, and 52b, and flows into nodes nN1 and nN2 as source currents Is1 and Is2.

[0048] In the comparative example shown in FIG. 5, compared to FIG. 7 (described later) of this embodiment, the number of conductor layer patterns adjacent to the conductor layer pattern 11 is small, that is, only the conductor layer pattern 13a. As shown in FIG. 5, currents Is1 and Is2 (see solid arrows in FIG. 5) are reverse currents to the direction of current Ip (see thin dashed arrow in FIG. 5) flowing through conductor layer pattern 11. However, currents Id1 and Id2 flowing through conductor layer 12 are not reverse currents to currents Is1 and Is2 but are currents in the same direction (see thick dashed arrow in FIG. 5). Therefore, a mutual inductance having a positive value is generated between conductor layer patterns 12 and 13a, which has the effect of increasing the return inductance of the path through which the switching transient current shown in FIG. 5 flows. Therefore, with the arrangement of conductor layer pattern 11 and the design of the direction of the transient current shown in FIG. 5, the effect of reducing the inductance of the main current path is small, and it can be said that the inductance is larger than that of the structure of FIG. 7 (described later) of this embodiment.

[0049] FIG. 6 is a diagram showing an equivalent circuit in which the wiring structure of the comparative example shown in FIG. 5 is simplified. The conductor layer pattern 11 shown in Fig. 5 can be represented by an inductor element connecting nodes nP1 and nP2 in the equivalent circuit as shown in Fig. 6. The wiring path connected by a bonding wire group from the conductor layer patterns 12 to 13 shown in Fig. 5 can be represented by a circuit from nodes nD to nN1 and nN2 in the equivalent circuit of Fig. 6.

[0050] Of the inductors representing the conductor layer pattern 11 (Figure 5), in the equivalent circuit of Figure 6, a negative mutual inductance M2 occurs between Lp1 and Ls2, and M1 occurs between Lp2 and inductor Ls1. However, for the other inductors representing the conductor layer patterns in the equivalent circuit, there is no relationship between the arrangement in which negative inductance occurs and the reverse current, so it can be seen that the negative mutual inductance is only between M1 and M2 in the current path that flows from node nP1 through nP2, returns to node nD, and flows out to nodes nN1 and nN2. Thus, in the <Comparative Example>, although there is an effect of reducing the return path inductance due to the mutual inductances M1 and M2, the effect of reducing the inductance value is small compared to the equivalent circuit shown in FIG. 8 (described later) of this embodiment. The comparative example has been described above with reference to FIGS.

[0051] <Effects of this embodiment> Next, the effects of this embodiment will be described with reference to FIGS. 1, 7 and 8. FIG. The module structures of region B1 of the power semiconductor module 100 of this embodiment shown in FIG. 1 and region B1' of the power semiconductor module 110 of the comparative example shown in FIG. 4 will be extracted, and the magnitude of inductance generated in both regions will be described. 1, region B2 is provided at a position that is line-symmetrical to region B1. Since the effect of the configuration of region B2 is similar to that of region B1, region B1 will be described in detail below.

[0052] Fig. 7 is a diagram for explaining the direction of current flow during switching in the structure of the B1 region shown in Fig. 1. Fig. 7 shows an excerpt of a circuit in which a lead frame 35 is used for power semiconductor elements 31 and 32. The lead frame 35 has at least one side 35H that is perpendicular to the conductor layer pattern 11 (second conductor layer pattern) through which a reverse current flows, or that intersects with the conductor layer pattern 11 (second conductor layer pattern) at an angle close to being perpendicular.

[0053] The direction of the transient current flow during switching in the circuit shown in FIG. 7 will be described below. In conductor layer pattern 11 (second conductor layer pattern) shown in Fig. 7, transient current Ip flows from high-voltage side main terminal 1 (Fig. 1) toward elements 21-24 of the high-voltage side arm in the direction indicated by the dashed arrow in Fig. 7 (from node nP1 to nP2). The transient current that has passed through the power semiconductor elements of the high-voltage side arm flows in conductor layer pattern 12a (first conductor layer pattern) as drain currents Id1 and Id2 of power semiconductor elements 31 and 32 in the direction indicated by the dashed line arrow in Fig. 7. The current that has passed through the power semiconductor elements 31 and 32 flows into the conductor layer pattern 13a (third conductor layer pattern) via the lead frame 35, and flows into the node nN as a source current Is.

[0054] What should be noted here is the direction of current flowing through the adjacent conductor layer patterns and lead frames. The conductor layer patterns are arranged so that currents Id1 and Id2 (see dashed arrows in FIG. 7) flow in the opposite direction (reverse current) to the current Is with respect to the direction of current ip flowing through conductor layer pattern 11 (see dashed arrows in FIG. 7). The switching transient currents flowing through conductor layer patterns 12 and 13, which are arranged to sandwich conductor layer pattern 11 on either side, are set to flow in the opposite direction. This relationship in current direction can be realized by using lead frame 35 to connect power semiconductor elements 31 and 32, and by connecting conductor layer pattern 11 to conductor layer pattern 13 in a shape in which lead frame 35 straddles conductor layer pattern 11.

[0055] Furthermore, when the width of the lead frame 35 can be set to be as wide as, for example, about 10 mm, the lead frame 35 is formed in the I shown by the solid arrow in FIG. LF 1 or I LF As shown in 2, the current Ip flows at a slope that is not perpendicular to the current Ip. LF 1 and I LF In other words, when we think of the current flow as a vector, it can be broken down into, for example, a direction that is parallel to and opposite to the direction of the current Ip, that is, a direction that is perpendicular to the direction of the reverse current.

[0056] If the two are perfectly orthogonal, no current component will be generated in the direction of the reverse current. However, if they are not orthogonal as in Figure 7, a current component in the direction of the reverse current will be generated. Therefore, Ip and I LF Between 1 and Ip or between I LF 2, a mutual inductance having a negative value is generated between the conductor layer pattern 11 through which Ip flows and the lead frame 35, thereby making it possible to reduce the return inductance of the wiring path shown in FIG.

[0057] On the other hand, the current Ip (see the dashed arrow in FIG. 7) flowing out from the node nP2 returns to the node nd via the high-voltage side arm and becomes the current Id1+Id2 (see the dashed-dotted arrow in FIG. 7), so that a return path is formed in which the current Ip flowing out from the node nP1 returns to the node nN as the current Is. The inductance of this return path is the inductance of the path through which the transient current flows when the power semiconductor module 100 switches, and is therefore important. From the above explanation of FIG. 7, it is clear that a structure that generates a reverse current can generate negative mutual inductance, thereby reducing the dominant inductance value during switching.

[0058] The concept described in the description of FIG. 7 is shown in a simplified equivalent circuit (FIG. 8). FIG. 8 is a diagram showing an electrically equivalent circuit of the circuit shown in FIG. The conductor layer pattern 11 shown in Fig. 7 can be represented by an inductor element connecting nodes nP1 and nP2 in the equivalent circuit shown in Fig. 8. To be precise, the equivalent circuit should be represented by a resistive element and a capacitive element, but this will be omitted since the purpose is to simply illustrate the gist of this embodiment. The wiring path connected by the lead frame 35 from the conductor layer pattern 12 to the conductor layer pattern 13 can be represented by a circuit from node nD to node nN in the equivalent circuit of Fig. 8. The negative mutual inductance in Fig. 8 is represented by M, and the relationship between the two related inductances is indicated by a bidirectional arrow.

[0059] Among the inductors representing the conductor layer pattern 11, a negative mutual inductance M3 occurs between Lp1 and Ld1, and a mutual inductance M4 occurs between Lp2 and the inductor L LF Between 1 and M LF In the following description, the power semiconductor element 31 is referred to as MOS1 (first switch), and the power semiconductor element 32 is referred to as MOS2 (second switch). LF 2 (Fig. 7) is the inductor L LF It flows through 2.

[0060] Figure 7 shows I LF When the current Ip flows from the power semiconductor element 32 toward the conductive pattern 13 at an angle perpendicular to the current Ip, an inverse current relationship does not exist between the currents. As a result, no flux linkage occurs between the currents, and the mutual inductance M LF 2 will be a very small value. Therefore, with regard to MOS2, the effect of the mutual inductance due to the current flowing through the lead frame 35 may be poor. In FIG. 8, the current Is flowing through the conductor layer pattern 13 is also a transient current in the opposite direction to the current Ip flowing through the conductor layer pattern 11, so a negative mutual inductance M1 occurs between Lp3 and Ls1, and a negative mutual inductance M2 occurs between Lp5 and Ls2. In other words, in the current path that flows from node nP1 through nP2, returns to node nD, and flows out to node nN, multiple negative mutual inductances (M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, M23, M24, M25, M26, M27, M28, M29, M30, M31, M32, M33, M34, M35, M36, M37, M38, M39, M40, M41, M42, M43, M44, M45, M46, M47, M48, M49, M50, M51, M52, M53, M54, M55, M56, M57, M58, M59, M60, M61, M62, M63, M64, M65, M66, M67, M68, M69, M70, M71, M72, M73, M74, M75, M76, M77, M78, M79, M82, M83, M84, M85, M86, M87, M88, M91, M92LF 1. M LF 2) It can be seen that the inductance generated in the current path can be reduced.

[0061] From the above description, the power semiconductor module 100 of this embodiment introduces the lead frame 35, and forms a wiring path spanning the conductor layer patterns by using the lead frame 35. This generates a lot of negative mutual inductance between a plurality of current paths, and can reduce the inductance value of the switching current path of the power semiconductor module 100. An example of the analysis results using electromagnetic field analysis software will be described. In the first embodiment shown in Fig. 1, the value of the return inductance generated between the high-voltage side main terminal 1 and the low-voltage side main terminal 3 was 11.4 nH at 10 MHz. On the other hand, in the <Comparative Example> shown in Fig. 4, the value of the return inductance generated between the high-voltage side main terminal 1 and the low-voltage side main terminal 3 was 14.0 nH. An inductance improvement of about 18% was confirmed.

[0062] 9A to 9C are cross-sectional views of the main part of a power semiconductor module for explaining the effect of the first embodiment. FIG. 9A is a schematic diagram of a power semiconductor module 200A of the first embodiment, FIG. 9B is a schematic diagram of a power semiconductor module 200B of the <Comparative Example> of FIG. 5, and FIG. 9C is a schematic diagram of the main part of a semiconductor module 200C of Patent Document 2. In each figure, a circle with a square indicates the direction of current flowing from the bottom of the paper to the top, perpendicular to the paper, and a circle with a cross indicates the direction of current flowing from the top of the paper to the bottom, perpendicular to the paper. An arrow (→) indicates the direction of current, and a bidirectional arrow (⇔) indicates mutual inductance.

[0063] 9B, a power semiconductor module 200B of the comparative example has metal patterns 203a and 203b wired on a heat sink 201 via an insulator 202, and a semiconductor chip 204 formed on the metal pattern 203a. A mutual inductance M1 is generated between the metal patterns 203a and 203b due to currents flowing in the opposite directions.

[0064] In the conventional semiconductor module 200C of FIG. 9C, mutual inductance M1 occurs between upper and lower metal patterns 203a and 203b sandwiching an insulator 202 due to currents flowing in opposite directions.

[0065] In contrast, in a power semiconductor module 200A of this embodiment shown in FIG. 9A, a lead frame 205 is inserted between a metal pattern 203a on which a semiconductor chip 204 is mounted and a metal pattern 203c that straddles an adjacent metal pattern 203b. With this configuration, a mutual inductance M1 occurs between metal patterns 203a and 203b, a mutual inductance M2 occurs between metal patterns 203b and 203c, and a mutual inductance M3 occurs between metal pattern 203b and lead frame 205. By introducing lead frame 205, it is possible to increase the number of locations where mutual inductance M (M1, M2, M3) occurs compared to the conventional structure. This makes it possible to increase the absolute value of the mutual inductance and reduce the total inductance L. The total inductance L is expressed by the following equation (1).

[0066] L = self-inductance of wiring Lself - mutual inductance from surrounding wiring M …(1)

[0067] [Effects of the first embodiment] As described above, the power semiconductor module 100 of the first embodiment is a power semiconductor module including the first switch and the second switch (MOS1, MOS2) configured using the power semiconductor elements 31, 32, and one or more half-bridge circuits (power semiconductor modules 100) configured by connecting the first switch and the second switch in series. The half-bridge circuit includes an insulating substrate 10 (FIG. 3), a conductor layer pattern 12a (first conductor layer pattern), a conductor layer pattern 11 (second conductor layer pattern), and a conductor layer pattern 13a (third conductor layer pattern) (FIG. 1) that are arranged on one surface of the insulating substrate 10 and are electrically insulated from each other, and the conductor layer pattern 12a (first conductor layer pattern), the conductor layer pattern 11 (second conductor layer pattern), and the conductor layer pattern 13a (third conductor layer pattern) (FIG. 1) are arranged on one surface of the insulating substrate 10 and are electrically insulated from each other. The semiconductor device includes power semiconductor elements 31, 32 (MOS1, MOS2) electrically and thermally connected on a first conductor layer pattern (MOS1), and lead frames 35, 36 electrically connecting the power semiconductor elements 31, 32 and the conductor layer pattern 13a (third conductor layer pattern) across the conductor layer pattern 11 (second conductor layer pattern), where the conductor layer pattern 11 (second conductor layer pattern) is disposed in a region between the conductor layer pattern 12a (first conductor layer pattern) and the conductor layer pattern 13a (third conductor layer pattern), and the direction of a transient current flowing through the conductor layer pattern 11 (second conductor layer pattern) is opposite to the direction of a current flowing through the conductor layer pattern 13a (third conductor layer pattern) (FIG. 7).

[0068] As mentioned in the problem to be solved, the challenges for power semiconductor modules are to reduce the risk of exceeding the withstand voltage and to reduce losses during operation. Therefore, it is important to reduce the internal inductance of the power semiconductor module. In the first embodiment, the power semiconductor module 100 includes lead frames 35 and 36 that cross the second conductor layer pattern 11 through which a reverse current flows and electrically connect the power semiconductor elements 31 and 32 on the first conductor layer pattern 12 to the third conductor layer pattern 13. This makes it possible to optimize both the self-inductance and mutual inductance of the wiring of each conductor layer pattern and to equalize the inductance of multiple chip paths. The lead frames 35 and 36 have a shape that synthesizes and adjusts the self-inductance of the path and the mutual inductance from the second conductor layer pattern 11 through which a reverse current flows in order to equalize the inductance of each of the multiple power semiconductor elements 31 and 32.

[0069] This allows a large amount of negative mutual inductance to be generated between multiple current paths, reducing the inductance value of the switching current paths of the power semiconductor module. As a result, it is possible to improve the heat balance between multiple chips, allowing the power semiconductor module to be used at high temperatures and increasing the inverter current.

[0070] In particular, in the first embodiment, in the power semiconductor module 100 constituting a half-bridge circuit, a control wiring structure that suppresses electromagnetic interference from the main current path and a wiring structure for the main current circuit of the power semiconductor module 100 that reduces the parasitic inductance of the main current path while also having excellent heat dissipation properties are adopted, thereby reducing the parasitic inductance generated in the main circuit current path and providing a control terminal arrangement configuration that achieves stable operation during high-speed switching. The power semiconductor module having such excellent characteristics is suitable for use in EVs and industrial power conversion devices.

[0071] In the power semiconductor module 100, the power semiconductor elements 31, 32 have a plurality of semiconductor chips (power semiconductor elements 31, 32; MOS1, MOS2) arranged on a conductor layer pattern 12a (first conductor layer pattern), and the lead frames 35, 36 have first connection surface portions 35AP1, 35AP2 (FIG. 12 described later) that are respectively connected to the electrode surfaces of the semiconductor chips (power semiconductor elements 31, 32; MOS1, MOS2) and a second connection surface portion 35AS' (FIG. 13 described later) that is connected to the conductor layer pattern 13a (third conductor layer pattern).

[0072] By configuring in this manner, the respective connection surface portions of the lead frames 35, 36 can be tightly connected to the electrode surfaces of the respective semiconductor chips (power semiconductor elements 31, 32; MOS1, MOS2) and the electrode surfaces of the conductor layer pattern 13a (third conductor layer pattern) with opposing surfaces in close contact with each other, thereby improving the reliability of the power semiconductor module 100.

[0073] In the power semiconductor module 100, the first connection surface portions 35AP1, 35AP2 (FIG. 12) have convex end faces (first connection surface portions 35AP1', 35AP2') (FIG. 13) that are convex toward the electrodes of each semiconductor chip (power semiconductor elements 31, 32; MOS1, MOS2).

[0074] By configuring it in this manner, the convex-shaped end faces (first connection surface portions 35AP1', 35AP2') can be connected to the electrodes of each semiconductor chip (power semiconductor elements 31, 32; MOS1, MOS2) with opposing surfaces in close contact with each other, thereby improving the reliability of the power semiconductor module 100.

[0075] In the power semiconductor module 100, the power semiconductor elements 31 and 32 have a plurality of semiconductor chips arranged in the longitudinal direction on the conductor layer pattern 12a (first conductor layer pattern), and the lead frames 35 and 36 cover the electrode surfaces of the respective semiconductor chips (power semiconductor elements 31 and 32; MOS1 and MOS2) and have a lead frame 35A (bridge portion) (FIGS. 12 and 13 described later) that connects between the electrodes of the respective semiconductor chips and the conductor layer pattern 13a (third conductor layer pattern) across the conductor layer pattern 11 (second conductor layer pattern), and the lead frame 35A (bridge portion) (FIGS. 12 and 13 described later) serves to control a switching current (I LF 1,I LF 2) (FIG. 7) is applied to the conductor layer pattern 13a (third conductor layer pattern).

[0076] With this configuration, it is possible to generate a large amount of negative mutual inductance between the multiple current paths, thereby reducing the inductance value of the switching current paths of the power semiconductor module 100. As a result, it is possible to improve the heat balance between the multiple chips, allowing the power semiconductor module to be used at high temperatures and increasing the inverter current.

[0077] In the power semiconductor module 100, the lead frame 35A (bridge portion) (FIGS. 12 and 13 described below) has at least one side 35H (FIG. 7, FIG. 12 and FIG. 13 described below) that is perpendicular to the conductor layer pattern 11 (second conductor layer pattern) through which a reverse current flows, or that intersects with the conductor layer pattern 11 (second conductor layer pattern) at an angle close to perpendicular.

[0078] With this configuration, the length of side 35H of lead frame 35A can be used as a shape design parameter for the lead frame.

[0079] Second embodiment A power semiconductor module according to a second embodiment of the present invention will now be described. In the first embodiment, it has been shown that the use of lead frames 35 and 36 (FIG. 1) makes it possible to reduce the inductance of the main current path (the path in which the current value changes during switching) of the power semiconductor module 100. The second embodiment shows a method for improving the uniformity of the current value during switching that flows between power semiconductor elements connected in parallel.

[0080] [Schematic configuration] Fig. 10 is a plan view showing a schematic configuration of a power semiconductor module 101 of the second embodiment, and is a plan view of the power semiconductor module 101 seen from above. The same components as those in Fig. 1 are denoted by the same reference numerals. Fig. 11 is a cross-sectional view taken along the line A-A' in Fig. 10. A power semiconductor module 101 of this embodiment differs from the power semiconductor module 100 shown in FIG. 1 only in the shapes of the lead frames 35A and 36A. Areas C1 and C2 enclosed by dashed lines in FIG. 10 correspond to areas B1 and B2 enclosed by dashed lines in FIG. 1, respectively.

[0081] The power semiconductor elements 31 and 32, the lead frame 35A and the conductor layer patterns therearound will be described.

[0082] The lead frame 35A has a side 35H that is perpendicular to the conductor layer pattern 11 (second conductor layer pattern) through which a reverse current flows, or that intersects with the conductor layer pattern 11 (second conductor layer pattern) at an angle close to being perpendicular. The lead frame 35A has a notch 35N in a shape seen from above. Specifically, the lead frame 35A has the notch 35N that cuts the side 35H in the length direction and / or width direction of the conductor layer pattern 12a (first conductor layer pattern). The lead frame 35A uses the area excluding the notch 35N to pass a switching current that flows through the conductor layer pattern 12a (first conductor layer pattern) to the conductor layer pattern 13a (third conductor layer pattern).

[0083] Of the lead frames 35A and 36A in FIG. 10, the lead frame 35A will be described as a representative example. Fig. 12 is a perspective view of the lead frame 35A of Fig. 10 as seen from above. Fig. 13 is a perspective view of the lead frame 35A of Fig. 10 as seen from below. 12 and 13, in lead frame 35A, one of the corners of lead frame 35 in FIG. 1 is cut out as notch 35N. Notch 35N is a rectangular notch in plan view, and has a notch length (Notch-L) and a notch width (Notch-W). Notch length (Notch-L) is the lateral length from metal pattern 203a to 203b shown in FIG. 9A. Notch width (Notch-W) is the longitudinal width of metal pattern 203b shown in FIG. 9A through which reverse current flows.

[0084] 12 and 13, the hole 35H in the lead frame 35A is a resin injection hole for facilitating the filling of the gap under the lead frame with the sealing resin when the power semiconductor module 101 (FIG. 10) is resin-sealed. Even when the hole 35H is provided, the effect shown in the first embodiment can be obtained.

[0085] As described above, the lead frame 35A has the notch 35N. As shown in Figures 12 and 13, the area of ​​the notch 35N is indicated by a dashed line, and among the dimensions of the notch 35N, the length of the notch is indicated as Notch-L and the width of the notch is indicated as Notch-W. A connection portion 35AP1 which is a portion connected to the source electrode of the power semiconductor element 31, and a connection portion 35AP2 which is a portion connected to the source electrode of the power semiconductor element 32 are provided with a shape that protrudes downward toward the lower surface of the lead frame.

[0086] 13 shows a perspective view of the lead frame 35A seen from below, as described above, and clearly shows the connection surfaces with the power semiconductor element and the conductor layer pattern. Specifically, the connection surface electrically and thermally connected to the source electrode of the power semiconductor element 31 via a solder layer is indicated as connection surface 35AP1' (first connection surface portion), and the connection surface connected to the power semiconductor element 32 is indicated as connection surface 35AP2' (first connection surface portion). In addition, the connection surface connected to the conductor layer pattern 13 and through which the main current flows is indicated as connection surface 35AM', and the sense connection surface that transmits the source electrode potential of the power semiconductor element to the sense terminal (SS2 terminal) is indicated as connection surface 35AS' (second connection surface portion). The structure of lead frame 35A (bridge portion) having cutout portion 35N has been described above. Note that lead frame 36A has the same structure as lead frame 35A.

[0087] <Effects of the Second Embodiment> Next, the effect of the cutout structure in the lead frame will be described, focusing on the deviation (imbalance) between the power semiconductor elements in the transient current that flows between the power semiconductor elements connected in parallel during switching.

[0088] 14A to 14C are diagrams showing current paths of a power semiconductor element in a circuit in which a lead frame is used for the power semiconductor element. Fig. 14A is a diagram for explaining the direction of current flow during switching in the structure of region B1 shown in Fig. 1, which does not have a notch. Fig. 14B is a diagram for explaining the direction of current flow during switching in the structure of region C1 shown in Fig. 10, when the notch width is Notch-W1. Fig. 14C is a diagram for explaining the direction of current flow during switching in the structure of region C1 shown in Fig. 10, when the notch width is Notch-W2. Note that region C2 shown in Fig. 10 has a similar current path as region C1 shown in Fig. 10, so region C1 will be described as a representative.

[0089] The effects of each of the structures shown in FIGS. 14A to 14C will now be described in detail. · Relationship between the structure of the lead frame in Fig. 14A and inductance The lead frame 35Aa shown in Fig. 14A has a "notchless" shape and extends from the connection site 35AP2 with the power semiconductor element 32 by the notch length (Notch-L). In this case, as shown by the solid-line arrow in Fig. 14A, the current from the source electrode of the power semiconductor element 32 (MOS2) flows obliquely through the lead frame 35Aa from the position of the notch length Notch-L to the node nN. That is, the current from the source electrode of the power semiconductor element 32 (MOS2) crosses at an angle obliquely with respect to the reverse current Ip as shown in Fig. 14A LF 2. As a result, the inductance of the current path of MOS2 with I LF 2 as the path is lower than the inductance of the current path of the power semiconductor element 31 (MOS1), and a relationship of LMOS2 < LMOS1 occurs.

[0090] Here, LMOS1 is defined as the inductance of the path passing through MOS1 among the return inductances from the node nP1 to nN, and LMOS2 is defined as the inductance of the path passing through MOS2 among the return inductances from the node nP1 to nN. When adopting the structure of the lead frame without the notch shown in Fig. 14A, the lead frame extends by the amount of Notch-L, and the inductance of the path of MOS2 with a shorter path length on the lead frame tends to be smaller.

[0091] · Relationship between the structure of the lead frames in Figs. 14B and 14C and inductance The lead frames shown in Figs. 14B and 14C are lead frames with notches, and this is the case where the notch width Notch-W is set to Notch-W1 and Notch-W2. By setting the notch width Notch-W, I LF 2 has a path orthogonal to the current Ip (in Figs. 14B and 14C, refer to I LF 2 (solid-line arrow) orthogonal to the current Ip (dashed-line arrow)). As a result, I LFThe absolute value of the negative mutual conductance occurring between MOS1 and Ip becomes smaller. This means that the return inductance from node nP1 to nN is smaller in the path through MOS1 than in the path through MOS2. MOS2 >L MOS1 A relationship occurs.

[0092] From the above, in the width Notch-W of the notch between FIG. 14A and FIG. 14B and FIG. 14C, L MOS1 ≒L MOS2 It is clear that there exists a width for which the inductance between MOS1 and MOS2 can be made uniform by adopting the shape of lead frame 35A and optimizing the width of the notch.

[0093] Fig. 15 is a diagram showing the results of an analysis of the magnitude of inductance in each current path in Fig. 14A to Fig. 14C. The vertical axis of Fig. 15 shows the total inductance value of the path through which current flows from nP1 to nN in Fig. 14A to Fig. 14C, and the horizontal axis of Fig. 15 shows the inductance value obtained by changing the notch width (Notch-W) of lead frame 35A. From the inductance values ​​obtained by changing the notch width (Notch-W) of the lead frame 35A, the tendency shown in the graph of Fig. 15 can be seen. It can be seen that when the lead frame has a notch width (Notch-W), the total inductance value tends to increase compared to when there is no notch.

[0094] 16A to 16D are waveform diagrams showing switching transient waveforms in the power semiconductor module 101 shown in Fig. 10 when the width Notch-W of the notches in the lead frames 35A and 36A is optimized and the inductance values ​​of the power semiconductor elements connected to the lead frames are made uniform. For comparison, waveform examples in the case where the inductance values ​​are not uniform are also shown.

[0095] FIG. 16A shows waveforms obtained by connecting an inductive load to the intermediate voltage main terminal and switching power semiconductor elements 31 to 34 (FIG. 10) in the low-voltage side arm for an analysis circuit equivalent to power semiconductor module 101 in FIG. 10, and illustrates the waveforms at the timing when the elements are turned on. 16A plots two current waveforms, with the dashed line plot (Is_MOS1) corresponding to the transient current flowing through power semiconductor elements 31 and 33. The dashed-dotted line plot (Is_MOS2) corresponding to the transient current flowing through power semiconductor elements 32 and . 16A shows a case where the inductance of each power semiconductor element connected to the same lead frame is non-uniform. As a result, the current waveforms of Is_MOS1 and Is_MOS2 do not match, and in particular the peak currents during switching are significantly different. The solid line plot in FIG. 16A represents the drain-source voltage Vds applied between the drain electrode and the source electrode of the power semiconductor element. The two power semiconductor elements (power semiconductor elements 31 and 33, or power semiconductor elements 32 and 34) are connected in parallel and therefore operate at the same Vds.

[0096] FIG. 16B is a characteristic diagram in which the losses occurring in each power semiconductor element for the transient waveform shown in FIG. 16A are calculated and plotted. Due to the non-uniformity of the currents shown in FIG. 16B, the loss occurring in MOS1 is larger than the loss occurring in MOS2, and for example, the loss in MOS1, P_MOS1, is 12% larger than that in PMOS2 (see the following equation (2)).

[0097] ΔP=(P_MOS1 / P_MOS2)-100%=12% …(2) However, P_MOS1=Is_MOS1×Vds P_MOS2=Is_MOS2×Vds

[0098] FIG. 16C is a waveform diagram showing switching transient waveforms when the notch width (Notch-W) of the lead frames 35 and 36 of the power semiconductor module 101 of FIG. 10 is optimized and the inductance of each element path is set equal. As shown in FIG. 16C, it can be confirmed that optimizing the switching width of the lead frame allows the current waveforms of Is_MOS1 and Is_MOS2 to operate with approximately the same shape (the two current waveforms are approximately overlapped).

[0099] FIG. 16D is a characteristic diagram in which the losses occurring in each power semiconductor element are calculated and plotted for the transient waveform shown in FIG. 16C. As shown in FIG. 16D, the current waveforms of Is_MOS1 and Is_MOS2 operate with approximately the same shape, so the deviation (imbalance) of the losses of each power semiconductor element can be kept small and reduced to 2% (see the following equation (3)).

[0100] ΔP=(P_MOS1 / P_MOS2)-100%=2% …(3) However, P_MOS1=Is_MOS1×Vds P_MOS2=Is_MOS2×Vds

[0101] Comparing the loss deviation of each power semiconductor element, which equivalently represents the deviation in current, it can be seen that by adopting a notched shape and optimizing its shape, the deviation can be reduced to 1 / 6, or 2%, in FIG. 16D compared to 12% in FIG. 16B.

[0102] ·supplementary explanation 17A to 17D are diagrams showing current paths of a power semiconductor element in a circuit using a lead frame for the power semiconductor element. The same components as those in FIGS. 14A to 14C are denoted by the same reference numerals. Fig. 17A is a diagram illustrating the direction of current flow during switching for the structure of region B1 shown in Fig. 1 that does not have a notch, Fig. 17B is a diagram illustrating the direction of current flow during switching for the structure of region C1 shown in Fig. 10 when the notch width is Notch-Wa, Fig. 17C is a diagram illustrating the direction of current flow during switching for the notch width Notch-Wb, and Fig. 17D is a diagram illustrating the direction of current flow during switching for the notch width Notch-Wc. FIG. 18 is a diagram showing a comparison of the inductance values ​​of LMOS1 and LMOS2 in the current paths of each of FIGS. 17A to 17D. LMOS1 is the inductance value of the path through which current flows from nP1 to nN and passes through MOS1 (power semiconductor element 31), and LMOS2 is the inductance value of the path through which current flows from nP1 to nN and passes through MOS2 (power semiconductor element 32).

[0103] As shown in FIG. 18, in the circuit without the notch of FIG. 17A, L MOS1 and L MOS2 The inductance value of is the smallest. In the circuit of FIG. 17B, the lead frame on MOS2 is partially cut out by the width of the cutout Notch-Wa, as shown in FIG. 17B. Therefore, L MOS1 The inductance value of L MOS2 The inductance value is slightly larger than that of L MOS1 and L MOS2 The inductance value is larger than that of the circuit of FIG. 17A.

[0104] In the circuit of FIG. 17C, the lead frame above MOS2 is notched by a larger width Notch-Wb as shown in FIG. MOS1 and L MOS2 The magnitude relationship of the inductance value of L MOS2 The inductance value of L MOS1 The inductance value is slightly larger than that of L MOS1 and L MOS2 The inductance value of is larger than that of the circuit of FIG. 17B.

[0105] In the circuit of FIG. 17D, the lead frame above MOS2 is cut out by the largest notch width Notch-Wc, as shown in FIG. MOS2 The inductance value of L MOS1 The inductance value of L MOS1 and L MOS2 The inductance value is the largest among the circuits of FIGS. 17A to 17D.

[0106] [Effects of the second embodiment] Incidentally, when a power semiconductor device has multiple semiconductor chips arranged in the longitudinal direction on a first conductor layer pattern, an inductance difference occurs between the multiple chips connected to the conductor (lead frame) through which the main current flows. The inductance difference leads to uneven heating of the chips. The uneven heating of the chips ultimately affects switching loss and suppression of surge voltage.

[0107] In the power semiconductor module 110 of the second embodiment, a lead frame 35A (bridging portion) (FIGS. 12 and 13) has a side 35H (FIGS. 7, 12, and 13) that is perpendicular to the conductor layer pattern 11 (second conductor layer pattern) through which a reverse current flows, or that intersects with the conductor layer pattern 11 (second conductor layer pattern) at an angle close to being perpendicular, and a cutout portion 35N (FIGS. 12 and 13) that cuts out the side 35H in the length direction and / or width direction of the conductor layer pattern 12a (first conductor layer pattern), and the lead frame 35A uses the area excluding the cutout portion 35N to flow a switching current that flows through the conductor layer pattern 12a (first conductor layer pattern) to the conductor layer pattern 13a (third conductor layer pattern).

[0108] With this configuration, the length of the notch Notch-L or the width of the notch Notch-W is adjusted to equalize the current path length of the switching current flowing from each semiconductor chip (power semiconductor elements 31, 32; MOS1, MOS2) to the third conductor layer pattern 13. As a result, in the current path that is / is not subjected to magnetic field coupling from the reverse current, the length of the notch 35N is adjusted to increase or decrease the magnitude of the magnetic field coupling, i.e., the mutual inductance, to adjust the inductance of one semiconductor chip path and make it possible to balance it with the inductance of the other semiconductor chip. The inductance values ​​between the multiple chips can be equalized. Here, adjustment by the notch length Notch-L or the notch width Notch-W has the advantage that it is easy to parameterize.

[0109] In the power semiconductor module 110 of the second embodiment, the notch 35N (FIGS. 12 and 13) is a part that determines the magnitude of the switching current (I LF 1,I LF 2) The length and / or width of the notch is set so that the deviation between the semiconductor chips (power semiconductor elements 31, 32; MOS1, MOS2) is small.

[0110] With this configuration, the magnitude of the switching current (I LF 1,I LF 2) is reduced. This makes it possible to increase or decrease the mutual inductance from the conductor layer pattern 11 (second conductor layer pattern) to the first chip current path by synthetic adjustment, and to achieve a balance with the second chip path inductance. This makes it possible to equalize the shunting of transient currents of the power semiconductor elements connected to the same lead frame, and also makes it possible to equalize the losses of the power semiconductor elements. As a result, it is possible to provide a power semiconductor module with a small inductance value of the main current path, and at the same time, to provide a highly reliable power semiconductor module.

[0111] Third embodiment A power conversion device according to a third embodiment of the present invention will be described. FIG. 19 is a block diagram showing a circuit configuration of a power conversion device according to the third embodiment of the present invention. FIG. 19 shows an example of a three-phase AC motor that drives the axle of an electric vehicle, which is composed of a battery 250, a power conversion device 260, and an electric motor 270 that serves as a load. The power conversion device 260 of this embodiment includes a 6-in-1 power module configured with a three-phase circuit of the power semiconductor module 100 (FIG. 1) or 101 (FIG. 10) as one phase, a capacitor 240, and a control circuit 230. The power semiconductor modules 100 and 101 in FIG. 16 are half-bridge circuits. The power conversion device 260 includes the gate drive circuits 210 whose number is equal to the number of phases of the AC.

[0112] The power conversion device 260 holds a main voltage (Vcc) using a capacitor 240, and a gate drive signal for a power semiconductor element in each power semiconductor module 100 or 101 generated by a control circuit 230 is input to each power semiconductor module 200 via gate drive circuits 210a, 210b, 210c. The leg circuits 220a, 220b, and 220c respectively constitute a first-phase inverter leg, a second-phase inverter leg, and a third-phase inverter leg. The output of each inverter leg is connected to the motor 270.

[0113] In this embodiment, the leg circuits 220a, 220b, and 220c have the same circuit configuration, so the circuit configuration will be described by taking the leg circuit 220a as an example. The leg circuit 220a includes a pair of upper and lower arms formed by the power semiconductor module 100 or 101, and a gate drive circuit 210a that controls the on / off of the power semiconductor module. According to this embodiment, the power semiconductor modules 100, 101 mounted on the power conversion device 260 are the power semiconductor modules described in the first or second embodiment, and the value of the internal inductance of the module can be reduced, and at the same time, the loss of the power semiconductor elements mounted on the module can be made uniform and operated. Therefore, high-speed switching is possible in the power conversion device 260 configured using the power semiconductor modules 100, 101, and in the motor drive system for an electric vehicle configured including the power conversion device 260. As a result, it is possible to reduce the loss of the power conversion device 260.

[0114] The effects of this embodiment can be summarized as follows. Since the internal inductance value of the power semiconductor module can be reduced and at the same time the losses of the power semiconductor elements mounted on the module can be made uniform to operate, high-speed switching can be enabled in the power conversion device 260 configured using this and in the electric vehicle motor drive system including the same, thereby enabling low loss in the power conversion device.

[0115] The present invention is not limited to the above-described embodiments, and includes other modified examples and application examples without departing from the gist of the present invention described in the claims. For example, the above-described embodiments have been described in detail to aid in understanding the present invention, and the present invention is not necessarily limited to those having all of the configurations described. In addition, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with another configuration. For example, the dimensions and insulation distances of the members constituting the power semiconductor modules 100 and 101 may be arbitrary depending on the application. Furthermore, the chip arrangement of the power semiconductor elements constituting the power semiconductor modules 100 and 101 is not limited to the form shown in the drawings.

[0116] In addition, in the embodiment in which the upper and lower arms are mounted on the same power semiconductor module 100, 101, the explanation has been given with a focus on one of the arm circuits, but the other arm circuit has the same effect, and there is no reduction in effect due to the 2-in-1 configuration. Rather, it is widely known that the adoption of the 2-in-1 configuration provides an additional effect of reducing parasitic inductance due to the effect that the direction of the main current flowing through the power semiconductor switching element flows in the opposite direction between adjacent conductor layers, and this suggests a suitable example from the viewpoint of providing a high-performance power semiconductor module.

[0117] The power semiconductor module 200 may be a unipolar device such as a JFET (Junction Field Effect Transistor) or a bipolar device such as an IGBT, in addition to a MOSFET. Depending on the device, the main terminal and the sense terminal are called a "collector" and an "emitter" instead of the above-mentioned "drain" and "source".

[0118] Furthermore, it is clear that the effects described in this specification can be obtained regardless of the form in which the power semiconductor module is configured, for example, in a case where the 2-in-1 configuration using the power semiconductor modules 100 and 101 shown in the embodiments is used as a module unit, or in a case where three 2-in-1 configurations are combined for three phases to form a 6-in-1 module. Furthermore, power conversion devices to which the present power semiconductor modules 100, 101 are applied can be used in motor drive systems for various types of moving objects, including railroad cars and electric vehicles, as well as industrial systems, PCS (Power Conditioning Systems) in solar power generation devices and wind power generation devices, smart grids (power distribution systems), and the like. [Explanation of symbols]

[0119] 1 High voltage main terminal 2 Medium voltage terminal 3 Low voltage main terminal 4~9 Control terminal pins (auxiliary terminals) 10 Insulating substrate (insulating layer) 11~18 Conductive layer pattern 11, 11a Conductive layer pattern (second conductive layer pattern) 12, 12b Conductive layer pattern (first conductive layer pattern) 13, 13a, 13b Conductive layer patterns (third conductive layer patterns) 19 Solder layer 21-24, 31-34 Power semiconductor elements 31 Power semiconductor element (MOS1, first switch) 32 Power semiconductor element (MOS2, second switch) 25,26,35,36,35A,36A Lead frame (bridge) 35H Side that is perpendicular to the second conductor layer pattern that carries a reverse current, or that intersects the second conductor layer pattern at an angle close to perpendicular 35AP1' Connection surface (first connection surface portion) 35AS' Connection surface (second connection surface) 100,101 Power semiconductor module (half-bridge circuit) 210 Gate drive circuit 220 Leg Circuit 230 Control circuit 240 Capacitor 250 Battery or power circuit 260 Power Converter 270 Electric motor

Claims

1. a first switch and a second switch configured using a power semiconductor element; A power semiconductor module including one or more half-bridge circuits each including the first switch and the second switch connected in series, The half-bridge circuit includes: An insulating substrate; a first conductor layer pattern, a second conductor layer pattern, and a third conductor layer pattern that are disposed on one surface of the insulating substrate and are electrically insulated from one another; the power semiconductor element being electrically and thermally connected onto the first conductor layer pattern; a lead frame that electrically connects the power semiconductor element and the third conductor layer pattern across the second conductor layer pattern, the second conductor layer pattern is disposed in a region between the first conductor layer pattern and the third conductor layer pattern, The direction of the transient current flowing through the second conductor layer pattern is opposite to the direction of the current flowing through the third conductor layer pattern. A power semiconductor module comprising:

2. The power semiconductor element is a plurality of semiconductor chips arranged on the first conductor layer pattern; The lead frame is a first connection surface portion connected to an electrode surface of each of the semiconductor chips; a second connection surface portion connected to the third conductor layer pattern.

2. The power semiconductor module according to claim 1 .

3. The first connection surface portion has a convex end surface that is convex toward the electrodes of the semiconductor chips.

3. The power semiconductor module according to claim 2.

4. The power semiconductor element is a plurality of semiconductor chips arranged in a longitudinal direction on the first conductor layer pattern; The lead frame is a bridge portion that covers an electrode surface of each of the semiconductor chips and connects between the electrode of each of the semiconductor chips and the third conductor layer pattern across the second conductor layer pattern; The bridging portion causes a switching current flowing through the first conductor layer pattern to flow through the third conductor layer pattern.

2. The power semiconductor module according to claim 1 .

5. The bridge portion has at least one side that is perpendicular to the second conductor layer pattern through which a reverse current flows, or that intersects with the second conductor layer pattern at an angle close to perpendicular to the second conductor layer pattern.

5. The power semiconductor module according to claim 4.

6. the bridging portion has a notch portion that cuts the side in the length direction and / or width direction of the first conductor layer pattern, The bridge portion causes a switching current flowing through the first conductor layer pattern to flow through the third conductor layer pattern by using an area other than the notch portion.

6. The power semiconductor module according to claim 5.

7. The notch has a length and / or a width such that a deviation in the magnitude of a switching current flowing through each of the semiconductor chips is small between the semiconductor chips.

7. The power semiconductor module according to claim 6.

8. A main circuit having one or more pairs of upper and lower arms; A power conversion device comprising: a drive circuit for driving the upper and lower arms, A power conversion device, wherein the upper and lower arms each include the power semiconductor module according to claim 1 .

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