Semiconductor package

Abstract

To provide a semiconductor package of which a product reliability is improved.SOLUTION: A semiconductor package according to the present invention, includes: a first semiconductor chip; a second semiconductor chip on the first semiconductor chip; a first bonding pad that is arranged on a first surface of the first semiconductor chip facing the second semiconductor chip; and a second bonding pad that is arranged on a second surface of the second semiconductor chip facing the first surface, and is in contact with the first bonding pad. The second bonding pad includes: a third surface that is in contacted with the first bonding pad; and a fourth surface that is opposite to the third surface. The second semiconductor chip includes: a first wiring pad that is in contact with the fourth surface of the second bonding pad; and a second wiring pad that is separated from the first wiring pad and the second bonding pad. A thickness of the second wiring pad is smaller than that of the first wiring pad.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor package, and more particularly to a semiconductor package with improved product reliability. [Background technology]

[0002] 2. Description of the Related Art With the development of the electronics industry, there is an increasing demand for electronic components with higher functionality, higher speed and smaller size. In response to this trend, a method is used in which a plurality of semiconductor chips are stacked and mounted on one package wiring structure, or a package is stacked on top of another package. In recent years, direct bonding has been used to vertically stack multiple dies, thereby reducing the interconnect length between stacked chips. This has created a demand for the development of semiconductor packages with improved product reliability. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in consideration of the above-mentioned problems with conventional semiconductor packages, and an object of the present invention is to provide a semiconductor package with improved product reliability. [Means for solving the problem]

[0004] In order to achieve the above-mentioned object, a semiconductor package according to the present invention comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first bonding pad arranged on a first surface of the first semiconductor chip facing the second semiconductor chip, and a second bonding pad arranged on a second surface of the second semiconductor chip facing the first surface and in contact with the first bonding pad, the second bonding pad including a third surface in contact with the first bonding pad and a fourth surface opposite the third surface, the second semiconductor chip including a first wiring pad in contact with the fourth surface of the second bonding pad and a second wiring pad spaced apart from the first wiring pad and the second bonding pad, and a thickness of the second wiring pad is smaller than a thickness of the first wiring pad.

[0005] In addition, in order to achieve the above-mentioned object, a semiconductor package according to the present invention includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first bonding pad arranged on a first surface of the first semiconductor chip facing the second semiconductor chip, and a second bonding pad arranged on a second surface of the second semiconductor chip facing the first surface and in contact with the first bonding pad, the second semiconductor chip includes a first wiring pad in contact with the second bonding pad, and a second wiring pad spaced from the first wiring pad and not in contact with the second bonding pad, the first wiring pad includes a third surface in contact with the second bonding pad and a fourth surface opposite the third surface, the second wiring pad includes a fifth surface facing the first semiconductor chip and a sixth surface opposite the fifth surface, the fourth surface and the sixth surface are arranged on the same plane, and the third surface is arranged below the fifth surface based on the first surface of the first semiconductor chip.

[0006] In order to achieve the above object, a semiconductor package according to the present invention includes a package substrate, a first semiconductor chip on the package substrate, a second semiconductor chip on the first semiconductor chip, a first bonding pad disposed on a first surface of the first semiconductor chip facing the second semiconductor chip, a second bonding pad disposed on a second surface of the second semiconductor chip facing the first surface and in contact with the first bonding pad, and a molding film disposed on the package substrate and covering the first semiconductor chip and the second semiconductor chip, wherein the second bonding pad includes a third surface in contact with the first bonding pad and a fourth surface opposite to the third surface. the first semiconductor chip includes a first through electrode in contact with the first bonding pad and a first wiring structure connected to the first through electrode, the second semiconductor chip includes a first wiring pad in contact with the fourth surface of the second bonding pad, a second wiring structure including a second wiring pad spaced apart from the first wiring pad and not in contact with the second bonding pad, and a second through electrode connected to the second wiring structure, the first bonding pad and the second bonding pad include copper (Cu), the first wiring pad and the second wiring pad include aluminum (Al), and a thickness of the second wiring pad is 50% or less of a thickness of the first wiring pad. Effect of the Invention

[0007] According to the semiconductor package of the present invention, the thickness of the Al on which the Cu pad is formed is increased, and the thickness of the adjacent Al on which the Cu pad is not formed is decreased, and the thickness of the adjacent Al on which the Cu pad is not formed is made 50% or less of the thickness of the Al on which the Cu pad is formed, thereby reducing Cu-Cu bonding defects and providing a semiconductor package with improved product reliability. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view for explaining a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Diagram 2] FIG. 2 is an enlarged view showing a portion P in FIG. [Diagram 3] 1 for explaining a semiconductor package according to another embodiment of the present invention. FIG. [Figure 4] 1 for explaining a semiconductor package according to another embodiment of the present invention. FIG. [Diagram 5] 1 for explaining a semiconductor package according to another embodiment of the present invention. FIG. [Figure 6] 1 for explaining a semiconductor package according to another embodiment of the present invention. FIG. [Figure 7] 1 for explaining a semiconductor package according to another embodiment of the present invention. FIG. [Figure 8] 11 is a schematic cross-sectional view illustrating a schematic configuration of a semiconductor package according to still another embodiment of the present invention. [Figure 9] FIG. 9 is an enlarged view showing a portion Q in FIG. [Figure 10] 9 is an enlarged view of a portion Q of FIG. 8 for illustrating a semiconductor package according to still another embodiment of the present invention. [Figure 11] 11 is a schematic cross-sectional view illustrating a schematic configuration of a semiconductor package according to still another embodiment of the present invention. [Figure 12] 12 is an enlarged view showing a portion R in FIG. 11. FIG. [Figure 13] 11 is a schematic cross-sectional view illustrating a schematic configuration of a semiconductor package according to still another embodiment of the present invention. [Figure 14] 1A to 1C are schematic cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 15] 1A to 1C are schematic cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 16] 1A to 1C are schematic cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 17] 1A to 1C are schematic cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 18] 1A to 1C are schematic cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 19] 1A to 1C are schematic cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 20] 1A to 1C are schematic cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 21] 1A to 1C are schematic cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 22] 1A to 1C are schematic cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 23] 1A to 1C are schematic cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 24] 1A to 1C are schematic cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Diagram 25] 1A to 1C are schematic cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 26] 1A to 1C are schematic cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 27] 1A to 1C are schematic cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 28] 5A to 5C are schematic cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor package according to another embodiment of the present invention. [Figure 29] 5A to 5C are schematic cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor package according to another embodiment of the present invention. [Diagram 30]5A to 5C are schematic cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor package according to another embodiment of the present invention. [Diagram 31] 5A to 5C are schematic cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor package according to another embodiment of the present invention. [Diagram 32] 5A to 5C are schematic cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor package according to another embodiment of the present invention. [Diagram 33] 5A to 5C are schematic cross-sectional views illustrating intermediate steps in a method for manufacturing a semiconductor package according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Next, a specific example of an embodiment of a semiconductor package according to the present invention will be described with reference to the drawings.

[0010] FIG. 1 is a cross-sectional view for explaining a schematic configuration of a semiconductor package according to an embodiment of the present invention, and FIG. 2 is an enlarged view showing a portion P in FIG. 1 and 2, the semiconductor package includes first to fourth semiconductor chips (100 to 400), a package substrate 500, rear bonding pads (150, 250, 350, 450), front bonding pads (160, 260, 360), bonding insulating films (610, 620, 630), connection wiring pads (142, 242, 342, 442), peripheral wiring pads (144, 244, 344, 444), and a molding film 700.

[0011] The description relating to the rear bond pads (150, 250, 350, 450) is substantially similar to the description relating to the first rear bond pad 150 and the second rear bond pad 250. Therefore, the following description will focus on the first rear bonding pad 150 and the second rear bonding pad 250. The description relating to the front side bonding pads (160, 260, 360) and package bonding pad 560 is substantially similar to the description relating to the first front side bonding pad 160. Therefore, the following description will focus on the first front bonding pad 160. The description relating to the connection wiring pads (142, 242, 342, 442) is substantially similar to the description relating to the first connection wiring pad 142 and the second connection wiring pad 242. Therefore, the following description will focus on the first connection wiring pad 142 and the second connection wiring pad 242. The description relating to the peripheral interconnect pads (144, 244, 344, 444) is substantially similar to the description relating to the first peripheral interconnect pad 144 and the second peripheral interconnect pad 244. Therefore, the following description will focus on the first peripheral wiring pads 144 and the second peripheral wiring pads 244.

[0012] The first to fourth semiconductor chips (100 to 400) may be logic chips or memory chips. The first to fourth semiconductor chips (100 to 400) may all be the same type of memory chips. For example, the first to fourth semiconductor chips (100 to 400) may be volatile memory chips such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). As another example, the first to fourth semiconductor chips (100 to 400) may be non-volatile memory chips such as PRAM (Phase-change RAM), MRAM (Magnetoresistive RAM), FeRAM (Ferroelectric RAM), or RRAM (Resistive RAM). As another example, the first to fourth semiconductor chips (100 to 400) may be HBM (High Bandwidth Memory).

[0013] Also, some of the first to fourth semiconductor chips (100 to 400) may be memory chips, and the other may be logic chips. For example, some of the first to fourth semiconductor chips (100 to 400) may be a microprocessor, an analog element, a digital signal processor, or an application processor.

[0014] The first to fourth semiconductor chips (100 to 400) are stacked on a package substrate 500 in the vertical direction. The first to fourth semiconductor chips (100 to 400) are electrically connected to each other or to a package substrate 500 via rear bonding pads (150, 250, 350, 450) and front bonding pads (160, 260, 360). The first to fourth semiconductor chips (100 to 400) have the same width. The side surfaces of the first to fourth semiconductor chips (100 to 400) are arranged on the same plane.

[0015] The first semiconductor chip 100 includes a first semiconductor substrate 110, a first semiconductor element layer 120, a first through electrode 130, a first wiring structure 140, a first connection wiring pad 142, a first peripheral wiring pad 144, a first rear bonding pad 150, and a first front bonding pad 160. The first semiconductor substrate 110 can be, for example, bulk silicon or silicon-on-insulator (SOI). As another example, the first semiconductor substrate 110 can be a silicon substrate. As yet another example, the first semiconductor substrate 110 may include, but is not limited to, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The first semiconductor substrate 110 includes a conductive region, such as an impurity-doped well or impurity-doped structure. The first semiconductor substrate 110 has various isolation structures such as a shallow trench isolation (STI) structure.

[0016] The first semiconductor device layer 120 is disposed on the lower surface of the first semiconductor substrate 110 . The first semiconductor device layer 120 may include a variety of types of individual devices and an interlayer insulating film. The discrete elements may include various microelectronic devices, for example, metal-oxide-semiconductor field effect transistors (MOSFETs) such as complementary metal-insulator-semiconductor transistors (CMOS transistors), system large scale integration (LSIs), flash memory, image sensors such as DRAM, SRAM, EEPROM, PRAM, MRAM, RRAM, CIS (CMOS imaging sensor), MEMS (micro-electro-mechanical systems), active elements, passive elements, etc.

[0017] The discrete devices of the first semiconductor device layer 120 are electrically connected to conductive regions formed within the first semiconductor substrate 110 . The individual elements of the first semiconductor element layer 120 are electrically isolated from adjacent individual elements by insulating films. The first semiconductor device layer 120 includes a first wiring structure 140 that electrically connects at least two of the plurality of discrete devices, or a plurality of discrete devices, to a conductive region of the first semiconductor substrate 110 . The first semiconductor device layer 120 includes a first connection wiring pad 142 and a first peripheral wiring pad 144 . The first connection wiring pads 142 and the first peripheral wiring pads 144 are disposed in the first semiconductor element layer 120 .

[0018] The first connection wiring pads 142 and the first peripheral wiring pads 144 are spaced apart from each other. For example, the first connection wiring pad 142 and the first peripheral wiring pad 144 are spaced apart in the horizontal direction at the same level. For example, the first connection wiring pad 142 and the first peripheral wiring pad 144 are spaced apart from each other in the first direction X. The first connection wiring pad 142 connects the first wiring structure 140 and the first rear bonding pad 150 . The first connection wiring pad 142 contacts the first wiring structure 140 and the first back bonding pad 150 . The lower surface of the first connection wiring pad 142 contacts the upper surface of the first rear bonding pad 150 . The first connection wiring pad 142 electrically connects the first wiring structure 140 to the first rear bonding pad 150 .

[0019] The first peripheral wiring pad 144 is connected to the first wiring structure 140 . The first peripheral wiring pad 144 contacts the first wiring structure 140 . The first peripheral wiring pads 144 are not connected to the first rear bonding pads 150 . The first peripheral wiring pads 144 do not contact the first rear bonding pads 150 . The lower surface of the first peripheral wiring pad 144 is spaced apart from the upper surface of the first rear bonding pad 150 . The lower surface of the first peripheral wiring pad 144 is covered with the insulating film in the first semiconductor element layer 120 . The lower surface of the first peripheral wiring pad 144 is surrounded by an insulating film in the first semiconductor element layer 120 . The first connection wiring pads 142 and the first peripheral wiring pads 144 may include at least one of aluminum (Al) and copper (Cu). For example, the first connection wiring pad 142 and the first peripheral wiring pad 144 each include aluminum (Al). Although a case is shown in which the width of the first peripheral wiring pad 144 in the first direction X is smaller than the width of the first connection wiring pad 142, the embodiment is not limited thereto. For example, the width of the first peripheral wiring pad 144 may be greater than the width of the first connection wiring pad 142 .

[0020] A first passivation layer 121 is formed on the first semiconductor element layer 120 to protect the first wiring structure 140, the first connection wiring pad 142, the first peripheral wiring pad 144, and other structures in the first semiconductor element layer 120 from external impact and moisture. The first passivation layer 121 exposes a portion of the lower surface of the first connection wiring pad 142 . The first through-electrode 130 penetrates the first semiconductor substrate 110 . The first through-electrode 130 extends from the upper surface of the first semiconductor substrate 110 to the lower surface thereof. The first through electrode 130 is connected to a first wiring structure 140 provided in the first semiconductor element layer 120 . The first through electrode 130 includes a barrier film formed on the surface of the pillar shape and a buried conductive layer filling the inside of the barrier film.

[0021] The barrier film may include at least one of, but is not limited to, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB. The buried conductive layer may include at least one of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, Cu alloys such as CuW, W, W alloys, Ni, Ru, and Co, but is not limited thereto. In some embodiments, an insulating film may be interposed between the first semiconductor substrate 110 and the first through-electrode 130 . The insulating film may include, but is not limited to, an oxide, a nitride, a carbide, a polymer, or a combination thereof.

[0022] The first wiring structure 140 includes a metal wiring layer and a via plug. For example, the first wiring structure 140 may be a multi-layer structure in which two or more metal wiring layers or two or more via plugs are alternately stacked. The first wiring structure 140 is connected to a first connection wiring pad 142 and a first peripheral wiring pad 144 . The first wiring structure 140 contacts a first connection wiring pad 142 and a first peripheral wiring pad 144 .

[0023] A first backside bonding pad 150 is disposed on the first semiconductor device layer 120 . The first rear bonding pad 150 is electrically connected to the first wiring structure 140 inside the first semiconductor device layer 120 . The first rear bonding pad 150 is electrically connected to the first through electrode 130 via the first wiring structure 140 . The first rear bonding pad 150 is disposed on the first connection wiring pad 142 . The first rear bonding pad 150 is connected to the first connection wiring pad 142 . The first rear bonding pad 150 contacts the first connection wiring pad 142 . For example, the top surface of the first rear bonding pad 150 contacts the bottom surface of the first connection wiring pad 142 . The first rear bonding pad 150 is not connected to the first peripheral wiring pad 144 . The first rear bonding pad 150 does not contact the first peripheral wiring pad 144 . The first rear bonding pad 150 is spaced apart from the first peripheral wiring pad 144 . An upper surface of the first rear bonding pad 150 is spaced apart from a lower surface of the first peripheral wiring pad 144 .

[0024] The first rear bonding pad 150 is electrically connected to the package bonding pad 560 . The first back bond pad 150 contacts the package bond pad 560 . The first rear bonding pad 150 is bonded to a package bonding pad 560 . The first rear bonding pad 150 and the package bonding pad 560 are directly bonded. The first backside bond pad 150 and the package bond pad 560 may be bonded together by a high temperature annealing process. The first rear bonding pads 150 and the package bonding pads 560 are bonded to electrically connect the first semiconductor chip 100 to the package substrate 500 .

[0025] For example, when the first rear bonding pad 150 and the package bonding pad 560 are coupled, the first connection wiring pad 142 connected to the first rear bonding pad 150 and the first wiring structure 140 are electrically connected to the package bonding pad 560 of the package substrate 500. The first rear bonding pad 150 receives at least one of a control signal, a power signal, and a ground signal for operating the first to fourth semiconductor chips (100 to 400) from the outside. The first rear bonding pad 150 receives data signals to be stored in the first to fourth semiconductor chips (100 to 400) from the outside. The first rear bonding pad 150 provides data stored in the first to fourth semiconductor chips (100 to 400) to the outside. The first rear bonding pad 150 may include at least one selected from aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). In some embodiments, the first back bond pad 150 comprises copper (Cu).

[0026] A first front bonding pad 160 is formed on the top surface of the first semiconductor substrate 110 and is electrically connected to the first through-electrode 130 . The first front bonding pad 160 is electrically connected to the first wiring structure 140 via the first through electrode 130 . The first front bonding pad 160 is made of the same material as the first back bonding pad 150 . Although not shown in the drawing, an upper passivation layer is formed on the upper surface of the first semiconductor substrate 110 so as to surround a portion of the side surface of the first through-electrode 130 . The first front bonding pad 160 is connected to the second rear bonding pad 250 . The first front side bond pad 160 contacts the second back side bond pad 250 . For example, the second surface 160S2 of the first front side bond pad contacts the first surface 250S1 of the second back side bond pad.

[0027] The first front bonding pad 160 is bonded to the second back bonding pad 250 . The first front bonding pad 160 is directly bonded to the second rear bonding pad 250 . The first front side bonding pad 160 and the second back side bonding pad 250 are bonded together by a high temperature annealing process. The first front surface bonding pad 160 is disposed on the second surface 100S2 of the first semiconductor chip. The second surface (100S2) of the first semiconductor chip faces the second semiconductor chip (200). For example, the second surface 100S2 of the first semiconductor chip faces the first surface 200S1 of the second semiconductor chip. The first front bonding pad 160 is disposed within the first bonding insulating layer 610 .

[0028] The first front bonding pads 160 and the second rear bonding pads 250 are bonded to electrically connect the second semiconductor chip 200 to the first semiconductor chip 100 . For example, the first through-electrode 130 of the first semiconductor chip 100 and the second wiring structure 240 of the second semiconductor chip 200 are electrically connected via the bonded first front bonding pad 160 and second rear bonding pad 250 . The first front bonding pad 160 and the second back bonding pad 250 are surrounded by a first bonding insulating layer 610 . A side surface of the first front bonding pad 160 and a side surface of the second rear bonding pad 250 are covered with a first bonding insulating film 610 .

[0029] The first front side bonding pad 160 and the second back side bonding pad 250 are bonded with a bonding thickness THB. The bond thickness THB refers to the thickness between the first surface 160S1 of the first front side bond pad and the second surface 250S2 of the second back side bond pad. The first side 160S1 of the first front side bonding pad is the side where the first front side bonding pad 160 contacts the second side 100S2 of the first semiconductor chip. The second surface 250S2 of the second back bonding pad is the surface where the second back bonding pad 250 contacts the first surface 200S1 of the second semiconductor chip. The bonding thickness THB is smaller than the thickness TH242 of the second connection wiring pad. However, the embodiment is not limited to this. For example, the bonding thickness THB may be greater than the thickness TH242 of the second connection wiring pad.

[0030] The width of the first front side bonding pad 160 is the same as the width of the second back side bonding pad 250 . For example, a side surface of the first front bonding pad 160 and a side surface of the second rear bonding pad 250 are disposed on the same plane. The width of the first front bonding pad 160 is greater than the width of the first through-electrode 130 . The thickness of the first front side bonding pad 160 is the same as the thickness of the second back side bonding pad 250 . The thickness between the first surface 160S1 of the first front bonding pad and the second surface 160S2 of the first front bonding pad is the same as the thickness between the first surface 250S1 of the second rear bonding pad and the second surface 250S2 of the second rear bonding pad.

[0031] The second semiconductor chip 200 is disposed on the first semiconductor chip 100 . The second semiconductor chip 200 is electrically connected to the first semiconductor chip 100 via a first front bonding pad 160 and a second rear bonding pad 250 disposed between the first semiconductor chip 100 and the second semiconductor chip 200 . The second semiconductor chip 200 includes a second semiconductor substrate 210, a second semiconductor element layer 220, a second through electrode 230, a second wiring structure 240, a second connection wiring pad 242, a second peripheral wiring pad 244, a second rear bonding pad 250, and a second front bonding pad 260.

[0032] The second semiconductor device layer 220 includes a second connection wiring pad 242 and a second peripheral wiring pad 244 . The second connection wiring pads 242 and the second peripheral wiring pads 244 are disposed in the second semiconductor element layer 220 . The second connection wiring pads 242 and the second peripheral wiring pads 244 are spaced apart from each other. For example, the second connection wiring pad 242 and the second peripheral wiring pad 244 are spaced apart in the horizontal direction at the same level. For example, the second connection wiring pad 242 and the second peripheral wiring pad 244 are spaced apart from each other in the first direction X.

[0033] The second connection wiring pads 242 and the second peripheral wiring pads 244 have different thicknesses. The thickness TH242 of the second connection wiring pad is greater than the thickness TH244 of the second peripheral wiring pad. The thickness TH242 of the second connection wiring pad refers to the thickness between the first surface 242S1 and the second surface 242S2 of the second connection wiring pad. The thickness TH244 of the second peripheral wiring pad refers to the thickness between the first surface 244S1 and the second surface 244S2 of the second peripheral wiring pad. The thickness TH244 of the second peripheral wiring pad is, for example, 50% or less of the thickness TH242 of the second connection wiring pad. The thickness TH242 of the second connection wiring pad is greater than the bonding thickness THB where the second rear bonding pad 250 and the first front bonding pad 160 are bonded.

[0034] The second surface 242S2 of the second connection wiring pad and the second surface 244S2 of the second peripheral wiring pad are disposed on the same plane. The second surface 242S2 of the second connection wiring pad is the surface opposite to the first surface 242S1 of the second connection wiring pad. The first surface 242S1 of the second connection wiring pad is the surface that comes into contact with the second rear bonding pad 250. The first surface 242S1 of the second connection wiring pad faces the first semiconductor chip 100. The second wiring structure 240 contacts the second surface 242S2 of the second connection wiring pad. A second wiring structure 240 is connected to the second surface 242S2 of the second connection wiring pad. The second surface 244S2 of the second peripheral wiring pad is the surface opposite to the first surface 244S1 of the second peripheral wiring pad.

[0035] The first surface 244S1 of the second peripheral wiring pad faces the first semiconductor chip 100. The first surface 244S1 of the second peripheral wiring pad is covered with the second insulating film 225 in the second semiconductor element layer 220. The second wiring structure 240 contacts the second surface 244S2 of the second peripheral wiring pad. A second wiring structure 240 is connected to the second surface 244S2 of the second peripheral wiring pad. The first surface 242S1 of the second connection wiring pad and the first surface 244S1 of the second peripheral wiring pad are not disposed on the same plane. For example, with respect to the second surface 100S2 of the first semiconductor chip, the first surface 242S1 of the second connection wiring pads is disposed below the first surface 244S1 of the second peripheral wiring pads. The first surface 242S1 of the second connection wiring pad and the first surface 244S1 of the second peripheral wiring pad have a step.

[0036] The first surface 242S1 of the second connection wiring pad is not covered by the second insulating film 225 in the second semiconductor element layer 220. The first surface 242S1 of the second connection wiring pad does not overlap the second insulating film 225 in the second semiconductor element layer 220. For example, the second insulating film 225 is not disposed between the second connection wiring pad 242 and the second rear bonding pad 250 . The first surface 242S1 of the second connection wiring pad and the second surface 250S2 of the second rear bonding pad are in direct contact with each other. The second connection wiring pad 242 is surrounded by the second insulating film 225 in the second semiconductor element layer 220 only on its side surfaces. The first surface 244S1 of the second peripheral wiring pad is covered with the second insulating film 225 in the second semiconductor element layer 220. The first surface 244S1 of the second peripheral wiring pad overlaps the second insulating film 225 in the second semiconductor element layer 220. The second insulating film 225 is disposed between the second peripheral wiring pad 244 and the first bonding insulating film 610 . The second peripheral wiring pad 244 is surrounded by the second insulating film 225 in the second semiconductor element layer 220 not only on the side surfaces but also on the first surface 244S1.

[0037] A second rear bonding pad 250 is disposed on the second semiconductor device layer 220 . The second rear bonding pad 250 is electrically connected to a second wiring structure 240 within the second semiconductor device layer 220 . The second rear bonding pad 250 is electrically connected to the second through electrode 230 via the second wiring structure 240 . The second back surface bonding pads 250 are disposed on the first surface 200S1 of the second semiconductor chip. For example, the first surface 200S1 of the second semiconductor chip faces the second surface 100S2 of the first semiconductor chip. The second rear bonding pad 250 is disposed within the first bonding insulating layer 610 . The second rear bonding pad 250 is disposed on the second connection wiring pad 242 . The second rear bonding pad 250 is connected to the second connection wiring pad 242 . The second rear bonding pad 250 contacts the second connection wiring pad 242 . For example, the second surface 250S2 of the second rear bonding pad contacts the first surface 242S1 of the second connection wiring pad.

[0038] The second rear bonding pad 250 is not connected to the second peripheral wiring pad 244 . The second rear bonding pad 250 does not contact the second peripheral wiring pad 244 . The second rear bonding pad 250 is spaced apart from the second peripheral wiring pad 244 . The second surface 250S2 of the second rear bonding pad is spaced apart from the first surface 244S1 of the second peripheral wiring pad. The second back bonding pad 250 is electrically connected to the first front bonding pad 160 . The second back bond pad 250 contacts the first front bond pad 160 .

[0039] The second back bonding pad 250 is bonded to the first front bonding pad 160 . The second rear bonding pad 250 and the first front bonding pad 160 are directly bonded. The second backside bonding pad 250 and the first frontside bonding pad 160 are bonded together by a high temperature annealing process. The second rear bonding pads 250 and the first front bonding pads 160 are bonded to each other, so that the second semiconductor chip 200 is electrically connected to the first semiconductor chip 100 . For example, when the second rear bonding pad 250 comes into contact with the first front bonding pad 160, the second connection wiring pad 242 connected to the second rear bonding pad 250 and the second wiring structure 240 are electrically connected to the first through electrode 130 of the first semiconductor chip 100.

[0040] The third semiconductor chip 300 is disposed on the second semiconductor chip 200 . The third semiconductor chip 300 includes a third semiconductor substrate 310, a third semiconductor element layer 320, a third through electrode 330, a third wiring structure 340, a third connection wiring pad 342, a third peripheral wiring pad 344, a third rear bonding pad 350, and a third front bonding pad 360. The fourth semiconductor chip 400 is disposed on the third semiconductor chip 300 . The fourth semiconductor chip 400 includes a fourth semiconductor substrate 410 , a fourth semiconductor device layer 420 , a fourth wiring structure 440 , a fourth connection wiring pad 442 , a fourth peripheral wiring pad 444 , and a fourth rear bonding pad 450 . The fourth semiconductor chip 400 differs from the first to third semiconductor chips (100 to 300) in that it does not include through electrodes and front bonding pads. The second to fourth semiconductor chips (200 to 400) are substantially the same as or similar to the first semiconductor chip 100. Therefore, detailed explanations relating to the second to fourth semiconductor chips (200 to 400) will be omitted.

[0041] The package substrate 500 is, for example, a printed circuit board (PCB), a ceramic substrate, or an interposer. Alternatively, the package substrate 500 is a semiconductor chip including a semiconductor element. The package substrate 500 can function as a support substrate for a semiconductor package. For example, on a package substrate 500, the above-mentioned first to fourth semiconductor chips (100 to 400) are stacked. The package substrate 500 includes a substrate body 510 , a bottom surface pad 520 , and a package bonding pad 560 . The lower surface pads 520 are disposed on the lower surface of the substrate main body 510 . The package bonding pad 560 is disposed on the upper surface of the substrate body 510 . The package bonding pad 560 is disposed in the upper passivation film 511 . The upper passivation film 511 is disposed on the upper surface of the substrate body 510 . An external connection terminal 540 is disposed on the bottom of the package substrate 500 . The external connection terminals 540 are disposed on the lower surface pads 520 . For example, the external connection terminals 540 are solder balls or bumps.

[0042] The bonding insulating films (610, 620, 630) are disposed between the first to fourth semiconductor chips (100 to 400). The bonding insulating film (610, 620, 630) includes, for example, silicon oxide. The side surfaces of the bonding insulating films (610, 620, 630) are disposed on the same plane as the side surfaces of the first to fourth semiconductor chips (100 to 400). That is, in the first direction X, the width of the bonding insulating film (610, 620, 630) is the same as the width of the first to fourth semiconductor chips (100 to 400).

[0043] The first bonding insulating film 610 fills the gap between the first semiconductor chip 100 and the second semiconductor chip 200 . The first bonding insulating layer 610 includes a first front bonding pad 160 and a second rear bonding pad 250 disposed between the first semiconductor chip 100 and the second semiconductor chip 200 . The second bonding insulating film 620 fills the gap between the second semiconductor chip 200 and the third semiconductor chip 300 . The second bonding insulating layer 620 includes a second front bonding pad 260 and a third rear bonding pad 350 disposed between the second semiconductor chip 200 and the third semiconductor chip 300 . The third bonding insulating film 630 fills the gap between the third semiconductor chip 300 and the fourth semiconductor chip 400 . The third bonding insulating layer 630 includes a third front bonding pad 360 and a fourth rear bonding pad 450 disposed between the third semiconductor chip 300 and the fourth semiconductor chip 400 .

[0044] The molding film 700 is formed on the package substrate 500 . The molding film 700 covers the first to fourth semiconductor chips (100 to 400). The molding film 700 includes a polymer such as, for example, a resin. For example, the molding film 700 includes, but is not limited to, EMC (Epoxy Molding Compound).

[0045] 3 to 7 are enlarged views showing a portion P in FIG. 1 for explaining a semiconductor package according to another embodiment of the present invention. For convenience of explanation, the following will mainly describe the points that are different from those described with reference to FIGS. Referring to FIG. 3, the bonding thickness THB and the thickness TH242 of the second connection wiring pad are the same. The thickness between the first surface 160S1 of the first front bonding pad and the second surface 250S2 of the second back bonding pad is the same as the thickness TH242 of the second connection wiring pad.

[0046] Referring to FIG. 4, the width of the first front side bonding pad 160 is not constant. For example, the first front surface bond pad 160 has an inverted trapezoidal cross section. The width of the first surface 160S1 of the first front surface bonding pad is smaller than the width of the second surface 160S2 of the first front surface bonding pad. That is, the width of the first front bonding pad 160 increases from the first semiconductor chip 100 toward the second semiconductor chip 200 . The width of the second rear bonding pad 250 is not constant. For example, the second rear bond pad 250 has a trapezoidal cross-section. The width of the first side 250S1 of the second rear bond pad is greater than the width of the second side 250S2 of the second rear bond pad. That is, the width of the second rear bonding pad 250 decreases as it approaches the second semiconductor chip 200 from the first semiconductor chip 100 . The second side 160S2 of the first front side bond pad and the first side 250S1 of the second back side bond pad have the same width. The first side 160S1 of the first front side bonding pad and the second side 250S2 of the second back side bonding pad have the same width.

[0047] Referring to FIG. 5, the second side 160S2 of the first front side bonding pad and the first side 250S1 of the second back side bonding pad do not have the same width. For example, the width of the second surface 160S2 of the first front surface bond pad is greater than the width of the first surface 250S1 of the second back surface bond pad. The first side 160S1 of the first front side bonding pad and the second side 250S2 of the second back side bonding pad do not have the same width. For example, the width of the first surface 160S1 of the first front surface bond pad is greater than the width of the second surface 250S2 of the second back surface bond pad.

[0048] Referring to FIG. 6, the first front bonding pad 160 and the second rear bonding pad 250 are offset from each other. For example, the center of the first front bond pad 160 and the center of the second back bond pad 250 do not coincide but are offset.

[0049] Referring to FIG. 7, the thickness of the first front side bond pad 160 is not the same as the thickness of the second back side bond pad 250 . The thickness of the first front side bond pad 160 is less than the thickness of the second back side bond pad 250 . FIG. 7 illustrates only the case where the thickness of the first front side bonding pad 160 is smaller than the thickness of the second back side bonding pad 250, but the embodiment is not limited thereto. For example, the thickness of the first front side bond pad 160 may be greater than the thickness of the second back side bond pad 250 .

[0050] FIG. 8 is a schematic cross-sectional view for explaining a schematic configuration of a semiconductor package according to still another embodiment of the present invention, and FIG. 9 is an enlarged view showing a portion Q in FIG. For convenience of explanation, the following will mainly describe the points that are different from those described with reference to FIGS. 8 and 9, the semiconductor package according to the present embodiment includes a first semiconductor chip 100, a second semiconductor chip 200, and a molding film 700. As shown in FIG.

[0051] The second semiconductor chip 200 is disposed on the first semiconductor chip 100 . The width of the second semiconductor chip 200 is smaller than the width of the first semiconductor chip 100 . The side surfaces of the second semiconductor chip 200 are not disposed on the same plane as the side surfaces of the first semiconductor chip 100 . The molding film 700 covers the second semiconductor chip 200 . The molding film 700 covers the side surfaces of the second semiconductor chip 200 . The first semiconductor device layer 120 is disposed on an upper surface of the first semiconductor substrate 110 . The first semiconductor element layer 120 includes a fifth connection wiring pad 182 . The fifth connection wiring pad 182 is disposed in the first semiconductor element layer 120.

[0052] A first front surface bonding pad 160 is disposed on the first semiconductor device layer 120 . The first front bonding pad 160 is electrically connected to the first wiring structure 140 . The first front bonding pad 160 is disposed on the fifth connection wiring pad 182 . The first front bonding pad 160 contacts the fifth connection wiring pad 182 . The fifth connection wiring pad 182 is connected to the first wiring structure 140 and the first front bonding pad 160 . The fifth connection wiring pad 182 contacts the first wiring structure 140 and the first front surface bonding pad 160 . The first surface 182S1 of the fifth connection wiring pad contacts the first wiring structure 140. The fifth connection wiring pad 182 electrically connects the first wiring structure 140 to the first front surface bonding pad 160 . The second surface 182S2 of the fifth connection wiring pad contacts the first surface 160S1 of the first front bonding pad.

[0053] The fifth connection wiring pad 182 is surrounded by the first insulating film 125 in the first semiconductor element layer 120. The side surface of the fifth connection wiring pad 182 is surrounded by the first insulating film 125 in the first semiconductor element layer 120 . The first surface 182S1 and the second surface 182S2 of the fifth connection wiring pad 182 are not covered by the first insulating film 125. The first surface 182S1 and the second surface 182S2 of the fifth connection wiring pad 182 do not overlap the first insulating film 125. The fifth connection wiring pad 182 includes aluminum. The first front bonding pad 160 is disposed between the fifth connection wiring pad 182 and the first rear bonding pad 250 . The first rear bonding pad 250 is disposed between the first front bonding pad 160 and the second connection wiring pad 242 .

[0054] FIG. 10 is an enlarged view of a portion Q of FIG. 8 for illustrating a semiconductor package according to still another embodiment of the present invention. For convenience of explanation, the following will mainly describe points that are different from those described with reference to FIGS. Referring to FIG. 10, the first semiconductor chip 100 includes a fifth peripheral wiring pad 184 .

[0055] The fifth peripheral wiring pad 184 is spaced apart from the fifth connection wiring pad 182 . For example, the fifth peripheral wiring pad 184 is spaced apart from the fifth connection wiring pad 182 in the first direction X. The fifth peripheral wiring pad 184 does not contact the first front surface bonding pad 160 . The fifth peripheral wiring pad 184 is spaced apart from the first front bonding pad 160 . The first front surface bonding pad 160 is not disposed on the fifth peripheral wiring pad 184 . The fifth connection wiring pad 182 and the fifth peripheral wiring pad 184 have different thicknesses. The thickness TH182 of the fifth connection wiring pad is greater than the thickness TH184 of the fifth peripheral wiring pad. The thickness TH184 of the fifth peripheral wiring pad is, for example, 50% or less of the thickness TH182 of the fifth connection wiring pad.

[0056] The first surface 182S1 of the fifth connection wiring pad and the first surface 184S1 of the fifth peripheral wiring pad are disposed on the same plane. The first surface 182S1 of the fifth connection wiring pad is the surface where the first wiring structure 140 contacts the fifth connection wiring pad 182. The first surface 184S1 of the fifth peripheral wiring pad is the surface where the first wiring structure 140 contacts the fifth peripheral wiring pad 184. The second surface 182S2 of the fifth connection wiring pad and the second surface 184S2 of the fifth peripheral wiring pad are not disposed on the same plane. For example, with the second surface 100S2 of the first semiconductor chip as a reference, the second surface 182S2 of the fifth connection wiring pad is disposed higher than the second surface 184S2 of the fifth peripheral wiring pad. The second surface 182S2 of the fifth connection wiring pad and the second surface 184S2 of the fifth peripheral wiring pad have a step.

[0057] The second surface 182S2 of the fifth connection wiring pad is the surface opposite to the first surface 182S1 of the fifth connection wiring pad. The second surface 182S2 of the fifth connection wiring pad is the surface that comes into contact with the first front surface bonding pad 160. The second surface 182S2 of the fifth connection wiring pad faces the second semiconductor chip 200. The second surface 184S2 of the fifth peripheral wiring pad is the surface opposite to the first surface 184S1 of the fifth peripheral wiring pad. The second surface 184S2 of the fifth peripheral wiring pad faces the second semiconductor chip 200. The second surface 184S2 of the fifth peripheral wiring pad is covered with the first insulating film 125 in the first semiconductor element layer 120.

[0058] Although FIG. 10 illustrates a case where the thickness TH182 of the fifth connection wiring pad is the same as the thickness TH242 of the second connection wiring pad, the embodiment is not limited thereto. For example, the thickness TH182 of the fifth connection wiring pad is smaller than the thickness TH242 of the second connection wiring pad. In FIG. 10, the thickness TH184 of the fifth peripheral wiring pad is the same as the thickness TH244 of the second peripheral wiring pad, but the embodiment is not limited to this. For example, the thickness TH184 of the fifth peripheral wiring pad may be smaller than the thickness TH244 of the second peripheral wiring pad.

[0059] FIG. 11 is a schematic cross-sectional view for explaining a schematic configuration of a semiconductor package according to still another embodiment of the present invention, and FIG. 12 is an enlarged view showing a portion R in FIG. For convenience of explanation, the following will mainly describe the points that are different from those described with reference to FIGS. 11 and 12, the semiconductor package according to the present embodiment includes a package substrate 500, a first semiconductor chip 100, a second semiconductor chip 200, and an interposer 800.

[0060] The package substrate 500 is mounted on a main board of an electronic device. For example, the package substrate 500 is mounted on a main board of an electronic device via an external connection terminal 540 . The package substrate 500 is a BGA (Ball Grid Array) substrate, but is not limited to this. The external connection terminals 540 are, for example, solder bumps, but are not limited to this. The external connection terminal 540 may have various shapes such as a land, a ball, a pin, a pillar, and the like. The number, intervals, arrangement, and the like of the external connection terminals 540 are not limited to those shown in the figure, and may of course be variously changed according to design.

[0061] The interposer 800 is disposed on the upper surface of the package substrate 500 . Interposer 800 may be, but is not limited to, a silicon interposer or an organic interposer. Interposer 800 includes opposing bottom and top surfaces. The lower surface of the interposer 800 faces the upper surface of the package substrate 500 . The interposer 800 is used to facilitate connection between the package substrate 500 and the first and second semiconductor chips 100 and 200, and to reduce warpage of the semiconductor package. Interposer 800 includes an interposer substrate 810 , interposer backside bond pads 850 , and interposer frontside bond pads 860 .

[0062] Interposer backside bond pads 850 and interposer frontside bond pads 860 are each used to electrically connect interposer 800 to other components. For example, interposer rear bond pads 850 are exposed from the bottom surface of interposer substrate 810 . Interposer front surface bond pads 860 are exposed from the top surface of interposer substrate 810 . The interposer backside bond pads 850 and the interposer frontside bond pads 860 may include, but are not limited to, a metallic material such as copper (Cu) or aluminum (Al). Interposer backside bond pads 850 contact package bond pads 560 . The interposer backside bond pads 850 are directly bonded to the package bond pads 560 . The interposer back surface bond pads 850 are electrically connected to the package bond pads 560 . The interposer rear bonding pads 850 and the package bonding pads 560 are bonded to electrically connect the interposer 800 and the package substrate 500 .

[0063] The interposer front side bond pad 860 contacts the first back side bond pad 150 and the second back side bond pad 250 . The interposer front surface bond pad 860 is directly bonded to the first rear surface bond pad 150 and the second rear surface bond pad 250 . The interposer front surface bond pad 860 is electrically connected to the first rear surface bond pad 150 and the second rear surface bond pad 250 . The interposer front surface bonding pads 860 and the first rear surface bonding pads 150 are bonded to electrically connect the first semiconductor chip 100 and the interposer 800 . The interposer front surface bonding pads 860 and the second rear surface bonding pads 250 are bonded to electrically connect the second semiconductor chip 200 and the interposer 800 .

[0064] The first semiconductor chip 100 and the second semiconductor chip 200 are mounted on the upper surface of the interposer 800 . The first semiconductor chip 100 and the second semiconductor chip 200 are disposed on the upper surface of the interposer 800 and spaced apart from each other. Each of the first semiconductor chip 100 and the second semiconductor chip 200 may be an integrated circuit (IC) in which hundreds to millions of semiconductor elements are integrated into one chip. In some embodiments, the first semiconductor chip 100 is a logic semiconductor chip. For example, the first semiconductor chip 100 may be an application processor (AP) such as a CPU (Central Processing Unit), a GPU (Graphic Processing Unit), an FPGA (Field-Programmable Gate Array), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an ASIC (Application-Specific IC), but is not limited thereto.

[0065] In some embodiments, the second semiconductor chip 200 may be a memory semiconductor chip. For example, the second semiconductor chip 200 may be a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or may be a non-volatile memory such as a flash memory, a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). As an example, the first semiconductor chip 100 is an ASIC such as a GPU, and the second semiconductor chip 200 is a stacked memory such as a High Bandwidth Memory (HBM). Such a stack memory is a memory in which multiple integrated circuits are stacked. The stacked integrated circuits are electrically connected to each other via TSVs (Through Silicon Vias) or the like.

[0066] In some embodiments, the second semiconductor chips 200 are arranged in greater numbers than the first semiconductor chips 100 . For example, a plurality of second semiconductor chips 200 are arranged around the first semiconductor chip 100 . For example, two second semiconductor chips 200 are arranged on each side of the first semiconductor chip 100. The first semiconductor chip 100 includes a first backside bonding pad 150 . The first back bonding pads 150 are used to electrically connect the first semiconductor chip 100 to other components. For example, the first rear bonding pad 150 is exposed from the bottom surface of the first semiconductor chip 100 . The first back bond pad 150 contacts the interposer front bond pad 860 . The first back bond pad 150 is disposed on the interposer front bond pad 860 . The first backside bond pad 150 is bonded to the interposer frontside bond pad 860 . As a result, the first semiconductor chip 100 is electrically connected to the interposer 800.

[0067] The second semiconductor chip 200 includes a second backside bonding pad 250 . The second rear bonding pads 250 are used to electrically connect the second semiconductor chip 200 to other components. For example, the second rear bonding pads 250 are exposed from the bottom surface of the second semiconductor chip 200 . The second back bond pad 250 contacts the interposer front bond pad 860 . The second back bond pad 250 is disposed on the interposer front bond pad 860 . The second backside bond pad 250 is bonded to the interposer frontside bond pad 860 . As a result, the second semiconductor chip 200 is electrically connected to the interposer 800. The first back bonding pad 150 and the second back bonding pad 250 may each include a metallic material such as, but not limited to, copper (Cu) or aluminum (Al). In some embodiments, the first back bond pad 150 and the second back bond pad 250 each comprise copper (Cu).

[0068] The package substrate 500 includes a sixth connection wiring pad 582 and a sixth peripheral wiring pad 584 . The sixth connection wiring pads 582 and the sixth peripheral wiring pads 584 are connected to the package substrate wiring 530 . The sixth connection wiring pad 582 and the sixth peripheral wiring pad 584 are spaced apart from each other. The sixth connection wiring pad 582 is connected to the package bonding pad 560 . The sixth connection wiring pad 582 contacts the package bonding pad 560 . The sixth connection wiring pad 582 is disposed on the package bonding pad 560 . The upper surface of the sixth connection wiring pad 582 contacts the lower surface of the package bonding pad 560 . The sixth connection wiring pad 582 electrically connects the package substrate wiring 530 and the package bonding pad 560 .

[0069] The sixth peripheral wiring pad 584 is not connected to the package bonding pad 560 . The sixth peripheral wiring pad 584 does not contact the package bonding pad 560 . The top surface of the sixth peripheral wiring pad 584 does not contact the bottom surface of the package bonding pad 560 . The sixth peripheral wiring pad 584 is spaced apart from the package bonding pad 560 . The upper surface of the sixth peripheral wiring pad 584 is spaced apart from the lower surface of the package bonding pad 560 . The thickness of the sixth connection wiring pad 582 is greater than the thickness of the sixth peripheral wiring pad 584 . The lower surface of the sixth connection wiring pad 582 is disposed on the same plane as the lower surface of the sixth peripheral wiring pad 584 . With the lower surface of the package substrate 500 as a reference, the upper surface of the sixth connection wiring pad 582 is disposed higher than the upper surface of the sixth peripheral wiring pad 584 . The upper surface of the sixth connection wiring pad 582 and the upper surface of the sixth peripheral wiring pad 584 have a step.

[0070] FIG. 13 is a schematic cross-sectional view illustrating a schematic configuration of a semiconductor package according to still another embodiment of the present invention. For convenience of explanation, the following will mainly describe the points that are different from those described with reference to FIGS. 13, the semiconductor package according to the present embodiment includes a fifth semiconductor chip 20. As shown in FIG.

[0071] Fifth semiconductor chip 20 is separated from the stacked first to fourth semiconductor chips (100 to 400). The fifth semiconductor chip 20 is disposed on the interposer 800 . The fifth semiconductor chip 20 is separated from the first to fourth semiconductor chips (100 to 400) stacked on the interposer 800. The fifth semiconductor chip 20 is covered with a molding film 700 . The side surfaces of the fifth semiconductor chip 20 are covered with a molding film 700 . The fifth semiconductor chip 20 includes a fifth rear bonding pad 25, a seventh connection wiring pad 42, and a seventh peripheral wiring pad 44.

[0072] The fifth rear bonding pad 25 is connected to the seventh connection wiring pad 42 . The fifth rear bonding pad 25 contacts the seventh connection wiring pad 42 . The fifth rear bonding pad 25 is not connected to the seventh peripheral wiring pad 44 . The fifth rear bonding pad 25 does not contact the seventh peripheral wiring pad 44 . The fifth back bond pad 25 contacts the interposer front bond pad 860 . The fifth rear bond pad 25 is bonded to the interposer front bond pad 860 . The fifth rear bonding pads 25 and the interposer front bonding pads 860 are bonded to electrically connect the fifth semiconductor chip 20 and the interposer 800 .

[0073] The interposer front surface bonding pads 860 are connected to the interposer wiring 840 . The interposer front surface bond pad 860 is connected to the fifth rear surface bond pad 25 and the first rear surface bond pad 150 . The interposer front surface bond pad 860 contacts the fifth back surface bond pad 25 and the first back surface bond pad 150 . A connection bump 870 is disposed between the interposer back surface bond pad 850 and the package bond pad 560 . However, the embodiment is not limited to this. For example, interposer back surface bond pad 850 and package bond pad 560 may be in direct contact.

[0074] 14 to 27 are schematic cross-sectional views showing intermediate stages for explaining a method for manufacturing a semiconductor package according to an embodiment of the present invention. Referring to FIG. 14, a first semiconductor device layer 120 is formed on a first semiconductor substrate 110 . A first through electrode 130 is formed in the first semiconductor substrate 110 . A first wiring structure 140 connected to the first through electrode 130 is formed in the first semiconductor element layer 120 .

[0075] 15 and 16, a first portion 142P1 of a first connection wiring pad and a first peripheral wiring pad 144 are formed. The first portion 142P1 of the first connection wiring pad and the first peripheral wiring pad 144 are formed in the first portion 125a of the first insulating film of the first semiconductor element layer 120. The first portion 125a of the first insulating film is formed on the first wiring structure 140. The first portion 142P1 of the first connection wiring pad and the first peripheral wiring pad 144 are connected to the first wiring structure 140. The first portion 142P1 of the first connection wiring pad and the first peripheral wiring pad 144 have the same thickness. The first surface 142PS1 of the first portion 142P1 of the first connection wiring pad and the first surface 144S1 of the first peripheral wiring pad are disposed on the same plane.

[0076] Referring to FIG. 17, a first connection wiring pad 142 is formed in the first insulating film 125 . Specifically, referring to FIG. 18, the second portion 125b of the first insulating film is formed on the first portion 142P1 of the first connection wiring pad and the first peripheral wiring pad 144. A first connection wiring pad recess 142R is formed which penetrates the second portion 125b of the first insulating film and exposes the first portion 142P1 of the first connection wiring pad. A first surface 142PS1 of a first portion 142P1 of the first connection wiring pad is exposed in the first connection wiring pad recess 142R. The first surface 144S1 of the first peripheral wiring pad is covered with the second portion 125b of the first insulating film.

[0077] Next, referring to FIG. 19, the second portion 142P2 of the first connection wiring pad is formed in the first connection wiring pad recess (142R in FIG. 18). The second portion 142P2 of the first connection wiring pad fills the first connection wiring pad recess (142R in FIG. 18). The second portion 142P2 of the first connection wiring pad is formed on the first portion 142P1 of the first connection wiring pad. The second portion 142P2 of the first connection wiring pad covers the first surface (142PS1 in FIG. 18) of the first portion 142P1 of the first connection wiring pad.

[0078] Next, referring to Figure 20, the second portion (142P2 in Figure 19) of the first connection wiring pad covering the upper surface of the second portion (125b in Figure 19) of the first insulating film is removed to form the first connection wiring pad 142 and the first peripheral wiring pad 144. The first surface 142PS1 of the first connection wiring pad is exposed from the first insulating film 125. The first surface 144S1 of the first peripheral wiring pad is covered with a first insulating film 125. The first insulating film 125 includes a first portion (125a in FIG. 19) and a second portion (125b in FIG. 19).

[0079] 21 and 22, a first rear bonding pad 150 is formed. A first rear bonding pad 150 is formed on the first connection wiring pad 142 . The first rear bonding pad 150 contacts the first connection wiring pad 142 . A first passivation layer 121 is formed on the first insulating film 125 . The first passivation layer 121 covers the first insulating film 125 . A first back bond pad 150 is formed in the first passivation layer 121 .

[0080] 23 and 24, the first semiconductor chip 100 is bonded onto a package substrate 500. As shown in FIG. After the first semiconductor chip 100 is bonded onto the package substrate 500, an annealing process is performed. For example, when the first semiconductor chip 100 is bonded onto the package substrate 500, heat is applied. When annealed, the first rear bond pad 150 expands. For example, the first surface 150S1 of the first back bonding pad protrudes beyond the first surface 121S1 of the first passivation layer. The first rear bonding pad 150 disposed on the first connection wiring pad 142 having a thickness greater than that of the first peripheral wiring pad 144 protrudes more than the first passivation layer 121 .

[0081] For example, the first connection wiring pad 142 also expands due to annealing. Therefore, the first back bonding pad 150 disposed on the first connection wiring pad 142 expands relatively more than the first passivation layer 121 . The first passivation layer 121 covering the first peripheral wiring pads 144 , which are thinner than the first connection wiring pads 142 , is less likely to expand than the first rear bonding pads 150 . For example, the first peripheral wiring pad 144 also expands due to annealing, but the first passivation layer 121 that is not in direct contact with the first peripheral wiring pad 144 and has a smaller thickness expands less than the first rear bonding pad 150 . Since the first insulating film 125 is disposed on the first peripheral wiring pad 144 , the expansion of the first peripheral wiring pad 144 due to annealing does not affect the first passivation layer 121 .

[0082] Referring to FIG. 25, the first rear bonding pad 150 and the package bonding pad 560 are bonded. The first rear bonding pad 150 expands relatively more than the first passivation layer 121, so that the first rear bonding pad 150 and the package bonding pad 560 are stably bonded to each other. On the other hand, for example, referring to FIG. 24, when the first surface 144S1 of the first peripheral wiring pad is positioned on the same plane as the first surface 142PS1 of the first connection wiring pad, the first peripheral wiring pad 144 expands due to annealing, causing the first passivation layer 121 to also expand. In this case, the first surface 150S1 of the first rear bonding pad protrudes less than the first surface 121S1 of the first passivation layer, and the first rear bonding pad 150 is not stably bonded to the package bonding pad 560. With respect to the first surface 121S1 of the first passivation layer as a reference, the first surface 144S1 of the first peripheral wiring pad is positioned higher than the first surface 142PS1 of the first connection wiring pad, so that even if the first peripheral wiring pad 144 expands due to annealing, the degree of expansion of the first passivation layer 121 due to the expansion of the first peripheral wiring pad 144 is reduced. Therefore, the first surface 150S1 of the first rear bonding pad protrudes relatively more than the first surface 121S1 of the first passivation layer, so that the first rear bonding pad 150 is stably bonded to the package bonding pad 560.

[0083] Referring to FIG. 26, a second semiconductor chip 200 is bonded onto a first semiconductor chip 100 . A first front bonding pad 160 is formed in a first portion 610 a of a first bonding insulating film disposed on the top surface of the first semiconductor chip 100 . A second rear bonding pad 250 is formed in the second portion 610 b of the first bonding insulating film disposed on the bottom surface of the second semiconductor chip 200 . The first semiconductor chip 100 and the second semiconductor chip 200 are bonded together by directly contacting the first front bonding pad 160 and the second rear bonding pad 250 . Similarly, when the first semiconductor chip 100 and the second semiconductor chip 200 are bonded, annealing is performed. The second rear bonding pad 250 disposed on the second connection wiring pad 242 having a thickness greater than that of the second peripheral wiring pad 244 protrudes relatively more than the second portion 610b of the first bonding insulating film due to annealing. Therefore, the second rear bonding pad 250 is stably bonded to the first front bonding pad 160 .

[0084] Referring to FIG. 27, a third semiconductor chip 300 and a fourth semiconductor chip 400 are bonded onto a second semiconductor chip 200 . Next, referring to FIG. 1, a molding film 700 is formed to cover the first to fourth semiconductor chips (100 to 400).

[0085] 28 to 33 are schematic cross-sectional views showing intermediate stages for illustrating a method for manufacturing a semiconductor package according to another embodiment of the present invention. For the sake of convenience, the following description will focus on the differences from the contents described with reference to FIGS. For reference, FIG. 28 is a schematic cross-sectional view showing a stage subsequent to that shown in FIG.

[0086] 14, 28 and 29, the first connection wiring pads 142 and the first pre-peripheral wiring pads 144P are formed. The first connection wiring pads 142 and the first pre-peripheral wiring pads 144P are formed in the first insulating film 125 of the first semiconductor element layer 120. The first connection wiring pad 142 and the first pre-peripheral wiring pad 144P are connected to the first wiring structure 140. The first connection wiring pads 142 and the first pre-peripheral wiring pads 144P have the same thickness. The first surface 142PS1 of the first connection wiring pad and the first surface 144PS1 of the first pre-peripheral wiring pad are disposed on the same plane.

[0087] Referring to FIG. 30, a first peripheral wiring pad 144 is formed in the first insulating film 125 . Specifically, referring to FIG. 31, a mask layer 129 is formed on a first insulating film 125 . The mask layer 129 covers the first connection wiring pads 142 . A first peripheral wiring pad trench 144T is formed through the mask layer 129 to expose the first pre-peripheral wiring pad 144P. A first surface 144PS1 of the first pre-peripheral wiring pad is exposed in the first peripheral wiring pad trench 144T. The first surface 142PS1 of the first connection wiring pad is covered with a mask layer 129.

[0088] Next, referring to FIG. 32, the upper portion of the first pre-peripheral wiring pad (144P in FIG. 31) is removed in the first peripheral wiring pad trench 144T. For example, the top of the first pre-peripheral wiring pad (144P in FIG. 31) is etched in the first peripheral wiring pad trench 144T. The upper portion of the first pre-peripheral wiring pad (144P in FIG. 31) is removed to form the first peripheral wiring pad 144. With the first semiconductor substrate 110 as a reference, the first surface 144S1 of the first peripheral wiring pad is disposed below the first surface 142PS1 of the first connection wiring pad.

[0089] Next, referring to FIG. 33, a first insulating film 125 is formed in the first peripheral wiring pad trench 144T. The first insulating film 125 fills the first peripheral wiring pad trench 144T. The first insulating film 125 covers the first surface 144S1 of the first peripheral wiring pad in the first peripheral wiring pad trench 144T. The description of the steps following FIG. 33 is omitted since it is similar to the description of FIG. 21 to FIG.

[0090] Although this specification contains many details of specific embodiments, this should not be interpreted as a limitation on the scope or scope of the invention, but rather as a description of features specific to particular implementations of a particular invention. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. In addition, even if features of an invention have been described as acting in a particular combination, and even if a claim is initially drafted in such a combination, one or more features from the combination in the claims may, in some cases, be excluded from the combination, and the combination in the claims may be practiced as a subcombination or a variation of the subcombination.

[0091] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0092] 100, 200, 300, 400 (1st to 4th) Semiconductor chips 110, 210, 310, 410 (1st to 4th) semiconductor substrate 120, 220, 320, 420 (1st to 4th) semiconductor element layers 121 First passivation layer 130, 230, 330 (1st to 3rd) through electrode 140, 240, 340, 440 (1st to 4th) wiring structure 142, 242, 342, 442 (1st to 4th) connection wiring pads 144, 244, 344, 444 (1st to 4th) peripheral wiring pads 150, 250, 350, 450 (1st to 4th) Rear bonding pads 160, 260, 360 (1st to 3rd) front bonding pads 225 Second insulating film 500 Package Substrate 510 Board main body 511 Upper passivation film 520 Bottom Pad 540 External connection terminal 560 Package Bonding Pad 610, 620, 630 Bonding insulating film 700 Molding Film

Claims

1. A first semiconductor chip; a second semiconductor chip on the first semiconductor chip; a first bonding pad disposed on a first surface of the first semiconductor chip facing the second semiconductor chip; a second bonding pad disposed on a second surface of the second semiconductor chip opposite the first surface and in contact with the first bonding pad; The second bonding pad is a third surface in contact with the first bonding pad; a fourth surface opposite the third surface; The second semiconductor chip is a first wiring pad in contact with the fourth surface of the second bonding pad; a second wiring pad spaced apart from the first wiring pad and the second bonding pad, A semiconductor package, wherein the thickness of the second wiring pad is smaller than the thickness of the first wiring pad.

2. 2. The semiconductor package according to claim 1, wherein the thickness of the second wiring pad is 50% or less of the thickness of the first wiring pad.

3. 2. The semiconductor package according to claim 1, further comprising a bonding insulating film disposed between the first semiconductor chip and the second semiconductor chip and surrounding the first bonding pad and the second bonding pad.

4. 4. The semiconductor package according to claim 3, wherein a side surface of the bonding insulating film is disposed on the same plane as a side surface of the second semiconductor chip.

5. The first wiring pad is a fifth surface in contact with the fourth surface; and a sixth surface opposite the fifth surface; The second wiring pad is a seventh surface facing the first semiconductor chip; an eighth surface opposite the seventh surface; The semiconductor package according to claim 1 , wherein the sixth surface and the eighth surface are disposed on the same plane.

6. the second semiconductor chip further includes an insulating film surrounding the first wiring pad and the second wiring pad; the insulating film covers a side surface of the first wiring pad and does not overlap the fifth surface and the sixth surface; 6. The semiconductor package according to claim 5, wherein the insulating film covers the side surfaces of the second wiring pads and the seventh surface, and does not overlap the eighth surface.

7. The second semiconductor chip is a wiring structure connected to the first wiring pad and the second wiring pad; a semiconductor substrate disposed on the wiring structure; The semiconductor package according to claim 1 , further comprising a through electrode penetrating the semiconductor substrate and connected to the wiring structure.

8. the first bonding pad and the second bonding pad include copper (Cu); 2. The semiconductor package according to claim 1, wherein the first wiring pad and the second wiring pad include aluminum (Al).

9. 2. The semiconductor package of claim 1, wherein a width of the first bonding pad increases as the first bonding pad approaches the second bonding pad in one direction.

10. 2. The semiconductor package of claim 1, wherein the width of the first bonding pad is greater than the width of the second bonding pad.

11. a package substrate disposed under the first semiconductor chip; 2. The semiconductor package according to claim 1, further comprising: a molding film disposed on the package substrate and covering the first semiconductor chip and the second semiconductor chip.

12. A first semiconductor chip; a second semiconductor chip on the first semiconductor chip; a first bonding pad disposed on a first surface of the first semiconductor chip facing the second semiconductor chip; a second bonding pad disposed on a second surface of the second semiconductor chip opposite the first surface and in contact with the first bonding pad; The second semiconductor chip is a first wiring pad in contact with the second bonding pad; a second wiring pad spaced apart from the first wiring pad and not in contact with the second bonding pad; The first wiring pad is a third surface in contact with the second bonding pad; a fourth surface opposite the third surface; The second wiring pad is a fifth surface facing the first semiconductor chip; a sixth surface opposite the fifth surface; the fourth surface and the sixth surface are disposed on the same plane, A semiconductor package, characterized in that, with respect to the first surface of the first semiconductor chip, the third surface is located below the fifth surface.

13. 13. The semiconductor package of claim 12, wherein a first thickness between the fifth surface and the sixth surface is less than or equal to 50% of a second thickness between the third surface and the fourth surface.

14. the second semiconductor chip further includes an insulating film surrounding a side surface of the first wiring pad, the insulating film does not overlap the third surface of the first wiring pad; The semiconductor package according to claim 12 , wherein the insulating film overlaps the fifth surface of the second wiring pad.

15. the first bonding pad and the second bonding pad include copper; 13. The semiconductor package of claim 12, wherein the first wiring pad and the second wiring pad include aluminum.

16. The semiconductor package of claim 12 , wherein the first semiconductor chip includes a through electrode connected to the first bonding pad.

17. The semiconductor package of claim 16 , wherein the width of the through electrode is smaller than the width of the first bonding pad.

18. 13. The semiconductor package of claim 12, wherein the width of the first wiring pad is greater than the width of the second bonding pad.

19. the second semiconductor chip further includes an insulating film surrounding a side surface of the first wiring pad and a side surface of the second wiring pad; The semiconductor package according to claim 12 , wherein the insulating film is not disposed between the second bonding pad and the first wiring pad.

20. A package substrate; a first semiconductor chip on the package substrate; a second semiconductor chip on the first semiconductor chip; a first bonding pad disposed on a first surface of the first semiconductor chip facing the second semiconductor chip; a second bonding pad disposed on a second surface of the second semiconductor chip opposite the first surface and in contact with the first bonding pad; a molding film disposed on the package substrate and covering the first semiconductor chip and the second semiconductor chip; The second bonding pad is a third surface in contact with the first bonding pad; a fourth surface opposite the third surface; The first semiconductor chip is a first through electrode in contact with the first bonding pad; a first wiring structure connected to the first through electrode, The second semiconductor chip is a first wiring pad in contact with the fourth surface of the second bonding pad; a second wiring structure including a second wiring pad spaced apart from the first wiring pad and not in contact with the second bonding pad; a second through electrode connected to the second wiring structure, the first bonding pad and the second bonding pad include copper (Cu); the first wiring pad and the second wiring pad contain aluminum (Al); 2. A semiconductor package comprising: a first wiring pad and a second wiring pad;

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