Semiconductor device

Abstract

To reduce influence of an inductance.SOLUTION: A semiconductor device 1 comprises: a first inverter circuit, a second inverter circuit and a third inverter circuit that include a first switching element 11 and a second switching element 12 and are connected to each other in parallel; a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer; an integrated circuit element 25H; and a sealing resin 50. A center of at least one second switching element 12 of centers of a plurality of second switching elements 12 is implemented by being apart from in a second direction. In a third side surface 50E, a recessed part 51 is provided in a portion between first terminal parts 33g being adjacent in a direction in which the third side surface 50E of a plurality of first terminal parts 33g extends. In a plan view, magnitude of a direction, in which the third side surface 50E extends, in the recessed part 51 is larger than magnitude of a direction being orthogonal to the direction, in which the third side surface 50E extends, in the recessed part 51.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] A semiconductor device has been developed that is integrated into a single package by mounting an inverter circuit having a first switching element supplied with a power supply voltage and a second switching element connected in series with the first switching element, and a control circuit that controls the on / off of each switching element on a lead frame (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-82281 A

[0004] [overview] In the semiconductor device, the control terminal of the second switching element and the control circuit are electrically connected by a bonding wire, and as the bonding wire becomes longer, the effect of inductance caused by the bonding wire becomes greater.

[0005] A semiconductor device according to one aspect of the present disclosure includes a first switching element to which a power supply voltage is supplied, a second switching element formed in a rectangular shape in a plan view and having a first electrode connected to the first switching element, a second electrode connected to ground, and a control electrode, a first inverter circuit, a second inverter circuit, and a third inverter circuit each including the first switching element and the second switching element, the first inverter circuit, the second inverter circuit, and the third inverter circuit being connected in parallel to each other, a first conductive layer on which the first switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are mounted and spaced apart from the first conductive layer, a second conductive layer on which the second switching element of the first inverter circuit is mounted and the second switching element of the second inverter circuit are mounted and spaced apart from the first conductive layer, a third conductive layer on which a switching element is mounted and the first conductive layer are spaced apart, a fourth conductive layer on which the second switching element of the third inverter circuit is mounted, the first inverter circuit, the second inverter circuit, and the third inverter circuit are spaced apart, an integrated circuit element is mounted with a control circuit that controls the second switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit, and a control wire electrically connecting a control electrode of the second switching element of the first inverter circuit, the second inverter circuit, and the third inverter circuit to the integrated circuit element, wherein the second conductive layer, the third conductive layer, and the fourth conductive layer are insulated from each other and spaced apart in a first direction, The first switching elements are mounted on the common first conductive layer in the same orientation as each other in a plan view, the second conductive layer has a first element mounting region in which the second switching element of the first inverter circuit is mounted, the third conductive layer has a second element mounting region in which the second switching element of the second inverter circuit is mounted, and the fourth conductive layer has a third element mounting region in which the second switching element of the third inverter circuit is mounted, the first element mounting region, the second element mounting region, and the third element mounting region have the same shape as each other and are formed into a rectangular shape in a plan view, and at least one of the centers of the second switching elements mounted in the first element mounting region, the second element mounting region, and the third element mounting region is the first switching element, the second switching element, the third switching element, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the integrated circuit element, and the control wire. The first switching element further includes a sealing resin formed in a flat rectangular shape that seals the first inverter circuit, the second inverter circuit, the third inverter circuit, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the integrated circuit element, and the control wire, the sealing resin having a third side surface from which a plurality of first terminal portions electrically connected to a control electrode of the first switching element protrude, the plurality of first terminal portions being arranged at a distance from each other in the direction in which the third side surface extends in a planar view, a recess is provided in a portion of the third side surface between first terminal portions adjacent to each other in the direction in which the third side surface extends, and a size of the recess in the direction in which the third side surface extends in a planar view is larger than a size of the recess in a direction perpendicular to the direction in which the third side surface extends. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an electrical configuration of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a plan view showing an internal arrangement of the semiconductor device. [Diagram 3] FIG. [Figure 4]FIG. [Diagram 5] Cross-sectional view taken along line 5-5 in Figure 2. [Figure 6] Cross-sectional view taken along line 6-6 in Figure 2. [Figure 7] An enlarged view of a portion of Figure 2. [Figure 8] Cross-sectional view taken along line 8-8 in Figure 7. [Figure 9] An enlarged view of a portion of Figure 2. [Figure 10] 10 is a cross-sectional view taken along line 10-10 in FIG. 9 . [Figure 11] FIG. 1 is a cross-sectional view showing the structure of a MOSFET. [Figure 12] FIG. 2 is a circuit diagram showing a detailed electrical configuration of a portion of the semiconductor device. [Figure 13] FIG. 11 is a circuit diagram showing a detailed electrical configuration of a part of a semiconductor device according to a second embodiment. [Figure 14] FIG. 2 is a schematic plan view showing the layout of a portion of an integrated circuit element of a semiconductor device. [Figure 15] FIG. 11 is an enlarged plan view of a portion of the internal arrangement configuration of a semiconductor device according to a third embodiment. [Figure 16] FIG. 13 is a block diagram showing an electrical configuration of a semiconductor device according to a fourth embodiment. [Figure 17] FIG. 2 is a plan view showing an internal arrangement of the semiconductor device. [Figure 18A] FIG. 2 is a cross-sectional perspective view showing a structure of a diode. [Figure 18B] FIG. 1 is a cross-sectional view showing a structure of a diode. [Figure 19] FIG. 13 is a circuit diagram illustrating an electrical connection configuration of a drive unit, for explaining the operation of the fourth embodiment. [Figure 20] FIG. 13 is a block diagram showing an electrical configuration of a semiconductor device according to a fifth embodiment. [Figure 21] FIG. 2 is a plan view showing an internal arrangement of the semiconductor device. [Figure 22] FIG. 13 is an enlarged plan view of a part of an internal arrangement configuration of a semiconductor device according to a modified example. [Figure 23] FIG. 13 is an enlarged plan view of a part of an internal arrangement configuration of a semiconductor device according to a modified example. [Figure 24]FIG. 13 is an enlarged plan view of a part of an internal arrangement configuration of a semiconductor device according to a modified example. [Diagram 25] FIG. 13 is an enlarged plan view of a part of an internal arrangement configuration of a semiconductor device according to a modified example. [Figure 26] FIG. 13 is an enlarged plan view of a part of an internal arrangement configuration of a semiconductor device according to a modified example. [Figure 27] FIG. 13 is an enlarged plan view of a part of an internal arrangement configuration of a semiconductor device according to a modified example. [Figure 28] FIG. 13 is an enlarged plan view of a part of an internal arrangement configuration of a semiconductor device according to a modified example. [Figure 29] FIG. 13 is a plan view showing an internal arrangement of a semiconductor device according to a modified example. [Diagram 30] FIG. 13 is a plan view showing an internal arrangement of a semiconductor device according to a modified example. [Diagram 31] FIG. 13 is a plan view showing an internal arrangement of a semiconductor device according to a modified example. [Diagram 32] FIG. 13 is an enlarged plan view of a part of an internal arrangement configuration of a semiconductor device according to a modified example. [Diagram 33] FIG. 13 is a plan view showing an internal arrangement of a semiconductor device according to a modified example. [Diagram 34] FIG. 13 is a cross-sectional view showing the structure of a modified example of a MOSFET. [Diagram 35] FIG. 13 is a cross-sectional view showing the structure of a modified example of a MOSFET. [Diagram 36] FIG. 11 is a cross-sectional view showing a structure of a modified diode. [Figure 37] FIG. 13 is a block diagram showing an electrical configuration of a semiconductor device according to a modified example. [Figure 38] FIG. 38 is a plan view showing an internal arrangement of the semiconductor device of FIG. 37. [Figure 39] FIG. 13 is a plan view showing an internal arrangement of a semiconductor device according to a modified example.

[0007] [Detailed Description] Each embodiment of the semiconductor device will be described below with reference to the drawings. Each embodiment shown below is an example of a configuration or method for embodying a technical idea, and is not intended to limit the material, shape, structure, arrangement, dimensions, etc. of each component to those described below. Various modifications can be made to each of the following embodiments.

[0008] In this specification, "a state in which component A is connected to component B" includes a case in which component A and component B are directly physically connected to each other, as well as a case in which component A and component B are indirectly connected to each other via another component that does not affect the electrical connection state.

[0009] Similarly, "a state in which component C is provided between component A and component B" includes a case in which component A and component C, or component B and component C, are directly connected to each other, as well as a case in which component A and component C, or component B and component C, are indirectly connected to each other via another component that does not affect the electrical connection state.

[0010] (First embodiment) As shown in Fig. 1, the semiconductor device 1 constitutes an inverter circuit for driving a motor 2, and includes a drive unit 10 having three inverter circuits, a first inverter circuit 10U, a second inverter circuit 10V, and a third inverter circuit 10W, and a control circuit 20 for controlling the drive unit 10. The inverter circuits 10U, 10V, and 10W are connected in parallel with each other. An example of the motor 2 is a three-phase brushless motor.

[0011] Each of the inverter circuits 10U, 10V, and 10W includes a first switching element 11 and a second switching element 12. The first switching element 11 and the second switching element 12 are connected in series. The first switching element 11 has a first terminal to which a power supply voltage is supplied, a second terminal connected to the second switching element 12, and a control terminal. The second switching element 12 has a first terminal connected to the second terminal of the first switching element 11, a second terminal connected to ground, and a control terminal. An example of the first switching element 11 and the second switching element 12 is a metal-oxide-semiconductor field-effect transistor (MOSFET). Hereinafter, the first switching element 11 of the first inverter circuit 10U is described as a MOSFET 11U, the first switching element 11 of the second inverter circuit 10V is described as a MOSFET 11V, and the first switching element 11 of the third inverter circuit 10W is described as a MOSFET 11W. In addition, the second switching element 12 of the first inverter circuit 10U is MOSFET 12U, the second switching element 12 of the second inverter circuit 10V is MOSFET 12V, and the second switching element 12 of the third inverter circuit 10W is MOSFET 12W. In this embodiment, N-channel MOSFETs are used for the MOSFETs 11U to 11W and 12U to 12W. The drains of the MOSFETs 11U to 11W are an example of the first terminals of the first switching elements 11, the sources of the MOSFETs 11U to 11W are an example of the second terminals of the first switching elements 11, and the gates of the MOSFETs 11U to 11W are an example of the control terminals of the first switching elements 11. The drains of the MOSFETs 12U to 12W are an example of the first terminals of the second switching elements 12, the sources of the MOSFETs 12U to 12W are an example of the second terminals of the second switching elements 12, and the gates of the MOSFETs 12U to 12W are an example of the control terminals of the second switching elements 12.

[0012] The MOSFET 11U and the MOSFET 12U are connected in series to each other. That is, the source of the MOSFET 11U and the drain of the MOSFET 12U are connected to each other. A node N between the source of the MOSFET 11U and the drain of the MOSFET 12U is electrically connected to a U-phase coil (not shown) of the motor 2.

[0013] The MOSFET 11V and the MOSFET 12V are connected in series to each other. That is, the source of the MOSFET 11V and the drain of the MOSFET 12V are connected to each other. A node N between the source of the MOSFET 11V and the drain of the MOSFET 12V is electrically connected to a V-phase coil (not shown) of the motor 2.

[0014] The MOSFET 11W and the MOSFET 12W are connected in series to each other. That is, the source of the MOSFET 11W and the drain of the MOSFET 12W are connected to each other. A node N between the source of the MOSFET 11W and the drain of the MOSFET 12W is electrically connected to a W-phase coil (not shown) of the motor 2.

[0015] The drains of the MOSFETs 11U to 11W are connected to each other. The drains of the MOSFETs 11U to 11W are electrically connected to an external power supply. The sources of the MOSFETs 12U to 12W are connected to each other. The sources of the MOSFETs 12U to 12W are connected to ground GND. The gates of the MOSFETs 11U to 11W and the gates of the MOSFETs 12U to 12W are each electrically connected to the control circuit 20.

[0016] It is preferable that the current flowing through each of the MOSFETs 11U to 11W and MOSFETs 12U to 12W is less than 30 A. In this embodiment, the current flowing through each of the MOSFETs 11U to 11W and MOSFETs 12U to 12W is about 15 A.

[0017] The control circuit 20 has a drive circuit 21 which is an example of a drive signal output circuit that outputs drive signals to the gates of the MOSFETs 11U-11W and the gates of the MOSFETs 12U-12W, respectively, a logic circuit 22 that controls the drive circuit 21, and a bootstrap circuit 23 that generates drive power supplies for high potential blocks of the drive circuit 21 and the logic circuit 22. The control circuit 20 has the drive circuits 21, logic circuit 22, and bootstrap circuit 23 corresponding to the MOSFETs 11U-11W and the MOSFETs 12U-12W, respectively.

[0018] The drive circuit 21 includes drive circuits 21UU, 21VU, and 21WU that control the gates of the high potential side MOSFETs 11U to 11W, and drive circuits 21UL, 21VL, and 21WL that control the gates of the low potential side MOSFETs 12U to 12W.

[0019] The drive circuit 21UU is electrically connected to the gate of the MOSFET 11U and outputs a drive signal to the gate. The drive circuit 21VU is electrically connected to the gate of the MOSFET 11V and outputs a drive signal to the gate. The drive circuit 21WU is electrically connected to the gate of the MOSFET 11W and outputs a drive signal to the gate.

[0020] The drive circuit 21UL is electrically connected to the gate of the MOSFET 12U and outputs a drive signal to the gate. The drive circuit 21VL is electrically connected to the gate of the MOSFET 12V and outputs a drive signal to the gate. The drive circuit 21WL is electrically connected to the gate of the MOSFET 12W and outputs a drive signal to the gate.

[0021] The logic circuit 22 has logic circuits 22UU, 22VU, 22WU which control drive circuits 21UU, 21VU, 21WU which control the gates of the high potential side MOSFETs 11U to 11W, and logic circuits 22UL, 22VL, 22WL which control drive circuits 21UL, 21VL, 21WL which control the gates of the low potential side MOSFETs 12U to 12W.

[0022] The logic circuit 22UU is electrically connected to the drive circuit 21UU and outputs to the drive circuit 21UU a signal for generating a drive signal that the drive circuit 21UU outputs to the gate of the MOSFET 11U. The logic circuit 22VU is electrically connected to the drive circuit 21VU and outputs to the drive circuit 21VU a signal for generating a drive signal that the drive circuit 21VU outputs to the gate of the MOSFET 11V. The logic circuit 22WU is electrically connected to the drive circuit 21WU and outputs to the drive circuit 21WU a signal for generating a drive signal that the drive circuit 21WU outputs to the gate of the MOSFET 11W.

[0023] The logic circuit 22UL is electrically connected to the drive circuit 21UL and outputs to the drive circuit 21UL a signal for generating a drive signal that the drive circuit 21UL outputs to the gate of the MOSFET 12U. The logic circuit 22VL is electrically connected to the drive circuit 21VL and outputs to the drive circuit 21VL a signal for generating a drive signal that the drive circuit 21VL outputs to the gate of the MOSFET 12V. The logic circuit 22WL is electrically connected to the drive circuit 21WL and outputs to the drive circuit 21WL a signal for generating a drive signal that the drive circuit 21WL outputs to the gate of the MOSFET 12W.

[0024] The bootstrap circuit 23 includes a first bootstrap circuit 23U, a second bootstrap circuit 23V, and a third bootstrap circuit 23W. The bootstrap circuits 23U, 23V, and 23W have a common configuration in which a boot diode and a boot capacitor are connected in series.

[0025] The first bootstrap circuit 23U is electrically connected to the source of the MOSFET 11U, the drive circuit 21UU, and the logic circuit 22UU. The first bootstrap circuit 23U generates a drive voltage for the drive circuit 21UU and the logic circuit 22UU.

[0026] The second bootstrap circuit 23V is electrically connected to the source of the MOSFET 11V, the drive circuit 21VU, and the logic circuit 22VU. The second bootstrap circuit 23V generates a drive voltage for the drive circuit 21VU and the logic circuit 22VU.

[0027] The third bootstrap circuit 23W is electrically connected to the source of the MOSFET 11W, the drive circuit 21WU, and the logic circuit 22WU. The third bootstrap circuit 23W generates a drive voltage for the drive circuit 21WU and the logic circuit 22WU.

[0028] In this embodiment, the drive circuits 21UU, 21VU, 21WU and the logic circuits 22UU, 22VU, 22WU are an example of a first control circuit that controls the first switching element 11. The drive circuits 21UL, 21VL, 21WL and the logic circuits 22UL, 22VL, 22WL are an example of a second control circuit that controls the second switching element 12. The drive circuit 21UL and the logic circuit 22UL are an example of a third control circuit that controls the second switching element 12 (MOSFET 12U) of the first inverter circuit. The drive circuit 21VL and the logic circuit 22VL are an example of a fourth control circuit that controls the second switching element 12 (MOSFET 12V) of the second inverter circuit. The drive circuit 21WL and the logic circuit 22WL are an example of a fifth control circuit that controls the second switching element 12 (MOSFET 12W) of the third inverter circuit.

[0029] An example of the configuration of the semiconductor device 1 will be described with reference to FIGS. The semiconductor device 1 further includes a lead 30, a heat dissipation member 40, and a sealing resin 50 (indicated by a two-dot chain line in FIG. 2). The semiconductor device 1 is packaged by sealing the driving unit 10 and the control circuit 20 (both see FIG. 1) with the sealing resin 50. The semiconductor device 1 is formed in a rectangular shape in a plan view. In the following description, the longitudinal direction of the semiconductor device 1 is defined as a first direction X, a direction perpendicular to the first direction X in the plan view of the semiconductor device 1 is defined as a second direction Y, and a direction perpendicular to both the first direction X and the second direction Y is defined as a third direction Z. The third direction Z can also be said to be the thickness direction of the semiconductor device 1.

[0030] 3, the dimension DX of the semiconductor device 1 (sealing resin 50) in the first direction X is preferably 60 mm or less. The dimension DY of the semiconductor device 1 (sealing resin 50) in the second direction Y is preferably 35 mm or less. The dimension DZ of the semiconductor device 1 (sealing resin 50) in the third direction Z is preferably 6 mm or less. In the semiconductor device 1 of this embodiment, the dimension DX in the first direction X is about 57 mm, the dimension DY in the second direction Y is about 30 mm, and the dimension DZ in the third direction Z is about 5 mm.

[0031] As shown in FIG. 3, the sealing resin 50 is formed in a flat rectangular shape. The sealing resin 50 is made of, for example, black epoxy resin. The sealing resin 50 has a front surface 50A, a back surface 50B, a first side surface 50C, a second side surface 50D, a third side surface 50E, and a fourth side surface 50F. The front surface 50A and the back surface 50B are flat surfaces along the first direction X and the second direction Y, and are substantially rectangular in shape with the first direction X as the longitudinal direction. The first side surface 50C is a side surface on one side of the sealing resin 50 in the first direction X, and the second side surface 50D is a side surface on the other side of the sealing resin 50 in the first direction X. The first side surface 50C and the second side surface 50D are flat surfaces along the second direction Y and the third direction Z, and are substantially rectangular in shape with the second direction Y as the longitudinal direction. The third side surface 50E is a side surface on one side of the sealing resin 50 in the second direction Y, and the fourth side surface 50F is a side surface on the other side of the sealing resin 50. The third side surface 50E and the fourth side surface 50F are planes along the first direction X and the third direction Z, and are substantially rectangular in shape with the first direction X as the longitudinal direction. The sealing resin 50 is provided with four first recesses 51 and two second recesses 52. The four first recesses 51 are formed so as to be recessed in the second direction Y from the third side surface 50E and to penetrate the sealing resin 50 in the third direction Z. The four first recesses 51 are provided at intervals in the first direction X with respect to a portion of the third side surface 50E closer to the first side surface 50C. The second recesses 52 are provided at the center of the first side surface 50C of the sealing resin 50 in the second direction Y and at the center of the second side surface 50D of the sealing resin 50 in the second direction Y. The second recesses 52 are formed so as to be recessed in the first direction X and to penetrate the sealing resin 50 in the third direction Z.

[0032] 4, the heat dissipation member 40 is exposed on a back surface 50B of the sealing resin 50. The heat dissipation member 40 is made of, for example, ceramics. The exposed surface 40A of the heat dissipation member 40 has a rectangular shape with the first direction X as the longitudinal direction.

[0033] As shown in Fig. 2, the lead 30 is a conductive support member that supports the MOSFETs 11U-11W and MOSFETs 12U-12W and the control circuit 20 (see Fig. 1) and constitutes a conductive path for these MOSFETs 11U-11W and MOSFETs 12U-12W. The lead 30 is formed, for example, by cutting such as punching and bending a metal plate material. An example of the material for the lead 30 is copper (Cu). The lead 30 has a thickness of, for example, about 0.42 mm.

[0034] The lead 30 includes a frame 31, frames 32U, 32V, and 32W, a plurality of control frames 33, a plurality of control frames 34, a frame 35U which is an example of a first ground frame, a frame 35V which is an example of a second ground frame, and a frame 35W which is an example of a third ground frame. The lead 30 of this embodiment also includes an auxiliary frame 36 which is not electrically connected to the MOSFET 11U and the MOSFET 12L and is a so-called non-connected frame. The frame 31 and the frames 32U, 32V, and 32W are arranged side by side with a gap in the first direction X. The plurality of control frames 33 and the plurality of control frames 34 are arranged side by side with a gap in the first direction X. The plurality of control frames 33 and the plurality of control frames 34 are arranged side by side with a gap in the second direction Y with the frame 31 and the frames 32U, 32V, and 32W. That is, the plurality of control frames 33 and the plurality of control frames 34 are arranged closer to the third side surface 50E of the sealing resin 50 in the second direction Y. The frames 35U, 35V, 35W are disposed on the opposite side of the frames 32U, 32V, 32W from the frame 31 in the first direction X. The frames 35U, 35V, 35W are disposed closer to the fourth side face 50F of the sealing resin 50 in the second direction Y. The auxiliary frame 36 is disposed at the end of the sealing resin 50 on the first side face 50C side and on the fourth side face 50F side. The auxiliary frame 36 has a terminal portion protruding from the fourth side face 50F.

[0035] The frame 31 is a lead frame for electrically connecting the drains of the MOSFETs 11U to 11W to an external power supply, and includes an island portion 31a, a terminal portion 31b, and a connection portion 31c. The island portion 31a, the terminal portion 31b, and the connection portion 31c are integrally formed. The island portion 31a is formed in a rectangular shape with the first direction X as the longitudinal direction. The MOSFETs 11U to 11W are mounted on the island portion 31a. The terminal portion 31b protrudes from the fourth side surface 50F of the sealing resin 50. The connection portion 31c connects the island portion 31a and the terminal portion 31b. The connection portion 31c extends from an end of the island portion 31a on the terminal portion 31b side in the second direction Y toward the terminal portion 31b. The terminal portion 31b protrudes from the sealing resin 50. The terminal portion 31b is formed in an L-shape extending from the sealing resin 50 in the second direction Y and then in the third direction Z (see FIG. 3). The island portion 31a, the terminal portion 31b, and the connection portion 31c may be formed separately and joined together to form the frame 31.

[0036] The first frame 32U is a lead frame for electrically connecting the drain of the MOSFET 12U and an electric device (for example, the motor 2) driven by the semiconductor device 1. The first frame 32U of this embodiment is electrically connected to a U-phase coil (not shown) of the motor 2. The second frame 32V is a lead frame for electrically connecting the drain of the MOSFET 12V and an electric device (for example, the motor 2) driven by the semiconductor device 1. The second frame 32V of this embodiment is electrically connected to a V-phase coil (not shown) of the motor 2. The third frame 32W is a lead frame for electrically connecting the drain of the MOSFET 12W and an electric device (for example, the motor 2) driven by the semiconductor device 1. The third frame 32W of this embodiment is electrically connected to a W-phase coil (not shown) of the motor 2. Each of the frames 32U, 32V, and 32W is formed to have substantially the same shape and has an island portion 32a, a terminal portion 32b, and a connection portion 32c. The island portion 32a, the terminal portion 32b, and the connection portion 32c are integrally formed. The island portion 32a is formed in a rectangular shape with the second direction Y being the longitudinal direction. The size (width dimension) of the island portion 32a of each of the frames 32U, 32V, and 32W in the first direction X is approximately 1 / 3 of the size (width dimension) of the island portion 31a of the frame 31 in the first direction X. The MOSFET 12U is mounted on the island portion 32a of the first frame 32U. The MOSFET 12V is mounted on the island portion 32a of the second frame 32V. The MOSFET 12W is mounted on the island portion 32a of the third frame 32W.

[0037] The terminal portion 32b of each of the frames 32U, 32V, 32W protrudes from a fourth side surface 50F of the sealing resin 50. Each of the terminal portions 32b is formed in an L shape extending from the sealing resin 50 in the second direction Y and then extending in the third direction Z (see FIG. 3).

[0038] The connection portion 32c of the first frame 32U extends from an end portion of the island portion 32a of the first frame 32U on the fourth side surface 50F side of the sealing resin 50 in the second direction Y and an end portion of the frame 31 side in the first direction X toward the terminal portion 32b. A wire bonding portion 32f having a rectangular shape in a plan view and extending in the first direction X is provided in a portion of the connection portion 32c on the fourth side surface 50F side of the sealing resin 50. As shown in FIG. 2, the connection portion 32c of the second frame 32V and the connection portion 32c of the third frame 32W each have the same shape as the connection portion 32c of the first frame 32U. The island portion 32a, the terminal portion 32b, and the connection portion 32c may be formed separately and joined together to form each of the frames 32U, 32V, and 32W.

[0039] The control frame 33 includes frames 33BU, 33BV, 33BW, frames 33U, 33V, 33W, a frame 33C, and a frame 33S. The frame 33S is a lead frame for supporting the integrated circuit element 25H. In one example of the integrated circuit element 25H, the high potential block circuit of the control circuit 20 is chipped. In this embodiment, the high potential block circuit of the control circuit 20 includes a first control circuit. That is, the high potential block circuit includes the drive circuits 21UU, 21VU, and 21WU and the logic circuits 22UU, 22VU, and 22WU (see FIG. 1 for both). The frame 33S has an island portion 33a, a first arm portion 33b extending from the island portion 33a toward the first side surface 50C of the sealing resin 50 along the first direction X, a second arm portion 33c extending in the second direction Y from the end of the first arm portion 33b on the first side surface 50C side of the sealing resin 50, and a terminal portion 33d extending from the second arm portion 33c. The island portion 33a, the first arm portion 33b, the second arm portion 33c, and the terminal portion 33d are integrally formed.

[0040] The island portion 33a is formed in a rectangular shape with the first direction X as the longitudinal direction. The size of the island portion 33a in the second direction Y is larger than the size of the first arm portion 33b in the second direction Y. The size of the island portion 33a in the first direction X is smaller than the size of the island portion 31a of the frame 31 in the first direction X. The island portion 33a is disposed with a gap between it and the island portion 31a of the frame 31 in the second direction Y. The island portion 33a is located approximately in the center of the island portion 31a of the frame 31 in the first direction X. More specifically, the island portion 33a is located such that its center position is slightly opposite to the first frame 32U in the first direction X from the center of the island portion 31a in the first direction X. An integrated circuit element 25H is mounted on the island portion 33a.

[0041] The first arm portion 33b extends to the first side surface 50C side of the sealing resin 50 beyond the frame 33BU. The first arm portion 33b is provided with a plurality of recesses 33e along the first direction X. The recesses 33e in this embodiment are circular in plan view and have a curved bottom in cross-sectional view. The second arm portion 33c is located near the first side surface 50C of the sealing resin 50. More specifically, the second arm portion 33c is located between the second recess 52 closest to the first side surface 50C among the four second recesses 52 and the first side surface 50C. The size (width dimension) of the second arm portion 33c in the first direction X is smaller than the size (width dimension) of the first arm portion 33b in the second direction Y. The terminal portion 33d protrudes from the sealing resin 50 in the second direction Y. The size (width dimension) of the terminal portion 33d in the first direction X is equal to the width dimension of the second arm portion 33c. Alternatively, the island portion 33a, the first arm portion 33b, and the second arm portion 33c may be formed separately and then joined together to form the frame 33S.

[0042] The frames 33BU, 33BV, 33BW, the frames 33U, 33V, 33W, and the frame 33C are arranged to surround the island portion 33a of the frame 33S. The frames 33BU, 33BV, and 33BW are lead frames for electrically connecting a control power supply (not shown) and the bootstrap circuit 23 (see FIG. 1). The frames 33U, 33V, and 33W are lead frames for connecting to a gate drive circuit (not shown) provided outside the semiconductor device 1. The gate drive circuit applies a gate signal voltage to the frames 33U, 33V, and 33W to generate a drive signal. The frame 33C is a lead frame for supplying power to the integrated circuit element 25H.

[0043] The first boot frame 33BU faces the island portion 33a of the frame 33S with a gap in the first direction X, and faces the first arm portion 33b of the frame 33S with a gap in the second direction Y. The frame 33BU is disposed closer to the first side surface 50C of the sealing resin 50 than the frames 33BV and 33BW.

[0044] The frames 33BV and 33BW are located closer to the third side surface 50E of the sealing resin 50 than the island portion 33a of the frame 33S. The frame 33BV is disposed to face the island portion 33a of the frame 33S with a gap in between in the second direction Y, and adjacent to the frame 33BU with a gap in between in the second direction Y. The frame 33BW is disposed to face the island portion 33a of the frame 33S with a gap in between in the second direction Y, and adjacent to the frame 33BV with a gap in between in the second direction Y. The frame 33BV is located between the frames 33BU and 33BW in the first direction X.

[0045] The frame 33BU has an island portion 33f and a terminal portion 33g. The island portion 33f and the terminal portion 33g are integrally formed. The frames 33BV and 33BW each have an island portion 33f and a terminal portion 33g, similar to the frame 33BU. The area of ​​the island portion 33f of the frame 33BU is larger than the area of ​​the island portion 33f of the frame 33BV and the area of ​​the island portion 33f of the frame 33BW. The island portion 33f of the frame 33BU has a portion extending from the island portion 33f of the frame 33BV toward the first arm portion 33b along the second direction Y. The island portion 33f of the frame 33BV and the island portion 33f of the frame 33BW each have a cutout portion corresponding to the second recess 52.

[0046] The boot diode 24U of the first bootstrap circuit 23U is mounted on the island portion 33f of the frame 33BU by soldering or the like. The boot diode 24U is located closer to the island portion 33f of the frame 33BV in the island portion 33f of the frame 33BU. The boot diode 24U is formed of a semiconductor chip. The boot diode 24U is provided with a cathode electrode serving as a front surface electrode and an anode electrode serving as a back surface electrode. The frame 33BU is electrically connected to the anode electrode of the boot diode 24U.

[0047] The boot diode 24V of the second bootstrap circuit 23V is mounted on the island portion 33f of the frame 33BV by soldering or the like. The boot diode 24V is located closer to the island portion 33f of the frame 33BU in the island portion 33f of the frame 33BV. The boot diode 24V is formed of a semiconductor chip. The boot diode 24V is provided with a cathode electrode serving as a front electrode and an anode electrode serving as a back electrode. The frame 33BV is electrically connected to the anode electrode of the boot diode 24V.

[0048] The boot diode 24W of the third bootstrap circuit 23W is mounted on the island portion 33f of the frame 33BW by solder or the like. The boot diode 24W is located at an end of the island portion 33f of the frame 33BW opposite to the island portion 33f of the frame 33BV in the first direction X. The boot diode 24W is formed of a semiconductor chip. The boot diode 24W is provided with a cathode electrode serving as a front electrode and an anode electrode serving as a back electrode. The frame 33BW is electrically connected to the anode electrode of the boot diode 24W.

[0049] The terminal portions 33g of the frames 33BU, 33BV, and 33BW protrude from a third side surface 50E of the sealing resin 50. The terminal portions 33g of the frames 33BU, 33BV, and 33BW are formed in an L-shape extending in the second direction Y and then in the third direction Z (see FIG. 3). A first recess 51 is located between the terminal portion 33g of the frame 33BU and the terminal portion 33g of the frame 33BV in the first direction X, and a first recess 51 is located between the terminal portion 33g of the frame 33BV and the terminal portion 33g of the frame 33BW in the first direction X. That is, the four first recesses 51 and the terminal portions 33g of the frames 33BU, 33BV, and 33BW are alternately arranged in the first direction X.

[0050] The frames 33U, 33V, 33W, and 33C are each formed in a substantially L-shape in a plan view. The frames 33U and 33V are located closer to the third side surface 50E of the sealing resin 50 than the island portion 33a of the frame 33S in the second direction Y. The frames 33V, 33W, and 33C are located closer to the second side surface 50D of the sealing resin 50 than the island portion 33a of the frame 33S in the first direction X. Parts of the frames 33W and 33C face the island portion 33a of the frame 33S with a gap in the first direction X. The frame 33U faces the island portion 33a of the frame 33S with a gap in the second direction Y, and is disposed facing the frame 33BW with a gap in the first direction X. The frame 33V faces the frame 33U with a gap in the first direction X and the second direction Y. Frame 33W faces frame 33V with a gap therebetween in the first direction X and the second direction Y. Frame 33C faces frame 33W with a gap therebetween in the first direction X and the second direction Y. The size of the gap between frames 33U and 33V in the first direction X is equal to the size of the gap between frames 33V and 33W. In the first direction X, the size of the gap between frames 33W and 33C is larger than the size of the gap between frames 33V and 33W.

[0051] In each of the frames 33U, 33V, 33W and 33C, the terminal portions protruding from the third side surface 50E of the sealing resin 50 are formed in an L shape extending from the sealing resin 50 in the second direction Y and then in the third direction Z (see FIG. 3).

[0052] The control frame 34 includes frames 34U, 34V, 34W, a frame 34CV, a frame 34S, and frames 34A, 34B, 34C, and 34D. The frame 34S is a lead frame for supporting the integrated circuit element 25L and for grounding the integrated circuit element 25L. In one example of the integrated circuit element 25L, the low potential block circuit of the control circuit 20 is chipped. In this embodiment, the low potential block circuit of the control circuit 20 includes a second control circuit. That is, the low potential block circuit includes the drive circuits 21UL, 21VL, and 21WL and the logic circuits 22UL, 22VL, and 22WL (see FIG. 1 for both). The frame 34S is formed in a substantially T-shape in plan view. More specifically, the frame 34S has an island portion 34a, a terminal portion 34b, a connection portion 34c, and an extension portion 34d. The island portion 34a, the terminal portion 34b, the connection portion 34c, and the extension portion 34d are integrally formed.

[0053] The island portion 34a is formed in a rectangular shape with the first direction X as the longitudinal direction. In the first direction X, the center position of the island portion 34a and the center position of the island portion 32a of the second frame 32V are equal to each other. The size of the island portion 34a in the first direction X is larger than the size of the island portion 32a in the first direction X. An end portion of the sealing resin 50 of the island portion 34a on the second side surface 50D side faces an end portion of the sealing resin 50 of the island portion 32a of the third frame 32W on the first side surface 50C side in the second direction Y. An end portion of the sealing resin 50 of the island portion 34a on the first side surface 50C side faces an end portion of the sealing resin 50 of the island portion 32a of the first frame 32U on the second side surface 50D side in the second direction Y. The size of the island portion 34a in the first direction X is larger than the size of the island portion 33a of the frame 33S in the first direction X. The size in the second direction Y of the island portion 34a is smaller than the size in the second direction Y of the island portion 33a.

[0054] The integrated circuit element 25L is mounted on the island portion 34a. The integrated circuit element 25L is disposed on the island portion 34a closer to the island portion 32a of the third frame 32W. More specifically, the integrated circuit element 25L is disposed on the island portion 34a so that its edge in the second direction Y is at the same position in the second direction Y as the edge of the island portion 34a on the island portion 34a side of the third frame 32W. In the first direction X, the center position of the integrated circuit element 25L and the center position of the island portion 34a of the third frame 32W are equal to each other. The size of the integrated circuit element 25L in the first direction X is approximately equal to the size of the integrated circuit element 25H in the first direction X. The size of the integrated circuit element 25L in the second direction Y is smaller than the size of the integrated circuit element 25H in the second direction Y. A plurality of recesses 34e are provided on both sides of the integrated circuit element 25L in the first direction X on the island portion 34a. The recesses 34e of this embodiment are circular in plan view and have curved bottoms in cross-sectional view.

[0055] The connection portion 34c connects the island portion 34a and the terminal portion 34b. The connection portion 34c extends from an end of the island portion 34a on the first side surface 50C side and an end of the third side surface 50E side of the sealing resin 50 along the second direction Y. The connection portion 34c is provided to face the frame 33C with a gap in the first direction X. The size of the gap in the first direction X between the connection portion 34c and the frame 33C is approximately equal to the size of the gap in the first direction X between the frame 33C and the frame 33W. The extension portion 34d extends from an end of the island portion 34a on the first side surface 50C side and an end of the fourth side surface 50F side of the sealing resin 50 along the first direction X. The tip of the extension portion 34d faces the island portion 33a of the frame 33S with a gap in the first direction X. The extension 34d faces, with a gap therebetween, the island portion 32a of the first frame 32U and a portion of the island portion 31a of the frame 31 closer to the second side surface 50D of the sealing resin 50 in the second direction Y. The extension 34d faces, with a gap therebetween, the frame 33C of the control frame 33 in the second direction Y. The terminal 34b protrudes from the third side surface 50E of the sealing resin 50. The terminal 34b is formed in an L-shape that extends in the second direction Y and then in the third direction Z (see FIG. 3).

[0056] The frames 34U, 34V, 34W, the frame 34CV, and the frames 34A, 34B, 34C, 34D are arranged to surround the island portion 34a of the frame 34S. The frames 34U, 34V, 34W, the frame 34CV, and the frame 34A are arranged closer to the third side surface 50E of the sealing resin 50 than the island portion 34a of the frame 34S in the second direction Y. The frames 34B, 34C, 34D are arranged closer to the second side surface 50D of the sealing resin 50 than the island portion 34a of the frame 34S in the first direction X.

[0057] The frames 34U, 34V, and 34W are lead frames for connecting to a gate drive circuit (not shown) provided outside the semiconductor device 1. The gate drive applies a gate signal voltage for generating a drive signal to the frames 34U, 34V, and 34W. The frame 34CV is a lead frame for supplying power to the integrated circuit element 25L. The frame 34A is a lead frame for outputting an abnormality signal when an abnormality occurs in the semiconductor device 1. The frame 34B is a lead frame for detecting a state in which at least one of the voltages applied to the frames 32U, 32V, and 32W is shorted to a high voltage application terminal (or a high potential terminal equivalent thereto). The frame 34C is a lead frame for grounding the integrated circuit element 25L. The frame 34D is a lead frame that is non-connected.

[0058] The portion (connection portion) in the frame 34U within the sealing resin 50 extends along the second direction Y, and the size (width dimension) in the first direction X decreases toward the tip. The portions in the frames 34V, 34W, 34CV, and 34A, 34B within the sealing resin 50 are inclined toward the second side surface 50D toward the third side surface 50E of the sealing resin 50. The portions in the frames 34V, 34W, 34CV, and 34A, 34C within the sealing resin 50 each have a size (width dimension) in the first direction X that decreases toward the tip. The frame 34D is formed in an L-shape consisting of a first portion extending in the first direction X and a second portion extending in the second direction Y. The size (width dimension) of the first portion of the frame 34D in the second direction Y decreases toward the tip. The first portions of the frames 34C and 34D are formed wider than the frames 34U, 34V, and 34W, the frame 34CV, and the frames 34A and 34B. The frames 34C and 34D each have a plurality of recesses 34f. The recesses 34f in this embodiment have the same shape as the recesses 34e. That is, the recesses 34f are circular in plan view and have curved bottoms in cross-sectional view.

[0059] The frames 34U, 34V, 34W, the frame 34CV, and the frames 34A, 34B, 34C, and 34D each have an L-shaped terminal portion that protrudes from the third side surface 50E of the sealing resin 50, extends in the second direction Y, and then extends in the third direction Z. The terminal portions of the frames 34U, 34V, 34W, the frame 34CV, and the frames 34A, 34B, 34C, and 34D are arranged side by side with gaps between them in the first direction X.

[0060] The frames 35U, 35V, and 35W serving as grounds are lead frames for grounding the sources of the MOSFETs 12U to 12W. Each of the frames 35U and 35V has an island portion 35a and a terminal portion 35b. The frame 35W has the island portion 35a, the terminal portion 35b, and a connection portion 35c. In the frames 35U and 35V, the island portion 35a and the terminal portion 35b are integrally formed. In the frame 35W, the island portion 35a, the terminal portion 35b, and the connection portion 35c are integrally formed.

[0061] The island portion 35a of the frames 35U and 35V is disposed near the fourth side surface 50F of the sealing resin 50, i.e., at the same position as the wire bonding portion 32f of each of the frames 32U, 32V, and 32W in the second direction Y. The island portion 35a of the frame 35W is disposed at the same position as the island portion 32a of the third frame 32W in the first direction X. That is, the island portion 35a of the frame 35W is disposed closer to the third side surface 50E of the sealing resin 50 than the island portions 35a of the frames 35U and 35V in the second direction Y. When viewed from the fourth side surface 50F of the sealing resin 50, a part of the island portion 35a of the frame 35W is disposed so as to overlap with the island portion 35a of the frame 35V. The island portion 35a of the frames 35U and 35V is disposed closer to the fourth side surface 50F of the sealing resin 50 than the island portion 32a of the third frame 32W. The island portion 35a of the frame 35U is formed in a rectangular shape with the first direction X as the longitudinal direction in a plan view. The island portion 35a of the frame 35V is formed in a substantially square shape in a plan view. The size of the island portion 35a of the frame 35U in the second direction Y is equal to the size of the island portion 35a of the frame 35V in the second direction Y. The size of the island portion 35a of the frame 35U in the first direction X is larger than the size of the island portion 35a of the frame 35V in the first direction X. The island portion 35a of the frame 35W is formed in a rectangular shape with the second direction Y as the longitudinal direction. The size of the island portion 35a of the frame 35W in the second direction Y is larger than the size of the island portion 35a of the frame 35U in the second direction Y. The area of ​​the island portion 35a of the frame 35W is larger than the area of ​​the island portion 35a of the frame 35U. The connection portion 35c extends in the second direction Y from an end portion of the island portion 35a on the second side surface 50D side of the sealing resin 50 in the first direction X and an end portion on the fourth side surface 50F side.

[0062] The terminal portions 35b of the frames 35U, 35V, and 35W protrude from the fourth side surface 50F of the sealing resin 50. The terminal portion 35b of the frame 35U is connected to an end portion of the island portion 35a of the frame 35U on the second side surface 50D side of the sealing resin 50. The terminal portion 35b of the frame 35V is connected to the center of the island portion 35a of the frame 35V in the first direction X. The terminal portion 35b of the frame 35W is connected to the connection portion 35c. Each terminal portion 35b is formed in an L-shape extending in the second direction Y and then in the third direction Z.

[0063] As shown in FIG. 5, the island portion 31a of the frame 31 is joined to the heat dissipation member 40. The connection portion 31c of the frame 31 is disposed away from the heat dissipation member 40 in the third direction Z. The frames 33S and 33BW are located closer to the surface 50A of the sealing resin 50 than the island portion 31a of the frame 31. The frames 33S and 33BW are disposed away from the heat dissipation member 40 in the third direction Z. Although not shown in FIG. 5, the control frame 33 other than the frames 33S and 33BW is also disposed so as to be located closer to the surface 50A of the sealing resin 50 than the frame 31, that is, so as to be separated from the heat dissipation member 40 in the third direction Z.

[0064] As shown in FIG. 6, the island portion 32a of the second frame 32V is joined to the heat dissipation member 40. FIG. 6 shows the cross-sectional structure of the second frame 32V and the plurality of control frames 33. The connection portion 32c of the second frame 32V is disposed away from the heat dissipation member 40 in the third direction Z. The frames 34S and 34U are located closer to the surface 50A of the sealing resin 50 than the second frame 32V. The frames 34S and 34U are located closer to the surface 50A of the sealing resin 50 than the frames 32U, 32V, and 32W. Although not shown in FIG. 6, the island portions 32a of the first frame 32U and the third frame 32W are each joined to the heat dissipation member 40. The connection portions 32c of the first frame 32U and the third frame 32W are each disposed away from the heat dissipation member 40 in the third direction Z. The control frame 34 other than the frame 34S and the frame 34U is disposed so as to be located closer to the front surface 50A of the sealing resin 50 than the frames 32U, 32V, and 32W, that is, so as to be spaced apart from the heat dissipation member 40 in the third direction Z.

[0065] Next, the detailed configuration of the frame 31 and the arrangement of the MOSFET 11U will be described with reference to FIGS. The frame 31 is provided with an element mounting area Rse where integrated circuit elements such as MOSFETs 11U to 11W can be mounted. The element mounting area Rse is a rectangular area with the first direction X as the longitudinal direction, and the element mounting area Rse is separated from other parts of the island portion 31a by a groove 31d. The element mounting area Rse is formed so as to be closer to the control frame 33 side of the island portion 31a in the second direction Y. The element mounting area Rse is also divided into six areas Ra1 to Ra6 by a groove 31e. The six areas Ra1 to Ra6 are formed by dividing the element mounting area Rse into three areas in the first direction X and two areas in the second direction Y. The three areas Ra1 to Ra3 are areas formed on the side of the element mounting area Rse facing the control frames 33 in the second direction Y. The three areas Ra4 to Ra6 are areas formed on the side of the element mounting area Rse facing the connection portion 31c in the second direction Y. As shown in FIG. 7, the regions Ra1 and Ra4 are arranged along the second direction Y, the regions Ra2 and Ra5 are arranged along the second direction Y, and the regions Ra3 and Ra6 are arranged along the second direction Y. The region Ra2 is located between the regions Ra1 and Ra3 in the first direction X. The region Ra1 is located closer to the first side surface 50C of the sealing resin 50 than the region Ra2, and the region Ra3 is located closer to the second side surface 50D of the sealing resin 50 than the region Ra2. The regions Ra1 to Ra3 are each a rectangular region whose longitudinal direction is the second direction Y. The regions Ra1 to Ra3 have the same size in the first direction X, and the regions Ra1 to Ra3 have the same size in the second direction Y. The regions Ra4 to Ra6 are each a rectangular region whose longitudinal direction is the second direction Y. The regions Ra4 to Ra6 have the same size in the first direction X, and the regions Ra4 to Ra6 have the same size in the second direction Y. The size of the regions Ra1 to Ra3 in the first direction X is equal to the size of the regions Ra4 to Ra6 in the first direction X. The size of the regions Ra1 to Ra3 in the second direction Y is larger than the size of the regions Ra4 to Ra6 in the second direction Y.

[0066] A MOSFET 11U is mounted in the region Ra1. The MOSFET 11U is located closer to the control frame 33 of the region Ra1 in the second direction Y. A MOSFET 11V is mounted in the region Ra2. The MOSFET 11V is located closer to the control frame 33 of the region Ra2 in the second direction Y. A MOSFET 11W is mounted in the region Ra3. The MOSFET 11W is located closer to the control frame 33 of the region Ra3 in the second direction Y. The position of the MOSFET 11U in the second direction Y, the position of the MOSFET 11V in the second direction Y, and the position of the MOSFET 11W in the second direction Y are all equal to one another. Semiconductor elements different from the MOSFETs 11U to 11W can be mounted in the regions Ra4 to Ra6. In this embodiment, no semiconductor elements are mounted in the regions Ra4 to Ra6.

[0067] 7, the MOSFETs 11U and 11V are arranged to overlap with the integrated circuit element 25H when viewed from the second direction Y. On the other hand, the MOSFET 11W is arranged closer to the second side surface 50D than the integrated circuit element 25H. Also, the MOSFET 11U is arranged such that the end of the MOSFET 11U on the first side surface 50C side is closer to the first side surface 50C than the edge of the integrated circuit element 25H on the first side surface 50C side.

[0068] A plurality of recesses 31f recessed in the third direction Z are provided in the island portion 31a in a portion other than the element mounting region Rse. The plurality of recesses 31f are arranged in a matrix in the first direction X and the second direction Y. The plurality of recesses 31f in this embodiment are circular in a plan view and have a curved bottom in a cross-sectional view.

[0069] The same MOSFETs are used as the MOSFETs 11U to 11W and the MOSFETs 12U to 12W. The MOSFET 11U is formed of a semiconductor chip having a rectangular shape in a plan view. The MOSFET 11U is disposed such that the second direction Y is the longitudinal direction. The size of the MOSFET 11U in the first direction X is smaller than the size of the region Ra1 in the first direction X. A source electrode pad 11s and a gate electrode pad 11g are provided on the front surface of the MOSFET 11U, and a drain electrode pad 11d (see FIG. 8) is provided on the back surface of the MOSFET 11U. Thus, the frame 31 is electrically connected to the drain of the MOSFET 11U. The solder SD (see FIG. 8) used to bond the MOSFET 11U to the island portion 31a bonds the MOSFET 11U to the island portion 31a by going through a molten state and then hardening. As can be seen from FIG. 7, the solder SD slightly protrudes from the periphery of the MOSFET 11U. The source electrode pad 11s, the drain electrode pad 11d, and the gate electrode pad 11g of the MOSFET 11U are made of, for example, aluminum (Al) or an aluminum alloy. Examples of aluminum alloys include Al--Cu, Al--Si--Cu, etc. The shape, size, and structure of the MOSFETs 11V and 11W, and the connection structure to the island portion 31a are the same as those of the MOSFET 11U.

[0070] The source electrode pad 11s of the MOSFET 11U occupies most of the surface of the MOSFET 11U. The gate electrode pad 11g of the MOSFET 11U is provided at one of the four corners of the surface of the MOSFET 11U, which is located on the first side surface 50C side of the sealing resin 50 in the first direction X and on the control frame 33 side in the second direction Y. A cutout is formed in the source electrode pad 11s of the MOSFET 11U to avoid the gate electrode pad 11g. The gate electrode pad 11g of the MOSFET 11U is formed in a rectangular shape with the longitudinal direction extending in the second direction Y.

[0071] 8, the island portion 31a of the frame 31 and the heat dissipation member 40 are bonded together by an adhesive AH. The adhesive AH is applied to the entire surface of the island portion 31a that faces the heat dissipation member 40. In other words, the entire surface of the island portion 31a that faces the heat dissipation member 40 and the heat dissipation member 40 are in contact with each other via the adhesive AH. The adhesive AH preferably appropriately bonds the heat dissipation member 40 made of ceramics to the island portion 31a made of copper (Cu) and has relatively good thermal conductivity; for example, a resin adhesive with excellent thermal conductivity is used.

[0072] Next, the detailed configuration of each of the frames 32U, 32V, 32W and the arrangement of the MOSFETs 12U to 12W will be described with reference to FIGS. The island portion 32a of the first frame 32U, the island portion 32a of the second frame 32V, and the island portion 32a of the third frame 32W have different shapes of ends on the connection portion 32c side in the second direction Y. The island portion 32a of the first frame 32U has a notch 32d formed therein to prevent interference with the connection portion 32c of the second frame 32V. The island portion 32a of the second frame 32V has a notch 32e formed therein to prevent interference with the connection portion 32c of the third frame 32W. On the other hand, no notch is formed in the island portion 32a of the third frame 32W.

[0073] Each of the frames 32U, 32V, and 32W has a device mounting area Rse formed therein, similar to the frame 31. The device mounting areas Rse of each of the frames 32U, 32V, and 32W are areas of the same shape. The device mounting areas Rse are rectangular areas whose longitudinal direction is the second direction Y. The size of the device mounting areas Rse of each of the frames 32U, 32V, and 32W in the second direction Y is equal to the size of the device mounting area Rse of the frame 31 in the second direction Y. The size of the device mounting areas Rse of each of the frames 32U, 32V, and 32W in the first direction X is about 1 / 3 of the size of the device mounting area Rse of the frame 31 in the first direction X. In other words, the size of the device mounting areas Rse of each of the frames 32U, 32V, and 32W in the first direction X is equal to the size of the device mounting area Rse of the frame 31 in the first direction X.

[0074] The element mounting area Rse of each frame 32U, 32V, 32W is separated from the other parts of the island portion 32a by a groove portion 32g. The element mounting area Rse is also divided into six areas Ra7 and Ra8 by a groove portion 32h. The areas Ra7 and Ra8 are arranged side by side in the second direction Y. The area Ra7 is an area formed on the side of the element mounting area Rse facing the multiple control frames 34 in the second direction Y. The area Ra7 is a rectangular area with the second direction Y being the longitudinal direction. The size of the area Ra7 is equal to the size of each of the areas Ra1 to Ra3 of the element mounting area Rse of the frame 31. The size of the area Ra8 is equal to the size of each of the areas Ra4 to Ra6 of the element mounting area Rse of the frame 31. In other words, the area of ​​the area Ra7 is larger than the area of ​​the area Ra8, and the size of the area Ra7 in the second direction Y is larger than the size of the area Ra8 in the second direction Y.

[0075] A MOSFET 12U is mounted in the region Ra7 of the first frame 32U. The MOSFET 12U is located closer to the control frame 34 in the region Ra7 of the first frame 32U in the second direction Y. A MOSFET 12V is mounted in the region Ra7 of the second frame 32V. The MOSFET 12V is located closer to the control frame 34 in the region Ra7 of the second frame 32V in the second direction Y. A MOSFET 12W is mounted in the region Ra7 of the third frame 32W. The MOSFET 12W is located closer to the control frame 34 in the region Ra7 of the third frame 32W in the second direction Y. The position of the MOSFET 12U in the second direction Y, the position of the MOSFET 12V in the second direction Y, and the position of the MOSFET 12W in the second direction Y are all equal to one another.

[0076] In the region Ra8 of each of the frames 32U, 32V, and 32W, a semiconductor element different from the MOSFETs 12U to 12W can be mounted. In this embodiment, no semiconductor element is mounted in the region Ra8 of each of the frames 32U, 32V, and 32W.

[0077] A plurality of recesses 32i are provided in the island portion 32a in a portion other than the element mounting region Rse, i.e., in the portion surrounding the element mounting region Rse in the island portion 32a. The plurality of recesses 32i in this embodiment have the same shape as the recess 31f, are circular in a plan view, and have a curved bottom in a cross-sectional view.

[0078] The MOSFET 12U is formed of a semiconductor chip having a rectangular shape in a plan view. The MOSFET 12U is arranged so that the second direction Y is the longitudinal direction. As described above, the same semiconductor chip as the MOSFET 11U is used for the MOSFET 12U, and therefore the size in the first direction X and the second direction Y of the MOSFET 12U is equal to the size in the first direction X and the second direction Y of the MOSFETs 11U to 11W. That is, the size in the first direction X of the MOSFET 12U is smaller than the size in the first direction X of each region Ra7. A source electrode pad 12s and a gate electrode pad 12g are provided on the front surface of the MOSFET 12U, and a drain electrode pad 12d (see FIG. 10) is provided on the back surface of the MOSFET 12U. Thus, the first frame 32U is electrically connected to the drain of the MOSFET 12U mounted on the first frame 32U. The solder SD (see FIG. 10) used for joining the island portion 32a of the first frame 32U to the MOSFET 12U is hardened through a molten state, thereby joining the MOSFET 12U to the island portion 32a.

[0079] The second frame 32V is electrically connected to the drain of the MOSFET 12V mounted on the second frame 32V. The third frame 32W is electrically connected to the drain of the MOSFET 12W mounted on the third frame 32W. The junction structure between the MOSFETs 12V, 12W and the island portion 32a of each of the frames 32V, 32W is the same as the junction structure between the MOSFET 12U and the island portion 32a of the first frame 32U.

[0080] The shape of the source electrode pads 12s of the MOSFETs 12U to 12W is the same as that of the source electrode pad 11s of the MOSFET 11U, and the shape of the gate electrode pads 12g of the MOSFETs 12U to 12W is the same as that of the gate electrode pad 11g of the MOSFET 11U. The source electrode pads 12s and the gate electrode pads 12g of the MOSFETs 12U to 12W are made of, for example, gold (Au). The drain electrode pads 12d of the MOSFETs 12U to 12W are made of, for example, gold (Au) or silver (Ag).

[0081] As shown in Fig. 10, the island portion 32a of each frame 32U, 32V, 32W and the heat dissipation member 40 are bonded together by an adhesive AH. The adhesive AH is applied to the entire surface of the island portion 32a of each frame 32U, 32V, 32W that faces the heat dissipation member 40. That is, the entire surface of the island portion 32a of each frame 32U, 32V, 32W that faces the heat dissipation member 40 and the heat dissipation member 40 are in contact with each other via the adhesive AH. The adhesive AH is preferably one that appropriately bonds the heat dissipation member 40 made of ceramics to the island portion 32a of each frame 32U, 32V, 32W made of copper (Cu) and has relatively good thermal conductivity, and for example, a resin adhesive having excellent thermal conductivity is used.

[0082] As shown in FIG. 2, the lead 30, the MOSFETs 11U-11W and MOSFETs 12U-12W, and the integrated circuit elements 25H and 25L are electrically connected to one another by wire bonding. More specifically, the semiconductor device 1 has high-potential side power wires that connect the lead 30 to the MOSFETs 11U-11W, respectively. The high-potential side power wires include a first wire 60U that is an example of a first power wire, a second wire 60V that is an example of a second power wire, and a third wire 60W that is an example of a third power wire. The semiconductor device 1 also has low-potential side power wires that connect the lead 30 to the MOSFETs 12U-12W, respectively. The low-potential side power wires include a first wire 61U that is an example of a fourth power wire, a second wire 61V that is an example of a fifth power wire, and a third wire 61W that is an example of a sixth power wire. The semiconductor device 1 also has a plurality of wires 62 connecting the integrated circuit element 25H and the MOSFETs 11U to 11W, and a plurality of wires 62 connecting the integrated circuit elements 25H, 25L and the plurality of control frames 33, 34. In this embodiment, the wires 60U, 60V, 60W are connected to the lead 30 and the MOSFETs 11U to 11W by wedge bonding. Also, the wires 61U, 61V, 61W are connected to the lead 30 and the MOSFETs 12U to 12W by wedge bonding. Also, in this embodiment, the plurality of wires 62 connect the integrated circuit elements 25H, 25L and the plurality of control frames 33, 34 by ball bonding. Also, the semiconductor device 1 has a first wire 62U, a second wire 62V, and a third wire 62W which are an example of control wires connecting the MOSFETs 12U to 12W and the integrated circuit element 25L, and a first wire 63U, a second wire 63V, and a third wire 63W which are an example of limiting wires. 9, the wires 63U, 63V, and 63W are provided separately from the wires 62U, 62V, and 62W. In this embodiment, the wires 62U, 62V, and 62W and the wires 63U, 63V, and 63W connect the integrated circuit element 25L and the MOSFETs 12U to 12W by ball bonding.

[0083] Each of the wires 60U, 60V, 60W, 61U, 61V, and 61W is made of, for example, aluminum (Al), and each of the wires 62, 62U, 62V, and 62W and each of the wires 63U, 63V, and 63W is made of, for example, gold (Au). The wire diameters of each of the wires 60U, 60V, 60W, 61U, 61V, and 61W are equal to each other. The wire diameters of each of the wires 62, 62U, 62V, and 62W are equal to each other. The wire diameters of each of the wires 63U, 63V, and 63W are equal to each other. The wire diameters of each of the wires 62, 62U, 62V, and 62W and each of the wires 63U, 63V, and 63W are equal to each other. The wire diameter of each of the wires 60U, 60V, 60W, 61U, 61V, 61W is larger than the wire diameter of each of the wires 62, 62U, 62V, 62W and the wire diameter of each of the wires 63U, 63V, 63W. The wire diameter of each of the wires 60U, 60V, 60W, 61U, 61V, 61W is about 10 times the wire diameter of each of the wires 62, 62U, 62V, 62W and the wire diameter of each of the wires 63U, 63V, 63W. An example of the wire diameter of each of the wires 60U, 60V, 60W, 61U, 61V, 61W is 400 μm. An example of the wire diameter of each of the wires 62, 62U, 62V, 62W and the wire diameter of each of the wires 63U, 63V, 63W is 38 μm.

[0084] A single first wire 60U connects the source electrode pad 11s of the MOSFET 11U to the wire junction 32f of the first frame 32U. A single second wire 60V connects the source electrode pad 11s of the MOSFET 11V to the wire junction 32f of the second frame 32V. A single third wire 60W connects the source electrode pad 11s of the MOSFET 11W to the wire junction 32f of the third frame 32W. These wires 60U, 60V, and 60W are generally parallel to each other. The first wire 60U passes through an area Ra5 of the element mounting area Rse and is connected to the wire junction 32f of the first frame 32U. The second wire 60V passes through an area Ra6 of the element mounting area Rse and the connection portion 32c of the first frame 32U and is connected to the wire junction 32f of the second frame 32V. The third wire 60W passes through the region Ra8 of the element mounting region Rse of the first frame 32U and the connection portion 32c of the second frame 32V, and is connected to the wire joint portion 32f of the third frame 32W.

[0085] The source electrode pad 11s of each of the MOSFETs 11U to 11W is connected to the integrated circuit element 25H by one wire 62. The gate electrode pad 11g of each of the MOSFETs 11U to 11W is connected to the integrated circuit element 25H by one wire 62.

[0086] 7, the connection portion of the first wire 60U with the source electrode pad 11s of the MOSFET 11U is thicker than other portions of the first wire 60U. This connection portion is provided closer to the integrated circuit element 25H than the edge of the gate electrode pad 11g of the MOSFET 11U on the source electrode pad 11s side in the second direction Y. That is, the connection portion of the first wire 60U with the source electrode pad 11s of the MOSFET 11U is provided so as to overlap with the gate electrode pad 11g of the MOSFET 11U as viewed from the first direction X, and extends so as to straddle one edge of the gate electrode pad 11g in the second direction Y. In addition, this connection portion is provided closer to the second side surface 50D than the center line (dotted chain line) indicating the center of the MOSFET 11U in the first direction X.

[0087] The connection portion of the second wire 60V with the source electrode pad 11s of the MOSFET 11V is thicker than other portions of the second wire 60V. This connection portion is provided closer to the integrated circuit element 25H than the edge of the gate electrode pad 11g of the MOSFET 11V on the source electrode pad 11s side in the second direction Y. That is, the connection portion of the second wire 60V with the source electrode pad 11s of the MOSFET 11V is provided so as to overlap with the gate electrode pad 11g of the MOSFET 11V when viewed from the first direction X, and extends so as to straddle one edge of the gate electrode pad 11g in the second direction Y. In addition, this connection portion is provided closer to the second side surface 50D than the center line (dotted chain line) indicating the center of the MOSFET 11V in the first direction X.

[0088] A connection portion of the third wire 60W with the source electrode pad 11s of the MOSFET 11W is thicker than other portions of the third wire 60W. This connection portion is provided closer to the integrated circuit element 25H than the edge of the gate electrode pad 11g of the MOSFET 11W on the source electrode pad 11s side in the second direction Y. That is, the connection portion of the third wire 60W with the source electrode pad 11s of the MOSFET 11W is provided so as to overlap with the gate electrode pad 11g of the MOSFET 11W as viewed from the first direction X, and extends so as to straddle one edge of the gate electrode pad 11g in the second direction Y. In addition, this connection portion is provided closer to the second side surface 50D than the center line (dotted chain line) indicating the center of the MOSFET 11W in the first direction X.

[0089] The integrated circuit element 25H is connected to each of the frames 33BU, 33BV, 33BW and the boot diodes 24U, 24V, 24W by wires 62. More specifically, the integrated circuit element 25H is connected to each of the island portions 33f of the frames 33BU, 33BV, 33BW by two wires 62. The integrated circuit element 25H is connected to each of the cathode electrodes of the frames 33BU, 33BV, 33BW by one wire 62.

[0090] The integrated circuit element 25H is connected to each of the frames 33U, 33V, and 33W by one wire 62. The integrated circuit element 25H is connected to the frame 33C by three wires 62. The integrated circuit element 25H is connected to the extension 34d of the frame 34S of the control frame 34 by two wires 62.

[0091] As shown in FIG. 2, one first wire 61U connects the source electrode pad 12s of the MOSFET 12U to the frame 35U. One second wire 61V connects the source electrode pad 12s of the MOSFET 12V to the frame 35V. One third wire 61W connects the source electrode pad 12s of the MOSFET 12W to the frame 35W. These wires 61U, 61V, and 61W are generally parallel to each other. The first wire 61U passes through the region Ra8 of the element mounting region Rse of the second frame 32V and the connection portion 32c of the third frame 32W to be connected to the frame 35U. The second wire 61V passes through the region Ra8 of the element mounting region Rse of the third frame 32W to be connected to the frame 35V. The third wire 61W passes through the region Ra7 side of the region Ra8 of the element mounting region Rse of the third frame 32W to be connected to the frame 35W.

[0092] 9, a connection portion of the first wire 61U with the source electrode pad 12s of the MOSFET 12U is thicker than other portions of the first wire 61U. This connection portion is provided closer to the integrated circuit element 25H than the edge of the gate electrode pad 12g of the MOSFET 12U on the source electrode pad 12s side in the second direction Y. That is, the connection portion of the first wire 61U with the source electrode pad 12s of the MOSFET 12U is provided so as to overlap with the gate electrode pad 12g of the MOSFET 12U as viewed from the first direction X, and extends so as to straddle one edge of the gate electrode pad 12g in the second direction Y. In addition, this connection portion is provided closer to the second side surface 50D than the center line (dotted chain line) indicating the center of the MOSFET 12U in the first direction X.

[0093] The connection portion of the second wire 61V with the source electrode pad 12s of the MOSFET 12V is thicker than other portions of the second wire 60V. This connection portion is provided closer to the integrated circuit element 25H than the edge of the gate electrode pad 12g of the MOSFET 12V on the source electrode pad 12s side in the second direction Y. That is, the connection portion of the second wire 61V with the source electrode pad 12s of the MOSFET 12V is provided so as to overlap with the gate electrode pad 12g of the MOSFET 12V as viewed from the first direction X, and extends so as to straddle one edge of the gate electrode pad 12g in the second direction Y. In addition, this connection portion is provided closer to the second side surface 50D than the center line (dotted chain line) indicating the center of the MOSFET 12V in the first direction X.

[0094] A connection portion of the third wire 61W with the source electrode pad 12s of the MOSFET 12W is thicker than other portions of the third wire 61W. This connection portion is provided closer to the integrated circuit element 25H than the edge of the gate electrode pad 12g of the MOSFET 12W on the source electrode pad 12s side in the second direction Y. That is, the connection portion of the third wire 61W with the source electrode pad 12s of the MOSFET 12W is provided so as to overlap with the gate electrode pad 12g of the MOSFET 12W as viewed from the first direction X, and extends so as to straddle one edge of the gate electrode pad 12g in the second direction Y. In addition, this connection portion is provided closer to the second side surface 50D than the center line (dotted chain line) indicating the center of the MOSFET 12W in the first direction X.

[0095] One first wire 62U, which is an example of a first control wire, connects the gate electrode pad 12g of the MOSFET 12U mounted on the first frame 32U to the integrated circuit element 25L. One second wire 62V, which is an example of a second control wire, connects the gate electrode pad 12g of the MOSFET 12V mounted on the second frame 32V to the integrated circuit element 25L. One third wire 62W, which is an example of a third control wire, connects the gate electrode pad 12g of the MOSFET 12W mounted on the third frame 32W to the integrated circuit element 25L. One end of each of these wires 62U, 62V, 62W is connected to an end of the integrated circuit element 25L on the MOSFETs 12U to 12W side. The number of each of the wires 62U, 62V, 63W is not limited to one, and may be multiple.

[0096] A single first wire 63U, which is an example of a first limiting wire, connects the source electrode pad 12s of the MOSFET 12U mounted on the first frame 32U to the integrated circuit element 25L. A single second wire 63V, which is an example of a second limiting wire, connects the source electrode pad 12s of the MOSFET 12V mounted on the second frame 32V to the integrated circuit element 25L. A single third wire 63W, which is an example of a third limiting wire, connects the source electrode pad 12s of the MOSFET 12W mounted on the third frame 32W to the integrated circuit element 25L. One end of each of these wires 63U, 63V, and 63W is connected to an end of the integrated circuit element 25L on the MOSFETs 12U to 12W side. The number of each of the wires 63U, 63V, and 63W is not limited to one, and may be multiple.

[0097] In the first direction X, the first wire 63U is arranged adjacent to the first wire 62U, the second wire 63V is arranged adjacent to the second wire 62V, and the third wire 63W is arranged adjacent to the third wire 62W. In more detail, the first wire 62U is arranged closer to the second frame 32V than the first wire 63U. The first wire 62U and the first wire 63U are each connected to the corner of the integrated circuit element 25L that is closer to the first frame 32U. The second wire 63V is arranged closer to the third frame 32W than the second wire 62V. The second wire 62V and the second wire 63V are each connected to a portion of the integrated circuit element 25L that is closer to the third frame 32W than the center portion in the first direction X. The third wire 62W is arranged closer to the second frame 32V than the third wire 63W. One end of each of the third wires 62W and 63W is connected to a portion of the integrated circuit element 25L on the second frame 32V side relative to the connection position of the wire 62 connected to the frame 34D and the integrated circuit element 25L.

[0098] The integrated circuit element 25L is connected to each of the frames 34U, 34V, and 34W by one wire 62. The integrated circuit element 25L is connected to each of the frames 34CV by two wires 62. The integrated circuit element 25L is connected to each of the frames 34A, 34B, and 34D by one wire 62. The integrated circuit element 25L is connected to each of the frames 34C by two wires 62. One end of the wire 62 connected to the frame 34D is connected to the end of the integrated circuit element 25L on the frame 34D side in the second direction Y.

[0099] [MOSFET structure] The detailed structures of the MOSFETs 11U-11W and 12U-12W will be described with reference to Fig. 11. Since the MOSFETs 11U-11W and 12U-12W have the same structure, the structure of the MOSFET 11U will be described below, and descriptions of the MOSFETs 11V, 11W and MOSFETs 12U-12W will be omitted.

[0100] The MOSFET 11U includes a silicon carbide (SiC) substrate 70. The SiC substrate 70 contains a high concentration of N-type impurities (for example, 1e18 to 1e21 cm -3 ) is doped. The SiC substrate 70 has a front surface 70A (upper surface) which is a Si surface, and a rear surface 70B (lower surface) which is a C surface.

[0101] The surface 70A of the SiC substrate 70 is doped with N-type impurities at a lower concentration than the SiC substrate 70. - A mold epitaxial layer 71 is laminated on the SiC substrate 70. The epitaxial layer 71 is formed on the SiC substrate 70 by so-called epitaxial growth. The epitaxial layer 71 formed on the surface 70A, which is a Si surface, is grown with the Si surface as the main growth surface. Therefore, the surface 71A of the epitaxial layer 71 formed by growth is a Si surface, similar to the surface 70A of the SiC substrate 70.

[0102] The epitaxial layer 71 has a C-face side (base layer) opposite to the Si-face side (surface layer), whose entire area remains in the same state as after epitaxial growth. - The N-type impurity concentration of the drain region 72 is, for example, 1e15 to 1e17 cm -3 It is.

[0103] On the other hand, a P-type body region 73 is formed in a surface portion of the epitaxial layer 71. The body region 73 contacts the drain region 72 from a surface 71A side (Si surface side) of the epitaxial layer 71. The P-type impurity concentration of the body region 73 is, for example, 1e16 to 1e19 cm -3 It is.

[0104] Gate trenches 74 are formed in the epitaxial layer 71 by digging down from the surface 71A. Although not shown in Fig. 11, a plurality of gate trenches 74 are formed at regular intervals, and they extend parallel to each other in the same direction (a direction perpendicular to the paper surface of Fig. 11; hereinafter, this direction may be referred to as "the direction along the gate width") to form, for example, a striped structure.

[0105] The gate trenches 74 face each other with a gap therebetween, and each have a pair of side surfaces 74a on a plane perpendicular to the surface 71 A, and a bottom surface 74b having a portion parallel to the surface 71 A. The gate trenches 74 penetrate the body region 73 in the layer thickness direction, and their deepest portion (bottom surface 74b) reaches the drain region 72.

[0106] A gate insulating film 75 is formed on the inner surface of the gate trench 74 and on the surface 71A of the epitaxial layer 71 so as to cover the entire inner surface (side surface 74a and bottom surface 74b) of the gate trench 74. The gate insulating film 75 is made of an oxide film containing nitrogen (Ni), for example, a silicon nitride oxide film formed by thermal oxidation using a nitrogen-containing gas. The nitrogen content (nitrogen concentration) in the gate insulating film 75 is, for example, 0.1 to 10%.

[0107] The gate insulating film 75 has a thickness T2 of a portion (insulating film bottom 75a) on the bottom surface 74b of the gate trench 74 smaller than a thickness T1 of a portion (insulating film side 75b) on the side surface 74a. Specifically, the ratio of the thickness T2 of the insulating film bottom 75a to the thickness T1 of the insulating film side 75b (thickness T2 of insulating film bottom 75a / thickness T1 of insulating film side 75b) is 0.3 to 1.0, and preferably 0.5 to 1.0. The thickness T1 of the insulating film side 75b is, for example, 300 to 1000 Å, and the thickness T2 of the insulating film bottom 75a is, for example, 150 to 500 Å.

[0108] A gate electrode 76 is buried in the gate insulating film 75. The gate electrode 76 is formed by completely filling the inside of the gate insulating film 75 with a polysilicon material doped with a high concentration of N-type impurities.

[0109] The surface layer of the body region 73 is provided with N + The source region 77 is a region doped with a high concentration of N-type impurities, which is higher than the N-type impurity concentration of the drain region 72. The N-type impurity concentration of the source region 77 is, for example, 1e18 to 1e21 cm -3 The source region 77 extends in a direction parallel to the gate width at a position adjacent to the gate trench 74.

[0110] The epitaxial layer 71 has a P + A P-type body contact region 78 is formed in the body region 73. The body contact region 78 is a region doped with a P-type impurity at a high concentration, which is higher than the P-type impurity concentration of the body region 73. The P-type impurity concentration of the body contact region 78 is, for example, 1e18 to 1e21 cm -3 It is.

[0111] That is, the gate trenches 74 and the source regions 77 are alternately provided in a direction perpendicular to the gate width, and each extends in a direction along the gate width. A boundary between adjacent unit cells in a direction perpendicular to the gate width is set on the source region 77 along the source region 77. At least one body contact region 78 is provided across two unit cells adjacent in a direction perpendicular to the gate width. The boundary between adjacent unit cells in the direction along the gate width is set so that the gate electrode 76 included in each unit cell has a constant gate width.

[0112] An interlayer insulating film 79 made of silicon oxide (SiO2) is laminated on the epitaxial layer 71. In the interlayer insulating film 79 and the gate insulating film 75, contact holes 80 are formed to expose the surfaces of the source region 77 and the body contact region 78.

[0113] A source wiring 81 is formed on the interlayer insulating film 79. The source wiring 81 is in contact (electrically connected) with the source region 77 and the body contact region 78 through a contact hole 80. The source wiring 81 has a polysilicon layer 82 at a contact portion with the source region 77 and the body contact region 78, and has a metal layer 83 on the polysilicon layer 82.

[0114] The polysilicon layer 82 is a doped layer formed using doped polysilicon doped with impurities, and has a dopant concentration of, for example, 1e19 to 1e21 cm -3 It is preferable that the polysilicon layer 82 is a highly doped layer doped with impurities at a high concentration of 5000 to 1000 Å. When forming the polysilicon layer 82 as a doped layer (including a highly doped layer), an N-type impurity such as phosphorus (P) or arsenic (As) or a P-type impurity such as boron (B) can be used as the impurity. The polysilicon layer 82 fills the contact hole 80. The thickness of the polysilicon layer 82 varies depending on the depth of the contact hole 80, and is, for example, 5000 to 1000 Å.

[0115] The metal layer 83 is formed using, for example, aluminum (Al), gold (Au), silver (Ag), copper (Cu), or an alloy or metal material containing these. The metal layer 83 forms the outermost layer of the source wiring 81, and is connected (bonded) to, for example, the first wire 60U. The thickness of the metal layer 83 is, for example, 1 to 5 μm.

[0116] In the source wiring 81, an intermediate layer 84 containing titanium (Ti) is interposed between the polysilicon layer 82 and the metal layer 83. The intermediate layer 84 is made of a single layer containing titanium or a plurality of layers including the titanium layer. The layer containing titanium can be formed using titanium, titanium nitride (TiN), or the like. The thickness of the intermediate layer 84 is, for example, 200 to 500 nm.

[0117] The source wiring 81 having such a polysilicon layer 82, intermediate layer 84, and metal layer 83 preferably has a laminated structure (Po-Si / Ti / TiN / Al) in which polysilicon (polysilicon layer 82), titanium (intermediate layer 84), titanium nitride (intermediate layer 84), and aluminum (metal layer 83) are laminated in this order.

[0118] A drain wiring 85 is formed on the rear surface 70B of the SiC substrate 70. The drain wiring 85 is in contact (electrically connected) with the SiC substrate 70. The drain wiring 85 has a polysilicon layer 86 at a contact portion with the SiC substrate 70, and has a metal layer 87 on the polysilicon layer 86.

[0119] The polysilicon layer 86 can be formed using the same material as that of the polysilicon layer 82. The thickness of the polysilicon layer 86 is, for example, 1000 to 2000 Å.

[0120] The metal layer 87 can be formed using the same material as that of the metal layer 83. The metal layer 87 forms the outermost layer of the drain wiring 85, and is joined to the island portion 31a when, for example, the SiC substrate 70 is mounted on the island portion 31a of the frame 31. The thickness of the metal layer 87 is, for example, 0.5 to 1 μm.

[0121] In the drain wiring 85, an intermediate layer 88 containing titanium (Ti) is interposed between the polysilicon layer 86 and the metal layer 87. The intermediate layer 88 can be formed using the same material as that constituting the intermediate layer 84.

[0122] A gate wiring 89 is in contact (electrically connected) with the gate electrode 76 via a contact hole (not shown) formed in the interlayer insulating film 79 . With a predetermined potential difference being generated between the source wiring 81 and the drain wiring 85 (between the source and drain), a predetermined voltage (a voltage equal to or higher than the gate threshold voltage) is applied to the gate wiring 89, whereby an electric field from the gate electrode 76 forms a channel in the body region 73 near the interface with the gate insulating film 75. As a result, a current flows between the source wiring 81 and the drain wiring 85, turning on the MOSFET 11U.

[0123] [Configuration of low potential block circuit] The circuit configuration of the low potential block circuit in the control circuit 20 will be described with reference to Fig. 12. Fig. 12 shows an example of the circuit configuration of the low potential block circuit.

[0124] 12, the integrated circuit element 25L has a first output terminal 25au, a second output terminal 25av, a third output terminal 25aw, a first input terminal 25bu, a second input terminal 25bv, and a third input terminal 25bw. The first output terminal 25au and the first input terminal 25bu are electrically connected to the control circuit 20 (specifically, the drive circuit 21UL of the control circuit 20). The second output terminal 25av and the second input terminal 25bv are electrically connected to the control circuit 20 (specifically, the drive circuit 21VL of the control circuit 20). The third output terminal 25aw and the third input terminal 25bw are electrically connected to the control circuit 20 (specifically, the drive circuit 21WL of the control circuit 20).

[0125] The first output terminal 25au is connected to the gate of the MOSFET 12U via the first wire 62U. The first input terminal 25bu is connected to the source of the MOSFET 12U via the first wire 63U. The second output terminal 25av is connected to the gate of the MOSFET 12V via the second wire 62V. The second input terminal 25bv is connected to the source of the MOSFET 12V via the second wire 63V. The third output terminal 25aw is connected to the gate of the MOSFET 12W via the third wire 62W. The third input terminal 25bw is connected to the source of the MOSFET 12W via the third wire 63W.

[0126] The drive circuit 21UL has a common-source circuit 21a serving as an output stage. The common-source circuit 21a has a first MOSFET 21b serving as a P-channel MOSFET and a second MOSFET 21c serving as an N-channel MOSFET. The source of the first MOSFET 21b is electrically connected to a power supply voltage terminal (frame 34CV), and the drain of the first MOSFET 21b is connected to the drain of the second MOSFET 21c. The gate of the first MOSFET 21b and the gate of the second MOSFET 21c are commonly connected. The drive circuit 21UL has an output wiring 21d that connects a node N1 between the drain of the first MOSFET 21b and the drain of the second MOSFET 21c to a first output terminal 25au of the integrated circuit element 25L, and a restriction wiring 21e that connects the source of the second MOSFET 21c of the common-source circuit 21a to a first input terminal 25bu of the integrated circuit element 25L. The output wiring 21d and the restriction wiring 21e are each provided in the integrated circuit element 25L. More specifically, the output wiring 21d and the limiting wiring 21e are provided closer to the first output terminal 25au and the first input terminal 25bu than the common-source circuit 21a in the second direction Y. The second MOSFET 21c of the common-source circuit 21a in the drive circuit 21UL is electrically connected to the source of the MOSFET 12U via the limiting wiring 21e, the first input terminal 25bu, and the first wire 63U.

[0127] The configurations of the drive circuit 21VL and the drive circuit 21WL are the same as that of the drive circuit 21UL. The output wiring 21d of the drive circuit 21VL connects the node N1 between the drain of the first MOSFET 21b and the drain of the second MOSFET 21c to the second output terminal 25av of the integrated circuit element 25L. The limiting wiring 21e of the drive circuit 21VL connects the source of the second MOSFET 21c of the source ground circuit 21a to the second input terminal 25bv of the integrated circuit element 25L. The second MOSFET 21c of the source ground circuit 21a in the drive circuit 21VL is electrically connected to the source of the MOSFET 12V via the limiting wiring 21e, the second input terminal 25bv, and the second wire 63V. The output wiring 21d of the drive circuit 21WL connects the node N1 between the drain of the first MOSFET 21b and the drain of the second MOSFET 21c to the third output terminal 25aw of the integrated circuit element 25L. The limiting wiring 21e of the drive circuit 21WL connects the source of the second MOSFET 21c of the source-grounded circuit 21a to the third input terminal 25bw of the integrated circuit element 25L. The second MOSFET 21c of the source-grounded circuit 21a in the drive circuit 21WL is electrically connected to the source of the MOSFET 12V via the limiting wiring 21e, the third input terminal 25bw, and the third wire 63W.

[0128] Thus, the semiconductor device 1 has a first control path RC1 that electrically connects the drive circuit 21UL and the gate (control terminal) of the MOSFET 12U, a second control path RC2 that electrically connects the drive circuit 21VL and the gate (control terminal) of the MOSFET 12V, and a third control path RC3 that electrically connects the drive circuit 21WL and the gate (control terminal) of the MOSFET 12W.

[0129] The first control path RC1 transmits a drive signal of the drive circuit 21UL to the gate of the MOSFET 12U. The first control path RC1 includes the output wiring 21d of the drive circuit 21UL and a first wire 62U. That is, the first wire 62U constitutes a part of the first control path RC1.

[0130] The second control path RC2 transmits a drive signal of the drive circuit 21VL to the gate of the MOSFET 12V. The second control path RC2 has the output wiring 21d of the drive circuit 21VL and a second wire 62V. That is, the second wire 62V constitutes a part of the second control path RC2.

[0131] The third control path RC3 transmits a drive signal of the drive circuit 21WL to the gate of the MOSFET 12W. The third control path RC3 has the output wiring 21d of the drive circuit 21WL and a third wire 62W. That is, the third wire 62W constitutes a part of the third control path RC3.

[0132] The semiconductor device 1 also has a first restriction path RS1 that electrically connects the first control path RC1 to the source (second terminal) of the MOSFET 12U, a second restriction path RS2 that electrically connects the second control path RC2 to the source (second terminal) of the MOSFET 12V, and a third restriction path RS3 that electrically connects the third control path RC3 to the source (second terminal) of the MOSFET 12W.

[0133] The first restriction path RS1 includes the restriction wiring 21e of the drive circuit 21UL and a first wire 63U. That is, the first wire 63U constitutes a part of the first restriction path RS1. The second restriction path RS2 includes the restriction wiring 21e of the drive circuit 21VL and a second wire 63V. That is, the second wire 63V constitutes a part of the second restriction path RS2. The third restriction path RS3 includes the restriction wiring 21e of the drive circuit 21WL and a third wire 63W. That is, the third wire 63W constitutes a part of the third restriction path RS3.

[0134] Each of the logic circuits 22UL, 22VL, and 22WL includes an RS flip-flop circuit 22a. The RS flip-flop circuit 22a includes a set terminal (S terminal) to which a set signal is input, a reset terminal (R terminal) to which a reset signal is input, and an output terminal (Q terminal) to which an output signal is output. The RS flip-flop circuit 22a sets an output signal to a high level using a falling edge of the set signal as a trigger, and sets an output signal to a low level using a falling edge of the reset signal as a trigger. The RS flip-flop circuit 22a is electrically connected to the gates of the MOSFETs 21b and 21c, and outputs an output signal to the gates. The MOSFETs 21b and 21c are complementarily turned on and off based on the output signal of the RS flip-flop circuit 22a. This generates a drive signal, which is output to the gate of the MOSFET 12L via the output wiring 21d.

[0135] The operation of this embodiment will be described. The semiconductor device 1 includes a limiting unit that suppresses fluctuations in the source-gate voltage of the MOSFET 12U. More specifically, as shown in Fig. 12, the semiconductor device 1 includes a first limiting unit CV1 as the limiting unit. The first limiting unit CV1 is a mechanism that suppresses fluctuations in the source-gate voltage of the MOSFET 12U that are caused by voltage fluctuations at the source of the MOSFET 12U, and includes a first limiting path RS1.

[0136] Since the first limiting section CV1 (first limiting path RS1) electrically connects the source of the second MOSFET 21c of the source ground circuit 21a of the drive circuit 21UL to the source of the MOSFET 12U, even if the source potential of the MOSFET 12U rises due to the current change dI / dt when the MOSFET 11U is turned on and the inductance of the first wire 61U connected to the source of the MOSFET 12U, the source potential of the second MOSFET 21c of the source ground circuit 21a of the drive circuit 21UL follows and rises, so that the gate-source voltage of the MOSFET 12U is prevented from becoming negative. As a result, the fluctuation of the threshold voltage Vth of the MOSFET 12U is suppressed. As a result, even if the intermittent operation of the first inverter circuit 10U is repeated, the increase in the fluctuation rate of the threshold voltage Vth of the MOSFET 12U is suppressed.

[0137] The semiconductor device 1 also includes a second limiting unit CV2 and a third limiting unit CV3 as limiting units. The second limiting unit CV2 is a mechanism for suppressing fluctuations in the source-gate voltage of the MOSFET 12V due to voltage fluctuations at the source of the MOSFET 12V, and has a second limiting path RS2. The third limiting unit CV3 is a mechanism for suppressing fluctuations in the source-gate voltage of the MOSFET 12W due to voltage fluctuations at the source of the MOSFET 12W, and has a third limiting path RS3. With this configuration, the increase in the rate of change of the threshold voltages Vth of the MOSFETs 12L and 12L is suppressed for the MOSFETs 12V and 12L, as with the MOSFET 12U.

[0138] According to this embodiment, the following effects can be obtained. (1-1) The semiconductor device 1 includes a first limiting unit CV1 (first limiting path RS1), a second limiting unit CV2 (second limiting path RS2), and a third limiting unit CV3 (third limiting path RS3). According to this configuration, even if the source potential of the MOSFET 12U fluctuates, the gate potential of the MOSFET 12U follows and fluctuates accordingly, so that fluctuations in the source-gate voltage of the MOSFET 12U are suppressed. Even if the source potential of the MOSFET 12V fluctuates, the gate potential of the MOSFET 12V follows and fluctuates accordingly, so that fluctuations in the source-gate voltage of the MOSFET 12V are suppressed. Even if the source potential of the MOSFET 12W fluctuates, the gate potential of the MOSFET 12W follows and fluctuates accordingly, so that fluctuations in the source-gate voltage of the MOSFET 12W are suppressed. Therefore, it is possible to suppress fluctuations in the threshold voltage Vth for each of the MOSFETs 12U to 12W.

[0139] (1-2) The first wire 63U constituting a part of the first restriction path RS1 is connected to the source electrode pad 12s of the MOSFET 12U. As a result, the potential of the source side of the MOSFET 12U can be extracted as the source side of the MOSFET 12U rather than the first wire 61U connected to the source electrode pad 12s of the MOSFET 12U. As a result, the MOSFET 12U can be controlled by the gate-source voltage of the MOSFET 12U in which the influence of the inductance of the first wire 61U is suppressed. In addition, the second wire 63V constituting a part of the second restriction path RS2 is connected to the source electrode pad 12s of the MOSFET 12V. The third wire 63W constituting a part of the third restriction path RS3 is connected to the source electrode pad 12s of the MOSFET 12W. In this way, since the second wire 63V and the third wire 63W have the same configuration as the first wire 63U, the same effect as the first wire 63U can be obtained.

[0140] In addition, since the distance between the MOSFETs 12U-12W and the integrated circuit element 25L is shorter than the distance between the frames 35U, 35V, 35W and the integrated circuit element 25L, the length of each of the wires 62U, 62V, 62W and the length of each of the wires 63U, 63V, 63W connecting the sources of the MOSFETs 12U-12W and the integrated circuit element 25L can be shortened. Therefore, the influence of the inductance of each of the wires 62U, 62V, 62W and the influence of the inductance of each of the wires 63U, 63V, 63W can be reduced.

[0141] (1-3) The MOSFET 12U is disposed at an end of the region Ra7 of the element mounting region Rse of the first frame 32U on the integrated circuit element 25L side in the second direction Y. This shortens the distance between the MOSFET 12U and the integrated circuit element 25L, and therefore the lengths of the first wires 62U and 63U connecting the MOSFET 12U and the integrated circuit element 25L can be shortened. This reduces the influence of the inductance of the first wires 62U and 63U. The MOSFET 12V is disposed at an end of the region Ra7 of the element mounting region Rse of the second frame 32V on the integrated circuit element 25L side in the second direction Y. The MOSFET 12W is disposed at an end of the region Ra7 of the element mounting region Rse of the third frame 32W on the integrated circuit element 25L side in the second direction Y. With this configuration, similar to the first wire 62U and the first wire 63U, the length of each wire 62V, 62W and the length of each wire 63V, 63W can be shortened, thereby reducing the influence of the inductance of each wire 62V, 62W and the influence of the inductance of each wire 63V, 63W.

[0142] (1-4) The first wire 63U is connected to a portion of the source electrode pad 12s of the MOSFET 12U that is closer to the integrated circuit element 25L. The second wire 63V is connected to a portion of the source electrode pad 12s of the MOSFET 12V that is closer to the integrated circuit element 25L. The third wire 63W is connected to a portion of the source electrode pad 12s of the MOSFET 12W that is closer to the integrated circuit element 25L. With this configuration, the length of each of the wires 63U, 63V, and 63W can be shortened. Therefore, the influence of the inductance of each of the wires 63U, 63V, and 63W can be reduced.

[0143] (1-5) Each of the wires 63U, 63V, 63W is connected to an end of the integrated circuit element 25L on the MOSFET 12U-12W side in the second direction Y. This allows the length of each of the wires 63U, 63V, 63W to be shortened. This allows the influence of the inductance of each of the wires 63U, 63V, 63W to be reduced.

[0144] (1-6) Grooves 32g and 32h that form the element mounting region Rse are formed in each of the frames 32U, 32V, and 32W. This makes it possible to prevent the solder SD from spreading beyond the element mounting region Rse when the MOSFETs 12U to 12W are mounted in the region Ra7 of the element mounting region Rse. Assuming that the molten solder SD is approaching, the edges of the grooves 32g and 32h are expected to have the effect of preventing the solder SD from exceeding the grooves 32g and 32h due to the action of surface tension, and to keep the molten solder SD in the grooves 32g and 32h. Since the grooves 32g and 32h are formed to surround the entire periphery of each of the MOSFETs 12U to 12W, the spreading of the solder SD can be further prevented. Since the grooves 31d and 31e of the frame 31 have a configuration similar to that of the grooves 32g and 32h, it is possible to prevent the solder SD from spreading beyond the element mounting area Rse when the MOSFETs 11U to 11W are mounted in the element mounting area Rse.

[0145] (1-7) A plurality of recesses 31f are provided in the frame 31, and a plurality of recesses 32i are provided in each of the frames 32U, 32V, and 32W. With this configuration, the sealing resin 50 fills the recesses 31f and 32i, thereby increasing the bonding strength of the sealing resin 50 to the frame 31 and each of the frames 32U, 32V, and 32W. This makes it possible to prevent the sealing resin 50 from peeling off from the frame 31 and each of the frames 32U, 32V, and 32W.

[0146] (1-8) The recesses 31f and 32i are not provided in the element mounting region Rse. This allows the MOSFETs 11U to 11W to be properly joined to the frame 31 by solder SD, and the MOSFETs 12U to 12W to the frames 32U, 32V, and 32W by solder SD. In addition, the recesses 31f of the frame 31 are arranged so as to surround the element mounting region Rse. This allows the sealing resin 50 to surround the MOSFETs 11U to 11W and be firmly joined to the island portion 31a of the frame 31. In addition, the recesses 32i of each of the frames 32U, 32V, and 32W are arranged so as to surround the element mounting region Rse. This allows the sealing resin 50 to surround the MOSFETs 12U to 12W and be firmly joined to the island portion 33a of each of the frames 32U, 32V, and 32W. In this way, it is possible to prevent the formation of gaps in the sealing resin 50 that communicate with the MOSFETs 11U to 11W and the MOSFETs 12U to 12W due to peeling of the sealing resin 50. This makes it possible to maintain a good insulating state of the MOSFETs 11U to 11W and the MOSFETs 12U to 12W.

[0147] Second embodiment The semiconductor device 1 of the second embodiment will be described with reference to Figures 13 and 14. The semiconductor device 1 of this embodiment is different from the semiconductor device 1 of the first embodiment in the configurations of the drive circuits 21UL, 21VL, and 21WL. In the following description, the same reference numerals are used to designate configurations common to the semiconductor device 1 of the first embodiment, and descriptions thereof may be omitted.

[0148] As shown in FIG. 13, the first limiting unit CV1 has a diode 13 provided in the first limiting path RS1. The second limiting unit CV2 has a diode 13 provided in the second limiting path RS2. The third limiting unit CV3 has a diode 13 provided in the third limiting path RS3. Each diode 13 is mounted on the integrated circuit element 25L. In detail, the diode 13 of the first limiting unit CV1 is provided in the limiting wiring 21e of the drive circuit 21UL. The anode of this diode 13 is electrically connected to the first input terminal 25bu, and the cathode is electrically connected to the node N2 of the output wiring 21d of the drive circuit 21UL. The diode 13 of the second limiting unit CV2 is provided in the limiting wiring 21e of the drive circuit 21VL. The anode of this diode 13 is electrically connected to the second input terminal 25bv, and the cathode is electrically connected to the node N2 of the output wiring 21d of the drive circuit 21VL. The diode 13 of the third limiting unit CV3 is provided on the limiting wiring 21e of the drive circuit 21WL. The anode of the diode 13 is electrically connected to the third input terminal 25bw, and the cathode is electrically connected to the node N2 of the output wiring 21d of the drive circuit 21WL.

[0149] 14, in the integrated circuit element 25L, the drive circuit 21UL, the drive circuit 21VL, and the drive circuit 21WL are arranged along the first direction X. That is, the drive circuit 21UL, the drive circuit 21VL, and the drive circuit 21WL are arranged along the longitudinal direction of the integrated circuit element 25L. Here, the direction in which the drive circuit 21UL, the drive circuit 21VL, and the drive circuit 21WL are arranged (first direction X) is an example of the arrangement direction of the third control circuit, the fourth control circuit, and the fifth control circuit.

[0150] The diode 13 of the first limiting unit CV1 is disposed around the common source circuit 21a of the drive circuit 21UL. More specifically, the diode 13 of the first limiting unit CV1 is disposed closer to the first output terminal 25au and the first input terminal 25bu, i.e., closer to the MOSFET 12U, than the common source circuit 21a of the drive circuit 21UL in the second direction Y.

[0151] The diode 13 of the second limiting unit CV2 is disposed around the common source circuit 21a of the drive circuit 21VL. More specifically, the diode 13 of the second limiting unit CV2 is disposed closer to the second output terminal 25av and the second input terminal 25bv, i.e., the MOSFET 12V, than the common source circuit 21a of the drive circuit 21VL in the second direction Y.

[0152] The diode 13 of the third limiting unit CV3 is disposed around the common source circuit 21a of the drive circuit 21WL. More specifically, the diode 13 of the third limiting unit CV3 is disposed closer to the third output terminal 25aw and the third input terminal 25bw, i.e., closer to the MOSFET 12W, than the common source circuit 21a of the drive circuit 21WL in the second direction Y.

[0153] The operation of this embodiment will be described below. Since the operation of each of the inverter circuits 10U, 10V, and 10W is the same, the operation of the first inverter circuit 10U will be described, and the explanation of the operation of the second inverter circuit 10V and the third inverter circuit 10W will be omitted.

[0154] When the MOSFET 11U of the first inverter circuit 10U is turned on, the source potential of the MOSFET 12U rises due to the change dI / dt of the current flowing through the MOSFET 11U and the inductance of the first wire 61U connected to the MOSFET 12U. Accordingly, the potential of the output wiring 21d of the drive circuit 21UL rises via the first wire 63U connected to the source of the MOSFET 12U and the limiting wiring 21e of the integrated circuit element 25L. Therefore, the gate-source voltage of the MOSFET 12U is prevented from becoming a negative value, and therefore the fluctuation of the threshold voltage Vth of the MOSFET 12U can be suppressed.

[0155] According to this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained. (2-1) The limiting wiring 21e of the drive circuits 21UL, 21VL, and 21WL is provided with a diode 13. This prevents the source potential of the MOSFETs 12U to 12W from increasing due to the output voltage of the drive circuits 21UL, 21VL, and 21WL when the MOSFETs 12U to 12W are turned on. This makes it possible to control the current flowing through each of the MOSFETs 12U to 12W with high precision.

[0156] (2-2) The diode 13 of the first limiting unit CV1 is disposed closer to the first output terminal 25au and the first input terminal 25bu than the source ground circuit 21a of the drive circuit 21UL. The diode 13 of the second limiting unit CV2 is disposed closer to the second output terminal 25av and the second input terminal 25bv than the source ground circuit 21a of the drive circuit 21VL. The diode 13 of the third limiting unit CV3 is disposed closer to the third output terminal 25aw and the third input terminal 25bw than the source ground circuit 21a of the drive circuit 21WL. This allows the length of the limiting wiring 21e of the drive circuits 21UL, 21VL, and 21WL to be shortened, and the influence of the inductance of the limiting wiring 21e to be reduced.

[0157] (2-3) Each diode 13 is provided within integrated circuit element 25L. With this configuration, semiconductor device 1 can be made smaller than in a configuration in which each diode 13 is provided as a semiconductor chip separate from integrated circuit element 25L.

[0158] Third embodiment 9 and 15, the semiconductor device 1 of the third embodiment will be described. The semiconductor device 1 of the present embodiment is different from the semiconductor device 1 of the first embodiment in the arrangement of the MOSFETs 12U. In the following description, the same reference numerals are used to designate configurations common to the configuration of the semiconductor device 1 of the first embodiment, and the description thereof may be omitted.

[0159] As shown in Fig. 9, in the first embodiment, the orientation (position) of each of the MOSFETs 12U-12W mounted on each of the frames 32U, 32V, 32W is the same. The MOSFETs 12U-12W in Fig. 9 are mounted on each of the frames 32U, 32V, 32W such that the second direction Y is the longitudinal direction. In this case, the first wires 62U and 63U of the MOSFET 12U of the first frame 32U arranged closest to the frame 31 among the frames 32U, 32V, 32W are long.

[0160] Therefore, in this embodiment, as shown in Fig. 15, the orientation (position) of the MOSFET 12U mounted on the first frame 32U is different from the orientation (position) of the MOSFET 12V mounted on the second frame 32V and the orientation (position) of the MOSFET 12W mounted on the third frame 32W. In detail, the MOSFET 12U of the first frame 32U is mounted on the first frame 32U such that the first direction X is the longitudinal direction. Furthermore, the MOSFET 12U is mounted on the first frame 32U such that its gate electrode pad 12g is close to the integrated circuit element 25L. More specifically, the MOSFET 12U is mounted on the first frame 32U such that its gate electrode pad 12g is on the MOSFET 12V side in the first direction X and on the frame 34 side in the second direction Y on the surface of the MOSFET 12U.

[0161] In this embodiment, the first wire 63U connecting the source electrode pad 12s of the MOSFET 12U to the integrated circuit element 25L and the first wire 62U connecting the gate electrode pad 12g of the MOSFET 12U to the integrated circuit element 25L are arranged differently. In more detail, the first wire 62U is arranged closer to the second frame 32V than the first wire 63U. The first wire 62U is connected to a region of the source electrode pad 12s adjacent to the gate electrode pad 12g in the first direction X and on the frame 33 side.

[0162] According to this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained. (3-1) The MOSFET 12U mounted on the first frame 32U is disposed on the first frame 32U so that its gate electrode pad 12g is close to the integrated circuit element 25L, and therefore the length of the first wire 62U connecting the gate electrode pad 12g and the integrated circuit element 25L can be shortened, thereby reducing the effect of the inductance of the first wire 62U.

[0163] (Fourth embodiment) A semiconductor device 1 of a fourth embodiment will be described with reference to Figures 16, 17, 18A, and 18B. The semiconductor device 1 of this embodiment is different from the semiconductor device 1 of the first embodiment in that a limiting unit that suppresses fluctuations in the potential of the sources of the MOSFETs 12U-12W when the MOSFETs 11U-11W are on is provided instead of the limiting unit of the semiconductor device 1 of the first embodiment. In the following description, the same reference numerals are used to designate configurations common to the configuration of the semiconductor device 1 of the first embodiment, and descriptions thereof may be omitted.

[0164] As shown in Figure 16, the semiconductor device 1 has a first limiting portion CP1, a second limiting portion CP2, and a third limiting portion CP3 as limiting portions instead of the first limiting portion CV1, the second limiting portion CV2, and the third limiting portion CV3 (all see Figure 14) as limiting portions of the first embodiment.

[0165] The first limiting unit CP1 is a mechanism that suppresses fluctuations in the potential of the source of the MOSFET 12U when the MOSFET 11U is on. The first limiting unit CP1 has a first diode 14U, which is an example of a sixth diode connected to the second switching element of the first inverter circuit 10U. The anode of the first diode 14U is connected to the source of the MOSFET 12U, and the cathode of the first diode 14U is connected to the drain of the MOSFET 12U.

[0166] The second limiting unit CP2 is a mechanism that suppresses fluctuations in the potential of the source of the MOSFET 12V when the MOSFET 11V is on. The second limiting unit CP2 has a second diode 14V, which is an example of a seventh diode, connected to the second switching element of the second inverter circuit 10V. The anode of the second diode 14V is connected to the source of the MOSFET 12V, and the cathode of the second diode 14V is connected to the drain of the MOSFET 12V.

[0167] The third limiting unit CP3 is a mechanism that suppresses fluctuations in the potential of the source of the MOSFET 12W when the MOSFET 11W is on. The third limiting unit CP3 has a third diode 14W, which is an example of an eighth diode connected to the second switching element of the third inverter circuit 10W. The anode of the third diode 14W is connected to the source of the MOSFET 12W, and the cathode of the third diode 14W is connected to the drain of the MOSFET 12W.

[0168] An example of each of the diodes 14U, 14V, and 14W is a Schottky barrier diode. In this embodiment, the first diode 14U is configured so that its forward voltage Vf is lower than the forward voltage of the body diode of the MOSFET 12U. The second diode 14V is configured so that its forward voltage Vf is lower than the forward voltage of the body diode of the MOSFET 12V. The third diode 14W is configured so that its forward voltage is lower than the forward voltage of the body diode of the MOSFET 12W. As shown in FIG. 17, each of the diodes 14U, 14V, and 14W is formed of a semiconductor chip. The first diode 14U is mounted in the region Ra8 of the first frame 32U, the second diode 14V is mounted in the region Ra8 of the second frame 32V, and the third diode 14W is mounted in the region Ra8 of the third frame 32W. Each of the diodes 14U, 14V, and 14W is located closer to the fourth side surface 50F of the sealing resin 50 in the second direction Y in the region Ra8.

[0169] Each of the diodes 14U, 14V, and 14W has an anode electrode pad 14a, which is a front electrode, and a cathode electrode, which is a back electrode. The cathode electrode of the first diode 14U is electrically connected to the first frame 32U by solder or the like. The cathode electrode of the second diode 14V is electrically connected to the second frame 32V by solder or the like. The cathode electrode of the third diode 14W is electrically connected to the third frame 32W by solder or the like.

[0170] As shown in FIG. 17, the first limiting portion CP1 further includes a first wire 61U and a first diode wire 64U, which is an example of a fourth diode wire provided separately from the first wire 61U. The first wire 61U connects the source electrode pad 12s of the MOSFET 12U of the first frame 32U to the island portion 35a of the frame 35U. The first wire 61U passes through the second diode 14V of the second frame 32V and the connection portion 32c of the third frame 32W to be connected to the frame 35U. The first diode wire 64U connects the anode electrode pad 14a of the first diode 14U to the island portion 35a of the frame 35U. The first diode wire 64U passes through the connection portion 32c of the frame 32V and the connection portion 32c of the frame 32W to be connected to the frame 35U. In the island portion 35a of the frame 35U, the position where the first wire 61U is connected and the position where the first diode wire 64U is connected are different from each other. More specifically, the position where the first wire 61U is connected to the island portion 35a of the frame 35U is located closer to the connection portion 32c of the third frame 32W than the position where the first diode wire 64U is connected to the island portion 35a of the frame 35U.

[0171] The second limiting portion CP2 further includes a second wire 61V and a second diode wire 64V, which is an example of a fifth diode wire provided separately from the second wire 61V. The second wire 61V connects the source electrode pad 12s of the MOSFET 12V of the second frame 32V to the island portion 35a of the frame 35V. The second wire 61V passes through the third diode 14W of the third frame 32W and is connected to the frame 35V. The second diode wire 64V connects the anode electrode pad 14a of the second diode 14V to the island portion 35a of the frame 35V. The second diode wire 64V passes through an end of the island portion 32a of the frame 32W on the connection portion 32c side and is connected to the frame 35V. In the island portion 35a of the frame 35V, the position to which the second wire 61V is connected and the position to which the second diode wire 64V is connected are different from each other. More specifically, the position where the second wire 61V is connected to the island portion 35a of the frame 35V is located closer to the island portion 35a of the frame 35U than the position where the second diode wire 64V is connected to the island portion 35a of the frame 35V.

[0172] The third limiting portion CP3 further includes a third wire 61W and a third diode wire 64W, which is an example of a sixth diode wire provided separately from the third wire 61W. The third wire 61W connects the source electrode pad 12s of the MOSFET 12W of the third frame 32W to the island portion 35a of the frame 35W. The third wire 61W passes through a portion of the frame 32W that is closer to the region Ra7 than the third diode 14W and is connected to the frame 35W. The third diode wire 64W connects the anode electrode pad 14a of the third diode 14W to the island portion 35a of the frame 35W. In the island portion 35a of the frame 35W, the position to which the third wire 61W is connected is different from the position to which the third diode wire 64W is connected. More specifically, the position where the third wire 61W is connected to the island portion 35a of the frame 35W is located closer to the island portion 32a of the third frame 32W than the position where the third diode wire 64W is connected to the island portion 35a of the frame 35W.

[0173] The diode wires 64U, 64V, 64W are made of, for example, aluminum (Al). The diode wires 64U, 64V, 64W have the same wire diameter as each other. The diode wires 64U, 64V, 64W have the same wire diameter as each wire 61U, 61V, 61W.

[0174] [Structure of the first to third diodes] Next, an example of the structure of each of the diodes 14U, 14V, and 14W will be described with reference to Figures 18A and 18B. Since the structures of the diodes 14U, 14V, and 14W are the same, the structure of the first diode 14U will be described below, and descriptions of the structures of the second diode 14V and the third diode 14W will be omitted.

[0175] The first diode 14U is N + For example, N-type impurity concentration is 1e18 to 1e21 cm -3The semiconductor device includes a silicon substrate 90 having a thickness of 100 nm to 150 nm. A cathode electrode 91 is formed on the back surface of the silicon substrate 90 so as to cover the entire surface of the silicon substrate 90. The cathode electrode 91 is made of a metal (e.g., gold (Au), nickel (Ni), silicide, cobalt (Co) silicide, etc.) that is in ohmic contact with N-type silicon.

[0176] The surface of the silicon substrate 90 has a lower concentration of N - For example, N-type impurity concentration is 1e15 to 1e17 cm -3 ) is laminated on an epitaxial layer 92 (semiconductor layer). The thickness of the epitaxial layer 92 is, for example, 2 μm to 20 μm.

[0177] A field insulating film 93 made of, for example, silicon oxide (SiO2) is laminated on the surface of the epitaxial layer 92. The thickness of the field insulating film 93 is, for example, 1000 Å or more, and preferably 7000 Å to 40000 Å. The field insulating film 93 may be made of other insulators such as silicon nitride (SiN).

[0178] The field insulating film 93 has an opening 94 that exposes the center of the epitaxial layer 92. A plurality of trenches 95 are formed in the surface layer of the center of the epitaxial layer 92 by digging the epitaxial layer 92 from the surface. Each trench 95 is a vertical groove extending in a predetermined direction. The bottom surface of the trench 95 is a plane along the surface of the epitaxial layer 92. Therefore, the cross section of each trench 95 is approximately rectangular. In this embodiment, seven trenches 95 extend in parallel at a predetermined interval. That is, the seven trenches 95 are formed in a stripe shape in a plan view.

[0179] A mesa portion 96 is formed in a portion of the surface layer of the epitaxial layer 92 that is sandwiched between adjacent trenches 95. When the trenches 95 have a substantially rectangular cross section, the mesa portion 96 accordingly has a substantially rectangular cross section. Each mesa portion 96 has a pair of sidewall surfaces (sidewall surfaces of the trenches 95) that rise, for example, substantially vertically from one side edge of the bottom surfaces of a pair of adjacent trenches 95, and a top surface (the surface of the epitaxial layer 92) that connects the pair of sidewall surfaces.

[0180] An anode electrode 97 is formed on the epitaxial layer 92. The anode electrode 97 fills the opening 94 of the field insulating film 93 and protrudes outward from the opening 94 so as to cover a peripheral portion 98 of the opening 94 in the field insulating film 93. That is, the peripheral portion 98 of the field insulating film 93 is sandwiched from above and below all around by the epitaxial layer 92 and the anode electrode 97. The amount of protrusion of the anode electrode 97 covering the peripheral portion 98 of the field insulating film 93 from the end of the opening 94 of the field insulating film 93 is, for example, 10 μm or more, preferably 10 μm to 100 μm.

[0181] The anode electrode 97 has a multi-layer structure (two-layer structure in this embodiment) including a Schottky metal 99 joined to the epitaxial layer 92 within an opening 94 in the field insulating film 93 and a contact metal 100 laminated on the Schottky metal 99.

[0182] The Schottky metal 99 is made of a metal (e.g., titanium (Ti), molybdenum (Mo), palladium (Pd), etc.) that forms a Schottky junction by bonding with N-type silicon. Titanium is used as the Schottky metal 99 in this embodiment. The Schottky metal 99 is formed so as to contact the surface of the epitaxial layer 92 including the inner wall surface (bottom surface and a pair of side wall surfaces) of the trench 95. Therefore, the Schottky metal 99 contacts the surface of the epitaxial layer 92 on the inner wall surfaces of all the trenches 95 and outside the trenches 95. The Schottky metal 99 also covers the entire inner wall surface of each trench 95 and extends continuously to the outside of the trenches 95. In other words, the Schottky metal 99 is bonded to the surface of the epitaxial layer 92 exposed from the opening 94 of the field insulating film 93 so as to completely cover the entire surface. The Schottky metal 99 of this embodiment includes a bottom portion 99a in contact with the bottom surface of the trench 95, a side portion 99b in contact with the sidewall surface of the trench 95 (the sidewall surface of the mesa portion 96), and a top portion 99c in contact with the top surface of the mesa portion 96.

[0183] In this case, as shown by the bold line in FIG. 18B, the junction surface (Schottky junction surface) S between the Schottky metal 99 and the surface of the epitaxial layer 92 is formed to have an uneven cross section in the region inside the opening 94 of the field insulating film 93. Therefore, the area of ​​the Schottky junction surface S is larger than the apparent area of ​​the epitaxial layer 92 in a plan view along the normal direction of the surface of the epitaxial layer 92 (the portion extending horizontally in FIG. 18B). In more detail, the Schottky junction surface S includes a bottom surface portion S1 in contact with the bottom surface of the trench 95, a side surface portion S2 in contact with the side wall surface of the trench 95 (the side wall surface of the mesa portion 96), and a top surface portion S3 in contact with the top surface of the mesa portion 96. When the trench 95 has a substantially rectangular cross section, the area of ​​the Schottky junction surface S can be made larger by the side surface portion S2 compared to when the trench 95 is not formed.

[0184] The Schottky metal 99 bonded to the epitaxial layer 92 forms a Schottky barrier (potential barrier) of, for example, 0.52 eV to 0.9 eV between it and the silicon semiconductor that constitutes the epitaxial layer 92. The thickness of the Schottky metal 99 in this embodiment is 0.02 μm to 0.2 μm.

[0185] The contact metal 100 is a portion of the anode electrode 97 that is exposed on the outermost surface of the first diode 14U and to which the first diode wire 64U (see FIG. 17) or the like is bonded. That is, the contact metal 100 constitutes the anode electrode pad 14a. The contact metal 100 is made of, for example, aluminum (Al). The thickness of the contact metal 100 in this embodiment is, for example, 0.5 μm to 5 μm. The contact metal 100 is embedded in each trench 95 so as to be in contact with the Schottky metal 99 covering the inner wall surface of each trench 95. That is, the contact metal 100 is in contact with a bottom surface portion 99a, a pair of side surfaces 99b, and a top surface portion 99c of the Schottky metal 99. Therefore, the contact metal 100 is formed to have an uneven cross section on the side of each trench 95 that is in contact with the Schottky metal 99. On the other hand, the surface of the contact metal 100 opposite to the side in contact with the Schottky metal 99 is formed flat along the surface of the epitaxial layer 92 (excluding the inner wall surface of the trench 95).

[0186] When the Schottky metal 99 is made of titanium, it is preferable that a titanium nitride (TiN) layer is interposed between the Schottky metal 99 and the contact metal 100 made of aluminum. The titanium nitride layer bonds the titanium of the Schottky metal 99 and the aluminum of the contact metal 100, ensures electrical conductivity between the titanium and aluminum, and also functions as a barrier layer that suppresses interdiffusion of titanium and aluminum. Such a barrier layer protects the Schottky junction surface S by suppressing or preventing the material of the contact metal 100 from diffusing into the Schottky metal 99.

[0187] A surface protection film (not shown) may be formed on the outermost surface of the first diode 14U. In this case, an opening that exposes the contact metal 100 is preferably formed in the center of the surface protection film. An external connection member such as a first diode wire 64U (see FIG. 17) is bonded to the contact metal 100 through this opening.

[0188] A guard ring 101 made of a P-type diffusion layer is formed on the surface layer of the epitaxial layer 92 so as to contact the Schottky metal 99. The guard ring 101 is formed along the contour of the opening 94 in the field insulating film 93 so as to straddle the inside and outside of the opening 94 in a plan view. Therefore, the guard ring 101 has an inner portion 101a that protrudes inwardly into the opening 94 of the field insulating film 93 and contacts an outer edge portion 99d that is an end portion of the Schottky metal 99 in the opening 94, and an outer portion 101b that protrudes outwardly from the opening 94 and faces the anode electrode 97 (the Schottky metal 99 on the peripheral portion 98) across the peripheral portion 98 of the field insulating film 93. The depth of the guard ring 101 from the surface of the epitaxial layer 92 is, for example, 0.5 μm to 8 μm.

[0189] The guard ring 101 formed across the inside and outside of the opening 94 of the field insulating film 93 covers the boundary between the peripheral portion 98 of the field insulating film 93 and the Schottky metal 99 from the epitaxial layer 92 side. Without the guard ring 101, when a reverse bias is applied to the first diode 14U, an electric field is concentrated at the boundary, making leakage more likely to occur. In the first diode 14U of this embodiment, the guard ring 101 covers the boundary, so that the electric field concentration can be alleviated by a depletion layer that spreads from the guard ring 101 when a reverse bias is applied, and leakage can be suppressed accordingly. Therefore, the withstand voltage of the first diode 14U is improved.

[0190] The operation of this embodiment will be described with reference to Fig. 19. The comparative semiconductor device is a semiconductor device that does not include the limiting units CP1, CP2, and CP3 (the diodes 14U, 14V, and 14W and the diode wires 64U, 64V, and 64W).

[0191] In the comparative semiconductor device, for example, when the motor 2 (see FIG. 1) is driven, when the MOSFET 11U is turned off, a regenerative current flows through the body diode of the MOSFET 12U, and when the MOSFET 11U is turned on at this time, a recovery current flows through the body diode of the MOSFET 12U. At this time, due to the influence of the inductance of the first wire 61U, the source potential of the MOSFET 12U may rise and become higher than the gate potential of the MOSFET 12U, generating a so-called negative bias.

[0192] In this respect, the semiconductor device 1 of the present embodiment has a configuration in which the first diode wire 64U and the first wire 61U are provided separately as the first limiting portion CP1, and the first diode wire 64U is connected to the island portion 35a of the frame 35U. For this reason, for example, when the motor 2 (see FIG. 1) is driven, when the MOSFET 11U is turned on, the regenerative current generated by turning off the MOSFET 12U flows through the first diode 14U because the forward voltage Vf of the first diode 14U is lower than the forward voltage of the body diode of the MOSFET 12U. That is, this regenerative current does not flow through the body diode of the MOSFET 12U through the first wire 61U. Therefore, the source potential of the MOSFET 12U, which is generated due to the current change dI / dt when the MOSFET 11U is on and the inductance of the first wire 61U, is suppressed from rising. Therefore, the generation of a negative bias of the MOSFET 12U can be suppressed.

[0193] Furthermore, the second diode wire 64V and the second wire 61V, and the third diode wire 64W and the third wire 61W have the same configuration as the first diode wire 64U and the first wire 61U, and therefore produce the same effects as those described above.

[0194] According to this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained. (4-1) By providing the wires 61U, 61V, 61W and the diode wires 64U, 64V, 64W connected to the MOSFETs 12U to 12W individually, the source potentials of the MOSFETs 12U to 12W are suppressed from rising. This prevents the gate-source voltage of the MOSFET 12U from becoming negative when the MOSFET 11U is turned on. Furthermore, this prevents the gate-source voltage of the MOSFET 12V from becoming negative when the MOSFET 11V is turned on. Furthermore, this prevents the gate-source voltage of the MOSFET 12W from becoming negative when the MOSFET 11W is turned on. This makes it possible to suppress fluctuations in the threshold voltage Vth for each of the MOSFETs 12U to 12W.

[0195] Fifth embodiment The semiconductor device 1 of the fifth embodiment will be described with reference to Fig. 20 and Fig. 21. The semiconductor device 1 of the present embodiment is different from the semiconductor device 1 of the fourth embodiment in that a diode connected in anti-parallel to each of the MOSFETs 11U to 11W is added. In the following description, the same reference numerals are used to designate configurations common to the configuration of the semiconductor device 1 of the fourth embodiment, and description thereof may be omitted.

[0196] As shown in FIG. 20, the semiconductor device 1 has a first diode 15U provided separately from the MOSFET 11U, a second diode 15V provided separately from the MOSFET 11V, and a third diode 15W provided separately from the MOSFET 11W. The anode of the first diode 15U is connected to the source of the MOSFET 11U, and the cathode of the first diode 15U is connected to the drain of the MOSFET 11U. The anode of the second diode 15V is connected to the source of the MOSFET 11V, and the cathode of the second diode 15V is connected to the drain of the MOSFET 11V. The anode of the third diode 15W is connected to the source of the MOSFET 11W, and the cathode of the third diode 15W is connected to the drain of the MOSFET 11W. The first diode 15U is an example of a third diode provided separately from the first switching element of the first inverter circuit 10U and electrically connected to the first switching element. The second diode 15V is an example of a fourth diode provided separately from the first switching element of the second inverter circuit 10V and electrically connected to the first switching element. The third diode 15W is an example of a fifth diode that is provided separately from the first switching element of the third inverter circuit 10W and is electrically connected to this first switching element.

[0197] An example of each of the diodes 15U, 15V, and 15W is a Schottky barrier diode similar to each of the diodes 14U, 14V, and 14W. As shown in FIG. 21, each of the diodes 15U, 15V, and 15W is formed of a semiconductor chip. The first diode 15U is mounted in a region Ra4 of the frame 31, the second diode 15V is mounted in a region Ra5, and the third diode 15W is mounted in a region Ra6. The first diode 15U is located closer to the fourth side surface 50F of the sealing resin 50 in the second direction Y in the region Ra6, the second diode 15V is located closer to the fourth side surface 50F of the sealing resin 50 in the second direction Y in the region Ra7, and the third diode 15W is located closer to the fourth side surface 50F of the sealing resin 50 in the second direction Y in the region Ra6.

[0198] Each of the diodes 15U, 15V, and 15W has an anode electrode pad 15a which is a front electrode and a cathode electrode which is a rear electrode. The cathode electrodes of the diodes 15U, 15V, and 15W are electrically connected to the frame 31 by solder or the like.

[0199] The anode electrode pad 15a of the first diode 15U and the wire bonding portion 32f of the first frame 32U are connected by a first wire 60U. The anode electrode pad 15a of the second diode 15V and the wire bonding portion 32f of the second frame 32V are connected by a second wire 60V. The anode electrode pad 15a of the third diode 15W and the wire bonding portion 32f of the third frame 32W are connected by a third wire 60W.

[0200] As shown in FIG. 21, the semiconductor device 1 has wires 60U, 60V, 60W, a first diode wire 65U on the high potential side, a second diode wire 65V on the high potential side, a third diode wire 65W on the high potential side, wires 61U, 61V, 61W, and wires 64U, 64V, 64W on the low potential side. The configuration and connection of the wires 61U, 61V, 61W and the diode wires 64U, 64V, 64W are the same as those in the fourth embodiment. The diode wires 64U, 64V, 64W are arranged so as to be approximately parallel to each other. The diode wires 65U, 65V, 65W are arranged so as to be approximately parallel to each other. The diode wires 64U, 64V, 64W and the diode wires 65U, 65V, 65W are arranged so as to be approximately parallel to each other. The diode wires 64U, 64V, 64W and the diode wires 65U, 65V, 65W are arranged so as to be approximately parallel to each other.

[0201] One first wire 60U connects the source electrode pad 11s of the MOSFET 11U to the wire junction 32f of the first frame 32U. One second wire 60V connects the source electrode pad 11s of the MOSFET 11V to the wire junction 32f of the second frame 32V. One third wire 60W connects the source electrode pad 11s of the MOSFET 11W to the wire junction 32f of the third frame 32W. The first wire 60U passes through the second diode 15V on the first diode 15U side relative to the second diode wire 65V and is connected to the wire junction 32f of the first frame 32U. The second wire 60V passes through the third diode 15W on the second diode 15V side relative to the third diode wire 65W and the connection portion 32c of the first frame 32U and is connected to the wire junction 32f of the second frame 32V. The third wire 60W passes through the third diode 15W side of the first diode wire 64U of the first diode 14U of the first frame 32U and the connection portion 32c of the second frame 32V, and is connected to the wire joint portion 32f of the third frame 32W.

[0202] The first diode wire 65U is provided separately from the first wire 60U. One first diode wire 65U connects the anode electrode pad 15a of the first diode 15U to the wire joint 32f of the frame 32U. The position where the first wire 60U is connected to the wire joint 32f of the first frame 32U is different from the position where the first diode wire 65U is connected to the wire joint 32f of the first frame 32U. In detail, the position where the first wire 60U is connected to the wire joint 32f of the first frame 32U is located closer to the wire joint 32f of the second frame 32V than the position where the first diode wire 65U is connected to the wire joint 32f of the first frame 32U. The first diode wire 65U passes through the connection portion 31c of the frame 31 and is connected to the wire joint 32f of the first frame 32U. The second diode wire 65V passes through the connection portion 32c of the first frame 32U and is connected to the wire joint portion 32f of the second frame 32V. The third diode wire 65W passes through the island portion 32a of the first frame 32U and the connection portion 32c of the second frame 32V and is connected to the wire joint portion 32f of the third frame 32W.

[0203] The second diode wire 65V is provided separately from the second wire 60V. One second diode wire 65V connects the anode electrode pad 15a of the second diode 15V and the wire joint 32f of the second frame 32V. The position where the second wire 60V is connected to the wire joint 32f of the second frame 32V is different from the position where the second diode wire 65V is connected to the wire joint 32f of the second frame 32V. In detail, the position where the second diode wire 65V is connected to the wire joint 32f of the second frame 32V is located closer to the wire joint 32f of the first frame 32U than the position where the second wire 60V is connected to the wire joint 32f of the second frame 32V.

[0204] The third diode wire 65W is provided separately from the third wire 60W. One third diode wire 65W connects the anode electrode pad 15a of the third diode 15W and the wire joint 32f of the third frame 32W. The position where the third wire 60W is connected to the wire joint 32f of the third frame 32W is different from the position where the third diode wire 65W is connected to the wire joint 32f of the third frame 32W. In detail, the position where the third diode wire 65W is connected to the wire joint 32f of the third frame 32W is located closer to the wire joint 32f of the second frame 32V than the position where the third wire 60W is connected to the wire joint 32f of the third frame 32W.

[0205] Each of the diode wires 65U, 65V, 65W is made of aluminum (Al), for example. The wire diameters of each of the diode wires 65U, 65V, 65W are equal to each other. The wire diameters of each of the diode wires 65U, 65V, 65W are equal to the wire diameters of each of the wires 60U, 60V, 60W. According to this embodiment, the same actions and effects as those of the fourth embodiment can be obtained.

[0206] (Modification) The above-described embodiments are merely examples of possible forms of the semiconductor device according to the present disclosure, and are not intended to limit the forms. In addition to the above-described embodiments, the semiconductor device according to the present disclosure may have the following modified forms, or a combination of at least two mutually compatible modified forms.

[0207] At least two of the second to fifth embodiments can be combined. In each of the above embodiments, the structure of the electrode pads of each of the MOSFETs 12U to 12W mounted on each of the frames 32U, 32V, and 32W and the orientation (position) of each of the MOSFETs 12U to 12W may be changed as desired. For example, the MOSFETs 12U to 12W may be changed as shown in (A1) to (A4) below.

[0208] (A1) As shown in FIG. 22, the gate electrode pads 12g of the MOSFETs 12U to 12W may be disposed on the second side surface 50D side of the sealing resin 50. The source electrode pads 12s of the MOSFETs 12U to 12W each have a cutout portion to avoid the gate electrode pad 12g. As shown in FIG. 22, the MOSFETs 12U and 12V are disposed such that the second direction Y is the longitudinal direction. On the other hand, the MOSFET 12W is disposed such that the first direction X is the longitudinal direction. The MOSFET 12W is disposed such that its gate electrode pad 12g is located on the frame 34 side. The MOSFET 12W is disposed closer to the second side surface 50D than the integrated circuit element 25L. Note that in FIG. 22, the MOSFET 12W is disposed such that it is located in the center of the region Ra7 in the first direction X, but is not limited thereto. For example, the MOSFET 12W may be disposed closer to the second frame 32V in the first direction X. Further, although the MOSFET 12U is arranged so as to be in the center of the region Ra7 in the first direction X, this is not limiting. For example, the MOSFET 12U may be arranged closer to the second frame 32V in the first direction X.

[0209] The first wire 62U and the first wire 63U are each connected to an end of the MOSFET 12U in the integrated circuit element 25L near the end on the first frame 32U side. The first wire 62U is disposed closer to the second frame 32V than the first wire 63U in the first direction X. The second wire 62V and the second wire 63V are each connected to the vicinity of the center of the integrated circuit element 25L in the first direction X. The second wire 62V is disposed closer to the third frame 32W than the second wire 63V in the first direction X. The third wire 62W and the third wire 63W are each connected to a portion of the integrated circuit element 25L on the third frame 32W side. The third wire 63W is disposed closer to the second frame 32V than the third wire 62W in the first direction X.

[0210] (A2) As shown in FIG. 23, each of the MOSFETs 12U to 12W has two gate electrode pads 12g. The MOSFETs 12U to 12W have a common structure. Therefore, the structure of the MOSFET 12U will be described as an example, and descriptions of the structures of the MOSFETs 12V and 12W will be omitted. The two gate electrode pads 12g of the MOSFET 12U are disposed at ends in the longitudinal direction of the MOSFET 12U. The two gate electrode pads 12g of the MOSFET 12U are disposed at an interval in a direction perpendicular to the longitudinal direction of the MOSFET 12U in a plan view. The source electrode pad 12s of the MOSFET 12U has a portion extending between the two gate electrode pads 12g and is formed in a convex shape in a plan view.

[0211] As shown in FIG. 23, the MOSFET 12V is arranged such that the second direction Y is its longitudinal direction. The MOSFETs 12U and 12W are arranged such that the first direction X is its longitudinal direction. The MOSFET 12U is arranged such that its gate electrode pad 12g is close to the integrated circuit element 25L. More specifically, the MOSFET 12U is arranged such that its gate electrode pad 12g is on the second frame 32V side. The MOSFET 12W is arranged such that its gate electrode pad 12g is close to the integrated circuit element 25L. More specifically, the MOSFET 12W is arranged such that its gate electrode pad 12g is on the second frame 32V side. In this way, the orientation (position) of the MOSFET 12U and the orientation (position) of the MOSFET 12W are opposite to each other.

[0212] The first wire 62U is connected to the gate electrode pad 12g on the integrated circuit element 25L side of the two gate electrode pads 12g of the MOSFET 12U. The first wire 63U is connected to a portion between the two gate electrode pads 12g in the source electrode pad 12s. The first wire 63U is disposed closer to the second frame 32V side than the first wire 62U in the first direction X. The second wire 62V is connected to the gate electrode pad 12g on the third frame 32W side of the two gate electrode pads 12g. The second wire 63V is connected to a portion between the two gate electrode pads 12g in the source electrode pad 12s. Therefore, the second wire 62V is disposed closer to the third frame 32W side than the second wire 63V in the first direction X. The third wire 62W is connected to the gate electrode pad 12g on the integrated circuit element 25L side of the two gate electrode pads 12g. The third wire 63W is connected to a portion between the two gate electrode pads 12g in the source electrode pad 12s. The third wire 63W is disposed closer to the second frame 32V side than the third wire 62W.

[0213] (A3) The orientation (position) of each of the MOSFETs 12U to 12W mounted on each of the frames 32U, 32V, and 32W can be changed arbitrarily. In one example, as shown in FIG. 24, the orientations (positions) of the MOSFETs 12U to 12W are different from one another. More specifically, the MOSFET 12U is arranged so that the gate electrode pad 12g approaches the integrated circuit element 25L and the longitudinal direction of the MOSFET 12U is aligned along a direction different from the first direction X and the second direction Y. An example of the angle θ1 between the longitudinal direction of the MOSFET 12U and the first direction X is 80°. The MOSFET 12V is arranged so that the longitudinal direction of the MOSFET 12W is aligned along the first direction X. The MOSFET 12W is arranged so that the gate electrode pad 12g approaches the integrated circuit element 25L and the longitudinal direction of the MOSFET 12W is aligned along a direction different from the first direction X and the second direction Y. An example of the angle θ2 between the longitudinal direction of the MOSFET 12W and the first direction X is 10°. The angles θ1 and θ2 can be arbitrarily changed within a range of 0° to 90°. In FIG. 24, the angles θ1 and θ2 are different, but the angles θ1 and θ2 may be equal to each other.

[0214] The first wire 62U and the first wire 63U are each connected to an end of the MOSFET 12U in the integrated circuit element 25L near the end on the first frame 32U side. The first wire 62U is disposed closer to the second frame 32V than the first wire 63U in the first direction X. The second wire 62V and the second wire 63V are each connected to the vicinity of the center of the integrated circuit element 25L in the first direction X. The second wire 63V is disposed closer to the third frame 32W than the second wire 62V in the first direction X. The third wire 62W and the third wire 63W are each connected to a portion of the integrated circuit element 25L on the third frame 32W side. The third wire 63W is disposed closer to the second frame 32V than the third wire 62W in the first direction X.

[0215] The orientations of the MOSFETs 12U and 12W of the modified example shown in Fig. 24 may be further changed as shown in Fig. 25. That is, as shown in Fig. 25, the MOSFET 12U is arranged so that the gate electrode pad 12g is spaced apart from the integrated circuit element 25L and the longitudinal direction of the MOSFET 12U is aligned along a direction different from the first direction X and the second direction Y. The MOSFET 12W is arranged so that the gate electrode pad 12g is spaced apart from the integrated circuit element 25L and the longitudinal direction of the MOSFET 12W is aligned along a direction different from the first direction X and the second direction Y. An example of the angle θ1 is 100°. In this case, the angle θ1 can be changed arbitrarily within a range of 90° or more and 180° or less.

[0216] The first wire 62U and the first wire 63U are each connected to an end of the MOSFET 12U in the integrated circuit element 25L near the end on the first frame 32U side. The first wire 63U is disposed closer to the second frame 32V than the first wire 62U in the first direction X. The third wire 62W and the third wire 63W are each connected to a portion of the integrated circuit element 25L on the third frame 32W side. The third wire 62W is disposed closer to the second frame 32V than the third wire 63W in the first direction X.

[0217] Furthermore, the MOSFETs 12U to 12W may be in a state in which the modified example shown in Fig. 24 and the modified example shown in Fig. 25 are combined. In one example, the orientation (layout posture) of the MOSFET 12U mounted on the first frame 32U is the orientation of the MOSFET 12U shown in Fig. 24, and the orientation (layout posture) of the MOSFET 12W mounted on the third frame 32W is the orientation of the MOSFET 12W shown in Fig. 25.

[0218] Similarly, the orientation of the MOSFETs 11U to 11W mounted on the frame 31 can be changed to the orientation of the MOSFETs 12U to 12W in FIGS. 24 and 25. In one example, as shown in FIG. 26, the orientations (positions) of the MOSFETs 11U to 11W are different from one another. More specifically, the MOSFET 11U is arranged so that the gate electrode pad 12g approaches the integrated circuit element 25H and the longitudinal direction of the MOSFET 11U is aligned along a direction different from the first direction X and the second direction Y. An example of the angle θ1 between the longitudinal direction of the MOSFET 11U and the first direction X is 80°. The MOSFET 11V is arranged so that the longitudinal direction of the MOSFET 11U is aligned along the first direction X. The MOSFET 11W is arranged so that the gate electrode pad 12g approaches the integrated circuit element 25H and the longitudinal direction of the MOSFET 11W is aligned along a direction different from the first direction X and the second direction Y. An example of the angle θ2 between the longitudinal direction of the MOSFET 11W and the first direction X is 10°. The angles θ1 and θ2 can be arbitrarily changed within a range of 0° to 90°. In Fig. 26, the angles θ1 and θ2 are different, but the angles θ1 and θ2 may be equal to each other.

[0219] The first wire 62U and the first wire 63U shown in FIG. 26 are connected near the end of the integrated circuit element 25H on the MOSFET 11U side. The first wire 62U is disposed closer to the first side surface 50C than the first wire 63U in the first direction X. The second wire 62V and the second wire 63V are connected near the center of the integrated circuit element 25H in the first direction X. The second wire 63V is disposed closer to the second side surface 50D than the second wire 62V in the first direction X. The third wire 62W and the third wire 63W are connected to a portion of the integrated circuit element 25H on the MOSFET 11W side. The third wire 63W is disposed closer to the second side surface 50D than the third wire 62W in the first direction X.

[0220] 27, the MOSFET 11U is arranged such that the gate electrode pad 12g is spaced apart from the integrated circuit element 25H and the longitudinal direction of the MOSFET 11U is aligned along a direction different from the first direction X and the second direction Y. The MOSFET 11W is arranged such that the gate electrode pad 12g is spaced apart from the integrated circuit element 25H and the longitudinal direction of the MOSFET 11W is aligned along a direction different from the first direction X and the second direction Y. An example of the angle θ1 is 100°. In this case, the angle θ1 can be changed arbitrarily within a range of 90° to 180°.

[0221] 27 are connected to the vicinity of an end of the MOSFET 11U in the integrated circuit element 25H. The first wire 63U is disposed closer to the first side surface 50C than the first wire 62U in the first direction X. The third wire 62W and the third wire 63W are connected to a portion of the integrated circuit element 25H on the second side surface 50D side. The third wire 63W is disposed closer to the second side surface 50D than the third wire 62W in the first direction X.

[0222] Furthermore, the orientations of the MOSFETs 11U to 11W may be a combination of the modified example shown in Fig. 26 and the modified example shown in Fig. 27. In one example, the orientation (layout posture) of the MOSFET 11U is the orientation of the MOSFET 11U shown in Fig. 26, and the orientation (layout posture) of the MOSFET 11W is the orientation of the MOSFET 11W shown in Fig. 27.

[0223] (A4) The shape and arrangement position of the gate electrode pad 12g of each of the MOSFETs 12U to 12W can be changed arbitrarily. The shape of the source electrode pad 12s is changed in accordance with the change in the shape and arrangement position of the gate electrode pad 12g. In one example, as shown in FIG. 28, the gate electrode pad 12g is formed in a rectangular shape with the first direction X as the longitudinal direction. The gate electrode pad 12g is located at the end of the integrated circuit element 25L side in the first direction X and at the center in the second direction Y on the surface of each of the MOSFETs 12U to 12W. A recess is formed at the end of the source electrode pad 12s on the integrated circuit element 25L side in the first direction X so as to avoid the gate electrode pad 12g. In FIG. 28, the MOSFETs 12U to 12W are arranged so that their longitudinal direction is along the first direction X. The orientation (arrangement posture) of the MOSFETs 12U to 12W can be changed arbitrarily.

[0224] The first wire 62U and the first wire 63U are each connected to an end of the MOSFET 12U in the integrated circuit element 25L near the end on the first frame 32U side. The first wire 63U is disposed closer to the second frame 32V side than the first wire 62U in the first direction X. The second wire 62V and the second wire 63V are each connected to the vicinity of the center of the integrated circuit element 25L in the first direction X. The second wire 63V is disposed closer to the first frame 32U side than the second wire 62V in the first direction X. The third wire 62W and the third wire 63W are each connected to a portion of the integrated circuit element 25L on the third frame 32W side. The third wire 63W is disposed closer to the second frame 32V side than the third wire 62W in the first direction X.

[0225] 28 can be applied to the gate electrode pads 11g and source electrode pads 11s of the MOSFETs 11U to 11W. In this case, in the semiconductor device 1, a current of 30 A or more can be passed through each of the MOSFETs 11U to 11W and 12U to 12W.

[0226] In the first to third embodiments, the shapes of the frame 31 and the frames 32U, 32V, 32W can be changed as desired. As an example, the frame 31 and the frames 32U, 32V, 32W may be changed to those shown in FIG.

[0227] More specifically, the size in the second direction Y of the island portion 31a of the frame 31 in Fig. 29 is smaller than the size in the second direction Y of the island portion 31a of the frames 31 in the first to third embodiments. The element mounting area Rse of the island portion 31a in Fig. 29 has areas Ra1 to Ra3, but does not have areas Ra4 to Ra6.

[0228] The size in the second direction Y of the island portion 32a of each of the frames 32U, 32V, 32W in Fig. 29 is smaller than the size in the second direction Y of the island portion 32a of each of the frames 32U, 32V, 32W in the first to third embodiments. The element mounting area Rse of the island portion 32a in Fig. 29 has an area Ra7 but does not have an area Ra8.

[0229] According to such a configuration, the size in the second direction Y of the frame 31 and each of the frames 32U, 32V, 32W is reduced, and thus the size in the second direction Y of the sealing resin 50 of the semiconductor device 1 is reduced. Therefore, the semiconductor device 1 can be made smaller and lighter.

[0230] In the first to third embodiments, the number of wires 63U, 63V, 63W connecting the source electrode pads 12s of the MOSFETs 12U to 12W to the integrated circuit element 25L can be changed arbitrarily. The number of wires 63U, 63V, 63W may be more than one. For example, the number of wires 63U, 63V, 63W may be two. Furthermore, at least one of the number of first wires 63U, the number of second wires 63V, and the number of third wires 63W may be different from the others.

[0231] In the fifth embodiment, the manner in which the MOSFETs 11U-11W and the diodes 15U, 15V, and 15W of the frame 31 are electrically connected can be changed arbitrarily. For example, the manner in which the MOSFETs 11U-11W and the diodes 15U, 15V, and 15W are connected can be changed as shown in the following (B1) and (B2).

[0232] (B1) As shown in FIG. 30, the MOSFET 11U, the first diode 15U, and the first frame 32U are connected by one first wire 60U. The MOSFET 11V, the second diode 15V, and the second frame 32V are connected by one second wire 60V. The MOSFET 11W, the third diode 15W, and the third frame 32W are connected by one third wire 60W. In detail, the first wire 60U connected to the source electrode pad 11s of the MOSFET 11U has a first portion extending along the second direction Y so as to connect to the anode electrode pad 15a of the first diode 15U, and a second portion extending toward the second side surface 50D as it approaches the fourth side surface 50F of the sealing resin 50 so as to connect the anode electrode pad 15a and the wire bonding portion 32f of the first frame 32U. The second wire 60V connected to the source electrode pad 11s of the MOSFET 11V has a first portion extending along the second direction Y to connect to the anode electrode pad 15a of the second diode 15V, and a second portion extending toward the second side surface 50D as it approaches the fourth side surface 50F of the sealing resin 50 to connect the anode electrode pad 15a and the wire bonding portion 32f of the second frame 32V. The third wire 60W connected to the source electrode pad 11s of the MOSFET 11W has a first portion extending along the second direction Y to connect to the anode electrode pad 15a of the third diode 15W, and a second portion extending toward the second side surface 50D as it approaches the fourth side surface 50F of the sealing resin 50 to connect the anode electrode pad 15a and the wire bonding portion 32f of the third frame 32W.

[0233] (B2) One or two of the diodes 15U, 15V, and 15W may be omitted. Also, the connection manner of the wires 60U, 60V, and 60W connected to the MOSFETs 11U to 11W can be changed arbitrarily. In one example, as shown in FIG. 31, the first diode 15U is omitted from the semiconductor device 1. The first wire 60U connected to the source electrode pad 11s of the MOSFET 11U is connected to the wire bonding portion 32f of the first frame 32U. The second wire 60V connected to the source electrode pad 11s of the MOSFET 11V has a first portion that connects to the anode electrode pad 15a of the second diode 15V and a second portion that connects the anode electrode pad 15a and the wire bonding portion 32f of the second frame 32V, as in FIG. 29. The third wire 60W connected to the source electrode pad 11s of the MOSFET 11W is connected to the wire bonding portion 32f of the third frame 32W. The third diode wire 65W connected to the anode electrode pad 15a of the third diode 15W is connected to a wire joint portion 32f of the third frame 32W.

[0234] In the third embodiment, the wires 63U, 63V, 63W connecting the source electrode pads 12s of the MOSFETs 12U to 12W of the frames 32U, 32V, 32W to the integrated circuit element 25L may be omitted as shown in Fig. 32. This configuration also provides the same effects as those of the third embodiment.

[0235] In the fifth embodiment, the configuration of the third embodiment may be applied, that is, a configuration in which the orientation (position) of the MOSFET 12U on the first frame 32U is changed. In this case, the connection manner of each of the wires 61U, 61V, 61W may be changed as shown in FIG. 33. In more detail, the MOSFET 12U, the diode 14U, and the frame 35U are connected by one first wire 61U. The MOSFET 12V, the second diode 14V, and the frame 35V are connected by one second wire 61V. The MOSFET 12W, the third diode 14W, and the frame 35W are connected by one third wire 61W. More specifically, the first wire 61U connected to the source electrode pad 12s of the MOSFET 12U has a first portion extending along the second direction Y to connect to the anode electrode pad 14a of the first diode 14U, and a second portion extending toward the second side surface 50D as it approaches the fourth side surface 50F of the sealing resin 50 to connect the anode electrode pad 14a and the island portion 35a of the frame 35U. The second wire 61V connected to the source electrode pad 12s of the MOSFET 12V has a first portion extending along the second direction Y to connect to the anode electrode pad 14a of the second diode 14V, and a second portion extending toward the second side surface 50D as it approaches the fourth side surface 50F of the sealing resin 50 to connect the anode electrode pad 14a and the island portion 35a of the frame 35V. The third wire 61W connected to the source electrode pad 12s of the MOSFET 12L has a first portion extending along the second direction Y so as to connect to the anode electrode pad 14a of the third diode 14W, and a second portion extending toward the second side surface 50D as it approaches the fourth side surface 50F of the sealing resin 50 so as to connect this anode electrode pad 14a and the island portion 35a of the frame 35W.

[0236] In each of the above embodiments, the regions Ra7 and Ra8 of the element mounting region Rse of each of the frames 32U, 32V, 32W may be formed to be spaced apart in the second direction Y. In this case, a plurality of recesses 32i may be formed in a portion between the regions Ra7 and Ra8 in the second direction Y. Similarly, for the frame 31, the regions Ra1 to Ra3 and regions Ra4 to Ra6 of the element mounting region Rse may be formed to be spaced apart in the second direction Y. In this case, a plurality of recesses 31f may be formed in a portion between the regions Ra1 to Ra3 and regions Ra4 to Ra6 in the second direction Y.

[0237] In each of the above embodiments, the structure of the MOSFETs 11U to 11W and 12U to 12W can be changed as desired. For example, the structure of the MOSFETs 11U to 11W and 12U to 12W may be changed as shown in (C1) and (C2) below. Since the structures of the MOSFETs 11U to 11W and 12U to 12W are the same, the structure of the MOSFET 11U will be described in the explanation of (C1) and (C2), and explanations of the structures of the MOSFETs 11V, 11W, and 12U to 12W will be omitted.

[0238] (C1) As shown in FIG. 34, the MOSFET 11U is an N + For example, N-type impurity concentration is 1e18 to 1e21 cm -3 The SiC substrate 110 has a front surface 110A (upper surface) which is a Si surface, and a rear surface 110B (lower surface) which is a C surface.

[0239] On the SiC substrate 110, N having a lower concentration than the SiC substrate 110 is provided. - For example, N-type impurity concentration is 1e15 to 1e17 cm -3 ) is laminated on the SiC substrate 110. The epitaxial layer 111 as a semiconductor layer is formed on the SiC substrate 110 by so-called epitaxial growth. The epitaxial layer 111 formed on the surface 110A, which is a Si surface, is grown with the Si surface as the main growth surface. Therefore, the surface 111A of the epitaxial layer 111 formed by growth is a Si surface, similar to the surface 110A of the SiC substrate 110.

[0240] A P-type body region 112 is formed in a wide area in the shape of a well on the surface 111A side (Si surface side) of the epitaxial layer 111. The P-type impurity concentration of the body region 112 is 1e16 to 1e19 cm -3 In the epitaxial layer 111, the region closer to the SiC substrate 110 (C-face side) than the body region 112 is N - The n-type drain region 113 (drift region) is a n-type drain region 113.

[0241] In the body region 112, N is present in almost the entire area on the surface 111A side. + For example, N-type impurity concentration is 1e18 to 1e21 cm -3 ) source region 114, and P + For example, P-type impurity concentration is 1e18~1e21cm -3 ) and body contact regions 115 are formed. A large number of body contact regions 115 are formed in a matrix. Then, source trenches 116 are formed in the same number as the body contact regions 115 so as to penetrate each of the body contact regions 115. Then, lattice-shaped gate trenches 117 are formed so as to surround each body contact region 115 in which the source trenches 116 are formed. As a result, a large number of unit cells 118 each functioning as a field effect transistor are formed in the epitaxial layer 111. That is, in the unit cell 118, the body contact region 115 is formed so as to surround the source trench 116, and the body region 112 is formed so as to further surround the body contact region 115. Then, the opposite side of the body region 112 to the body contact region 115 side is exposed on the side surface of the gate trench 117. In addition, in the unit cell 118, the depth direction of the gate trench 117 is the gate length direction, and the circumferential direction of each unit cell 118 perpendicular to the gate length direction is the gate width direction.

[0242] Both the source trench 116 and the gate trench 117 extend from the surface 111A of the epitaxial layer 111 through the body region 112 to reach the drain region 113. In this embodiment, the depth of the source trench 116 and the depth of the gate trench 117 are equal to each other. A distance D1 between a side surface 116a of the source trench 116 and a side surface 117a of the gate trench 117 is, for example, 0.5 μm to 3 μm. If the distance D1 is within a range of 0.5 μm to 3 μm, an increase in the resistance value (on-resistance) when each unit cell 118 is turned on can be suppressed, and the electric field applied to the bottom of the gate trench 117 can be alleviated.

[0243] The gate trench 117 has both end corners 117b curved toward the drain region 113 in a direction perpendicular to the gate width at the bottom (opposing direction with the adjacent unit cell 118), and has a U-shaped cross section in which the side surfaces 117a and the bottom surface 117c facing each other are continuous through the curved surface. Furthermore, like the gate trench 117, the source trench 116 has a U-shaped cross section in which the side surfaces 116a and the bottom surface 116b facing each other are continuous through the curved surface. This allows the electric field applied to the both end corners 117b at the bottom of the gate trench 117 to be dispersed to parts other than the both end corners 117b when the unit cell 118 is turned off. This allows the dielectric breakdown of the part (insulating film bottom 120a) on the bottom surface 117c of the gate insulating film 120 described later to be suppressed.

[0244] In the drain region 113, an implantation active layer 119 is formed as an implantation layer formed by implantation of P-type impurities (e.g., boron (B), aluminum (Al), etc.) in a portion from the bottom surface 117c of the gate trench 117 to the middle part in the thickness direction. The implantation active layer 119 is formed in a lattice shape overlapping the gate trench 117 in a plan view, and has a width narrower than the distance between adjacent unit cells 118. The depth of the implantation active layer 119 in this embodiment is, for example, 0.1 μm to 0.5 μm.

[0245] The implantation active layer 119 is a high resistance layer having a higher resistance than the surrounding regions (for example, the drain region 113) in the epitaxial layer 111. The resistance of the implantation active layer 119 is, for example, several tens of kΩ / □ to several hundreds of kΩ / □. The P-type impurity concentration of the implantation active layer 119 is, for example, 1e16 to 1e21 cm -3 It is.

[0246] A gate insulating film 120 is formed on the inner surface of the gate trench 117 so as to cover the entire area. The gate insulating film 120 is made of an oxide film containing nitrogen, for example, a silicon nitride oxide film formed by thermal oxidation using a gas containing nitrogen and oxygen. The nitrogen content (nitrogen concentration) of the gate insulating film 120 is, for example, 0.1 to 10%.

[0247] The gate insulating film 120 has a thickness T4 of a portion (insulating film bottom portion 120a) on the bottom surface 117c of the gate trench 117 smaller than a thickness T3 of a portion (insulating film side portion 120b) on the side surface 117a of the gate trench 117. The ratio (T4 / T3) of thickness T4 to thickness T3 is 0.3 to 1.0, and preferably 0.5 to 1.0. The thickness T3 is 300 to 1000 Å, and the thickness T4 is 150 to 500 Å. The inside of the gate insulating film 120 is filled with a polysilicon material doped with a high concentration of N-type impurities, so that the gate electrode 121 is embedded in the gate trench 117.

[0248] An interlayer insulating film 122 made of silicon oxide (SiO2) is laminated on the epitaxial layer 111. In the interlayer insulating film 122 and the gate insulating film 120, a contact hole 123 is formed to expose the surfaces of the source trench 116 and the source region 114 of each unit cell 118.

[0249] A source wiring 124 is formed on the interlayer insulating film 122. The source wiring 124 enters the source trenches 116 of all the unit cells 118 collectively through each contact hole 123, and contacts the drain region 113, the body contact region 115, and the source region 114 in each unit cell 118, in that order from the bottom side of the source trench 116. That is, the source wiring 124 is a common wiring for all the unit cells 118. An interlayer insulating film (not shown) is formed on the source wiring 124, and the source wiring 124 is electrically connected to the source electrode pad 11s through the interlayer insulating film. On the other hand, the gate electrode pad 11g is electrically connected to the gate electrode 121 through a gate wiring (not shown) routed on the interlayer insulating film (not shown).

[0250] The source wiring 124 has a polysilicon layer 125 , an intermediate layer 126 , and a metal layer 127 in this order from the contact side with the epitaxial layer 111 . The polysilicon layer 125 is a doped layer formed using doped polysilicon doped with impurities, and has a thickness of, for example, 1e19 to 1e21 cm -3 The polysilicon layer 125 is a highly doped layer doped with impurities at a high concentration. When forming the polysilicon layer 125 as a doped layer (including a highly doped layer), N-type impurities such as nitrogen (N), phosphorus (P), and arsenic (As), and P-type impurities such as aluminum (Al) and boron (B) can be used as impurities. The thickness of the polysilicon layer 125 is, for example, 5000 to 10000 Å.

[0251] The polysilicon layer 125 of this embodiment is formed so as to cover the entire surface of the unit cell 118 exposed in the contact hole 123 , and is in contact with the drain region 113 , the body contact region 115 , and the source region 114 in the source trench 116 .

[0252] By using polysilicon for the contact layers of the source wiring 124 with the drain region 113, the body contact region 115, and the source region 114, the source wiring 124 can be in ohmic junction with both the body contact region 115, which is a high-concentration impurity region, and the source region 114. On the other hand, with respect to the low-concentration drain region 113, a heterojunction junction with a smaller junction failure than the diffusion potential of the body diode 128 (PN diode formed by the junction between the body region 112 and the drain region 113) present in the MOSFET 11U can be formed.

[0253] Incidentally, when a current flows through the body diode 128 in the MOSFET 11U, holes that have moved from the body region 112 to the drain region 113 recombine with electrons in the drain region 113, and the resulting binding energy may cause defects in the SiC crystal in the epitaxial layer 111 to spread in-plane. Since these crystal defects have a high resistance, if the crystal defects spread toward the gate trench 117 side, they may interfere with normal transistor operation, resulting in an increase in on-resistance.

[0254] 34, if a heterojunction is formed by contact between the polysilicon layer 125 and the drain region 113, even if a reverse voltage is applied between the source and drain and a current flows through the body diode 128, the current can be made to flow preferentially to the heterojunction side rather than the body diode 128 side. As a result, the expansion of crystal defects in SiC can be suppressed, and an increase in on-resistance can be suppressed.

[0255] Intermediate layer 126 is laminated on polysilicon layer 125, and is made of a single layer containing titanium (Ti) or a plurality of layers including such a layer. The layer containing titanium can be formed using titanium, titanium nitride (TiN), etc. Intermediate layer 126 has a thickness of, for example, 200 to 500 nm.

[0256] The metal layer 127 is laminated on the intermediate layer 126, and is formed using, for example, aluminum (Al), gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), or an alloy or a metal material containing these. The metal layer 127 forms the outermost layer of the source wiring 124. The thickness of the metal layer 127 is 1 to 5 μm.

[0257] A specific example of the combination of the polysilicon layer 125, intermediate layer 126, and metal layer 127 described above is a laminated structure (Poly-Si / Ti / TiN / Al) in which Poly-Si (polysilicon layer 125), Ti (intermediate layer 126), TiN (intermediate layer 126), and Al (metal layer 127) are laminated in this order.

[0258] A drain electrode 129 is formed to cover the entire back surface 110B of the SiC substrate 110. This drain electrode 129 is a common electrode for all the unit cells 118. An example of the drain electrode 129 is a laminated structure (Ti / Al) in which titanium (Ti) and aluminum (Al) are laminated in this order from the SiC substrate 110 side.

[0259] With a predetermined potential difference being generated between the source electrode pad 11s (source wiring 124) and the drain electrode 129 (between the source and drain), a predetermined voltage (a voltage equal to or higher than the gate threshold voltage) is applied to the gate electrode pad 11g, whereby an electric field from the gate electrode 121 forms a channel in the body region 112 near the interface with the gate insulating film 120. As a result, a current flows between the source wiring 124 and the drain electrode 129, and the MOSFET 11U is turned on.

[0260] (C2) As shown in FIG. 35, the MOSFET 11U is an N + The SiC substrate 130 includes an N-type SiC substrate 130. The surface 130A of the SiC substrate 130 includes an N-type SiC substrate 130 doped with N-type impurities at a lower concentration than the SiC substrate 130. -A mold epitaxial layer 131 is laminated on the substrate 12. A surface 131A of the epitaxial layer 131 is formed of, for example, a (0001) surface of SiC.

[0261] The epitaxial layer 131 is formed of N - 35, a P-type drain region 132 is formed. A P-type body region 133 is formed in the surface portion of the epitaxial layer 131. Although not shown in FIG. 35, a plurality of body regions 133 are formed at regular intervals, and extend parallel to each other in the same direction (perpendicular to the paper surface of FIG. 35), and are arranged, for example, in a stripe or matrix shape. The drain region 132 is exposed between adjacent body regions 133. In addition, N-type body regions 133 are formed in the surface portion of the body region 133 at intervals from its periphery. + A source region 134 of the type is formed.

[0262] A gate insulating film 135 is formed on a surface 131A of the epitaxial layer 131, straddling the drain region 132, the body region 133, and the source region 134. The gate insulating film 135 is made of, for example, silicon oxide (SiO2). A gate electrode 136 made of polysilicon doped with a high concentration of N-type impurities is formed on the gate insulating film 135. The gate electrode 136 faces the drain region 132, the body region 133, and the source region 134 via the gate insulating film 135.

[0263] An interlayer insulating film 137 made of silicon oxide (SiO2) is laminated on the epitaxial layer 131. A source wiring 138 is formed on the interlayer insulating film 137. The source wiring 138 is electrically connected to the body region 133 and the source region 134 via a contact hole 139 formed in the interlayer insulating film 137.

[0264] A gate wiring 140 is electrically connected to the gate electrode 136 through a contact hole (not shown) formed in the interlayer insulating film 137. In addition, a drain electrode 141 is formed on the rear surface 130B of the SiC substrate 130.

[0265] By controlling the potential of the gate electrode 136 while applying an appropriate positive voltage to the drain electrode 141, a channel can be formed in the body region 133 near the interface with the gate insulating film 135 due to the electric field from the gate electrode 136. This allows a current to flow between the source wiring 138 and the drain electrode 141.

[0266] In the fourth and fifth embodiments, the structure of each of the diodes 14U, 14V, 14W and each of the diodes 15U, 15V, 15W can be changed as desired. For example, the structure of each of the diodes 14U, 14V, 14W and each of the diodes 15U, 15V, 15W may be changed to a planar structure as shown in Fig. 36. Since the structures of each of the diodes 14U, 14V, 14W and each of the diodes 15U, 15V, 15W are the same, the following description will be given of the structure of the first diode 14U, and the description of the structures of the other diodes 14V, 14W, 15U, 15V, 15W will be omitted.

[0267] As shown in FIG. 36, the first diode 14U is an N + For example, N-type impurity concentration is 1e18 to 1e21 cm -3 The semiconductor substrate 150 is made of silicon (Si). A cathode electrode 151 is formed on a back surface 150B of the semiconductor substrate 150 so as to cover the entire area. The cathode electrode 151 is made of a metal (e.g., gold (Au), nickel (Ni), silicide, cobalt (Co), etc.) that is in ohmic contact with N-type silicon.

[0268] The surface 150A of the semiconductor substrate 150 has a lower concentration of N than the semiconductor substrate 150. -An epitaxial layer 152 made of silicon of a n-type (for example, an N-type impurity concentration of 1e15 to 1e17 cm-3) is laminated on the epitaxial layer 152. The thickness of the epitaxial layer 152 is, for example, 2 to 10 μm.

[0269] A field insulating film 153 made of silicon oxide (SiO2) is laminated on a surface 152A of the epitaxial layer 152. The thickness of the field insulating film 153 is, for example, 1000 Å or more, and preferably 7000 Å to 40000 Å. The field insulating film 153 may be made of other insulators such as silicon nitride (SiN).

[0270] An opening 153a is formed in the field insulating film 153 to expose the center of the epitaxial layer 152. An anode electrode 154 is formed on the field insulating film 153. The anode electrode 154 fills the opening 153a of the field insulating film 153 and projects outward in a flange shape so as to cover the peripheral portion 153b of the opening 153a in the field insulating film 153 from above. In other words, the peripheral portion 153b of the opening 153a in the field insulating film 153 is sandwiched from above and below by the epitaxial layer 152 and the anode electrode 154 all around.

[0271] The anode electrode 154 in FIG. 36 has a multilayer structure (two-layer structure in FIG. 36) of a Schottky metal 155 joined to the epitaxial layer 152 in the opening 153a of the field insulating film 153, and an electrode metal 156 laminated on the Schottky metal 155.

[0272] The Schottky metal 155 is made of a metal (e.g., titanium (Ti), molybdenum (Mo), palladium (Pd), etc.) that forms a Schottky junction when bonded to N-type silicon. The Schottky metal 155 bonded to the epitaxial layer 152 forms a Schottky barrier (potential barrier) of, for example, 0.52 eV to 0.9 eV between the Schottky metal 155 and the silicon semiconductor that constitutes the epitaxial layer 152. The thickness of the Schottky metal 155 is, for example, 0.02 to 0.20 μm.

[0273] The electrode metal 156 is a portion of the anode electrode 154 that is exposed on the outermost surface of the first diode 14U and to which the first diode wire 65U and the like are joined. That is, the electrode metal 156 constitutes the anode electrode pad 14a. The electrode metal 156 is made of, for example, aluminum (Al). The thickness of the electrode metal 156 is thicker than that of the Schottky metal 155 and is, for example, 0.5 to 5.0 μm.

[0274] A surface protection film 157 made of silicon nitride (SiN) is formed on the outermost surface of the first diode 14U. An opening 157a exposing the electrode metal 156 is formed in the center of the surface protection film 157. The first diode wire 65U and the like are bonded to the electrode metal 156 through the opening 157a.

[0275] A region of the surface 152A of the epitaxial layer 152 where the Schottky metal 155 is in Schottky contact with the surface 152A of the epitaxial layer 152 is defined as an active region 158, and a region surrounding the active region 158 is defined as an outer peripheral region 159. In the surface layer portion of the epitaxial layer 152, an outer peripheral trench 160 is formed at the boundary between the active region 158 and the outer peripheral region 159 by digging down from the surface 152A of the epitaxial layer 152. The outer peripheral trench 160 is annular in plan view and is formed along the boundary between the active region 158 and the outer peripheral region 159 so as to straddle them. The bottom surface of the outer peripheral trench 160 includes a flat surface along the surface 152A of the epitaxial layer 152 and the surface 150A of the semiconductor substrate 150. Therefore, the cross section of the outer peripheral trench 160 is approximately rectangular.

[0276] An insulating layer 161 made of, for example, silicon oxide (SiO2) is formed on the entire inner wall surface (side surface and bottom surface) of the outer periphery trench 160. The insulating layer 161 has a thickness of, for example, 0.2 to 0.5 μm.

[0277] A conductor 162 made of polysilicon is provided in the peripheral trench 160. The conductor 162 is connected to the Schottky metal 155 and faces the entire inner wall surface (including the side and bottom surface) of the peripheral trench 160 via the insulating layer 161. The conductor 162 may be provided so as to completely fill the space in the peripheral trench 160 in which the insulating layer 161 is formed, or may be formed in the form of a film along the inner surface of the insulating layer 161. Thus, the first diode 14U is a planar Schottky barrier diode in which the surface of the epitaxial layer 152 with which the Schottky metal 155 is in Schottky contact is flat.

[0278] In the second embodiment, the position of the diode 13 in the integrated circuit element 25L can be changed arbitrarily. The diode 13 is preferably disposed around the source ground circuit 21a of each of the drive circuits 21UL, 21VL, and 21WL. This allows the length of the restriction wiring 21e connecting the diode 13 and the output wiring 21d of the source ground circuit 21a to be shortened. It is more preferable that the diode 13 is provided between the source ground circuit 21a of each of the drive circuits 21UL, 21VL, and 21WL and the output terminal 25a and the input terminal 25b in the second direction Y. This allows the length of the restriction wiring 21e to be further shortened. The diode 13 may be provided as a semiconductor chip separate from the integrated circuit element 25L.

[0279] In each of the above embodiments, the semiconductor device 1 including the MOSFETs 11U-11W and 12U-12W of the first inverter circuit 10U, the second inverter circuit 10V, and the third inverter circuit 10W has been described, but the configuration of the semiconductor device 1 is not limited to this. For example, as shown in Figs. 37 and 38, the semiconductor device 1 may include one inverter circuit.

[0280] More specifically, as shown in FIG. 37, the semiconductor device 1 includes one inverter circuit 10A as the driving unit 10, and one drive circuit 21A and one logic circuit 22A as the control circuit 20. The inverter circuit 10A includes a MOSFET 11U and a MOSFET 12L. The drain of the MOSFET 11U is connected to an external power supply, and the source of the MOSFET 11U is connected to the drain of the MOSFET 12L. The source of the MOSFET 12L is grounded. The drive circuit 21A includes a drive circuit 21AU and a drive circuit 21AL, and the logic circuit 22A includes a logic circuit 22AU and a logic circuit 22AL. The drive circuit 21AU is connected to the gate of the MOSFET 11U and outputs a gate drive signal to the gate. The drive circuit 21AL is connected to the gate of the MOSFET 12L and outputs a gate drive signal to the gate. The logic circuit 22AU is connected to the drive circuit 21AU and outputs a signal to the drive circuit 21AU for the drive circuit 21AU to generate a gate drive signal. The logic circuit 22AL is connected to the drive circuit 21AL, and outputs a signal to the drive circuit 21AL for causing the drive circuit 21AL to generate a gate drive signal.

[0281] As shown in FIG. 38, in the semiconductor device 1, the MOSFET 11U, the MOSFET 12L, and the integrated circuit element 25A including the drive circuit 21A and the logic circuit 22A are provided as semiconductor chips. The semiconductor device 1 includes a lead 200 on which the MOSFET 11U, the MOSFET 12L, and the control circuit 20 are mounted, and a sealing resin 220 that seals the MOSFET 11U, the MOSFET 12L, and the integrated circuit element 25A. The sealing resin 220 is formed of, for example, a black epoxy resin, and is formed in a rectangular shape in a plan view. The sealing resin 220 has a first side 221 and a second side 222 as side surfaces along its longitudinal direction, and a third side 223 and a fourth side 224 as side surfaces along a direction perpendicular to the longitudinal direction in a plan view. In the following description, the direction along the longitudinal direction of the sealing resin 220 is defined as a "first direction V", and the direction perpendicular to the first direction V in a plan view is defined as a "second direction W".

[0282] The lead 200 has a frame 201, a frame 205, a control frame 209, and first to sixth terminal frames 213 to 218 as a plurality of terminal frames. The frame 201 is disposed on a first side surface 221 side, which is one end (left end in FIG. 35) of the sealing resin 220 in the first direction V, and the frame 205 is disposed on a second side surface 222 side, which is the other end (right end in FIG. 35) of the sealing resin 220 in the first direction V. The frame 201 and the frame 205 are formed to be symmetrical with respect to a center line CL extending along the first direction V at the center of the second direction W of the sealing resin 220. The control frame 209 and the first to sixth terminal frames 213 to 218 are disposed on a fourth side surface 224 side, which is one end (lower end in FIG. 35) of the sealing resin 220 in the first direction V.

[0283] The frame 201 is a lead frame for electrically connecting the drain of the MOSFET 11U to an external power supply, and constitutes a VDC terminal. The frame 201 has an island portion 202, a terminal portion 203, and a connection portion 204. The island portion 202, the terminal portion 203, and the connection portion 204 are integrally formed.

[0284] Frame 205 is a lead frame for electrically connecting the drain of MOSFET 12L to an apparatus or electronic component electrically connected to semiconductor device 1, and constitutes an output terminal (OUT terminal). Frame 205 has island portion 206, terminal portion 207, and connection portion 208. Island portion 206, terminal portion 207, and connection portion 208 are integrally formed.

[0285] The island portion 202 of the frame 201 and the island portion 206 of the frame 205 are disposed closer to the third side surface 223 of the sealing resin 220 in the second direction W, and are disposed side by side in the second direction W. The island portion 202 and the island portion 206 are rectangular in shape with the second direction W as the longitudinal direction in a plan view. The island portion 202 and the island portion 206 protrude from the third side surface 223 of the sealing resin 220 in the second direction W. The island portion 202 and the island portion 206 are symmetrical with respect to the center line CL.

[0286] The connection portion 204 of the frame 201 extends from an end portion of the island portion 202 on the first side surface 221 side and the fourth side surface 224 side of the sealing resin 220 toward the fourth side surface 224. The terminal portion 203 of the frame 201 extends from the connection portion 204 along the second direction W. The terminal portion 203 and the connection portion 204 are disposed closer to the first side surface 221 of the sealing resin 220 than the frame 205, the control frame 209, and the first to sixth terminal frames 213 to 218.

[0287] The connection portion 208 of the frame 205 extends from an end portion of the island portion 206 on the second side face 222 side and the fourth side face 224 side of the sealing resin 220 toward the fourth side face 224. The terminal portion 207 of the frame 205 extends from the connection portion 208 along the second direction W. The terminal portion 207 and the connection portion 208 are disposed closer to the second side face 222 of the sealing resin 220 than the frame 201, the control frame 209, and the first to sixth terminal frames 213 to 218.

[0288] The control frame 209 and the first to sixth terminal frames 213 to 218 are arranged on the fourth side 224 side of the sealing resin 220 relative to the island portion 202 of the frame 201 and the island portion 206 of the frame 205 in the second direction W, and are arranged between the connection portion 204 of the frame 201 and the connection portion 208 of the frame 205 in the second direction W.

[0289] The control frame 209 is a lead frame for grounding the integrated circuit element 25A and constitutes a GND terminal. The control frame 209 has an island portion 210, a terminal portion 211, and a connection portion 212. The island portion 210, the terminal portion 211, and the connection portion 212 are integrally formed.

[0290] The island portion 210 is formed in a rectangular shape with the first direction V being the longitudinal direction. The island portion 210 is disposed closer to the first side surface 221 of the sealing resin 220 in the first direction V. The island portion 210 is disposed at a position different from the island portion 202 of the frame 201 and the island portion 206 of the frame 205 in the second direction W. More specifically, the island portion 210 is disposed closer to the fourth side surface 224 of the sealing resin 220 than the island portion 202 and the island portion 206, and disposed at a position overlapping with the island portion 202 and the island portion 206 when viewed from the second direction W. The island portion 210 is disposed closer to the connection portion 204 of the frame 201 than the connection portion 208 of the frame 205 in the second direction W.

[0291] The connection portion 212 of the control frame 209 extends from approximately the center of the island portion 210 in the first direction V toward the fourth side surface 224 of the sealing resin 220. The terminal portion 211 of the control frame 209 extends along the second direction W from the end of the connection portion 212 on the fourth side surface 224 side of the sealing resin 220.

[0292] The first terminal frame 213 is a lead frame for grounding the source of the MOSFET 12L, and constitutes a PGND terminal. The second terminal frame 214 constitutes a VCC terminal, which is an application terminal of the power supply voltage VCC. The third terminal frame 215 constitutes a power short detection terminal (FOB terminal) that detects a state in which the voltage applied to the OUT terminal (frame 205) is shorted to a high voltage application terminal (or a high potential terminal equivalent thereto). The fourth terminal frame 216 constitutes an HIN terminal to which a gate drive signal voltage input from a gate drive circuit (not shown) external to the semiconductor device 1 is applied to the gate of the MOSFET 11U. The fifth terminal frame 217 constitutes a LIN terminal to which a gate drive signal voltage input from the gate drive circuit to the gate of the MOSFET 12L is applied. The sixth terminal frame 218 constitutes a VB terminal, which is an application terminal of a boost voltage VB obtained by boosting the power supply voltage VCC.

[0293] The first terminal frame 213 and the fourth to sixth terminal frames 216-218 are arranged between the connection portion 212 of the control frame 209 and the connection portion 208 of the frame 205 in the first direction V. The second terminal frame 214 and the third terminal frame 215 are arranged between the connection portion 212 of the control frame 209 and the connection portion 204 of the frame 201 in the first direction V.

[0294] The first terminal frame 213 has a rectangular island portion 213a whose longitudinal direction is the second direction W. The island portion 213a is disposed between the island portion 210 of the control frame 209 and the connection portion 208 of the frame 205 in the first direction V. The island portion 213a is disposed adjacent to the island portion 206 of the frame 205 in the second direction W. The fourth to sixth terminal frames 216 to 218 are disposed closer to the fourth side surface 224 of the sealing resin 220 than the island portion 210 of the control frame 209 and the island portion 213a of the first terminal frame 213 in the second direction W. The second terminal frame 214 and the third terminal frame 215 are disposed closer to the fourth side surface 224 of the sealing resin 220 than the island portion 210 of the control frame 209.

[0295] The MOSFET 11U is mounted by solder or the like on a portion of the island portion 202 of the frame 201 close to the fourth side surface 224 of the sealing resin 220. That is, the drain of the MOSFET 11U is electrically connected to the island portion 202 of the frame 201. The MOSFET 11U is disposed such that its gate electrode pad 11g is on the first side surface 221 side and the fourth side surface 224 side of the sealing resin 220.

[0296] The MOSFET 12L is mounted by solder or the like on a portion of the island portion 206 of the frame 205 close to the fourth side surface 224 of the sealing resin 220. That is, the drain of the MOSFET 12L is electrically connected to the island portion 206 of the frame 205. The MOSFET 12L is arranged such that its gate electrode pad 12g is on the MOSFET 11U side and on the fourth side surface 224 side of the sealing resin 220. That is, in FIG. 35, the orientation (position) of the MOSFET 11U and the orientation (position) of the MOSFET 12L are the same.

[0297] The integrated circuit element 25A is mounted by solder or the like on an island portion 210 of the control frame 209. The integrated circuit element 25A is disposed closer to the MOSFET 11U in the second direction W than to the MOSFET 12L.

[0298] The source electrode pad 11s of the MOSFET 11U and the frame 205 are electrically connected by a wire 60. This electrically connects the source of the MOSFET 11U and the drain of the MOSFET 12L. The wire 60 is connected to a portion of the island portion 206 of the frame 205 that is closer to the third side surface 223 of the sealing resin 220 than the MOSFET 12L. The source electrode pad 11s of the MOSFET 11U and the integrated circuit element 25A are connected by a wire 62, and the gate electrode pad 11g of the MOSFET 11U and the integrated circuit element 25A are connected by a wire 62. The control wire 62 connected to the gate electrode pad 11g is disposed closer to the first side surface 221 of the sealing resin 220 than the wire 63, which is an example of a limiting wire connected to the source electrode pad 11s.

[0299] The source electrode pad 12s of the MOSFET 12L and the island portion 213a of the first terminal frame 213 are electrically connected by a wire 61. The wire 61 is connected to the island portion 213a of the first terminal frame 213. The gate electrode pad 12g of the MOSFET 12L and the integrated circuit element 25A are connected by a wire 62, and the source electrode pad 12s of the MOSFET 12L and the integrated circuit element 25A are connected by a sense wire 63. The wire 62 connected to the gate electrode pad 12g is disposed closer to the MOSFET 11U side than the wire 63 connected to the source electrode pad 12s. The wire 63 is connected to the source of the second MOSFET 21c of the source ground circuit 21a in the drive circuit 21AL in the integrated circuit element 25A via the limiting wiring 21e (see FIG. 37). This makes it possible to obtain an effect equivalent to the effect of (1-1) of the first embodiment.

[0300] Moreover, the integrated circuit element 25A is connected to the frame 201, the control frame 209, and the first to sixth terminal frames 213 to 218 by wires 62. More specifically, the integrated circuit element 25A and the connection portion 204 of the frame 201 are connected by one wire 62. The integrated circuit element 25A and the connection portion 212 of the control frame 209 are connected by one wire 62. The integrated circuit element 25A and a portion of the first terminal frame 213 that is closer to the fourth side surface 224 of the sealing resin 220 than the island portion 213a are connected by one wire 62. The integrated circuit element 25A and the second terminal frame 214 are connected by two wires 62. The integrated circuit element 25A and the third to sixth terminal frames 215 to 218 are each connected by one wire 62.

[0301] 37 and 38, the semiconductor device 1 includes a limiting unit CV that suppresses fluctuations in the source-gate voltage of the MOSFET 12L due to voltage fluctuations at the source of the MOSFET 12L. The limiting unit CV has a limiting path RS that electrically connects the control path RC and the source of the MOSFET 12L. The limiting path RS has a wire 63 that connects the source electrode pad 12s of the MOSFET 12L and the input terminal 25b of the integrated circuit element 25A, and a limiting wiring 21e of the drive circuit 21AL. In other words, the wire 63 constitutes a part of the limiting path RS.

[0302] The semiconductor device 1 also includes a control path RC (see FIG. 37) that electrically connects the drive circuit 21AL and the gate of the MOSFET 12L and transmits a drive signal of the drive circuit 21AL. The control path RC has a wire 62 that connects the gate electrode pad 12g of the MOSFET 12L and the output terminal 25a of the integrated circuit element 25A, and an output wiring 21d of the drive circuit 21AL. In other words, the wire 62 that connects the gate electrode pad 12g of the MOSFET 12L and the output terminal 25a configures a part of the control path RC.

[0303] 38, a diode 13 may be added between the wire 62 connected to the source electrode pad 12s of the MOSFET 12L and the output wiring 21d of the drive circuit 21AL. This makes it possible to obtain an effect similar to that of the second embodiment (2-1). The diode 13 may be provided inside the integrated circuit element 25A, or may be provided as a semiconductor chip separate from the integrated circuit element 25A.

[0304] In the modification shown in FIG. 38, the orientation of the MOSFETs 11U and 12L can be changed arbitrarily. In one example, as shown in FIG. 39, the orientation of the MOSFET 11U is changed so that the gate electrode pad 11g of the MOSFET 11U approaches the control circuit 20. More specifically, the MOSFET 11U is arranged so that the gate electrode pad 11g of the MOSFET 11U is located on the control circuit 20 side and the MOSFET 12L side on the surface of the MOSFET 11U. In this case, the wire 62 connecting the control circuit 20 and the gate electrode pad 11g of the MOSFET 11U is arranged closer to the MOSFET 12L than the wire 62 connecting the control circuit 20 and the source electrode pad 11s of the MOSFET 11U. Note that in the modification shown in FIG. 39, the wire 62 connecting the source electrode pad 12s of the MOSFET 12L and the control circuit 20 may be omitted.

[0305] In each of the above embodiments, the orientation (position) of the MOSFETs 11U to 11W relative to the island portion 31a of the frame 31 can be changed as desired. For example, the orientation (position) of the MOSFET 11U may be changed so that the gate electrode pad 11g of the MOSFET 11U approaches the integrated circuit element 25H. This configuration can provide effects similar to those of the third embodiment.

[0306] <Additional Notes> [Appendix A1] an inverter circuit including a first switching element to which a power supply voltage is supplied, and a second switching element having a first terminal connected to the first switching element, a second terminal connected to ground, and a control terminal; a first control circuit that controls the first switching element; a second control circuit that controls the second switching element; a limiting unit that suppresses a fluctuation in voltage between the second terminal and the control terminal based on a voltage fluctuation at the second terminal of the second switching element. Semiconductor device.

[0307] [Appendix A2] an integrated circuit element provided apart from the inverter circuit, on which the second control circuit is mounted, and having an output terminal and an input terminal electrically connected to the second control circuit; the semiconductor device includes a control wire electrically connecting the control terminal and the output terminal; The limiting portion includes a limiting wire that is provided separately from the control wire and electrically connects the input terminal and the second terminal. 13. The semiconductor device according to claim 12 .

[0308] [Appendix A3] the second control circuit has a drive signal output circuit that outputs a drive signal; the semiconductor device includes a control path that electrically connects the drive signal output circuit and the control terminal and through which the drive signal is transmitted; the limiting unit has a limiting path that electrically connects the control path and a second terminal of the second switching element, the control wire constitutes a part of the control path; The restricting wire constitutes a part of the restricting path. 2. The semiconductor device according to claim 1 .

[0309] [Appendix A4] the control path includes an output wiring provided in the integrated circuit element and electrically connecting the drive signal output circuit and the output terminal; The restriction path includes a restriction wiring provided in the integrated circuit element and electrically connecting the input terminal and the output wiring of the integrated circuit element. 10. The semiconductor device according to claim 9,

[0310] [Appendix A5] The limiting unit has a diode provided in the limiting path, an anode of the diode electrically connected to a second terminal of the second switching element; The cathode of the diode is electrically connected to the drive signal output circuit. The semiconductor device according to appendix A3 or A4.

[0311] [Appendix A6] The diode is mounted on the integrated circuit element and is provided on the limiting wiring. The semiconductor device according to Appendix A5, which cites Appendix A4.

[0312] [Appendix A7] The diode is disposed around the drive signal output circuit within the integrated circuit element. The semiconductor device according to Appendix A6.

[0313] [Appendix A8] the second control circuit further includes a logic circuit that controls the drive signal output circuit, In the integrated circuit element, the drive signal output circuit is disposed closer to the second switching element than the logic circuit, The diode is disposed on the second switching element side with respect to the drive signal output circuit. The semiconductor device according to Appendix A7.

[0314] [Appendix A9] the second switching element includes a ground electrode pad serving as the second terminal and a control electrode pad serving as the control terminal, the control wire is connected to the output terminal of the integrated circuit element and to the control electrode pad; The limiting wire is connected to the ground electrode pad and the input terminal of the integrated circuit element. The semiconductor device according to any one of Appendices A2 to A8.

[0315] [Appendix A10] a power wire is connected to the ground electrode pad for connecting the ground electrode pad to the ground; The diameter of the limiting wire is smaller than the diameter of the power wire. The semiconductor device according to claim A9.

[0316] [Appendix A11] The limiting wire is connected to a portion of the ground electrode pad closer to the integrated circuit element than a portion to which the power wire is connected in a plan view. The semiconductor device according to claim A10.

[0317] [Appendix A12] the inverter circuit includes a first inverter circuit, a second inverter circuit, and a third inverter circuit connected in parallel with each other; The limiting portion includes a first limiting portion, a second limiting portion, and a third limiting portion, the first limiting unit suppresses a fluctuation in voltage between a second terminal of a second switching element in the first inverter circuit and a control terminal based on a voltage fluctuation at a second terminal of a second switching element in the first inverter circuit; the second limiting unit suppresses a fluctuation in voltage between a second terminal of a second switching element in the second inverter circuit and a control terminal based on a voltage fluctuation at a second terminal of a second switching element in the second inverter circuit; The third limiting unit suppresses a fluctuation in voltage between a second terminal of a second switching element in the third inverter circuit and a control terminal based on a voltage fluctuation at a second terminal of a second switching element in the third inverter circuit. The semiconductor device according to any one of Appendix A1 to A11.

[0318] [Appendix A13] the second control circuit is implemented in an integrated circuit device; the second control circuit includes a third control circuit that controls a second switching element of the first inverter circuit, a fourth control circuit that controls the second switching element of the second inverter circuit, and a fifth control circuit that controls the second switching element of the third inverter circuit; the second switching element of the first inverter circuit, the second switching element of the second inverter circuit, and the second switching element of the third inverter circuit are each formed in a rectangular shape in a plan view, and each have a ground electrode pad as the second terminal and a control electrode pad as the control terminal, the integrated circuit element has a first input terminal and a first output terminal electrically connected to the third control circuit, a second input terminal and a second output terminal electrically connected to the fourth control circuit, and a third input terminal and a third output terminal electrically connected to the fifth control circuit; The semiconductor device includes: a first frame on which a second switching element of the first inverter circuit is mounted; a second frame on which a second switching element of the second inverter circuit is mounted; a third frame on which a second switching element of the third inverter circuit is mounted; a first control wire connecting a control electrode pad of a second switching element of the first inverter circuit and the first output terminal; a first limiting wire connecting a ground electrode pad of a second switching element of the first inverter circuit and the first input terminal; a second control wire connecting a control electrode pad of a second switching element of the second inverter circuit and the second output terminal; a second limiting wire connecting a ground electrode pad of a second switching element of the second inverter circuit and the second input terminal; a third control wire connecting a control electrode pad of a second switching element of the third inverter circuit and the third output terminal; a third limiting wire connecting a ground electrode pad of a second switching element of the third inverter circuit and the third input terminal; Equipped with the first frame, the second frame, and the third frame are spaced apart from one another and are arranged along an arrangement direction of the third control circuit, the fourth control circuit, and the fifth control circuit such that the first frame and the third frame sandwich the second frame; The second frame is disposed so as to face the integrated circuit elements in a direction perpendicular to the arrangement direction in a plan view. The semiconductor device according to claim A12.

[0319] [Appendix A14] a control electrode pad of a second switching element of each of the first inverter circuit, the second inverter circuit, and the third inverter circuit is formed at any one of four corners of the second switching element in a plan view; At least one of the second switching element of the first inverter circuit and the second switching element of the third inverter circuit is disposed in a position different from that of the second switching element of the second inverter circuit so that a control electrode pad of the second switching element is close to the integrated circuit element. The semiconductor device according to Appendix A13.

[0320] [Appendix A15] an inverter circuit including a first switching element to which a power supply voltage is supplied, and a second switching element having a first terminal connected to the first switching element, a second terminal connected to ground, and a control terminal; a limiting unit that suppresses a fluctuation in the potential of the second terminal of the second switching element when the first switching element is on. Semiconductor device.

[0321] [Appendix A16] The semiconductor device includes a frame serving as the ground, the limiting portion includes a second diode, a second power wire, and a second diode wire; the second diode is provided separately from the second switching element, and includes a cathode electrically connected to a first terminal of the second switching element and an anode electrically connected to the frame, the second diode wire electrically connects a second terminal of the second switching element and the frame; The second diode wire electrically connects the anode of the second diode to the frame. The semiconductor device according to Appendix A15.

[0322] [Appendix A17] The second diode is a Schottky barrier diode. The semiconductor device according to Appendix A16.

[0323] [Appendix A18] A position to which the second power wire is connected and a position to which the second diode wire is connected in the frame are different from each other. The semiconductor device according to appendix A16 or A17.

[0324] [Appendix A19] the first switching element has a first terminal to which a power supply voltage is supplied and a second terminal connected to a first terminal of the second switching element; The semiconductor device further comprises a first diode; The first diode is provided separately from the first switching element and includes a cathode electrically connected to a first terminal of the first switching element and an anode electrically connected to a second terminal of the first switching element. The semiconductor device according to any one of Appendix A16 to A18.

[0325] [Appendix A20] a lead frame on which the second switching element and the second diode are mounted, and a first terminal of the second switching element and a cathode of the second diode are electrically connected; a first power wire electrically connecting a second terminal of the first switching element and the lead frame; a first diode wire electrically connecting the anode of the first diode and the lead frame; Equipped The semiconductor device according to Appendix A19.

[0326] [Appendix A21] The position to which the first power wire is connected and the position to which the first diode wire is connected are different from each other in the lead frame. The semiconductor device according to Appendix A20.

[0327] [Appendix A22] the inverter circuit includes a first inverter circuit, a second inverter circuit, and a third inverter circuit connected in parallel with each other; The limiting portion includes a first limiting portion, a second limiting portion, and a third limiting portion, the first limiting unit suppresses a fluctuation in a potential of a second terminal of a second switching element of the first inverter circuit when a first switching element of the first inverter circuit is on; the second limiting unit suppresses a fluctuation in a potential of a second terminal of a second switching element of the second inverter circuit when a first switching element of the second inverter circuit is on; The third limiting unit suppresses a fluctuation in potential of a second terminal of a second switching element of the third inverter circuit when a first switching element of the third inverter circuit is turned on. The semiconductor device according to any one of Appendix A15 to A21.

[0328] [Appendix A23] a second diode provided separately from the second switching element, the second diode including a cathode electrically connected to a first terminal of the second switching element and an anode electrically connected to the frame serving as the ground; a lead frame on which the second switching element and the second diode are mounted and to which a first terminal of the second switching element and a cathode of the second diode are electrically connected; the lead frame includes a first frame, a second frame, and a third frame; the second diodes include a sixth diode, a seventh diode, and an eighth diode; the sixth diode has a cathode electrically connected to a first terminal of a second switching element of the first inverter circuit and an anode electrically connected to a second terminal of the second switching element, the seventh diode has a cathode electrically connected to a first terminal of a second switching element of the second inverter circuit and an anode electrically connected to a second terminal of the second switching element, the eighth diode has a cathode electrically connected to a first terminal of a second switching element of the third inverter circuit and an anode electrically connected to a second terminal of the second switching element, a second switching element of the first inverter circuit and the sixth diode are mounted on the first frame; the second frame is disposed at a distance from the first frame, a second switching element of the second inverter circuit and the seventh diode are mounted on the second frame, the third frame is disposed at a distance from the first frame and the second frame, a second switching element of the third inverter circuit and the eighth diode are mounted on the third frame, The frame includes a first ground frame, a second ground frame, and a third ground frame spaced apart from each other, The first limiting portion is The sixth diode; a fourth power wire electrically connecting a second terminal of a second switching element of the first inverter circuit and the first ground frame; a fourth diode wire electrically connecting the anode of the sixth diode and the first ground frame; having The second limiting portion is the seventh diode; a fifth power wire electrically connecting a second terminal of a second switching element of the second inverter circuit and the second ground frame; a fifth diode wire electrically connecting the anode of the seventh diode and the second ground frame; having The third limiting portion is the eighth diode; a sixth power wire electrically connecting a second terminal of a second switching element of the third inverter circuit and the third ground frame; a sixth diode wire electrically connecting the anode of the eighth diode and the third ground frame; have 2. The semiconductor device according to claim 1,

[0329] [Appendix A24] The semiconductor device includes: a third diode provided separately from the first switching element of the first inverter circuit, the third diode including a cathode electrically connected to a first terminal of the first switching element and an anode electrically connected to a second terminal of the first switching element; a first power wire electrically connecting a second terminal of a first switching element of the first inverter circuit and the first frame; a fourth diode provided separately from the first switching element of the second inverter circuit, the fourth diode including a cathode electrically connected to a first terminal of the first switching element and an anode electrically connected to a second terminal of the first switching element; a second power wire electrically connecting a second terminal of a first switching element of the second inverter circuit and the second frame; a fifth diode provided separately from the second switching element of the third inverter circuit, the fifth diode including a cathode electrically connected to a first terminal of the second switching element and an anode electrically connected to a second terminal of the second switching element; a third power wire electrically connecting a second terminal of a first switching element of the third inverter circuit and the third frame; Equipped The semiconductor device according to Appendix A23.

[0330] [Appendix A25] a first diode wire electrically connecting the anode of the third diode and the first frame; a second diode wire electrically connecting the anode of the fourth diode and the second frame; a third diode wire electrically connecting the anode of the fifth diode and the third frame; Equipped The semiconductor device according to Appendix A24.

[0331] [Appendix A26] The current flowing through the second switching element is less than 30A. The semiconductor device according to any one of Appendix A1 to A25.

[0332] [Appendix A27] The second switching element is a SiC MOSFET. The semiconductor device according to any one of Appendix A1 to A26.

[0333] [Appendix B1] a first switching element to which a power supply voltage is supplied; a second switching element formed in a rectangular shape in a plan view, the second switching element having a first electrode connected to the first switching element, a second electrode connected to ground, and a control electrode; a first inverter circuit, a second inverter circuit, and a third inverter circuit, each including the first switching element and the second switching element, and connected in parallel with each other; a first conductive layer on which the first switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are mounted; a second conductive layer provided apart from the first conductive layer and on which the second switching element of the first inverter circuit is mounted; a third conductive layer provided apart from the first conductive layer and on which the second switching element of the second inverter circuit is mounted; a fourth conductive layer provided apart from the first conductive layer and on which the second switching element of the third inverter circuit is mounted; an integrated circuit device provided apart from the first inverter circuit, the second inverter circuit, and the third inverter circuit, and including a control circuit for controlling the second switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit; a control wire electrically connecting a control electrode of the second switching element of the first inverter circuit, the second inverter circuit, and the third inverter circuit to the integrated circuit element; the second conductive layer, the third conductive layer, and the fourth conductive layer are insulated from each other and spaced apart in a first direction; the first switching elements are mounted on the common first conductive layer in the same orientation as one another in a plan view; the second conductive layer has a first element mounting region in which the second switching element of the first inverter circuit is mounted, the third conductive layer has a second element mounting region in which the second switching element of the second inverter circuit is mounted, the fourth conductive layer has a third element mounting region in which the second switching element of the third inverter circuit is mounted, the first element mounting region, the second element mounting region, and the third element mounting region are formed to have the same shape as one another and to be rectangular in a plan view; a center of at least one of the second switching elements mounted in the first element mounting region, the second element mounting region, and the third element mounting region is mounted so as to be spaced apart from one another in a second direction intersecting the first direction in a plan view; At least one of the second switching elements in the first element mounting region, the second switching elements in the second element mounting region, and the second switching elements in the third element mounting region is inclined with respect to the other second switching elements in a plan view. Semiconductor device.

[0334] [Appendix B2] the semiconductor device is formed in a rectangular shape with the first direction being a longitudinal direction in a plan view, The second switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are arranged side by side in the first direction in a plan view, and are disposed at positions where at least a portion of the second switching elements overlap each other when viewed from the first direction. 4. The semiconductor device according to claim 1.

[0335] [Appendix B3] a sealing resin formed in a flat rectangular shape that seals the first inverter circuit, the second inverter circuit, the third inverter circuit, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the integrated circuit element, and the control wire, the sealing resin has a side surface from which a plurality of first terminal portions electrically connected to a control electrode of the first switching element protrude, the first terminal portions are spaced apart from one another in a direction in which the side surfaces extend in a plan view, The side surface has a recess in a portion between adjacent first terminal portions among the plurality of first terminal portions in an extending direction of the side surface. The semiconductor device according to appendix B1 or B2.

[0336] [Appendix B4] In a plan view, the size of the recess in the direction in which the side surface extends is larger than the size of the recess in the direction perpendicular to the direction in which the side surface extends. 4. The semiconductor device according to claim 3.

[0337] [Appendix B5] a plurality of second terminals protruding from the side surface and electrically connected to the integrated circuit element; the second terminal portions are spaced apart from one another in a direction in which the side surface extends in a plan view, In a plan view, a distance between two of the plurality of first terminal portions arranged on both sides of the recess is greater than a distance between adjacent second terminal portions among the plurality of second terminal portions in a direction in which the side surfaces extend. The semiconductor device according to appendix B3 or B4.

[0338] [Appendix B6] The current flowing through the second switching element is less than 30A. The semiconductor device according to any one of Appendix B1 to B5.

[0339] [Appendix B7] The second switching element is a SiC MOSFET. The semiconductor device according to any one of Appendix B1 to B6. [Explanation of symbols]

[0340] 1 Semiconductor device 10A inverter circuit 10U 1st inverter circuit 10V 2nd inverter circuit 10W 3rd inverter circuit 11 First switching element 11U, 11V, 11W MOSFET (first switching element) 12 Second switching element 12U, 12V, 12W MOSFET (second switching element) 12s Source electrode pad (ground electrode pad) 12g Gate electrode pad (control electrode pad) 13. Diode 14U 1st diode (2nd diode, 6th diode) 14V 2nd Diode (2nd Diode, 7th Diode) 14W 3rd diode (2nd diode, 8th diode) 15U 1st diode (1st diode, 3rd diode) 15V 2nd Diode (1st Diode, 4th Diode) 15W 3rd diode (1st diode, 5th diode) 21 Drive circuit (drive signal output circuit) 21UU Drive circuit (first control circuit) 21VU drive circuit (first control circuit) 21WU Drive circuit (first control circuit) 21UL Drive circuit (2nd control circuit, 3rd control circuit) 21VL Drive circuit (2nd control circuit, 4th control circuit) 21WL Drive circuit (2nd control circuit, 5th control circuit) 21a Source ground circuit 21d Output wiring 21e Restricted Wiring 22 Logic Circuits 22UU Logic circuit (first control circuit) 22VU Logic circuit (first control circuit) 22WU Logic circuit (first control circuit) 22UL Logic circuit (2nd control circuit, 3rd control circuit) 22VL Logic circuit (2nd control circuit, 4th control circuit) 22WL Logic circuit (2nd control circuit, 5th control circuit) 25L Integrated circuit element (integrated circuit element of second control circuit) 25a Output terminal 25au 1st output terminal (output terminal) 25av 2nd output terminal (output terminal) 25aw 3rd output terminal (output terminal) 25b Input terminal 25bu 1st input terminal (input terminal) 25bv 2nd input terminal (input terminal) 25bw 3rd input terminal (input terminal) 32U 1st Frame 32V 2nd Frame 32W 3rd Frame 35U Frame (Ground Frame, 1st Ground Frame) 35V Frame (Ground Frame, Second Ground Frame) 35W Frame (Ground Frame, 3rd Ground Frame) 60 Wire 60U 1st Wire (1st Power Wire) 60V 2nd Wire (2nd Power Wire) 60W 3rd Wire (3rd Power Wire) 61 Wire 61U 1st wire (4th power wire) 61V 2nd Wire (5th Power Wire) 61W 3rd Wire (6th Power Wire) 62 Control Wire 62U 1st Wire 62V 2nd Wire 62W 3rd Wire 63 Wire (Restrictive Wire) 63U First Wire (First Restricting Wire) 63V 2nd Wire (2nd limiting wire) 63W 3rd Wire (3rd limiting wire) 64U Wire for 1st diode (wire for 4th diode) 64V Wire for 2nd diode (Wire for 5th diode) 64W 3rd Diode Wire (6th Diode Wire) 65U Wire for 1st diode 65V Wire for 2nd Diode 65W 3rd Diode Wire RC Control Path RC1 First control pathway RC2 Second control path RC3 Third control pathway RS Restricted Route RS1 First restricted pathway RS2 Second restriction pathway RS3 3rd restricted route CV Restriction CV1 First Restriction CV2 Second Restriction CV3 Third Restriction CP1 First Restriction Section CP2 Second Restriction Section CP3 Third Restriction Section

Claims

1. a first switching element to which a power supply voltage is supplied; a second switching element formed in a rectangular shape in a plan view, the second switching element having a first electrode connected to the first switching element, a second electrode connected to ground, and a control electrode; a first inverter circuit, a second inverter circuit, and a third inverter circuit each including the first switching element and the second switching element and connected in parallel with each other; a first conductive layer on which the first switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are mounted; a second conductive layer provided apart from the first conductive layer and on which the second switching element of the first inverter circuit is mounted; a third conductive layer provided apart from the first conductive layer and on which the second switching element of the second inverter circuit is mounted; a fourth conductive layer provided apart from the first conductive layer and on which the second switching element of the third inverter circuit is mounted; an integrated circuit element provided at a distance from the first inverter circuit, the second inverter circuit, and the third inverter circuit, and including a control circuit for controlling the second switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit; a control wire electrically connecting a control electrode of the second switching element of the first inverter circuit, the second inverter circuit, and the third inverter circuit to the integrated circuit element; the second conductive layer, the third conductive layer, and the fourth conductive layer are insulated from each other and spaced apart from each other in a first direction; the first switching elements are mounted on the common first conductive layer in the same orientation as one another in a plan view, the second conductive layer has a first element mounting region in which the second switching element of the first inverter circuit is mounted, the third conductive layer has a second element mounting region in which the second switching element of the second inverter circuit is mounted, the fourth conductive layer has a third element mounting region in which the second switching element of the third inverter circuit is mounted, the first element mounting region, the second element mounting region, and the third element mounting region are formed to have the same shape as one another and to have a rectangular shape in a plan view, a center of at least one of the second switching elements mounted in the first element mounting region, the second element mounting region, and the third element mounting region is mounted so as to be spaced apart from one another in a second direction intersecting the first direction in a plan view; a sealing resin formed in a flat rectangular shape that seals the first inverter circuit, the second inverter circuit, the third inverter circuit, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the integrated circuit element, and the control wire, the sealing resin has a third side surface from which a plurality of first terminal portions electrically connected to a control electrode of the first switching element protrude, the first terminal portions are spaced apart from one another in a direction in which the third side surface extends in a plan view, a recess is provided in the third side surface between adjacent first terminal portions among the plurality of first terminal portions in a direction in which the third side surface extends; In a plan view, a size of the recess in a direction in which the third side surface extends is larger than a size of the recess in a direction perpendicular to the direction in which the third side surface extends. Semiconductor device.

2. the semiconductor device is formed in a rectangular shape with the first direction being a longitudinal direction in a plan view, The second switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are arranged side by side in the first direction in a plan view, and are disposed at positions where at least a portion of the second switching elements overlap each other when viewed from the first direction. The semiconductor device according to claim 1 .

3. a plurality of second terminals protruding from the third side surface and electrically connected to the integrated circuit element; the second terminal portions are spaced apart from one another in a direction in which the third side surface extends in a plan view, In a plan view, a distance between two of the first terminal portions arranged on both sides of the recess among the plurality of first terminal portions is greater than a distance between adjacent second terminal portions among the plurality of second terminal portions in a direction in which the third side surface extends. The semiconductor device according to claim 1 .

4. the sealing resin has a fourth side surface facing the third side surface and from which a plurality of third terminal portions protrude, each of the third terminal portions includes an island portion that is electrically connected to the second switching element by a power wire and is covered with the sealing resin; The ends of the at least two island portions on the third side surface side are flush with each other. The semiconductor device according to claim 1 .

5. the integrated circuit element is mounted on a fifth conductive layer spaced apart from the first to fourth conductive layers; the first switching element has a back surface on which a drain electrode pad is provided, and a front surface on which a source electrode pad and a gate electrode pad are provided, the sealing resin has a sealing resin rear surface opposite to the rear surface and a sealing resin front surface opposite to the front surface, A connection surface between the integrated circuit element and the fifth conductive layer is located closer to the sealing resin surface than the back surface of the first switching element in a cross-sectional view seen from the first direction. The semiconductor device according to claim 1 .

6. The current flowing through the second switching element is less than 30 A. The semiconductor device according to any one of claims 1 to 5.

7. The second switching element is a SiC MOSFET. The semiconductor device according to any one of claims 1 to 6.

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