High performance power integrated circuit semiconductor device

Abstract

To provide a high-voltage, high-current power integrated circuit semiconductor device that can achieve low loss, small chip area, and high reliability by eliminating the snap-back phenomenon characteristic of reverse-conducting semiconductor elements.SOLUTION: An Si power integrated circuit semiconductor device chip 200 consists of an element-integrated substrate 201 in which a semiconductor chip body with dielectric isolation integrated circuit structure is laid out with single-crystal islands containing integrated circuit components in an isolation area 217 and an element support substrate 202 with both support and conductive path functions for the element-integrated substrates laminated on top of each other, and the element-integrated substrate is provided with a main functional part of vertical semiconductor element in a predetermined single-crystal island and a drain 205 or a collector 204 by removing a dielectric insulation isolation film 206 at the bottom of the single-crystal island and laminated with the element support substrate to form the vertical semiconductor element.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an integrated circuit semiconductor device, and more particularly to a high-performance power integrated circuit semiconductor device suitable for achieving large power capacity, i.e., high voltage resistance and large current, and also suitable for miniaturization and low loss. [Background technology]

[0002] In recent years, Si power integrated circuit semiconductor devices integrating output elements with high withstand voltages and small to medium power capacities have been developed and commercialized for various applications. As these output elements, Si-IGBTs and Si-MOSFETs, which are also used as major semiconductor devices as individual elements, are widely used. However, while Si-IGBT individual elements have been supplied with withstand voltages up to 6.5 kV and 100 A, power integrated circuit semiconductor devices have only withstand voltages of 0.7 kV and current capacity of 20 A due to various constraints, and there is a demand for larger power capacities. On the other hand, Si-IGBTs, which are expected to be used as output elements for power integrated circuit semiconductor devices, have been pursued as individual elements in recent years to achieve high performance such as low loss, and have shown remarkable progress with various innovations to reduce on-resistance and increase turn-off speed. Representative examples include Si reverse conducting IGBTs, which have recently been commercialized as power elements for electric vehicles, as shown in Prior Art Example 1 in FIG. 10 and Prior Art Example 2 in FIG. 11, and are disclosed in Non-Patent Documents 1 and 2, respectively. A brief explanation will be given below, but for the sake of simplicity, an n-channel element will be taken as an example. In the prior art example 1, a collector short-circuited Si-IGBT (n-channel type), - The drift layer is shorted to the collector electrode by an n+ short circuit provided in the p+ collector layer, and when turned off, - By removing carriers remaining in the drift layer through this n+ short circuit, the turn-off time is shortened, resulting in significant loss reduction.

[0003] Incidentally, in the case of Si reverse conducting IGBTs including the disclosed prior art example 1, the output characteristics, i.e., the Ice-Vce characteristics between the collector-emitter voltage (hereinafter referred to as Vce) and the collector-emitter current (hereinafter referred to as Ice), have a snapback phenomenon in which the collector-emitter voltage immediately before turning on is greater than the collector-emitter voltage immediately after turning on, inducing various transient phenomena and impairing reliability. The collector-emitter voltage immediately before turning on is hereinafter referred to as the snapback voltage and written as Vsb, and the collector-emitter current at this Vsb is hereinafter referred to as the snapback current and written as Isb. The Si reverse conducting IGBT (n-channel type) of prior art example 2 is composed of a reverse conducting Si-IGBT region composed of multiple reverse conducting Si-IGBT cells and a pilot IGBT region composed of one pilot IGBT cell. The width of the collector of the pilot IGBT cell is made significantly larger than the width of the collector of the reverse conducting IGBT cell, which significantly increases the lateral resistance of the buffer layer between the short circuits, and the pilot IGBT region turns on before the reverse conducting IGBT region with a small Isb, suppressing the snap-back phenomenon that occurs when turning on, suppressing malfunctions due to transient voltages and transient currents, and improving reliability. Note that these disclosed IGBTs have no blocking capability against reverse voltages because the n drift layer is shorted to the collector electrode by the n+ short circuit, and are therefore collectively referred to as reverse conducting IGBTs. Therefore, all of them will be referred to as reverse conducting IGBTs below.

[0004] Meanwhile, Prior Art Example 3 by the inventors discloses a 650V 25A class dielectric isolation type integrated circuit in which a control low voltage vertical element and horizontal element and an output high voltage vertical IGBT are integrated on the same chip. The control element section suggests that drive circuits and protection circuits can be integrated to achieve high density and high integration of high performance functions, while the output IGBT has a vertical structure to significantly reduce drift resistance, thereby achieving low on-resistance and large current capacity, thereby achieving a significant increase in current, low loss, and high performance of the power integrated circuit semiconductor device.

[0005] In recent years, the development of high-voltage, high-power and medium-power semiconductor devices using wide-gap semiconductors such as SiC semiconductors has been promoted, and significant performance improvements have been made in semiconductor devices such as SiC-MOSFET individual elements and SiC-IGBT individual elements. For example, Prior Art Example 4 discloses a 6.5 kV-class SiC-MOSFET individual element. In this element, a SiC Schottky diode is built in as a flywheeling diode (hereinafter referred to as FWD), which is indispensable for applications such as inverters, and the on-voltage degradation specific to SiC semiconductor devices is suppressed to achieve high performance and high reliability. However, wide-gap semiconductors such as SiC semiconductors have many issues in addition to the crystal quality and large area of ​​semiconductor chips, and the development of basic element circuits is just beginning, and there are no examples of development or practical application of a full-scale power integrated circuit semiconductor device that integrates control circuits and high-voltage, high-current output elements. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] Hajime AKIYAMA and 5 others, EFECTS OF SHORTED COLLECTOR ON CHARACTERISTICS OF IGBTS, Proceedings of The 2nd International Symposium on Power Semiconductor Devices & ICs, April 1990, p.131-136. [Non-Patent Document 2] Litauras Storasta, et al., A Comparison of charge dynamics in the Reverse-Conducting RCIGBT and Bi-mode Insulated Gate Transistor BiGT, Proceedings of The 22nd International Symposium on Power Semiconductor Devices & ICs, June 2010, p.391-394. [Non-Patent Document 3] T. Mizoguchi, T. Shirasawa, M. Mori, Y. Sugawara, 600V, 25A Dielectrically-Isolated Power IC with Vertical IGBT, Proceedings of the 3rd International Symposium on Power Semiconductor Devices & ICs, April 1991, pp. 40-44. [Non-Patent Document 4] Koutarou KAWAHARA and 9 others, 6.5kV Schottky-Barrier-Diode-Embedded SiC-MOSFET for Comact Full-Unipolar Modeule. Proceedings of The 29th International Symposium on Power Semiconductor Devices & ICs, June 2017, p.41-44. Summary of the Invention [Problem to be solved by the invention]

[0007] As mentioned above, the current power integrated circuit semiconductor device is limited to a withstand voltage of 0.7 kV and a current capacity of 25 A or less due to various technical problems, and increasing the power capacity to meet various new needs is an important issue. In order to increase the power capacity, both high withstand voltage and large current must be achieved. Moreover, it must be achieved with a chip size that is economically reasonable (for example, 20 mm x 20 mm or less). As mentioned above, in the IGBT individual elements and MOSFET individual elements expected to be used as output elements of power integrated circuit semiconductor devices, in recent years, low on-resistance and high turn-off speed have been pursued for the purpose of high performance such as low loss, and reverse conducting IGBTs and reverse conducting MOSFETs have been attracting attention as suitable elements. In this specification, reverse conducting semiconductor elements are defined in a narrower sense than the general term

[0003] , and an element that functions as an FWD indispensable for inverters and the like when a high withstand voltage pn main junction in the element is reverse biased is defined as a reverse conducting semiconductor element. In this case, since the FWD is inherent in the element, there is no need to introduce or form a new one separately, and the chip area occupied by the output element can be reduced by nearly half, which is expected to lead to a significant reduction in the area of ​​the integrated circuit semiconductor device chip and therefore lower costs. However, reverse conducting semiconductor elements of this definition have various technical issues, as described below, and there are no examples of them being mounted on power integrated circuit semiconductor devices and put to practical use.

[0008] In various industrial fields, such as mobile devices such as EVs, there is a strong demand for small, lightweight, low-loss, low-cost semiconductor devices with a capacity of 1 kV 10 A or more, and while this is currently being met with semiconductor modules, power integrated circuit semiconductor devices are expected to be significantly smaller, lighter, lower-loss, and lower-cost. Therefore, the first important challenge is to solve the technical problems of the prior art, devise a structure that can accommodate reverse-conducting semiconductor elements such as reverse-conducting IGBTs and reverse-conducting MOSFETs that are suitable for low-loss and high performance (e.g. high reliability), and realize a power integrated circuit semiconductor device with a high breakdown voltage of 1 kV or more and a large current capacity.

[0009] In Prior Art Example 3, the output IGBT of the dielectric type integrated circuit semiconductor device is vertically structured to significantly reduce the drift resistance, and the device has succeeded in achieving low on-resistance and large current capacity, but reverse conducting semiconductor elements are not considered and are not mentioned at all. In the structure of Prior Art Example 3, it is difficult to provide a short circuit on the collector electrode side of the back surface of the element as in the individual elements of Prior Art Examples 1 and 2 because a thick p+ collector is used, so that the loss reduction based on the significant reduction in switching loss due to the shortened turn-off time by mounting a reverse conducting semiconductor element cannot be enjoyed, and the FWD function cannot be achieved by using the p-body junction inherent to the IGBT, so that the chip area must be significantly increased by newly incorporating the reverse conducting semiconductor element into the chip, or it must be externally attached. The second problem to be solved in power integrated circuit semiconductor devices is to be able to mount a reverse conducting semiconductor element with a small occupancy area and low loss.

[0010] However, reverse conducting semiconductor devices such as reverse conducting IGBTs have a short turn-on time, i.e. the time it takes for the device to transition from just before turning on to just after it turns on. Therefore, when the snapback phenomenon occurs, a steep voltage change (hereafter referred to as dV / dt) and a steep current change (hereafter referred to as dI / dt) occur at the time of turning on. As a result, a steep jump in current (C·dv / dt) occurs due to the parasitic capacitance present in the circuit, and a steep jump in voltage (L·dI / dt) occurs due to the parasitic reactor, which induces a large transient phenomenon. This can cause a large disturbance in a circuit that uses a reverse conducting semiconductor device such as a reverse conducting IGBT, resulting in malfunction or, in some cases, damage to elements or circuits, resulting in a significant loss of reliability. Therefore, suppressing or eliminating the snapback phenomenon is a third extremely serious problem in power integrated circuit semiconductor devices in which various circuits are integrated in a small chip area.

[0011] In addition, in the Si reverse conducting IGBT of the prior art example 2, a pilot IGBT region is provided adjacent to the reverse conducting IGBT region consisting of many reverse conducting IGBT cells. The p+ collector width of the pilot IGBT region is made significantly larger than the p+ collector width of the IGBT cells in the reverse conducting IGBT region, so that the lateral resistance of the buffer layer on the p+ collector is made very large, and therefore the pilot IGBT region is turned on first with a small Isb. This suppresses the snapback phenomenon in the pilot IGBT region. However, in the case of the prior art example 2, the area of ​​the pilot IGBT region in the total IGBT chip area becomes quite large. For example, in the case of the prior art example 2, the data shows that the p+ collector width of the standard cell of the Si reverse conducting IGBT designed for 3.3 kV is 180 micrometers, while the p+ collector width of the pilot IGBT is made about 3.6 times as large as the 180 micrometers, so that the Vsb is set to about 0.7 V, which is the built-in voltage, to eliminate the snapback phenomenon. If the p+ collector width of the reverse conducting IGBT standard cell is made much smaller and miniaturized, the lateral resistance of the standard cell is reduced, so a larger current is required to obtain the built-in voltage Vbi of the collector junction, and the p+ collector width of the pilot IGBT must be correspondingly larger. As a result, the snapback phenomenon is eliminated, but the area of ​​the reverse conducting IGBT standard cell region occupying the entire IGBT chip of a given area is reduced, so the number of standard cells integrated in a given chip is reduced, the on-resistance increases, and the original function of the reverse conducting IGBT, which is to remove carriers remaining at the time of turn-off, cannot be effectively performed. In the current situation where the chip size of the element is set to about 20 mm x 20 mm or less from the viewpoint of economics such as yield, eliminating the snapback phenomenon of the reverse conducting semiconductor element in a small occupancy area is an important problem in power integrated circuit semiconductor device, and is the fourth problem to be solved.

[0012] In the prior art example 4, a SiC Schottky diode is built into the SiC-MOSFET as a FWD, which has succeeded in suppressing on-voltage degradation and improving reliability, but the dedicated chip area is significantly increased by about two times. Since the drift resistance increases significantly at higher temperatures or higher withstand voltages, a further significant increase in the area of ​​the SiC Schottky diode is unavoidable in order to reduce loss. In addition, unlike the reverse conducting IGBT, when an excessive current arrives or is supplied due to an accident, the IGBT cannot be operated to increase the current withstand capacity by lowering the on-resistance due to conductivity modulation, so in order to avoid damage to the element, it is necessary to further increase the dedicated chip area of ​​the SiC-MOSFET and SiC-FWD in response to the expected overcurrent. In the current area of ​​integrated circuit semiconductor device chips, which is limited to about 20 mm x 20 mm, the increase in the dedicated area due to the FWD is a significant problem and is the fifth issue to be solved.

[0013] The present invention aims to provide a structure of a power integrated circuit semiconductor device capable of mounting a component element having a large power capacity, i.e., a component element having a high breakdown voltage and / or a large current capacity, particularly a reverse conducting semiconductor element, in order to solve the problems of the prior art and to increase the power capacity. Another object of the present invention is to provide a power integrated circuit semiconductor device having a structure capable of mounting a component element having a large power capacity with a small occupancy area or low loss. Another object of the present invention is to provide a high-performance reverse conducting power integrated circuit semiconductor device capable of reducing the chip size by achieving the FWD function without integrating a separate FWD. Another object of the present invention is to provide a highly reliable power integrated circuit semiconductor device capable of suppressing or eliminating the snapback phenomenon in a high-performance reverse conducting power integrated circuit semiconductor device for output, and capable of eliminating this phenomenon with a smaller occupancy area. Another object of the present invention is to provide a highly reliable high-performance reverse conducting power integrated circuit semiconductor device capable of eliminating or suppressing on-voltage degradation by using a wide-gap semiconductor such as SiC. [Means for solving the problem]

[0014] solution

[0015] Before proceeding, some terms will be defined. In an integrated circuit semiconductor device, the semiconductor portion of an integrated circuit semiconductor device chip excluding electrodes, wiring, insulating protective film, etc. is defined as the chip body and will be described by this name. In addition, the integrated circuit components are connected to other integrated circuit components by wiring via a surface insulating protective film on the semiconductor chip body, and the wiring portion that crosses over the isolation region between the components exposed on the surface within the semiconductor chip body, the dielectric insulating isolation film, and the inclined channel stopper is defined as a jumper wiring. The chip body is composed of an element integration substrate and an element support substrate layered underneath it. The upper part of the chip body, which is composed of an isolation region in which single crystal islands on which elements are formed are laid out with a dielectric insulating isolation film interposed therebetween, is defined as the element integration substrate, and the lower part of the chip body, which supports this substrate and all or part of which functions as a conductive path and a heat dissipation path for the elements, is defined as the element support substrate, and will be described using these names hereinafter. Furthermore, in semiconductor elements integrated on a single crystal island, an element in which both the input and output electrodes are formed on one main surface of the chip, i.e., surface A of the above-mentioned element integration substrate opposite the element support substrate, is defined as a lateral semiconductor element, while an element in which either the input or output electrode is formed on surface A of the element integration substrate and the other electrode is formed on the other main surface of the chip, i.e., surface B of the above-mentioned element support substrate opposite the element integration substrate, is defined as a vertical semiconductor element. In the following, in order to avoid complexity and to facilitate understanding, the following description will focus on a power integrated circuit semiconductor device that uses n-channel type IGBTs and n-channel type MOSFETs as components with large power capacities (e.g., output elements).

[0016] In order to solve the above-mentioned problems and achieve the object of the present invention, the power integrated circuit semiconductor device of the present invention is a dielectrically isolated type integrated circuit semiconductor device, in which the semiconductor chip body is configured by single crystal islands being laid out in an isolation region via a dielectric insulating isolation film, the side of the single crystal island has a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and the integrated circuit components in the single crystal island are connected to the integrated circuit components in other single crystal islands by wiring via a surface insulating protective film on the semiconductor chip body, in the integrated circuit semiconductor device, the components with large power capacity have a novel Surface Carrier Density Decrease Electric Field Reduction Region (abbreviated as SCaDFRR, pronounced SCAD FRR) provided on the surface of the inclined channel stopper layer under the jumper wiring.

[0017] In order to solve the above-mentioned problems and achieve the object of the present invention, the power integrated circuit semiconductor device of the present invention is characterized in that a component element having a large power capacity has a thick embedded insulating protective film provided between the surface carrier concentration reduced electric field relaxation region SCaDFRR on the surface of the gradient channel stopper layer and the surface of the chip body, and the surface insulating protective film is provided on the surface of the chip body in contact with this thick embedded insulating protective film.

[0018] In order to solve the above problems and achieve the object of the present invention, the power integrated circuit semiconductor device according to the present invention is a dielectrically isolated type integrated circuit semiconductor device, the semiconductor chip body of which is configured by single crystal islands being laid out in an isolation region via a dielectric insulating isolation film, the side of the single crystal island having a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and the integrated circuit constituent elements in the single crystal island are connected to the integrated circuit constituent elements in other single crystal islands by wiring via a surface insulating protective film on the semiconductor chip body, The present invention is characterized in that a lateral IGBT is included in a specific single crystal island as an integrated circuit component element, a buffer layer is provided on at least the bottom surface of a collector of the lateral IGBT in contact with the collector, and a part of the buffer layer is exposed on the surface of the semiconductor chip and connected to an electrode of the collector of the lateral IGBT to be short-circuited with the collector.

[0019] In order to solve the above-mentioned problems and achieve the object of the present invention, the power integrated circuit semiconductor device according to the present invention is a dielectrically isolated type integrated circuit semiconductor device, the semiconductor chip body of which is configured by single crystal islands being laid out in an isolation region via a dielectric insulating isolation film, the side surfaces of the single crystal islands having a predetermined angle with respect to the surface of the semiconductor chip body determined by the crystal orientation, and integrated circuit components in the single crystal islands are connected to integrated circuit components in other single crystal islands by wiring via a surface insulating protective film on the semiconductor chip body, the semiconductor chip body of the dielectrically isolated type integrated circuit semiconductor device being configured by laminating and bonding an element integrated substrate, the element integrated substrate being configured by laying out the single crystal islands including the integrated circuit components in the isolation region, and an element support substrate having both a support function and a conductive path function for the element integrated substrate, the element integrated substrate being provided with predetermined single crystal islands from which the dielectric insulating isolation film at the bottom of the single crystal islands has been removed in order to integrate vertical semiconductor elements, and a first main electrode and a control electrode on the surface of the predetermined single crystal island are connected to each other by wiring via a surface insulating protective film on the semiconductor chip body. The vertical semiconductor element is characterized in that a main functional part of the vertical semiconductor element connected to an electrode is formed between the surface of the predetermined single crystal island and a buffer layer at the bottom of the island, a drain or collector of the vertical semiconductor element is connected to the buffer layer and formed exposed on the bonding surface of the element integrated substrate and bonded to the element support substrate, and the vertical semiconductor element is configured by connecting the drain or collector to a second main electrode on the back surface of the element support substrate via the element support substrate. The main functional part is a name that indicates the remaining structural factors excluding the drain or collector or short circuit part from the structural factors in the chip body that constitutes the element.

[0020] In order to solve the above problems and achieve the object of the present invention, a power integrated circuit semiconductor device according to the present invention comprises: In

[0019] , the vertical semiconductor element is a bipolar element, the first main electrode is formed on the surface of the specified single crystal island on which the main functional unit is formed, and the second main electrode is formed on the back surface of the element support substrate of the semiconductor chip body, a third main electrode is formed on the surface of the inclined channel stopper of the specified single crystal island on which the main functional unit is formed or on the surface of the isolation region adjacent thereto via the dielectric insulating isolation film, and a part of the isolation region is connected to the buffer layer at the bottom of the specified single crystal island and the collector, the drift layer of the main functional unit and the isolation region of the element integration substrate have the same polarity, but the element support substrate has the opposite polarity, and the second main electrode is electrically connected to the third main electrode, thereby forming an element between the first main electrode and the second main electrode and the third main electrode. In order to solve the above problems and achieve the object of the present invention, a power integrated circuit / semiconductor device according to the present invention comprises: In the method of

[0019] , the vertical semiconductor element is a unipolar element, the first main electrode is formed on the surface of the predetermined single crystal island on which the main functional unit is formed, the second main electrode is formed on the back surface of the element support substrate of the semiconductor chip body, a third main electrode is formed on a surface of the inclined channel stopper of the predetermined single crystal island on which the main functional unit is formed or on a surface of the isolation region adjacent thereto via the dielectric insulating isolation film, and a part of the isolation region is connected to the buffer layer at the bottom of the predetermined single crystal island and the drain, the drift layer of the main functional unit and the element support substrate have the same polarity, but the isolation region of the element integration substrate has an opposite polarity, and the second main electrode is electrically connected to the third main electrode, whereby the element between the first main electrode and the second main electrode and the third main electrode constitutes a vertical reverse conducting semiconductor element.

[0021] In order to solve the above-mentioned problems and achieve the object of the present invention, the power integrated circuit semiconductor device of the present invention is characterized in that the reverse conducting semiconductor element has a single buffer layer or a multiple buffer layer consisting of two or more layers.

[0022] In order to solve the above problems and achieve the object of the present invention, the power integrated circuit semiconductor device according to the present invention is characterized in that the semiconductor chip body has a structure in which the bonding surfaces of the element integrated substrate having a bonding surface with a mixture of polycrystalline and single-crystalline surfaces and the element support substrate having a bonding surface with only a single-crystalline surface or a bonding surface with only a polycrystalline surface are directly bonded together. In the following, in order to clarify the difference from the bonding structure in various conventional dielectric isolation type power integrated circuit semiconductor devices and to avoid confusion, the case in which the element integrated substrate has a bonding surface with a mixture of polycrystalline and single-crystalline surfaces and the element support substrate has a bonding surface with only a single-crystalline surface is referred to as Single and Poly mixed crystal surface & Single crystal surface Direct Bonding Structure, or SP&S-DBS for short. Also, the case in which the element integrated substrate is the same but the element support substrate has a bonding surface with only a polycrystalline surface is referred to as Single and Poly mixed crystal surface & Poly crystal surface Direct Bonding Structure, or SP&P-DBS for short.

[0023] In order to solve the above problems and achieve the object of the present invention, the power integrated circuit semiconductor device according to the present invention is characterized in that the semiconductor device is made of a SiC semiconductor. Also, in order to solve the above problems and achieve the object of the present invention, the power integrated circuit semiconductor device according to the present invention is characterized in that the surface of the single crystal island of the power integrated circuit semiconductor device made of a SiC semiconductor is configured using a C-plane, i.e., a (000-1) crystal plane, the side surface is configured using a {0-33-8} plane, and the bottom surface of the single crystal island has a single crystal island crystal plane structure configured using a Si-plane, i.e., a (0001) plane.

[0024] In order to solve the above problems and achieve the object of the present invention, a power integrated circuit semiconductor device according to the present invention comprises: In a dielectrically isolated integrated circuit semiconductor device, the semiconductor chip body is configured with single crystal islands laid out in an isolation region via a dielectric insulating isolation film, the side of the single crystal island has a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and integrated circuit components in the single crystal island are connected to integrated circuit components in other single crystal islands by wiring provided on a surface insulating protective film on the surface of the semiconductor chip body, the vertical semiconductor element has the surface carrier concentration reduced field relaxation region (SCaDFRR), and also has a structure (SP&S-DBS or SP&P-DBS) in which the element integrated substrate having a mixed attachment surface of polycrystalline and single crystal surfaces is bonded to the element support substrate having an attachment surface of only single crystal surfaces or only polycrystalline surfaces.

[0025] In order to solve the above problems and achieve the object of the present invention, a power integrated circuit / semiconductor device according to the present invention comprises: An inverter circuit is built in, and the inverter circuit The upper arm of each phase is configured as described in [Claim 1] to [Claim 7]. The vertical semiconductor element or the vertical reverse conducting semiconductor element is included. The lower arm is configured to include a lateral semiconductor element or a lateral reverse conducting semiconductor element. It is characterized by the fact that

[0026] The power integrated circuit semiconductor device according to the present invention, in the above-mentioned invention, is provided with a new surface electric field relaxation region (SCaDFRR) on the surface of the graded channel stopper layer under the wiring across the component element with a large power capacity, thereby achieving a high breakdown voltage. In addition, despite the thick element support substrate, the first main electrode is formed on the main surface and the second main electrode and the third main electrode are electrically connected to realize a reverse conducting semiconductor element with a vertical output structure between the first main electrode, the second main electrode, and the third main electrode. This makes it possible to significantly reduce the drift resistance compared to the case where an IGBT is configured with a lateral structure in a dielectric isolation island, thereby achieving a low on-resistance and a large current capacity. Therefore, these high breakdown voltages and large current capacities can achieve a large capacity of the power integrated circuit semiconductor device.

[0027] In order to realize high voltage resistance of power integrated circuit semiconductor devices, it is necessary to provide an electric field relaxation region to relax the surface peak electric field in order to suppress the surface dielectric breakdown of the semiconductor chip body under the jumper, and also to thicken the insulating protective film under the jumper. When the withstand voltage is high, the field area becomes quite large if only the electric field relaxation region is provided, so the insulating protective film is also made thick, but this thickness becomes very large. Although it varies depending on the electric field relaxation region to be provided and the composition of the insulating film, for example, it is estimated from prior art document 3 that uses an electric field relaxation region called FRR and a Si oxide film (hereinafter referred to as SiO2 film) that a thickness of 12 μm or more is required for a withstand voltage of 1.2 kV, making it difficult to form. In addition, a large step occurs when connecting the wiring on the thin insulating protective film of the element inside the insulating isolation island, and the wiring is broken at this step. To avoid this, the insulating protective film inside the element is made in a stepped shape, with each step usually being about 1 to 2 μm, but for example, in the case of a high voltage resistance where the insulating protective film thickness is 12 μm or more, the number of steps must be increased, which results in the size of most integrated circuit semiconductor device components becoming larger and the chip becoming bulky. For these reasons, there are no examples of integrated circuit semiconductor devices with a high voltage resistance of 650 V or more, which is a major obstacle to commercialization.

[0028] In the present invention, a novel surface carrier concentration reduction electric field relaxation region SCaDFRR is provided on the surface of the gradient channel stopper under the jumper to achieve high breakdown voltage for a component with a large power capacity. In the prior art document 3, the electric field relaxation region FRR is introduced on the drift region surface under the jumper to increase the carrier concentration on the drift region surface and achieve high breakdown voltage, but the entire surface of the high concentration gradient channel stopper is also made more highly concentrated. As a result, the electric field concentration at the drift region side end of the gradient channel stopper surface is higher, and the breakdown voltage, i.e., the voltage at which the maximum electric field of this electric field concentration part reaches the breakdown electric field strength of the semiconductor material, is limited to a low value. In the present invention, a novel SCaDFRR with a lower carrier concentration is provided on the drift region side surface of the gradient channel stopper under the jumper. As a result, the low concentration SCaDFRR region is depleted due to the potential difference with the jumper, and the position where the surface electric field is maximum moves to the vicinity of the boundary between the SCaDFRR and the gradient channel stopper surface that is not depleted. As a result, the electric field can be relaxed by the voltage share of the SCaDFRR, and the breakdown voltage can be increased. Therefore, it is preferable that the SCaDFRR is long as long as the surface of the inclined channel stopper maintains its function as a channel stopper. Since the SCaDFRR region is provided inside the inclined channel stopper, it has the characteristic that the element size does not increase. Since the SCaDFRR can provide a high withstand voltage, the thickness of the insulating protective film under the jumper can be reduced if the withstand voltage is to be maintained. In addition, the thickness of the insulating protective film can be reduced while providing a high withstand voltage within the range of the maximum electric field reduction effect of the SCaDFRR. In addition, as long as the FRR is provided adjacent to the inclined channel stopper under the jumper on the drift region side surface, the FRR can effectively exert the electric field relaxation effect, so it is also preferable to have the FRR and the SCaDFRR coexist.

[0029] As described in

[0027] above, in order to realize a high withstand voltage of a power integrated circuit semiconductor device, it is necessary to thicken the insulating protective film under the jumper wiring to reduce the electric field strength on the surface of the semiconductor element and make the maximum electric field strength equal to or less than the dielectric breakdown electric field strength of the semiconductor material. When the withstand voltage is high, the thickness of this insulating protective film becomes very large, so in order to avoid disconnection of the wiring, the insulating protective film is made step-like to reduce the step difference at each step, but as a result, the number of steps must be increased, and the size of most of the integrated circuit semiconductor device components becomes large, resulting in an enlarged chip, which is not practical. In order to solve this problem, in the present invention, a thick buried insulating film is provided under the surface of the chip body, the SCaDFRR is provided directly under it, and a separate insulating protective film is also provided on the surface of the chip body above this thick buried insulating film. For example, when the semiconductor material is Si and FRR is used and a SiO2 film is used as the insulating film, an insulating film thickness of 12 μm or more is required when the withstand voltage is 1.2 kV. However, if the insulating film thickness reduction effect of the above-mentioned SCaDFRR is estimated to be 2 μm and the thickness of the insulating protective film on the surface of the chip body is set to a realistic thickness of about 6 μm, this can be solved by making the thickness of the buried insulating film under the main surface about 4 μm or more.

[0030] In the present invention, the main functional part of the component element having a large power capacity is formed in the single crystal island from which the dielectric insulating isolation film at the bottom of the single crystal island has been removed, and the main functional part is connected to the conductive path of the element support substrate via the drain or collector to form a vertical semiconductor element. As a result, compared to the horizontal semiconductor element of the conventional dielectric isolation type power integrated circuit semiconductor device, the drain or collector is formed below the main functional part instead of on the element surface, so that the drift thickness can be made smaller, the drift resistance can be significantly reduced, and loss can be reduced, and the current capacity can be significantly increased without increasing the element area, resulting in a large power capacity.

[0031] In the present invention, a first main electrode is formed on the surface of the single crystal island on which the main functional part of the component element with large power capacity is formed, and a second main electrode is formed on the back surface of the semiconductor chip body, and a third main electrode is formed on the surface of the isolation region adjacent to the single crystal island on which the main functional part is formed and sandwiched by a dielectric insulating isolation film, and the second main electrode and the third main electrode are electrically connected, so that the element between the first main electrode and the second main electrode and the third main electrode can be easily realized as a vertical structure reverse conducting semiconductor element.

[0032] In the present invention, when the vertical semiconductor element of the power integrated circuit semiconductor device is a bipolar element, the drift layer and the isolation region of the element integration substrate are of the same polarity, and the element support substrate is of the opposite polarity, so that a reverse conducting vertical bipolar semiconductor element such as a reverse conducting vertical IGBT can be easily provided. For example, in the case of this bipolar element, the drift layer and the isolation region of the element integration substrate are of the same n-type, but the element support substrate is of the opposite polarity p-type. As a result, a vertical IGBT can be formed between the first main electrode and the second main electrode, a short circuit can be formed between the first main electrode and the third main electrode, and the second main electrode and the third main electrode are electrically connected, so that a vertical reverse conducting IGBT can be realized between the first main electrode and the second main electrode and the third main electrode. As a result, a large current capacity and low loss can be enjoyed due to the small on-resistance of the vertical element, and low loss can also be enjoyed due to the reduced turn-off time of the reverse conducting IGBT. In addition, when reverse bias is applied, the first main electrode and the third main electrode can be operated as a FWD consisting of a p-body junction, and there is no need to integrate a separate FWD, which allows for significant chip miniaturization. In the structure of Prior Art Example 3, it was difficult to provide an n+ short circuit because the collector electrode corresponding to the second main electrode was connected via a thick p-collector layer, but in the present invention, by configuring the element support substrate and the element integration substrate with different polarities, it is easy to provide a vertical IGBT and a short circuit section independently, and as a result, it is easy to provide a vertical reverse conducting IGBT structure. As a result, it is possible to enjoy low loss and large current capacity due to the vertical structure, and further low loss due to a significant reduction in switching loss due to the shortened turn-off time of the reverse conducting semiconductor element.

[0033] In the present invention, when the vertical semiconductor element of the power integrated circuit semiconductor device is a unipolar element, the drift layer and the element support substrate are made to have the same polarity and the isolation region of the element integration substrate is made to have the opposite polarity, and a reverse conducting vertical unipolar semiconductor element can be easily provided. For example, when the vertical semiconductor element is a unipolar element such as a MOSFET, the drift layer and the element support substrate are made to have the same n-type polarity and the isolation region of the element integration substrate is made to have the opposite polarity of p-type. As a result, a vertical MOSFET can be formed between the first main electrode and the second main electrode, and an IGBT can be formed between the first main electrode and the third main electrode. Since the second main electrode and the third main electrode are electrically connected, the first main electrode and the second main electrode and the third main electrode function as a reverse conducting IGBT when forward biased. Since no pn junction is interposed in the current path of the vertical MOSFET, a large current capacity and low loss due to the small on-resistance of the vertical structure can be enjoyed at a low applied voltage. On the other hand, at an applied voltage equal to or higher than the built-in voltage, the IGBT can also be operated in parallel. As a result, the low loss due to the IGBT's conductivity modulation and the small temperature dependency of the on-resistance are effective, making it possible to process excessive current, especially at high temperatures. At this time, part of the vertical MOSFET functions as an n+ short circuit, so the IGBT functions as a reverse conducting IGBT, and the turn-off time is shortened, resulting in a significant reduction in switching loss and low loss. In addition, when reverse biased, the first main electrode and the second main electrode can be operated as a FWD consisting of a p-body junction, which eliminates the need for a separate FWD and allows for a significant reduction in chip size.

[0034] In the present invention, the reverse conducting semiconductor element of the power integrated circuit semiconductor device has a buffer layer of one layer configuration, or a multiple buffer layer of two or more layers. In the case of a single layer configuration, the thickness of the buffer layer and the impurity concentration are appropriately reduced to maximize the lateral resistance of the buffer layer above it even with a specified small p collector layer width, so that even with a small Isb, Vsb is equal to or less than the built-in voltage Vbi of the p+ collector junction, eliminating the snapback phenomenon. As a result, the chip area of ​​the power integrated circuit semiconductor device is reduced with a reverse conducting semiconductor element of a small p+ collector width, and the snapback phenomenon is suppressed or eliminated, achieving high reliability. In addition, in the case of a multiple buffer layer of two or more layers, only the final layer is set to remain not entirely depleted by the built-in voltage Vbi of the p+ collector junction, and the other layers are set to be entirely depleted. As a result, the resistance of the buffer layer through which Isb flows can be further increased, the p+ collector width can be further reduced, the area of ​​the reverse conducting semiconductor element and, ultimately, the chip area of ​​the power integrated circuit semiconductor device can be further reduced, and the snapback phenomenon can be further suppressed or eliminated, achieving high reliability.

[0035] In the present invention, for an integrated circuit semiconductor device consisting of only lateral semiconductor elements, a wafer for forming semiconductor chips is formed by bonding a wafer for an element integrated substrate having a polycrystalline bonding surface and a wafer for an element support substrate having a single crystal bonding surface. Pre-treatment for bonding the wafer for an element integrated substrate is, for example, 70° C. NH 4 OH and H 2 O 2 The wafer is treated with the solution, rinsed with ultrapure water, and then spin-dried. A single crystal Si wafer for an element support substrate is then set on the wafer for an element integrated substrate, and they are bonded together by high-temperature heat treatment in an oxidizing atmosphere. Compared to the conventional epitaxial growth in which both wafers are integrated, the high-temperature, long-term epitaxial growth process for forming the support substrate and the post-growth grinding and polishing process for flattening large curvatures can be omitted, resulting in a significant simplification of the power integrated circuit semiconductor device manufacturing process and a considerable reduction in cost. On the other hand, for the formation of an integrated circuit semiconductor device including a vertical semiconductor element, a wafer for an element integrated substrate having a bonding surface in which the single crystal surface of the region for forming the vertical semiconductor element and the polycrystalline surface formed on the insulating oxide film are mixed by removing the insulating oxide film, and a wafer for an element support substrate having a bonding surface consisting of only a single crystal surface is bonded to realize a wafer with a new bonding structure for forming a semiconductor chip (SP&S-DBS described in

[0022] ). The bonding strength of the bonding surface between single crystal surfaces is higher than that of the bonding surface between a single crystal surface and a polycrystalline surface, but bonding between single crystal surfaces tends to cause voids to occur at the bonding boundary, reducing the bonding strength, so this problem is overcome by devising the bonding temperature, bonding pressure, bonding atmosphere gas, and pretreatment process and materials. For example, as a pretreatment process, a wafer for an element integration substrate having a bonding surface where polished single crystal surfaces and polycrystalline surfaces are mixed, and a wafer for an element support substrate having a bonding surface where only a single crystal surface is bonded are heat-treated in a reducing atmosphere such as hydrogen annealing before bonding, and hydrogen atoms are bonded to the dangling ring bonds of Si atoms on the bonding surface. Next, the bonding process of both wafers is performed in an oxidizing atmosphere, and these hydrogen atoms are bonded to oxygen to form H 2 The bonding strength is increased by this bonding, so the bonding temperature and bonding pressure applied to the wafers are made higher than those in the bonding of the polycrystalline bonding surface and the single crystal bonding surface described above at the beginning of this paragraph. As a result, compared to the case where only the above-mentioned lateral semiconductor elements are used, there is a bonding portion between single crystal faces with high bonding strength, and since the bonding strength of this portion is improved, the bonding strength of the entire bonded wafer is improved. This further reduces damage caused by partial peeling in the subsequent element manufacturing process, and is expected to improve the yield of good products.

[0036] The power integrated circuit semiconductor device according to the present invention is the above-mentioned invention, The integrated circuit semiconductor device is made of a wide gap semiconductor such as a SiC semiconductor. As a result, it has become possible to achieve a higher breakdown voltage, lower loss, smaller chip size, and higher heat resistance that far surpasses that of silicon semiconductors. In addition, a semiconductor device having high performance such as a dielectric isolation type power integrated circuit semiconductor device can be realized. Compared with pn-isolated power integrated circuit semiconductor devices, the leakage current is extremely small even at high temperatures. Therefore, it is suitable for achieving high voltage and high heat resistance, and since the width of the isolation region between elements can be significantly narrower than element isolation using pn junctions, it is also suitable for achieving small chip size and low loss. Therefore, the SiC dielectric isolation type power integrated circuit semiconductor device, which is configured by combining both, can be said to be an ideal power semiconductor device. In the case of an integrated circuit semiconductor device having a SP&S-DBS wafer configuration made of a SiC semiconductor, for example, in order to increase the bonding strength, as described in

[0035] , A wafer for an element integration substrate having a bonding surface in which a single crystal surface and a polycrystalline surface are mixed, which have been polished as a pretreatment process, and a wafer for an element support substrate having a bonding surface only of a single crystal surface. Before bonding, both wafers are heat-treated in a reducing atmosphere such as hydrogen annealing to bond hydrogen atoms to the dangling bonds of silicon atoms and carbon atoms (hereafter referred to as C atoms) on the bonding surface. The subsequent bonding process is carried out in an oxidizing atmosphere to bond these hydrogen atoms with oxygen to form H 2 The Si atoms are removed as O and bonded to the C atoms. In order to increase the bonding strength due to this bond, the bonding temperature and the bonding pressure applied to the wafer are set higher than those in the case of Si described in

[0035] . For the final polishing of both wafers prior to this pre-processing, it is effective to apply a method such as the Catalyst Surface Reference Etching method (commonly known as the CARE method), which has ultra-high precision polishing accuracy at the atomic level. The heat treatment in a reducing atmosphere before pasting is carried out using NO or N 2 Nitriding treatment in an O atmosphere is also acceptable, and the subsequent bonding process is similarly performed in an oxidizing atmosphere, whereby the nitrogen atoms of the dangling ring bonds are combined with oxygen and removed, and the Si atoms and C atoms on the bonding surfaces of both wafers are combined to complete the bonding.

[0037] In the present invention, in order to realize this SiC semiconductor dielectric isolation type integrated circuit semiconductor device, a new single crystal island crystal plane structure is used in which each surface of the single crystal island is composed of a crystal plane having a crystal orientation unique to the present invention. That is, a new single crystal island crystal plane structure is used in which an n single crystal island is formed using 4HSIC, the surface of the single crystal island is composed of a C-plane, i.e., a (000-1) crystal plane, the side is composed of a {0-33-8} plane equivalent to a (0-33-8) plane, and the bottom surface of the single crystal island is composed of a Si-plane, i.e., a (0001) plane. As a result, the following advantages are obtained. (1) When the catalyst surface reference etching method (CARE method), which is an excellent flattening technology, is used for the Si-plane, it is possible to obtain flatness at the atomic level superior to that of the C-plane. Therefore, by making the bottom of the single crystal island a Si plane, a better quality bonding surface and a stronger bonding surface can be obtained during bonding, which is extremely suitable for the vertical element formed by bonding the single crystal parts in the present invention. (2) The side surface is formed of a {0-33-8} plane equivalent to the (0-33-8) plane, and has an inclination angle of 54.7 degrees or (180 degrees - 54.7 degrees) with respect to the C plane on the surface. This crystal plane is suitable because it has a fast oxidation rate and is easy to form a thick insulating isolation oxide film for high voltage resistance. Furthermore, even if there are micro defects such as micropipes in the drift region that cause poor voltage resistance or increased leakage current, this plane can be almost completely blocked during formation by CVD methods such as epitaxial, and is extremely suitable as a crystal plane for forming a high-quality, thin channel stopper. (3) The C plane can obtain the best MOS interface and fabricate a MOSFET with high channel mobility. Furthermore, the C plane is the crystal plane with the fastest oxidation rate, and is extremely suitable for high-voltage integrated circuit semiconductor devices that require a thick, high-quality insulating protection film under the jumper wiring. In addition, the dielectric breakdown strength of SiC semiconductors is about one order of magnitude higher than that of Si semiconductors, so as explained in

[0027] and

[0029] , the insulating protection film under the jumper wiring can be made thin even in the case of high voltage resistance. As a result, it becomes easier to form the insulating protective film, and the number of steps required to avoid disconnection of wiring can be reduced, preventing the device area from becoming larger and enabling the chip to be made smaller. On the other hand, in the case of SiC semiconductors, bipolar devices such as IGBTs and FWDs that are composed of p-body junctions have a unique on-voltage degradation phenomenon, which causes a problem of significant loss of reliability.However, the reverse conducting structure of the present invention described above allows only majority carriers to flow when the element is started up or operating, and the MaCH-TEDREC method (an operating method invented by the present inventor and disclosed in Patent No. 6232687) can be applied, in which the junction temperature is raised to a temperature above the on-voltage degradation phenomenon suppression temperature to suppress or eliminate on-voltage degradation. This makes it possible to eliminate or significantly suppress the on-voltage degradation phenomenon, and achieve high reliability.

[0038] In the case where the power integrated circuit semiconductor device according to the present invention has an inverter circuit built therein, the upper arm of the inverter is configured to include the vertical semiconductor element. As a result, for example, in the case of an inverter having one or more phase arms, the upper arm of each phase has the collector or drain of the reverse conducting semiconductor element of each phase connected in parallel to the high potential wiring of the power supply, so the element structure of the present invention in which a plurality of reverse conducting semiconductor elements can be connected in parallel to the second main electrode (collector electrode or drain electrode) via the element support substrate is preferable. On the other hand, the lower arm of each phase has the first main electrode (emitter electrode or source electrode) connected in parallel to the low and high potential wiring of the power supply, but since the potential of the second main electrode (collector electrode or drain electrode) changes during the operation of the inverter, a reverse conducting semiconductor element having a structure in which the second main electrode (collector electrode or drain electrode) is independent from the other phases is preferable. For this reason, the structures of the seventh to ninth embodiments are set as the preferable arm structure for one phase. Effect of the Invention

[0039] As described above, according to the present invention, in a dielectrically isolated power integrated circuit semiconductor device, a vertical structure of the output reverse conducting element can be realized, and a large current capacity and low loss can be achieved, thereby enabling a large capacity and low loss of the power integrated circuit semiconductor device. Furthermore, by optimizing and multiplexing the buffer layer, the snapback phenomenon can be eliminated in a small occupied area, and high reliability can be achieved. In addition, a wafer for a dielectrically isolated integrated circuit semiconductor device using the novel wafer bonding structure SP&S-DBS can be used to significantly reduce costs, and the wafer bonding strength can be improved, making subsequent element manufacturing more economical. Furthermore, by using a SiC semiconductor and applying a novel SiC single crystal island crystal face structure in addition to SCaDFRR and SP&S-DBS, a large capacity and low loss can be achieved, and on-voltage degradation can be eliminated, thereby improving reliability. As a result, the application of the power integrated circuit semiconductor device of the present invention can greatly contribute to the miniaturization, weight reduction, low loss, high reliability, and economical improvement of various power conversion circuit-equipped devices such as home appliances, offices, vehicles, and industrial devices. [Brief description of the drawings]

[0040] [Figure 1] Schematic cross-sectional view of a Si lateral reverse conducting IGBT according to a first embodiment. [Diagram 2] Schematic cross-sectional view of a Si reverse conducting IGBT according to a second embodiment. [Diagram 3] Manufacturing process flow of Si reverse conducting IGBT according to the second embodiment [Figure 4] Schematic cross-sectional view of a SiC reverse conducting MOSFET according to a third embodiment. [Diagram 5] Schematic cross-sectional view of a SiC reverse conducting MOSFET according to a fourth embodiment. [Figure 6] Schematic cross-sectional view of a SiC reverse conducting IGBT according to a fifth embodiment. [Figure 7] Output element configuration for one phase of the Si single-phase inverter integrated circuit semiconductor device according to the seventh embodiment [Figure 8] Configuration of output elements for one phase of a SiC three-phase inverter integrated circuit semiconductor device according to the eighth embodiment [Figure 9]Schematic cross-sectional view of a SiC reverse conducting MOSFET according to a sixth embodiment. [Figure 10] Schematic cross-sectional view of a high-voltage Si reverse conducting IGBT according to prior art example 1 [Figure 11] Schematic cross-sectional view of a high-voltage Si reverse conducting IGBT according to prior art example 2 [Figure 12] Schematic cross-sectional view of a high-voltage SiIGBT according to prior art example 3 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] A preferred embodiment of the dielectric isolation type power integrated circuit semiconductor device according to the present invention will be described in detail below with reference to the attached drawings. In this specification and the attached drawings, in layers and regions with n or p semiconductor polarity, electrons or holes, respectively, are majority carriers. In the drawings, the numbers and arrows indicating layers and regions are, in principle, only one representative of each is shown for the same layer or region, and the others are omitted. In addition, each figure is a schematic cross-sectional view to avoid complexity and to better explain the invention, and each structural factor has no correlation such as size relationship or proportionality within each figure or between each figure. However, the numerical values ​​of each structural factor in the description are described as specifically as possible, so please understand them there. In addition, in order to avoid complexity in the figures, the number of cells of the output element is limited to 3 to 4, and the number of multiple stages of the surface protection film is only drawn diagrammatically in one stage. Furthermore, peripheral circuit components other than the output element are drawn diagrammatically in about two stages. In the power integrated circuit semiconductor device, elements constituting the gate drive circuit of the known output element, various detection circuits for voltage, current, temperature, etc., and various protection circuits are formed on each insulating isolation island as a single element, multiple elements, or circuit units according to the specifications of the power integrated circuit semiconductor device. In this specification, the circuits and elements other than these output elements are collectively defined as peripheral circuits and peripheral circuit elements, and are described by these names. In the following embodiments, the description will focus on the output elements in particular in the dielectric isolation type power integrated circuit semiconductor device chip, which is essential for understanding the present invention, and descriptions of the peripheral circuits and packages will be omitted.

[0042] (Embodiment 1) FIG. 1 shows a main part of a power integrated circuit semiconductor device chip 100 according to a first embodiment. 1 is a schematic cross-sectional view of an output element according to a first embodiment of the present invention. The device chip 100 is a device manufactured using a Si semiconductor, for example, with a design voltage of 1.2 kV / 3 A class. This is a dielectric isolation type power integrated circuit semiconductor device chip, and in FIG. The output element is a reverse conducting IGBT with a trench gate structure and a striped cell type. The stripe-shaped single crystal island has 25 stripe-shaped cells, but it is complicated. To avoid cluttering, only three cells are shown in the figure. The width of the output element single crystal island is about 520 μm. The length of the single crystal island is 5 mm. Compared to the pn isolation type, the dielectric isolation type has extremely low leakage current even at high temperatures and has excellent insulation between elements. The edge isolation region is significantly smaller, making it easier to achieve high voltage resistance and reduce chip size. It is very suitable for power integrated circuit semiconductor devices. The chip body of the first embodiment is composed of an element integrated substrate 101 and an element support substrate 102. The two substrates are bonded together using wafer bonding technology. The pasting technology was developed by the inventors and is called "NEW DIELECTRIC ISOLATION FOR HIGH VOLTAGE ICS BY SINGLE SILICON POLY SILICON DIRECT BOND ING (SPSDB) TECHNIQUE" in Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, May 1992, p.316- 321". The bonding structure using this wafer bonding technology is named

[0022] If we follow the method described above, we can call this structure P&S-DBS, and it can be formed, for example, by using the pasting method and pretreatment described in the top 1-10 lines of

[0035] . By applying this structure, Thick element support substrate in conventional dielectrically isolated power multiplier circuit semiconductor device fabrication process This eliminates the need for a long epitaxial growth process at temperatures of 1200° C. or higher. The power integrated circuit semiconductor device manufacturing process can be greatly simplified and the manufacturing equipment can be simplified. The advantages are that it is possible to greatly simplify the system and simplify maintenance, and to greatly reduce costs. Most of the various bonding structures of dielectric isolation type power integrated circuit semiconductor devices, including SOI, disclosed so far are P&S-DBS.

[0043] First, the configuration and features of the first embodiment of Fig. 1 will be described. To briefly describe the configuration of a conventional dielectrically isolated integrated circuit semiconductor device, the Si semiconductor chip body is configured by laying single crystal islands in an isolation region 117 via a dielectric insulating isolation film 106, and the side of the single crystal island is inclined at a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and therefore the channel stopper 125 extending along the dielectric insulating isolation film 106 is inclined with respect to the front and back surfaces, and is hereinafter referred to as an inclined channel stopper. In addition, the integrated circuit components in the single crystal island are connected to the integrated circuit components in other single crystal islands by wiring via a surface insulating protective film provided on the semiconductor chip body, and as described in paragraph

[0015] , the wiring portion 116 that crosses over the isolation region, the dielectric insulating isolation film, and the inclined channel stopper exposed on the surface of the semiconductor chip body is defined as a crossover wiring. In this embodiment, the surface of the Si semiconductor chip body is composed of a (001) plane, the side surface is composed of a {111} plane, and the specified angle determined by the crystal orientation with respect to the surface is approximately 54.7 degrees or (180 degrees - 54.7 degrees).

[0044] The p-collector 104 of the reverse conducting IGBT in the single crystal island in the device integrated substrate 101 is surrounded by an n-buffer layer 107 and connected to the second main electrode (collector electrode) 103 via a short circuit part 105 located away from the n-emitter 110, forming a reverse conducting structure. The n-buffer layer 107 has a double buffer layer configuration and has a higher lateral resistance than a single buffer layer configuration, so that even if the extending p-collector width is short, a built-in voltage Vbi of about 0.7V can be achieved with a small Isb and the IGBT can be turned on, so that the snapback phenomenon can be significantly suppressed. In other words, the snapback phenomenon can be significantly suppressed with a small occupied area. The basic concept of the double buffer layer is disclosed in Patent No. 6383971 by the present inventor. In addition, the p-body 109 connected to the first main electrode (emitter electrode) 120 and the drift layer 108 form an FWD and are connected to the second main electrode (collector electrode) 103 via the n-short circuit part 105. As a result, there is no need to separately integrate FWD within the single crystal island, allowing for a significant reduction in the device area.

[0045] The dielectric isolation type power integrated circuit semiconductor device chip in this embodiment, which aims to achieve a significantly higher breakdown voltage, is different in configuration from the conventional dielectric isolation type integrated circuit semiconductor device chip in the following two points. The first difference is that in addition to the conventional high breakdown voltage technology for field relaxation such as the field plate 123 for field relaxation at the junction end and the surface field relaxation layer FRR for field relaxation at the inclined channel stopper portion, a new surface carrier density decrease field relaxation region (SCaDFRR for short) is provided on the surface of the inclined channel stopper 125 under the jumper. In the 600V chip of the prior art 3, the surface insulating protective film 118 under the jumper is an insulating film made of SiO2 with a thickness of about 5.4 μm. In the case of this embodiment, a breakdown voltage of 1.2 kV or more is required, so the surface insulating protective film 118 made of SiO2 needs to be about 12 μm or more thick, which makes it difficult to form. In this embodiment, therefore, the SCaDFRR 121 is newly provided on the surface of the inclined channel stopper 125 to improve the breakdown voltage and to reduce the thickness of the insulating film. The principle is described in

[0028] , but by providing the SCaDFRR, a film thickness reduction of about 2 μm or more is expected, although this varies depending on the length, the film quality of the insulating film, the degree of coexistence with the FRR, etc., and when applied to the above-mentioned prior art 3, the film thickness can be reduced to about 10 μm.

[0046] The second difference is that a buried insulating film 140 is used in the chip body under the jumper wiring. When a voltage corresponding to the withstand voltage is applied, the surface electric field concentration under this jumper wiring 116 causes dielectric breakdown on the Si surface, so it is necessary to set the surface insulating protective film thickness to alleviate this surface electric field concentration and prevent dielectric breakdown. When the withstand voltage is high, this thickness becomes very large, and for example, in the case of a withstand voltage of 1.2 kV, as described above, an insulating film thickness of 12 μm or more is required, which makes it difficult to form. In addition, a large step occurs between the wiring 119 on the thin insulating film until it is connected to the element inside the insulating isolation island, and the wiring breaks at the step part. To avoid this, the insulating film under the wiring inside the element is made step-like, and the step at each step is usually about 1 to 2 μm, but in the case of a high withstand voltage, the number of steps must be increased, and the step part between the steps becomes large, resulting in the size of most integrated circuit semiconductor device components becoming larger and the chip becoming bloated. For this reason, there are no examples of integrated circuit semiconductor devices with high withstand voltages of 650 V or more, which is a major obstacle to commercialization.

[0047] In this embodiment, a thick buried insulating film 140 is provided by burying a part of the thick surface insulating protective film 118 under the jumper wiring that was previously formed on the surface of the chip body under the transition wiring under the surface of the chip body, and the SCaDFRR 121 is provided under it, and another surface insulating protective film 118 with a thickness minus the buried insulating film thickness is provided on the surface of the chip body. For example, since the insulating film thickness reduction effect of the above-mentioned SCaDFRR is expected to be about 2 μm, the thickness of the buried insulating film under the main surface is set to about 4 μm in order to make the thickness of the surface insulating protective film on the surface of the chip body a realistic thickness of about 6 μm. This makes it possible to reduce the number of steps of the insulating protective film on the surface of the chip body of the power integrated circuit semiconductor device, and to achieve a reduction in the chip area.

[0048] The main structural specifications are, for example, the drift layer with an impurity concentration of 1x10 14 cm -3 The thickness may be 140 μm. The n+ emitter region has an impurity concentration and a thickness of 5×10 19 cm -3 1.5μm, p-body region is 3x10 17 cm-3 The thickness from the surface is 4 μm, and the n-buffer layer is 2 x 10 16 cm -3 4μm, p+ collector area is 1x10 19 cm -3 2 μm. The distance from the p-body region to the SiO2 dielectric isolation film may be 170 μm and the thickness of the graded channel stopper may be 5 μm. The thickness of the gate oxide may be 1300 Å and the thickness of the SiO2 dielectric isolation film may be 5 μm. The thickness of the chip body may be about 300 μm.

[0049] Next, the characteristics of the power integrated circuit semiconductor device of the first embodiment will be described. The power integrated circuit semiconductor element chip 100 was mounted in a high-voltage package for measuring characteristics and subjected to an operation test. When a forward voltage was applied between the emitter electrode 120 and the collector electrode 103 with no gate voltage applied, a leakage current flows, but the device exhibits good forward blocking characteristics, with a breakdown voltage at room temperature, i.e., a voltage indicating avalanche breakdown, of approximately 1.42 kV, and a leakage current before avalanche breakdown of 1×10 at room temperature. -6 A / cm 2 The following is 8x10 even at high temperatures of 250℃ -6 A / cm 2 The following is good:

[0050] In addition, when a gate voltage is applied in the forward direction and then increased, the reverse conducting IGBT turns on. Although a snapback phenomenon was observed, Vsb is low at about 1.6 V, which is a level that does not pose a problem in practical use. In addition, when the gate voltage is increased to 100 A / cm 2 The on-state voltage at room temperature when a current density of 100 A / cm is applied is low at about 2.5 V. 2 The turn-off time when current is applied is approximately 1.2μs, which is half that of a Si-IGBT of the same voltage class. In this way, the reverse conducting IGBT function reduces the turn-off time and speeds it up, resulting in a significant reduction in switching loss and low loss. Furthermore, the 100A / cm of FWD 2 When a current density of 1.5 V is applied at room temperature, the on-state voltage is low and favorable.

[0051] As described above, according to this embodiment, a high-voltage reverse conducting IGBT can be integrated as an output element of a Si power integrated circuit semiconductor device chip by using the SCaDFRR and the buried insulating film, and the high voltage resistance, reduction in chip occupation area, and low loss can be achieved, and a large capacity of the power integrated circuit semiconductor device can be achieved. Furthermore, the snapback phenomenon can be significantly suppressed to a level that does not pose a problem in practical use, and high reliability can be achieved. In addition, during the return current of the inverter, the built-in diode consisting of the p-body and n-drift layer can be used as a FWD diode, and there is no need to provide a new diode separately, and the semiconductor chip size of the power integrated circuit semiconductor device can be significantly reduced, resulting in cost reduction.

[0052] (Embodiment 2) Fig. 2 is a cross-sectional view showing a schematic diagram of an output element which is a main part of a Si power integrated circuit semiconductor device chip 200 according to the second embodiment. The semiconductor device chip 200 according to the second embodiment shown in Fig. 2 is a dielectrically isolated type power integrated circuit semiconductor device chip having a designed voltage resistance of, for example, 1.2 kV-60 A class, which is manufactured using a Si semiconductor, and is configured by bonding an element integrated substrate 201 and an element support substrate 202 together using a new bonding structure (SP&S-DBS) according to the present invention. This configuration can be formed, for example, by using the attachment method and pretreatment described in lines 19 to 26 at the top of

[0035] . The output element is a vertical reverse conducting IGBT with a trench gate structure, employing a novel reverse conducting IGBT structure according to the present invention, and is integrated within a dielectrically insulated isolated single crystal island and adjacent isolation region 217 of element integration substrate 201. The output element is stripe shaped, with the stripe shaped single crystal island having a width of approximately 6.5 mm and a length of 5 mm. Five hundred stripe shaped cells are formed in the stripe shaped single crystal island, but to avoid complication, only four cells are shown in the figure. As described above, compared with the pn isolation type, the dielectric isolation type has an extremely small leakage current even at high temperatures and requires a significantly smaller isolation region, making it easy to achieve high voltage resistance and reduce chip size, and is therefore suitable for high voltage power integrated circuit semiconductor devices.

[0053] First, the configuration and features of the first embodiment of FIG. 2 will be specifically described. In the second embodiment, the main functional part of the reverse conducting IGBT 200 of the output element is mostly formed in the dielectric isolation island, but since the insulating film 206 at the bottom of the dielectric isolation island is removed, it is connected to the p+ element support substrate 202 via the p+ collector 204, and this p+ element support substrate 202 is connected to the collector electrode 203, which is the second main electrode. Therefore, the element part between the emitter electrode 220, which is the first main electrode, and the collector electrode 203, which is the second main electrode, can function as a vertical Si-IGBT. On the other hand, the element part between the first main electrode 220 and the third main electrode 215 is connected to the n+ region (n+ short circuit part and drain of MOSFET) 205 via the part where the insulating film at the bottom of the dielectric isolation island has been removed, and is further connected to the third main electrode 215 via the n isolation region 217. Therefore, the element between the first main electrode 220 and the third main electrode 215 can function as a Si-MOSFET. Moreover, the third main electrode 215 is electrically connected to the metal part of the package to which the second main electrode 203 is die-bonded by wire bonding outside the chip, so the second main electrode 203 and the third main electrode 215 are electrically connected. Therefore, the elements between the first main electrode 220 and the second main electrode 203 and the third main electrode 215 function as a reverse conducting IGBT as a whole. Also, by adjusting the width of the n+ region 205 and the width of the p region 204, it is possible to make the operation of the MOSFET the main operation when the width of the n+ region 205 is large, and the operation of the IGBT the main operation when the width of the p+ region 205 is large. In the case of this embodiment, in order to make the operation of the IGBT the main operation, the ratio of the width of the p+ region 204 to the width of the n+ region 205 may be set to about 90:10, and the p+ region 204 may be made considerably large. On the other hand, the n+ region 205 functions as a short circuit part of the p+ collector 204, so that the discharge of the remaining carriers in the drift layer 208 can be promoted quickly at the time of turn-off, and as a result, the turn-off time is shortened and the turn-off loss is reduced, so that the loss of the power integrated circuit semiconductor device chip can be reduced. In addition, since the width of the p+ collector 204 becomes large, multiple n+ regions 205 are provided in the p+ collector 204 for each predetermined number of cells to efficiently and quickly discharge the remaining carriers. Only one n+ region 205 is shown in Fig. 2 for illustrative purposes.The spacing between the n+ regions 205 is determined by the conditions for suppressing the snapback phenomenon. The n+ regions 205 provided within the p+ collector 204 divide the p+ collector 204 at a specified location at the back of the page in the figure, connecting the n+ regions 205 on the left and right of the p+ collector 204 and the internal n+ regions to each other, thereby reducing resistance and quickly discharging remaining carriers.

[0054] In addition, when a voltage corresponding to the breakdown voltage is applied between the first main electrode and the second main electrode, electric field concentration occurs at the high-voltage junction end inside the element, but this is suppressed by a known termination technology such as the field plate 223 in the figure, and the channel generated on the chip surface is blocked by the inclined channel stopper technology. Furthermore, to prevent gate insulation breakdown due to electric field concentration at the bottom of the trench gate, known technologies such as thickening the oxide film 212 at the bottom of the gate and installing a p-well for covering the bottom of the gate (not shown) are applied. When appropriate design is performed using these technologies, the main factor that determines the breakdown voltage is the electric field concentration that occurs under the wiring, and in the case of this element structure, it is the surface electric field concentration at the inclined channel part 225 under the jumper wiring 216. This surface electric field concentration causes insulation breakdown on the Si surface at a voltage lower than the breakdown voltage, so in order to prevent this insulation breakdown, it is necessary to alleviate the surface electric field concentration and make the insulating protective film thicker. If the breakdown voltage is high, this thickness becomes very large. For example, in the case of a breakdown voltage of 1.2 kV, an insulating protective film thickness of 12 μm or more is required, which makes it difficult to form. Furthermore, a large step occurs between the emitter 210 inside the insulating isolation island and the wiring 219 on the thin insulating protective film up to the connection, causing the wiring to break at the step. To avoid this, the insulating protective film under the wiring inside the element is made step-like, with the step at each step usually being about 1 to 2 μm, but in the case of high voltage resistance, the number of steps must be increased, and the stepping parts between the steps become more numerous, resulting in the size of most integrated circuit semiconductor device components becoming larger and the chip becoming bloated. For these reasons, there are no examples of integrated circuit semiconductor devices with high voltage resistance of 650 V or more, which is a major obstacle to commercialization.

[0055] In this embodiment, a significant portion of the thick insulating protective film 218 under the jumper wiring, which was conventionally formed on the chip surface, is formed as a buried insulating film 240 under the surface of the chip body, thereby reducing the thickness of the surface insulating protective film 218 formed on the chip surface and reducing the step and the number of steps. In addition, the new electric field relaxation region SCaDFRR221 described above in the first embodiment is formed under the buried insulating film 240, which allows the insulation film pressure to be reduced by about 2 μm or more. As a result, for example, the surface oxide film 218, which requires 12 μm or more to achieve a breakdown voltage of 1.2 kV, can be reduced to about 6 μm, and the buried insulating film 240 under the surface can be reduced to about 4 μm, thereby achieving both a high breakdown voltage of the power integrated circuit semiconductor device chip and a reduction in the chip area by reducing the number of steps. In addition, when this chip is used in an inverter or the like, the pn junction diode composed of the p body 209 and the n drift layer 208 can be used as a FWD diode during the return current of the inverter. That is, the return current flows through the route of the first electrode 220 → p body 209 → n drift 208 → n+ short circuit portion 205 → isolation region 217 → third electrode 215, and functions as an FWD. As a result, it is not necessary to provide a new diode separately as the FWD. Since the FWD requires a current capacity almost equal to that of the IGBT, the semiconductor chip size of the power integrated circuit device can be reduced to nearly half, which allows the power integrated circuit device to be miniaturized and reduced in cost.

[0056] As for the snapback phenomenon associated with reverse conducting IGBTs, the width of the single crystal island for reverse conducting IGBTs is sufficiently wide as described in

[0052] , so that even a single buffer layer can increase the lateral resistance, and a small snapback current Isb can reduce the snapback voltage Vsb to the built-in voltage Vbi of Si or less, thereby eliminating the snapback phenomenon, and therefore this is fully applicable. However, since the p+ collector 204 to which the buffer layer extends becomes large, the gap between the short circuits increases, and the discharge speed of the remaining carriers at the time of turn-off may be impaired. In this case, the application of a double buffer layer is preferable. By using a double buffer layer, the lateral resistance of the current path of the non-depleted snapback current Isb in the buffer layer on the side in contact with the drift 208 can be increased, so that the p+ collector width that can eliminate the snapback phenomenon can be reduced. In other words, the gap between the short circuits can be reduced, so the discharge speed of the remaining carriers at the time of turn-off can be increased, and the original switching speed of the reverse conducting IGBT can be improved to more effectively achieve low loss, and high reliability can be achieved by eliminating the snapback phenomenon.

[0057] Next, the manufacturing process flow of the second embodiment will be briefly described with reference to FIG. 3. It should be noted in advance that the right side of [5] and [6] in FIG. 3 is slightly expanded compared to the previous drawings [4] for convenience of drawing. First, a mask for forming a separation groove is formed on the n-type single crystal main substrate 230, and the n-type single crystal main substrate 230 is selectively etched with high-temperature molten KOH liquid until the separation groove reaches a predetermined depth. In this etching, the mask width of the third main electrode 215 formation portion is made wider than the mask width of the other separation V-groove formation portions. The separation groove may be 160 μm deep. When the etching depth of the V-groove portion reaches 160 μm, the wide third main electrode 215 formation portion is automatically formed together with the other V-groove portions. Next, the n-type gradient channel stopper 225 is formed by diffusion, and further, for example, a selective double diffusion of phosphorus and antimony is performed to form the double buffer layer 207 (see FIG. 3 [1]). After that, a SiO 2 for dielectric insulation isolation is formed. 2 An insulating film 206 is formed on the entire surface. The thickness of the insulating film 206 may be about 4 μm. Then, the SiO 2The insulating film 206 is removed by selective etching, and then a p+ single crystal layer for the p+ collector 204 is formed by epitaxial growth. For example, the thickness of the p+ epitaxial layer may be 18 μm. The p+ epitaxial layer is then selectively etched to form the p+ collector 204. The p+ collector 204 in the n short-circuit layer 205 formation portion is then removed by selective etching, and the SiO2 dielectric insulating separation film 206 in the third main electrode 215 formation portion is then selectively etched away (see [2] in FIG. 2). This exposes the single crystal in the n short-circuit layer 205 formation portion and the third main electrode 215 formation portion. Next, n+ epitaxial growth is performed on the entire surface until it reaches a thickness that completely fills all the separation trenches, including the third main electrode 215 formation portion. At this time, n single crystals grow on the n+ short circuit layer 205 formation portion, the third main electrode 215 formation portion, and the p+ collector 204, while n polycrystals grow on the insulating isolation oxide film 206, resulting in a mixture of both crystals in the isolation region 217. After that, grinding and mirror polishing are performed until the p+ collector 204 is exposed, completing the element integrated substrate 201 (see [3] in FIG. 3).

[0058] After that, a wafer with a new bonded structure (SP&S-DBS) is completed by bonding this wafer, a separately prepared n+ single crystal wafer having only a single crystal surface bonding surface and serving as an element support substrate 202, and an element integrated substrate 201 having a new polycrystalline and single crystal surface mixed bonding surface (see [4] in FIG. 3). The bonded wafer with this new bonded structure has a smaller curvature than a wafer of a conventional epitaxial growth substrate, and has a smaller curvature and stronger adhesive strength than the wafer of the bonded structure (P&S-DBS) of a single crystal surface and a polycrystalline single surface disclosed in the first embodiment and the conventional wafers disclosed so far. The reason for the smaller curvature is that polycrystals shrink more severely than single crystals when cooled after epitaxial growth, causing the wafer to bend more, but in the new structure, the shrinkage is suppressed because single crystal regions are mixed. The strong adhesive strength is due to the fact that, while the conventional bonding portion is only a bonding portion of a single crystal and a polycrystal, the new structure also has a bonding portion of a single crystal and a single crystal, which has a strong adhesive strength. However, the bonding portion of the single crystal and the single crystal tends to have voids at the bonding boundary, which reduces the bonding strength, so the occurrence of voids has been eliminated by making efforts in the bonding temperature and pressure, bonding atmosphere gas, and pretreatment materials. The bonded wafer thus completed has small curvature and strong adhesive strength, and the upper surface of the single crystal main substrate 230 is then polished until the dielectrically isolated crystal island is exposed from the upper surface side of the bonded wafer, finishing the element integrated substrate 201, and completing the wafer for power integrated circuit semiconductor device chips (see [5] in Figure 3). The thickness of the completed wafer may be about 300 μm. After that, 4 μm of Si in the portion where the buried insulating film 240 is to be formed is removed by selective etching, then selective ion implantation of phosphorus or aluminum is performed in the portion where the SCaDFRR 221 is to be formed, and then SiO2 having a thickness of 4 μm or more is formed on the entire surface by CVD, followed by mirror polishing to complete the formation of the buried insulating film 240. After that, although a description is omitted because it is a well-known general method, electrodes and wiring such as output elements with a trench gate structure, elements for drive and control circuits with a planar gate structure, elements for detection and protection circuits, and the third electrode 215 are formed in each single crystal island using a predetermined element manufacturing technology to complete the power integrated circuit semiconductor device of the second embodiment (see [6] in FIG. 3).

[0059] In this embodiment, by using the above-mentioned new bonding structure (SP&S-DBS), the curvature of the bonded wafer can be reduced and the bonding strength of the entire bonded wafer can be improved. As a result, the manufacturing process can be simplified in the subsequent specified element manufacturing process, damage during element manufacturing can be reduced, and the yield of good products can be improved. Above all, the new bonding structure (SP&S-DBS) makes it possible to omit the conventional high-temperature and long-term epitaxial growth process at about 1200°C, thereby achieving a significant simplification of the power integrated circuit semiconductor device manufacturing process and simplifying the manufacturing equipment. The enormous benefits are that it simplifies operation and maintenance, resulting in significant cost reductions.

[0060] Other than the above, the main structural specifications, for example, the drift layer, p-body region, n+ emitter region, n-buffer layer, gradient channel stopper, and gate oxide film, are the same as those in the first embodiment. On the other hand, the p+ collector region is 1×10 19 cm -3 18μm, and the impurity concentration of the p+ isolation region is 1x10 19 cm -3 The distance from the p-body region to the SiO2 dielectric insulating isolation film may be 170 μm, the thickness of the SiO2 dielectric insulating isolation film may be 4 μm, and the p+ element support substrate may have a carrier concentration of 1×10 19 cm -3 The thickness may be 150 μm. In this case, the thickness of the element integrated substrate 201, that is, the thickness of the region between the p+ element support substrate 202 and the surface of the chip body, is 155 μm.

[0061] Next, the characteristics of the power integrated circuit semiconductor device manufactured by the above process flow will be described. This power integrated circuit semiconductor element chip 200 was mounted in a package created for characteristic measurement and subjected to an operation test. Naturally, the third main electrode 215 is wire-bonded to the metal terminal surface of the package to which the second main electrode 203 is die-bonded, and the two are electrically connected. The element exhibits good forward blocking characteristics, withstand voltage at room temperature, i.e., the voltage indicating avalanche breakdown, is about 1.36 kV, and the leakage current before avalanche breakdown is 5×10 at room temperature. -6 A / cm 2 Below, even at high temperatures of 250°C, the -5 A / cm 2 The results are good, at less than 1.9μs. Furthermore, when a gate voltage is applied in the forward direction and then increased, the reverse conducting IGBT turns on, but no snap-back phenomenon was observed when it turns on. When a current density of 100A / cm2 is applied in the on state, the on-voltage at room temperature is low and good, at approximately 1.9V. Furthermore, the turn-off time when a current density of 50A is applied is approximately 0.7μs, which is shorter than that of a Si-IGBT of the same voltage class. As a result of the reduced turn-off time and increased speed, switching losses can be significantly reduced and low-loss can be achieved. Furthermore, the 100A / cm2 current density of the FWD 2 When a current density of 1.5 V is applied at room temperature, the on-state voltage is low and favorable.

[0062] As described above, according to this embodiment, by applying the SCaDFRR and the buried insulating film, it becomes possible to integrate a vertical structure reverse conducting IGBT with high withstand voltage and large current capacity as an output element of a power integrated circuit semiconductor device chip, and it is possible to achieve high withstand voltage, reduction in chip occupation area, and low loss, and it is possible to achieve a significant increase in capacity of the power integrated circuit semiconductor device. In addition, by applying the new polycrystalline and single crystal mixed bonding structure (SP&S-DBS), it is possible to realize a dielectric isolation type integrated circuit wafer with a good quality bonding surface with strong adhesive strength, small curvature, and low cost. Furthermore, it is possible to eliminate the snapback phenomenon and achieve high reliability. In addition, during the return current of the inverter, the built-in diode consisting of the p body and n drift layer can be used as a FWD diode, and there is no need to provide a new diode separately, and the semiconductor chip size of the power integrated circuit semiconductor device can be significantly reduced, and further cost reduction can be achieved.

[0063] (Embodiment 3) In general, SiC semiconductor elements have the following characteristics compared to Si semiconductor elements: high voltage resistance, small size and low loss, high heat resistance, It has significantly superior performance in terms of high heat dissipation and high power tolerance, making it suitable for power elements. In particular, since the dielectric breakdown field strength of SiC is high, the width of the field region of the element is set to about one order of magnitude that of Si. Since it can be made small, the device area can be significantly reduced for the same breakdown voltage. - Integrated circuit semiconductor devices have a higher leakage current than pn isolation type power integrated circuit semiconductor devices. Since the amount of SiO2 is extremely small even at high temperatures, it is suitable for achieving high voltage and heat resistance. Since the width can be significantly narrowed, it is suitable for small, low-loss, high-voltage integrated circuit semiconductor devices. The inventors have focused on the above features and have implemented the above features in the first and second embodiments in order to better achieve the object of the present invention. The new polycrystalline and single crystal mixed bonded structure SP&S-DBS and the new In addition to the SCaDFRR structure, a new structure suitable for SiC dielectrically isolated power integrated circuit semiconductor devices A new single crystal island crystal plane structure was devised and applied to the third embodiment. FIG. 4 shows a SiC dielectric isolation type power supply manufactured using the SiC semiconductor according to the third embodiment. Schematic cross-sectional view of an integrated circuit semiconductor device chip 300, focusing on an output element which is a main part of the chip. The integrated circuit semiconductor device chip 300 is made up of an element integrated substrate 301, an element support substrate 302, and These are bonded together using the new bonding structure SP&S-DBS according to the present invention. However, since the current SiC bulk crystal has inferior crystal quality compared to Si bulk crystal, for example, in the process flow of FIG. 3 (which is an IGBT process flow and should be referred to with the understanding that it differs from MOSFETs), [1] (described in

[0057] ) before forming a mask for forming an isolation groove on the starting n-type single crystal main substrate 230, epitaxial growth of an n-type single crystal layer thicker than the V isolation groove of a predetermined depth is performed on the SiC single crystal main substrate (corresponding to 230 in FIG. 3), so that all the completed single crystal islands are embedded in this epitaxial layer. As a result, since the SiC epitaxial single crystal layer has much better crystal quality than the SiC bulk crystal, each integrated circuit component element formed on the epitaxial single crystal island can have significantly better characteristics than when formed in the SiC bulk crystal. Naturally, the SiC single crystal main substrate is completely removed in the polishing step in the process flow [5] of Figure 3, and only the epitaxial single crystal remains in each single crystal island of the device integration substrate. The same applies to the device integration substrates of the fourth and subsequent embodiments. The above-mentioned novel SiC bonding structure SP&S-DBS can be formed by using the bonding method and its pretreatment described in the top lines 11 to 18 of

[0036] . The same can be said for the SiC chips of the SiC dielectric isolation type power integrated circuit semiconductor devices of the following embodiments 4, 5, and 8.

[0064] The output element is a SiC reverse conducting MOSFET with a design breakdown voltage of 1.2 kV and a current capacity of 100 A, and is integrated in a dielectric insulating isolation island of the element integration substrate 301. It is a vertical reverse conducting MOSFET with a trench gate structure and has a stripe shape. The single crystal island in which the output element is integrated is about 2.5 mm wide and 5 mm long. A large number of cells are integrated and connected in parallel in the single crystal island, but only four cells are shown in the figure for the sake of explanation to avoid complication. In the dielectrically isolated integrated circuit semiconductor device, the semiconductor chip body is configured by single crystal islands laid out in the isolation region 317 via the dielectric insulating isolation film 306, and the side of the single crystal island is inclined at a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body. In order to realize an ideal combination of the above-mentioned dielectrically isolated integrated circuit semiconductor device and a SiC semiconductor, in this embodiment, a novel single crystal island crystal plane structure is used in which each face of the single crystal island is configured with a face of a crystal orientation unique to the present invention. That is, 4HSIC is used to form an n-single crystal island, the surface of the single crystal island is composed of the C-face, i.e., the (000-1) crystal face, the side is composed of the {0-33-8} face, and the bottom of the single crystal island is composed of the Si-face, i.e., the (0001) face. As a result, the following advantages are obtained. (1) In the manufacture of ordinary SiC individual elements, the Si-face has been achieved with extremely high flatness at the atomic level by using the catalytic surface reference etching method (CARE method), which is an excellent flattening technique, and it has been reported that the flatness achieved by applying this method is better than that of the C-face. Therefore, by making the bottom of the single crystal island the Si-face, a better quality and stronger bonding surface between the single crystal faces can be obtained in the polycrystalline and single crystal mixed bonding structure SP&P-DBS, which is extremely suitable for the vertical element composed of the bonding of the single crystal parts in this embodiment. (2) The {0-33-8} plane on the side has an inclination angle of 54.7 degrees or (180 degrees - 54.7 degrees) with respect to the C-plane on the surface, and is suitable in that it has an extremely fast oxidation rate and is easy to form a thick insulating isolation oxide film for high voltage. In other words, by forming a thick insulating isolation oxide film, the MOS effect caused by the potential difference between the isolation region and the single crystal island can be suppressed, and depletion and accumulation on the side of the single crystal island through the dielectric insulating isolation film can be suppressed, thereby suppressing interference with the characteristics of the high voltage elements inside the single crystal island, such as an increase in leakage current.Furthermore, this plane is also extremely suitable as a crystal plane for forming a high-quality gradient channel stopper layer for high-voltage elements, since even if there are minute defects such as micropipes in the drift region that cause voltage failure, they can be almost completely blocked during the formation of the growth layer by CVD methods such as epitaxial growth. (3) The C plane provides the best MOS interface, making it ideal for fabricating MOSFETs with high channel mobility. Furthermore, the C plane is the crystal plane with the highest oxidation rate, making it extremely suitable for high-voltage integrated circuit semiconductor devices that require a thick, high-quality insulating protective film under the jumper wiring.

[0065] Incidentally, in the SiC semiconductor device, the thickness of the drift region can be significantly reduced for the same breakdown voltage as the Si semiconductor device of the second embodiment, and therefore the V-groove for forming the single crystal island can be significantly shallower. This results in the following advantages. (1) In the epitaxial growth process for filling the V-groove when forming the isolation region of the device integration substrate, the polycrystalline layer formed can be thin, so that the curvature caused by the contraction of polycrystalline Si during the cooling process at the end of the epitaxial growth can be reduced. As a result, the processes of polishing and bonding in the subsequent flattening process for bonding can be easily performed, and the wafer can be made large in diameter, which is advantageous for reducing costs. (2) In order to obtain a predetermined strength with less damage in a series of manufacturing processes for forming the device on the single crystal island, the wafer thickness is generally set to, for example, about 300 to 400 μm. For example, if the thickness is set to 300 μm, a 1.2 kV Si element is restricted by a thick drift region of about 150 μm, so the thickness of the element support substrate wafer must be half that, at about 150 μm, but with a SiC element, the drift region can be made significantly thinner, so it can be made thicker at about 250 μm. As a result, the element support substrate wafer can be made thicker, making it less likely to bend, and in the series of manufacturing processes for forming elements on single crystal islands, there are fewer adverse effects such as wafer bending due to oxidation and high-temperature heat treatment, and damage to elements due to these fluctuations.

[0066] The configuration and features of the third embodiment of Fig. 4 will be specifically described below. In the third embodiment, the output element is a stripe-shaped trench-gate type SiC reverse conducting MOSFET 300, and most of its main functional parts are formed in a dielectric isolation island, but since the insulating film at the bottom of this dielectric isolation island is removed, it can be connected to an n+ element support substrate 302 via an n-drain 305, and this n+ element support substrate 302 is connected to a second main electrode 303. Therefore, the element between the first main electrode 320 and the second main electrode 303 can function as a vertical reverse conducting SiC MOSFET, and the drift resistance can be reduced compared to the horizontal structure of the first embodiment, and the on-resistance reduction effect due to this and the on-resistance reduction effect due to the physical properties of SiC can significantly reduce loss.

[0067] In this embodiment, similarly to the second embodiment, a significant portion of the thick insulating film 318 under the interconnector 316, which was previously formed on the chip surface, is formed as a buried insulating film 340 under the surface of the chip body, and a SCaDFRR 321 is provided directly below it, thereby achieving a high breakdown voltage, and further reducing the thickness of the insulating protective film 318 on the surface of the chip body, thereby reducing the steps and the number of steps. Since the diffusion speed of impurities in SiC is extremely slow compared to Si, a high-concentration n-type gradient channel stopper must be formed by a deposition technique such as CVD. As a result, the gradient channel stopper on the main surface of the chip under the wiring has a nearly uniform high-concentration carrier concentration (for example, 8×10 18 cm -3 ) and the carrier concentration (for example, 8×10 15 cm -3 The difference between the surface electric field strength and the surface electric field strength (which may be 1x10) is extremely large, and the extension of the channel under the wiring is abruptly stopped at this portion, causing a sudden increase in the surface electric field strength, resulting in dielectric breakdown and damage to the SiC surface portion and the SiO2 film. In this embodiment, in addition to the FRR, a new SCaDFRR321 is provided to reduce the surface electric field strength. This SCaDFRR321 ion-implants a p-type dopant into the n-type gradient channel stopper on the main surface of the chip to offset the carrier concentration, for example, 1x10 16 ~5x10 17 cm-3 The surface electric field strength is relaxed within the range of 1.2 μm. In the case of a 1.2 kV SiC element, the width of the field region is about 15 μm, which is about one order of magnitude smaller than that of a Si element, so the high voltage resistance effect of the SCaDFRR321 formed on the surface of the gradient channel stopper with a thickness of about 5 μm is relatively significantly larger than that of a Si element. In addition, if a part of the high voltage resistance effect of the SCaDFRR321 is used to reduce the thickness of the insulating protective film 318, a larger thickness reduction effect can be obtained than in the case of Si. As a result, for example, a surface insulating protective oxide film of 12 μm or more is required to achieve a 1.2 kV withstand voltage, but if the thickness of the buried insulating film 340 under the surface is set to about 4 μm and the insulating film thickness reduction effect due to the high withstand voltage by the SCaDFRR321 is added to this, the surface insulating protective oxide film can be made 6 μm or less, and the chip area can be reduced by reducing the number of steps in the chip. In addition, a part of the reduced chip area can be used to increase the number of cells, thereby achieving a low loss effect.

[0068] In addition, this element functions as a flywheeling diode FWD, which is essential for inverters and the like, when the high-voltage main junction is reverse biased, and corresponds to a reverse conducting SiC MOSFET as defined in

[0007] . It is not necessary to introduce or form a new FWD separately, and cost reduction is expected due to a significant reduction in chip area. Since the FWD requires a current capacity almost equal to that of a MOSFET, the semiconductor chip size of the power integrated circuit semiconductor device can be reduced to approximately half, and the power integrated circuit semiconductor device chip can be made smaller and less expensive. Incidentally, the above-mentioned FWD is composed of a built-in SiC pn diode, but such a SiC bipolar semiconductor element has an on-voltage degradation phenomenon in which the on-voltage specific to SiC increases over time due to stacking faults inherent in the element. This causes the loss of the element when current is applied to increase over time, the efficiency of the applicable device such as an inverter to deteriorate over time, and if it progresses excessively, the element may be damaged, or the current sharing balance between the elements in the module may be lost, causing some elements to be damaged, leading to damage to the applicable device. As a countermeasure to resolve or suppress this, the present inventor developed the MaCH-TEDREC method and disclosed it in Patent No. 5835679. This method is a method of preventing the expansion of stacking faults that are inherent in the element, which are the cause of degradation, by raising the element temperature to a degradation suppression temperature or higher (for example, 150°C to 200°C or higher in the case of elimination) by passing only majority carriers during element startup or operation. In the case of a reverse conducting MOSFET using an inherent pn diode as a FWD, only the forward current caused by majority carriers can be passed independently during forward bias, so that the MaCH-TEDREC method can be applied to resolve on-voltage degradation. In this way, this embodiment can resolve the on-voltage degradation over time that is specific to SiC bipolar elements and achieve high reliability of a power integrated circuit semiconductor device.

[0069] The main structural specifications of this embodiment are as follows. For example, the drift layer 308 has an impurity concentration of 8×10 15 cm -3 The thickness of the n+ source region 310 may be 13 μm. The impurity concentration and thickness of the n+ source region 310 may be 3×10 19 cm -30.3μm, p-body region 309 is 1x10 18 cm -3 The thickness from the main surface is 0.7 μm, and the n-gradient channel stopper layer is 8 x 10 18 cm -3 -Thickness 4μm, n+ drain region 304 is 5x10 19 cm -3 The thickness may be 13 μm, the distance from the p-body region to the SiO2 dielectric insulating isolation film may be 25 μm, and the thickness of the SiO2 dielectric insulating isolation film 306 may be 5 μm. 19 cm -3 The thickness may be 260 μm. In this case, the thickness of the element integrated substrate 301, that is, the region between the n+ element support substrate 302 and the surface of the chip body, is about 40 μm. The thickness of the gate oxide film 311 may be 1000 angstroms.

[0070] Next, the characteristics of the power integrated circuit semiconductor device according to this embodiment will be described. This power integrated circuit semiconductor element chip 300 was mounted in a package created for characteristic measurement and subjected to an operation test. When a forward voltage was applied between the source electrode 320 and the drain electrode 303 with no gate voltage applied, a leakage current flows, but the device exhibits good forward blocking characteristics, and the withstand voltage at room temperature, i.e., the voltage at which avalanche breakdown occurs, is about 1.42 kV. Also, the leakage current before avalanche breakdown is 5×10 at room temperature. -6 A / cm 2 The following is 1x10 even at high temperatures of 250°C. -6 A / cm 2 The results are satisfactory, with a current of less than 100A / cm. Also, when a gate voltage is applied in the forward direction and increased, the reverse conducting MOSFET turns on. 2 The on-state voltage at room temperature when a current density of 1000 Ω / cm is applied is low at 0.35 V, and the on-state voltage at 200°C is also low at 0.51 V. The specific on-state resistance RonS is 3.5 mΩ / cm at room temperature. 2 The gate voltage Vg is set to 20 V and the current is 300 A / cm 2 When a current density of 50A / cm is applied, the on-state voltage is about 1.5V, which allows for significant loss reduction. 2When measured under the condition of a current density of 100 A / cm, the turn-on time was 1.5 ns and the turn-off time was about 35 ns. As a result of reducing the switching time and increasing the speed, the switching loss can be significantly reduced. 2 Current density was applied for 2000 hours. The MaCH-TEDREC method was effective even after the test, and no on-state voltage degradation was observed.

[0071] As described above, according to this embodiment, by applying SCaDFRR and a buried insulating film to the SiC reverse conducting MOSFET which is the output element of the SiC power integrated circuit semiconductor device chip, a high breakdown voltage is achieved, and by reducing the thickness of the insulating film on the surface of the chip body, the step and the number of steps are reduced, thereby achieving a reduction in chip area and low loss. In addition, by applying the new single crystal island crystal plane structure and the new polycrystalline and single crystal mixed bonding structure SP&S-DBS, a thick oxide film is easily formed under the jumper wiring, making it easy to achieve a high breakdown voltage, and a low-cost dielectric isolation type integrated circuit semiconductor device with a good quality and strong bonding surface with small curvature can be realized. Furthermore, during the return current of the inverter, a diode consisting of a p body and an n drift layer in the element can be used as a FWD diode, and there is no need to provide a new diode separately, and the semiconductor chip size of the power integrated circuit semiconductor device can be significantly reduced, resulting in further cost reduction. In addition, high reliability can be achieved by eliminating on-voltage degradation.

[0072] (Fourth embodiment) Fig. 5 is a schematic cross-sectional view showing an output element, which is a main part of a SiC dielectric isolation type power integrated circuit semiconductor device chip with a design breakdown voltage of 1.2 kV and a current capacity of 80 A class, manufactured using a SiC semiconductor according to the fourth embodiment. This is an output vertical reverse conducting MOSFET intended to be able to respond to a case where a power conversion equipment equipped with this chip needs to suddenly supply a large current exceeding that during normal operation in the event of an accident or the like. The differences in the element structure compared to the third embodiment are that the third main electrode 415 is provided in the adjacent isolation region 417 and is externally connected to the second electrode 403 by wire bonding, that the isolation region 417 is p-type SiC with the polarity opposite to that of the n-type element support substrate 402, and that p-collectors 404 of the reverse conducting IGBT are provided on both sides of the n-drain 405. Functionally, during normal operation, the vertical reverse conducting MOSFET between the first main electrode 420 and the second main electrode 403 operates, and when a large current is supplied during an accident or the like, the reverse conducting IGBT between the first main electrode 420 and the second main electrode 403 and the third main electrode 415 also operates, and the current passing through the IGBT is added to the current passing through the vertical reverse conducting MOSFET for a predetermined, relatively short time until the protection device is activated, thereby responding to the accident. When the reverse conducting IGBT operates, the n-drain 405 of the vertical reverse conducting MOSFET and the element support substrate 402 function as a short circuit, accelerating the discharge of remaining carriers at the time of turn-off and reducing loss.

[0073] 5, the fourth embodiment includes all the new matters of the present invention described in the second and third embodiments. That is, the new SCaDFRR and buried insulating film, the new single crystal island crystal surface structure, the new polycrystalline and single crystal mixed laminated structure SP&S-DBS, the new reverse conducting IGBT structure with the third main electrode, etc. are all included, and the same effect is achieved. Also, except for the element structure in the single crystal island and the above-mentioned differences, the fourth embodiment is almost the same as the third embodiment, including the specifications.

[0074] The area of ​​the single crystal island is the same, but the area of ​​the third main electrode is increased. In addition, since p collectors are provided on both sides, the width of the n drain is about 80%, and the rated current during operation is reduced by about 20%. However, in the event of an accident, a reverse conducting IGBT current can be passed. For example, with an applied voltage of 7V, the element temperature rises due to self-heating, and the on-resistance of the MOSFET increases, so the current does not flow in proportion to the applied voltage, but the on-resistance of the reverse conducting IGBT hardly changes even if the element temperature changes due to the contribution of the conductivity modulation effect. As a result, in the event of an accident, a current of about 190A, nearly twice that of the reverse conducting MOSFET of embodiment 3, can be expected, although it is for a short period of time limited by the thermal resistance of the package, etc. In addition, high reliability can be achieved by eliminating the snapback phenomenon and the on-voltage degradation of the IGBT and FWD. Furthermore, although the current passing through the FWD decreases slightly, it is at a level that does not cause any practical problems, and there is no need to provide a new diode separately, so the SiC chip size can be significantly reduced, and costs can be reduced.

[0075] In this embodiment, the ratio between the low on-resistance MOSFET function and the current-withstand function can be set to some degree as desired depending on the application by changing the ratio between the width of n-drain 405 and the width of p-collector 404. In some cases, it is also possible to enjoy only the MOSFET function between the first and second main electrodes without connecting the third main electrode to the second main electrode.

[0076] As described above, according to this embodiment, in the event of an accident, although the period is limited by the thermal resistance of the package and the like, a larger current flow is expected compared to the reverse conducting MOSFET of the third embodiment. Also, as in the third embodiment, by applying the SCaDFRR and the buried insulating film, a high breakdown voltage can be achieved, and the thickness of the insulating film on the surface of the chip body can be reduced, thereby reducing the steps and the number of steps, thereby reducing the chip area and reducing loss. Also, high reliability can be achieved by eliminating the snapback phenomenon and on-voltage degradation. Furthermore, during the return current of the inverter, the diode composed of the p body and n drift layer contained in the element can be used as the FWD diode, and there is no need to provide a new diode separately, so that the semiconductor chip size of the power integrated circuit semiconductor device can be significantly reduced, thereby reducing costs.

[0077] (Embodiment 5) FIG. 6 is a cross-sectional view showing a schematic diagram of an output element, which is a main part of a SiC dielectric isolation type power integrated circuit semiconductor device chip with a design breakdown voltage of 1.2 kV and a current capacity of 60 A, manufactured using a SiC semiconductor according to embodiment 5. The temperature dependency of the on-resistance of the SiC-IGBT is extremely small compared to that of the SiC-MOSFET, so this is an output vertical reverse conducting IGBT intended for use in high temperature regions. The differences in element structure from embodiment 4 are that the isolation region 517 is made of n-type SiC having the opposite polarity to the p-type element support substrate 402, that n short-circuiting parts 505 of the reverse conducting MOSFET are provided on both sides of the p-collector 504, and that the element support substrate 502 is made of polycrystalline SiC. When the reverse conducting IGBT operates, residual carriers at the time of turn-off are quickly discharged via the short-circuiting parts 505 and the third main electrode 515 externally connected to the second main electrode 503, thereby reducing loss. In this embodiment 5, polycrystalline SiC is used as the element support substrate 502 in the novel polycrystalline / single crystal mixed bonding structure SP&P-DBS of the present invention, but by increasing the bonding temperature, it is possible to realize a bonding strength that is comparable to that of a single crystal support substrate, and curvature is at an acceptable level, so there is no problem in practical use. The advantage of being able to significantly reduce costs compared to single crystal element support substrates is extremely large.

[0078] (Sixth embodiment) FIG. 9 is a schematic cross-sectional view showing an output element, which is a main part of a SiC dielectric isolation type power integrated circuit semiconductor device chip 600 manufactured using a SiC semiconductor according to the sixth embodiment. The output element is a SiC reverse conducting MOSFET with a design breakdown voltage of 1.2 kV and a current capacity of 100 A, and is a vertical structure reverse conducting MOSFET with a trench gate structure, and has a stripe shape. The width of the single crystal island in which the output element is integrated is about 2.5 mm, and the length of the single crystal island is 5 mm. In comparison with the third embodiment, the sixth embodiment has the single crystal island side formed of {11-22} crystal planes, and when forming the isolation region of the element integrated substrate 701 without using an attachment substrate, the epitaxial growth layer is thickened to make the element integrated substrate 701 serve as an element support substrate. However, the structural specifications and manufacturing process flow of the integrated circuit semiconductor device chip 600 and the SiC reverse conducting MOSFET of the output element are exactly the same, and the characteristics of the manufactured output element are almost the same. The side surface of the single crystal island formed by the {11-22} crystal plane of the sixth embodiment has a larger inclination angle with respect to the C-plane of the front surface of the single crystal island and the Si-plane of the back surface of the single crystal island than the {0-33-8} plane, so that the bottom area of ​​the single crystal island can be increased, thereby reducing the on-resistance of the output element, and the volume of the single crystal island can be increased, thereby increasing the heat storage capacity and the power withstand capacity. This feature has a greater effect as the withstand voltage of the element increases, since the drift layer becomes thicker and the single crystal island becomes thicker as a result. Naturally, the same effect can be obtained by using a crystal plane other than the {11-22} plane, such as the {10-12} plane or the {10-11} plane, which has a larger inclination angle with respect to the surface of the single crystal island than the {0-33-8} plane. In addition, the sixth embodiment does not have various advantages of using a bonding substrate as in the first to fifth embodiments, but has an advantage of reducing the number of manufacturing steps, since the thick element integrated substrate of the present embodiment can be formed by simply extending the epitaxial time for forming the isolation region of the element integrated substrate.

[0079] (Seventh embodiment) FIG. 7 shows the output element configuration for one phase of a Si dielectric isolation type single-phase inverter integrated circuit semiconductor device according to a seventh embodiment, which is configured using Si semiconductor elements with a withstand voltage of 1.2 kV and a current capacity of 30 A. All output elements are reverse conducting Si-IGBTs with a trench gate structure, the upper arm is a reverse conducting Si-IGBT with a vertical structure, and the lower arm is a reverse conducting Si-IGBT with a horizontal structure. FIG. 7 shows a simplified element structure, and the numbers and arrows of each structural element are omitted. However, the horizontal structure reverse conducting Si-IGBT has almost the same element configuration as the IGBT of the first embodiment in FIG. 1, except for the element size and the fact that it is formed on a p-type single crystal element support substrate, and the vertical structure reverse conducting Si-IGBT has almost the same element configuration as the IGBT of the second embodiment in FIG. 2, except for the element size. The fabrication process flow of the element structure in FIG. 7 is almost the same as the process flow in FIG. 3. That is, although not shown, a single crystal island for a lateral reverse conducting Si-IGBT that is larger than the vertical reverse conducting Si-IGBT is created in the same manner as the small single crystal island 260 for the control circuit element in Fig. 3, and a wafer for fabricating chips for integrated circuit semiconductor devices is completed as in Fig. 3(5). After that, a lateral reverse conducting Si-IGBT is also created in the single crystal island using a process flow similar to that for the element portion of the vertical reverse conducting Si-IGBT formed in the single crystal island.

[0080] In the upper arm of each phase of the single-phase inverter, the collectors of the reverse conducting Si-IGBTs of each layer are connected in parallel to the high potential wiring of the power supply, so an element structure in which the collector 204 can be connected in parallel to the second main electrode (collector electrode) 203 in FIG. 2 via an element support substrate is preferable. On the other hand, the lower arm of each phase is connected in parallel to the low and high potential wiring of the power supply, but the collector potential changes during the operation of the inverter, so a horizontal structure reverse conducting Si-IGBT in which the second main electrode (collector electrode) 203 is independent from the other phases is preferable. For this reason, the structure of FIG. 7 is set as a suitable arm structure for one phase. Compared to the vertical structure reverse conducting Si-IGBT, the drift resistance of the lateral structure reverse conducting Si-IGBT is large, so in order to make the current capacity of the 1.2 kV elements of the upper and lower arms almost the same, it is necessary to make the element area about three times larger so that the on-resistance can be made almost the same. According to the results of the trial calculation, it is expected that a one-chip single-phase inverter with 600V, 5kW, and PWM frequency of 20kHz class can be realized with a chip size of 20mm x 20mm. As a result, it is expected that this will contribute greatly to the miniaturization, weight reduction, and loss reduction of various motor-equipped devices such as home appliances, office equipment, vehicles, and industrial equipment.

[0081] (Embodiment 8) The semiconductor device according to embodiment 8 in FIG. 8 shows the output element configuration for one phase of a SiC dielectric isolation type three-phase inverter integrated circuit semiconductor device configured using SiC semiconductor elements with a breakdown voltage of 1.2 kV and a current capacity of 80 A. All output elements have a trench gate structure, with the upper arm being a reverse conducting SiC-MOSFET with a vertical structure and the lower arm being a reverse conducting SiC-MOSFET with a horizontal structure. Although a simplified structure is shown in FIG. 8, the vertical structure reverse conducting SiC-MOSFET has almost the same element configuration as the SiC-MOSFET of embodiment 3 in FIG. 4, except for the element size. Also, the lateral structure reverse conducting SiC-MOSFET is configured with SiC semiconductor instead of Si, and the values ​​of each component factor correspond to the SiC element, and except for the element size, the lateral structure reverse conducting SiC-MOSFET is similar to the IGBT of embodiment 1 in FIG. 1 in the single crystal island. The element configuration is almost the same. The fabrication process flow for the element structure in Fig. 8 is almost the same as the process flow in Fig. 3. That is, although not shown, a single crystal island for a lateral-structure reverse-conducting SiC-MOSFET, which is larger than a vertical-structure reverse-conducting SiC-MOSFET, is fabricated in the same manner as the single crystal island 260 for the small control circuit element, and the integrated circuit semiconductor device chip wafer in Fig. 3(5) is completed. After that, a lateral-structure reverse-conducting SiC-MOSFET is also fabricated in the single crystal island using almost the same process flow as the element portion of the vertical-structure reverse-conducting SiC-MOSFET formed in the single crystal island.

[0082] In the upper arm of each phase of the three-phase inverter, the collectors of the reverse conducting SiC-MOSFETs of each layer are connected in parallel to the high potential wiring of the power supply, so an element structure in which the drains 204 can be connected in parallel to the second main electrode (drain electrode) 203 in FIG. 2 via an element support substrate is preferable. On the other hand, the lower arm of each phase is connected in parallel to the low and high potential wiring of the power supply, but the collector potential changes during the operation of the inverter, so a lateral structure reverse conducting SiC-MOSFET in which the second main electrode (drain electrode) 203 is independent from the other phases is preferable. For this reason, the structure in FIG. 8 is set as the most preferable structure. Compared to the vertical structure reverse conducting SiC-MOSFET, the lateral structure reverse conducting SiC-MOSFET has a large drift resistance, so in order to make the current capacity of the 1.2 kV elements of the upper and lower arms almost the same, it is necessary to enlarge the single crystal island size of the lateral structure reverse conducting SiC-MOSFET to about 1.9 times larger so that the on-resistance can be made almost the same. According to the results of the trial calculations, a one-chip three-phase inverter with 600V, 30kW, and PWM frequency of 20kHz class can be realized with a chip size of 20mm x 20mm, despite the three-phase configuration. As a result, this can contribute greatly to the miniaturization, weight reduction, reduction of loss, and high reliability of various motor-equipped devices for home appliances, office use, vehicles, industrial use, etc.

[0083] (Embodiment 9) The semiconductor device according to embodiment 9 is a SiC dielectric isolation type three-phase inverter integrated circuit semiconductor device configured using SiC semiconductor elements with a withstand voltage of 1.2 kV and a current capacity of 60 A, not shown. The output elements constituting one phase are all reverse conducting SiC-IGBTs with a trench gate structure, the upper arm is a reverse conducting SiC-IGBT with a vertical structure, and the lower arm is a reverse conducting SiC-IGBT with a horizontal structure. The element support substrate is made of a p+ polycrystalline substrate. The vertical structure reverse conducting SiC-IGBT has almost the same element configuration as the IGBT of embodiment 5 in FIG. 6. The horizontal structure reverse conducting SiC-IGBT is the same as embodiment 1 in FIG. 1, except that it uses the element size and a structure factor with values ​​corresponding to SiC semiconductor, and is formed on a p-type single crystal element support substrate. Other than that, there are few differences from the above-mentioned embodiment 6, so the explanation will be omitted, but despite the large current capacity of 60A and the three-phase configuration, the effect of reducing the on-resistance due to the conductivity modulation of the IGBT makes a large contribution, and it is expected that a one-chip three-phase inverter suitable for high-temperature applications, 600V, 20kW, PWM frequency of 20kHz class, can be realized with a chip size of 20mm x 20mm. As a result, it can contribute greatly to the miniaturization, weight reduction, low loss, and high reliability of various motor-equipped devices for home appliances, offices, vehicles, industrial use, etc.

[0084] Although the present invention has been described above based on the first to ninth embodiments, it is obvious to those skilled in the art that the present invention is not limited to these and can be easily modified and applied in various ways. For example, it is natural that the present invention can be applied to a power integrated circuit semiconductor device in which a reverse conducting semiconductor element with a higher breakdown voltage of 2 kV or more or a low breakdown voltage of 1 kV or less is used as an output element by changing the numerical values ​​of the structural specifications or modifying the cell structure. Although the n-type reverse conducting SiC-IGBT has been mentioned, it is also natural that the present invention can be similarly applied to a p-type reverse conducting SiC-IGBT with a different polarity. It is natural that the cell shape can be modified and applied to various mesh shapes including a honeycomb shape in addition to the stripe shape mentioned. It is also natural that the present invention can be applied to semiconductor elements with various gates such as a planar gate type in addition to the trench gate type IGBT and MOSFET mentioned. Furthermore, although the reverse conducting SiC-IGBT and reverse conducting SiC-MOSFET have been mentioned as reverse conducting semiconductor elements, they can be expanded to other transistors such as static induction transistors and junction gate transistors, and can also be expanded to reverse conducting semiconductor elements using other wide gap semiconductors such as GaN and diamond. In addition, although a dielectrically insulated integrated circuit semiconductor device called EPIC has been mentioned, the crystal plane configuration of the single crystal island is not limited to the configuration mentioned in the present invention, and it is easily understood by those skilled in the art that the side surface can be configured with other crystal planes having a specific certain crystal plane angle with respect to the front and back surfaces of the single crystal island. In addition, although 4H-SiC has been mentioned, it is easily understood that the present invention can be applied to other polytypes of SiC crystals. Furthermore, it is easily understood by those skilled in the art that the present invention can be applied to SOI and other dielectrically insulated integrated circuit semiconductor devices other than EPIC, and further, that the present invention can be modified and applied to pn junction isolated integrated circuit semiconductor devices. [Industrial Applicability]

[0085] The present invention can be used in various inverters for EVs, HEVs, electric railway vehicles, etc., and can improve efficiency and extend driving distances by significantly reducing size and weight and reducing loss. It can also improve efficiency by reducing size and weight and reducing loss in power conditioners for solar power generation and wind power generation. It can also be applied to power supplies and inverters for home appliances and office equipment to reduce size and weight and reduce loss. As such, the industrial applicability is extremely great. [Explanation of symbols]

[0086] [1].101, 201, 301, 401, 501, 601: Element integration substrate. [2].102, 202, 302, 402, 502, 602: Element support substrate. [3].103, 203, 303, 403, 503, 603: First main electrode. [4].104, 204, 304, 404, 504, 604: P+ collector layer. [5].105, 205, 305, 405, 505, 605: N+ short circuit or N+ drain. [6].106, 206, 306, 406, 506, 606: Insulating isolation oxide film. [7].107, 207, 307, 407, 507, 607: N buffer layer. [8].108,208,308,408,508,608: n-type drift layer. [9].109,209,309,409,509,609: p-type body region.

[10] .110,210,310,410,510,610: n-type emitter region.

[11] .111,211,311,411,511,611: gate oxide.

[12] .112,212,312,412,512,612: polycrystalline silicon electrode.

[13] .113,213,313,413,513,613: gate electrode.

[14] .114,214,314,414,514,614: interlayer insulating film.

[15] . 115, 215, 315, 415, 515, 615: 3rd main electrode.

[16] . 116, 216, 316, 416, 516, 616: jumper wiring.

[17] . 117, 217, 317, 417, 517, 617: isolation region.

[18] . 118, 218, 318, 418, 518, 618: insulating film under jumper wiring.

[19] . 119, 219, 319, 419, 519, 619: internal wiring.

[20] . 120, 220, 320, 420, 520, 620: 1st main electrode.

[21] .121,221,321,421,521,621: Surface Carrier Concentration Reduced Field Relaxation Region (SCaDFRR).

[22] .122,222,322,422,522,622: Electrodes for control circuit elements.

[23] .123,223,323,423,523,623: Field plates.

[24] .124,224,324,424,524,624: Surface Field Relaxation Layer (abbreviated as FRR).

[25] .125,225,325,425,525,625: Graded channel stopper.

[26] .140,240,340,440,540,640: Buried insulating film.

[27] .230: Single crystal main substrate.

Claims

1. A dielectrically isolated integrated circuit semiconductor device, the semiconductor chip body of which is configured by laying single crystal islands in an isolation region with a dielectric insulating isolation film interposed therebetween, the side of the single crystal island has a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and the integrated circuit component elements in the single crystal island are connected to the integrated circuit component elements in other single crystal islands by wiring provided on a surface insulating protective film on the surface of the semiconductor chip body, the semiconductor chip body of the dielectrically isolated power integrated circuit semiconductor device is configured by laminating and bonding an element integration substrate, the element integration substrate being configured by spreading the single crystal islands including the integrated circuit components in the isolation region, and an element support substrate having both a support function for the element integration substrate and a conductive path function, a first main electrode and a control electrode on a surface of the predetermined single crystal island, the first main electrode and the control electrode being connected to the first main electrode and the control electrode on the surface of the predetermined single crystal island, the first main electrode and the control electrode being connected to the first main electrode and the control electrode on the surface of the predetermined single crystal island, the second main electrode and the control electrode being connected to the first main electrode and the control electrode on the surface of the predetermined single crystal island, the second main electrode and the control electrode being connected to the first main electrode and the control electrode on the surface of the predetermined single crystal island, the second main electrode and the control electrode being connected to the first main electrode and the control electrode on the surface of the predetermined single crystal island, the second main electrode and the control electrode being connected to the first main electrode and the control electrode on the surface of the predetermined single crystal island, the second main electrode and the control electrode being connected to the second ...

2. In

1. , the vertical semiconductor element is a bipolar element, the first main electrode is formed on the surface of the predetermined single crystal island on which the main functional part of the element integration substrate is formed, and the second main electrode is formed on the back surface of the element support substrate of the semiconductor chip body, a third main electrode is formed on a surface of the inclined channel stopper of the predetermined single crystal island on which the main functional part is formed or on a surface of the isolation region adjacent to the predetermined single crystal island via the dielectric insulating isolation film, and a part of the isolation region is connected to a buffer at the bottom of the predetermined single crystal island and the collector, a drift layer of said main function section and an isolation region of said element integration substrate have the same polarity, but said element support substrate has an opposite polarity, and said second main electrode and said third main electrode are electrically connected to each other, so that elements between the first main electrode and the second main electrode and between the first main electrode and the third main electrode constitute vertical reverse conducting semiconductor elements.

3. In

1. , the vertical semiconductor element is a unipolar element, the first main electrode is formed on the surface of the predetermined single crystal island on which the main functional part of the element integration substrate is formed, and the second main electrode is formed on the back surface of the element support substrate of the semiconductor chip body, a third main electrode is formed on the surface of the inclined channel stopper of the predetermined single crystal island on which the main functional part is formed or on the surface of the isolation region adjacent thereto via the dielectric insulating isolation film, and a part of the isolation region is connected to a buffer at the bottom of the predetermined single crystal island and the drain, a drift layer of the main function section and the element support substrate have the same polarity, but an isolation region of the element integration substrate has an opposite polarity; and the second main electrode and the third main electrode are electrically connected to each other, so that elements between the first main electrode and the second main electrode and between the first main electrode and the third main electrode constitute vertical reverse conducting semiconductor elements.

4. A power integrated circuit semiconductor device according to any one of claims 2 to 3, characterized in that the reverse conducting semiconductor element has a single buffer layer or a multiple buffer layer consisting of two or more layers.

5. In any one of claims 1 to 4, the semiconductor chip body is A structure in which the element integrated substrate having a bonding surface with a mixture of polycrystalline and single-crystalline surfaces is bonded to the element support substrate having a bonding surface with only a single-crystalline surface (SP&S-DBS); or a structure (SP&P-DBS) in which the element integration substrate having a bonding surface that includes a mixture of polycrystalline and single-crystalline surfaces and the element support substrate having a bonding surface that is made of only polycrystalline surfaces are bonded together.

6. 6. A power integrated circuit semiconductor device according to claim 1, wherein the semiconductor chip body is made of a SiC semiconductor.

7. A power integrated circuit semiconductor device as claimed in claim 6, characterized in that the specified single crystal island has a single crystal island crystal plane structure in which the surface is composed of a C-plane, i.e., a (000-1) crystal plane, the side is composed of a {0-33-8} plane, and the bottom surface of the single crystal island is composed of a Si-plane, i.e., a (0001) plane.

8. In any of claims 1 to 7, the power integrated circuit semiconductor device has an inverter circuit built therein, and an arm configuration of each phase of the inverter circuit is such that an upper arm is configured to include the vertical semiconductor element or the vertical reverse conducting semiconductor element described in

1. to

7. , and a lower arm is configured to include a lateral semiconductor element or a lateral reverse conducting semiconductor element.

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