Semiconductor device

Abstract

To provide a semiconductor device which can suppress degradation in high frequency properties.SOLUTION: A semiconductor device comprises: a substrate; a compound semiconductor layer 10b provided on the substrate; a plurality of unit FETs, aligned in an X-direction intersecting a Y-direction, each of which has a source electrode 12, a drain electrode 16, a gate electrode 14, and a field plate electrode 18 provided above the compound semiconductor layer between the gate electrode and the drain electrode, across an insulator film 25a. The plurality of unit FETs each has: a first unit FET 30h; and a second unit FET which is closer to an end of the plurality of unit FETs in the X-direction than the first unit FET. A first distance L2H between an end, of the gate electrode, closer to the drain electrode and an end, of the field plate electrode, closer to the drain electrode in the X-direction of the first unit FET is shorter than a second distance between an end, of the gate electrode, closer to the drain electrode and an end, of the field plate electrode, closer to the drain electrode in the X-direction of the second unit FET.SELECTED DRAWING: Figure 4C

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art It is known that a field plate is used in a FET (Field Effect Transistor) such as a HEMT (High Electron Mobility Transistor) having a compound semiconductor layer (see, for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-102756 A [Patent Document 2] JP 2008-277604 A Summary of the Invention [Problem to be solved by the invention]

[0004] The use of a field plate suppresses the concentration of the electric field in the semiconductor layer between the gate electrode and the drain electrode. It also suppresses the drift phenomenon of the drain current, such as current collapse. However, the provision of a field plate increases the electrostatic capacitance between the source and drain, degrading the high-frequency characteristics.

[0005] The present disclosure has been made in consideration of the above-mentioned problems, and has an object to suppress deterioration of high-frequency characteristics. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a compound semiconductor layer provided on the substrate; a source electrode provided on the compound semiconductor layer and extending in a first direction; a drain electrode provided on the compound semiconductor layer and extending in the first direction; a gate electrode provided on the compound semiconductor layer and extending in the first direction, the gate electrode being sandwiched between the source electrode and the drain electrode; and a field plate electrode provided above the compound semiconductor layer between the gate electrode and the drain electrode with an insulating film sandwiched therebetween, the plurality of unit FETs being arranged in a second direction intersecting the first direction, the plurality of unit FETs including a first unit FET and a second unit FET closer to an end of the plurality of unit FETs in the second direction than the first unit FET, and a first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the first unit FET is shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the second unit FET.

[0007] One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a compound semiconductor layer provided on the substrate; a source electrode provided on the compound semiconductor layer and extending in a first direction; a drain electrode provided on the compound semiconductor layer and extending in the first direction; a gate electrode provided on the compound semiconductor layer and extending in the first direction and sandwiched between the source electrode and the drain electrode; and a field plate electrode provided above the compound semiconductor layer between the gate electrode and the drain electrode with an insulating film sandwiched therebetween; and a plurality of unit FETs arranged in a second direction intersecting the first direction, wherein in at least one unit FET of the plurality of unit FETs, a first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at a center of the at least one unit FET in the first direction is shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at an end of the at least one unit FET in the first direction. Effect of the Invention

[0008] According to the present disclosure, degradation of high-frequency characteristics can be suppressed. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA of FIG. [Diagram 3] FIG. 3 is a plan view of the unit FETs 30a, 30d, and 30h in the first embodiment. [Figure 4A] FIG. 4A is a cross-sectional view of the unit FET 30a taken along the line AA. [Figure 4B] FIG. 4B is a cross-sectional view of the unit FET 30d taken along line AA. [Figure 4C] FIG. 4C is a cross-sectional view of the unit FET 30h taken along line AA. [Diagram 5]FIG. 5 is a diagram showing the length L1 and the distance L2 in each unit FET in the first embodiment. [Figure 6] FIG. 6 is a diagram showing the length L1 and distance L2 in each unit FET in the first comparative example. [Figure 7] FIG. 7 is a diagram showing the length L1 and the distance L2 in each unit FET in the first modification of the first embodiment. [Figure 8] FIG. 8 is a plan view of unit FETs 30a, 30d and 30h in the second embodiment. [Figure 9] FIG. 9 is a diagram showing the length L1 and the distance L2 in each unit FET in the second embodiment. [Figure 10] FIG. 10 is a plan view of unit FETs 30a, 30d, and 30h in the third embodiment. [Figure 11] FIG. 11 is a diagram showing the length L1 and the distance L2 in each unit FET in the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [Details of the embodiment of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a compound semiconductor layer provided on the substrate; a source electrode provided on the compound semiconductor layer and extending in a first direction; a drain electrode provided on the compound semiconductor layer and extending in the first direction; a gate electrode provided on the compound semiconductor layer and extending in the first direction, the gate electrode being sandwiched between the source electrode and the drain electrode; and a field plate electrode provided above the compound semiconductor layer between the gate electrode and the drain electrode with an insulating film sandwiched therebetween, the unit FETs being arranged in a second direction intersecting the first direction, the unit FETs including a first unit FET and a second unit FET closer to an end of the unit FETs in the second direction than the first unit FET, and a first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the first unit FET is shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the second unit FET, thereby suppressing deterioration of high frequency characteristics. (2) In the above (1), the distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in a unit FET among the plurality of unit FETs that is closest to a center of the plurality of unit FETs in the second direction may be the shortest among the distances in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode in the plurality of unit FETs, thereby improving high frequency characteristics. (3) In the above (1) or (2), the distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in a unit FET among the plurality of unit FETs that is closest to an end of the plurality of unit FETs in the second direction may be the longest among the distances in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode in the plurality of unit FETs, thereby improving high frequency characteristics. (4) In any one of (1) to (3) above, the first distance at the center of the first unit FET in the first direction may be shorter than the first distance at an end of the first unit FET in the first direction, thereby improving high frequency characteristics. (5) In any one of (1) to (4) above, the plurality of unit FETs may include a third unit FET provided between the first unit FET and the second unit FET in the second direction, and a third distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the third unit FET may be longer than the first distance and shorter than the second distance, thereby improving high frequency characteristics. (6) In any one of (1) to (5) above, a first length in the second direction of the field plate electrode in the first unit FET may be shorter than a second length in the second direction of the field plate electrode in the second unit FET, thereby improving high frequency characteristics. (7) One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a compound semiconductor layer provided on the substrate; a source electrode provided on the compound semiconductor layer and extending in a first direction; a drain electrode provided on the compound semiconductor layer and extending in the first direction; a gate electrode provided on the compound semiconductor layer and extending in the first direction, sandwiched between the source electrode and the drain electrode; and a field plate electrode provided above the compound semiconductor layer between the gate electrode and the drain electrode with an insulating film sandwiched therebetween, the unit FETs being arranged in a second direction intersecting the first direction, wherein in at least one unit FET of the plurality of unit FETs, a first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at a center in the first direction of the at least one unit FET is shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at an end of the at least one unit FET in the first direction. This can improve high frequency characteristics. (8) In the above (7), in the at least one unit FET, in a central portion including the center in the first direction and having a constant width in the first direction, a distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode may be constant, and a distance in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode may gradually increase from the central portion toward the end in the first direction. This can improve high frequency characteristics. (9) In any one of the above (1) to (8), in the plurality of unit FETs, the field plate electrode may be electrically shorted to the source electrode, thereby making it possible to suppress drift of the drain current. (10) In any one of the above (1) to (9), the compound semiconductor layer may be a nitride semiconductor layer, which can further suppress the drift of the drain current.

[0011] Specific examples of semiconductor devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0012] [Example 1] Example 1 is an example of a FET used in a radio frequency power amplifier. Fig. 1 is a plan view of the semiconductor device in Example 1. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1. The arrangement direction of source electrode 12, gate electrode 14, and drain electrode 16 is defined as the X direction (second direction intersecting the first direction), the extension direction is defined as the Y direction (first direction), and the normal direction of substrate 10 (i.e., the direction perpendicular to the upper surface of substrate 10) is defined as the Z direction. Field plates are not shown in Figs. 1 and 2.

[0013] 1 and 2, in the semiconductor device 100, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. The semiconductor layer 10b includes, for example, a channel layer 10c and a barrier layer 10d provided on the channel layer 10c. The substrate 10 includes an active region 11. The region other than the active region 11 is a non-active region 13 in which the semiconductor layer 10b is inactivated by ion implantation or the like. That is, the active region 11 is a region in the substrate 10 in which the semiconductor layer 10b is activated, and the non-active region 13 is a region in which the semiconductor layer 10b is inactivated.

[0014] A source electrode 12 (source finger), a gate electrode 14 (gate finger), and a drain electrode 16 (drain finger) are provided on the active region 11, extending in the Y direction. The planar shapes of the source electrode 12, the gate electrode 14, and the drain electrode 16 are substantially rectangular, with the longer sides of the rectangle extending in the Y direction. The source electrode 12, the gate electrode 14, and the drain electrode 16 are arranged in the X direction.

[0015] The source electrodes 12 and the drain electrodes 16 are alternately arranged in the X direction. The gate electrode 14 is sandwiched between one source electrode 12 and one drain electrode 16. The source electrode 12 and the drain electrode 16 sandwiching the gate electrode 14 form one unit FET 30a to 30h. Adjacent unit FETs 30a to 30h share the source electrode 12 or the drain electrode 16. The unit FETs 30a to 30h are arranged in the X direction. Of the arranged unit FETs 30a to 30h, the unit FETs 30a to 30h are arranged in order from an end 42 in the X direction to a center 40. The number of unit FETs can be set appropriately. The end 42 is the end in the X direction of the source electrode 12 of the outermost unit FET 30a in the X direction. The center 40 is the center in the X direction of both ends 42.

[0016] A gate bus bar 24 and a drain bus bar 26 are provided on the non-active region 13 of the substrate 10. The gate bus bar 24 and the drain bus bar 26 extend in the X direction. The +Y ends in the Y direction of the multiple gate electrodes 14 are connected to the gate bus bar 24. The -Y ends in the Y direction of the multiple drain electrodes 16 are connected to the drain bus bar 26.

[0017] A via hole 22 penetrating the substrate 10 is provided under the source electrode 12. A metal layer 28 is provided on the lower surface of the substrate 10. A reference potential such as a ground potential is supplied to the metal layer 28. A metal layer 28a is provided on the side and upper surface (i.e., bottom surface) of the via hole 22. The metal layer 28a is the same metal layer as the metal layer 28 and is formed at the same time. The source electrode 12 is electrically connected to the metal layer 28 through the via hole 22 and is short-circuited. This supplies a reference potential to the source electrode 12. The via hole 22 may not be provided in the source electrode 12, and a source pad to which the source electrode 12 is connected may be provided on the inactive region 13, and a via hole may be provided in the source pad.

[0018] Fig. 3 is a plan view of the unit FETs 30a, 30d, and 30h in Example 1. Figs. 4A to 4C are AA cross-sectional views of the unit FETs 30a, 30d, and 30h, respectively.

[0019] As shown in FIG. 3 to FIG. 4C, the field plate electrode 18 is provided above the gate electrode 14 and above the semiconductor layer 10b between the gate electrode 14 and the drain electrode 16, with the insulating film 25a sandwiched therebetween. Outside the active region 11, the field plate electrode 18 is electrically connected to the source electrode 12 by the wiring 15, and is short-circuited. The wiring 15 is formed, for example, from the same metal layer as the field plate electrode 18, and the wiring 15 and the source electrode 12 are in electrical contact with each other through an opening in the insulating film 25a. This provides a reference potential to the field plate electrode 18. The field plate electrode 18 may pass above the gate electrode 14 in the active region 11, with the insulating film 25a sandwiched therebetween, and be electrically connected to the source electrode 12. An insulating film 25b is provided on the source electrode 12, the drain electrode 16, and the field plate electrode 18. The insulating films 25a and 25b form an insulating film 25.

[0020] Fig. 5 is a diagram showing the length L1 and distance L2 of each unit FET in Example 1. The horizontal axis of Fig. 5 indicates unit FETs 30a to 30h arranged in the X direction, and the vertical axis indicates the length L1 and distance L2 of the unit FETs 30a to 30h. Length L1 is the length of field plate electrode 18 in the X direction. Distance L2 is the distance between the end of gate electrode 14 closer to drain electrode 16 in the X direction and the end of field plate electrode 18 closer to drain electrode 16 in the X direction.

[0021] As shown in Fig. 3 to Fig. 4C, the distance Lgd in the unit FETs 30a to 30h is approximately the same to the extent of a manufacturing error. The length L1 in the unit FETs 30a, 30d, and 30h is L1A, L1D, and L1H, respectively. The distance L2 in the unit FETs 30a, 30d, and 30h is L2A, L2D, and L2H, respectively. As shown in Fig. 3 to Fig. 4C, L1A>L1D>L1H and L2A>L2D>L2H. As shown in Fig. 5, the length L1 and the distance L2 become shorter from the end 42 toward the center 40. In each of the unit FETs 30a to 30h, the length L1 is approximately constant in the Y direction to the extent of a manufacturing error, and the distance L2 is approximately constant in the Y direction to the extent of a manufacturing error.

[0022] The semiconductor layer 10b is a compound semiconductor layer, for example, a nitride semiconductor layer or an arsenide semiconductor layer. When the semiconductor device is a nitride semiconductor layer, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a sapphire substrate, a gallium nitride (GaN) substrate, or a diamond substrate. The semiconductor layer 10b includes one or more nitride semiconductor layers, for example, gallium nitride, aluminum gallium nitride (AlGaN), or indium gallium nitride (InGaN). When the semiconductor device is a GaN HEMT, the channel layer 10c is, for example, a gallium nitride layer, and the barrier layer 10d is, for example, an aluminum gallium nitride layer.

[0023] When the semiconductor device is an arsenide semiconductor layer, the substrate 10a is, for example, a gallium arsenide (GaAs) substrate, and the semiconductor layer 10b includes one or more arsenide semiconductor layers, such as gallium arsenide, aluminum gallium arsenide (AlGaAs), or indium gallium arsenide (InGaAs).

[0024] The source electrode 12 and the drain electrode 16 are, for example, an adhesive film (for example, a titanium film) provided on the substrate 10 and a metal film such as an aluminum film provided on the adhesive film. A low resistance film such as gold may be provided on the aluminum film. The gate electrode 14 is, for example, an adhesive film (for example, a nickel film) provided on the substrate 10 and a metal film such as a gold film provided on the adhesive film. The field plate electrode 18 is, for example, a metal film such as an adhesive film (for example, a nickel film or a titanium film) provided on the insulating film 25a and a low resistance film (aluminum film or a gold film) provided on the adhesive film. The metal layers 28 and 28a are, for example, gold layers.

[0025] The insulating film 25a is an inorganic insulating film such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer, for example a silicon nitride layer. The insulating film 25b is an inorganic insulating film such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer, or an organic insulating film such as a polyimide layer.

[0026] [Comparative Example 1] Fig. 6 is a diagram showing the length L1 and distance L2 of each unit FET in Comparative Example 1. As shown in Fig. 6, in Comparative Example 1, the length L1 of the unit FETs 30a to 30h is length L10, which is approximately constant to within the range of manufacturing error. The distance L2 of the unit FETs 30a to 30h is distance L20, which is approximately constant to within the range of manufacturing error.

[0027] By providing the field plate electrode 18 between the gate electrode 14 and the drain electrode 16 and sandwiching the insulating film 25a, it is possible to suppress the electric field concentration in the semiconductor layer 10b. When the electric field in the semiconductor layer 10b between the gate electrode 14 and the drain electrode 16 becomes high, a drift of the drain current called a drain idle current (Idq) drift or a current collapse phenomenon is likely to occur. The mechanism by which the drift of the drain current occurs will be explained. Electrons become high-energy due to the high electric field, and are captured in traps in the semiconductor layer 10b. This reduces the drain current. The electrons captured in the traps are released over time. Therefore, when the electric field between the gate electrode 14 and the drain electrode 16 becomes low, the drain current recovers over time. In this way, the drift of the drain current occurs.

[0028] For example, when the semiconductor device is used in an amplifier circuit, if a drift in the drain current occurs, the output characteristics of the amplifier circuit are affected by the immediately preceding output and change. This complicates the processing of the distortion compensation circuit of the amplifier circuit, making distortion compensation difficult. Such a drift in the drain current is a problem that occurs in a FET that uses a compound semiconductor layer as the semiconductor layer 10b, and is particularly likely to occur when a nitride semiconductor layer is used as the semiconductor layer 10b.

[0029] When the length of the field plate electrode 18 between the gate electrode 14 and the drain electrode 16 (i.e., the distance L2) is increased, the electric field in the semiconductor layer 10b is relaxed and the number of electrons captured in the traps is reduced. This reduces the drift of the drain current. However, when the distance L2 is increased, the distance between the field plate electrode 18 and the drain electrode 16 is shortened and the source-drain capacitance Cds is increased. This deteriorates the high-frequency characteristics of the semiconductor device.

[0030] Thus, in Comparative Example 1, when the length L1 and the distance L2 are increased, the drift of the drain current is suppressed but Cds increases and the high-frequency characteristics deteriorate. When the length L1 and the distance L2 are decreased, Cds decreases and the high-frequency characteristics improve but the drift of the drain current increases.

[0031] In order to reduce Cds, it is conceivable to increase the distance Lgd between the gate electrode 14 and the drain electrode 16. However, increasing the distance Lgd increases the drain resistance.

[0032] [Operation of Example 1] 1 are isothermal lines showing the temperature distribution when the semiconductor device 100 is operated. The dashed line 52 is a higher temperature than the dashed line 50. Of the unit FETs 30a to 30h, the unit FET 30h closest to the center 40 has the highest temperature, and the unit FET 30a closest to the end 42 in the X direction of the unit FETs 30a to 30h has the lowest temperature. The temperatures of the unit FETs 30b to 30g decrease from the center 40 toward the end 42.

[0033] In the drift of the drain current, the time constant of the emission of electrons from the traps is faster as the temperature increases. Therefore, as the temperature increases, the drift of the drain current is alleviated. As a result, the drift of the drain current is small in the unit FET 30h close to the center 40, and large in the unit FET 30a close to the end 42.

[0034] In the unit FET 30h (first unit FET) having a high temperature, even if the distance L2H (first distance) is shortened, the drift of the drain current is small and can be within the allowable range of the drain current drift. On the other hand, in the unit FET 30a (second unit FET) having a low temperature, if the distance L2A (first distance) is shortened, the drift of the drain current becomes large and exceeds the allowable range of the drain current drift. Therefore, the distance L2H is made shorter than the distance L2A. As a result, in the unit FET 30h, the drift of the drain current can be within the allowable range and Cds can be made small. On the other hand, in the unit FET 30a, although Cds is large, the drift of the drain current can be made within the allowable range. As a result, the drift of the drain current is within the allowable range in both Example 1 and Comparative Example 1, and in Example 1, Cds can be suppressed and high-frequency characteristics can be improved as a whole semiconductor device compared to Comparative Example 1.

[0035] Moreover, in the X direction, a unit FET 30d (third unit FET) is provided between the unit FETs 30h and 30a. In the unit FET 30d, a distance L2D (third distance) is longer than the distance L2H and shorter than the distance L2A. This allows the unit FET 30d to keep the drift of the drain current within an acceptable range and reduce Cds. Therefore, in the entire semiconductor device, the drift of the drain current is kept within an acceptable range, Cds is suppressed, and high frequency characteristics are improved.

[0036] Cds is affected not only by the distance between the field plate electrode 18 and the drain electrode 16, but also by the length L1 of the field plate electrode 18 in the X direction. That is, as the length L1 increases, Cds increases. On the other hand, as the length L1 increases, the distance L2 increases, and the drift of the drain current is suppressed.

[0037] Therefore, the length L1H (first length) in the X direction of the field plate electrode 18 in the unit FET 30h is shorter than the length L1A (second length) in the X direction of the field plate electrode 18 in the unit FET 30a. This makes it possible to keep the drift of the drain current within an allowable range, suppress Cds in the entire semiconductor device, and improve the high-frequency characteristics.

[0038] In the unit FET 30d, the length L1D (third length) in the X direction of the field plate electrode 18 is shorter than the length L1A and longer than the length L1H, thereby keeping the drift of the drain current within an allowable range, suppressing Cds in the entire semiconductor device, and improving the high-frequency characteristics.

[0039] In order to suppress Cds, the distance L2H of the unit FET 30h closest to the center 40 can be set to 0.9 times or less, 0.8 times or less, or 0.7 times or less of the distance L2A of the unit FET 30a closest to the end 42. The length L1H of the unit FET 30h closest to the center 40 can be set to 0.9 times or less, 0.8 times or less, or 0.7 times or less of the length L1A of the unit FET 30a closest to the end 42. The distance L2H and the length L1H of the unit FET 30h may be zero. That is, the unit FET 30h does not need to be provided with a field plate electrode 18.

[0040] [Modification 1 of Example 1] FIG. 7 is a diagram showing the length L1 and distance L2 of each unit FET in the first modified example of the first embodiment. As shown in FIG. 7, for example, the lengths L1H of the unit FETs 30e to 30h in the group 54 including the center 40 are approximately the same as the manufacturing error, and the distances L2H are approximately the same as the manufacturing error. The lengths L1A of the unit FETs 30a to 30d in the group 56 including the end 42 are approximately the same as the manufacturing error, and the distances L2A are approximately the same as the manufacturing error. As in the first modified example of the first embodiment, the unit FETs 30a to 30h are divided into a plurality of groups 54 and 56, and the lengths L1 and distances L2 may be approximately the same in each of the groups 54 and 56. The number of groups 54 and 56 may be three or more.

[0041] Of the unit FETs 30a to 30h, the unit FET with the highest temperature is the unit FET 30h that is closest to the center 40. Therefore, as in the first embodiment and its first modified example, the distance L2H in the unit FET 30h that is closest to the center 40 among the unit FETs 30a to 30h can be made the shortest among the distances L2 of the unit FETs 30a to 30h. This can improve the high frequency characteristics.

[0042] Of the unit FETs 30a to 30h, the unit FET with the lowest temperature is the unit FET 30a closest to the end. Therefore, as in the first embodiment and its first modified example, the distance L2A in the unit FET 30a closest to the end 42 of the unit FETs 30a to 30h can be made the longest of the distances L2 of the unit FETs 30a to 30h. This can improve the high frequency characteristics.

[0043] As in the first embodiment, the length L1 may be gradually shortened and the distance L2 may be gradually shortened from the end 42 to the center 40. As in FIG. 5, the length L1 and the distance L2 may change linearly with respect to X. The length L1 and the distance L2 may change curvedly with respect to X. As in the first modification of the first embodiment, the length L1 may be shortened in a stepwise manner and the distance L2 may be shortened in a stepwise manner from the end 42 to the center 40. Furthermore, the length L1 and the distance L2 may each be symmetrical in the X direction with respect to the center 40, or each may be asymmetrical in the X direction with respect to the center 40.

[0044] [Example 2] Fig. 8 is a plan view of unit FETs 30a, 30d and 30h in Example 2. Fig. 9 is a diagram showing the length L1 and distance L2 in each unit FET in Example 2.

[0045] 8, in unit FETs 30a to 30h, the center and end in the Y direction are denoted by 44 and 46, respectively. The positive end 46 in the Y direction is the end of the drain electrode 16, and the negative end 46 in the Y direction is the end of the source electrode 12 or the active region 11. The center 44 is the center in the Y direction of both ends 46.

[0046] A region including a center 44 of the field plate electrode 18 in the Y direction is defined as a central portion 18a. A region including an end 46 of the field plate electrode 18 in the Y direction is defined as an end 18b. As shown in FIG. 9, in the unit FETs 30a to 30h, a length L10b at the end 46 is longer than a length L10a at the center 44. In the unit FETs 30a to 30h, a distance L20b at the end 46 is longer than a distance L20a at the center 44. The lengths L10a in the unit FETs 30a to 30h are approximately the same as each other within a manufacturing error, the lengths L10b in the unit FETs 30a to 30h are approximately the same as each other within a manufacturing error, the distances L20a in the unit FETs 30a to 30h are approximately the same as each other within a manufacturing error, and the distances L20b in the unit FETs 30a to 30h are approximately the same as each other within a manufacturing error.

[0047] 8, within the range of the central portion 18a, the length L10a is approximately the same as the manufacturing error, and the distance L20a is approximately the same as the manufacturing error. At the end portion 18b between the central portion 18a and the end 46, the length L10 gradually becomes longer from the central portion 18a toward the end 46, and the distance L20 gradually becomes longer from the central portion 18a toward the end 46. The other configurations are the same as those of the first embodiment, and therefore description thereof will be omitted.

[0048] [Operation of Example 2] 1, when the semiconductor device 100 is operated, in each of the unit FETs 30a to 30h, the temperature is highest at the center 44 in the Y direction and the temperature is lowest at the end 46 in the Y direction. The temperature decreases from the center 44 to the end 46.

[0049] Therefore, in at least one of the unit FETs 30a to 30h, the distance L20a (first distance) at the center 44 in the Y direction is made shorter than the distance L20b (second distance) at the end 46 in the Y direction. Also, the length L10a at the center 44 is made shorter than the length L10b at the end 46. As a result, since the distance L20a is short at the center 44 where the temperature is high, the drift of the drain current is within the allowable range and Cds can be reduced. At the end 46, since the distance L20b is long, the drift of the drain current can be kept within the allowable range even at a low temperature. As a result, the drift of the drain current is kept within the allowable range, and Cds can be suppressed and the high frequency characteristics can be improved for the entire semiconductor device.

[0050] Of the unit FETs 30a to 30h, the unit FETs closer to the center 40 tend to have a larger temperature distribution in the Y direction. Therefore, of the unit FETs 30a to 30h, the distance L20a at least at the center 44 of the unit FET 30h can be made shorter than the distance L20b at the end 46 of the unit FET 30h.

[0051] In the unit FET 30h, L20b-L20a may be set to 0.05 times or more, 0.1 times or more, or 0.2 times or more of the distance L20b. L10b-L10a may be set to 0.05 times or more, 0.1 times or more, or 0.2 times or more of the length L10b.

[0052] [Example 3] Fig. 10 is a plan view of unit FETs 30a, 30d and 30h in Example 3. Fig. 11 is a diagram showing the length L1 and distance L2 in each unit FET in Example 3.

[0053] 10, the length L1 of the center 44 in the Y direction of the unit FETs 30a, 30d, and 30h is L1Aa, L1Da, and L1Ha, respectively. The distance L2 of the center 44 in the Y direction of the unit FETs 30a, 30d, and 30h is L2Aa, L2Da, and L2Ha, respectively. The length L1 of the end 46 in the Y direction of the unit FETs 30a, 30d, and 30h is L1Ab, L1Db, and L1Hb, respectively. The distance L2 of the end 46 in the Y direction of the unit FETs 30a, 30d, and 30h is L2Ab, L2Db, and L2Hb, respectively.

[0054] L1Aa <L1Ab、L2Aa<L2Ab、L1Da<L1Db、L2Da<L2Db、L1Ha<L1HbおよびL2Ha<L2Hbであり、かつ、L1Aa> L1Da>L1Ha, L1Ab>L1Db>L1Hb, L2Aa>L2Da>L2Ha and L2Ab>L2Db>L2Hb.

[0055] As shown in Fig. 11, in the unit FETs 30a to 30h, the length L1 at the end 46 (see Fig. 10) is longer than the length L1 at the center 44 (see Fig. 10). In the unit FETs 30a to 30h, the distance L2 at the end 46 is longer than the distance L2 at the center 44. The length L1 and the distance L2 at the center 44 become shorter from the end 42 toward the center 40. The length L1 and the distance L2 at the end 46 become shorter from the end 42 toward the center 40. The other configurations are the same as those in the second embodiment, and therefore description thereof will be omitted.

[0056] [Operation of Example 3] As shown in FIG. 1, when the semiconductor device 100 is operated, the temperatures at the centers 40 and 44 of the unit FETs 30a to 30h are highest, and the temperatures decrease from the center 40 to the edge 42 and from the center 44 to the edge 46.

[0057] Therefore, the distances L2Ha and L2Hb in the unit FET 30h are made shorter than the distances L2Aa and L2Ab in the unit FET 30a, respectively, and the distance L2Ha is made shorter than the distance L2Hb in the unit FET 30h. As a result, in the centers 40 and 44 where the temperature is high, the distance L2Ha is short, so the drift of the drain current is within the allowable range and Cds can be reduced. At the ends 42 and 46, the distance L2Aa is long, so the drift of the drain current can be within the allowable range even at a low temperature. As a result, the drift of the drain current is within the allowable range, and Cds can be suppressed and the high frequency characteristics can be improved for the entire semiconductor device. In the unit FET 30a as well, the distance L2Aa may be shorter than the distance L2Ab.

[0058] Of the unit FETs 30a to 30h, the unit FETs closer to the center 40 tend to have a larger temperature distribution in the Y direction. Therefore, of the unit FETs 30a to 30h, the distance L1Ha at the center 44 of at least the unit FET 30h can be made shorter than the distance L1Hb at the end 46 of the unit FET 30h.

[0059] The lengths L1Ha and L1Hb in the unit FET 30h may be shorter than the lengths L1Aa and L1Ab in the unit FET 30a, respectively, and the length L1Ha may be shorter than the length L1Hb in the unit FET 30h. Also in the unit FET 30a, the length L1Aa may be shorter than the length L1Ab.

[0060] 1, the temperature of the unit FETs 30a to 30h is relatively constant near the center in the Y direction, and the temperature drops sharply toward the end 46. Thus, the length L1 and distance L2 in the central portion 18a, which includes the center 40 and has a constant width in the Y direction, can be made constant, and the length L1 and distance L2 at the end 18b can be gradually increased from the central portion 18a toward the end 46. The width in the Y direction of the central portion 18a is, for example, 0.1 to 0.9 times the gate width of the unit FETs 30a to 30h, or 0.3 to 0.6 times the gate width of the unit FETs 30a to 30h.

[0061] In the second and third embodiments, the length L1 and the distance L2 of the end 18b linearly increase from the central portion 18a toward the end 46, but they may also increase in a curved manner. Furthermore, the length L1 at the end 18b may be constant at any position in the Y direction, and the distance L2 may be constant at any position in the Y direction. There may be no central portion 18a having a constant length L1 and distance L2 in the Y direction, and the length L1 and the distance L2 may gradually increase from the center 44 toward the end 46. Furthermore, the length L1 and the distance L2 may each be symmetrical in the Y direction with respect to the center 44, or each may be asymmetrical in the Y direction with respect to the center 44.

[0062] In the first to third embodiments, in the unit FETs 30a to 30h, the field plate electrode 18 is electrically shorted to the source electrode 12. This makes it possible to further suppress electric field concentration in the semiconductor layer 10b between the gate electrode 14 and the drain electrode 16.

[0063] In the unit FETs 30a to 30h, the field plate electrode 18 does not necessarily have to be provided above the gate electrode 14. By providing the field plate electrode 18 above the gate electrode 14 with the insulating film 25a therebetween, the parasitic capacitance between the gate electrode 14 and the drain electrode 16 can be suppressed.

[0064] The drift of the drain current is likely to occur when the semiconductor layer 10b is a nitride semiconductor layer. Therefore, when the semiconductor layer 10b is a nitride semiconductor layer, the length L1 and the distance L2 can be made different as in the first to third embodiments.

[0065] The drift of the drain current is likely to occur when the semiconductor layer 10b has a gallium nitride channel layer and an aluminum gallium nitride barrier layer. Therefore, when the semiconductor layer 10b has a gallium nitride channel layer and an aluminum gallium nitride barrier layer, the length L1 and the distance L2 can be made different as in the first to third embodiments.

[0066] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0067] 10, 10a Board 10b Semiconductor layer 10c Channel Layer 10d Barrier layer 11 Active area 12 Source electrode 13 Inactive region 14 Gate electrode 15 Wiring 16 Drain electrode 18 Field plate electrode 18a central part 18b End 22 Via Hole 24 Gate bus bar 25, 25a, 25b Insulating film 26 Drain busbar 28, 28a metal layer 30a to 30h unit FET 40, 44 center 42, 46 end 50, 52 dashed line Groups 54 and 56 100 Semiconductor device

Claims

1. A substrate; a compound semiconductor layer provided on the substrate; a plurality of unit FETs arranged in a second direction intersecting the first direction, each unit FET including: a source electrode provided on the compound semiconductor layer and extending in a first direction; a drain electrode provided on the compound semiconductor layer and extending in the first direction; a gate electrode provided on the compound semiconductor layer and extending in the first direction, the gate electrode being sandwiched between the source electrode and the drain electrode; and a field plate electrode provided above the compound semiconductor layer between the gate electrode and the drain electrode with an insulating film sandwiched therebetween; Equipped with The plurality of unit FETs include A first unit FET; a second unit FET that is closer to an end of the plurality of unit FETs in the second direction than the first unit FET; having a first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the first unit FET is shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the second unit FET.

2. 2. The semiconductor device according to claim 1, wherein a distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in a unit FET among the plurality of unit FETs that is closest to a center of the plurality of unit FETs in the second direction is the shortest among distances in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode in the plurality of unit FETs.

3. 3. The semiconductor device according to claim 1, wherein a distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in a unit FET among the plurality of unit FETs that is closest to an end of the plurality of unit FETs in the second direction is the longest among distances in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode in the plurality of unit FETs.

4. 3 . The semiconductor device according to claim 1 , wherein the first distance at a center of the first unit FET in the first direction is shorter than the first distance at an end of the first unit FET in the first direction.

5. The plurality of unit FETs include a third unit FET provided between the first unit FET and the second unit FET in the second direction, 3. The semiconductor device according to claim 1, wherein in the third unit FET, a third distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode is longer than the first distance and shorter than the second distance.

6. 3 . The semiconductor device according to claim 1 , wherein a first length in the second direction of the field plate electrode in the first unit FET is shorter than a second length in the second direction of the field plate electrode in the second unit FET.

7. A substrate; a compound semiconductor layer provided on the substrate; a plurality of unit FETs arranged in a second direction intersecting the first direction, each unit FET including: a source electrode provided on the compound semiconductor layer and extending in a first direction; a drain electrode provided on the compound semiconductor layer and extending in the first direction; a gate electrode provided on the compound semiconductor layer and extending in the first direction, the gate electrode being sandwiched between the source electrode and the drain electrode; and a field plate electrode provided above the compound semiconductor layer between the gate electrode and the drain electrode with an insulating film sandwiched therebetween; Equipped with a semiconductor device in which, in at least one unit FET among the plurality of unit FETs, a first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at a center in the first direction of the at least one unit FET is shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at an end in the first direction of the at least one unit FET.

8. 8. The semiconductor device according to claim 7, wherein in the at least one unit FET, in a central portion including the center in the first direction and having a constant width in the first direction, a distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode is constant, and a distance in the second direction between the end of the gate electrode closer to the drain electrode and the end of the field plate electrode closer to the drain electrode gradually increases from the central portion toward the end in the first direction.

9. 8. The semiconductor device according to claim 1, wherein the field plate electrode of each of the unit FETs is electrically short-circuited to the source electrode.

10. 8. The semiconductor device according to claim 1, wherein the compound semiconductor layer is a nitride semiconductor layer.

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