Da conversion device

Abstract

To reduce the number of circuit elements while assuring required DA conversion accuracy and resolution.SOLUTION: A DA conversion device includes DA converters for performing DA conversion for a plurality of channels, and a control circuit. Each DA converter includes a ladder resistance circuit for generating an analog conversion signal according to a digital input signal, and a signal output circuit for outputting an analog output signal based on the analog conversion signal. The control circuit selectively operates in a first state of causing a DA converter of a specific channel to perform m-bit DA conversion or a second state of causing the DA converter of the specific channel to perform n-bit DA conversion. Each of m and n represents integers of 2 or more, and n is larger than m. In the second state, the DA converter of the specific channel generates an analog conversion signal using ladder resistance circuit of the specific channel and a ladder resistance circuit of another channel.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present disclosure relates to a digital-to-analog converter. [Background technology]

[0002] DA conversion devices having a ladder resistor circuit (see, for example, Patent Document 1 below) are widely used. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-219263 A

[0004] [overview] It is important to reduce the number of circuit elements required to configure a DA conversion device while ensuring the required DA conversion accuracy and resolution.

[0005] A DA conversion device according to one embodiment of the present disclosure is a DA conversion device comprising DA converters for multiple channels configured to perform digital-to-analog conversion, and a control circuit, each DA converter having a ladder resistor circuit configured to generate an analog conversion signal corresponding to a digital input signal, and a signal output circuit configured to output an analog output signal based on the analog conversion signal, the control circuit selectively operates in a first state in which the DA converter of a specific channel performs m-bit digital-to-analog conversion, or in a second state in which the DA converter of the specific channel performs n-bit digital-to-analog conversion, m and n represent integers equal to or greater than 2, n being greater than m, and in the second state, the DA converter of the specific channel generates the analog conversion signal using the ladder resistor circuit of the specific channel and the ladder resistor circuits of other channels. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic configuration diagram of a DA conversion device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is an external perspective view of the DA conversion device according to the embodiment of the present disclosure. [Diagram 3] FIG. 3 is a structural diagram of a digital input signal according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a circuit diagram of a DA converter according to a basic configuration. [Diagram 5] FIG. 5 is a circuit diagram of a DA converter according to a basic configuration. [Figure 6] FIG. 6 is a circuit diagram of a two-channel DA converter according to a reference example. [Figure 7] FIG. 7 is a diagram showing a state of voltage application to a resistor group according to a reference example (first mode). [Figure 8] FIG. 8 is a diagram showing a state of voltage application to a resistor group according to a reference example (second mode). [Figure 9] FIG. 9 is a circuit diagram of a two-channel DA converter according to a first example of an embodiment of the present disclosure. [Figure 10] FIG. 10 relates to a first example belonging to an embodiment of the present disclosure and is a diagram showing a state of voltage application to a resistor group in an 8-bit conversion case of the first channel. [Figure 11] FIG. 11 relates to a first example belonging to an embodiment of the present disclosure and is a diagram showing a state of voltage application to a resistor group in an 8-bit conversion case of the second channel. [Figure 12] FIG. 12 relates to a first example belonging to an embodiment of the present disclosure and is a diagram showing a state of voltage application to a resistor group in a 10-bit conversion case of the first channel. [Figure 13] FIG. 13 is a diagram showing an equivalent circuit of a resistor group according to a first example of an embodiment of the present disclosure. [Figure 14] FIG. 14 relates to a first example belonging to an embodiment of the present disclosure and is a diagram showing a state of voltage application to a resistor group in a 10-bit conversion case of the first channel. [Figure 15] FIG. 15 is a circuit diagram of a two-channel DA converter according to a second example of the embodiment of the present disclosure. [Figure 16] FIG. 16 relates to a second example belonging to an embodiment of the present disclosure and is a diagram showing a state of voltage application to a resistor group in a 10-bit conversion case of the second channel. [Figure 17] FIG. 17 is a circuit diagram of a two-channel DA converter according to a third example of the embodiment of the present disclosure. [Figure 18] FIG. 18 is a diagram showing three states of the sample and hold circuit of the first channel according to a third example of the embodiment of the present disclosure. [Figure 19] FIG. 19 is a diagram showing three states of the sample and hold circuit of the second channel according to a third example of the embodiment of the present disclosure. [Figure 20] FIG. 20 is a diagram showing an example of combinations of states of the sample-and-hold circuits of the first and second channels according to a third example belonging to an embodiment of the present disclosure. [Figure 21] FIG. 21 is a diagram showing an internal configuration of a converter block according to a fourth example of the embodiment of the present disclosure.

[0007] [Detailed Description] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings, the same parts are given the same reference numerals, and duplicated descriptions of the same parts are generally omitted. In this specification, for the sake of simplicity, by writing a symbol or code referring to information, signal, physical quantity, functional part, circuit, element, or part, the name of the information, signal, physical quantity, functional part, circuit, element, or part corresponding to the symbol or code may be omitted or abbreviated.

[0008] First, some terms used in the description of the embodiments of the present disclosure will be explained. Ground refers to a reference conductive part having a reference potential of 0V (zero volts), or refers to the potential of 0V itself. The reference conductive part may be formed using a conductor such as a metal. The potential of 0V may also be called ground potential. In the embodiments of the present disclosure, a voltage shown without a particular reference represents a potential seen from the ground. Level refers to the level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level.

[0009] Any switch can be composed of one or more FETs (field effect transistors), and when a switch is in the on state, both ends of the switch are conductive, whereas when a switch is in the off state, both ends of the switch are non-conductive. Hereinafter, the on and off states of any switch may be simply expressed as on and off.

[0010] Unless otherwise specified, the connection between multiple parts that form a circuit, such as any circuit elements, wiring, nodes, etc., may be understood to refer to an electrical connection.

[0011] 1 shows a schematic configuration of a DA conversion device 1 according to an embodiment of the present disclosure. In this embodiment, "DA" is an abbreviation for "digital / analog." Therefore, the DA conversion device is a digital / analog conversion device.

[0012] The DA conversion device 1 comprises a converter block BLK equipped with DA converters 10 for multiple channels, and a control circuit 20 that controls the operation of the DA converters 10 for each channel. The total number of DA converters 10 provided in the DA conversion device 1 (i.e., the number of channels of the DA converters 10) is any number equal to or greater than two. The DA converter 10 for the i-th channel is particularly represented by the symbol "10[i]", where i represents any integer.

[0013] FIG. 2 is an external perspective view of the DA conversion device 1. The DA conversion device 1 is an electronic component (semiconductor device) including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a case (package) for accommodating the semiconductor chip, and a plurality of external terminals exposed from the case to the outside of the DA conversion device 1. The DA conversion device 1 is formed by sealing the semiconductor chip in a case (package) made of resin. Note that the number of external terminals of the DA conversion device 1 and the type of case for the DA conversion device 1 shown in FIG. 2 are merely examples, and can be designed arbitrarily. A converter block BLK and a control circuit 20 are provided on the semiconductor chip.

[0014] FIG. 1 also shows an MPU (Micro Processing Unit) 2 provided outside the DA conversion device 1. The DA conversion device 1 and the MPU 2 are connected via a communication line. The MPU 2 transmits a command signal to the DA conversion device 1 via the communication line. The control circuit 20 has a communication interface circuit (not shown) and receives a command signal 30 from the MPU 2. The command signal includes a digital input signal, and the command signal instructs DA conversion (digital-to-analog conversion) of the digital input signal. The control circuit 20 converts the digital input signal in the command signal into an analog signal in the DA converter 10 of one of the channels according to the instruction of the command signal. DA conversion refers to the operation of converting a digital input signal into an analog signal. The DA converter 10 that has performed the DA conversion outputs the analog signal obtained by the DA conversion as an analog output signal Aout. The analog output signal Aout is supplied to an arbitrary external circuit different from the DA conversion device 1. The external circuit here may be the MPU 2 or a circuit other than the MPU 2. The analog output signal Aout of the DA converter 10[i] is specifically represented by the symbol "Aout[i]".

[0015] The command signal is transmitted from the MPU 2 to the DA conversion device 1 by serial communication. In this case, for example, the command signal is transmitted from the MPU 2 to the DA conversion device 1 by a three-wire serial interface using a data signal, a clock signal, and a chip select signal. The serial digital input signal may be converted into a parallel digital input signal by using a shift register (not shown) provided in the control circuit 20. The command signal may be transmitted from the MPU 2 to the DA conversion device 1 by parallel communication. Also, bidirectional communication may be possible between the DA conversion device 1 and the MPU 2.

[0016] The digital input signal included in the command signal is called the digital input signal Din. Figure 3 shows the structure of the digital input signal Din. The digital input signal Din is an L-bit digital signal, where L is an integer value of 2 or more. The digital input signal Din is composed of the 1st to Lth bits, and the i-th bit in the digital input signal Din is called bit B[i-1]. That is, the digital input signal Din is composed of bits B[0] to B[L-1]. Bit B[i] is the most significant bit of bit B[i-1]. Therefore, among bits B[0] to B[L-1], bit B[0] is the least significant bit, and bit B[L-1] is the most significant bit. Bits B[0] to B[L-1] each have one bit of data. The data in bit B[i] is called data d[i]. Data d[i] has a value of "0" or "1". The digital input signal Din is a digital value D expressed in binary. VAL For example, if “L=4”, then “D VAL =d[0]+2 1 d[1]+2 2 d[2]+2 3 d[3]” and the digital value D VAL takes an integer value from 0 to 15 in decimal notation.

[0017] The control circuit 20 can cause the DA converter 10[1] to perform DA conversion on the digital input signal Din based on the command signal. At this time, the result of converting the digital input signal Din into an analog signal is output from the DA converter 10[1] as the analog output signal Aout[1]. Similarly, the control circuit 20 can cause the DA converter 10[2] to perform DA conversion on the digital input signal Din based on the command signal. At this time, the result of converting the digital input signal Din into an analog signal is output from the DA converter 10[2] as the analog output signal Aout[2]. The plurality of external terminals provided in the DA conversion device 1 include a first output terminal from which the analog output signal Aout[1] is derived and a second output terminal from which the analog output signal Aout[2] is derived. When the converter block BLK is provided with DA converters 10 having 3 or more channels, the same applies to the DA converters 10 other than the DA converters 10[1] and 10[2].

[0018] Each channel's DA converter 10 includes a ladder resistor circuit that generates an analog conversion signal corresponding to the digital input signal Din, and a signal output circuit that outputs an analog output signal Aout based on the analog conversion signal. The ladder resistor circuit is composed of a plurality of resistors. As DA converters having a ladder resistor circuit, there are binary-type DA converters and decoder-type DA converters. In the binary method, a resistor group connected in an R2R method is provided in the ladder resistor circuit. The decoder method is sometimes referred to as the unary method or the segment method. In the DA converter 10 according to the present embodiment, a configuration combining the binary method and the decoder method is adopted in consideration of the balance between the conversion accuracy in DA conversion and the efficiency of the circuit area.

[0019] <<Basic Configuration of DA Converter>> Figure 4 shows the circuit diagram of the DA converter 10 according to the basic configuration REF1 is shown. The DA converter 10 REF1The DA converter 10 includes a resistor group 611 that employs a binary system (R2R system), a resistor group 612 that employs a decoder system, an output buffer 613, and a wiring 614 that is connected to the resistor groups 611 and 612 and the output buffer 613. REF1 is an 8-bit DA converter. An analog signal corresponding to an 8-bit digital input signal Din is generated on a line 614, and an output buffer 613 outputs the signal on the line 614 with low impedance as a result of the DA conversion.

[0020] Of the 8-bit digital input signal Din, voltages V[0] to V[4] corresponding to the lowest 5 bits of data d[0] to d[4] are supplied to a resistor group 611, and voltages V[0]' to V[6]' corresponding to the highest 3 bits of data d[5] to d[7] are supplied to a resistor group 612. The voltages V[0] to V[4] and V[0]' to V[6]' each have a high level or a low level (ground potential).

[0021] DA Converter 10 REF1 When the data d[0] is used, if the data d[0] is "1", the voltage V[0] has a high level, and if the data d[0] is "0", the voltage V[0] has a low level (ground potential). The same applies to the voltages V[1] to V[4]. REF1 When this is used, the levels of voltages V[0]' to V[6]' are determined by decoding the upper 3 bits of data d[5] to d[7]. Data d[5] to d[7] have integer values ​​greater than or equal to 0 and less than or equal to 7 in decimal notation. Of the total of 7 voltages V[0]' to V[6]', the number of voltages that are set to high level is equal to the number of data values ​​d[5] to d[7] in decimal notation.

[0022] DA Converter 10 REF1 In order to realize the above operation in the above, the resistor group 611 is made up of a total of 16 unit resistors, and the resistor group 613 is made up of a total of 7 unit resistors.

[0023] FIG. 5 shows the basic configuration of the DA converter 10. REF2 The circuit diagram of the DA converter 10 is shown below. REF2The DA converter 10 includes a resistor group 621 that employs a binary system (R2R system), a resistor group 622 that employs a decoder system, an output buffer 623, and a wiring 624 that is connected to the resistor groups 621 and 622 and the output buffer 623. REF2 is a 10-bit DA converter. An analog signal corresponding to a 10-bit digital input signal Din is generated on a wiring 624, and an output buffer 623 outputs the signal on the wiring 624 with low impedance as a result of the DA conversion.

[0024] Of the 10-bit digital input signal Din, voltages V[0] to V[5] corresponding to the lowest 6 bits of data d[0] to d[5] are supplied to a resistor group 621, and voltages V[0]' to V

[14] ' corresponding to the highest 4 bits of data d[6] to d[9] are supplied to a resistor group 622. The voltages V[0] to V[5] and V[0]' to V

[14] ' each have a high level or a low level (ground potential).

[0025] DA Converter 10 REF2 When the data d[0] is used, if the data d[0] is "1", the voltage V[0] has a high level, and if the data d[0] is "0", the voltage V[0] has a low level (ground potential). The same applies to the voltages V[1] to V[5]. REF2 When this is used, the levels of voltages V[0]' to V

[14] ' are determined by decoding the upper 4 bits of data d[6] to d[9]. Data d[6] to d[9] have integer values ​​greater than or equal to 0 and less than or equal to 15 in decimal notation. Of the total of 15 voltages V[0]' to V

[14] ', the number of voltages that are set to high level is equal to the number of values ​​of data d[6] to d[9] in decimal notation.

[0026] DA Converter 10 REF2 In order to realize the above operation in the above, the resistor group 611 is made up of a total of 19 unit resistors, and the resistor group 613 is made up of a total of 16 unit resistors.

[0027] That is, the DA converter 10 in FIG. REF1Based on this, we added three unit resistors to the binary resistor group and eight unit resistors to the decoder resistor group, resulting in a 10-V DAC in Figure 5. REF2 5, the three unit resistors within a dashed frame 621add correspond to the additions to the resistor group in the binary system, and the eight unit resistors within a dashed frame 622add correspond to the additions to the resistor group in the decoder system.

[0028] In general terms, the following can be said. When adding a unit resistor to a resistor group using the binary method to expand (increase) the number of bits of the DA converter by one, the number of additional unit resistors required is three. When adding a unit resistor to a resistor group using the decoder method to expand (increase) the number of bits of the DA converter by one, the number of additional unit resistors required is two. k-1 Here, k is the number of bits assigned to the resistor group of the decoder type in the expanded DA converter. For example, in the DA converter 10 of FIG. REF1 The DA converter 10 in Figure 5 REF2 When expanding to 10 DACs, REF2 In the above, the number of bits k assigned to the decoder resistor group 622 is 4. Therefore, the number of additional unit resistors required to expand the decoder resistor group 612 to the decoder resistor group 622 is “2 k-1 =2 4-1 =8”, so the answer is 8.

[0029] <<Operation mode>> Here, we will explain the operation modes of the DA conversion device 1. The DA conversion device 1 is configured to be able to operate in any one of a plurality of operation modes. The plurality of operation modes may be configured with three or more operation modes, but here, we will focus on two operation modes included in the plurality of operation modes, a first mode and a second mode.

[0030] In the first mode, each of the DA converters 10[1] and 10[2] performs m-bit DA conversion. In the second mode, only one of the DA converters 10[1] and 10[2] performs n-bit DA conversion, and the other DA converter does not perform DA conversion. In the following, unless otherwise specified, in the second mode, only the DA converter 10[1] of the DA converters 10[1] and 10[2] performs DA conversion. That is, in the second mode, only the DA converter 10[1] of the DA converters 10[1] and 10[2] performs DA conversion. m and n each represent an integer of 2 or more, and n is greater than m.

[0031] m-bit DA conversion refers to the operation of converting an m-bit digital input signal Din into an analog signal and outputting the analog signal obtained by conversion as an analog output signal Aout. n-bit DA conversion refers to the operation of converting an n-bit digital input signal Din into an analog signal and outputting the analog signal obtained by conversion as an analog output signal Aout.

[0032] In the first mode, the control circuit 20 controls the operation of each of the DA converters 10[1] and 10[2] based on a command signal so that m-bit DA conversion is performed in each of the DA converters 10[1] and 10[2]. The m-bit DA conversion by the DA converter 10[1] and the m-bit DA conversion by the DA converter 10[2] may be performed simultaneously or at different times. In the second mode, the control circuit 20 controls the operation of the DA converter 10[1] based on a command signal so that n-bit DA conversion is performed in the DA converter 10[1].

[0033] In the first mode, when m-bit DA conversion is performed by the DA converter 10[1], "L=m" (see Figure 3), the m-bit digital input signal Din included in the command signal is DA converted by the DA converter 10[1], and an analog output signal Aout[1] indicating the result of the DA conversion by the DA converter 10[1] is generated. Similarly, in the first mode, when m-bit DA conversion is performed by the DA converter 10[2], "L=m", and the L-bit digital input signal Din included in the command signal is DA converted by the DA converter 10[2], and an analog output signal Aout[2] indicating the result of the DA conversion by the DA converter 10[2] is generated.

[0034] In the second mode, when n-bit DA conversion is performed by the DA converter 10[1], "L=n" (see Figure 3), the n-bit digital input signal Din included in the command signal is DA converted by the DA converter 10[1], and an analog output signal Aout[1] indicating the result of the DA conversion by the DA converter 10[1] is generated.

[0035] In the following, for the sake of concreteness of explanation, an example will be taken in which "m=8" and "n=10".

[0036] <<Reference example>> FIG. 6 shows a DA converter 10 according to a reference example. REF3 and 10 REF4 The circuit diagram of the DA converter 10 is shown below. REF3 and 10 REF4 are DA converters 10[1] and 10[2] according to a reference example.

[0037] DA Converter 10 REF3 The DA converter 10 includes a resistor group 631 that employs a binary system (R2R system), a resistor group 632 that employs a decoder system, an output buffer 633, and a wiring 634 that is connected to the resistor groups 631 and 632 and the output buffer 633. REF3 In order to perform a maximum of 10-bit DA conversion in the DA converter 10, the resistor group 631 has 19 unit resistors and the resistor group 632 has 15 unit resistors. REF4 The DA converter 10 includes a resistor group 641 that employs a binary system (R2R system), a resistor group 642 that employs a decoder system, an output buffer 643, and a wiring 644 that is connected to the resistor groups 641 and 642 and the output buffer 643. REF4In order to perform 8-bit DA conversion in the DA converter 10, the resistor group 641 has 16 unit resistors and the resistor group 642 has 7 unit resistors. REF3 and 10 REF4 There are a total of 57 unit resistors.

[0038] The DA converter 10 is designed to perform 8-bit DA conversion in the first mode and 10-bit DA conversion in the second mode. REF3 6, the three unit resistors within the dashed frame 631add are added to the resistor group 631, and the eight unit resistors within the dashed frame 632add are added to the resistor group 632.

[0039] FIG. 7 shows the DA converter 10 in the first mode. REF3 and 10 REF4 The figure shows the voltage application state of the DA converter 10 in the first mode. REF3 When performing DA conversion, an analog signal corresponding to an 8-bit digital input signal Din is generated on a wiring 634, and an output buffer 633 outputs the signal on the wiring 634 with low impedance as a result signal of the DA conversion. At this time, voltages V[0] to V[4] corresponding to the lower 5-bit data d[0] to d[4] of the 8-bit digital input signal Din are supplied to a part of a resistor group 631, and voltages V[0]' to V[6]' corresponding to the upper 3-bit data d[5] to d[7] are supplied to a part of a resistor group 632. Here, the part of the resistor group 631 refers to the resistor group outside the dashed frame 631add of the resistor group 631, and the part of the resistor group 632 refers to the resistor group outside the dashed frame 632add of the resistor group 632.

[0040] In the first mode, the DA converter 10 REF4When performing DA conversion, an analog signal corresponding to the 8-bit digital input signal Din is generated on a wiring 644, and an output buffer 643 outputs the signal on the wiring 644 with low impedance as a result signal of the DA conversion. At this time, voltages V[0] to V[4] corresponding to the lower 5 bits of data d[0] to d[4] of the 8-bit digital input signal Din are supplied to a resistor group 641, and voltages V[0]' to V[6]' corresponding to the upper 3 bits of data d[5] to d[7] are supplied to a resistor group 642.

[0041] FIG. 8 shows the DA converter 10 in the second mode. REF3 The figure shows the voltage application state of the DA converter 10 in the second mode. REF3 When performing DA conversion, an analog signal corresponding to the 10-bit digital input signal Din is generated on a wiring 634, and the output buffer 633 outputs the signal on the wiring 634 with low impedance as a result signal of the DA conversion. At this time, voltages V[0] to V[5] corresponding to the lower 6 bits of data d[0] to d[5] of the 10-bit digital input signal Din are supplied to a resistor group 631, and voltages V[0]' to V

[14] ' corresponding to the upper 4 bits of data d[6] to d[9] are supplied to a resistor group 632.

[0042] As described above, the DA converter 10 according to the reference example REF3 and 10 REF4 In this case, a total of 57 unit resistors are required. The technology that enables the reduction in the number of unit resistors or related technologies will be described in the following several examples. The matters described above in this embodiment are applied to the following respective examples (excluding matters related to the reference example) unless otherwise specified and unless there is a contradiction. In the respective examples, if there is a matter that contradicts the matters described above, the description in each example may take precedence. Furthermore, unless there is a contradiction, matters described in any of the following several examples can also be applied to any other example (i.e., any two or more of the multiple examples can be combined).

[0043] <<First Example>> A first embodiment will be described. Fig. 9 is a circuit diagram of DA converters 10A and 10B according to the first embodiment. In the first embodiment, the DA converters 10A and 10B in Fig. 9 are used as DA converters 10[1] and 10[2], respectively.

[0044] The DA converter 10A includes a resistor group 111 that employs a binary system (R2R system), a resistor group 112 that employs a decoder system, a signal output circuit 113, and wiring (conversion wiring) 114. The resistor groups 111 and 112 form a ladder resistor circuit in the DA converter 10A. The ladder resistor circuit (111, 112) in the DA converter 10A is a ladder resistor circuit of the first channel.

[0045] The DA converter 10B includes a resistor group 121 that employs a binary system (R2R system), a resistor group 122 that employs a decoder system, a signal output circuit 123, and wiring (conversion wiring) 124. The resistor groups 121 and 122 form a ladder resistor circuit in the DA converter 10B. The ladder resistor circuit (121, 122) in the DA converter 10B is a ladder resistor circuit of the second channel.

[0046] The converter block BLK (see FIG. 1) also includes a switch SW inserted between the wiring 114 and 124. The switch SW may be an analog switch capable of propagating an analog signal. A first end of the switch SW is connected to the wiring 114, and a second end of the switch SW is connected to the wiring 124. Thus, when the switch SW is on, the wiring 114 and 124 are connected to each other through the switch SW. When the switch SW is off, the wiring 114 and 124 are not connected to each other. When the wiring 114 and 124 are not connected to each other, the ladder resistor circuit (111, 112) of the DA converter 10A and the ladder resistor circuit (121, 122) of the DA converter 10B are not connected to each other.

[0047] The resistor group 111 includes unit resistors R10 to R16, R20 to R25, and R30 to R35. The resistor group 112 includes unit resistors R40 to R46. The resistor group 121 includes unit resistors R60, R61, R63 to R66, R71 to R75, and R81 to R85. The resistor group 122 includes unit resistors R90 to R96. All the unit resistors included in the resistor groups 111, 112, 121, and 122 have the same resistance value (however, there may be an error). Hereinafter, the unit resistors may be abbreviated to simply resistors.

[0048] The connections of the components of the DA converter 10A will be described. A first terminal of the resistor R10 is connected to ground. A second terminal of the resistor R10 is connected to a first terminal of the resistor R11. A second end of the resistor R11 and a first end of the resistor R12 are connected to a node N20. A second end of the resistor R12 and a first end of the resistor R13 are connected to a node N21. A second end of the resistor R13 and a first end of the resistor R14 are connected to a node N22. A second end of the resistor R14 and a first end of the resistor R15 are connected to a node N23. A second end of the resistor R15 and a first end of the resistor R16 are connected to a node N24. The second end of the resistor R16 is connected to a node N25. The node N25 is connected to the wiring 114.

[0049] A first end of resistor R20, a first end of resistor R21, a first end of resistor R22, a first end of resistor R23, a first end of resistor R24, and a first end of resistor R25 are connected to nodes N20, N21, N22, N23, N24, and N25, respectively. The second end of resistor R20, the second end of resistor R21, the second end of resistor R22, the second end of resistor R23, the second end of resistor R24, and the second end of resistor R25 are connected to a first end of resistor R30, a first end of resistor R31, a first end of resistor R32, a first end of resistor R33, a first end of resistor R34, and a first end of resistor R35, respectively. The second end of resistor R30, the second end of resistor R31, the second end of resistor R32, the second end of resistor R33, the second end of resistor R34, and the second end of resistor R35 are connected to nodes N30, N31, N32, N33, N34, and N35, respectively.

[0050] The first terminals of the resistors R40 to R46 are commonly connected to the wiring 114. The second terminal of the resistor R40, the second terminal of the resistor R41, the second terminal of the resistor R42, the second terminal of the resistor R43, the second terminal of the resistor R44, the second terminal of the resistor R45, and the second terminal of the resistor R46 are connected to nodes N40, N41, N42, N43, N44, N45, and N46, respectively. When the switch SW is on, each resistor in the resistor group 122 is also connected to the wiring 114 via the switch SW, but the first terminals of the resistors R40 to R46 are directly connected to the wiring 114 without going through the switch SW (the node N25 is also directly connected to the wiring 114 without going through the switch SW).

[0051] The signal output circuit 113 is composed of an operational amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal. In the operational amplifier in the signal output circuit 113, the non-inverting input terminal is connected to the wiring 114 (specifically, directly connected to the wiring 114 without going through a switch SW), and the inverting input terminal and the output terminal are shorted to each other. Therefore, the operational amplifier in the signal output circuit 113 functions as a voltage follower, and outputs the signal in the wiring 114 from its own output terminal with a sufficiently low output impedance. In the first and second modes, an analog output signal Aout[1] (see FIG. 1) is output from the output terminal of the operational amplifier in the signal output circuit 113.

[0052] The connections of the components of the DA converter 10B will be described. A first terminal of the resistor R60 is connected to ground. A second terminal of the resistor R60 is connected to a first terminal of the resistor R61. A second end of the resistor R61 and a first end of the resistor R63 are connected to a node N71. A second end of the resistor R63 and a first end of the resistor R64 are connected to a node N72. A second end of the resistor R64 and a first end of the resistor R65 are connected to a node N73. A second end of resistor R65 and a first end of resistor R66 are connected to a node N74. The second end of the resistor R66 is connected to a node N75. The node N75 is connected to the wiring 124.

[0053] A first end of the resistor R71, a first end of the resistor R72, a first end of the resistor R73, a first end of the resistor R74, and a first end of the resistor R75 are connected to nodes N71, N72, N73, N74, and N75, respectively. The second terminal of resistor R71, the second terminal of resistor R72, the second terminal of resistor R73, the second terminal of resistor R74, and the second terminal of resistor R75 are connected to a first terminal of resistor R81, a first terminal of resistor R82, a first terminal of resistor R83, a first terminal of resistor R84, and a first terminal of resistor R85, respectively. A second end of the resistor R81, a second end of the resistor R82, a second end of the resistor R83, a second end of the resistor R84, and a second end of the resistor R85 are connected to nodes N81, N82, N83, N84, and N85, respectively.

[0054] The first terminals of the resistors R90 to R96 are commonly connected to the wiring 124. The second terminal of the resistor R90, the second terminal of the resistor R91, the second terminal of the resistor R92, the second terminal of the resistor R93, the second terminal of the resistor R94, the second terminal of the resistor R95, and the second terminal of the resistor R96 are connected to nodes N90, N91, N92, N93, N94, N95, and N96, respectively. When the switch SW is on, each resistor in the resistor group 112 is also connected to the wiring 124 via the switch SW, but the first terminals of the resistors R90 to R96 are directly connected to the wiring 124 without going through the switch SW (the node N75 is also directly connected to the wiring 124 without going through the switch SW).

[0055] The signal output circuit 123 is composed of an operational amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal. In the operational amplifier in the signal output circuit 123, the non-inverting input terminal is connected to the wiring 124 (specifically, directly connected to the wiring 124 without going through a switch SW), and the inverting input terminal and the output terminal are shorted to each other. Therefore, the operational amplifier in the signal output circuit 123 functions as a voltage follower, and outputs the signal on the wiring 124 from its own output terminal with a sufficiently low output impedance. In the first mode, an analog output signal Aout[2] (see FIG. 1) is output from the output terminal of the operational amplifier in the signal output circuit 123.

[0056] The control circuit 20 supplies low-level voltages V L or high level voltage V H Selectively supplies the low-level voltage V L has ground potential. High-level voltage V H is the low-level voltage V L The DA conversion device 1 receives a power supply voltage VCC from an external power supply device (not shown) and operates based on the power supply voltage VCC. H Alternatively, an internal power supply voltage generated in the DA conversion device 1 based on the power supply voltage VCC may be a high-level voltage V H It may be.

[0057] --- 8-bit conversion case of the first channel --- 10 shows the voltage application state in the case where 8-bit DA conversion is performed by the DA converter 10A in the first mode (hereinafter referred to as the 8-bit conversion case of the first channel). In the first mode, the switch SW is off. In the first mode, the control circuit 20 fixes the potential of the node 30 to the ground potential (i.e., fixes the voltage of the node 30 to the low-level voltage V L The digital input signal Din in the 8-bit conversion case of the first channel is specifically referred to as the first digital input signal Din.

[0058] In the 8-bit conversion case of the first channel, the control circuit 20 supplies voltages V[0] to V[4] corresponding to the lowest 5 bits of data d[0] to d[4] of the 8-bit first digital input signal Din to the resistor group 111, and supplies voltages V[0]' to V[6]' corresponding to the highest 3 bits of data d[5] to d[7] to the resistor group 112. In the 8-bit conversion case of the first channel, the voltages V[0] to V[4] are supplied to the nodes N31 to N35, respectively, and the voltages V[0]' to V[6]' are supplied to the nodes N40 to N46, respectively.

[0059] In the 8-bit conversion case of the first channel, for each integer i satisfying “0≦i≦4”, if the data d[i] is “1”, the voltage V[i] is the high-level voltage V H If data d[i] is set to “0”, voltage V[i] is set to the low-level voltage V L is set to.

[0060] In the case of 8-bit conversion for the first channel, the control circuit 20 decodes the most significant 3 bits of data d[5] to d[7] to determine the level of the voltage V[0]' to V[6]' to be supplied to the resistor group 112. The data d[5] to d[7] have integer values ​​in decimal notation that are greater than or equal to 0 and less than or equal to 7. The value of the data d[5] to d[7] in decimal notation is represented by the value VAL[d[5]:d[7]].

[0061] Of the seven voltages V[0]' to V[6]', the high-level voltage V H , and the remaining (7-VAL[d[5]:d[7]]) voltages are set to the low-level voltage V L In detail, if "VAL[d[5]:d[7]]=0", the voltages V[0]' to V[6]' are all set to the low-level voltage V L If "VAL[d[5]:d[7]]=7", voltages V[0]' to V[6]' are all high-level voltages V HFor any integer j that satisfies "1≦j≦6", if "VAL[d[5]:d[7]]=j", the voltages V[0]' to V[j-1]' are set to the high-level voltage V H , while the voltages V[j]' to V[6]' are set to the low-level voltage V L is set to.

[0062] In the 8-bit conversion case of the first channel, the ladder resistor circuit (111, 112) of the first channel generates an analog conversion signal corresponding to an 8-bit first digital input signal Din on the wiring 114. The analog conversion signal generated on the wiring 114 is obtained by converting the first digital input signal Din into an analog voltage signal with 8-bit resolution, and varies according to the first digital input signal Din. In the 8-bit conversion case of the first channel, the signal output circuit 113 performs impedance conversion of the analog conversion signal generated on the wiring 114, and outputs the analog conversion signal after impedance conversion as the analog output signal Aout[1]. In the process of generating the analog output signal Aout[1] from the analog conversion signal generated on the wiring 114, the signal output circuit 113 may amplify the analog conversion signal. In any case, in the 8-bit conversion case of the first channel, as the value of the first digital input signal Din increases, the potential of the analog conversion signal generated on the wiring 114 rises monotonically, and the potential of the analog output signal Aout[1] also rises monotonically.

[0063] Thus, in the case of 8-bit conversion of the first channel, as shown in FIG. 10, of the ladder resistor circuit (111, 112) of the first channel and the ladder resistor circuit (121, 122) of the second channel, DA conversion of the first digital input signal Din is performed by the DA converter 10A using only the ladder resistor circuit (111, 112) of the first channel.

[0064] ---2nd channel 8-bit conversion case--- 11 shows the voltage application state in the case where 8-bit DA conversion is performed by the DA converter 10B in the first mode (hereinafter referred to as the 8-bit conversion case of the second channel). As described above, in the first mode, the switch SW is off. The digital input signal Din in the 8-bit conversion case of the second channel is particularly referred to as the second digital input signal Din.

[0065] In the 8-bit conversion case of the second channel, the control circuit 20 supplies voltages V[0] to V[4] corresponding to the lowest 5 bits of data d[0] to d[4] of the 8-bit second digital input signal Din to the resistor group 121, and supplies voltages V[0]' to V[6]' corresponding to the highest 3 bits of data d[5] to d[7] to the resistor group 122. In the 8-bit conversion case of the second channel, the voltages V[0] to V[4] are supplied to nodes N81 to N85, respectively, and the voltages V[0]' to V[6]' are supplied to nodes N90 to N96, respectively.

[0066] In the 8-bit conversion case of the second channel, for each integer i satisfying “0≦i≦4”, if the data d[i] is “1”, the voltage V[i] is the high-level voltage V H If data d[i] is set to “0”, voltage V[i] is set to the low-level voltage V L is set to.

[0067] In the 8-bit conversion case of the second channel, the control circuit 20 determines the levels of the voltages V[0]' to V[6]' to be supplied to the resistor group 122 by decoding the upper 3 bits of data d[5] to d[7]. The data d[5] to d[7] have integer values ​​of 0 or more and 7 or less in decimal notation. The values ​​of the data d[5] to d[7] in decimal notation are represented by values ​​VAL[d[5]:d[7]]. In the 8-bit conversion case of the second channel, the method of setting the levels of the voltages V[0]' to V[6]' according to the values ​​VAL[d[5]:d[7]] is the same as in the 8-bit conversion case of the first channel. Therefore, of the seven voltages V[0]' to V[6]', the high-level voltage V H, and the remaining (7-VAL[d[5]:d[7]]) voltages are set to the low-level voltage V L is set to.

[0068] In the 8-bit conversion case of the second channel, the ladder resistor circuit (121, 122) of the second channel generates an analog conversion signal corresponding to the 8-bit second digital input signal Din on the wiring 124. The analog conversion signal generated on the wiring 124 is obtained by converting the second digital input signal Din into an analog voltage signal with 8-bit resolution, and varies according to the second digital input signal Din. In the 8-bit conversion case of the second channel, the signal output circuit 123 performs impedance conversion of the analog conversion signal generated on the wiring 124, and outputs the analog conversion signal after impedance conversion as the analog output signal Aout[2]. In the process of generating the analog output signal Aout[2] from the analog conversion signal generated on the wiring 124, the signal output circuit 123 may amplify the analog conversion signal. In any case, in the 8-bit conversion case of the second channel, as the value of the second digital input signal Din increases, the potential of the analog conversion signal generated on the wiring 124 rises monotonically, and the potential of the analog output signal Aout[2] also rises monotonically.

[0069] Thus, in the case of 8-bit conversion of the second channel, as shown in FIG. 11, of the ladder resistor circuit (111, 112) of the first channel and the ladder resistor circuit (121, 122) of the second channel, DA conversion of the second digital input signal Din is performed by the DA converter 10B using only the ladder resistor circuit (121, 122) of the second channel.

[0070] In the first mode, the control circuit 10 may cause only one of the DA converters 10A and 10B to perform DA conversion, or may cause both DA converters to perform DA conversion simultaneously. In the latter case, the first digital input signal Din for the DA converter 10A and the second digital input signal Din for the DA converter 10B may be a common digital input signal Din, or may be two different digital input signals Din.

[0071] ---10-bit conversion case of the first channel--- FIG. 12 shows the voltage application state in the case where 10-bit DA conversion is performed by the DA converter 10A in the second mode (hereinafter referred to as the 10-bit conversion case of the first channel). In the 10-bit conversion case of the first channel, of the DA converters 10[1] and 10[2], only the DA converter 10[1] performs DA conversion, and the DA converter 10[2] does not perform DA conversion. In the second mode, the switch SW is on. The digital input signal Din in the 10-bit conversion case of the first channel is particularly referred to as the third digital input signal Din.

[0072] In the case of 10-bit conversion of the first channel, the DA converter 10A performs DA conversion of the third digital input signal Din using not only the ladder resistor circuit (111, 112) of the first channel but also the ladder resistor circuit (121, 122) of the second channel (an analog conversion signal for the third digital input signal Din is generated on the wiring 114).

[0073] In the 10-bit conversion case of the first channel, the control circuit 20 supplies voltages V[0] to V[5] corresponding to the lowest 6 bits of data d[0] to d[5] of the 10-bit third digital input signal Din to the resistor group 111, and supplies voltages V[0]' to V

[14] ' corresponding to the highest 4 bits of data d[6] to d[9] to the combination of resistor groups 121, 112, and 122.

[0074] In the 10-bit conversion case of the first channel, the voltages V[0] to V[5] are supplied to the nodes N30 to N35, respectively. In the 10-bit conversion case of the first channel, for each integer i that satisfies “0≦i≦5”, if the data d[i] is “1”, the voltage V[i] is a high-level voltage V H If data d[i] is set to “0”, voltage V[i] is set to the low-level voltage V L is set to.

[0075] In the 10-bit conversion case of the first channel, the voltage V[0]' is commonly supplied to the nodes N81 to N85. In the 10-bit conversion case of the first channel, the voltages V[1]', V[3]', V[5]', V[7]', V[9]', V

[11] ', and V

[13] ' are supplied to the nodes N40, N41, N42, N43, N44, N45, and N46, respectively, and the voltages V[2]', V[4]', V[6]', V[8]', V

[10] ', and V

[12] ', and V

[14] ' are supplied to the nodes N90, N91, N92, N93, N94, N95, and N96, respectively.

[0076] In the case of 10-bit conversion for the first channel, the control circuit 20 decodes the most significant 4 bits of data d[6] to d[9] to determine the level of the voltage V[0]' to V

[14] ' to be supplied to the combination of the resistor groups 121, 112, and 122. The data d[6] to d[9] have integer values ​​in decimal notation that are greater than or equal to 0 and less than or equal to 15. The value of the data d[6] to d[9] in decimal notation is represented by the value VAL[d[6]:d[9]].

[0077] Of the 15 voltages V[0]' to V

[14] ', the voltages corresponding to the values ​​VAL[d[6]:d[9]] are set to the high-level voltage V H The remaining (15-VAL[d[6]:d[9]]) voltages are set to the low-level voltage V L In detail, if "VAL[d[6]:d[9]]=0", the voltages V[0]' to V

[14] ' are all set to the low-level voltage V L If "VAL[d[6]:d[9]]=15", voltages V[0]' to V

[14] ' are all high-level voltages V H For any integer j that satisfies "1≦j≦14", if "VAL[d[6]:d[9]]=j", the voltages V[0]' to V[j-1]' are set to the high-level voltage V H , while the voltages V[j]' to V

[14] ' are set to the low-level voltage V L is set to.

[0078] In the 10-bit conversion case of the first channel, the resistor group 121 is equivalent to a single unit resistor Ra inserted between the node receiving the voltage V[0]' and the wiring 124 (see FIG. 13). Therefore, in the 10-bit conversion case of the first channel, the combination of the resistor groups 121, 112, and 122 can be regarded as a decoder-type resistor group having a total of 15 unit resistors.

[0079] In the case of 10-bit conversion of the first channel, the ladder resistor circuit (111, 112) of the first channel and the ladder resistor circuit (121, 122) of the second channel cooperate to generate an analog conversion signal corresponding to a 10-bit third digital input signal Din on the wiring 114. The analog conversion signal generated on the wiring 114 is obtained by converting the third digital input signal Din into an analog voltage signal with a resolution of 10 bits, and varies according to the third digital input signal Din. In the case of 10-bit conversion of the first channel, the signal output circuit 113 performs impedance conversion of the analog conversion signal generated on the wiring 114, and outputs the analog conversion signal after impedance conversion as the analog output signal Aout[1]. In the process of generating the analog output signal Aout[1] from the analog conversion signal generated on the wiring 114, the signal output circuit 113 may amplify the analog conversion signal. In any case, in the case of 10-bit conversion of the first channel, as the value of the third digital input signal Din increases, the potential of the analog conversion signal generated on the wiring 114 rises monotonically, and the potential of the analog output signal Aout[1] also rises monotonically.

[0080] In comparison with the reference example shown in FIG. 6, in the DA converters 10A and 10B according to the first embodiment, the required number of unit resistors is reduced from 57 to 49, and the mounting area of ​​the ladder resistor circuit can be reduced by approximately 14%.

[0081] Furthermore, a method of supplying voltage to the resistor group in which the decoder system is adopted is devised. This will be described. In the case of 10-bit conversion of the first channel, the control circuit 20 individually supplies a high-level voltage V to the second terminals of the resistors R40 to R46 and R90 to R96 (i.e., the nodes N40 to N46 and N90 to N96) in accordance with the value of the 10-bit third digital input signal Din. H or low-level voltage V L As a result, the currents of the resistors R40 to R46 and R90 to R96 (i.e., the currents flowing through the resistors R40 to R46 and R90 to R96, respectively) are controlled in accordance with the value of the third digital input signal Din, and thus the result of DA conversion of the 10-bit third digital input signal Din (analog converted signal) is generated on the wiring 114.

[0082] Here, in the second mode, of the resistors R40 to R46 and R90 to R96, the resistors R40 to R46 are directly connected to the wiring 114 without passing through the switch SW, while the resistors R90 to R96 are connected to the wiring 114 via the switch SW. For this reason, in the 10-bit conversion case of the first channel, if a low-level voltage V L and supplies a high-level voltage V H is supplied, a relatively large voltage drop occurs in the switch SW due to a current flowing from the wiring 124 to the wiring 114. The voltage drop in the switch SW is a factor in degrading the accuracy of the DA conversion.

[0083] Considering this, the voltages are assigned as shown in FIG. 12. That is, in the case of 10-bit conversion of the first channel, among the resistors R40 to R46, the high-level voltage V H The total number of resistors SUM1 to R90 and the high-level voltage V His set to be equal to or less than 1. That is, in the case of 10-bit conversion of the first channel, the control circuit 20 performs control to keep the absolute value of the difference (SUM1-SUM2) equal to or less than 1. This suppresses the voltage drop of the switch SW, thereby suppressing deterioration in accuracy of DA conversion due to the voltage drop of the switch SW.

[0084] If the absolute value of the difference (SUM1-SUM2) is 1 or less, the voltage allocation method may be changed from that shown in FIG. 12. For example, in the 10-bit conversion case of the first channel, voltage application as shown in FIG. 14 may be performed. In the configuration shown in FIG. 14, in the 10-bit conversion case of the first channel, voltages V[1]', V[4]', V[5]', V[8]', V[9]', V

[12] ', and V

[13] ' are supplied to nodes N40, N41, N42, N43, N44, N45, and N46, respectively, and voltages V[2]', V[3]', V[6]', V[7]', V

[10] ', V

[11] ', and V

[14] ' are supplied to nodes N90, N91, N92, N93, N94, N95, and N96, respectively. In the configuration shown in FIG. 14, the supply destinations of the voltages V[0] to V[5] and V[0]' are the same as those in FIG.

[0085] <<Second Example>> A second embodiment will be described. Resistors R62, R70, and R80 may be added to the DA converter 10B (FIG. 9) in the first embodiment as shown in FIG. 15. In the second embodiment, the DA converters 10A and 10B in FIG. 15 are used as the DA converters 10[1] and 10[2], respectively. The DA converter 10B according to the second embodiment is obtained by modifying the DA converter 10B (FIG. 9) in the first embodiment by adding resistors R62, R70, and R80. Except for the addition and the following matters associated with the addition, the configuration and operation of the DA converter 10B according to the second embodiment are the same as those of the DA converter 10B according to the first embodiment, and the configuration and operation of the DA converter 10A according to the second embodiment are the same as those of the DA converter 10A according to the first embodiment. The resistors R62, R70, and R80 are components of the resistor group 121 of the DA converter 10B according to the second embodiment. Resistors R62, R70, and R80 are unit resistors and have the same resistance value as other unit resistors (such as resistor R60) (although there may be some error).

[0086] A first end of resistor R60 is connected to ground. A second end of resistor R60 is connected to a first end of resistor R61. With the addition of resistor R62, the second end of resistor R61 and the first end of resistor R62 are connected to node N70. A second end of resistor R62 is connected to node N71. A first end of resistor R70 is connected to node N70. A second end of resistor R70 is connected to a first end of resistor R80. A second end of resistor R80 is connected to node N80.

[0087] The operation of the DA converter 10A in the case of 8-bit conversion of the first channel is as shown in the first embodiment (see FIG. 10). The operation of the DA converter 10B in the case of 8-bit conversion of the second channel is also as shown in the first embodiment (see FIG. 11). However, in the case of 8-bit conversion of the second channel according to the second embodiment, the control circuit 20 sets the voltage of the node N80 to the low-level voltage V L Secure it in place.

[0088] The operation of the DA converter 10A in the case of 10-bit conversion of the first channel is also the same as that shown in the first embodiment (see FIG. 12). However, in the case of 10-bit conversion of the first channel according to the second embodiment, the voltage V[0]' is supplied in common to the nodes N80 to N85.

[0089] ---2nd channel 10-bit conversion case--- In the second mode, 10-bit DA conversion can also be performed by the DA converter 10B. The case in which 10-bit DA conversion is performed by the DA converter 10B in the second mode is referred to as the 10-bit conversion case of the second channel. In the 10-bit conversion case of the second channel, of the DA converters 10[1] and 10[2], only the DA converter 10[2] performs DA conversion, and the DA converter 10[1] does not perform DA conversion.

[0090] 16 shows the voltage application state in the 10-bit conversion case of the second channel. As described above, in the second mode, the switch SW is on. The digital input signal Din in the 10-bit conversion case of the second channel is specifically referred to as the fourth digital input signal Din.

[0091] In the 10-bit conversion case of the second channel, the DA converter 10B performs DA conversion of the fourth digital input signal Din using not only the ladder resistor circuit (121, 122) of the second channel but also the ladder resistor circuit (111, 112) of the first channel (an analog conversion signal for the fourth digital input signal Din is generated on the wiring 124). By reversing the roles of the DA converters 10A and 10B in the 10-bit conversion case of the first channel, the operation in the 10-bit conversion case of the second channel is realized.

[0092] That is, in the case of 10-bit conversion of the second channel, the control circuit 20 supplies voltages V[0] to V[5] corresponding to the lowest 6 bits of data d[0] to d[5] of the 10-bit fourth digital input signal Din to the resistor group 121, and supplies voltages V[0]' to V

[14] ' corresponding to the highest 4 bits of data d[6] to d[9] to the combination of the resistor groups 111, 112 and 122.

[0093] In the 10-bit conversion case of the second channel, the voltages V[0] to V[5] are supplied to the nodes N80 to N85, respectively. In the 10-bit conversion case of the second channel, for each integer i that satisfies “0≦i≦5”, if the data d[i] is “1”, the voltage V[i] is a high-level voltage V H If data d[i] is set to “0”, voltage V[i] is set to the low-level voltage V L is set to.

[0094] In the 10-bit conversion case of the second channel, the voltage V[0]' is commonly supplied to the nodes N30 to N35. In the 10-bit conversion case of the second channel, the voltages V[1]', V[3]', V[5]', V[7]', V[9]', V

[11] ', and V

[13] ' are supplied to the nodes N90, N91, N92, N93, N94, N95, and N96, respectively, and the voltages V[2]', V[4]', V[6]', V[8]', V

[10] ', and V

[12] ', and V

[14] ' are supplied to the nodes N40, N41, N42, N43, N44, N45, and N46, respectively.

[0095] In the 10-bit conversion case of the second channel, the control circuit 20 decodes the upper 4 bits of data d[6] to d[9] to determine the levels of the voltages V[0]' to V

[14] ' to be supplied to the combinations of the resistor groups 111, 112, and 122. The data d[6] to d[9] have integer values ​​of 0 to 15 in decimal notation. The values ​​of the data d[6] to d[9] in decimal notation are represented by values ​​VAL[d[6]:d[9]]. The method of setting the levels of the voltages V[0]' to V

[14] ' according to the values ​​VAL[d[6]:d[9]] is the same as in the 10-bit conversion case of the first channel.

[0096] In the case of 10-bit conversion of the second channel, the ladder resistor circuit (121, 122) of the second channel and the ladder resistor circuit (111, 112) of the first channel cooperate to generate an analog conversion signal corresponding to a 10-bit fourth digital input signal Din on the wiring 124. The analog conversion signal generated on the wiring 124 is obtained by converting the fourth digital input signal Din into an analog voltage signal with a resolution of 10 bits, and varies according to the fourth digital input signal Din. In the case of 10-bit conversion of the second channel, the signal output circuit 123 performs impedance conversion of the analog conversion signal generated on the wiring 124, and outputs the analog conversion signal after impedance conversion as the analog output signal Aout[2]. In the process of generating the analog output signal Aout[2] from the analog conversion signal generated on the wiring 124, the signal output circuit 123 may amplify the analog conversion signal. In any case, in the case of 10-bit conversion of the second channel, as the value of the fourth digital input signal Din increases, the potential of the analog conversion signal generated on the wiring 124 rises monotonically, and the potential of the analog output signal Aout[2] also rises monotonically.

[0097] As in the case of 10-bit conversion of the first channel, in the case of 10-bit conversion of the second channel, control is performed to keep the absolute value of the above difference (SUM1-SUM2) at 1 or less.

[0098] <<Third Example>> A third embodiment will now be described. A sample-and-hold circuit may be provided in each DA converter 10 in the converter block BLK. Thus, a sample-and-hold circuit may be added to each of the DA converters 10A and 10B in the first or second embodiment. Figure 17 shows a circuit diagram of the DA converters 10A and 10B according to the third embodiment. In the third embodiment, the DA converters 10A and 10B in Figure 17 are used as DA converters 10[1] and 10[2], respectively.

[0099] The DA converter 10A according to the third embodiment is obtained by adding a sample-and-hold circuit 115 to the DA converter 10A according to the second embodiment (see FIG. 15). The DA converter 10B according to the third embodiment is obtained by adding a sample-and-hold circuit 125 to the DA converter 10B according to the second embodiment (see FIG. 15). Except for the addition of the sample-and-hold circuits 115 and 125 and the following matters associated with this addition, the configuration and operation of the DA converters 10A and 10B according to the third embodiment are similar to the configuration and operation of the DA converters 10A and 10B according to the second embodiment. The sample-and-hold circuits 115 and 125 may be added to the DA converters 10A and 10B according to the first embodiment.

[0100] The sample and hold circuit 115 is inserted between the signal output circuit 113 and the wiring 114. The sample and hold circuit 115 includes switches 115a and 115b and a capacitor 115c. A first end of the switch 115a is connected to the wiring 114 and a first end of the switch SW. A second end of the switch 115a is connected to a first end of the switch 115b at a node 115d. A second end of the switch 115b is connected to a first end of the capacitor 115c, and a second end of the capacitor 115c is connected to ground. The signal at the node 115d is input to the signal output circuit 113 as an output signal of the sample and hold circuit 115. In particular, the node 115d is connected to a non-inverting input terminal of an operational amplifier serving as the signal output circuit 113.

[0101] The sample and hold circuit 125 is inserted between the signal output circuit 123 and the wiring 124. The sample and hold circuit 125 includes switches 125a and 125b and a capacitor 125c. A first end of the switch 125a is connected to the wiring 124 and a second end of the switch SW. A second end of the switch 125a is connected to a first end of the switch 125b at a node 125d. A second end of the switch 125b is connected to a first end of the capacitor 125c, and a second end of the capacitor 125c is connected to ground. The signal at the node 125d is input to the signal output circuit 123 as an output signal of the sample and hold circuit 125. In particular, the node 125d is connected to a non-inverting input terminal of an operational amplifier serving as the signal output circuit 123.

[0102] The control circuit 20 controls the switches 115a, 115b, 125a and 125b to be turned on or off individually.

[0103] The sample-and-hold circuit 115 is in one of the through state, sample state, and hold state shown in FIG.

[0104] In the through state of the sample and hold circuit 115, the switch 115a is on and the switch 115b is off. In the through state, the sample and hold circuit 115 passes through the signal on the wiring 114 to the signal output circuit 113, i.e., outputs the signal on the wiring 114 to the signal output circuit 113 in real time (therefore, the signal on the wiring 114 at a certain time is output to the signal output circuit 113 at that time).

[0105] In the sample state of the sample and hold circuit 115, the switches 115a and 115b are both on. In the sample state, the sample and hold circuit 115 samples the signal on the wiring 114. The sampled signal is held in the capacitor 115c, and the signal held in the capacitor 115c appears at the node 115d. However, in the sample state, the sample and hold circuit 115 outputs the signal on the wiring 114 to the signal output circuit 113 in real time, just like in the through state (hence, the signal on the wiring 114 at a certain time is output to the signal output circuit 113 at that time).

[0106] In the hold state of the sample-and-hold circuit 115, the switch 115a is off and the switch 115b is on. The control circuit 20 can set the sample-and-hold circuit 115 to the sample state for a required time and then to the hold state. The sample-and-hold circuit 115 in the hold state continuously outputs the signal of the wiring 114 sampled in the sample state and held in the capacitor 115c to the signal output circuit 113 (the non-inverting input terminal of the operational amplifier as the signal output circuit 113). After the sample-and-hold circuit 115 is set to the sample state at the first time, when the sample-and-hold circuit 115 is switched from the sample state to the hold state at the second time, the signal of the wiring 114 immediately before the second time is held in the capacitor 115c, and the held signal of the capacitor 115c is output to the signal output circuit 113 at the second time and after.

[0107] The signal output circuit 113 outputs a signal corresponding to the output signal of the sample and hold circuit 115 (i.e., the signal at node 115d) as the analog output signal Aout[1]. In detail, the signal output circuit 113 performs impedance conversion on the output signal of the sample and hold circuit 115 (i.e., the signal at node 115d), and outputs the output signal of the sample and hold circuit 115 after the impedance conversion as the analog output signal Aout[1].

[0108] The sample-and-hold circuit 125 is in one of the through state, sample state, and hold state shown in FIG.

[0109] In the through state of the sample and hold circuit 125, the switch 125a is on and the switch 125b is off. In the through state, the sample and hold circuit 125 passes through the signal on the wiring 124 to the signal output circuit 123, i.e., outputs the signal on the wiring 124 to the signal output circuit 123 in real time (therefore, the signal on the wiring 124 at a certain time is output to the signal output circuit 123 at that time).

[0110] In the sample state of the sample and hold circuit 125, the switches 125a and 125b are both on. In the sample state, the sample and hold circuit 125 samples the signal on the wiring 124. The sampled signal is held in the capacitor 125c, and the signal held in the capacitor 125c appears at the node 125d. However, in the sample state, the sample and hold circuit 125 outputs the signal on the wiring 124 to the signal output circuit 123 in real time, just like in the through state (hence, the signal on the wiring 124 at a certain time is output to the signal output circuit 123 at that time).

[0111] In the hold state of the sample-and-hold circuit 125, the switch 125a is off and the switch 125b is on. The control circuit 20 can set the sample-and-hold circuit 125 to the sample state for a required time and then to the hold state. The sample-and-hold circuit 125 in the hold state continuously outputs the signal of the wiring 124 sampled in the sample state and held in the capacitor 125c to the signal output circuit 123 (the non-inverting input terminal of the operational amplifier as the signal output circuit 123). After the sample-and-hold circuit 125 is set to the sample state at the first time, when the sample-and-hold circuit 125 is switched from the sample state to the hold state at the second time, the signal of the wiring 124 immediately before the second time is held in the capacitor 125c, and the held signal of the capacitor 125c is output to the signal output circuit 123 from the second time onwards.

[0112] The signal output circuit 123 outputs a signal corresponding to the output signal of the sample and hold circuit 125 (i.e., the signal at node 125d) as the analog output signal Aout[2]. In detail, the signal output circuit 123 performs impedance conversion on the output signal of the sample and hold circuit 125 (i.e., the signal at node 125d), and outputs the output signal of the sample and hold circuit 125 after the impedance conversion as the analog output signal Aout[2].

[0113] By providing the sample-and-hold circuits 115 and 125, it becomes possible to output the DA conversion result of the current digital input signal Din from the signal output circuit of one of the first and second channels, while holding the analog output signal of the signal output circuit of the other channel as the DA conversion result of the past digital input signal Din.

[0114] For example, at the first time of interest, DA conversion in the 10-bit conversion case of the first channel is performed, and the signal generated in the DA conversion on the wiring 114 is held in the capacitor 115c, and the sample-and-hold circuit 115 is switched from the sample state to the hold state. After that, at the second time of interest, DA conversion in the 10-bit conversion case of the second channel is performed, and the signal generated in the DA conversion on the wiring 124 is output to the signal output circuit 123 by putting the sample-and-hold circuit 125 in the through state. The state of the DA converters 10A and 10B at the second time of interest is shown in FIG. 20. Then, at the second time of interest and immediately thereafter, the result of the 10-bit DA conversion performed at the first time of interest is output as the analog output signal Aout[1], while the result of the 10-bit DA conversion performed at the second time of interest is output as the analog output signal Aout[2].

[0115] <<Fourth Example>> A fourth embodiment will be described. As shown in FIG. 21, a plurality of pairs of DA converters 10A and 10B may be provided in the converter block BLK. For example, the first DA converter 10A, the first DA converter 10B, the second DA converter 10A, and the second DA converter 10B are provided in the converter block BLK as the DA converters 10 of the first to fourth channels, respectively. The pair of the first DA converter 10A and the first DA converter 10B is the same as the pair of DA converters 10A and 10B shown in the first, second, or third embodiment, and the pair of the second DA converter 10A and the second DA converter 10B is the same as the pair of DA converters 10A and 10B shown in the first, second, or third embodiment. Three or more pairs of DA converters 10A and 10B may be provided in the converter block BLK.

[0116] <<Fifth Example>> A fifth embodiment will now be described. A DA conversion device 1 that always operates in the first mode and a DA conversion device 1 that always operates in the second mode may be manufactured as separate electronic components. For convenience, the DA conversion device 1 that always operates in the first mode will be referred to as a DA conversion device 1 fixed in the first mode, and the DA conversion device 1 that always operates in the second mode will be referred to as a DA conversion device 1 fixed in the second mode.

[0117] In the manufacturing stage of the DA conversion device 1, a second process is carried out after a first process. In the first process, the DA conversion device 1 shown in any one of the first to fourth embodiments is formed on a semiconductor chip. In the second process, it is determined and fixed whether the DA conversion device 1 on the semiconductor chip is always operated in the first mode or always in the second mode. The DA conversion device 1 is provided with a nonvolatile memory (not shown) that stores mode data MDa in a nonvolatile manner. The mode data MDa has "0" or "1". In the second process, "0" or "1" is written to the mode data MDa of the DA conversion device 1 using a specified shipping process equipment (not shown).

[0118] The DA conversion device 1 in which "0" is written to the mode data MDa is a DA conversion device 1 fixed to the first mode. The DA conversion device 1 in which "0" is written to the mode data MDa reads out the mode data MDa of "0" every time it is started, and always operates in the first mode based on the mode data MDa of "0". When the DA conversion device 1 fixed to the first mode has the configuration shown in the first embodiment, for example, the control circuit 20 determines the levels of the voltages V[0] to V[4] and V[0]' to V[6]' from the 8-bit digital input signal Din, and supplies the voltages V[0] to V[4] and V[0]' to V[6]' to the corresponding nodes so that the DA conversion according to the 8-bit conversion case of the first channel shown in FIG. 10 or the DA conversion according to the 8-bit conversion case of the second channel shown in FIG. 11 is realized. The same applies when the DA conversion device 1 fixed to the first mode has the configuration shown in the embodiment other than the first embodiment.

[0119] The DA conversion device 1 in which "1" is written to the mode data MDa is a DA conversion device 1 fixed to the second mode. The DA conversion device 1 in which "1" is written to the mode data MDa reads out the mode data MDa of "1" every time it is started, and always operates in the second mode based on the mode data MDa of "1". When the DA conversion device 1 fixed to the second mode has the configuration shown in the first embodiment, for example, the control circuit 20 determines the levels of the voltages V[0] to V[5] and V[0]' to V

[14] ' from the 10-bit digital input signal Din, and supplies the voltages V[0] to V[5] and V[0]' to V

[14] ' to the corresponding nodes so that the DA conversion in the 10-bit conversion case of the first channel shown in FIG. 12 is realized. The same applies when the DA conversion device 1 fixed to the second mode has the configuration shown in the embodiment other than the first embodiment.

[0120] The switch SW may be a switching element that is controlled to be on or off by the control circuit 20. In this case, the control circuit 20 in the DA conversion device 1 fixed in the first mode always sets the switch SW to off based on the mode data MDa of "0", and the control circuit 20 in the DA conversion device 1 fixed in the second mode always sets the switch SW to on based on the mode data MDa of "1".

[0121] The switch SW may be a fuse element that can be physically disconnected. In this case, when the DA conversion device 1 is caused to function as a DA conversion device 1 fixed in the first mode, the fuse element serving as the switch SW is disconnected during the manufacturing stage of the DA conversion device 1 to fix the switch SW to off. When the DA conversion device 1 is caused to function as a DA conversion device 1 fixed in the second mode, the fuse element is not disconnected during the manufacturing stage of the DA conversion device 1, and the switch SW is kept on.

[0122] According to the method of the fifth embodiment, a common semiconductor chip can be used to selectively form a DA conversion device 1 fixed to the first mode and a DA conversion device 1 fixed to the second mode. Being able to form a plurality of types of products (electronic components) using a common semiconductor chip is advantageous in terms of reducing the development costs and inventory management costs of the semiconductor chip.

[0123] <<Sixth Example>> A sixth embodiment will now be described. Unlike the fifth embodiment, in the sixth embodiment, the operation mode of the DA conversion device 1 can be switched and set at any timing after the DA conversion device 1 is manufactured and shipped.

[0124] For example, the control circuit 20 in the DA conversion device 1 operates the converter block BLK in a first mode or a second mode based on the mode data MDb. The mode data MDb has a value of "0" or "1." A memory (not shown) for storing the mode data MDb may be provided in the DA conversion device 1. In this case, the memory for storing the mode data MDb may be a non-volatile memory, or may be a volatile memory such as a register.

[0125] The value of the mode data MDb may be determined based on a mode setting command signal supplied from the MPU 2 to the DA conversion device 1. Alternatively, an external terminal for mode setting may be included in the multiple external terminals provided in the DA conversion device 1, in which case the value of the mode data MDb may be determined based on the level of a voltage supplied from outside the DA conversion device 1 to the external terminal for mode setting.

[0126] When the mode data MDb has a value of "0", the DA conversion device 1 operates in the first mode. When the DA conversion device 1 has the configuration shown in the first embodiment, for example, and the mode data MDb has a value of "0", the control circuit 20 determines the levels of the voltages V[0] to V[4] and V[0]' to V[6]' from the 8-bit digital input signal Din, and supplies the voltages V[0] to V[4] and V[0]' to V[6]' to the corresponding nodes, so that the DA conversion according to the 8-bit conversion case of the first channel shown in FIG. 10 or the 8-bit conversion case of the second channel shown in FIG. 11 is realized. The same applies when the DA conversion device 1 has a configuration shown in an embodiment other than the first embodiment (for example, the second or third embodiment).

[0127] When the mode data MDb has a value of "1", the DA conversion device 1 operates in the second mode. When the DA conversion device 1 has the configuration shown in the first embodiment, for example, and the mode data MDb has a value of "1", the control circuit 20 determines the levels of voltages V[0] to V[5] and V[0]' to V

[14] ' from the 10-bit digital input signal Din, and supplies V[0] to V[5] and V[0]' to V

[14] ' to the corresponding nodes, so that DA conversion is realized in the 10-bit conversion case of the first channel shown in FIG. 12. The same applies when the DA conversion device 1 has a configuration shown in an embodiment other than the first embodiment (for example, the second or third embodiment).

[0128] The switch SW according to the sixth embodiment is a switching element that is controlled to be on or off by the control circuit 20. When the mode data MDb has a value of "0", the control circuit 20 controls and sets the switch SW to be off. When the mode data MDb has a value of "1", the control circuit 20 controls and sets the switch SW to be on.

[0129] According to the method of the sixth embodiment, one DA conversion device 1 can be selectively operated in the first mode or the second mode, thereby meeting various DA conversion needs.

[0130] <<Seventh Example>> The seventh embodiment will be described. In the seventh embodiment, modified techniques or supplementary matters for each of the above matters will be described.

[0131] The control circuit 20 can operate selectively in a first state in which the DA converter 1 of a specific channel performs m-bit DA conversion, or in a second state in which the DA converter 1 of the specific channel performs n-bit DA conversion. The specific channel is, for example, the first channel or the second channel, and in the first embodiment, it is the first channel. The first state corresponds to the first mode, and the second state corresponds to the second mode.

[0132] It was described above that m-bit DA conversion is executed in the first mode and n-bit DA conversion is executed in the second mode, and for the sake of concreteness of the description, it was exemplified that (m, n) = (8, 10). However, as long as m and n have integer values of 2 or more and "m < n" holds, the respective values of m and n are arbitrary, and for example, (m, n) = (10, 12) may be used.

[0133] The embodiments of the present disclosure can be appropriately modified within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meaning of the terms of the present disclosure or each constituent element is not limited to those described in the above embodiments. The specific numerical values shown in the above description text are merely examples, and as a matter of course, they can be changed to various numerical values.

[0134] <<Supplementary Note>> A supplementary note is provided for the present disclosure in which specific configuration examples were shown in the above embodiments.

[0135] A DA conversion device according to one aspect of the present disclosure is a DA conversion device (1) including DA converters (10) for multiple channels configured to perform digital-to-analog conversion, and a control circuit (20), each of which has a ladder resistor circuit configured to generate an analog conversion signal corresponding to a digital input signal (Din), and a signal output circuit configured to output an analog output signal based on the analog conversion signal, and the control circuit selectively operates in a first state in which the DA converter of a specific channel performs m-bit digital-to-analog conversion, or in a second state in which the DA converter of the specific channel performs n-bit digital-to-analog conversion, where m and n represent integers equal to or greater than 2, and n is greater than m, and in the second state, the DA converter of the specific channel generates the analog conversion signal using the ladder resistor circuit of the specific channel and the ladder resistor circuits of other channels (first configuration).

[0136] This makes it possible to reduce the area of ​​the ladder resistor circuit, and therefore the area of ​​the DA conversion device.

[0137] With regard to the DA conversion device of the first configuration described above, in the first state, the DA converter of the specific channel (e.g., 10[1]) and the DA converter of the other channel (e.g., 10[2]) each perform digital-to-analog conversion on an m-bit digital input signal, the DA converter of the specific channel generates an analog conversion signal of the specific channel using a ladder resistor circuit of the specific channel (e.g., 111, 112), and the DA converter of the other channel generates an analog conversion signal of the other channel using a ladder resistor circuit of the other channel (e.g., 121, 122), and in the second state, the DA converter of the specific channel performs digital-to-analog conversion on an n-bit digital input signal, while the digital-to-analog conversion by the DA converter of the other channel is not performed (second configuration).

[0138] In the DA conversion device of the second configuration, each DA converter has a conversion wiring (114, 124) through which the analog conversion signal is generated, and a switch (SW) is provided between the conversion wiring of the specific channel and the conversion wiring of the other channels, and in the first state, the switch is off, and the conversion wiring and ladder resistor circuit of the specific channel and the conversion wiring and ladder resistor circuits of the other channels are disconnected from each other, and in the second state, the switch is on, and the result of digital-to-analog conversion of the n-bit digital input signal is generated on the conversion wiring of the specific channel (e.g., 114) using the ladder resistor circuit of the specific channel (e.g., 111, 112) and the ladder resistor circuit of the other channels (e.g., 121, 122). (Third configuration)

[0139] In the DA conversion device according to the third configuration, the conversion wiring of the specific channel is connected to a first end of the switch, the conversion wiring of the other channel is connected to a second end of the switch, the ladder resistor circuit of the specific channel has a first resistor group (e.g., 112), the ladder resistor circuit of the other channel has a second resistor group (e.g., 122), each first end of a plurality of first resistors (e.g., R40 to R46) included in the first resistor group is directly connected to the conversion wiring of the specific channel (e.g., 114) without passing through the switch, each first end of a plurality of second resistors (e.g., R90 to R96) included in the second resistor group is directly connected to the conversion wiring of the other channel (e.g., 124) without passing through the switch, In the first state, the control circuit supplies a high-level voltage or a low-level voltage individually to each second terminal of the plurality of first resistors and each second terminal of the plurality of second resistors in accordance with a value of the n-bit digital input signal, thereby generating a result of digital-to-analog conversion of the n-bit digital input signal in a conversion wiring of the specific channel by controlling the respective currents of the plurality of first resistors and the plurality of second resistors, and in the second state, the control circuit may be configured to keep a difference between a total number of first resistors among the plurality of first resistors to which the high-level voltage is supplied and a total number of second resistors among the plurality of second resistors to which the high-level voltage is supplied to be equal to or less than 1 (fourth configuration).

[0140] This makes it possible to minimize the effects of the switch (suppressing deterioration of the accuracy of DA conversion due to the switch).

[0141] With respect to the DA conversion device of the third or fourth configuration, in the first state and the second state, the signal output circuit (e.g., 113) of the specific channel outputs a signal corresponding to the signal in the conversion wiring of the specific channel as an analog output signal of the specific channel, and in the first state, the signal output circuit (e.g., 123) of the other channel outputs a signal corresponding to the signal in the conversion wiring of the other channel as an analog output signal of the other channel (fifth configuration).

[0142] In the DA conversion device according to the third or fourth configuration, each DA converter may have a sample and hold circuit, the sample and hold circuit (e.g., 115) of the specific channel through-outputs the signal in the conversion wiring of the specific channel to the signal output circuit of the specific channel, or outputs a held signal obtained by sampling and holding the signal in the conversion wiring of the specific channel to the signal output circuit of the specific channel, the signal output circuit of the specific channel outputs a signal corresponding to the output signal of the sample and hold circuit of the specific channel as the analog output signal of the specific channel, and the sample and hold circuit (e.g., 125) of the other channel through-outputs the signal in the conversion wiring of the other channel to the signal output circuit of the other channel, or outputs a held signal obtained by sampling and holding the signal in the conversion wiring of the other channel to the signal output circuit of the other channel, and the signal output circuit of the other channel outputs a signal corresponding to the output signal of the sample and hold circuit of the other channel as the analog output signal of the other channel (sixth configuration). [Explanation of symbols]

[0143] 1. Digital-to-analog converter 2 MPU BLK Converter block 10, 10[1], 10[2], 10A, 10B DA converter 20 Control circuit Din Digital input signal B[1]~B[L-1] bits d[1]~d[L-1] data Aout[1], Aout[2] Analog output signal 10 REF1 ~10 REF4 DA Converter 611, 612, 621, 622, 631, 632, 641, 642 resistance group 613, 623, 633, 634 Output Buffers 614, 624, 634, 644 Wiring 111, 112, 121, 122 resistance group 113, 123 Signal output circuit 114, 124 wiring (conversion wiring) SW Switch R10~R16, R20~R25, R30~R35, R40~R46 Unit resistors R60~R66, R70~R75, R80~R85, R90~R96 Unit resistors N20~N25, N30~N35, N40~N46 nodes N70~N75, N80~N85, N90~N96 nodes V[0]~V[5], V[0]'~V

[14] ' Voltage 115, 125 Sample and hold circuit 115a, 115b, 125a, 125b Switches 115c, 125c capacitors 115d, 125d nodes

Claims

1. A DA conversion device including a plurality of channels of DA converters configured to perform digital / analog conversion and a control circuit, Each DA converter has a ladder resistor circuit configured to generate an analog converted signal corresponding to a digital input signal, and a signal output circuit configured to output an analog output signal based on the analog converted signal; the control circuit selectively operates in a first state in which the DA converter of a specific channel performs m-bit digital-to-analog conversion, or in a second state in which the DA converter of the specific channel performs n-bit digital-to-analog conversion; m and n each represent an integer of 2 or more, n is greater than m; In the second state, the DA converter of the specific channel generates the analog conversion signal using the ladder resistor circuit of the specific channel and the ladder resistor circuits of other channels. , D / A conversion device.

2. In the first state, the DA converter of the specific channel and the DA converter of the other channel each perform digital-to-analog conversion on an m-bit digital input signal, the DA converter of the specific channel generates an analog-converted signal of the specific channel using a ladder resistor circuit of the specific channel, and the DA converter of the other channel generates an analog-converted signal of the other channel using the ladder resistor circuit of the other channel, In the second state, the DA converter of the specific channel performs digital-to-analog conversion on an n-bit digital input signal, while the DA converters of the other channels are not performing digital-to-analog conversion.

2. The DA conversion device according to claim 1.

3. Each DA converter has a conversion line from which the analog conversion signal is generated; a switch is provided between the conversion wiring of the specific channel and the conversion wiring of the other channel; In the first state, the switch is off, and the conversion wiring and the ladder resistor circuit of the specific channel are not connected to the conversion wiring and the ladder resistor circuit of the other channel, In the second state, the switch is on, and a result of digital / analog conversion of the n-bit digital input signal is generated on a conversion line of the specific channel using the ladder resistor circuit of the specific channel and the ladder resistor circuits of the other channels.

3. The DA conversion device according to claim 2.

4. the conversion wiring of the specific channel is connected to a first end of the switch, and the conversion wiring of the other channel is connected to a second end of the switch; the ladder resistor circuit of the specific channel has a first resistor group, and the ladder resistor circuit of the other channel has a second resistor group; a first end of each of the plurality of first resistors included in the first resistor group is directly connected to a conversion wiring of the specific channel without passing through the switch, and a first end of each of the plurality of second resistors included in the second resistor group is directly connected to a conversion wiring of the other channel without passing through the switch; In the second state, the control circuit supplies a high level voltage or a low level voltage to each second end of the plurality of first resistors and each second end of the plurality of second resistors individually according to a value of the n-bit digital input signal, thereby generating a result of digital / analog conversion of the n-bit digital input signal on a conversion wiring of the specific channel by controlling the currents of the plurality of first resistors and the plurality of second resistors, respectively; In the second state, the control circuit maintains a difference between the total number of first resistors to which the high-level voltage is supplied among the plurality of first resistors and the total number of second resistors to which the high-level voltage is supplied among the plurality of second resistors at 1 or less.

4. The DA conversion device according to claim 3.

5. In the first state and the second state, the signal output circuit of the specific channel outputs a signal corresponding to a signal in a conversion wiring of the specific channel as an analog output signal of the specific channel; In the first state, the signal output circuit of the other channel outputs a signal corresponding to a signal in a conversion wiring of the other channel as an analog output signal of the other channel.

5. The DA conversion device according to claim 3 or 4.

6. Each DA converter has a sample-and-hold circuit, the sample and hold circuit of the specific channel outputs a signal in the conversion wiring of the specific channel to the signal output circuit of the specific channel through the conversion wiring of the specific channel, or outputs a held signal obtained by sampling and holding the signal in the conversion wiring of the specific channel to the signal output circuit of the specific channel; the signal output circuit of the specific channel outputs a signal corresponding to the output signal of the sample-and-hold circuit of the specific channel as an analog output signal of the specific channel; the sample and hold circuit of the other channel outputs the signal in the conversion wiring of the other channel to the signal output circuit of the other channel through, or outputs a held signal obtained by sampling and holding the signal in the conversion wiring of the other channel to the signal output circuit of the other channel; The signal output circuit of the other channel outputs a signal corresponding to the output signal of the sample-and-hold circuit of the other channel as an analog output signal of the other channel.

5. The DA conversion device according to claim 3 or 4.

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