Semiconductor light-emitting device and method for manufacturing the same

Abstract

To provide a semiconductor light-emitting device that can improve light-emitting characteristics and a method for manufacturing the same.SOLUTION: A semiconductor light-emitting device according to an embodiment includes a light-emitting layer, a semiconductor substrate, and a multilayer film part. The semiconductor substrate includes gallium arsenide (GaAs) that is a cubic crystal. The semiconductor substrate includes a substrate lower surface and a substrate upper surface. The substrate upper surface is positioned between the light-emitting layer and the substrate lower surface and is tilted with respect to a (100) plane of the cubic crystal. The multilayer film part includes a first layer and a second layer. The first layer includes a first surface that is positioned between the substrate upper surface and the light-emitting layer and extends along the substrate upper surface. The second layer includes a second surface that is positioned between the first surface and the light-emitting layer, contacts the first surface and is opposed to the surface contacting the first surface. An unevenness of the second surface is greater than an unevenness of the first surface. The light from the light-emitting layer passes through the multilayer film part and is emitted.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to a semiconductor light emitting device and a method for manufacturing the same. [Background technology]

[0002] Semiconductor light emitting devices have been developed that emit light from a light emitting layer through a substrate, and it is desirable to improve the light emitting characteristics of such semiconductor light emitting devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2012-15394 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor light emitting device capable of improving light emitting characteristics, and a method for manufacturing the same. [Means for solving the problem]

[0005] The semiconductor light emitting device according to the embodiment includes a light emitting layer, a semiconductor substrate, and a multilayer film portion. The semiconductor substrate includes cubic gallium arsenide (GaAs). The semiconductor substrate has a substrate lower surface and a substrate upper surface. The substrate upper surface is located between the light emitting layer and the substrate lower surface and is inclined with respect to the cubic (100) plane. The multilayer film portion includes a first layer and a second layer. The first layer has a first surface located between the substrate upper surface and the light emitting layer and extending along a plane parallel to the substrate upper surface. The second layer is located between the first surface and the light emitting layer and has a second surface that is in contact with the first surface and is opposite to the surface in contact with the first surface. The unevenness of the second surface is larger than the unevenness of the first surface. Light from the light emitting layer is emitted through the multilayer film portion. [Brief description of the drawings]

[0006] [Figure 1] 1A and 1B are schematic views illustrating a semiconductor light emitting device according to an embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view illustrating a light emitting layer of the semiconductor light emitting device according to the embodiment. [Diagram 3] 3A and 3B are schematic views illustrating the multilayer film portion of the semiconductor light emitting device according to the embodiment. [Figure 4] FIG. 4 is an image illustrating a portion of the semiconductor light emitting device according to the embodiment. [Diagram 5] 5(a) and 5(b) are images illustrating a portion of the semiconductor light emitting device according to the embodiment. [Figure 6] FIG. 6 is a graph illustrating the emission intensity distribution in a semiconductor light emitting device. [Figure 7] 7(a) and 7(b) are schematic plan views illustrating the emission intensity distribution in a semiconductor light emitting device. [Figure 8] 8A and 8B are schematic cross-sectional views illustrating the semiconductor light emitting device according to the embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to the embodiment. [Figure 10] 10(a) to 10(e) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor light emitting device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those already explained are given the same reference numerals and detailed explanations are omitted as appropriate.

[0008] 1A and 1B are schematic views illustrating a semiconductor light emitting device according to an embodiment. Fig. 1(a) is a plan view of a semiconductor light emitting device 1 according to an embodiment as viewed from above, and Fig. 1(b) is a cross-sectional view taken along line A1-A2 shown in Fig. 1(a).

[0009] 1(b), the semiconductor light emitting device 1 includes a semiconductor substrate 100, a first buffer layer 301-1, a multilayer film portion 310, a second buffer layer 301-2, an n-type cladding layer 102, a light emitting layer 103, a p-type cladding layer 104, a p-type contact layer 105, a p-side electrode 106, and an n-side electrode 107. The semiconductor light emitting device 1 is, for example, a light emitting diode.

[0010] The semiconductor substrate 100 includes cubic gallium arsenide (GaAs). The semiconductor substrate 100 is, for example, an n-type GaAs substrate. The semiconductor substrate 100 has a substrate lower surface 100s and a substrate upper surface 100t that is the surface opposite to the substrate lower surface 100s. The substrate upper surface 100t is inclined at an inclination angle θ with respect to the (100) plane of the cubic crystal of GaAs. That is, the inclination angle θ is the angle between the substrate upper surface 100t and the (100) plane of the cubic crystal of GaAs. The inclination angle θ is, for example, an off angle. The semiconductor substrate 100 is, for example, an off substrate with an off angle of the inclination angle θ.

[0011] In the description of the embodiment, an XYZ Cartesian coordinate system is used. The direction from the semiconductor substrate 100 toward the light emitting layer 103 is defined as the Z direction. Two directions that are perpendicular to the Z direction and perpendicular to each other are defined as the X direction (second direction) and the Y direction (third direction). The direction from the substrate lower surface 100s toward the substrate upper surface 100t is, for example, parallel to the Z direction. The direction perpendicular to the substrate upper surface 100t is, for example, parallel to the Z direction. For the sake of explanation, the direction from the semiconductor substrate 100 toward the light emitting layer 103 is referred to as "up" and the opposite direction is referred to as "down". These directions are based on the relative positional relationship between the semiconductor substrate 100 and the light emitting layer 103 and are unrelated to the direction of gravity.

[0012] 1(a), in a plan view, the p-side electrode 106 is aligned with the n-side electrode 107 in the X direction. In this example, the X direction is the longitudinal direction of the semiconductor light emitting device 1. That is, for example, the length of the semiconductor substrate 100 in the X direction is longer than the length of the semiconductor substrate 100 in the Y direction. Also, for example, the length of the multilayer film portion 310 in the X direction is longer than the length of the multilayer film portion 310 in the Y direction. Also, for example, the length of the light emitting layer 103 in the X direction is longer than the length of the light emitting layer 103 in the Y direction.

[0013] The area of ​​the p-side electrode 106 is larger than the area of ​​the n-side electrode 107. In this example, the p-side electrode 106 is 350 micrometers (μm)×150 μm, and the n-side electrode 107 is 130 μm×130 μm.

[0014] 1(b), the first buffer layer 301-1 is located between the p-side electrode 106 and the substrate upper surface 100t, and between the n-side electrode 107 and the substrate upper surface 100t. The first buffer layer 301-1 is provided on the substrate upper surface 100t so as to be in contact with the substrate upper surface 100t. The first buffer layer 301-1 is, for example, an n-type GaAs layer.

[0015] The multilayer film portion 310 is located between the p-side electrode 106 and the first buffer layer 301-1, and between the n-side electrode 107 and the first buffer layer 301-1. The multilayer film portion 310 is provided on the first buffer layer 301-1 so as to be in contact with the first buffer layer 301-1. The structure of the multilayer film portion 310 will be described later with reference to FIG. 3.

[0016] As shown in FIG. 1(b), the second buffer layer 301-2 includes a first buffer portion 101a and a second buffer portion 101b. The first buffer portion 101a is arranged in the X direction with the second buffer portion 101b and is continuous with the second buffer portion 101b. The first buffer portion 101a is located between the n-side electrode 107 and the multilayer film portion 310. The second buffer portion 101b is located between the p-side electrode 106 and the multilayer film portion 310. The second buffer layer 301-2 (the first buffer portion 101a and the second buffer portion 101b) is provided on the multilayer film portion 310 so as to be in contact with the multilayer film portion 310. The second buffer layer 301-2 is, for example, an n-type GaAs layer.

[0017] The n-type cladding layer 102 is located between the second buffer portion 101b and the p-side electrode 106. The n-type cladding layer 102 is provided on the second buffer portion 101b so as to be in contact with the second buffer portion 101b. The n-type cladding layer 102 contains aluminum gallium arsenide mixed crystal (hereinafter referred to as AlGaAs) represented by the composition formula Al Y Ga 1-Y As (0 < Y < 1). For example, Al 0.5 Ga 0.5 As can be used for the n-type cladding layer 102.

[0018] The light-emitting layer 103 (active layer) is located between the n-type cladding layer 102 and the p-side electrode 106. The light-emitting layer 103 is provided on the n-type cladding layer 102 so as to be in contact with the n-type cladding layer 102. The position of the light-emitting layer 103 is above the multilayer film portion 310. That is, at least a part of the multilayer film portion 310 is located between the light-emitting layer 103 and the first buffer layer 301-1. An example of the structure of the light-emitting layer 103 will be described later with reference to FIG. 2.

[0019] The p-type cladding layer 104 is located between the light-emitting layer 103 and the p-side electrode 106. The p-type cladding layer 104 is provided on the light-emitting layer 103 so as to be in contact with the light-emitting layer 103. The p-type cladding layer 104 contains AlGaAs. For example, Al 0.5 Ga 0.5As can be used.

[0020] The p-type contact layer 105 is located between the p-type cladding layer 104 and the p-side electrode 106. The p-type contact layer 105 is provided on the p-type cladding layer 104 so as to be in contact with the p-type cladding layer 104. The p-type contact layer 105 is, for example, a p-type GaAs layer.

[0021] The n-type GaAs (semiconductor substrate 100, first buffer layer 301-1, second buffer layer 301-2) and n-type cladding layer 102 contain n-type impurities. The n-type impurities include at least one of silicon (Si), selenium (Se), and germanium (Ge), for example. The p-type cladding layer 104 and p-type contact layer 105 contain p-type impurities. The p-type impurities include at least one of beryllium (Be), magnesium (Mg), and zinc (Zn), for example.

[0022] The p-side electrode 106 is provided on the p-type contact layer 105 so as to be in contact with the p-type contact layer 105. The p-side electrode 106 includes a metal material such as gold, titanium, aluminum, or copper.

[0023] The n-side electrode 107 is provided on the first buffer portion 101a so as to be in contact with the first buffer portion 101a. The n-side electrode 107 includes a metal material such as gold, titanium, aluminum, or copper.

[0024] In this manner, the p-side electrode 106 and the n-side electrode 107 are formed on the upper surface side of the semiconductor light emitting device 1. The semiconductor light emitting device 1 emits light from the light emitting layer 103 from the surface opposite to the p-side electrode 106 and the n-side electrode 107. The lower surface (substrate lower surface 100s) of the semiconductor light emitting device 1 is a light extraction surface.

[0025] The p-side electrode 106 is, for example, an electrode for current injection. When a bias is applied to the p-side electrode 106 and the n-side electrode 107, the current injected from the p-side electrode 106 flows into the light-emitting layer 103. As a result, the light-emitting layer 103 emits light. The light from the light-emitting layer 103 passes through the second buffer layer 301-2, the multilayer film portion 310, the first buffer layer 301-1, and the semiconductor substrate 100, and is radiated to the outside from the lower surface of the semiconductor light-emitting device 1. Thus, the embodiment is a semiconductor light-emitting device that irradiates light from a surface different from the surface on which the electrode for current injection is formed.

[0026] FIG. 2 is a schematic cross-sectional view illustrating the light-emitting layer of the semiconductor light-emitting device according to the embodiment. The light-emitting layer 103 has, for example, a multi-quantum well (MQW) structure. The light-emitting layer 103 includes a plurality of quantum well layers 103a and a plurality of barrier layers 103b. The quantum well layers 103a and the barrier layers 103b are alternately stacked in the Z direction. The quantum well layer 103a is located between adjacent barrier layers 103b.

[0027] The light-emitting layer 103 is, for example, an InGaAs / AlGaAsP-based MQW active layer. That is, the quantum well layer 103a contains, for example, an indium gallium arsenide mixed crystal (hereinafter, InGaAs) represented by the composition formula In X Ga 1-X As (0 < X < 1). For example, In 0.2 Ga 0.8 As can be used for the quantum well layer 103a. The barrier layer 103b contains, for example, an aluminum gallium arsenide phosphorus mixed crystal (hereinafter, AlGaAsP) represented by the composition formula Al x Ga 1-x As 1-y P y (0 < x < 1, 0 < y < 1). For example, Al 0.15 Ga 0.85 As 0.9 P 0.1 can be used for the barrier layer 103b.

[0028] For example, the light-emitting layer 103 is set to emit light with a wavelength of 950 nanometers (nm).

[0029] 3A and 3B are schematic views illustrating the multilayer film portion of the semiconductor light emitting device according to the embodiment. Fig. 3(a) is a schematic cross-sectional view illustrating the multilayer film portion 310. The multilayer film portion 310 includes a first semiconductor layer 310a and a second semiconductor layer 310b. Fig. 3(b) is a schematic plan view of one of the second semiconductor layers 310b (second layer 20) viewed from above. For example, a plurality of first semiconductor layers 310a are provided, and a plurality of second semiconductor layers 310b are provided.

[0030] Each first semiconductor layer 310a includes a first semiconductor material. The first semiconductor material is, for example, AlGaAs. Each second semiconductor layer 310b includes a second semiconductor material. The second semiconductor material is, for example, InGaAs. As shown in FIG. 3(a), the first semiconductor layer 310a is provided on the second semiconductor layer 310b so as to be in contact with the second semiconductor layer 310b. In this example, the first semiconductor layer 310a and the second semiconductor layer 310b are alternately stacked in the Z direction. The multilayer film portion 310 is, for example, an InGaAs / AlGaAs periodic layer in which an InGaAs layer and an AlGaAs layer are alternately (periodically) stacked.

[0031] As shown in FIG. 3(a), the multiple first semiconductor layers 310a include a first layer 10. In other words, the first layer 10 is one of the first semiconductor layers 310a. The first layer 10 is a layer located at the bottom among the multiple first semiconductor layers 310a. The first layer 10 is provided on the first buffer layer 301-1 so as to be in contact with the first buffer layer 301-1. The first layer 10 has a first surface 10u. The first surface 10u is an upper surface opposite to a lower surface in contact with the first buffer layer 301-1.

[0032] The plurality of second semiconductor layers 310b includes the second layer 20. In other words, the second layer 20 is one of the second semiconductor layers 310b. The second layer 20 is provided on the first surface 10u of the first layer 10 so as to be in contact with the first surface 10u. That is, the second layer 20 is located between the first surface 10u of the first layer 10 and the light emitting layer 103. The second layer 20 has a second surface 20u. The second surface 20u is an upper surface opposite to a lower surface 20s in contact with the first layer 10.

[0033] The first surface 10u is flatter than the second surface 20u. The first layer 10 is, for example, a flat layer. The second surface 20u has greater unevenness than the first surface 10u. The second layer 20 is, for example, a non-flat layer.

[0034] Large unevenness (low flatness) corresponds to, for example, a large maximum height Rz or a large arithmetic mean roughness Ra. That is, for example, the maximum height Rz of the second surface 20u is larger than the maximum height Rz of the first surface 10u. Note that the maximum height Rz is the distance along the Z direction between the highest position of the surface (the position closest to the light emitting layer 103) and the lowest position of the surface (the position closest to the semiconductor substrate 100) in the observation range. Or, for example, the arithmetic mean roughness Ra of the second surface 20u is larger than the arithmetic mean roughness Ra of the first surface 10u.

[0035] As shown in FIG. 3(a) and FIG. 3(b), the upper surface f2 (e.g., the second surface 20u) of the second semiconductor layer 310b has a plurality of first inclined surfaces 31 and a plurality of second inclined surfaces 32. The first inclined surfaces 31 and the second inclined surfaces 32 are alternately arranged in the X direction. The first inclined surfaces 31 are inclined with respect to the X direction and the Z direction. The second inclined surfaces 32 are inclined with respect to the X direction and the Z direction. The first inclined surfaces 31 and the second inclined surfaces 32 extend in the Y direction. The first inclined surfaces 31 and the second inclined surfaces 32 are not inclined with respect to, for example, the Y direction. As shown in FIG. 3(b), for example, a boundary region between the first inclined surfaces 31 and the second inclined surfaces 32 extends along the Y direction.

[0036] For example, the first inclined surfaces 31 are arranged in the X direction at a constant period P. The first inclined surfaces 31 are inclined at an inclination angle φ with respect to the substrate upper surface 100t (see FIG. 1(b)).

[0037] 3(a), the first inclined surface 31 and the second inclined surface 32 are repeatedly arranged in the X direction, so that the thickness (length along the Z direction) of the second semiconductor layer 310b varies in the X direction. On the other hand, the thickness of the first layer 10 does not substantially vary along the X direction and is constant. The lower surface of the first layer 10 is flat, as is the upper surface (first surface 10u) of the first layer 10. The lower surface and the upper surface of the first layer 10 extend on the XY plane and are, for example, substantially parallel to each other.

[0038] The size of the unevenness and the film thickness can be evaluated by observing a cross section including the direction in which the first inclined surfaces 31 are repeatedly arranged (e.g., the X direction) and the Z direction, as shown in Fig. 3(a), with a transmission electron microscope (TEM). The width of the observation range used for the evaluation is set to a size that allows, for example, the entirety of at least one first inclined surface 31 and the entirety of at least one second inclined surface 32 to be observed.

[0039] In this way, the multilayer film section 310 includes the first layer 10 (flat layer) and the second layer 20 (non-flat layer) laminated on the first layer 10 and having a lower flatness than the first layer 10. That is, the unevenness of the second surface 20u of the second layer 20 is larger than the unevenness of the first surface 10u of the first layer 10. By providing such a non-flat layer, the light from the light emitting layer 103 is refracted and spreads when passing through the multilayer film section 310. That is, the multilayer film section 310 functions as, for example, a light diffusion layer. This can improve the light intensity distribution on the light extraction surface, and can improve the light emission characteristics. For example, the area with high light emission intensity on the light extraction surface can be expanded, and the light extraction efficiency can be improved.

[0040] For example, the shapes of the flat layer (first layer 10) and the non-flat layer (second layer 20) can be formed by crystal growth using a semiconductor substrate having a substrate upper surface 100t that is inclined with respect to the (100) plane. For example, the first buffer layer 301-1, the multilayer film portion 310, the second buffer layer 301-2, the n-type cladding layer 102, the light emitting layer 103, the p-type cladding layer 104, and the p-type contact layer 105 can be fabricated in a single continuous process using crystal growth by metalorganic chemical vapor deposition (MOCVD) with the semiconductor substrate 100 as a growth substrate.

[0041] In this case, the first layer 10 and the second layer 20 are, for example, single crystals. For example, when the cross section is observed by TEM as described above, if the first layer 10 is a crystal in which crystal lattices are connected without being divided at the interface of crystal defects or grain boundaries, the first layer 10 can be regarded as a single crystal, and if the second layer 20 is a crystal in which crystal lattices are connected without being divided at the interface of crystal defects or grain boundaries, the second layer 20 can be regarded as a single crystal. For example, the first surface 10u and the second surface 20u are crystal surfaces, and the surface orientation of the second surface 20u is different from the surface orientation of the first surface 10u. For example, the surface orientation of the first inclined surface 31 is different from the surface orientation of the first surface 10u. The surface orientation of the second inclined surface 32 is different from the surface orientation of the first surface 10u. In addition, the surface orientation of the first inclined surface 31 is different from the surface orientation of the second inclined surface 32.

[0042] The surface orientation of the first surface 10u may be the same as the surface orientation of the substrate upper surface 100t of the semiconductor substrate 100. The inclination angle φ of the first inclined surface 31 of the second surface 20u depends on the surface orientation of the substrate upper surface 100t. For example, the first inclined surface 31 extends along a direction parallel to the (100) surface of the semiconductor substrate 100. For example, the inclination angle φ of the first inclined surface 31 is the same as the inclination angle θ of the substrate upper surface 100t. For example, the first inclined surface 31 is a (100) surface. Note that in FIG. 3(a) and FIG. 8(b) described later, the inclination angle φ is displayed large for ease of viewing.

[0043] Example 1 4, 5(a) and 5(b) are images illustrating a portion of the semiconductor light emitting device according to the embodiment. 4 shows a cross-sectional TEM image of a layer structure in which a first buffer layer 301-1, a multilayer film portion 310 (InGaAs / AlGaAs periodic layer), and a second buffer layer 301-2 are grown using a semiconductor substrate 100 in which a substrate upper surface 100t, which is the crystal growth surface of the semiconductor substrate 100, is tilted 15° in the

[0011] direction from the (100) plane. Here, the multilayer film portion 310 has a five-layer structure of AlGaAs / InGaAs / AlGaAs / InGaAs / AlGaAs. The In X Ga 1-X The In composition of As is 0.1, and Al Y Ga 1-Y The Al composition Y of As is set to 0.1.

[0044] The various raw materials used in the MOCVD growth to create this layer structure include, for example, group III raw materials such as trimethylindium: (CH3)3In:TMI, trimethylgallium: (CH3)3Ga:TMG, and trimethylaluminum: (CH3)3Al:TMA, and group V raw materials such as arsine: AsH3 and phosphine: PH3. Other growth conditions include a temperature of 700°C and a pressure of 5 kPa.

[0045] As shown in FIG. 4, the flatness of the InGaAs film (white contrast in the figure) is lost, a film thickness distribution is observed, and the shape is dependent on the tilt angle of the substrate. Furthermore, the shape dependent on the tilt angle of the substrate has a crystal plane, which is periodically formed. Thus, although the flatness is lost and a film thickness distribution is observed, the single crystallinity is maintained, and no crystal defects are observed in the InGaAs film or at the interface with the upper layer AlGaAs, which would damage the upper layer stack. On the other hand, although the flatness of AlGaAs is lost, the film thickness is relatively uniform, and it was also found that the second buffer layer 301-2 stacked as the upper layer can be grown flat. According to the inventor's intensive experiments, it was found that such a shape can be created by reducing the supply ratio of the group V raw material to the group III raw material (V / III ratio), which is a condition for MOCVD growth, and specifically, it was possible to create it by making the V / III ratio 50 or less.

[0046] Figures 5(a) and 5(b) are TEM images of a structure in which the inclination angle of the substrate upper surface 100t is changed from 15° in the structure of Figure 4. In Figure 5(a), the inclination angle of the substrate upper surface 100t is 2°, and in Figure 5(b), the inclination angle of the substrate upper surface 100t is 5°.

[0047] It can be seen that the shape of the multilayer film portion 310 (InGaAs / AlGaAs periodic layer) changes depending on the tilt angle of the substrate. In this way, the shape of the multilayer film portion 310 can be adjusted by the tilt angle of the substrate.

[0048] FIG. 6 is a graph illustrating the emission intensity distribution in a semiconductor light emitting device. 7(a) and 7(b) are schematic plan views illustrating the emission intensity distribution in a semiconductor light emitting device. 6 shows the emission intensity distribution of the semiconductor light emitting device 9 of the reference example and the emission intensity distribution of the semiconductor light emitting device 1a according to the embodiment. The semiconductor light emitting device 9 of the reference example does not include the multilayer film portion 310. In other respects, the semiconductor light emitting device 9 is similar to the semiconductor light emitting device 1 described above.

[0049] When a bias is applied to the p-side electrode 106 and the n-side electrode 107, a current injected from the p-side electrode 106 flows into the light-emitting layer 103, and the light-emitting layer 103 emits light along the shape of the p-side electrode 106. Figures 6, 7(a) and 7(b) show the light emission intensity distribution on the light extraction surface when a bias current of 5 mA is applied. Figure 6 shows the light emission intensity distribution in the longitudinal direction (X direction) of the device structure, and the light emission intensity is normalized. Note that "0" on the horizontal axis of Figure 6 is the position of the end of the p-side electrode 106 on the n-side electrode 107 side. The solid line in Figure 6 represents the light emission intensity distribution in the semiconductor light-emitting device 9. Light emission is thus obtained along the shape of the p-side electrode 106, but the intensity decreases toward the electrode end. This is because the light from the light-emitting layer 103 includes a component that is directly radiated outside the device and a component that is repeatedly reflected multiple times inside the device structure and is radiated outside the device, and the emission intensity distribution at the light extraction surface is determined by the superposition of these light components in addition to the distribution along the shape of the current injection electrode. Figure 7(a) is a bottom view of the light extraction side of the semiconductor light-emitting device 9. Figure 7(a) shows a light-emitting region R with a normalized emission intensity of 0.9 or more. Even with a back-emitting device structure that takes into account light shielding by the electrode, the light extraction intensity distribution does not necessarily have approximately the same area as the shape of the current injection electrode, and improvement was required.

[0050] In response to this, it is possible to process the shape of the light extraction surface or to create a structure for diffusing light inside the device structure. However, adding these processes will complicate the device fabrication process. Also, it is difficult to change the inside of the device structure in a single fabrication process, and this will increase the number of steps. Furthermore, it is possible to create a textured layer between the light-emitting layer and the light extraction surface, for example by mechanical processing, as a structure for diffusing light. However, if crystal defects occur due to the textured shape, this may have an adverse effect on the characteristics of the light-emitting layer.

[0051] In response to this, the inventors conducted extensive experiments and found that a non-flat layer can be formed by changing the formation method using the same material as the device constituent layers, and that it can be produced in a single MOCVD process, making it useful as a light diffusing layer. That is, a non-flat layer can be formed using the MOCVD method as described with reference to FIG.

[0052] The semiconductor light emitting device 1a shown in FIG. 6 and FIG. 7(b) is different from the semiconductor light emitting device 9 of the reference example in that a multilayer film portion 310 is formed between the first buffer layer 301-1 and the second buffer layer 301-2. In the semiconductor light emitting device 1a, a substrate with a crystal growth surface inclined 15° from the (100) plane toward the

[0011] direction is used as the semiconductor substrate 100. Here, the V / III ratio during growth of the multilayer film portion 310 is set to 30, and the V / III ratio of the light emitting layer 103 using the same material system is set to 200, so that a non-flat layer is formed in the multilayer film portion 310, and the upper layer, the second buffer layer 301-2, can be embedded flatly, and the light emitting layer 103 can be made into a flat layer. In addition, the number of periods (the number of InGaAs layers repeatedly stacked) of the multilayer film portion 310 is set to 10, and the total thickness of the InGaAs thick film portion (the total thickness (d) of the plurality of second semiconductor layers 310b) is set to 160 nm.

[0053] Fig. 6 shows the emission intensity distribution on the light extraction surface when a bias current of 5 mA is applied to the semiconductor light emitting device 1a fabricated in this manner. The dotted line in Fig. 6 represents the emission intensity distribution in the semiconductor light emitting device 1a. Fig. 7(b) is a bottom view of the light extraction side of the semiconductor light emitting device 1a. Fig. 7(b) shows the light emitting region R where the normalized emission intensity is 0.9 or more.

[0054] As can be seen from this result, the light extraction area is expanded by adopting the multilayer film portion 310 in the structure. This is thought to be because when the light emitted from the light emitting layer 103 passes through the multilayer film portion 310 inside the device structure, and each time it passes through due to multiple reflections, the refraction state of the light is diffused differently from that in the structure of the reference example. Therefore, in this embodiment, a non-flat layer (InGaAs / AlGaAs periodic layer) capable of diffusing light can be created in a single MOCVD growth process, and as a result, the light extraction efficiency is improved. Excellent effects were obtained in terms of productivity and characteristic improvement.

[0055] 3, in the multilayer film section 310, when a plurality of first semiconductor layers 310a and a plurality of second semiconductor layers 310b are stacked, the total thickness of the plurality of second semiconductor layers 310b may be equal to or greater than the thickness at which light from the light emitting layer 103 is refracted. For example, when the total thickness of the plurality of second semiconductor layers 310b is d, the wavelength of light from the light emitting layer 103 is λ, and the effective refractive index of the second layer 20 at the wavelength (λ) is n, it is desirable that the formula d ≧ λ / (2n) is satisfied. This allows the light from the light emitting layer 103 to be refracted in the multilayer film section 310, making it easy to expand the light emitting region.

[0056] Here, as shown in FIG. 3(a), the plurality of second semiconductor layers 310b includes a bottom layer (second layer 20) of the second semiconductor layers 310b that is closest to the semiconductor substrate 100, and a top layer (third layer 22) of the second semiconductor layers 310b that is closest to the light emitting layer 103. In this case, the total thickness (d) of the plurality of second semiconductor layers 310b is the length along the Z direction between the bottom end of the bottom layer (the point of the second layer 20 that is closest to the substrate) and the top end of the top layer (the point of the third layer 22 that is closest to the light emitting layer). The total thickness (d) of the plurality of second semiconductor layers 310b is the thickness of a range including the first semiconductor layer 310a located between the second semiconductor layers 310b, as shown in FIG. 3(a). The total thickness (d) of the plurality of second semiconductor layers 310b is, for example, 150 nm or more.

[0057] In the multilayer film portion 310, the first semiconductor layers 310a and the second semiconductor layers 310b are alternately provided in multiple layers, thereby increasing the number of interfaces between the first semiconductor layers 310a and the second semiconductor layers 310b. This allows light from the light emitting layer 103 to be diffused by, for example, refraction at the interfaces.

[0058] As already described with reference to FIG. 3(a), the second surface 20u of the second layer 20 has, for example, a crystal plane with a different plane orientation from the first surface 10u of the first layer 10. The second layer 20 is, for example, a single crystal. For example, the inclination angle φ (FIG. 3(a)) of the first inclined surface 31 of the second layer 20 depends on the inclination angle θ (FIG. 1(b)) of the semiconductor substrate 100. For example, the inclination angle φ is the same as the inclination angle θ. Such shapes of the first layer 10 and the second layer 20 can be formed by crystal growth. Compared to creating an uneven shape in a device by etching or mechanical processing, the occurrence of crystal defects can be suppressed.

[0059] Example 2 8A and 8B are schematic cross-sectional views illustrating the semiconductor light emitting device according to the embodiment. FIG. 8(a) shows a semiconductor light emitting device 2 according to an embodiment. FIG. 8(b) shows a structure of a multilayer film portion 310 of the semiconductor light emitting device 2. The structure of the semiconductor light emitting device 2 differs from that of the semiconductor light emitting device 1 in that the multilayer film portion 310 (InGaAs / AlGaAs periodic layer) has a two-layer structure in which each of AlGaAs / InGaAs monolayers is combined, and the thickness D of the thick film portion of the InGaAs layer is set to 150 nm. That is, the multilayer film portion 310 in the embodiment may have a two-layer structure having only two layers, the first layer 10 and the second layer 20. The thickness D is the distance in the Z direction between the upper end and the lower end of the second layer 20 (InGaAs layer), i.e., the maximum length in the Z direction.

[0060] In the semiconductor light emitting device 2, the number of interfaces of non-flat surfaces is reduced compared to the semiconductor light emitting device 1. However, even in this case, compared to the semiconductor light emitting device 9 of the reference example, the light from the light emitting layer 103 is refracted by the second layer 20, which is a non-flat layer, and the effect of expanding the light emitting area at the light extraction surface is obtained. Furthermore, when adopting this structure, it was found that the structure becomes flat with only a single InGaAs layer, and the effect may not be obtained. Therefore, it was found that it is desirable to use an alloy layer containing Al (here, an AlGaAs layer) as the base in order to obtain a non-flat layer. This is thought to be because, for example, an Al alloy layer formed under growth conditions with a relatively low V / III ratio plays a role in transmitting the inclination state of the crystal plane orientation to the upper layer.

[0061] For example, when the multilayer film section 310 has a two-layer structure of the first layer 10 and the second layer 20, it is desirable to satisfy the formula d1≧λ / (2n), where d1 is the thickness of the multilayer film section 310, λ is the wavelength of light from the light emitting layer 103, and n is the effective refractive index of the second layer 20 at that wavelength (λ). This allows the light from the light emitting layer 103 to be refracted in the multilayer film section 310, making it easy to expand the light emitting region.

[0062] Here, the thickness (d1) of the multilayer film portion 310 in the case of a two-layer structure is the length along the Z direction between the bottom end of the first layer 10 (the point of the first layer 10 closest to the substrate) and the top end of the second layer 20 (the point of the second layer 20 closest to the light emitting layer). The thickness (d1) of the multilayer film portion 310 in the case of a two-layer structure is, for example, 150 nm or more.

[0063] The embodiment of the present invention is not limited to the above. The inclination direction of the plane orientation of the semiconductor substrate 100 is set to

[0011] , but is not limited to this, and a similar effect can be obtained if the orientation is equivalent to this. For example, the substrate upper surface 100t of the semiconductor substrate 100 is inclined in any of the

[0011] , [01-1], [0-1-1], and [0-11] directions of the cubic crystal with respect to the (100) plane of the GaAs. For example, the direction perpendicular to the substrate upper surface 100t may be a direction inclined by an inclination angle θ in any of the

[0011] , [01-1], [0-1-1], and [0-11] directions from the

[0100] direction.

[0064] The inclination angle θ may be any angle that, for example, impairs the flatness of the InGaAs layer of the multilayer film portion 310. As shown in Figs. 4, 5(a) and 5(b), the shape can be adjusted depending on the inclination angle. However, if the inclination angle θ exceeds 25°, for example, the crystal growth itself may be adversely affected, inducing defects in the growth process of the device constituent layers, resulting in deterioration of characteristics. Therefore, it is preferable that the inclination angle θ is 1° or more and 25° or less. However, the embodiment is not necessarily limited to this.

[0065] In the above embodiment, the In composition of the InGaAs layer of the multilayer film portion 310 is set to 0.1, but this is not limited thereto, and any composition that is transparent to the light emitted from the light emitting layer 103 can be selected.

[0066] FIG. 9 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to the embodiment. 9 differs from the above-described semiconductor light emitting devices 1 and 2 in the arrangement of a multilayer film portion 310. In the semiconductor light emitting device 3, the first buffer layer 301-1 and the second buffer layer 301-2 described with reference to FIG. 1(b) etc. are not provided, and instead a buffer layer 301 is provided. The multilayer film portion 310 is provided on the buffer layer 301.

[0067] The buffer layer 301 is provided on the substrate upper surface 100t of the substrate 100 so as to be in contact with the substrate upper surface 100t. The buffer layer 301 is, for example, an n-type GaAs layer. The buffer layer 301 has a first portion 301a provided between the substrate upper surface 100t and the n-side electrode 107, and a second portion 301b provided between the substrate upper surface 100t and the p-side electrode 106. The first portion 301a is aligned with the second portion 301b in the X direction. The second portion 301b is thicker than the first portion 301a. A step is provided on the upper surface of the buffer layer 301 (the surface opposite to the substrate 100).

[0068] The multilayer film portion 310 is located between the second portion 301b of the buffer layer 301 and the p-side electrode 106. The multilayer film portion 310 is provided on the second portion 301b of the buffer layer 301 so as to be in contact with the second portion 301b. The multilayer film portion 310 is not provided between the buffer layer 301 and the n-side electrode 107. In other words, the multilayer film portion 310 is not provided on the first portion 301a.

[0069] The multilayer film section 310 has the same structure as the multilayer film section 310 described with reference to FIG. 3(a) or FIG. 8(b). That is, the multilayer film section 310 has a structure in which a first semiconductor layer 310a (see FIG. 3(a)) and a second semiconductor layer 310b (see FIG. 3(a)) are laminated. The multilayer film section 310 includes a first layer 10 (see FIG. 3(a)) which is a flat layer and a second layer 20 (see FIG. 3(a)) which is a non-flat layer. However, in this example, the first layer 10 is laminated on the buffer layer 301.

[0070] The n-type cladding layer 102, the light emitting layer 103, the p-type cladding layer 104, and the p-type contact layer 105 are located between the multilayer film portion 310 and the p-side electrode 106. The n-type cladding layer 102 is provided on the multilayer film portion 310 so as to be in contact with the multilayer film portion 310. As in the above-described semiconductor light emitting device 1, the light emitting layer 103, the p-type cladding layer 104, the p-type contact layer 105, and the p-side electrode 106 are laminated on the n-type cladding layer 102. The n-side electrode 107 is provided on the first portion 301a of the buffer layer 301 so as to be in contact with the first portion 301a.

[0071] When a bias is applied to the p-side electrode 106 and the n-side electrode 107, a current injected from the p-side electrode 106 flows into the light-emitting layer 103, causing the light-emitting layer 103 to emit light. Light from the light-emitting layer 103 passes through the multilayer film portion 310, the buffer layer 301, and the semiconductor substrate 100, and is emitted to the outside from the bottom surface of the semiconductor light-emitting device 3.

[0072] In the semiconductor light emitting device 3, it is not necessary to stack a buffer layer on the multilayer film portion 310. Therefore, in manufacturing the semiconductor light emitting device, the load on the equipment for forming the buffer layer can be reduced. For example, the manufacturing cost can be reduced.

[0073] A current injected from the p-side electrode 106 flows to the n-side electrode 107 via the light emitting layer 103, the n-type cladding layer 102, the multilayer film portion 310, and the buffer layer 301. That is, the multilayer film portion 310 is present in the path of a current flowing between the p-side electrode 106 and the n-side electrode 107. Therefore, for example, the multilayer film portion 310 is doped with an n-type impurity. That is, in the semiconductor light emitting device 3, the multilayer film portion 310 has n-type conductivity. This ensures conductivity and suppresses an increase in the operating voltage.

[0074] In the multilayer film portion 310, for example, an InGaAs layer and an AlGaAs layer are laminated. For example, the multilayer film portion 310 is an InGaAs / AlGaAs periodic layer in which InGaAs layers and AlGaAs layers are alternately laminated. It is effective to dope the InGaAs layer and the AlGaAs layer with an appropriate n-type impurity concentration. That is, the InGaAs layer and the AlGaAs layer have different band gaps, and therefore have different activation rates of the doped impurity. Therefore, in order to obtain the same effective carrier concentration, the impurities are doped with different concentrations. Specifically, the impurity doping concentration in the AlGaAs layer with a large band gap is made higher than the impurity doping concentration in the InGaAs layer with a small band gap.

[0075] For example, the concentration of n-type impurities in an InGaAs layer is 1×10 17 atoms / cm3 More than 3×10 17 atoms / cm 3 For example, the concentration of n-type impurities in an AlGaAs layer is 1×10 17 atoms / cm 3 More than 3×10 17 atoms / cm 3 This makes it possible to suppress the influence on the operating voltage. The n-type impurity is, for example, at least one of Si, Se, and Ge.

[0076] In the structure described with reference to FIG. 1(b), the current flowing between the p-side electrode 106 and the n-side electrode 107 passes through the light emitting layer 103, the n-type cladding layer 102, and the second buffer layer 301-2. In the structure of FIG. 1(b), the current flowing between the p-side electrode 106 and the n-side electrode 107 does not need to pass through the multilayer film portion 310. In this case, the multilayer film portion 310 does not need to be doped with n-type impurities. For example, in the structure of FIG. 1(b), the electrical resistivity of the multilayer film portion 310 is higher than that of the second buffer layer 301-2 and higher than that of the substrate 100. In the structure of FIG. 1(b), the multilayer film portion 310 with a relatively high electrical resistivity is disposed directly below the second buffer layer 301-2, so that when the second buffer layer 301-2 is thin, the current path in the second buffer layer 301-2 becomes narrow. This increases the electrical resistance between the p-side electrode 106 and the n-side electrode 107. On the other hand, in the structure of FIG. 9, the substrate 100 is disposed directly below the buffer layer 301. Part of the current may flow between the p-side electrode 106 and the n-side electrode 107 via the substrate 100. This makes it possible to suppress, for example, an increase in the electrical resistance between the p-side electrode 106 and the n-side electrode 107. For example, it is possible to suppress an increase in the operating voltage of the semiconductor light emitting device.

[0077] 10(a) to 10(e) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor light emitting device according to the embodiment. The manufacturing method of the semiconductor light emitting devices 1 and 2 includes a lamination process of successively forming, by a single MOCVD process, a laminate including a first buffer layer 301-1, a multilayer film portion 310, a second buffer layer 301-2, an n-type cladding layer 102, an emission layer 103, a p-type cladding layer 104, and a p-type contact layer 105 on a semiconductor substrate 100. For example, a laminate from the lower first buffer layer 301-1 to the upper p-type contact layer 105 is formed without removing the semiconductor substrate 100 from a chamber.

[0078] The lamination process includes supplying a first source gas containing a group V element and a second source gas containing a group III element. For example, a V / III ratio is defined for the source gas containing the first source gas and the second source gas. The V / III ratio is the ratio of the number of atoms of the group V element supplied per unit time to the number of atoms of the group III element supplied per unit time. Each layer is formed by appropriately changing the ratio of the source gas.

[0079] As shown in FIG. 10(a), a first buffer layer 301-1 is formed on a semiconductor substrate 100. Then, as shown in FIG. 10(b), a multilayer film portion 310 is formed in a state in which the V / III ratio is smaller than that when the first buffer layer 301-1 is formed. Then, as shown in FIG. 10(c), a second buffer layer 301-2, an n-type cladding layer 102, an emission layer 103, a p-type cladding layer 104, and a p-type contact layer 105 are sequentially laminated in a state in which the V / III ratio is larger than that when the multilayer film portion 310 is formed. The steps from FIG. 10(a) to FIG. 10(c) are performed as a single crystal growth by the MOCVD method. The raw materials and growth conditions in the MOCVD method are as already described with reference to FIG. 4, for example.

[0080] 10(d), the n-type cladding layer 102, the light emitting layer 103, the p-type cladding layer 104, and a portion of the p-type contact layer 105 are removed by, for example, etching to expose the first buffer portion 101a of the second buffer layer 301-2. Then, as shown in FIG. 10(e), the n-side electrode 107 is formed on the first buffer portion 101a, and the p-side electrode 106 is formed on the p-type contact layer 105 by, for example, sputtering.

[0081] In this way, the multilayer film portion 310 can be produced in a single MOCDV continuous process in the same manner as the other device constituent layers. This allows for a light-emitting device with high productivity. In addition, for example, the light-emitting layer 103 and the multilayer film portion 310 (first layer 10 and second layer 20) are made of the same material system. That is, for example, the light-emitting layer 103 contains the same group V element as the group V element contained in the second layer 20, and the same group III element as the group III element contained in the first layer 10. By using the same material system, productivity can be improved.

[0082] The semiconductor light emitting device 3 described with reference to FIG. 9 can also be formed by the same manufacturing method as above. That is, the manufacturing method of the semiconductor light emitting device 3 includes a lamination step of continuously forming a laminate including the buffer layer 301, the multilayer film portion 310, the n-type cladding layer 102, the light emitting layer 103, the p-type cladding layer 104, and the p-type contact layer 105 on the semiconductor substrate 100 by a single MOCVD process. In manufacturing the semiconductor light emitting device 3, the buffer layer 301 is formed on the semiconductor substrate 100. Thereafter, the multilayer film portion 310 is formed in a state in which the V / III ratio is smaller than when the buffer layer 301 is formed. Thereafter, the n-type cladding layer 102, the light emitting layer 103, the p-type cladding layer 104, and the p-type contact layer 105 are sequentially laminated in a state in which the V / III ratio is larger than when the multilayer film portion 310 is formed. Thereafter, the multilayer film portion 310, the n-type cladding layer 102, the light emitting layer 103, the p-type cladding layer 104, and the p-type contact layer 105 are partially removed by, for example, etching to expose the first portion 301a of the buffer layer 301. An n-side electrode 107 is formed on the first portion 301a, and a p-side electrode 106 is formed on the p-type contact layer 105.

[0083] The embodiment may include the following features. (Configuration 1) A light-emitting layer; a semiconductor substrate including cubic gallium arsenide (GaAs) and having a substrate lower surface and a substrate upper surface located between the light emitting layer and the substrate lower surface and inclined with respect to a (100) plane of the cubic crystal; a multilayer film section including: a first layer located between the upper surface of the substrate and the light emitting layer, the first layer having a first surface; and a second layer located between the first surface and the light emitting layer, the second layer being in contact with the first surface extending along a plane parallel to the upper surface of the substrate and having a second surface opposite to the surface in contact with the first surface, wherein unevenness of the second surface is greater than unevenness of the first surface, and light from the light emitting layer is emitted through the multilayer film section; A semiconductor light emitting device comprising: (Configuration 2) The multilayer film portion is a plurality of first semiconductor layers including the first layer, each of the first semiconductor layers including a first semiconductor material; A plurality of second semiconductor layers that are alternately laminated with the plurality of first semiconductor layers, include the second layer, and each contain a second semiconductor material; The semiconductor light-emitting device according to Configuration 1, including the same. (Configuration 3) The semiconductor light-emitting device according to Configuration 1 or 2, wherein the second surface has a crystal plane with a plane orientation different from that of the first surface. (Configuration 4) The semiconductor light-emitting device according to Configuration 3, wherein the second layer is a single crystal. (Configuration 5) The first layer contains at least aluminum, The second layer contains indium gallium arsenide (InGaAs) represented by the composition formula In x Ga 1-x As (0 < x < 1), and is the semiconductor light-emitting device according to any one of Configurations 1 to 4. (Configuration 6) The plurality of second semiconductor layers include a lowermost layer closest to the semiconductor substrate among the plurality of second semiconductor layers and an uppermost layer closest to the light-emitting layer among the plurality of second semiconductor layers, When the distance along the Z direction from the semiconductor substrate to the light-emitting layer between the lower end of the lowermost layer and the upper end of the uppermost layer is d, the wavelength of the light from the light-emitting layer is λ, and the effective refractive index of the second layer at the wavelength is n, the formula d ≧ λ / (2·n) is satisfied. The semiconductor light-emitting device according to Configuration 2. (Configuration 7) The multilayer film portion has a two-layer structure of the first layer and the second layer, When the thickness of the multilayer film portion is d1, the wavelength of the light from the light-emitting layer is λ, and the effective refractive index of the second layer at the wavelength is n, the formula d1 ≧ λ / (2·n) is satisfied. The semiconductor light-emitting device according to Configuration 1. (Configuration 8) The upper surface of the substrate is inclined in any one of the

[0011] direction, [01-1] direction, [0-1-1] direction, and [0-11] direction of the cubic crystal with respect to the (100) plane of the cubic crystal. The semiconductor light-emitting device according to any one of Configurations 1 to 7. (Configuration 9) 9. The semiconductor light emitting device according to any one of configurations 1 to 8, wherein the upper surface of the substrate is inclined at an angle of 1° to 25° with respect to a (100) plane of the semiconductor substrate. (Configuration 10) the second surface has a first inclined surface inclined with respect to an upper surface of the substrate, 10. The semiconductor light emitting device according to any one of configurations 1 to 9, wherein an inclination angle of the first inclined surface with respect to the upper surface of the substrate is the same as an inclination angle of the upper surface of the substrate with respect to the (100) plane. (Configuration 11) The method includes forming a multilayer film portion and a light emitting layer above a semiconductor substrate upper surface including cubic gallium arsenide (GaAs) and having a substrate upper surface inclined with respect to a (100) plane of the cubic crystal by a metal-organic chemical vapor deposition method in one step; the multilayer film portion includes a first layer located above the upper surface of the substrate and having a first surface extending along a plane parallel to the upper surface of the substrate, and a second layer provided on the first surface and having a second surface in contact with the first surface and opposite to the surface in contact with the first surface, The unevenness of the second surface is larger than the unevenness of the first surface, A method for manufacturing a semiconductor light emitting device, wherein the light emitting layer is located above the multilayer film portion. (Configuration 12) the second layer includes a group V element and a group III element, 12. The method of claim 11, wherein the light-emitting layer contains a group V element that is the same as the group V element of the second layer, and a group III element that is the same as the group III element of the second layer. (Configuration 13) 13. The method according to claim 11, wherein a V / III ratio during growth of the multilayer film portion is lower than a V / III ratio during growth of the light-emitting layer.

[0084] According to the embodiment, it is possible to provide a semiconductor light emitting device capable of improving light emitting characteristics.

[0085] In this specification, "vertical" and "parallel" do not only mean strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may mean substantially vertical and substantially parallel.

[0086] Although some embodiments of the present invention have been illustrated above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments can be implemented in combination with each other. [Explanation of symbols]

[0087] 1, 1a, 2, 3, 9: Semiconductor light-emitting device 10: 1st layer 10u: 1st page 20: 2nd layer 20u: 2nd side 22:Third layer 31: 1st slope 32:Second slope 100: Semiconductor substrate 100s:Bottom surface of the board 100t: Top surface of the board 101a: First buffer portion 101b: Second buffer part 102: n-type cladding layer 103: Light-emitting layer 103a: Quantum well layer 103b: Barrier layer 104: p-type cladding layer 105: p-type contact layer 106:p side electrode 107:n side electrode 301: Buffer layer 301a: Part 1 301b:Second part 301-1: First buffer layer 301-2: Second buffer layer 310: Multilayer film part 310a: First semiconductor layer 310b: second semiconductor layer D: Film thickness P: Cycle R: Light field f2: above θ: Tilt angle φ: Tilt angle

Claims

1. A light-emitting layer; a semiconductor substrate including cubic gallium arsenide (GaAs), the semiconductor substrate having a substrate lower surface and a substrate upper surface located between the light emitting layer and the substrate lower surface and inclined with respect to a (100) plane of the cubic crystal; a multilayer film section including: a first layer located between the upper surface of the substrate and the light emitting layer, the first layer having a first surface extending along a plane parallel to the upper surface of the substrate; and a second layer located between the first surface and the light emitting layer, the second layer having a second surface in contact with the first surface and opposite to the surface in contact with the first surface, wherein unevenness of the second surface is greater than unevenness of the first surface, and light from the light emitting layer is emitted through the multilayer film section; A semiconductor light emitting device comprising:

2. The multilayer film portion is a plurality of first semiconductor layers including the first layer, each of the first semiconductor layers including a first semiconductor material; a plurality of second semiconductor layers alternately stacked with the plurality of first semiconductor layers and including the second layer, each of the second semiconductor layers including a second semiconductor material; The semiconductor light emitting device of claim 1 .

3. The semiconductor light emitting device according to claim 1 , wherein the second surface has a crystal plane having a different plane orientation from that of the first surface.

4. The semiconductor light emitting device of claim 3 , wherein the second layer is single crystal.

5. the first layer includes at least aluminum; The second layer has the composition formula In ｘ G １－ｘ 3. The semiconductor light emitting device according to claim 1, further comprising indium gallium arsenide (InGaAs) represented by the formula: InGaAs (0<x<1).

6. the second semiconductor layers include a lowermost layer among the second semiconductor layers that is closest to the semiconductor substrate, and an uppermost layer among the second semiconductor layers that is closest to the light emitting layer, 3. The semiconductor light-emitting device according to claim 2, wherein the formula d ≧ λ / (2 n) is satisfied, where d is a distance along the Z direction from the semiconductor substrate to the light-emitting layer between a lower end of the lowermost layer and an upper end of the uppermost layer, λ is a wavelength of light from the light-emitting layer, and n is an effective refractive index of the second layer at said wavelength.

7. the multilayer film portion has a two-layer structure including the first layer and the second layer, 2. The semiconductor light-emitting device according to claim 1, wherein the formula d1 ≧ λ / (2·n) is satisfied, where d1 is a thickness of the multilayer film portion, λ is a wavelength of light from the light-emitting layer, and n is an effective refractive index of the second layer at said wavelength.

8. 3. The semiconductor light-emitting device according to claim 1, wherein the upper surface of the substrate is inclined relative to a (100) plane of the cubic crystal in any one of a [011] direction, a [01-1] direction, a [0-1-1] direction, and a [0-11] direction of the cubic crystal.

9. 3. The semiconductor light emitting device according to claim 1, wherein the upper surface of the substrate is inclined at an angle of 1° to 25° with respect to a (100) plane of the semiconductor substrate.

10. the second surface has a first inclined surface inclined with respect to an upper surface of the substrate, 3. The semiconductor light emitting device according to claim 1, wherein an inclination angle of the first inclined surface with respect to the upper surface of the substrate is the same as an inclination angle of the upper surface of the substrate with respect to the (100) plane.

11. The method includes a step of forming a multilayer film portion and a light emitting layer above a semiconductor substrate upper surface including cubic gallium arsenide (GaAs) and having a substrate upper surface inclined with respect to a (100) plane of the cubic crystal, by a metal-organic chemical vapor deposition method in one step; the multilayer film portion includes a first layer located above the upper surface of the substrate and having a first surface extending along a plane parallel to the upper surface of the substrate, and a second layer provided on the first surface and having a second surface in contact with the first surface and opposite to a surface in contact with the first surface, The unevenness of the second surface is larger than the unevenness of the first surface, A method for manufacturing a semiconductor light emitting device, wherein the light emitting layer is located above the multilayer film portion.

12. the second layer includes a group V element and a group III element, The method according to claim 11 , wherein the light-emitting layer contains a group V element that is the same as the group V element of the second layer, and a group III element that is the same as the group III element of the second layer.

13. The method according to claim 11 or 12, wherein a V / III ratio during growth of the multilayer film portion is lower than a V / III ratio during growth of the light emitting layer.

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