Semiconductor device drive device

Abstract

To provide a technique that enables the type of error state to be identified early from an external identification signal.SOLUTION: A semiconductor device drive device includes a plurality of error state detection circuits that generate error signals corresponding to error states, an error state identification signal generation circuit that generates an error state identification signal having a waveform that differs for each type of error state and a smaller pulse width than each error signal on the basis of the plurality of error signals generated by the plurality of error state detection circuits, and an error state identification signal output terminal that outputs the error state identification signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor element driving device. [Background technology]

[0002] Various technologies have been proposed for semiconductor element driving devices that drive semiconductor elements. For example, Patent Document 1 proposes a technology in which a semiconductor element driving device generates an identification signal with a different pulse width for each error state, thereby enabling an external control device to identify the type of error state from the identification signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-93065 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the conventional technology, the pulse width of the identification signal is larger than the pulse width of the error signal for each error state, so the time from when the output of the identification signal starts to when it ends is long, which causes a problem that the external control device cannot quickly identify the type of error state from the identification signal.

[0005] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique that enables the type of error state to be identified early from an external identification signal. [Means for solving the problem]

[0006] The semiconductor element driving device according to the present disclosure is a semiconductor element driving device that drives a semiconductor element, and includes a plurality of error state detection circuits, each of which detects an error state of the semiconductor element or the semiconductor element driving device and generates an error signal corresponding to the detected error state, an error state identification signal generation circuit that generates, based on the plurality of error signals generated by the plurality of error state detection circuits, an error state identification signal that has a different waveform for each type of error state and has a smaller pulse width than each of the error signals, an error state identification signal output terminal that outputs the error state identification signal, a protection action signal generation circuit that generates a protection action signal for protecting the semiconductor element based on the error state identification signal, a protection action signal output terminal that outputs the protection action signal, and a protection circuit that protects the semiconductor element based on the protection action signal. Effect of the Invention

[0007] According to the present disclosure, an error state identification signal having a smaller pulse width than each error signal is generated, so that the type of error state can be identified early from the identification signal externally. [Brief description of the drawings]

[0008] [Figure 1] 1 is a diagram showing a configuration of a semiconductor element driving device according to a first embodiment. [Diagram 2] 1 is a circuit diagram showing a configuration of an error state identification signal generating circuit according to a first embodiment. [Diagram 3] 4 is a timing chart showing an operation of the error state identification signal generating circuit according to the first embodiment. [Figure 4] 1 is a circuit diagram showing a configuration of a protection action signal generating circuit according to a first embodiment. [Diagram 5] 4 is a timing chart showing the operation of the protection action signal generating circuit according to the first embodiment. [Figure 6] FIG. 11 is a diagram showing a configuration of a semiconductor element driving device according to a second embodiment. [Figure 7] FIG. 11 is a diagram showing a configuration of a semiconductor element driving device according to a third embodiment. [Figure 8] FIG. 13 is a diagram showing a configuration of a semiconductor element driving device according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The features described in each of the following embodiments are merely examples, and not all features are necessarily required. In the following description, the same or similar reference numerals are used to denote similar components in multiple embodiments, and different components will be mainly described.

[0010] <Embodiment 1> 1 is a diagram showing a configuration of a semiconductor element driving device 81 according to the present embodiment 1. The semiconductor element driving device 81 drives a semiconductor element 1. A chip (not shown) on which the semiconductor element 1 is provided is provided with a temperature detection diode 2 embedded in the chip, and a current detection transistor 3 for detecting a current having a correlation with the collector-emitter current of the semiconductor element 1.

[0011] In FIG. 1, the semiconductor element 1 and the current detection transistor 3 are IGBTs (Insulated Gate Bipolar Transistors), but may be MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or RC-IGBTs (Reverse Conducting - IGBTs). The semiconductor element 1 and the current detection transistor 3 may be made of normal silicon (Si), or may be made of wide band gap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), diamond, etc. When the semiconductor element 1 and the current detection transistor 3 are made of wide band gap semiconductors, stable operation under high temperature and high voltage and high switching speed can be achieved.

[0012] The semiconductor element driving device 81 has an input terminal IN, an output terminal OUT, error terminals ERR1, ERR2, ERR3, and ERR4, a protection action signal output terminal FO, and an error state identification signal output terminal FOI. The input terminal IN is a terminal to which a driving pulse signal is input from an external control device (not shown), and the output terminal OUT is a terminal that outputs a drive signal to the gate of the semiconductor element 1. The error terminals ERR1, ERR2, ERR3, and ERR4 are terminals for detecting an error state of the semiconductor element 1 or the semiconductor element driving device 81. The protection action signal output terminal FO is a terminal that outputs a protection action signal, which will be described later, and the error state identification signal output terminal FOI is a terminal that outputs an error state identification signal, which will be described later.

[0013] The semiconductor element driving device 81 of FIG. 1 includes a plurality of error state detection circuits, an error state identification signal generating circuit 9, a protection action signal generating circuit 10, a protection circuit 11, and an amplifier 12.

[0014] The multiple error state detection circuits according to the first embodiment include a power supply voltage abnormality detection circuit 4, a desaturation state detection circuit 5, a gate abnormality detection circuit 6, a temperature abnormality detection circuit 7, and a current abnormality detection circuit 8. Each of the multiple error state detection circuits detects an error state of the semiconductor element 1 or the semiconductor element driving device 81, and generates an error signal corresponding to the detected error state.

[0015] When the power supply voltage abnormality detection circuit 4 detects an abnormal state of the power supply voltage of the semiconductor element driving device 81 as an error state, it generates an error signal corresponding to the error state. For example, when the power supply voltage abnormality detection circuit 4 detects an abnormal state in which the power supply voltage VCC of the semiconductor element driving device 81 is equal to or lower than a predetermined voltage, it generates and outputs an error signal err0.

[0016] When the desaturation state detection circuit 5 detects the desaturation state of the semiconductor element 1 when the semiconductor element 1 is in the on state as an error state, it generates an error signal corresponding to the error state. For example, when the desaturation state detection circuit 5 detects an abnormal state in which the collector-emitter voltage of the semiconductor element 1 does not decrease to a predetermined saturation voltage when the semiconductor element 1 is in a completely on state, it generates and outputs an error signal err1.

[0017] When the gate abnormality detection circuit 6 detects an abnormal state of the gate of the semiconductor element 1 as an error state, it generates an error signal corresponding to the error state. For example, when the gate abnormality detection circuit 6 detects an abnormal state in which the gate voltage of the semiconductor element 1 does not rise to a predetermined voltage or higher within a predetermined time when the semiconductor element 1 is turned on, it generates and outputs an error signal err2. Also, for example, when the gate abnormality detection circuit 6 detects an abnormal state in which the gate voltage of the semiconductor element 1 does not fall to a predetermined voltage or lower within a predetermined time when the semiconductor element 1 is turned off, it generates and outputs an error signal err2.

[0018] When the temperature abnormality detection circuit 7 detects an abnormal state of the temperature of the semiconductor element 1 as an error state, it generates an error signal corresponding to the error state. For example, the temperature abnormality detection circuit 7 detects the chip temperature based on the inter-terminal voltage of the temperature detection diode 2, and when it detects an abnormal state in which the detected chip temperature is equal to or higher than a predetermined temperature, it generates and outputs the error signal err3.

[0019] When the current abnormality detection circuit 8 detects an abnormal state of the current of the semiconductor element 1 as an error state, it generates an error signal corresponding to the error state. For example, when the current abnormality detection circuit 8 detects an abnormal state in which the current flowing between the collector and emitter of the current detection transistor 3 is equal to or greater than a predetermined current, it determines that an abnormal state of the current of the semiconductor element 1 has been detected, and generates and outputs an error signal err4.

[0020] The error state identification signal generating circuit 9, which will be described in detail later, generates an error state identification signal having a different waveform for each type of error state based on the multiple error signals err0, err1, err2, err3, and err4 generated by the multiple error state detection circuits, respectively. Below, a case will be described in which the error state identification signal generating circuit 9 generates an error state identification signal having a different duty (also called duty ratio) for each type of error state. As will be described later, the error state identification signal has a smaller pulse width than each of the error signals err0, err1, err2, err3, and err4.

[0021] The error state identification signal generation circuit 9 outputs an error state identification signal to the error state identification signal output terminal FOI and the protection action signal generation circuit 10, and the error state identification signal is output from the error state identification signal output terminal FOI to the outside of the semiconductor element driving device 81. This enables an external control device to identify the type of error state from the error state identification signal.

[0022] Based on the error state identification signal, the protection action signal generation circuit 10 generates a protection action signal for protecting the semiconductor device 1. For example, the protection action signal generation circuit 10 performs filtering on the error state identification signal to generate a protection action signal having a pulse width equal to or greater than the output period of the error state identification signal.

[0023] The protection action signal generating circuit 10 outputs a protection action signal to a protection action signal output terminal FO and a protection circuit 11, and the protection action signal is output from the protection action signal output terminal FO to the outside of the semiconductor element driving device 81.

[0024] The protection circuit 11 protects the semiconductor element 1 based on the protection action signal. For example, when the protection action signal is not output from the protection action signal generation circuit 10, the protection circuit 11 drives the semiconductor element 1 by outputting the driving pulse signal input from the input terminal IN to the semiconductor element 1 via the amplifier 12. On the other hand, when the protection action signal is output from the protection action signal generation circuit 10, the protection circuit 11 performs an error protection operation of stopping the output of the driving pulse signal to the semiconductor element 1 via the amplifier 12 and stopping the driving of the semiconductor element 1. This protects the semiconductor element 1. Note that, in the example of FIG. 1, the protection circuit 11 includes an AND circuit that outputs a signal generated by the logical AND of the inverted protection action signal and the driving pulse signal, but is not limited thereto.

[0025] The amplifier 12 amplifies the output of the protection circuit 11 and outputs the amplified output from an output terminal OUT to the gate of the semiconductor device 1.

[0026] 2 is a circuit diagram showing a configuration of the error state identification signal generation circuit 9 according to the present embodiment 1. The error state identification signal generation circuit 9 includes a priority circuit 13, an OR circuit 18, a clock signal generation circuit 19, a D flip-flop circuit 20, a quinary counter circuit 21, a pulse signal generation circuit 22, AND circuits 28, 29, 30, 31, and an OR circuit 32.

[0027] The priority circuit 13 includes AND circuits 14, 15, 16, and 17, and generates post-priority error signals err0a, err1a, err2a, err3a, and err4a, which are prioritized in the order of error signals err0, err1, err2, err3, and err4. For example, when the error signal err0 is on (High), the post-priority error signal err0a is on, and the post-priority error signals err1a, err2a, err3a, and err4a are off (Low), regardless of whether the error signals err1, err2, err3, and err4, which have a lower priority than the error signal err0, are on or off. For example, when the error signal err0 is off and the error signal err1 is on, the post-priority error signal err0a is off, the post-priority error signal err1a is on, and the post-priority error signals err2a, err3a, and err4a are off, regardless of whether the error signals err2, err3, and err4, which have a lower priority than the error signal err1, are on or off.

[0028] The post-priority error signals err0a, err1a, err2a, and err3a are input to AND circuits 28, 29, 30, and 31, and the post-priority error signal err4a is input to an OR circuit 32.

[0029] Separate from the priority circuit 13, the error signals err0, err1, err2, err3, and err4 are input to an OR circuit 18. The output signal of the OR circuit 18 and a clock signal clk generated by a clock signal generation circuit 19 are input to a D terminal and a CLK terminal of a D flip-flop circuit 20, respectively.

[0030] The quinary counter circuit 21 outputs counter circuit output signals Q0, Q1, and Q2 based on the output signal of the Q terminal of the D flip-flop circuit 20 and the clock signal clk.

[0031] The pulse signal generating circuit 22 includes AND circuits 23, 24, and 25, all of whose inputs are inverted, an inverter circuit 26, and an OR circuit 27. The pulse signal generating circuit 22 generates a pulse signal d20 with a duty of 20%, a pulse signal d40 with a duty of 40%, a pulse signal d60 with a duty of 60%, and a pulse signal d80 with a duty of 80%, based on the counter circuit output signals Q0, Q1, and Q2. The pulse signals d20, d40, d60, and d80 have substantially the same frequency, and have a frequency that is approximately 1 / 5 of the frequency of the clock signal clk.

[0032] The post-priority error signals err0a, err1a, err2a, and err3a and the pulse signals d20, d40, d60, and d80 are respectively input to the AND circuits 28, 29, 30, and 31. The OR circuit 32 outputs an error state identification signal based on the output signals of the AND circuits 28, 29, 30, and 31 and the post-priority error signal err4a.

[0033] FIG. 3 is a time chart showing the operation of the error state identification signal generating circuit 9 according to the first embodiment.

[0034] As shown in Fig. 3, the error state identification signal generation circuit 9 outputs a pulse signal whose duty corresponds to the error signal as the error state identification signal. Duties of 20%, 40%, 60%, 80%, and 100% correspond to the error signals err0, err1, err2, err3, and err4, respectively. In this way, the error state identification signal generation circuit 9 generates error state identification signals with different duties for each type of error state based on the multiple error signals err1, err2, err3, and err4 generated by the multiple error state detection circuits, respectively.

[0035] 3, the error state identification signal has a smaller pulse width than each of the error signals err0, err1, err2, err3, and err4. Therefore, the time from when the output of the error state identification signal starts to when it ends is short, so that the external control device can quickly identify the type of error state from the error state identification signal output from the error state identification signal output terminal FOI.

[0036] Furthermore, when multiple error signals are output at the same time, a pulse signal with a duty corresponding to the error signal with the highest priority among the multiple error signals being output is output as the error state identification signal. For example, during the period T1-T2 when the error signals err0 and err1 are output, a pulse signal with a duty of 20% corresponding to the error signal err0, which has a higher priority than the error signal err1, is output as the error state identification signal. For example, during the period T3-T4 when the error signals err2, err3, and err4 are output, a pulse signal with a duty of 60% corresponding to the error signal err2, which has a higher priority than the error signals err3 and err4, is output as the error state identification signal.

[0037] 4 is a circuit diagram showing a configuration of the protection action signal generating circuit 10 according to the present embodiment 1. The protection action signal generating circuit 10 includes a transistor 33, a current source 34, a capacitor 35, a power supply 36, and a comparator 37.

[0038] Based on the error state identification signal, the transistor 33 and the current source 34 charge and discharge the capacitor 35. Based on the result of comparison between the voltage of the capacitor 35 and the voltage of the power supply 36, the comparator 37 outputs an output signal that serves as a protection operation signal.

[0039] Fig. 5 is a time chart showing the operation of the protection action signal generation circuit 10 according to the present embodiment 1. Fig. 5 shows the error state identification signal at the error state identification signal output terminal FOI, the voltage cin of the capacitor 35, and the protection action signal at the protection action signal output terminal FO.

[0040] 5, the current value output by the current source 34 and the capacitance value of the capacitor 35 are set so that the voltage cin of the capacitor 35 does not rise to the voltage V of the power supply 36 during the output period of the error state identification signal. The protection action signal generating circuit 10 configured in this manner can output a protection action signal for a period longer than the output period of the error state identification signal, and can therefore generate a protection action signal having a pulse width longer than the output period of the error state identification signal.

[0041] <Summary of the first embodiment> According to the semiconductor element driving device 81 of the first embodiment, an error state identification signal having a different waveform for each type of error state is generated, a protection action signal is generated based on the error state identification signal, and the error state identification signal and the protection action signal are output from the error state identification signal output terminal FOI and the protection action signal output terminal FO, respectively. With this configuration, the external control device can identify the error state during a protection action due to an error. Furthermore, since the error state identification signal has a smaller pulse width than each error signal, the external control device can identify the type of error state at an early stage. Furthermore, since the error state identification signal is output from a single error state identification signal output terminal FOI, there is no need to provide a terminal for each type of error state, and the number of terminals can be reduced.

[0042] <Modification of the first embodiment> In the first embodiment, the case where the multiple error state detection circuits include a power supply voltage abnormality detection circuit 4, a desaturation state detection circuit 5, a gate abnormality detection circuit 6, a temperature abnormality detection circuit 7, and a current abnormality detection circuit 8 has been described. However, the multiple error state detection circuits may include at least two of these circuits, or may include a circuit that detects an abnormality other than the above. In other words, even if the types and number of the multiple error state detection circuits are not limited to those described above, the same effect as in the first embodiment can be obtained. In this specification, for example, at least one (two) of A, B, C, ..., and Z means any one (two) of all combinations of one or more types (two types) extracted from the group of A, B, C, ..., and Z.

[0043] Furthermore, in accordance with the configuration of a plurality of error state detection circuits, the temperature detection diode 2 and the current detection transistor 3 do not necessarily have to be provided.

[0044] In the first embodiment, the error state identification signal generation circuit 9 generates an error state identification signal having a different duty for each type of error signal. However, the error state identification signal generation circuit 9 may be any circuit that generates a signal that can identify an error state, and may be, for example, a circuit that generates an error state identification signal having at least one of a different duty, a different frequency, and a different amplitude for each type of error signal.

[0045] Furthermore, as long as the protection action signal generation circuit 10 is a circuit that generates a protection action signal having a pulse width equal to or greater than the output period of the error state identification signal, the same effect as in the first embodiment can be obtained even if it is not the circuit in Fig. 4. Similarly, the error state identification signal generation circuit 9 does not have to be the circuit in Fig. 2.

[0046] <Embodiment 2> 6 is a diagram showing a configuration of a semiconductor element driving device 81 according to the present embodiment 2. The semiconductor element driving device 81 according to the present embodiment 2 includes a primary side circuit 81A, a secondary side circuit 81B, and level shift circuits 38, 39, 40, 41, 42, and 43.

[0047] 1 according to the first embodiment, an error state identification signal output terminal FOI, a protection action signal generation circuit 10, a protection action signal output terminal FO, a protection circuit 11, and an input terminal IN. The primary side circuit 81A transmits signals to an external control device that is external to the semiconductor element driving device 81, and receives a drive signal for driving the semiconductor element 1 from the external control device at the input terminal IN.

[0048] The primary side circuit 81A also includes a power supply voltage abnormality detection circuit 44, an OR circuit 45, and an AND circuit 46, one of the inputs of which is inverted.

[0049] The power supply voltage abnormality detection circuit 44 generates and outputs an error signal err5 when it detects an abnormal state of the power supply voltage VCC1 of the primary side circuit 81A. The OR circuit 45 outputs a signal indicating the logical sum of the error signal err5 output from the power supply voltage abnormality detection circuit 44 and the protection action signal output from the protection action signal generation circuit 10 to the protection circuit 11 and the protection action signal output terminal FO. The AND circuit 46 outputs a signal indicating the logical product of the inverted error signal err5 output from the power supply voltage abnormality detection circuit 44 and the error state identification signal output from the error state identification signal generation circuit 9 to the error state identification signal output terminal FOI.

[0050] According to this configuration, when the error signal err5 is not output from the power supply voltage abnormality detection circuit 44, the protection operation signal and the error state identification signal can be output from the protection operation signal output terminal FO and the error state identification signal output terminal FOI, as in embodiment 1.

[0051] On the other hand, when an error signal err5 is output from the power supply voltage abnormality detection circuit 44, an ON signal is output from the protection operation signal output terminal FO, and an OFF signal is output from the error state identification signal output terminal FOI without outputting an error state identification signal.

[0052] The secondary circuit 81B drives the semiconductor element 1 based on the drive signal substantially received by the primary circuit 81A. The secondary circuit 81B includes the power supply voltage abnormality detection circuit 4 according to the first embodiment shown in Fig. 1, the desaturation state detection circuit 5, the gate abnormality detection circuit 6, the temperature abnormality detection circuit 7, the current abnormality detection circuit 8, and the amplifier 12. When the power supply voltage abnormality detection circuit 4 detects an abnormal state of the power supply voltage VCC2 of the secondary circuit 81B, it generates and outputs an error signal err0.

[0053] The level shift circuit 43 level-shifts the drive signal received by the primary side circuit 81A and transmits it to the secondary side circuit 81B. The level shift circuits 38, 39, 40, 41, and 42 level-shift the multiple error signals err0, err1, err2, err3, and err4 generated by the secondary side circuit 81B and transmit them to the primary side circuit 81A.

[0054] <Summary of the second embodiment> According to the semiconductor element driving device 81 of the present embodiment 2 as described above, the level shift circuits 38, 39, 40, 41, 42, and 43 enable the secondary side circuit 81B to drive the semiconductor element 1 based on the driving signal received by the primary side circuit 81A, and the primary side circuit 81A can identify an error state detected in the secondary side circuit 81B.

[0055] Furthermore, when the signal from the error state identification signal output terminal FOI is off and the signal from the protection operation signal output terminal FO is on, the external control device can determine that a power supply voltage abnormality has been detected in the primary side circuit 81A. This allows the external control device to distinguish between an error state detected in the primary side circuit 81A and an error state detected in the secondary side circuit 81B. Furthermore, it is not necessary to provide a terminal dedicated to the error state of the primary side circuit 81A, and the number of terminals can be reduced.

[0056] <Modification of the second embodiment> In the second embodiment, a configuration has been described in which the error state identification signal from the error state identification signal generation circuit 9 and the protection action signal from the protection action signal generation circuit 10 are changed based on the output of the power supply voltage abnormality detection circuit 44. However, the error state identification signal generation circuit 9 may generate an error state identification signal according to the error states of the primary side circuit 81A and the secondary side circuit 81B based on the output of the power supply voltage abnormality detection circuit 44 and the error signal of the secondary side circuit 81B. With this configuration, the protection action signal can be output from the protection action signal output terminal FO and the error state identification signal can be output from the error state identification signal output terminal FOI without using the OR circuit 45 and the AND circuit 46.

[0057] <Embodiment 3> Fig. 7 is a diagram showing the configuration of a semiconductor element driving device 81 according to the third embodiment. The configuration of the third embodiment is similar to that of the second embodiment shown in Fig. 6, except that an error state identification signal generating circuit 9 is included in a secondary side circuit 81B, and a level shift circuit 47 is provided instead of the level shift circuits 38, 39, 40, 41, and 42. The level shift circuit 47 level-shifts the error state identification signal generated in the secondary side circuit 81B and transmits it to the primary side circuit 81A.

[0058] <Summary of the Third Embodiment> According to the semiconductor element driving device 81 of the third embodiment, since the error state identification signal generating circuit 9 is included in the secondary side circuit 81B, it is not necessary to provide a level shift circuit for each error state. As a result, it is expected that the circuit area and current consumption of the semiconductor element driving device 81 can be reduced.

[0059] <Fourth embodiment> Fig. 8 is a diagram showing the configuration of a semiconductor element driving device 81 according to a fourth embodiment. The configuration of the fourth embodiment is similar to that of the third embodiment shown in Fig. 7, except that a transmitting circuit 48, a transformer 49, and a receiving circuit 50 are provided instead of the level shift circuit 47, and a transmitting circuit 51, a transformer 52, and a receiving circuit 53 are provided instead of the level shift circuit 43. The transmitting circuits 48 and 51, the transformers 49 and 52, and the receiving circuits 50 and 53 are included in the concept of insulating elements.

[0060] The transmission circuit 48, the transformer 49, and the reception circuit 50 transmit the error state identification signal generated in the secondary circuit 81B as an AC signal to the primary circuit 81A. The transmission circuit 48, the transformer 49, and the reception circuit 50 insulate the DC signals of the primary circuit 81A and the secondary circuit 81B.

[0061] The transmission circuit 51, the transformer 52, and the reception circuit 53 transmit the drive signal received by the primary circuit 81A as an AC signal to the secondary circuit 81B. The transmission circuit 51, the transformer 52, and the reception circuit 53 insulate the DC signals of the primary circuit 81A and the secondary circuit 81B.

[0062] <Summary of the fourth embodiment> According to the semiconductor element driving device 81 according to the third embodiment as described above, signals can be transmitted while DC signals of the primary side circuit 81A and the secondary side circuit 81B are insulated.

[0063] <Modification of the fourth embodiment> In the fourth embodiment, the isolation elements include the transformers 49 and 52, but they do not have to include the transformers 49 and 52 as long as the signals can be transmitted while the DC signals of the primary circuit 81A and the secondary circuit 81B are isolated. For example, the isolation elements may include capacitors instead of the transformers 49 and 52. The isolation elements may also include photocouplers capable of transmitting optical signals other than DC signals. Even in this case, the same effects as those of the fourth embodiment can be obtained.

[0064] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0065] Various aspects of the present disclosure are summarized below as appendices.

[0066] (Appendix 1) A semiconductor element driving device for driving a semiconductor element, a plurality of error state detection circuits, each of which detects an error state of the semiconductor device or the semiconductor device driving apparatus and generates an error signal corresponding to the detected error state; an error state identification signal generating circuit for generating an error state identification signal having a waveform different for each type of error state and a pulse width smaller than that of each of the error signals, based on the plurality of error signals generated by the plurality of error state detection circuits; an error state identification signal output terminal for outputting the error state identification signal; a protection operation signal generating circuit that generates a protection operation signal for protecting the semiconductor device based on the error state identification signal; a protection action signal output terminal for outputting the protection action signal; a protection circuit that protects the semiconductor element based on the protection operation signal; A semiconductor element driving device comprising:

[0067] (Appendix 2) 2. The semiconductor element driving device according to claim 1, The plurality of error condition detection circuits include a power supply voltage abnormality detection circuit that detects an abnormal state of a power supply voltage of the semiconductor element driving device as the error state; a desaturation state detection circuit that detects a desaturation state of the semiconductor element when the semiconductor element is in an on state as the error state; a gate abnormality detection circuit that detects an abnormal state of a gate of the semiconductor element as the error state; a temperature abnormality detection circuit that detects an abnormal state of the temperature of the semiconductor element as the error state; a current abnormality detection circuit that detects an abnormal state of the current of the semiconductor element as the error state; A semiconductor element driving device comprising at least two of the above.

[0068] (Appendix 3) A semiconductor element driving device according to claim 1 or 2, The semiconductor element driving device, wherein at least one of a duty, a frequency, and an amplitude of the error state identification signal differs for each of the types of the error state, thereby causing the waveform of the error state identification signal to differ.

[0069] (Appendix 4) A semiconductor element driving device according to any one of Supplementary Note 1 to Supplementary Note 3, A semiconductor element driving device, wherein a pulse width of the protection action signal is equal to or longer than an output period of the error state identification signal.

[0070] (Appendix 5) A semiconductor element driving device according to any one of claims 1 to 4, a primary side circuit that receives a drive signal for driving the semiconductor element from an external device of the semiconductor element drive device, and includes the error state identification signal generation circuit, the error state identification signal output terminal, the protection action signal generation circuit, the protection action signal output terminal, and the protection circuit; a secondary circuit that drives the semiconductor device and includes the plurality of error state detection circuits; a level shift circuit that level-shifts the drive signal received by the primary side circuit and transmits the level-shifted drive signal to the secondary side circuit, and level-shifts the plurality of error signals generated by the secondary side circuit and transmits the level-shifted error signals to the primary side circuit; The semiconductor element driving device further comprises:

[0071] (Appendix 6) A semiconductor element driving device according to any one of claims 1 to 4, a primary side circuit that receives a drive signal for driving the semiconductor element from an external device of the semiconductor element drive device, and includes the error state identification signal output terminal, the protection action signal generating circuit, the protection action signal output terminal, and the protection circuit; a secondary circuit that drives the semiconductor device and includes the plurality of error state detection circuits and the error state identification signal generation circuit; a level shift circuit that level-shifts the drive signal received by the primary side circuit and transmits the level-shifted drive signal to the secondary side circuit, and level-shifts the error state identification signal generated by the secondary side circuit and transmits the level-shifted error state identification signal to the primary side circuit; The semiconductor element driving device further comprises:

[0072] (Appendix 7) A semiconductor element driving device according to any one of claims 1 to 4, a primary side circuit that receives a drive signal for driving the semiconductor element from an external device of the semiconductor element drive device, and includes the error state identification signal output terminal, the protection action signal generating circuit, the protection action signal output terminal, and the protection circuit; a secondary circuit that drives the semiconductor device and includes the plurality of error state detection circuits and the error state identification signal generation circuit; an insulating element that transmits the drive signal received by the primary side circuit to the secondary side circuit as a signal other than a DC signal, transmits the error state identification signal generated by the secondary side circuit to the primary side circuit as a signal other than a DC signal, and isolates the DC signals between the primary side circuit and the secondary side circuit; The semiconductor element driving device further comprises:

[0073] (Appendix 8) A semiconductor element driving device according to any one of Supplementary Note 5 to Supplementary Note 7, The semiconductor element driving device further comprises a power supply voltage abnormality detection circuit included in the primary side circuit and configured to detect an abnormal state of the power supply voltage of the primary side circuit. [Explanation of symbols]

[0074] 1 semiconductor element, 4,44 power supply voltage abnormality detection circuit, 5 desaturation state detection circuit, 6 gate abnormality detection circuit, 7 temperature abnormality detection circuit, 8 current abnormality detection circuit, 9 error state identification signal generation circuit, 10 protection operation signal generation circuit, 11 protection circuit, 38,39,40,41,42,43,47 level shift circuit, 48,51 transmission circuit, 49,52 transformer, 50,53 receiving circuit, 81 semiconductor element drive device, 81A primary side circuit, 82B secondary side circuit, FO protection operation signal output terminal, FOI error state identification signal output terminal.

Claims

1. A semiconductor element driving device for driving a semiconductor element, a plurality of error state detection circuits, each of which detects an error state of the semiconductor device or the semiconductor device driving apparatus and generates an error signal corresponding to the detected error state; an error state identification signal generating circuit for generating an error state identification signal having a waveform different for each type of error state and a pulse width smaller than that of each of the error signals, based on the plurality of error signals generated by the plurality of error state detection circuits; an error state identification signal output terminal for outputting the error state identification signal; a protection operation signal generating circuit that generates a protection operation signal for protecting the semiconductor device based on the error state identification signal; a protection action signal output terminal for outputting the protection action signal; a protection circuit that protects the semiconductor element based on the protection operation signal; A semiconductor element driving device comprising:

2. 2. The semiconductor element driving device according to claim 1, The plurality of error condition detection circuits include a power supply voltage abnormality detection circuit that detects an abnormal state of a power supply voltage of the semiconductor element driving device as the error state; a desaturation state detection circuit that detects a desaturation state of the semiconductor element when the semiconductor element is in an on state as the error state; a gate abnormality detection circuit that detects an abnormal state of a gate of the semiconductor element as the error state; a temperature abnormality detection circuit that detects an abnormal state of the temperature of the semiconductor element as the error state; a current abnormality detection circuit that detects an abnormal state of the current of the semiconductor element as the error state; A semiconductor element driving device comprising at least two of the above.

3. 3. The semiconductor element driving device according to claim 1, The semiconductor element driving device, wherein at least one of a duty, a frequency, and an amplitude of the error state identification signal differs for each of the types of the error state, thereby causing the waveform of the error state identification signal to differ.

4. 3. The semiconductor element driving device according to claim 1, A semiconductor element driving device, wherein a pulse width of the protection action signal is equal to or longer than an output period of the error state identification signal.

5. 2. The semiconductor element driving device according to claim 1, a primary side circuit that receives a drive signal for driving the semiconductor element from an external device of the semiconductor element drive device, and includes the error state identification signal generation circuit, the error state identification signal output terminal, the protection action signal generation circuit, the protection action signal output terminal, and the protection circuit; a secondary circuit that drives the semiconductor device and includes the plurality of error state detection circuits; a level shift circuit that level-shifts the drive signal received by the primary side circuit and transmits the level-shifted drive signal to the secondary side circuit, and level-shifts the plurality of error signals generated by the secondary side circuit and transmits the level-shifted error signals to the primary side circuit; The semiconductor element driving device further comprises:

6. 2. The semiconductor element driving device according to claim 1, a primary side circuit that receives a drive signal for driving the semiconductor element from an external device of the semiconductor element drive device, and includes the error state identification signal output terminal, the protection action signal generating circuit, the protection action signal output terminal, and the protection circuit; a secondary circuit that drives the semiconductor device and includes the plurality of error state detection circuits and the error state identification signal generation circuit; a level shift circuit that level-shifts the drive signal received by the primary circuit and transmits the level-shifted drive signal to the secondary circuit, and level-shifts the error state identification signal generated by the secondary circuit and transmits the level-shifted error state identification signal to the primary circuit; The semiconductor element driving device further comprises:

7. 2. The semiconductor element driving device according to claim 1, a primary side circuit that receives a drive signal for driving the semiconductor element from an external device of the semiconductor element drive device, and includes the error state identification signal output terminal, the protection action signal generating circuit, the protection action signal output terminal, and the protection circuit; a secondary circuit that drives the semiconductor device and includes the plurality of error state detection circuits and the error state identification signal generation circuit; an insulating element that transmits the drive signal received by the primary side circuit to the secondary side circuit as a signal other than a DC signal, transmits the error state identification signal generated by the secondary side circuit to the primary side circuit as a signal other than a DC signal, and isolates the DC signals between the primary side circuit and the secondary side circuit; The semiconductor element driving device further comprises:

8. 8. The semiconductor element driving device according to claim 5, The semiconductor element driving device further comprises a power supply voltage abnormality detection circuit included in the primary side circuit and configured to detect an abnormal state of a power supply voltage of the primary side circuit.

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