Test device and test method

Abstract

To provide a test device and a test method capable of appropriately testing a memory cell.SOLUTION: Regarding operations of a test device, read characteristics are acquired, the read characteristics indicating a relation between a read voltage of a memory cell on which write processing is performed, and a logarithm of a cell current, and in the write processing, a write operation and a verify operation are repeated while increasing a write voltage. A threshold voltage of the memory cell is calculated by applying first processing to the read characteristics, the first processing defining a sub threshold region in the read characteristics as a first region and paying attention to a second region which is a region of a read voltage larger than a maximum read voltage of the first region. A first slope in first threshold characteristics indicating a relation between the write voltage in the write processing and the threshold voltage is computed on the basis of the threshold voltage which is calculated in the first processing, and a first slope deterioration component is calculated by subtracting the first slope from a slope in ideal threshold characteristics.SELECTED DRAWING: Figure 15

Description

[Technical field]

[0001] The present embodiment relates to a test device and a test method. [Background technology]

[0002] A test device for testing a semiconductor memory device including memory cells may perform a write process on the memory cells while increasing the write voltage, and test the read characteristics of the memory cells. It is desirable for the test device to appropriately test the memory cells. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-136185 A [Patent Document 2] JP 2014-053060 A [Patent Document 3] JP 2008-210503 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a test apparatus and a test method capable of appropriately testing memory cells. [Means for solving the problem]

[0005] According to one embodiment, a test device is provided that includes an interface unit and a controller. The interface unit acquires a read characteristic. The read characteristic indicates a relationship between a read voltage of a memory cell and a logarithm of a cell current. A write process is performed on the memory cell. In the write process, a write operation and a verify operation are repeated while increasing the write voltage. The controller performs a first process on the read characteristic to obtain a threshold voltage of the memory cell. The first process is a process that focuses on a second region in the read characteristic. The second region is a region of a read voltage that is greater than a maximum read voltage of the first region. The first region is a subthreshold region. The controller calculates a first slope in the first threshold characteristic based on the threshold voltage obtained in the first process. The first threshold characteristic indicates a relationship between a write voltage and a threshold voltage in the write process. The controller obtains a first slope degradation component by subtracting the first slope from a slope in an ideal threshold characteristic. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of a test device according to an embodiment. [Diagram 2] 1 is a perspective view showing a configuration of a semiconductor memory device to be tested in an embodiment; [Diagram 3] 1 is a block diagram showing a configuration of a semiconductor memory device to be tested in an embodiment; [Figure 4] FIG. 2 is a circuit diagram showing a configuration of a memory cell array according to the embodiment. [Diagram 5] 4 is a diagram showing threshold voltage distributions of memory cells according to the embodiment; [Figure 6] 1 is a cross-sectional view showing a configuration of a memory cell array according to an embodiment. [Figure 7] 1 is a cross-sectional view showing a configuration of a memory cell according to an embodiment. [Figure 8] FIG. 2 is a block diagram showing the functional configuration of a controller according to the embodiment. [Figure 9] 11A and 11B are diagrams showing a write process to a memory cell in the embodiment; [Figure 10]11 is a diagram showing a process PC1 for obtaining a threshold voltage of a memory cell according to the embodiment. [Figure 11] 11 is a diagram showing a process PC2 for obtaining a threshold voltage of a memory cell according to the embodiment. [Figure 12] 5 is a diagram showing the relationship between the threshold voltage and the write voltage of a memory cell according to the embodiment. [Figure 13] 6A and 6B are diagrams showing changes in a band diagram due to a slope degradation component in the embodiment. [Figure 14] 6A and 6B are diagrams showing changes in read characteristics due to a fringe effect and changes in read characteristics due to a decrease in carrier capture efficiency in an embodiment. [Figure 15] 4 is a flowchart showing the operation of a test device according to an embodiment. [Figure 16] FIG. 11 is a diagram showing a process PC11 for determining the threshold voltage of a memory cell according to a first modified example of the embodiment. [Figure 17] 13A and 13B are diagrams showing an erase process for a memory cell according to a second modified example of the embodiment. [Figure 18] FIG. 13 is a diagram showing a process PC1 for determining the threshold voltage of a memory cell according to a second modified example of the embodiment. [Figure 19] FIG. 11 is a diagram showing a process PC2 for determining the threshold voltage of a memory cell according to a second modified example of the embodiment. [Figure 20] FIG. 13 is a graph showing the relationship between the threshold voltage and the erase voltage of a memory cell according to a second modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] A test device according to an embodiment will be described in detail below with reference to the accompanying drawings. Note that the present invention is not limited to the embodiment.

[0008] (Embodiment) The test device according to the embodiment is a test device for testing a semiconductor memory device including memory cells, and performs a write process on the memory cells while increasing the write voltage to test the read characteristics of the memory cells, with some modifications being made to ensure that the memory cells are appropriately tested.

[0009] The test device 300 may be configured as shown in Fig. 1. Fig. 1 is a block diagram showing the configuration of the test device 300.

[0010] The test device 300 can be connected to the semiconductor memory device 1 via a communication medium 400. The communication medium 400 may be a wired communication path such as a coaxial cable, or a wireless communication path. When the test device 300 is connected to the semiconductor memory device 1, it can supply a test pattern to the semiconductor memory device 1 via the communication medium 400 to test the semiconductor memory device 1.

[0011] The test device 300 includes an interface (I / F) unit 301 , an input unit 305 , a storage unit 303 , a display unit 304 , and a controller 302 .

[0012] The interface unit 301 has an external connection terminal 301a. The external connection terminal 301a is connectable to the semiconductor memory device 1 via a communication medium 400. The interface unit 301 performs an interface operation between the semiconductor memory device 1 and the controller 302 under the control of the controller 302.

[0013] The input unit 305 can receive instructions from a user. For example, the input unit 305 may receive a test execution instruction related to a test of a memory cell. When the input unit 305 receives an instruction from a user, the input unit 305 supplies the instruction to the controller 302. The input unit 305 may include a keyboard, a mouse, a touch panel, etc.

[0014] The storage unit 303 stores predetermined information. The predetermined information includes information related to testing of memory cells. The storage unit 303 may store test data 303a. The storage unit 303 may be a non-volatile storage medium such as a hard disk.

[0015] The display unit 304 has a display screen 304a and can display predetermined information on the display screen 304a. For example, the display unit 304 may display information related to a test of a memory cell (e.g., test conditions, test results, etc.) on the display screen 304a.

[0016] The controller 302 comprehensively controls each unit of the test apparatus 300. The controller 302 may perform a predetermined control in response to an instruction from a user, or may perform a predetermined control autonomously in response to the establishment of a predetermined condition.

[0017] For example, the controller 302 generates a write command in response to an instruction from a user via the input unit 305 or autonomously in response to the establishment of a predetermined condition, and reads out the test data 303a from the storage unit 303. The controller 302 supplies the write command and the test data 303a to the interface unit 301. The write command includes an address of a memory cell to be tested. The interface unit 301 converts the write command and the test data 303a into a format for the communication medium 400, and supplies them to the semiconductor memory device 1 via the communication medium 400.

[0018] The semiconductor memory device 1 has a plurality of memory cells. When the semiconductor memory device 1 receives a write command and test data, it can perform a write process of the test data to the memory cell addressed by the write command. The write process may be performed by an ISPP (Incremental Step Pulse Programming) method. In the write process, a write operation and a verify operation are repeated while increasing the write voltage. When the verify operation is OK and the write process of the test data to the memory cell is completed, the semiconductor memory device 1 transmits a write completion notification to the interface unit 301 via the communication medium 400.

[0019] Upon receiving the write completion notification, the interface unit 301 supplies the write completion notification to the controller 302 .

[0020] Thereafter, the controller 302 generates a read command in response to an instruction from a user via the input unit 305 or autonomously in response to the establishment of a predetermined condition. The read command includes an address of a memory cell to be tested. The controller 302 may generate a read command including an address of a memory cell on which a write process has been performed. The controller 302 supplies the read command to the interface unit 301.

[0021] When the semiconductor memory device 1 receives a read command, it can perform a read process on the memory cell addressed by the read command. In the read process, the cell current is detected while sweeping the read voltage. When the semiconductor memory device 1 completes the read process on the memory cell, it generates read characteristic information 303b. The read characteristic information 303b indicates the read characteristics. The read characteristics indicate the relationship between the read voltage and the logarithm (common logarithm) of the cell current. The semiconductor memory device 1 transmits the read characteristic information 303b to the interface unit 301 via the communication medium 400.

[0022] The interface unit 301 receives the read characteristic information 303b. Upon acquiring the read characteristic information 303b, the interface unit 301 supplies the read characteristic information 303b to the controller 302. The controller 302 stores the read characteristic information 303b in the storage unit 303.

[0023] The controller 302 performs process PC1 on the read characteristics indicated by the read characteristic information 303b to obtain the threshold voltage of the memory cell. Process PC1 is a process for obtaining the threshold voltage by focusing on the overdrive region in the read characteristics. Process PC1 includes a process for obtaining the voltage corresponding to the tangent near the boundary between the subthreshold region and the overdrive region in the read characteristics as the threshold voltage. Process PC1 may include a process using the GM-MAX method (extrapolation method using maximum mutual conductance).

[0024] In this specification, the subthreshold region is defined as the common logarithm of the current (cell current: Icell) flowing through the memory cell with the word line WL voltage (WL voltage: Vwl) on the horizontal axis, that is, log 10 When (Icell) is plotted on the vertical axis, it refers to the WL voltage region that changes linearly (i.e., the waveform becomes a straight line with a constant slope). The overdrive region refers to the region of WL voltage that is even higher than the maximum WL voltage in the subthreshold region. In the following, "logarithm" refers to common logarithm.

[0025] The controller 302 generates threshold characteristic information 303c based on the threshold voltage obtained in the process PC1. The threshold characteristic information 303c indicates a threshold characteristic TP1. The threshold characteristic TP1 indicates the relationship between the write voltage and the threshold voltage in the write process. The controller 302 may obtain the threshold characteristic TP1 by plotting the threshold voltage obtained in the process PC1 and the write voltage during the write process on a plane having coordinate axes, and generate the threshold characteristic information 303c.

[0026] Here, the average rate of change of the threshold voltage with respect to the write voltage is called the slope, and the phenomenon in which the average rate of change of the threshold voltage with respect to the write voltage attenuates from an ideal rate of change (e.g., 1) is called slope degradation.

[0027] The controller 302 calculates a slope SL1 in the threshold characteristic TP1. The slope SL1 indicates an average rate of change of the threshold voltage with respect to the write voltage in the threshold characteristic TP1. The controller 302 generates slope degradation component information 303d according to the slope SL1. The slope degradation component information 303d indicates a slope degradation component ΔDS1. The controller 302 may obtain a threshold characteristic TP0 based on ideal conditions and calculate a slope SL0 in the threshold characteristic TP0. The controller 302 may obtain a slope degradation component ΔDS1 by subtracting the slope SL1 from the slope SL0. The controller 302 stores the slope degradation component information 303d in the storage unit 303.

[0028] The controller 302 performs process PC2 on the read characteristics indicated by the read characteristic information 303b to obtain the threshold voltage of the memory cell. Process PC2 is a process for obtaining the threshold voltage by focusing on the subthreshold region in the read characteristics. Process PC2 includes a process for obtaining the voltage corresponding to the approximation line of the subthreshold region in the read characteristics as the threshold voltage.

[0029] The controller 302 generates threshold characteristic information 303e based on the threshold voltage obtained in process PC2. The threshold characteristic information 303e indicates a threshold characteristic TP2. The threshold characteristic TP2 indicates the relationship between the write voltage and the threshold voltage in the write process. The controller 302 may obtain the threshold characteristic TP2 by plotting the threshold voltage obtained in process PC2 and the write voltage during the write process, and generate the threshold characteristic information 303e.

[0030] The controller 302 calculates a slope SL2 in the threshold characteristic TP2. The slope SL2 indicates the inclination of the change in the threshold voltage with respect to the write voltage. The controller 302 generates slope degradation component information 303f according to the slope SL2. The slope degradation component information 303f indicates a slope degradation component ΔDS2. The controller 302 may obtain the slope degradation component ΔDS2 by subtracting the slope SL2 from the slope SL1. The controller 302 stores the slope degradation component information 303f in the storage unit 303.

[0031] The controller 302 reads out the slope degradation component information 303d and the slope degradation component information 303f from the storage unit 303. The controller 302 notifies the user of the slope degradation component ΔDS1 corresponding to the slope degradation component information 303d and the slope degradation component ΔDS2 corresponding to the slope degradation component information 303f. The controller 302 may display the slope degradation component ΔDS1 and the slope degradation component ΔDS2 on the display screen 304a of the display unit 304. The controller 302 may display the slope degradation component information 303d and the slope degradation component information 303f on the display screen 304a of the display unit 304 in a form in which the magnitude relationship between the slope degradation component ΔDS1 and the slope degradation component ΔDS2 can be recognized. In this way, the test device 300 can notify the user of the slope degradation component ΔDS1 and the slope degradation component ΔDS2. When a memory cell has a defect, the cause of the defect can be predicted to some extent by comparing the slope degradation component ΔDS1 and the slope degradation component ΔDS2.

[0032] The slope degradation component ΔDS1 indicates degradation due to a decrease in the carrier capture efficiency of the memory cell. The decrease in carrier capture efficiency is a phenomenon in which it becomes difficult to store charge in the charge storage film as the block insulating film of the memory cell becomes thinner in response to demands for miniaturization. When the carrier capture efficiency decreases, the write voltage at which the memory cell is verified OK during the write process tends to increase, which may hasten degradation of the memory cell.

[0033] The slope degradation component ΔDS2 indicates degradation due to the fringe effect of the memory cell. The fringe effect is a phenomenon in which cell current flows at a read voltage lower than the appropriate read voltage as the distance between memory cells becomes smaller in response to demands for miniaturization. When the fringe effect occurs, the read voltage in the read process of the memory cell tends to become lower, making it difficult for the sense amplifier to operate properly.

[0034] For example, if the slope degradation component ΔDS1 is larger than the slope degradation component ΔDS2 when a memory cell has a defect, it can be predicted that the defect is mainly caused by a decrease in the carrier capture efficiency of the memory cell. This makes it possible to prompt the user to take measures against the decrease in the carrier capture efficiency of the memory cell.

[0035] Alternatively, if the slope degradation component ΔDS2 is larger than the slope degradation component ΔDS1 when a memory cell has a defect, it can be predicted that the defect is mainly caused by the fringe effect of the memory cell. This makes it possible to prompt the user to take measures against the fringe effect of the memory cell.

[0036] Next, the semiconductor memory device 1 to be tested will be described. As shown in Fig. 2, the semiconductor memory device 1 has a three-dimensional structure in which a columnar semiconductor film penetrates a stack in which multiple conductive layers are stacked with insulating layers interposed between them, and adjacent portions between each conductive layer and the semiconductor film function as memory cells. Fig. 2 is a perspective view showing the configuration of the semiconductor memory device 1 to be tested. In the following, the direction in which the word lines WL extend is defined as the X direction, the direction in which the bit lines BL extend is defined as the Y direction, and the direction perpendicular to the X direction and the Y direction is defined as the Z direction.

[0037] As shown in FIG. 2, the semiconductor memory device 1 includes a select gate SGS, a word line WL, and a select gate SGD. The select gate SGS is stacked on a substrate SUB via an insulating layer 7. In the example of FIG. 2, three layers of select gates SGS are provided. The word line WL is stacked on the topmost select gate SGS via the insulating layer 7. In the example of FIG. 2, the word line WL is provided in multiple layers alternately with the insulating layer 7 along the Z direction. The select gate SGD is stacked on the topmost word line WL via the insulating layer 7. The select gate SGS, the word line WL, and the select gate SGD are plate-shaped extending in the X direction and the Y direction, respectively.

[0038] 2, the select gate SGD, the word line WL, and the select gate SGS are divided and insulated in the Y direction by slits ST. The source line SL is disposed on the +Z side of the substrate SUB via an interlayer insulating film 81. The slit ST is provided on the +Z side of the source line SL and extends in the X and Z directions.

[0039] The select gate SGD is divided in the Y direction, for example, by a dividing film SHE. In the example of FIG. 2, select gates SGD0 and SGD1 divided in the Y direction are shown. The dividing film SHE is provided above (on the +Z side of) the word line WL and extends in the X and Z directions. Therefore, the select gate SGD0 and the select gate SGD1 are arranged side by side in the Y direction on the word line WL. In the example of FIG. 2, each of the select gates SGD0 and SGD1 is provided in three layers.

[0040] The substrate SUB is, for example, a silicon substrate. The select gate SGS, the word line WL, and the select gate SGD are, for example, metal layers containing tungsten (W). The insulating layer 7 and the interlayer insulating film 81 are, for example, insulators containing silicon oxide.

[0041] The semiconductor memory device 1 further includes a plurality of pillars 4. The pillars 4 extend in the Z direction, which is the stacking direction of the select gate SGS, the word line WL, and the select gate SGD. The semiconductor memory device 1 further includes a plurality of bit lines BL provided above the select gate SGD.

[0042] The pillars 4 are each electrically connected to a bit line BL via a contact plug 31. For example, one of the pillars 4 sharing the select gate SGD0 and one of the pillars 4 sharing the select gate SGD1 are electrically connected to one bit line BL.

[0043] In FIG. 2, for simplicity of illustration, an interlayer insulating film provided between the selection gate SGD and the bit line BL is omitted.

[0044] In the semiconductor memory device 1, the select gate SGD, the word line WL, and the select gate SGS are each composed of a conductive layer. A stacked body SST in which conductive layers and insulating layers 7 are alternately stacked is composed on the +Z side of the source line SL. The stacked body SST is penetrated by pillars 4 to form a three-dimensional arrangement of memory cells (a memory cell array).

[0045] That is, in the semiconductor memory device 1, the portions where the word lines WL and the pillars 4 intersect are configured to function as memory cells, and a memory cell array 2 is configured in which a plurality of memory cells are arranged three-dimensionally. Also, the portions where the select gates SGS and the pillars 4 intersect function as source-side select gates, and the portions where the select gates SGD0, SGD1 and the pillars 4 intersect function as drain-side select gates. In the semiconductor memory device 1, by increasing the number of stacks of the word lines WL in the stack SST, it is possible to increase the memory capacity without using finer patterning technology.

[0046] FIG. 3 is a block diagram showing a schematic configuration of the semiconductor memory device 1. As shown in FIG.

[0047] 3, the semiconductor memory device 1 includes a memory cell array 2, a peripheral circuit 100, and an interface 200. The peripheral circuit 100 includes a WL driving circuit 110, an SGS driving circuit 120, an SGD driving circuit 130, a SL driving circuit 140, and a sense amplifier circuit 150.

[0048] The WL driving circuit 110 is a circuit that controls the voltage applied to the word line WL, the SGS driving circuit 120 is a circuit that controls the voltage applied to the select gate SGS, the SGD driving circuit 130 is a circuit that controls the voltage applied to the select gate SGD, and the SL driving circuit 140 is a circuit that controls the voltage applied to the source line SL, and the sense amplifier circuit 150 is a circuit that controls the voltage applied to the bit line BL and determines the data read according to the signal from the selected memory cell.

[0049] The peripheral circuit 100 controls the operation of the semiconductor memory device 1 based on an instruction input via the interface 200 from the outside (for example, a memory controller of a memory system to which the semiconductor memory device 1 is applied).

[0050] Next, the circuit configuration of the memory cell array 2 will be described with reference to Fig. 4. Fig. 4 is a circuit diagram showing the configuration of the memory cell array 2.

[0051] The memory cell array 2 has a plurality of blocks BLK, each of which is a collection of a plurality of memory cell transistors MT. Hereinafter, the memory cell transistors MT will be simply referred to as memory cells MT.

[0052] Each block BLK has multiple string units SU0, SU1, SU2, and SU3, which are a set of memory cells MT associated with word lines WL and bit lines BL. Each string unit SU0 to SU3 has multiple memory strings MST in which memory cells MT are connected in series. The number of memory strings MST in the string units SU0 to SU3 is arbitrary.

[0053] The string units SU0, SU1, SU2, and SU3 correspond to the select gates SGD0, SGD1, SGD2, and SGD3, share the select gate SGS, and function as drive units in the block BLK. Each string unit SU can be driven by its corresponding select gate SGD and select gate SGS. Each string unit SU includes a plurality of memory strings MST.

[0054] Each memory string MST includes, for example, ten memory cells MT (MT0 to MT9) and select transistors DGT and SGT. The memory cells MT have a control gate and a charge storage film, and retain and store data in a non-volatile manner. The ten memory cells MT are connected in series between the source of the select transistor DGT and the drain of the select transistor SGT. The number of memory cells MT in the memory string MST is not limited to ten.

[0055] The gates of the selection transistors DGT in the string units SU0 to SU3 are connected to the selection gates SGD0 to SGD3, respectively. On the other hand, the gates of the selection transistors SGT in the string units SU are commonly connected to, for example, a selection gate SGS.

[0056] The drains of the select transistors DGT of each memory string MST in each string unit SU are connected to different bit lines BL0 to BLk (k is any integer equal to or greater than 2). The bit lines BL0 to BLk commonly connect one memory string MST in each string unit SU across multiple blocks BLK. Furthermore, the sources of the select transistors SGT are commonly connected to a source line SL.

[0057] That is, the string unit SU is a set of memory strings MST connected to different bit lines BL0 to BLk and connected to the same select gate SGD. Each block BLK is a set of multiple string units SU0 to SU3 that share a word line WL. The memory cell array 2 is a set of multiple blocks BLK that share the bit lines BL0 to BLk.

[0058] The bit lines BL0 to BLk (when not distinguishing between the individual bit lines, they will be indicated as BL) are connected to a memory string MST. When the selection gate DGT is turned on, the channel region of each memory cell MT in the memory string MST can be made conductive to the bit line BL. Each bit line BL is connected to a corresponding sense amplifier SA among the multiple sense amplifiers SA0 to SAp in the sense amplifier circuit 150.

[0059] The word lines WL0 to WL9 (when the word lines are not distinguished from one another, they will be referred to as WL) commonly connect the control gates of the memory cells MT between the memory strings MST in each string unit SU in the physical block BLK. That is, the control gates of the memory cells MT in the same row in each string unit SU in the physical block BLK are connected to the same word line WL. That is, the string unit SU in the physical block BLK includes a plurality of memory cell groups MCG corresponding to the plurality of word lines WL, and each memory cell group MCG includes (k+1) memory cells MT connected to the same word line WL.

[0060] When each memory cell MT is configured to be able to hold a 1-bit value (when operating in single-level cell (SLC) mode), (p+1) memory cells MT (i.e., memory group MCG) connected to the same word line WL are treated as one physical page, and data write and read operations are performed for each physical page.

[0061] For example, in a single level cell (SLC) mode in which each memory cell MT stores a one-bit value, each word line WL holds one physical page of data. As shown in FIG. 5(a), the threshold distribution of memory cells MT in the memory cell array 2 includes two states (small regions) ST0 and ST1 within a range (Vmin to Vmax) in which the threshold voltage is controlled. FIG. 5 is a diagram showing the threshold voltage distribution of memory cells MT. Each state ST indicates the distribution of the threshold voltage of memory cells MT. A different one-bit value is associated with each state ST. States ST0 and ST1 can be associated with "1" and "0", respectively.

[0062] Each memory cell MT may be configured to hold a multi-bit value. When each memory cell MT can store a value of n (n≧2) bits, the storage capacity per word line WL is equal to the size of n physical pages. That is, each memory cell group MCG is treated as n physical pages.

[0063] In a multi-level cell (MLC) mode in which each memory cell MT stores a two-bit value, each word line WL holds data for two physical pages. As shown in FIG. 5(b), the threshold distribution of memory cells MT in the memory cell array 2 includes four states ST0 to ST3 within a range (Vmin to Vmax) in which the threshold voltage is controlled. Each state ST is associated with a different two-bit value. States ST0,...,ST3 can be associated with "11",...,"00", respectively.

[0064] In a triple-level cell (TLC) mode in which each memory cell MT stores a three-bit value, data for three physical pages is held in each word line WL. As shown in FIG. 5(c), there are eight states ST0 to ST7 in the threshold voltage control range (Vmin to Vmax) for the threshold voltage distribution of the memory cells MT in the memory cell array 2. A different three-bit value is associated with each state ST. States ST0,...,ST7 can be associated with "111",...,"000", respectively.

[0065] In a quad level cell (QLC) mode in which each memory cell MT stores a 4-bit value, each word line WL holds data for four physical pages. As shown in FIG. 5(d), there are 16 states ST0 to ST15 in the threshold voltage control range (Vmin to Vmax) for the threshold voltage distribution of the memory cells MT in the memory cell array 2. A different 4-bit value is associated with each state ST. States ST0,...,ST15 can be associated with "1111",...,"0000", respectively.

[0066] In a penta-level cell (PLC) mode in which each memory cell MT stores a 5-bit value, data for 5 physical pages is held in each word line WL. As shown in FIG. 5(e), there are 32 states ST0 to ST31 in the threshold voltage control range (Vmin to Vmax) for the threshold voltage distribution of the memory cells MT in the memory cell array 2. A different 5-bit value is associated with each state ST. States ST0,...,ST31 can be associated with "11111",...,"00000", respectively.

[0067] Next, the cross-sectional configuration of the memory cell array 2 will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view showing the configuration of the memory cell array 2.

[0068] In the semiconductor memory device 1, a conductive layer 3 is disposed on the +Z side of the substrate SUB via an interlayer insulating film 81. The conductive layer 3 may be formed of a material mainly composed of a semiconductor (e.g., silicon) containing impurities or a material mainly composed of a conductive substance (e.g., a metal such as tungsten). The conductive layer 3 extends in a plate shape in the XY direction and functions as a source line SL (see FIG. 2). A plurality of pillars 4 are disposed on the +Z side of the conductive layer 3. The plurality of pillars 4 are arranged in the XY direction. Each pillar 4 extends in the Z direction and penetrates the stack SST (see FIG. 2).

[0069] The laminate SST has a structure in which a plurality of laminates SST1 and SST2 are laminated. In Fig. 6, the laminate SST is divided into two laminates SST1 and SST2, but the laminate SST may be divided into three or more laminates.

[0070] Each columnar body 4 has a tier 4a, a joint portion 4b, a tier 4c, and a cap layer 4d stacked in this order on the +Z side of the conductive layer 3. The laminate SST has a laminate SST1, a joint layer JL, and a laminate SST2 stacked in this order on the +Z side of the conductive layer 3.

[0071] The laminates SST1 and SST2 are each formed by stacking conductive layers 6 functioning as word lines WL and the like with insulating layers 7 interposed therebetween. The tier 4a extends in the Z direction and penetrates the laminate SST1. The joint portion 4b has a Z position corresponding to the joint layer JL. The joint layer JL may be formed of a material mainly composed of an oxide (e.g., silicon oxide). The tier 4c extends in the Z direction and penetrates the laminate SST2. The +Z side end of the tier 4a is coupled to the tier 4c via the joint portion 4b. The cap layer 4d extends in a plate shape in the XY direction and covers the +Z side end of the tier 4c. The cap layer 4d may be formed of a material mainly composed of a semiconductor (e.g., polysilicon) containing impurities, for example. A conductive layer 9 is disposed on the +Z side of the laminate SST2 with interlayer insulating films 82 and 83 interposed therebetween. The conductive layer 9 may be formed of a material mainly composed of a conductive material (e.g., a metal such as tungsten). The conductive layer 9 extends in a line shape in the Y direction and functions as a bit line BL (see FIG. 2). The cap layer 4d is connected to the bit line BL via a contact plug 31.

[0072] As shown in Fig. 7, the columnar body 40 has a core member 41, a semiconductor film 42, and an insulating film 43, in that order from the central axis CA side. The insulating film 43 is a multilayer film including an insulating film 43a, a charge storage film 43b, and an insulating film 43c, in that order from the central axis CA side. Fig. 7(a) is a YZ cross-sectional view showing the configuration of the memory cell, and is an enlarged cross-sectional view of part A in Fig. 6. Fig. 7(b) is an XY cross-sectional view showing the configuration of the memory cell, and is a cross-section taken along line BB in Fig. 7(a).

[0073] The core member 41 has a generally cylindrical shape disposed in the vicinity of the central axis CA of the columnar body 40 and extending along the central axis CA of the columnar body 40. The core member 41 may be formed of a material containing an insulator (for example, a semiconductor oxide such as silicon oxide) as a main component.

[0074] The semiconductor film 42 is disposed so as to surround the core member 41 from the outside, and has a generally cylindrical shape extending along the central axis CA of the columnar body 40. The semiconductor film 42 further covers the end of the core member 41 on the -Z side, and is connected to the conductive film 3. The semiconductor film 42 can be formed of a material mainly composed of a semiconductor (e.g., polysilicon) that does not substantially contain impurities.

[0075] The insulating film 43a is disposed so as to surround the semiconductor film 42 from the outside, and has a generally cylindrical shape extending along the central axis CA of the columnar body 40. The insulating film 43a may be made of a material containing an oxide (e.g., silicon oxide or silicon oxynitride) as a main component.

[0076] The charge storage film 43b is disposed so as to surround the insulating film 43a from the outside and has a substantially cylindrical shape extending along the central axis CA of the columnar body 40. The charge storage film 43b may be formed of a material containing nitride (for example, silicon nitride) as a main component.

[0077] The insulating film 43c is disposed so as to surround the charge storage film 43b from the outside and has a generally cylindrical shape extending along the central axis CA of the columnar body 40. The insulating film 43c may be formed of a material mainly composed of an oxide (e.g., silicon oxide, metal oxide, or a laminate of these). This may form an ONO-type three-layer structure in which the charge storage film 43b is sandwiched between a pair of insulating films 43a and 43c.

[0078] The insulating film 8 covers the insulating film 43c from the outside in the XY directions, and extends to cover the +Z side surface of the conductive layer 6, the surface on the columnar body 40 side, and the -Z side surface of the conductive layer 6, forming a substantially hollow disk shape having an axis along the Z direction. The insulating film 8 may be made of an insulating material such as aluminum oxide. In the following, for simplification, illustration and description of the insulating film 8 may be omitted.

[0079] The semiconductor film 42 of the columnar body 40 is connected to the conductive film 3 serving as the source line SL on the -Z side, and is connected to a conductive layer functioning as the bit line BL on the +Z side via a contact plug 31. That is, the semiconductor film 42 of the columnar body 40 includes a channel region (active region) in the memory string MST.

[0080] In each of the laminates SST1 and SST2 shown in FIG. 6, conductive layers 6 and insulating layers 7 are alternately and repeatedly laminated. Each conductive layer 6 extends in a plate shape in the XY direction. Each conductive layer 6 may be formed of a material mainly composed of a conductive material (e.g., a metal such as tungsten). Each conductive layer 6 may be covered with an insulating film 8 on the +Z side surface, the -Z side surface, and the surface facing the tiers 4a and 4c. The insulating film 8 may have a different composition from the insulator 43c. The insulating film 8 may be formed of a material mainly composed of an insulator (e.g., a metal oxide such as aluminum oxide, zirconium oxide, or hafnium oxide). Each insulating layer 7 extends in a plate shape in the XY direction. Each insulating layer 7 may be formed of a material mainly composed of an insulator (e.g., a semiconductor oxide such as silicon oxide).

[0081] In the stacked body SST1, of the multiple conductive layers 6 arranged spaced apart from each other in the Z direction, at least the conductive layer 6 closest to the -Z side functions as a selection gate SGS, and the other conductive layers 6 function as word lines WL0 to WL4.

[0082] A select transistor SGT is formed at a position where the conductive layer 6 of the select gate SGS intersects with the semiconductor film 42 and the charge storage film 43b. A memory cell MT0 is formed at a position where the conductive layer 6 of the word line WL0 intersects with the semiconductor film 42 and the charge storage film 43b. A memory cell MT1 is formed at a position where the conductive layer 6 of the word line WL1 intersects with the semiconductor film 42 and the charge storage film 43b. A memory cell MT2 is formed at a position where the conductive layer 6 of the word line WL2 intersects with the semiconductor film 42 and the charge storage film 43b. A memory cell MT3 is formed at a position where the conductive layer 6 of the word line WL3 intersects with the semiconductor film 42 and the charge storage film 43b. A memory cell MT4 is formed at a position where the conductive layer 6 of the word line WL4 intersects with the semiconductor film 42 and the charge storage film 43b. Note that the charge storage film 43b and the insulating film 43c may be partially omitted from the tier 4a at a position where the tier 4a intersects with the conductive layer 6 of the select gate SGS.

[0083] In a laminate SST2 stacked on a laminate SST1 via a joint layer JL, of multiple conductive layers 6 arranged at a distance from each other in the Z direction, at least the conductive layer 6 closest to the +Z side functions as a select gate SGD, and the other conductive layers 6 function as word lines WL5 to WL9.

[0084] A memory cell MT5 is formed at a position where the conductive layer 6 of the word line WL5 intersects with the semiconductor film 42 and the charge storage film 43b. A memory cell MT6 is formed at a position where the conductive layer 6 of the word line WL6 intersects with the semiconductor film 42 and the charge storage film 43b. A memory cell MT7 is formed at a position where the conductive layer 6 of the word line WL7 intersects with the semiconductor film 42 and the charge storage film 43b. A memory cell MT8 is formed at a position where the conductive layer 6 of the word line WL8 intersects with the semiconductor film 42 and the charge storage film 43b. A memory cell MT9 is formed at a position where the conductive layer 6 of the word line WL9 intersects with the semiconductor film 42 and the charge storage film 43b. A select transistor DGT is formed at a position where the conductive layer 6 of the select gate SGD intersects with the semiconductor film 42 and the charge storage film 43b. In addition, the charge storage film 43b and the insulating film 43c may be partially omitted from the tier 4c at a position where the tier 4c intersects with the conductive layer 6 of the select gate SGD.

[0085] In a process of writing information to a memory cell MT, a write voltage is applied to the conductive layer 6 of the selected word line WL, a transfer voltage is applied to the conductive layer 6 of the unselected word line WL, and a reference voltage is applied to the semiconductor film 42. The write voltage has a potential (e.g., 20V) for injecting charges (electrons) of the semiconductor film 42 into the charge storage film 43b. The transfer voltage has a potential (e.g., 10V) between the write voltage and the reference voltage. The reference voltage has a reference potential (e.g., 0V). As a result, charges are stored in the charge storage film 43b of the selected memory cell MT at the position where the conductive layer 6 of the selected word line WL intersects with the semiconductor film 42, and information is written to the selected memory cell MT.

[0086] In the process of erasing information from the memory cell MT, a reference voltage is applied to the conductive layer 6 of each word line WL, an erase voltage is applied to the semiconductor film 42, and an intermediate voltage between the two is applied to the selection gates SGS and SGD. The erase voltage has a potential (e.g., 20V) for injecting opposite charges (holes) of the semiconductor film 42 into the charge storage film 43b. The reference voltage has a reference potential (e.g., 0V). The intermediate voltage has a potential (e.g., 5V) between the erase process and the reference voltage. By such control, electron-hole pairs are generated by GIDL (Gate Induced Drain Leakage) near the drains of the selection transistors SGT and DGT, and the opposite charges (holes) are injected from the semiconductor film 42 into the charge storage film 43b. As a result, the charges stored in the charge storage film 43b are erased, and the information in the memory cell MT can be erased.

[0087] Next, the configuration and operation of the controller 302 in the test device 300 will be described.

[0088] 1, the controller 302 includes, in terms of hardware, a processor 302a, a volatile memory 302b, and a non-volatile memory 302c. The non-volatile memory 302c may store a program PG for testing memory cells.

[0089] 8, the controller 302 functionally includes a write processing unit 3021, a read processing unit 3022, an acquisition unit 3023, a threshold calculation unit 3024, a slope calculation unit 3025, a degradation component calculation unit 3026, a threshold calculation unit 3027, a slope calculation unit 3028, a degradation component calculation unit 3029, and a notification unit 3030. FIG. 8 is a block diagram showing the functional configuration of the controller 302.

[0090] In the controller 302, each unit shown in Fig. 8 may be realized in hardware (for example, as a circuit), or may be realized in software, or some may be realized in hardware and the rest may be realized in software. When each unit shown in Fig. 8 is realized in software, the controller 302 may execute the program PG to functionally construct each unit shown in Fig. 8 on the volatile memory 302b either collectively at the time of compilation or sequentially as the processing progresses.

[0091] The write processing unit 3021 generates a write command in response to an instruction from a user via the input unit 305 or autonomously in response to the establishment of a predetermined condition, and reads out test data 303a from the storage unit 303. The write processing unit 3021 supplies the write command and test data 303a to the interface unit 301. The write command includes an address of a memory cell to be tested. The interface unit 301 supplies the write command and test data 303a to the semiconductor storage device 1 via the communication medium 400.

[0092] When the semiconductor memory device 1 receives a write command and test data, it can perform a write process of the test data to a memory cell addressed by the write command. In the write process, as shown in FIG. 9, a write operation and a verify operation are repeated while increasing the write voltage. FIG. 9 is a diagram showing a write process to a memory cell MT. FIG. 9 illustrates a case where the verify is OK after six write operations in a write process using a write start voltage Vws0 and an increase width ΔVpgm of the write voltage, and the write time is WT0. When the verify operation is OK and the write process of the test data to the memory cell MT is completed, the semiconductor memory device 1 transmits a write completion notification to the interface unit 301 via the communication medium 400.

[0093] Upon receiving the write completion notification, the interface unit 301 supplies the write completion notification to the controller 302 .

[0094] 8 generates a read command autonomously in response to an instruction from a user via the input unit 305 or in response to the establishment of a predetermined condition. The read command includes an address of a memory cell to be tested. The read processing unit 3022 may generate a read command including an address of a memory cell to which a write process has been performed. The read processing unit 3022 supplies the read command to the interface unit 301.

[0095] When the semiconductor memory device 1 receives a read command, it can perform a read process on the memory cell addressed by the read command. In the read process, the cell current is detected while sweeping the read voltage for each memory cell, for example, as shown in FIG. 10 or FIG. 11. FIG. 10 is a diagram showing a process PC1 for determining the threshold voltage of the memory cell MT. FIG. 11 is a diagram showing a process PC2 for determining the threshold voltage of the memory cell MT.

[0096] When the read process of the memory cell is completed, the semiconductor memory device 1 generates read characteristic information. The read characteristic information indicates the read characteristic. The read characteristic indicates the relationship between the read voltage and the logarithm of the cell current. The semiconductor memory device 1 generates read characteristic information indicating the read characteristics Pf1 to Pf3, for example, as shown in FIG. 10 or FIG. 11. In FIG. 10 or FIG. 11, the vertical axis indicates the logarithm of the cell current, and the horizontal axis indicates the read voltage. In FIG. 10 or FIG. 11, the read voltage=0 on the vertical axis, and the cell current=0 on the horizontal axis. In FIG. 10 or FIG. 11, a read process is performed on each memory cell MT written in the multi-level cell (MLC) mode, and the read characteristics Pf1, Pf2, and Pf3 corresponding to the states ST1, ST2, and ST3 are illustrated.

[0097] Each of the read characteristics Pf1 to Pf3 has a subthreshold region and an overdrive region. In the subthreshold region of the read characteristic Pf, the logarithm of the cell current increases linearly and steeply as the read voltage increases. In the overdrive region of the read characteristic Pf, the logarithm of the cell current increases nonlinearly and gently as the read voltage increases. In each of the read characteristics Pf1 to Pf3, the slope of the tangent tends to be maximum near the boundary between the subthreshold region and the overdrive region.

[0098] The semiconductor memory device 1 transmits the read characteristic information to the interface unit 301 via the communication medium 400 .

[0099] The interface unit 301 receives the read characteristic information. When the interface unit 301 acquires the read characteristic information 303b, the interface unit 301 supplies the read characteristic information 303b to the acquisition unit 3023 shown in FIG.

[0100] The threshold calculation unit 3024 performs process PC1 on the read characteristics indicated by the read characteristic information 303b to obtain the threshold voltage of the memory cell. Process PC1 is a process for obtaining the threshold voltage by focusing on the overdrive region in the read characteristics. Process PC1 includes a process for obtaining a voltage corresponding to a tangent near the boundary between the subthreshold region and the overdrive region in the read characteristics as the threshold voltage. Process PC1 may include a process using the GM-MAX method.

[0101] For example, for the graph of the read characteristic Pf1 shown in Fig. 10, the threshold calculation unit 3024 calculates the slope of the tangent corresponding to the read voltage value while changing the read voltage value, and determines the coordinate point CP1 including the read voltage value at which the slope of the tangent is maximum. The threshold calculation unit 3024 determines the intersection point CX1 between the tangent line TL1 of the coordinate point CP1 to the graph of the read characteristic Pf1 and the horizontal axis (cell current = 0). The threshold calculation unit 3024 sets the read voltage value at the intersection point CX1 as the threshold voltage Vth1.

[0102] For the graph of the read characteristic Pf2, the threshold calculation unit 3024 calculates the slope of the tangent corresponding to the read voltage value while changing the read voltage value, and determines the coordinate point CP2 including the read voltage value at which the slope of the tangent is maximum. The threshold calculation unit 3024 determines the intersection point CX2 between the tangent line TL2 of the coordinate point CP2 for the graph of the read characteristic Pf2 and the horizontal axis (cell current=0). The threshold calculation unit 3024 sets the read voltage value at the intersection point CX2 as the threshold voltage Vth2.

[0103] For the graph of the read characteristic Pf3, the threshold calculation unit 3024 calculates the slope of the tangent corresponding to the read voltage value while changing the read voltage value, and determines the coordinate point CP3 including the read voltage value at which the slope of the tangent is maximum. The threshold calculation unit 3024 determines the intersection point CX3 between the tangent line TL3 of the coordinate point CP3 for the graph of the read characteristic Pf3 and the horizontal axis (cell current=0). The threshold calculation unit 3024 sets the read voltage value at the intersection point CX3 as the threshold voltage Vth3.

[0104] As shown in FIG. 10, the process PC1 for determining the threshold voltage with a focus on the overdrive region makes it possible to determine the threshold voltage while removing the influence of the fringe effect (the influence of the deterioration of the slope in the subthreshold region).

[0105] The threshold calculation unit 3024 shown in FIG. 8 supplies the threshold voltage calculated in the process PC1 to the slope calculation unit 3025.

[0106] The slope calculation unit 3025 generates threshold characteristic information 303c based on the threshold voltage obtained in the process PC1. The threshold characteristic information 303c indicates a threshold characteristic TP1. The threshold characteristic TP1 indicates the relationship between the write voltage and the threshold voltage in the write process. As shown by the dotted line in FIG. 12, the slope calculation unit 3025 may obtain the threshold characteristic TP1 by plotting the threshold voltage obtained in the process PC1 and the write voltage during the write process on a plane having the coordinate axes, and generate the threshold characteristic information 303c. FIG. 12 is a diagram showing the relationship between the threshold voltage Vth and the write voltage Vpgm of the memory cell MT. In FIG. 12, the threshold characteristic TP1 is shown as an approximately straight line. In the threshold characteristic TP1, the threshold voltage Vth tends to increase linearly as the write voltage Vpgm increases.

[0107] The slope calculation unit 3025 calculates a slope SL1 in the threshold characteristic TP1. The slope SL1 indicates the gradient of the change in the threshold voltage with respect to the write voltage. The slope SL1 corresponds to the gradient of the straight line of the threshold characteristic TP1 shown in FIG. 12. The slope calculation unit 3025 supplies the slope SL1 to the degradation component calculation unit 3026.

[0108] The degradation component calculation unit 3026 shown in FIG. 8 generates slope degradation component information 303d according to the slope SL1. The slope degradation component information 303d indicates a slope degradation component ΔDS1. The degradation component calculation unit 3026 may obtain the threshold characteristic TP0 based on ideal conditions. For example, the degradation component calculation unit 3026 may perform a simulation under ideal conditions and obtain the threshold characteristic TP0 shown by the dashed line in FIG. 12 according to the simulation result. In FIG. 12, the threshold characteristic TP0 is shown as an approximately straight line. The degradation component calculation unit 3026 may calculate the slope SL0 in the threshold characteristic TP0. The slope SL0 corresponds to the slope of the straight line of the threshold characteristic TP0 shown in FIG. 12. The degradation component calculation unit 3026 may obtain the slope degradation component ΔDS1 by subtracting the slope SL1 from the slope SL0. The slope degradation component ΔDS1 corresponds to the difference between the slope of the straight line of the threshold characteristic TP0 and the slope of the straight line of the threshold characteristic TP1 shown in FIG. 12. The degradation component calculation unit 3026 stores the slope degradation component information 303 d in the storage unit 303 .

[0109] The threshold calculation unit 3027 performs process PC2 on the read characteristics indicated by the read characteristic information 303b to obtain the threshold voltage of the memory cell. Process PC2 is a process for obtaining the threshold voltage by focusing on the subthreshold region in the read characteristics. Process PC2 includes a process for obtaining the voltage corresponding to the approximation line of the subthreshold region in the read characteristics as the threshold voltage.

[0110] 11, the threshold calculation unit 3027 calculates an approximation line PL1 in the subthreshold region and obtains an intersection CX11 between the approximation line PL1 and the horizontal axis (cell current=0). The threshold calculation unit 3027 sets the read voltage value at the intersection CX11 as the threshold voltage Vth11.

[0111] For the graph of the read characteristic Pf2, the threshold calculation unit 3027 calculates an approximation line PL2 in the subthreshold region, and obtains an intersection CX12 between the approximation line PL2 and the horizontal axis (cell current=0). The threshold calculation unit 3027 sets the read voltage value at the intersection CX12 as the threshold voltage Vth12.

[0112] For the graph of the read characteristic Pf3, the threshold calculation unit 3027 calculates an approximation line PL3 in the subthreshold region, and obtains an intersection CX13 between the approximation line PL3 and the horizontal axis (cell current=0). The threshold calculation unit 3027 sets the read voltage value at the intersection CX13 as the threshold voltage Vth13.

[0113] As shown in FIG. 11, according to the process PC2 for determining the threshold voltage with a focus on the subthreshold region, the threshold voltage can be determined in a form including the influence of the fringe effect (the influence of the deterioration of the slope in the subthreshold region).

[0114] The threshold calculation unit 3027 shown in FIG. 8 supplies the threshold voltage calculated in the process PC2 to the slope calculation unit 3028.

[0115] The slope calculation unit 3028 generates threshold characteristic information 303e based on the threshold voltage obtained in the process PC2. The threshold characteristic information 303e indicates threshold characteristic TP2. The threshold characteristic TP2 indicates the relationship between the write voltage and the threshold voltage in the write process. As shown by the solid line in FIG. 12, the slope calculation unit 3028 may obtain threshold characteristic TP2 by plotting the threshold voltage obtained in the process PC2 and the write voltage during the write process on a plane having the coordinate axes, and generate threshold characteristic information 303e. In FIG. 12, the threshold characteristic TP2 is shown as an approximately straight line. In the threshold characteristic TP2, the threshold voltage Vth tends to increase linearly as the write voltage Vpgm increases.

[0116] The slope calculation unit 3028 calculates a slope SL2 in the threshold characteristic TP2. The slope SL2 indicates the gradient of the change in the threshold voltage with respect to the write voltage. The slope SL2 corresponds to the gradient of the straight line of the threshold characteristic TP2 shown in FIG. 12. The slope calculation unit 3028 supplies the slope SL2 to the degradation component calculation unit 3029.

[0117] The degradation component calculation unit 3029 shown in FIG. 8 generates slope degradation component information 303f according to the slope SL2. The slope degradation component information 303f indicates a slope degradation component ΔDS2. The degradation component calculation unit 3029 may obtain the slope degradation component ΔDS2 by subtracting the slope SL2 from the slope SL1. The slope degradation component ΔDS2 corresponds to the difference between the slope of the straight line of the threshold characteristic TP1 and the slope of the straight line of the threshold characteristic TP2 shown in FIG. 12. The degradation component calculation unit 3029 stores the slope degradation component information 303f in the storage unit 303.

[0118] The notification unit 3030 reads out the slope degradation component information 303d and the slope degradation component information 303f from the storage unit 303. The notification unit 3030 may display the slope degradation component ΔDS1 and the slope degradation component ΔDS2 on the display screen 304a of the display unit 304. The notification unit 3030 may display the slope degradation component information 303d and the slope degradation component information 303f on the display screen 304a of the display unit 304 in a form in which the magnitude relationship between the slope degradation component ΔDS1 and the slope degradation component ΔDS2 can be recognized. This allows the test device 300 to notify the user of the slope degradation component ΔDS1 and the slope degradation component ΔDS2. When a memory cell has a defect, the cause of the defect can be predicted to some extent by comparing the slope degradation component ΔDS1 and the slope degradation component ΔDS2.

[0119] For example, if the slope degradation component ΔDS1 is larger than the slope degradation component ΔDS2 when a memory cell has a defect, it can be predicted that the defect is mainly caused by a decrease in the carrier capture efficiency of the memory cell. This makes it possible to prompt the user to take measures against the decrease in the carrier capture efficiency of the memory cell.

[0120] Alternatively, if the slope degradation component ΔDS2 is larger than the slope degradation component ΔDS1 when a memory cell has a defect, it can be predicted that the defect is mainly caused by the fringe effect of the memory cell. This makes it possible to prompt the user to take measures against the fringe effect of the memory cell.

[0121] Next, the slope degradation component will be described with reference to Figs. 12 to 14. Fig. 13 is a diagram showing a change in the band diagram due to the slope degradation component. Fig. 14 is a diagram showing a change in the read characteristics due to the fringe effect and a change in the read characteristics due to a decrease in carrier capture efficiency. Fig. 13 shows a band diagram during writing in the structure of "semiconductor film 42 / insulating film 43a / charge storage film 43b / insulating film 43c / insulating film 8 / conductive layer 6" (see Fig. 7(a)). The horizontal direction indicates the XY position in the cross section passing through the central axis CA, and the vertical direction indicates the height of the potential for electrons. The potential for electrons has the opposite polarity to the electric potential.

[0122] In FIG. 13, the potential diagram for electrons immediately before the first write voltage Vws0 (see FIG. 9) is applied to the conductive layer 6 during writing and the voltage is dropped is shown by a solid line. In addition, consider the potential diagram for electrons immediately before the voltage is dropped when Vws0+ΔVpgm, which is increased by ΔVpgm, is applied to the conductive layer 6 as the second write voltage. As shown by the dotted arrow, when the charge (electrons) tunnel-injected from the semiconductor film 42 into the insulating film 43a (tunnel insulating film) is captured by the charge storage film 43b, the potential diagram for electrons shown by the solid line changes, for example, as shown by the dashed line. Under ideal conditions, the electric field applied to the insulating film 43a, and therefore the potential for electrons, should be the same as that during the first write. Naturally, the charge written into the charge storage film through the second write operation causes the potential to bend upwards, which should push down the potential of the conductive layer 6 by ΔVth. However, at the same time, the potential difference of the conductive layer 6 between the first write operation and the second write operation must be ΔVpgm. In other words, under ideal conditions, ΔVpgm=ΔVth is satisfied, and the slope of the ideal threshold characteristic TP0 shown in FIG. 12 is approximately 1.

[0123] However, suppose that a problem during writing causes a slope degradation, and the slope of the threshold characteristic TP1 or TP2 shown in FIG. 12 becomes ΔVth / ΔVpgm<1. ​​In this case, ΔVpgm>ΔVth, and the slope (electric field) of the dashed-dotted line in FIG. 13 is forcibly increased, so that the potential of the conductive layer 6 must be further reduced by (ΔVpgm-ΔVth). In other words, the potential diagram for electrons immediately before the second write voltage falls changes from the dashed-dotted line in FIG. 13 to the dotted line. Then, the electric field and potential applied to the insulating film 43a (tunnel insulating film) increase with the number of times the write operation is repeated.

[0124] At this time, as the write voltage Vpgm increases, the electric field of the insulating film 43a and thus the tunnel current should increase, but experiments have shown that the essential ΔVth does not increase. In other words, it is considered that the electron capture efficiency is reduced enough to cancel out the increase in the tunnel current. In other words, in a write operation accompanied by slope deterioration due to a problem during writing, the tunnel current tends to increase (e.g., X times) and its capture efficiency tends to decrease (e.g., 1 / X times). In this case, as shown in FIG. 14(b), the read characteristics may shift to the low voltage side. In FIG. 14(b), a change in the read characteristics due to a decrease in the carrier capture efficiency is illustrated as a shift of the measured subthreshold characteristics shown by the solid line to the low voltage side with respect to the ideal read characteristics shown by the dotted line.

[0125] On the other hand, problems during reading can cause slope degradation. For example, when reading data from a memory cell with a high threshold voltage Vth, an electric field caused by the word line WL to which a high read voltage is applied propagates to the semiconductor film 42 between the word lines WL, and the subthreshold coefficient of the read characteristics is degraded by the electric field that is deflected to the back side of the channel, as shown in FIG. 14(a). In this case, the higher the threshold voltage Vth and thus the read voltage, the greater the degradation of the electric field that is deflected to the back side of the channel, and thus the subthreshold coefficient.

[0126] FIG. 14(a) illustrates an example of a change in read characteristics due to the fringe effect, in which the measured subthreshold coefficient shown by the solid line becomes larger than the ideal subthreshold coefficient shown by the dotted line. Due to the three-dimensional fringe effect during reading, the higher the level of the state ST (see FIG. 5), the more significant the degradation of the subthreshold coefficient and, in turn, the decrease in the threshold voltage Vth. As a result, as shown in FIG. 12, the slope of the threshold characteristic is less than 1, as in the threshold characteristic TP1 or TP2. On the other hand, FIG. 14(b) illustrates the degradation of the slope of the threshold characteristic due to a problem during writing. When under the influence of this effect, even if the influence of the degradation of the subthreshold coefficient accompanying the increase in the threshold voltage Vth is removed, the slope of the threshold characteristic is less than 1. In FIG. 14(a) and FIG. 14(b), the vertical axis indicates the logarithm of the cell current, and the horizontal axis indicates the read voltage.

[0127] Next, the operation of the test device 300 will be described with reference to Fig. 15. Fig. 15 is a flowchart showing the operation of the test device 300.

[0128] In the test device 300, the controller 302 controls the semiconductor memory device 1 to execute a write process (S1). The controller 302 generates a write command for testing, and supplies the write command and test data to the semiconductor memory device 1 via the interface unit 301 and the communication line 400. This causes the write process to be performed in the semiconductor memory device 1. In the write process, a write operation and a verify operation are repeated while increasing the write voltage. The write process may be performed by the ISPP method.

[0129] The controller 302 controls the semiconductor memory device 1 to execute a read process, and acquires the read characteristics from the semiconductor memory device 1 (S2). The controller 302 generates a read command, and supplies the read command to the semiconductor memory device 1 via the interface unit 301 and the communication line 400. This causes the semiconductor memory device 1 to perform the read process. In the read process, the cell current is detected while sweeping the read voltage. The controller 302 acquires the read characteristics from the semiconductor memory device 1 via the communication line 400 and the interface unit 301 as a response to the read command.

[0130] When S2 is completed, the processes of S3 to S5 and the processes of S6 to S7 are carried out in parallel.

[0131] The controller 302 performs process PC1 on the read characteristics to calculate the threshold voltage of the memory cell (S3). Process PC1 is a process for obtaining a threshold voltage by focusing on an overdrive region in the read characteristics. Process PC1 includes a process for obtaining a voltage corresponding to a tangent near the boundary between a subthreshold region and an overdrive region in the read characteristics as the threshold voltage. Process PC1 may include a process using the GM-MAX method.

[0132] The controller 302 calculates a slope SL1 based on the threshold voltage calculated in S3 (S4). The controller 302 calculates a threshold characteristic TP1 based on the threshold voltage calculated in process PC1. The threshold characteristic TP1 indicates the relationship between the write voltage and the threshold voltage in the write process. The controller 302 may calculate the threshold characteristic TP1 by plotting the threshold voltage calculated in process PC1 and the write voltage during the write process on a plane whose coordinate axes are the threshold voltage calculated in process PC1 and the write voltage during the write process. The controller 302 calculates a slope SL1 in the threshold characteristic TP1.

[0133] The controller 302 calculates a slope degradation component ΔDS1 based on the slope SL1 calculated in S4 (S5). The controller 302 may obtain a threshold characteristic TP0 based on an ideal condition and calculate a slope SL0 in the threshold characteristic TP0. The controller 302 may obtain a slope degradation component ΔDS1 by subtracting the slope SL1 from the slope SL0.

[0134] Meanwhile, the controller 302 performs process PC2 on the read characteristics to calculate the threshold voltage of the memory cell (S6). Process PC2 is a process for obtaining the threshold voltage by focusing on the subthreshold region in the read characteristics. Process PC2 includes a process for obtaining the voltage corresponding to the approximation line of the subthreshold region in the read characteristics as the threshold voltage.

[0135] The controller 302 calculates a slope SL2 based on the threshold voltage calculated in S6 (S7). The controller 302 calculates a threshold characteristic TP2 based on the threshold voltage calculated in process PC2. The threshold characteristic TP2 indicates the relationship between the write voltage and the threshold voltage in the write process. The controller 302 may calculate the threshold characteristic TP2 by plotting the threshold voltage calculated in process PC2 and the write voltage during the write process on a plane whose coordinate axes are the threshold voltage calculated in process PC2 and the write voltage during the write process. The controller 302 calculates a slope SL2 in the threshold characteristic TP2.

[0136] When both S5 and S7 are completed, the controller 302 calculates a slope degradation component ΔDS1 based on the slope SL1 calculated in S4 and the slope SL2 calculated in S7 (S8). The controller 302 may obtain the slope degradation component ΔDS2 by subtracting the slope SL2 from the slope SL1.

[0137] The controller 302 notifies the user of the slope degradation components ΔDS1 and ΔDS2 (S9). The controller 302 may display the slope degradation components ΔDS1 and ΔDS2 on the display screen 304a of the display unit 304. The controller 302 may display the slope degradation component information 303d and the slope degradation component information 303f on the display screen 304a of the display unit 304 in a form that allows the user to recognize the magnitude relationship between the slope degradation components ΔDS1 and ΔDS2. This allows the test device 300 to notify the user of the slope degradation components ΔDS1 and ΔDS2. When a memory cell has a defect, the cause of the defect can be predicted to some extent by comparing the slope degradation components ΔDS1 and ΔDS2.

[0138] For example, if the slope degradation component ΔDS1 is larger than the slope degradation component ΔDS2 when a memory cell has a defect, it can be predicted that the defect is mainly caused by a decrease in the carrier capture efficiency of the memory cell. This makes it possible to prompt the user to take measures against the decrease in the carrier capture efficiency of the memory cell.

[0139] Alternatively, if the slope degradation component ΔDS2 is larger than the slope degradation component ΔDS1 when a memory cell has a defect, it can be predicted that the defect is mainly caused by the fringe effect of the memory cell. This makes it possible to prompt the user to take measures against the fringe effect of the memory cell.

[0140] As described above, in the embodiment, the controller 302 of the test device 300 performs the process PC1 focusing on the overdrive region on the read characteristics of the memory cell on which the write process has been performed in the test of the semiconductor memory device 1 to obtain the threshold voltage. This makes it possible to obtain the threshold voltage by removing the influence of the fringe effect (the influence of the degradation of the slope in the subthreshold region). The controller 302 calculates the slope SL1 in the threshold characteristic TP1 showing the relationship between the write voltage and the threshold voltage based on the threshold voltage obtained by the process PC1, and obtains the slope degradation component ΔDS1 by subtracting the slope SL1 from the slope SL0 in the ideal threshold characteristic TP0. This makes it possible to separate the component showing the degradation due to the decrease in the carrier capture efficiency of the memory cell and obtain it as the slope degradation component ΔDS1.

[0141] In the embodiment, the controller 302 of the test device 300 performs a process PC2 focusing on the subthreshold region on the read characteristics of the memory cell on which the write process has been performed in the test of the semiconductor memory device 1 to obtain the threshold voltage. This allows the threshold voltage to be obtained in a form including the influence of the fringe effect (the influence of the degradation of the slope in the subthreshold region). The controller 302 calculates the slope SL2 in the threshold characteristic TP2 indicating the relationship between the write voltage and the threshold voltage in the write process based on the threshold voltage obtained by the process PC2, and obtains the slope degradation component ΔDS2 by subtracting the slope SL2 from the slope SL1. This allows the component indicating the degradation due to the fringe effect of the memory cell to be separated and obtained as the slope degradation component ΔDS2.

[0142] As a first modification of the embodiment, in S3 of Fig. 15, the controller 302 of the test device 300 may perform a process PC11 as shown in Fig. 16 on the read characteristics instead of the process PC1 shown in Fig. 10 to calculate the threshold voltage of the memory cell. Fig. 16 is a diagram showing the process PC11 for calculating the threshold voltage of the memory cell in the first modification of the embodiment. In Fig. 16, the vertical axis indicates the logarithm of the cell current, and the horizontal axis indicates the read voltage.

[0143] Process PC11 is similar to process PC1 in that it is a process that determines the threshold voltage by focusing on the overdrive region in the read characteristics, but differs from process PC1 in that it determines the threshold voltage by shifting a copy of the waveform of the low-level read characteristics in the voltage direction.

[0144] 16, the controller 302 calculates an approximation line PL21 in the subthreshold region, and obtains an intersection point CX21 between the approximation line PL21 and the horizontal axis (cell current=0). The controller 302 sets the read voltage value at the intersection point CX21 as the threshold voltage Vth21.

[0145] In obtaining the threshold voltage for the graph of the read characteristic Pf2, the controller 302 non-logarithmizes the cell current in each of the read characteristics Pf1 and Pf2 to obtain the read characteristics Pf1' and Pf2'. The read characteristics Pf1' and Pf2' change non-linearly in the subthreshold region and the overdrive region. Although not shown, the waveforms of the read characteristics Pf1' and Pf2' are curved in the subthreshold region and the overdrive region.

[0146] The controller 302 shifts the copy of the waveform of the read characteristic Pf1' in the voltage direction, as indicated by the dotted white arrow. The controller 302 fits the waveform of the copied read characteristic Pf1' to the waveform of the read characteristic Pf2'. The controller 302 obtains the read characteristic Pf22 by logarithmizing the cell current in the fitted read characteristic Pf1'. In this way, the controller 302 obtains the waveform of the fitted read characteristic Pf22, as indicated by the dotted line. The overdrive region of the fitted read characteristic Pf22 almost overlaps with the overdrive region of the read characteristic Pf2. The controller 302 obtains the threshold voltage corresponding to the read characteristic Pf2 using the waveform of the read characteristic Pf22. That is, the controller 302 calculates an approximation line PL22 of the subthreshold region of the read characteristic Pf22, and obtains an intersection CX22 between the approximation line PL22 and the horizontal axis (cell current=0). The controller 302 sets the read voltage value of the node CX22 as the threshold voltage Vth22.

[0147] In addition, when a method is adopted in which the read characteristics Pf1 and Pf2 in which the cell current is logarithmicized are obtained based on the read characteristics Pf1' and Pf2' in which the cell current is not logarithmicized, the read characteristics Pf1' and Pf2' are stored in advance in the memory unit 303, and in the process PC11, the stored read characteristics Pf1' and Pf2' can be used in correspondence with the read characteristics Pf1 and Pf2, respectively.

[0148] In obtaining the threshold voltage for the graph of the read characteristic Pf3, the controller 302 non-logarithmizes the cell currents in the read characteristics Pf1 and Pf3, respectively, to obtain the read characteristics Pf1' and Pf3'. The read characteristics Pf1' and Pf3' change non-linearly in the subthreshold region and the overdrive region. Although not shown, the waveforms of the read characteristics Pf1' and Pf3' are curved in the subthreshold region and the overdrive region.

[0149] The controller 302 shifts the copy of the waveform of the read characteristic Pf1' in the voltage direction, as indicated by the dashed-dotted white arrow. The controller 302 fits the waveform of the copied read characteristic Pf1' to the waveform of the read characteristic Pf3'. The controller 302 obtains the read characteristic Pf23 by logarithmizing the cell current in the fitted read characteristic Pf1'. In this way, the controller 302 obtains the waveform of the fitted read characteristic Pf23, as indicated by the dashed-dotted line. The overdrive region of the fitted read characteristic Pf23 almost overlaps with the overdrive region of the read characteristic Pf3. The controller 302 obtains the threshold voltage corresponding to the read characteristic Pf3 using the waveform of the read characteristic Pf23. That is, the controller 302 calculates an approximation line PL23 of the subthreshold region of the read characteristic Pf23, and obtains an intersection CX23 between the approximation line PL23 and the horizontal axis (cell current=0). The controller 302 sets the read voltage value of the node CX23 as the threshold voltage Vth23.

[0150] In addition, when a method is adopted in which the read characteristics Pf1 and Pf3 in which the cell current is logarithmicized are obtained based on the read characteristics Pf1' and Pf3' in which the cell current is not logarithmicized, the read characteristics Pf1' and Pf3' are stored in advance in the memory unit 303, and in the process PC11, the stored read characteristics Pf1' and Pf3' can be used in correspondence with the read characteristics Pf1 and Pf3, respectively.

[0151] As shown in FIG. 16, the process PC11 for determining the threshold voltage with a focus on the overdrive region also makes it possible to determine the threshold voltage while removing the influence of the fringe effect (the influence of the deterioration of the slope in the subthreshold region).

[0152] Furthermore, the concept of the embodiment can be applied to testing memory cells that have undergone an erase process, in addition to testing memory cells that have undergone a write process.

[0153] As a second modified example of the embodiment, the controller 302 may further include, functionally, an erase processing unit 3031 shown in FIG. 8. The erase processing unit 3031 generates an erase command in response to an instruction from a user via the input unit 305 or autonomously in response to the establishment of a predetermined condition. The erase processing unit 3031 supplies the erase command to the interface unit 301. The erase command includes an address of a memory cell to be tested. The interface unit 301 supplies the erase command to the semiconductor memory device 1 via the communication medium 400.

[0154] When the semiconductor memory device 1 receives an erase command, it can perform an erase process on the memory cell addressed by the erase command. The erase process may be performed by an ISPE (Incremental Step Pulse Erasing) method. In the erase process, as shown in FIG. 17, an erase operation and a verify operation are repeated while increasing the erase voltage. FIG. 17 is a diagram showing an erase process on a memory cell MT. FIG. 17 illustrates a case where the verify is OK after six erase operations in an erase process using an erase start voltage Ves0 and an increase width ΔVera of the erase voltage, and the erase time is ET0. When the verify operation is OK and the erase process on the memory cell MT is completed, the semiconductor memory device 1 transmits an erase completion notification to the interface unit 301 via the communication medium 400.

[0155] Upon receiving the erase completion notification, the interface unit 301 supplies the erase completion notification to the controller 302 .

[0156] 8 generates a read command autonomously in response to an instruction from a user via the input unit 305 or in response to the establishment of a predetermined condition. The read command includes an address of a memory cell to be tested. The read processing unit 3022 may generate a read command including an address of a memory cell on which an erase process has been performed. The read processing unit 3022 supplies the read command to the interface unit 301.

[0157] When the semiconductor memory device 1 receives a read command, it can perform a read process on the memory cell addressed by the read command. In the read process, for each memory cell, the cell current is detected while sweeping the read voltage, for example, as shown in FIG. 18 or FIG. 19. FIG. 18 is a diagram showing a process PC1 for determining the threshold voltage of the memory cell MT. FIG. 19 is a diagram showing a process PC2 for determining the threshold voltage of the memory cell MT.

[0158] When the read process of the memory cell is completed, the semiconductor memory device 1 generates read characteristic information. The read characteristic information indicates the read characteristic. The read characteristic indicates the relationship between the read voltage and the logarithm of the cell current. The semiconductor memory device 1 generates read characteristic information indicating the read characteristic Pf0, for example, as shown in FIG. 18 or FIG. 19. In FIG. 18 or FIG. 19, the vertical axis indicates the logarithm of the cell current, and the horizontal axis indicates the read voltage. In FIG. 18 or FIG. 19, the read voltage=0 on the vertical axis, and the cell current=0 on the horizontal axis. In FIG. 18 or FIG. 19, a read process is performed on each memory cell MT written in the multi-level cell (MLC) mode, and the read characteristic Pf0 corresponding to the state ST0 is illustrated.

[0159] The read characteristic Pf0 has a subthreshold region and an overdrive region. In the subthreshold region, the logarithm of the cell current increases linearly and steeply as the read voltage increases. In the overdrive region, the logarithm of the cell current increases nonlinearly and gently as the read voltage increases. In the read characteristic Pf0, the slope of the tangent tends to be maximum near the boundary between the subthreshold region and the overdrive region.

[0160] The semiconductor memory device 1 transmits the read characteristic information to the interface unit 301 via the communication medium 400 .

[0161] The interface unit 301 receives the read characteristic information. When the interface unit 301 acquires the read characteristic information 303b, the interface unit 301 supplies the read characteristic information 303b to the acquisition unit 3023 shown in FIG.

[0162] The threshold calculation unit 3024 performs process PC1 on the read characteristics indicated by the read characteristic information 303b to obtain the threshold voltage of the memory cell. Process PC1 is a process for obtaining the threshold voltage by focusing on the overdrive region in the read characteristics. Process PC1 includes a process for obtaining a voltage corresponding to a tangent near the boundary between the subthreshold region and the overdrive region in the read characteristics as the threshold voltage. Process PC1 may include a process using the GM-MAX method.

[0163] For example, for the graph of the read characteristic Pf0 shown in Fig. 18, the threshold calculation unit 3024 calculates the slope of the tangent corresponding to the read voltage value while changing the read voltage value, and determines the coordinate point CP0 including the read voltage value at which the slope of the tangent is maximum. The threshold calculation unit 3024 determines the intersection point CX0 between the tangent TL0 of the coordinate point CP0 to the graph of the read characteristic Pf0 and the horizontal axis (cell current = 0). The threshold calculation unit 3024 sets the read voltage value at the intersection point CX0 as the threshold voltage Vth0.

[0164] As shown in FIG. 18, according to the process PC1 for determining the threshold voltage with a focus on the overdrive region, the influence of the fringe effect (the influence of the deterioration of the slope in the subthreshold region) can be removed to determine the threshold voltage.

[0165] The threshold calculation unit 3024 shown in FIG. 8 supplies the threshold voltage calculated in the process PC1 to the slope calculation unit 3025.

[0166] The slope calculation unit 3025 generates threshold characteristic information 303c based on the threshold voltage obtained in the process PC1. The threshold characteristic information 303c indicates a threshold characteristic TP11. The threshold characteristic TP11 indicates the relationship between the erase voltage and the threshold voltage in the erase process. As shown by the dotted line in FIG. 20, the slope calculation unit 3025 may obtain the threshold characteristic TP11 by plotting the threshold voltage obtained in the process PC1 and the erase voltage in the erase process on a plane whose coordinate axes are the threshold voltage and the erase voltage in the erase process, and generate the threshold characteristic information 303c. FIG. 20 is a diagram showing the relationship between the threshold voltage Vth and the erase voltage Vera of the memory cell MT. In FIG. 20, the threshold characteristic TP11 is shown as an approximately straight line. In the threshold characteristic TP11, the threshold voltage Vth tends to decrease linearly as the erase voltage Vera increases.

[0167] The slope calculation unit 3025 calculates a slope SL11 of the threshold characteristic TP11. The slope SL11 indicates the gradient of the change in threshold voltage with respect to the erase voltage. The slope SL11 corresponds to the gradient of the straight line of the threshold characteristic TP11 shown in FIG. The slope calculation unit 3025 supplies the slope SL11 to the degradation component calculation unit 3026.

[0168] The degradation component calculation unit 3026 shown in FIG. 8 generates slope degradation component information 303d according to the slope SL11. The slope degradation component information 303d indicates a slope degradation component ΔDS11. The degradation component calculation unit 3026 may obtain the threshold characteristic TP10 based on ideal conditions. For example, the degradation component calculation unit 3026 may perform a simulation under ideal conditions and obtain the threshold characteristic TP10 shown by the dashed line in FIG. 20 according to the simulation result. In FIG. 20, the threshold characteristic TP10 is shown as an approximately straight line. The degradation component calculation unit 3026 may calculate the slope SL10 in the threshold characteristic TP10. The slope SL10 corresponds to the inclination of the straight line of the threshold characteristic TP10 shown in FIG. 20. The degradation component calculation unit 3026 may obtain the slope degradation component ΔDS11 by subtracting the slope SL11 from the slope SL10. The slope degradation component ΔDS11 corresponds to the difference between the slope of the straight line of the threshold characteristic TP10 and the slope of the straight line of the threshold characteristic TP11 shown in Fig. 20. The degradation component calculation unit 3026 stores the slope degradation component information 303d in the storage unit 303.

[0169] The threshold calculation unit 3027 performs process PC2 on the read characteristics indicated by the read characteristic information 303b to obtain the threshold voltage of the memory cell. Process PC2 is a process for obtaining the threshold voltage by focusing on the subthreshold region in the read characteristics. Process PC2 includes a process for obtaining the voltage corresponding to the approximation line of the subthreshold region in the read characteristics as the threshold voltage.

[0170] 19, the threshold calculation unit 3027 calculates an approximation line PL0 in the subthreshold region and obtains an intersection CX10 between the approximation line PL0 and the horizontal axis (cell current=0). The threshold calculation unit 3027 sets the read voltage value at the intersection CX10 as the threshold voltage Vth10.

[0171] As shown in FIG. 19, according to the process PC2 for determining the threshold voltage with a focus on the subthreshold region, the threshold voltage can be determined in a form including the influence of the fringe effect (the influence of the deterioration of the slope in the subthreshold region).

[0172] The threshold calculation unit 3027 shown in FIG. 8 supplies the threshold voltage calculated in the process PC2 to the slope calculation unit 3028.

[0173] The slope calculation unit 3028 generates threshold characteristic information 303e based on the threshold voltage obtained in the process PC2. The threshold characteristic information 303e indicates a threshold characteristic TP2. The threshold characteristic TP2 indicates the relationship between the write voltage and the threshold voltage in the write process. As shown by the solid line in FIG. 20, the slope calculation unit 3028 may obtain a threshold characteristic TP12 by plotting the threshold voltage obtained in the process PC2 and the write voltage during the write process on a plane having the coordinate axes, and generate the threshold characteristic information 303e. In FIG. 20, the threshold characteristic TP12 is shown as an approximately straight line. In the threshold characteristic TP12, the threshold voltage Vth tends to decrease linearly as the erase voltage Vera increases.

[0174] The slope calculation unit 3028 calculates a slope SL12 of the threshold characteristic TP12. The slope SL12 indicates the gradient of the change in threshold voltage with respect to the erase voltage. The slope SL12 corresponds to the gradient of the straight line of the threshold characteristic TP12 shown in FIG. The slope calculation unit 3028 supplies the slope SL12 to the degradation component calculation unit 3029.

[0175] The degradation component calculation unit 3029 shown in FIG. 8 generates slope degradation component information 303f according to the slope SL12. The slope degradation component information 303f indicates a slope degradation component ΔDS12. The degradation component calculation unit 3029 may obtain the slope degradation component ΔDS12 by subtracting the slope SL12 from the slope SL11. The slope degradation component ΔDS12 corresponds to the difference between the slope of the straight line of the threshold characteristic TP11 and the slope of the straight line of the threshold characteristic TP12 shown in FIG. 20. The degradation component calculation unit 3029 stores the slope degradation component information 303f in the storage unit 303.

[0176] The notification unit 3030 reads out the slope degradation component information 303d and the slope degradation component information 303f from the storage unit 303. The notification unit 3030 may display the slope degradation component ΔDS11 and the slope degradation component ΔDS12 on the display screen 304a of the display unit 304. The notification unit 3030 may display the slope degradation component information 303d and the slope degradation component information 303f on the display screen 304a of the display unit 304 in a form in which the magnitude relationship between the slope degradation component ΔDS11 and the slope degradation component ΔDS12 can be recognized. In this way, the test device 300 can notify the user of the slope degradation component ΔDS11 and the slope degradation component ΔDS12. When a memory cell has a defect, the cause of the defect can be predicted to some extent by comparing the slope degradation component ΔDS11 and the slope degradation component ΔDS12.

[0177] For example, if the slope degradation component ΔDS11 is greater than the slope degradation component ΔDS12 when a memory cell has a defect, it can be predicted that the defect is mainly caused by a decrease in the carrier capture efficiency of the memory cell. This makes it possible to prompt the user to take measures against the decrease in the carrier capture efficiency of the memory cell.

[0178] Alternatively, if the slope degradation component ΔDS12 is greater than the slope degradation component ΔDS11 when a memory cell has a defect, it can be predicted that the defect is mainly caused by the fringe effect of the memory cell. This makes it possible to prompt the user to take measures against the fringe effect of the memory cell.

[0179] In this way, the controller 302 of the test device 300 performs the process PC1 focusing on the overdrive region on the read characteristics of the memory cell that has been erased in the test of the semiconductor memory device 1 to obtain the threshold voltage. This makes it possible to obtain the threshold voltage by removing the influence of the fringe effect (the influence of the degradation of the slope in the subthreshold region). The controller 302 calculates the slope SL11 in the threshold characteristic TP11 that indicates the relationship between the erase voltage and the threshold voltage based on the threshold voltage obtained by the process PC1, and obtains the slope degradation component ΔDS11 by subtracting the slope SL11 from the slope SL10 in the ideal threshold characteristic TP10. This makes it possible to separate the component that indicates the degradation due to the decrease in the carrier capture efficiency of the memory cell and obtain it as the slope degradation component ΔDS11.

[0180] Moreover, in testing the semiconductor memory device 1, the controller 302 of the test device 300 performs a process PC2 focusing on the subthreshold region on the read characteristics of the memory cell that has been erased, to obtain the threshold voltage. This allows the threshold voltage to be obtained in a form that includes the influence of the fringe effect (the influence of the degradation of the slope in the subthreshold region). The controller 302 calculates the slope SL12 in the threshold characteristic TP12 that indicates the relationship between the erase voltage and the threshold voltage in the erase process based on the threshold voltage obtained by the process PC2, and obtains the slope degradation component ΔDS12 by subtracting the slope SL12 from the slope SL11. This allows the component indicating the degradation due to the fringe effect of the memory cell to be separated and obtained as the slope degradation component ΔDS12.

[0181] In addition, in testing memory cells that have been erased, the controller 302 of the test device 300 may perform a process PC11 as shown in Fig. 16 on the read characteristics instead of the process PC1 to calculate the threshold voltage of the memory cell. The content of the process PC11 is the same as that of the first modified example of the embodiment. Therefore, the process PC11 that calculates the threshold voltage with attention to the overdrive region can also calculate the threshold voltage by removing the influence of the fringe effect (the influence of the deterioration of the slope in the subthreshold region).

[0182] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0183] 1 semiconductor memory device, 300 test device, 301 interface section, 302 controller, 303 memory section, 304 display section, 305 input section.

Claims

1. an interface unit for acquiring read characteristics indicating a relationship between a read voltage and a logarithm of a cell current of a memory cell in which a write process in which a write operation and a verify operation are repeated while increasing a write voltage is performed; a controller for performing a first process on the read characteristics, the first process being focused on a subthreshold region in the read characteristics as a first region and a second region being a region of a read voltage higher than a maximum read voltage of the first region, to obtain a threshold voltage of a memory cell, calculating a first slope in a first threshold characteristic indicating a relationship between a write voltage in the write process and a threshold voltage based on the threshold voltage obtained by the first process, and subtracting the first slope from a slope in an ideal threshold characteristic to obtain a first slope degradation component; A test device comprising:

2. The controller performs a second process on the read characteristics focusing on a first region in the read characteristics to obtain a threshold voltage of a memory cell, calculates a second slope in a second threshold characteristic indicating a relationship between a write voltage in the write process and a threshold voltage based on the threshold voltage obtained by the second process, and obtains a second slope degradation component by subtracting the second slope from the first slope.

2. The test device of claim 1.

3. The controller, as the first process, obtains a threshold voltage according to a tangent line at which a slope of a waveform of the read characteristics is maximum.

2. The test device of claim 1.

4. the interface unit acquires a first read characteristic and a second read characteristic of a memory cell; The controller, as the first process, uses a third read characteristic and a fourth read characteristic obtained by de-logarithmizing a cell current in the first read characteristic and the second read characteristic, shifts a copy of a waveform of the third read characteristic in a voltage direction and fits it to the waveform of the fourth read characteristic, logarithms the cell current in the fitted third read characteristic to obtain a waveform of a fifth read characteristic, and obtains a threshold voltage corresponding to the second read characteristic using the waveform of the fifth read characteristic.

2. The test device of claim 1.

5. The first slope degradation component indicates degradation in carrier capture efficiency of the memory cell.

2. The test device of claim 1.

6. the first slope degradation component indicates degradation in carrier capture efficiency of a memory cell; The second slope degradation component indicates degradation related to the fringe effect of the memory cell.

3. A test device as claimed in claim 2.

7. the interface unit acquires read characteristics indicating a relationship between a read voltage and a logarithm of a cell current of a memory cell that has been subjected to an erase process in which an erase operation and a verify operation are repeated while increasing an erase voltage; The controller performs the first process on the read characteristics to obtain a threshold voltage of the memory cell, calculates a third slope in a third threshold characteristic indicating a relationship between an erase voltage in the erase process and a threshold voltage based on the threshold voltage obtained in the first process, and obtains a third slope degradation component by subtracting the third slope from a slope in an ideal threshold characteristic.

2. A test device as claimed in claim 1.

8. The controller performs a second process on the read characteristics focusing on a first region in the read characteristics to obtain a threshold voltage of the memory cell, calculates a fourth slope in a fourth threshold characteristic indicating a relationship between an erase voltage in the erase process and a threshold voltage based on the threshold voltage obtained by the second process, and obtains a fourth slope degradation component by subtracting the fourth slope from the third slope.

8. A test device as claimed in claim 7.

9. acquiring a read characteristic indicating a relationship between a read voltage and a logarithm of a cell current of a memory cell in which a write process in which a write operation and a verify operation are repeated while increasing a write voltage is performed; determining a threshold voltage of a memory cell by subjecting the read characteristics to a first process in which a subthreshold region in the read characteristics is defined as a first region and a second region is defined as a region having a read voltage higher than a maximum read voltage of the first region; calculating a first slope of a threshold characteristic indicating a relationship between a write voltage and a threshold voltage in the write process based on the threshold voltage obtained in the first process; determining a first slope degradation component by subtracting the calculated first slope from a slope in an ideal threshold characteristic; Test methods including:

10. performing a second process on the read characteristic focusing on a first region in the read characteristic to obtain a threshold voltage of the memory cell; calculating a second slope of a threshold characteristic indicating a relationship between a write voltage and a threshold voltage in the write process based on the threshold voltage obtained in the second process; determining a second slope degradation component by subtracting the second slope from the first slope; Also includes 10. The test method according to claim 9.

11. acquiring read characteristics showing a relationship between a read voltage and a logarithm of a cell current of a memory cell that has been subjected to an erase process in which an erase operation and a verify operation are repeated while increasing an erase voltage; performing the first processing on the read characteristics to obtain a threshold voltage of the memory cell; calculating a third slope in a third threshold characteristic indicating a relationship between an erase voltage and a threshold voltage in the erase process based on the threshold voltage obtained in the first process; determining a third slope degradation component by subtracting the third slope from a slope in an ideal threshold characteristic; Also includes 10. The test method according to claim 9.

12. performing a second process on the read characteristic focusing on a first region in the read characteristic to obtain a threshold voltage of the memory cell; calculating a fourth slope in a fourth threshold characteristic indicating a relationship between an erase voltage and a threshold voltage in the erase process based on the threshold voltage obtained in the second process; determining a fourth slope degradation component by subtracting the fourth slope from the third slope; Also includes 12. The method of claim 11.

Images