Semiconductor memory device

Abstract

To provide a semiconductor memory device with high reliability.SOLUTION: A semiconductor memory device includes a first conductive layer and a second conductive layer adjacent to the first conductive layer in a first direction. Each of a plurality of write loops includes a first program operation for supplying a program voltage to the first conductive layer and for supplying a first bit line voltage to a bit line, and a second program operation for supplying the program voltage to the first conductive layer and for supplying a second bit line voltage larger than the first bit line voltage to the bit line. The program voltage increases by an offset voltage as the number of times the write loop is executed increases. The write operation includes a state determination operation that determines whether or not the second conductive layer is controlled to a Low state condition. If the second conductive layer is controlled to the Low state condition, the first program operation is executed, and if the second conductive layer is not controlled to the Low state condition, the second program operation is executed.SELECTED DRAWING: Figure 22

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art There is known a semiconductor memory device that includes a substrate, a plurality of first conductive layers aligned in a first direction intersecting a surface of the substrate, and a semiconductor layer extending in the first direction and facing the plurality of first conductive layers. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2020 / 0350022 [Patent Document 2] JP 2012-190523 A Summary of the Invention [Problem to be solved by the invention]

[0004] A highly reliable semiconductor memory device is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a substrate, a plurality of conductive layers arranged in a first direction intersecting a surface of the substrate, a first semiconductor layer extending in the first direction and facing the plurality of conductive layers, a charge storage layer provided between the plurality of conductive layers and the first semiconductor layer, a bit line electrically connected to one end of the first semiconductor layer in the first direction, and a control circuit electrically connected to the plurality of conductive layers and the bit line. The plurality of conductive layers include a first conductive layer and a second conductive layer adjacent to the first conductive layer in the first direction. The control circuit is configured to be able to execute a write operation, and the write operation includes a plurality of write loops. Each of the plurality of write loops includes a first program operation that supplies a program voltage to the first conductive layer, supplies a write pass voltage smaller than the program voltage to the second conductive layer, and supplies a first bit line voltage to the bit line, and a second program operation that supplies a program voltage to the first conductive layer, supplies a write pass voltage to the second conductive layer, and supplies a second bit line voltage larger than the first bit line voltage to the bit line. The program voltage increases by an offset voltage with an increase in the number of times the write loop is executed. The write operation includes a state determination operation for determining whether the second conductive layer is controlled to a low state. If the second conductive layer is controlled to a low state, a first program operation is executed, and if the second conductive layer is not controlled to a low state, a second program operation is executed. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic block diagram showing a configuration of a memory system 10 according to a first embodiment. [Diagram 2] FIG. 2 is a schematic side view showing a configuration example of the memory system 10. [Diagram 3] FIG. 2 is a schematic plan view showing the same configuration example. [Figure 4] 1 is a schematic block diagram showing a configuration of a memory die MD according to a first embodiment. [Diagram 5] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD according to the first embodiment. FIG. [Figure 6]2 is a schematic circuit diagram showing a configuration of a sense amplifier module SAM. [Figure 7] 2 is a schematic circuit diagram showing a configuration of a sense amplifier unit SAU. FIG. [Figure 8] 1 is a schematic exploded perspective view showing a configuration example of a semiconductor memory device according to a first embodiment. [Figure 9] 2 is a schematic bottom view showing an example of the configuration of the chip CM. FIG. [Figure 10] 2 is a schematic perspective view showing a configuration of a portion of a memory cell array MCA. FIG. [Figure 11] 2 is a schematic cross-sectional view showing a configuration of a portion of a memory cell array MCA. FIG. [Figure 12] 2 is a schematic diagram for explaining data recorded in a memory cell MC. FIG. [Figure 13] FIG. 2 is a diagram showing data stored in latch circuits XDL, ADL, BDL, CDL, TDL, and SDL. [Figure 14] 5 is a schematic flowchart for explaining a write operation according to the first embodiment. [Figure 15] FIG. 4 is a schematic waveform diagram for explaining a write operation according to the first embodiment. [Figure 16] FIG. 11 is a schematic cross-sectional view for explaining a program operation. [Figure 17] FIG. 11 is a schematic cross-sectional view for explaining a verify operation. [Figure 18] 11 is a schematic waveform diagram for explaining a read operation of an adjacent memory cell MC. FIG. [Figure 19] 11 is a schematic cross-sectional view for explaining a read operation of an adjacent memory cell MC. FIG. [Figure 20] FIG. 13 is a diagram for explaining the relationship between the number of loops nW and the program voltage VPGM. [Figure 21] FIG. 13 is a diagram for explaining the relationship between the number of loops nW and the program voltage VPGM. [Figure 22]4A to 4C are diagrams for explaining a program operation and a verify operation in the first embodiment; [Figure 23] 5A to 5C are schematic cross-sectional views for explaining the execution order of write operations in the first embodiment. [Figure 24] 4 is a schematic cross-sectional view showing a state of carriers after a write operation in the first embodiment. FIG. [Diagram 25] 6A and 6B are diagrams for explaining a downshift of a threshold voltage after a write operation in the first embodiment. [Figure 26] 10 is a schematic flowchart for explaining a write operation according to the second embodiment; [Figure 27] 11 is a schematic circuit diagram showing a configuration of a sense amplifier unit SAU according to a second embodiment. FIG. [Figure 28] 13A and 13B are diagrams for explaining a program operation and a verify operation in the second embodiment. [Figure 29] 13A to 13C are schematic cross-sectional views for explaining the execution order of write operations in the third embodiment. [Diagram 30] 13A to 13C are schematic cross-sectional views for explaining the execution order of write operations in the fourth embodiment. [Diagram 31] FIG. 13 is a schematic cross-sectional view showing a state of carriers after a write operation in the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example, and is not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments may be given the same reference numerals, and explanations may be omitted.

[0008] In addition, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0009] In addition, in this specification, the term "control circuit" may refer to a peripheral circuit such as a sequencer provided on a memory die, or may refer to a controller die or controller chip connected to a memory die, or may refer to a configuration that includes both of these.

[0010] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in an OFF state.

[0011] In addition, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0012] In addition, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in a current path between the two wirings, and that the transistor or the like is in an ON state.

[0013] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0014] In this specification, a direction along a predetermined plane may be referred to as a first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as a second direction, and a direction that intersects with this predetermined plane may be referred to as a third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0015] In this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "up," and the direction toward the substrate along the Z direction is called "down." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are called side surfaces, etc.

[0016] [First embodiment] [Memory System 10] FIG. 1 is a schematic block diagram showing the configuration of a memory system 10 according to the first embodiment.

[0017] The memory system 10 performs operations such as reading, writing, and erasing user data in response to a signal transmitted from a host computer 20. The memory system 10 is, for example, a memory chip, a memory card, an SSD, or other system capable of storing user data. The memory system 10 includes a plurality of memory dies MD that store user data, and a controller die CD that is connected to the plurality of memory dies MD and the host computer 20. The controller die CD includes, for example, a processor, a RAM, and the like, and performs processes such as conversion between logical addresses and physical addresses, bit error detection / correction, garbage collection (compaction), and wear leveling.

[0018] Fig. 2 is a schematic side view showing a configuration example of the memory system 10 according to this embodiment. Fig. 3 is a schematic plan view showing the same configuration example. For convenience of explanation, some components are omitted in Figs. 2 and 3.

[0019] 2, the memory system 10 according to the present embodiment includes a mounting substrate MSB, a plurality of memory dies MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory die MD. A pad electrode P is provided in an end region in the Y direction of the upper surface of the mounting substrate MSB, and the other region is bonded to the lower surface of the memory die MD via an adhesive or the like. A pad electrode P is provided in an end region in the Y direction of the upper surface of the memory die MD, and the other region is bonded to the lower surface of another memory die MD or the controller die CD via an adhesive or the like. A pad electrode P is provided in an end region in the Y direction of the upper surface of the controller die CD.

[0020] 3, the mounting substrate MSB, the memory dies MD, and the controller die CD each include a plurality of pad electrodes P arranged in the X direction. The pad electrodes P provided on the mounting substrate MSB, the memory dies MD, and the controller die CD are connected to each other via bonding wires B.

[0021] 2 and 3 are merely examples, and the specific configuration can be adjusted as appropriate. For example, in the example shown in FIG. 2 and FIG. 3, a controller die CD is stacked on a plurality of memory dies MD, and these configurations are connected by bonding wires B. In such a configuration, a plurality of memory dies MD and a controller die CD are included in one package. However, the controller die CD may be included in a package separate from the memory die MD. In addition, a plurality of memory dies MD and a controller die CD may be connected to each other via through electrodes or the like, instead of the bonding wires B.

[0022] [Circuit configuration of memory die MD] Fig. 4 is a schematic block diagram showing a configuration of a memory die MD according to the first embodiment. Fig. 5 is a schematic circuit diagram showing a configuration of a part of the memory die MD according to the first embodiment. Fig. 6 is a schematic circuit diagram showing a configuration of a sense amplifier module SAM. Fig. 7 is a schematic circuit diagram showing a configuration of a sense amplifier unit SAU.

[0023] FIG. 4 illustrates a plurality of control terminals. These control terminals may be represented as control terminals corresponding to a high active signal (positive logic signal), as control terminals corresponding to a low active signal (negative logic signal), or as control terminals corresponding to both a high active signal and a low active signal. In FIG. 4, the reference numerals of control terminals corresponding to low active signals include an overline. In this specification, the reference numerals of control terminals corresponding to low active signals include a slash (" / "). The description in FIG. 4 is an example, and the specific embodiment can be adjusted as appropriate. For example, it is possible to make some or all of the high active signals low active signals, and to make some or all of the low active signals high active signals.

[0024] 4, the memory die MD includes a memory cell array MCA for storing data, and a peripheral circuit PC connected to the memory cell array MCA. The peripheral circuit PC includes a voltage generating circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. The peripheral circuit PC also includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. The peripheral circuit PC also includes an input / output control circuit I / O, and a logic circuit CTR.

[0025] [Circuit configuration of memory cell array MCA] 5, the memory cell array MCA includes a plurality of memory blocks BLK. Each of the memory blocks BLK includes a plurality of string units SU. Each of the string units SU includes a plurality of memory strings MS. One end of each of the memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other ends of each of the memory strings MS are connected to the peripheral circuit PC via a common source line SL.

[0026] The memory string MS includes a drain side select transistor STD, a plurality of memory cells MC (memory transistors), a source side select transistor STS, and a source side select transistor STSb, which are connected in series between a bit line BL and a source line SL. Hereinafter, the drain side select transistor STD, the source side select transistor STS, and the source side select transistor STSb may be simply referred to as select transistors (STD, STS, STSb).

[0027] The memory cells MC are field-effect transistors including a semiconductor layer functioning as a channel region, a gate insulating film including a charge storage film, and a gate electrode. The threshold voltage of the memory cells MC varies depending on the amount of charge in the charge storage film. The memory cells MC store one or more bits of data. A word line WL is connected to each of the memory cells MC corresponding to one memory string MS. Each of these word lines WL functions as a gate electrode of the memory cells MC included in all the memory strings MS in one memory block BLK.

[0028] The selection transistors (STD, STS, STSb) are field-effect transistors including a semiconductor layer functioning as a channel region, a gate insulating film, and a gate electrode. The selection transistors (STD, STS, STSb) have their gate electrodes connected to selection gate lines (SGD, SGS, SGSb), respectively. The drain side selection gate line SGD is provided corresponding to the string unit SU, and functions as the gate electrodes of the drain side selection transistors STD included in all the memory strings MS in one string unit SU. The source side selection gate line SGS functions as the gate electrodes of the source side selection transistors STS included in all the memory strings MS in the multiple string units SU. The source side selection gate line SGSb functions as the gate electrodes of the source side selection transistors STSb included in all the memory strings MS in the multiple string units SU.

[0029] [Circuit configuration of voltage generation circuit VG] The voltage generating circuit VG (FIG. 4) is connected to a plurality of voltage supply lines 31, as shown in FIG. 5. The voltage generating circuit VG includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit 32. The step-down circuit and the step-up circuit each generate a power supply voltage V CC and ground voltage V SS The voltage generation circuit VG is connected to a voltage supply line to which voltages (FIG. 4) are supplied. These voltage supply lines are connected to, for example, the pad electrodes P described with reference to FIGS. 2 and 3. The voltage generation circuit VG generates a plurality of operating voltages to be applied to the bit lines BL, source lines SL, word lines WL and select gate lines (SGD, SGS, SGSb) during read operations, write operations and erase operations on the memory cell array MCA in accordance with, for example, a control signal from the sequencer SQC, and outputs these simultaneously to a plurality of voltage supply lines 31. The operating voltages output from the voltage supply lines 31 are appropriately adjusted in accordance with the control signal from the sequencer SQC.

[0030] [Circuit configuration of row decoder RD] The row decoder RD (FIG. 4) receives address data D ADDand a block selection circuit 23 and a voltage selection circuit 24 which transfer an operating voltage to the memory cell array MCA in response to an output signal of the address decoder 22.

[0031] The address decoder 22 includes a plurality of block selection lines BLKSEL and a plurality of voltage selection lines 33. The address decoder 22 sequentially refers to the row address RA of the address register ADR (FIG. 4) in accordance with, for example, a control signal from the sequencer SQC, decodes the row address RA, and turns on a predetermined block selection transistor 35 and a voltage selection transistor 37 corresponding to the row address RA, and turns off the other block selection transistors 35 and voltage selection transistors 37. For example, the voltages of the predetermined block selection line BLKSEL and voltage selection line 33 are set to the “H” state, and the other voltages are set to the “L” state. Note that when P-channel transistors are used instead of N-channel transistors, reverse voltages are applied to these wirings.

[0032] In the illustrated example, the address decoder 22 is provided with one block selection line BLKSEL for each memory block BLK. However, this configuration can be changed as appropriate. For example, the address decoder 22 may be provided with one block selection line BLKSEL for each of two or more memory blocks BLK.

[0033] The block selection circuit 23 includes a plurality of block selection units 34 corresponding to the memory blocks BLK. Each of the plurality of block selection units 34 includes a plurality of block selection transistors 35 corresponding to the word lines WL and the selection gate lines (SGD, SGS, SGSb). The block selection transistors 35 are, for example, field effect type voltage resistant transistors. The drain electrodes of the block selection transistors 35 are electrically connected to the corresponding word lines WL or selection gate lines (SGD, SGS, SGSb). The source electrodes are electrically connected to the voltage supply line 31 via the wiring CG and the voltage selection circuit 24. The gate electrodes are commonly connected to the corresponding block selection lines BLKSEL.

[0034] The block selection circuit 23 further includes a plurality of transistors (not shown). These transistors are connected to the selection gate lines (SGD, SGS, SGSb) and the ground voltage V SS These transistors are connected between the voltage supply lines that supply a ground voltage V SS It should be noted that the word lines WL included in the unselected memory blocks BLK are in a floating state.

[0035] The voltage selection circuit 24 includes a plurality of voltage selection units 36 corresponding to the word lines WL and the select gate lines (SGD, SGS, SGSb). Each of the plurality of voltage selection units 36 includes a plurality of voltage selection transistors 37. The voltage selection transistors 37 are, for example, field effect type voltage resistant transistors. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS, SGSb) via the wiring CG and the block selection circuit 23. The source terminals are electrically connected to the corresponding voltage supply lines 31. The gate electrodes are connected to the corresponding voltage selection lines 33.

[0036] In the illustrated example, the wiring CG is connected to the voltage supply line 31 via one voltage selection transistor 37. However, this configuration is merely an example, and the specific configuration can be adjusted as appropriate. For example, the wiring CG may be connected to the voltage supply line 31 via two or more voltage selection transistors 37.

[0037] [Circuit configuration of the sense amplifier module SAM] The sense amplifier module SAM (FIG. 4) includes a plurality of sense amplifier units SAU corresponding to a plurality of bit lines BL, as shown in FIG. 6. Each of the sense amplifier units SAU includes a sense amplifier SA connected to the bit line BL, a wiring LBUS connected to the sense amplifier SA, latch circuits SDL, ADL, BDL, CDL, and TDL connected to the wiring LBUS, and a precharge charge transistor 55 (FIG. 7) connected to the wiring LBUS. The wiring LBUS in the sense amplifier unit SAU is connected to a wiring DBUS via a switch transistor DSW.

[0038] 7, the sense amplifier SA includes a sense transistor 41 that discharges the charge on the line LBUS in response to the current flowing through the bit line BL. The source electrode of the sense transistor 41 is connected to the ground voltage V SS The sense node SEN is connected to a voltage supply line through which a voltage is supplied. The drain electrode is connected to the wiring LBUS via a switch transistor 42. The gate electrode is connected to the bit line BL via a sense node SEN, a discharge transistor 43, a node COM, a clamp transistor 44, and a voltage-resistant transistor 45. The sense node SEN is connected to an internal control signal line CLKSA via a capacitor 48.

[0039] In addition, the sense amplifier SA switches the node COM and the sense node SEN to a voltage V DD The voltage supply line or voltage V SRC The voltage transfer circuit includes a node N1, a charging transistor 46 connected between the node N1 and a sense node SEN, a charging transistor 49 connected between the node N1 and a node COM, and a voltage supply line to which the node N1 and the voltage V DD A charging transistor 47 is connected between the node N1 and the voltage supply line to which the voltage V SRCand a discharge transistor 50 connected between the voltage supply line to which the charge transistor 47 is supplied. The gate electrodes of the charge transistor 47 and the discharge transistor 50 are commonly connected to a node INV_S of the latch circuit SDL.

[0040] The sense transistor 41, the switch transistor 42, the discharge transistor 43, the clamp transistor 44, the charge transistor 46, the charge transistor 49, and the discharge transistor 50 are, for example, enhancement type NMOS transistors. The voltage-resistant transistor 45 is, for example, a depletion type NMOS transistor. The charge transistor 47 is, for example, a PMOS transistor.

[0041] Also, the gate electrode of the switch transistor 42 is connected to a signal line STB. The gate electrode of the discharge transistor 43 is connected to a signal line XXL. The gate electrode of the clamp transistor 44 is connected to a signal line BLC. The gate electrode of the voltage-resistant transistor 45 is connected to a signal line BLS. The gate electrode of the charge transistor 46 is connected to a signal line HLL. The gate electrode of the charge transistor 49 is connected to a signal line BLX. These signal lines STB, XXL, BLC, BLS, HLL, and BLX are connected to the sequencer SQC.

[0042] The latch circuit SDL includes nodes LAT_S and INV_S, an inverter 51 having an output terminal connected to the node LAT_S and an input terminal connected to the node INV_S, an inverter 52 having an input terminal connected to the node LAT_S and an output terminal connected to the node INV_S, a switch transistor 53 connected to the node LAT_S and a wiring LBUS, and a switch transistor 54 connected to the node INV_S and a wiring LBUS. The switch transistors 53 and 54 are, for example, NMOS transistors. The gate electrode of the switch transistor 53 is connected to the sequencer SQC via a signal line STL. The gate electrode of the switch transistor 54 is connected to the sequencer SQC via a signal line STI.

[0043] The latch circuits ADL, BDL, CDL, and TDL are configured almost the same as the latch circuit SDL. However, as described above, the node INV_S of the latch circuit SDL is electrically connected to the gate electrodes of the charge transistor 47 and the discharge transistor 50 in the sense amplifier SA. The latch circuits ADL, BDL, CDL, and TDL differ from the latch circuit SDL in this respect.

[0044] The switch transistor DSW is, for example, an NMOS transistor. The switch transistor DSW is connected between the wiring LBUS and the wiring DBUS. The gate electrode of the switch transistor DSW is connected to the sequencer SQC via the signal line DBS (FIG. 6).

[0045] As shown in FIG. 6, the above-mentioned signal lines STB, HLL, XXL, BLX, BLC, and BLS are commonly connected among all the sense amplifier units SAU included in the sense amplifier module SAM. DD The voltage supply line and voltage V SRC The voltage supply lines to which the voltages are supplied are connected in common to all the sense amplifier units SAU included in the sense amplifier module SAM. Also, the signal lines STI and STL of the latch circuit SDL are connected in common to all the sense amplifier units SAU included in the sense amplifier module SAM. Similarly, the signal lines ATI, BTI, CTI, TTI and signal lines ATL, BTL, CTL, TTL corresponding to the signal lines STI and STL in the latch circuits ADL, BDL, CDL, TDL are connected in common to all the sense amplifier units SAU included in the sense amplifier module SAM. Meanwhile, a plurality of the signal lines DBS are provided corresponding to all the sense amplifier units SAU included in the sense amplifier module SAM.

[0046] [Circuit configuration of cache memory CM] The cache memory CM (FIG. 4) includes a plurality of latch circuits XDL connected to the latch circuits ADL, BDL, CDL, and TDL in the sense amplifier module SAM via wiring DBUS. Data DAT included in the plurality of latch circuits XDL is sequentially transferred to the sense amplifier module SAM or the input / output control circuit I / O.

[0047] In addition, a decode circuit and a switch circuit (not shown) are connected to the cache memory CM. The decode circuit decodes a column address CA held in an address register ADR (FIG. 4). The switch circuit connects a latch circuit corresponding to the column address CA to a bus DB (FIG. 4) in response to an output signal from the decode circuit.

[0048] [Circuit configuration of sequencer SQC] The sequencer SQC (Figure 4) reads the command data D held in the command register CMR. CMD In accordance with the above, the sequencer SQC outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generating circuit VG. In addition, the sequencer SQC outputs status data D ST is output to the status register STR.

[0049] The sequencer SQC also generates a ready / busy signal and outputs it to the terminal RY / / BY. During the period when the terminal RY / / BY is in the “L” state (busy period), access to the memory die MD is basically prohibited. During the period when the terminal RY / / BY is in the “H” state (ready period), access to the memory die MD is permitted. The terminal RY / / BY is realized by, for example, the pad electrode P described with reference to FIGS. 2 and 3.

[0050] [Circuit configuration of input / output control circuit I / O] The input / output control circuit I / O includes data signal input / output terminals DQ0 to DQ7, clock signal input / output terminals DQS, / DQS, and an input circuit such as a comparator and an output circuit such as an OCD (Off Chip Driver) circuit connected to the data signal input / output terminals DQ0 to DQ7. The input / output circuit I / O also includes a shift register and a buffer circuit connected to the input and output circuits. The input circuit, output circuit, shift register, and buffer circuit are each driven by a power supply voltage V CCQ and ground voltage V SS The data signal input / output terminals DQ0 to DQ7, the clock signal input / output terminals DQS and / DQS, and the power supply voltage V CCQ The terminals to which the data are supplied are realized by, for example, the pad electrodes P described with reference to Figures 2 and 3. Data input via the data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR in response to an internal control signal from the logic circuit CTR. Data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit in response to an internal control signal from the logic circuit CTR.

[0051] [Circuit configuration of logic circuit CTR] The logic circuit CTR (FIG. 4) receives external control signals from the controller die CD via the external control terminals / CEn, CLE, ALE, / WE, RE, and / RE, and outputs internal control signals to the input / output control circuit I / O in response to the external control signals. Note that the external control terminals / CEn, CLE, ALE, / WE, RE, and / RE are realized by, for example, the pad electrodes P described with reference to FIGS. 2 and 3.

[0052] [Memory Die MD Structure] 8 is a schematic exploded perspective view showing a configuration example of the semiconductor memory device according to the first embodiment. As shown in FIG. 8, the memory die MD includes a chip C on the memory cell array MCA side. M and the peripheral circuit PC side chip C P And, it is equipped with.

[0053] Chip C M A plurality of pad electrodes P that can be connected to bonding wires B are provided on the upper surface of the chip C. M On the underside of I1 Also, chip C P On the upper surface of the I2 The following is Chip C M Regarding the multiple laminated electrodes P I1 The surface on which the pad electrodes P are provided is called the front surface, and the surface on which the pad electrodes P are provided is called the back surface. P Regarding the multiple laminated electrodes P I2 The surface on which the chip C is provided is called the front surface, and the surface opposite the front surface is called the back surface. P The surface of the chip C P The chip C is located above the back surface of the chip C. M The back side of the chip is C M The surface of the substrate is provided above the substrate.

[0054] Chip C M and Chip C P is Chip C M Surface and chip C P The surface of the laminated electrodes P I1 is a plurality of laminated electrodes P I2 , and a plurality of bonding electrodes P I2 The electrode is placed in a position where it can be attached to the I1 and the laminated electrode P I2 What is Chip C? M and Chip C P The laminate functions as a laminate electrode for bonding the two and electrically connecting them.

[0055] In the example of FIG. 8, chip C M The corners a1, a2, a3, and a4 of the chip C P As shown in FIG. 8, the corners b1, b2, b3, and b4 of the chip C PThe semiconductor device includes a semiconductor substrate 200. On the upper surface of the semiconductor substrate 200, transistors included in the peripheral circuit PC are formed.

[0056] FIG. 9 shows chip C M FIG. 9 is a schematic bottom view showing a configuration example of the laminated electrode P I1 Some of the configuration such as the above is omitted. Fig. 10 is a schematic perspective view showing a configuration of a portion of the memory cell array MCA. Fig. 11 is a schematic cross-sectional view showing a configuration of a portion of the memory cell array MCA.

[0057] [Chip C M Structure of In the example of FIG. 9, chip C M 9 includes four memory planes MPL0, MPL1, MPL2, and MPL3 aligned in the X direction. Each of the four memory planes MPL0 to MPL3 corresponds to a memory cell array MCA (FIG. 5). Each of the four memory planes MPL0 to MPL3 includes a plurality of memory blocks BLK aligned in the Y direction. In the example of FIG. 9, each of the plurality of memory blocks BLK includes hook-up regions R HU and a memory hole region R MH Also, the chip C M The peripheral region R is provided on one end side in the Y direction from the four memory planes MPL0 to MPL3. P Equipped with.

[0058] In the illustrated example, the hook-up region R HU is the memory cell array region R MCA However, this configuration is merely an example, and the specific configuration can be adjusted as appropriate. For example, the hook-up region R HU is the memory cell array region R MCA The hook-up region R may be provided at one end in the X direction, not at both ends in the X direction. HU is the memory cell array region R MCA Alternatively, the light source 10 may be provided at the center or near the center in the X direction.

[0059] 10, a plurality of memory blocks BLK in the memory cell array MCA are aligned in the Y direction. A plurality of string units SU in the memory block BLK are aligned in the Y direction. An inter-block insulating layer ST such as silicon oxide (SiO2) is provided between two adjacent memory blocks BLK in the Y direction. An inter-string unit insulating layer SHE such as silicon oxide (SiO2) is provided between two adjacent string units SU in the Y direction.

[0060] The memory block BLK includes a plurality of conductive layers 110 aligned in the Z direction, and a plurality of semiconductor layers 120 extending in the Z direction. In addition, as shown in FIG. 11, a gate insulating film 130 is provided between each of the conductive layers 110 and the semiconductor layers 120.

[0061] 10, the conductive layer 110 has a generally plate-like shape extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 110 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged in the Z direction.

[0062] Some of the conductive layers 110 function as word lines WL (FIG. 5) and gate electrodes of memory cells MC (FIG. 5) connected thereto. In the following description, such conductive layers 110 may be referred to as conductive layers 110(WL). Each of the conductive layers 110(WL) is electrically independent for each memory block BLK.

[0063] One or more conductive layers 110 located above the multiple conductive layers 110(WL) function as the gate electrodes of the source side select gate line SGS (FIG. 5) and the multiple source side select transistors STS (FIG. 5) connected thereto. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110(SGS). The one or more conductive layers 110(SGS) are electrically independent for each memory block BLK.

[0064] One or more conductive layers 110 located below the multiple conductive layers 110(WL) function as gate electrodes of a drain side select gate line SGD (FIG. 5) and multiple drain side select transistors STD (FIG. 5) connected thereto. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110(SGD). The width in the Y direction of these multiple conductive layers 110(SGD) is smaller than the width in the Y direction of the conductive layer 110(WL). In addition, an inter-string unit insulating layer SHE is provided between two conductive layers 110(SGD) adjacent to each other in the Y direction in one memory block BLK. Each of these multiple conductive layers 110(SGD) is electrically independent for each string unit SU.

[0065] A conductive layer 100 is provided above the multiple conductive layers 110. The conductive layer 100 is connected to the upper end of the semiconductor layer 120. The semiconductor layer 120 may include, for example, polycrystalline silicon containing N-type impurities such as phosphorus (P), or may include a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers. In addition, an insulating layer 101 such as silicon oxide (SiO2) is provided between the conductive layer 100 and the conductive layer 110.

[0066] The conductive layer 100 functions as a source line SL (FIG. 5). The source line SL is provided in common to all the memory blocks BLK included in the memory cell array MCA, for example.

[0067] The semiconductor layers 120 are arranged in a predetermined pattern in the X-direction and the Y-direction. The semiconductor layers 120 function as channel regions of a plurality of memory cells MC and select transistors (STD, STS) included in one memory string MS (FIG. 5). The semiconductor layers 120 include, for example, polycrystalline silicon (Si) or the like. The semiconductor layers 120 have a substantially bottomed cylindrical shape, and an insulating layer 125 of silicon oxide or the like is provided in the central portion, as shown in FIG. 11 for example. The outer peripheral surfaces of the semiconductor layers 120 are surrounded by the conductive layers 110 and face the conductive layers 110.

[0068] An impurity region (not shown) containing N-type impurities such as phosphorus (P) is provided at the lower end of the semiconductor layer 120. This impurity region is connected to the bit line BL through a via contact electrode.

[0069] An impurity region (not shown) containing N-type impurities such as phosphorus (P) is provided at the upper end of the semiconductor layer 120. This impurity region is connected to the conductive layer 100.

[0070] The gate insulating film 130 has a substantially cylindrical shape with a bottom covering the outer peripheral surface of the semiconductor layer 120. The gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 stacked between the semiconductor layer 120 and the conductive layer 110, as shown in FIG. 11, for example. The tunnel insulating film 131 and the block insulating film 133 include, for example, silicon oxide (SiO2) or the like. The charge storage film 132 includes, for example, a film capable of storing charge, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120 except for the contact portion between the semiconductor layer 120 and the conductive layer 110.

[0071] 11 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may include a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0072] [Threshold voltage of memory cell MC] Next, the threshold voltage of a memory cell MC that stores multiple bits of data will be described with reference to Fig. 12. Fig. 12 shows the threshold voltage of a memory cell MC that stores three bits of data as an example.

[0073] Fig. 12(a) is a schematic histogram for explaining the threshold voltage of a memory cell MC in which 3-bit data is recorded. The horizontal axis indicates the voltage of the word line WL, and the vertical axis indicates the number of memory cells MC. Fig. 12(b) is a table showing an example of the relationship between the threshold voltage of a memory cell MC in which 3-bit data is recorded and the data recorded therein.

[0074] In the example of FIG. 12(a), the threshold voltage of the memory cell MC is controlled to eight different states. The threshold voltage of the memory cell MC controlled to the Er state is equal to or lower than the erase verify voltage V VFYEr For example, the threshold voltage of the memory cell MC controlled to the A state is smaller than the verify voltage V VFYA Larger than the verify voltage V VFYB For example, the threshold voltage of the memory cell MC controlled to the B state is smaller than the verify voltage V VFYB Larger than the verify voltage V VFYC Similarly, the threshold voltages of the memory cells MC controlled to the C state to the F state are smaller than the verify voltage V VFYC ~Verify voltage V VFYF Larger than the verify voltage V VFYD ~Verify voltage V VFYG For example, the threshold voltage of the memory cell MC controlled to the G state is smaller than the verify voltage V VFYG Larger than the read pass voltage V READ Less than.

[0075] In the example of FIG. 12(a), a read voltage V CGARIn addition, a read voltage V CGBR Similarly, between the threshold distribution corresponding to the B state and the threshold distribution corresponding to the C state, and between the threshold distribution corresponding to the F state and the threshold distribution corresponding to the G state, read voltages V CGBR ~Read voltage V CGGR is set.

[0076] For example, the Er state corresponds to the lowest threshold voltage. A memory cell MC in the Er state is, for example, a memory cell MC in an erased state. For example, data "111" is assigned to a memory cell MC in the Er state.

[0077] The A state corresponds to a threshold voltage higher than the threshold voltage corresponding to the Er state. For example, data "110" is assigned to the memory cells MC in the A state.

[0078] Moreover, the B state corresponds to a threshold voltage higher than the threshold voltage corresponding to the above-mentioned A state. For example, data "100" is assigned to the memory cells MC in the B state.

[0079] Similarly, the C-state to G-state in the figure correspond to threshold voltages higher than the threshold voltages corresponding to the B-state to F-state. For example, data “000”, “010”, “011”, “001”, and “101” are assigned to the memory cells MC in these states.

[0080] In the case of the allocation illustrated in FIG. 12(b), the data of the lower bit (lower page: LP) is read at two read voltages V CGAR ,V CGER The data of the middle bit (Middle Page: MP) can be read at three read voltages V CGBR ,V CGDR ,V CGFRThe data of the upper bit (UP: Upper Page) can be distinguished by two read voltages V CGCR ,V CGGR This type of data assignment is sometimes called the 2-3-2 code.

[0081] The number of bits of data recorded in the memory cells MC, the number of states, and the allocation of data to each state can be changed as appropriate.

[0082] [Data stored in the latch circuit] FIG. 13 is a diagram showing data stored in the latch circuits XDL, ADL, BDL, CDL, TDL, and SDL. For example, as shown in FIG. 13, the latch circuit XDL stores data read by the sense amplifier module SAM and data transferred from the input / output control circuit I / O. The latch circuit ADL stores data of a lower page. The latch circuit BDL stores data of a middle page. The latch circuit CDL stores data of an upper page. The latch circuit TDL stores QPW data indicating whether or not to execute a program operation of a quick pass write (QPW) to be described later. The latch circuit SDL stores data for controlling the sense amplifier SA, as described above.

[0083] [Write operation] Next, the write operation of the semiconductor memory device according to this embodiment will be described with reference to FIGS.

[0084] FIG. 14 is a schematic flow chart for explaining the write operation according to the first embodiment. FIG. 15 is a schematic waveform diagram for explaining the write operation according to the first embodiment. FIG. 16 is a schematic cross-sectional view for explaining the program operation. Note that FIG. 16 shows the program operation of quick pass write. FIG. 17 is a schematic cross-sectional view for explaining the verify operation. FIG. 18 is a schematic waveform diagram for explaining the read operation of the adjacent memory cell MC. FIG. 19 is a schematic cross-sectional view for explaining the read operation of the adjacent memory cell MC. FIGS. 20 and 21 are diagrams showing the write operation when the loop count n is reached. W and the program voltage V PGM 22 is a diagram for explaining the relationship between the program operation and the verify operation of the first embodiment.

[0085] When a write operation is to be performed, a command set for executing the write operation is input from the controller die CD to the memory die MD. This command set includes command data D CMD , address data D specifying the page PG, memory block BLK, memory die MD, etc. that are the targets of the write operation ADD , and data DAT to be written to memory cells MC in the page PG. Accordingly, at timing t201, the terminal RY / / BY goes to the "L" state (FIG. 15).

[0086] In step S101 (FIG. 14), the initial program voltage V PGM0 (FIGS. 20 and 21) are set. The initial program voltage V PGM0 is the program voltage V in the program operation (step S103) PGM is the initial value of the voltage.

[0087] In step S102, the loop count n W Set to 1. Loop count n W is a variable that indicates the number of write loops. Loop count n WThe data is recorded in a register etc. In step 102, the data to be recorded in the selected memory cell MC in the write operation is latched in the latch circuits ADL to CDL.

[0088] In step S103, a program operation is performed. The program operation corresponds to timings t211 to t216 in FIG. 15. In this embodiment, the program operation includes a normal program operation and a quick pass write (QPW) program operation. The normal program operation may be called a first program operation. The quick pass write program operation may be called a second program operation.

[0089] Here, among the multiple selected memory cells MC, those for which the threshold voltage is adjusted may be referred to as "write memory cells MC". Among the multiple selected memory cells MC, those for which the threshold voltage is not adjusted may be referred to as "prohibited memory cells MC". Among the multiple write memory cells MC, those for which the threshold voltage has come close to a target value to a certain extent may be referred to as "weak write memory cells MC". Furthermore, memory cells adjacent to the write memory cells MC (including weak write memory cells MC) in the Z direction may be referred to as "adjacent memory cells MC". Furthermore, the selected word line WL S The word line WL adjacent to the word line WL in the Z direction may be called the "adjacent word line WL".

[0090] Basically, the quick pass write (QPW) program operation is performed on the weak write memory cell MC. Also, the normal program operation is performed on the write memory cell MC that is not the weak write memory cell MC. However, in this embodiment, even if it is a weak write memory cell MC, if it is determined in step 112 described later that the adjacent memory cell MC adjacent to the weak write memory cell MC in the Z direction is in the erase state (a state controlled to the Er state in FIG. 12), the normal program operation is performed.

[0091] At timing t211 of the program operation (FIG. 15), for example, the bit line BL connected to the write memory cell MC among the multiple selected memory cells MC W Voltage V SRC and supplies a bit line BL connected to a prohibited memory cell MC among the selected memory cells MC. P Voltage V DD For example, the bit line BL W The latch circuit SDL (Fig. 7) corresponding to the bit line BL P The latch circuit SDL (FIG. 7) corresponding to each of these latches latches "H." The states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, L, H, H, L, H."

[0092] At timing t212 of the program operation (FIG. 15), the write memory cell MC is selectively connected to the bit line BL W For example, the drain side select gate line SGD is connected to the voltage V SGD This supplies the voltage V SRC The bit line BL W The drain side select transistor STD corresponding to the voltage V DD The bit line BL P The drain side select transistor STD corresponding to the drain side select transistor STD is turned off.

[0093] At timing t212 of the program operation, the selected word line WL S and unselected word lines WL U Write pass voltage V PASS is supplied to turn all memory cells MC ON. PASS For example, the read pass voltage V READ Greater than.

[0094] In the period from timing t211 to timing t212, the quick pass write program operation and the normal program operation are both the same operation.

[0095] At timing t213 of the program operation, if it is determined in step S112 described below that the adjacent memory cell MC is not in the erased state and the memory cell MC to be written is a weakly written memory cell MC, a quick pass write (QPW) program operation is executed.

[0096] The program operation of the quick pass write is executed as follows. QPW , voltage V QPW For example, before timing t213, the gate voltage of the clamp transistor 44 in FIG. 7 is adjusted in advance. At this time, the bit line BL W The voltage V SRC is supplied, the bit line BL W The voltage on the bit line BL P is disconnected from the sense amplifier SA (FIG. 7) by the clamp transistor 44. Next, at timing t213, the bit line BL QPW The data latched in the latch circuit SDL (FIG. 7) corresponding to the weak write memory cell MC is switched from “L” to “H”. As a result, the voltage of the node COM (FIG. 7) of the sense amplifier SA corresponding to the weak write memory cell MC is changed to the voltage V SRC to voltage V DD The voltage of the corresponding bit line BL is clamped by the clamp transistor 44 to the voltage V SRC to voltage V QPW The voltage V QPW is the voltage V SRC Larger than the voltage V DD It is a smaller voltage.

[0097] On the other hand, if the memory cell MC to be written is not a weakly written memory cell MC at timing t213 of the program operation, and if it is determined in step S112 described below that the adjacent memory cell MC is in the erased state, a normal program operation is executed.

[0098] In a normal program operation, the bit line BL connected to the write memory cell MCW , and the bit line BL connected to the weak write memory cell MC QPW , voltage V SRC (i.e., voltage V SRC (keep as is).

[0099] At timing t214 of the program operation (FIG. 15), the selected word line WL S Program voltage V PGM Supply the program voltage V PGM is the write pass voltage V PASS Greater than.

[0100] Here, for example, as shown in FIG. 16, in a normal program operation, the bit line BL W The channel of the semiconductor layer 120 connected to SRC Such a semiconductor layer 120 and the selected word line WL S A relatively large electric field is generated between the charge storage film 132 (FIG. 11) and the tunnel insulating film 131 (FIG. 11). As a result, electrons in the channel of the semiconductor layer 120 tunnel into the charge storage film 132 (FIG. 11) through the tunnel insulating film 131 (FIG. 11). As a result, in a normal program operation, the threshold voltage of the write memory cell MC increases relatively significantly.

[0101] In addition, in the program operation of the quick pass write, the bit line BL QPW The channel of the semiconductor layer 120 connected to QPW Such a semiconductor layer 120 and the selected word line WL S An electric field smaller than the above electric field is generated between the charge storage film 132 and the tunnel insulating film 131. As a result, electrons in the channel of the semiconductor layer 120 tunnel into the charge storage film 132 (FIG. 11) through the tunnel insulating film 131 (FIG. 11). As a result, in the program operation of the quick pass write, the threshold voltage of the weak write memory cell MC increases by a relatively small amount.

[0102] In addition, in a normal program operation, the bit line BL QPW The channel of the semiconductor layer 120 connected to SRCSuch a semiconductor layer 120 and the selected word line WL S A relatively large electric field is generated between the charge storage film 132 (FIG. 11) and the weak write memory cell MC. As a result, electrons in the channel of the semiconductor layer 120 tunnel into the charge storage film 132 (FIG. 11) through the tunnel insulating film 131 (FIG. 11). As a result, in a normal program operation, the threshold voltage of the weak write memory cell MC increases relatively significantly.

[0103] Also, the bit line BL P The channel of the semiconductor layer 120 connected to the selected word line WL is in an electrically floating state, and the potential of this channel is U The write pass voltage V PASS The semiconductor layer 120 and the selected word line WL S Between the charge storage film 132 and the semiconductor layer 120, an electric field smaller than any of the electric fields described above is generated. Therefore, electrons in the channel of the semiconductor layer 120 do not tunnel into the charge storage film 132 (FIG. 11). Therefore, the threshold voltage of the inhibited memory cell MC does not increase.

[0104] At timing t215 of the program operation, the selected word line WL S and unselected word lines WL U Write pass voltage V PASS is supplied to turn all memory cells MC into the ON state.

[0105] At timing t216 of the program operation, the selected word line WL S , unselected word lines WL U and the select gate lines (SGD, SGS, SGSb) are connected to the ground voltage V SS supplies.

[0106] In the period from timing t215 to timing t216, the quick pass write program operation and the normal program operation are both the same operation.

[0107] In steps S104 to S108 (FIG. 14), a verify operation is performed.

[0108] At timing t221 of the verify operation, for example, as shown in FIG. S and unselected word lines WL U The read pass voltage V READ In addition, a voltage V SG Supply voltage V to turn on the selection transistors (STD, STS, STSb). SG For example, the voltage V SGD Greater than.

[0109] In step S104 (FIG. 14), the selected word line WL S This sets the initial level of the verify voltage supplied to the

[0110] For example, at timing t222 of the verify operation, the selected word line WL S Then, the initial level of the verify voltage (V VFYA 17, some of the selected memory cells MC are turned on and the remaining selected memory cells MC are turned off.

[0111] Next, in step S105 (FIG. 14), the verify voltage level V VFYA Then, in step S106 (FIG. 14), the verify voltage level V VFYA For the 1000V, verify is performed at the normal sense level VH. In this way, one level of verify voltage V VFYA For this, verification is performed twice, once at a sense level VL slightly lower than the normal sense level VH and once at the normal sense level VH.

[0112] For example, at timing t222, charging of the bit line BL is performed. At this time, for example, based on the data in the latch circuits ADL to CDL, the bit line BL (in the example of FIG. 15, the bit line BL A ) to voltage V BL +V SL and the other bit lines BL are supplied with voltage V SRC (Figure 17)

[0113] During the verify operation from timing t223 to timing t224 (FIG. 15), the verify voltage level V VFYA For example, as shown in FIG. 15, the sense amplifier module SAM (FIG. 6) senses the bit line BL A The ON / OFF state of the memory cell MC connected to the latch circuits ADL to CDL is detected, and data indicating the state of the memory cell MC is obtained. At this time, data indicating the ON / OFF state of the memory cell MC and the like are latched in the latch circuits ADL to CDL.

[0114] During the verify operation from timing t225 to timing t226 (FIG. 15), the verify voltage level V VFYA For example, as shown in FIG. 15, the sense amplifier module SAM (FIG. 6) detects the bit line BL A The ON / OFF state of the memory cell MC connected to the latch circuits ADL to CDL is detected, and data indicating the state of the memory cell MC is obtained. At this time, data indicating the ON / OFF state of the memory cell MC and the like are latched in the latch circuits ADL to CDL.

[0115] Note that the time t1 between timing t223 and timing t224 is shorter than the time t2 between timing t225 and timing t226. Therefore, the charge discharged from the sense node SEN (FIG. 7) between timing t223 and timing t224 is less than the charge discharged from the sense node SEN (FIG. 7) between timing t225 and timing t226. In this way, in the two verify operations, the selected word line WL S The level of the verify voltage supplied to VFYA However, because the sense times for the two verify operations are different, the verify voltage level V VFYA In response to the sense level VL, which is slightly lower than the normal sense level VH, and then the normal sense level VH are verified.

[0116] For example, memory cells MC determined to be in the OFF state in the data detected between timing t225 and timing t226 (data detected in the second verify) are likely to have a threshold voltage that has reached the target value. At least some of such memory cells MC are set as inhibited memory cells MC in the next and subsequent write loops.

[0117] Also, for example, memory cells MC that are determined to be in the ON state in the data detected between timing t225 and timing t226 (data detected in the second verify) and are determined to be in the OFF state in the data detected between timing t223 and timing t224 (data detected in the first verify) are likely to have threshold voltages approaching the target value to some extent. At least some of such memory cells MC are set as weakly written memory cells MC in the next write loop. In this case, as described above, if the adjacent memory cells MC adjacent to the weakly written memory cells MC are not in the erased state, a quick pass write program operation is executed. On the other hand, if the adjacent memory cells MC adjacent to the weakly written memory cells MC are in the erased state, a normal program operation is executed.

[0118] Also, for example, memory cells MC determined to be in the ON state in the data detected between timing t223 and timing t224 are likely to have threshold voltages that are somewhat different from the target value. At least some of such memory cells MC are set as write memory cells MC in the next write loop.

[0119] As described above with reference to FIG. 13, the latch circuit TDL latches QPW data indicating whether or not to execute a program operation of the quick pass write (QPW). For example, the bit line BL P The QPW data "1" is set in the latch circuit TDL corresponding to the bit line BL connected to the weak write memory cell MC. QPW The QPW data "1" is set in the latch circuit TDL corresponding to the bit line BL connected to the write memory cell MC that is not the weak write memory cell MC. W In the latch circuit TDL corresponding to this, the QPW data "0" is set.

[0120] Based on the data indicating the ON / OFF state of the memory cell MC latched in the latch circuits ADL to CDL and the QPW data latched in the latch circuit TDL, it is determined whether or not a quick pass write program operation is executed in the program operation of the next write loop (step S103).

[0121] In step S107 (FIG. 14), it is determined whether the verify voltage is at the final level. If the verify voltage is not at the final level (NO in step S107), the next level of the verify voltage is set in step .

[0122] For example, at timing t227 of the verify operation, the verify voltage is not the final level (NO in step S207), so the next level V VFYBis supplied (step S208). During the verify operation from timing t227 to timing t231, the same process as that from timing t222 to timing t226 is performed for memory cells MC in other states (B state in the example of FIG. 15). In FIG. 15, the bit line BL connected to the memory cell MC corresponding to the B state is referred to as the bit line BL B It states:

[0123] Also, for example, at timing t232 of the verify operation, the verify voltage is not the final level (NO in step S207), so the next level V VFYC is supplied (step S208). During the verify operation from timing t232 to timing t236, the same process as that from timing t222 to timing t226 is performed for memory cells MC in other states (C state in the example of FIG. 15). In FIG. 15, the bit line BL connected to the memory cell MC corresponding to the C state is referred to as the bit line BL C It states:

[0124] Also, for example, at timing t237 of the verify operation, the verify voltage is at the final level (YES in step S207), so that the selected word line WL S and unselected word lines WL U The read pass voltage V READ In addition, a voltage V SG is supplied to turn on the selection transistors (STD, STS, STSb).

[0125] At timing t238 of the verify operation, the selected word line WL S , unselected word lines WL U and the select gate lines (SGD, SGS, SGSb) are connected to the ground voltage V SS supplies.

[0126] Then, the data latched in the latch circuit SDL is transferred to a counter circuit not shown in the figure, and the number of memory cells MC whose threshold voltage has reached the target value or the number of memory cells MC whose threshold voltage has not reached the target value is counted.

[0127] In the example of FIG. 15, the selected word line WL S There are three verify voltage levels V VFY (V VFYA ,V VFYB ,V VFYC ) is supplied to the selected word line WL S The level of the verify voltage supplied to VFY The number of loops can be two or less, four or more, and W The thickness may vary depending on the

[0128] In step S109 (FIG. 14), the result of the verify operation is judged. For example, by referring to the counter circuit, if the number of memory cells MC whose threshold voltage has not reached the target value is equal to or greater than a certain number, the verify operation is judged as FAIL, and the process proceeds to step S110. On the other hand, if the number of memory cells MC whose threshold voltage has not reached the target value is equal to or less than a certain number, the verify operation is judged as PASS, and the process proceeds to step S115.

[0129] In step S110, the loop count n W A given number of times N W If it has not been reached, the process proceeds to step S111. If it has been reached, the process proceeds to step S116.

[0130] In step S111, the loop count n W Then, the process proceeds to step S112. In step S112, the data read operation of the adjacent memory cell MC is executed.

[0131] This read operation is an operation for identifying whether the data of the selected memory cells MC is in the erased state by reading data of the selected memory cells MC corresponding to the selected page PG. S0 indicates the selected word line WL connected to the selected page PG in FIG. 16 and FIG. 17. S and the adjacent word line WL (adjacent word line WL) on the negative side in the Z direction. The read operation starts, for example, at timing t11 in FIG.

[0132] In a read operation, for example, as shown in FIG. 19, a voltage V DD Also, a voltage V SRC supplies.

[0133] In the read operation, for example, as shown in FIGS. 18 and 19, in the period from timing t12 to timing t16, a voltage V SG An electron channel is formed in the channel region of the drain side select transistor STD, and a voltage V DD will be transferred.

[0134] In the read operation, for example, as shown in FIG. 19, a voltage V SG An electron channel is formed in the channel region of the source side select transistors STS and STSb, and a voltage V SRC will be transferred.

[0135] In addition, in a read operation, for example, as shown in FIGS. 18 and 19, in the period from timing t12 to timing t16, the unselected word line WL U The read pass voltage V READ The read pass voltage V READ is the voltage V DD ,V SRC Also, the read pass voltage VREAD and voltage V DD ,V SRC The voltage difference between the selected memory cell MC and the unselected memory cell MC is greater than the threshold voltage when the memory cell MC functions as an NMOS transistor, regardless of the data stored in the memory cell MC. Therefore, an electron channel is formed in the channel region of the unselected memory cell MC, and a voltage V DD ,V SRC will be transferred.

[0136] In the read operation, for example, as shown in FIG. 18 and FIG. 19, in the period from timing t13 to timing t16, the selected word line WL S0 Read voltage V CGR Supply the read voltage V CGR is the read pass voltage V READ In this embodiment, as shown in FIGS. 18 and 19, the read voltage V CGR The read voltage V corresponding to the A state CGAR The read voltage V CGAR and voltage V SRC The voltage difference between the read voltage V and the bit line BL is greater than the threshold voltage of the memory cell MC in the Er state. Therefore, the memory cell MC in the Er state is in the ON state. Therefore, a current flows through the bit line BL connected to such a memory cell MC. On the other hand, the read voltage V CGAR and voltage V SRC The voltage difference between the bit line BL and the threshold voltage of the memory cells MC in the A state to the G state is smaller than the threshold voltage of the memory cells MC in the A state to the G state. Therefore, the memory cells MC in the A state to the G state are turned off. Therefore, no current flows through the bit line BL connected to such memory cells MC.

[0137] In a read operation, the sense amplifier module SAM (FIG. 6) detects whether or not a current flows through the bit line BL, thereby detecting the ON / OFF state of the memory cell MC.

[0138] In the example of FIG. 18, the sense amplifier SA performs a sensing operation on the bit line BL in the period from timing t14 to timing t15.

[0139] For example, when a selected memory cell MC (adjacent memory cell MC) corresponding to one bit line BL is in an ON state, a selected word line WL S0 This indicates that the adjacent word line WL is in the erased state (controlled to the Er state). In this case, data of, for example, “1” is stored in the latch circuit SDL corresponding to that bit line BL.

[0140] Also, for example, when a selected memory cell MC (adjacent memory cell MC) corresponding to one bit line BL is in the OFF state, the selected word line WL S0 This indicates that the adjacent word line WL is not in the erased state (controlled to the Er state). In this case, for example, data "0" is stored in the latch circuit SDL corresponding to that bit line BL.

[0141] In step S113 (FIG. 14), if the adjacent memory cell MC is in an erased state (the data stored in the latch circuit SDL is "1") and the data stored in the latch circuit TDL is "1", the data stored in the latch circuit TDL is corrected from "1" to "0". In this way, the data stored in the latch circuit TDL is corrected from "1" to "0", and thus, in the program operation of the next write loop (step S103), a normal program operation is executed on the weak-write memory cell MC. Note that if the adjacent memory cell MC is not in an erased state (the data stored in the latch circuit SDL is "0") or if the data stored in the latch circuit TDL is "0", the data stored in the latch circuit TDL is not corrected.

[0142] In step S114, for example, the program voltage V PGM A certain offset voltage ΔV is added to the program voltage V PGM is the loop count n W After that, the process proceeds to step S103.

[0143] 20 shows an example in which the program operation in the write loop is executed six times when the adjacent memory cell MC is not in the erased state. W In the program operation in (=1), the selected word line WL S to the initial program voltage V PGM0 Also, the second write loop (loop count n W In the program operation at =2), the initial program voltage V PGM0 + offset voltage ΔV1 (V PGM0 +ΔV1) to the program voltage V PGM Select word line WL as S Here, the offset voltage ΔV1 is an offset voltage that is added when a normal program operation is performed.

[0144] The third write loop (loop count n W In the program operation at (=3), the program voltage (V PGM0 +ΔV1) plus the offset voltage ΔV1 (V PGM0 +2ΔV1) to the program voltage V PGM Select word line WL as S 22(1), most of the threshold voltage distribution of the memory cells MC to be programmed exceeds the level VL of the verify voltage. In this case, the threshold voltage of the memory cells MC to be programmed approaches the target value (sense level VH) to some extent.

[0145] The fourth write loop (loop count n W In the program operation at (=4), the program voltage (V PGM0 +2ΔV1) plus the offset voltage ΔV2 (V PGM0 +2ΔV1+ΔV2) is the program voltage V PGM Select word line WL as SHere, the offset voltage ΔV2 is an offset voltage that is added when the quick pass write program operation is executed. As described above, in a normal program operation, the threshold voltage of the memory cell MC to be written increases relatively greatly, whereas in a quick pass write program operation, the threshold voltage of the memory cell MC to be written increases relatively slightly. Therefore, the offset voltage ΔV2 is smaller than the offset voltage ΔV1. In this way, in the quick pass write program operation, data is written with a smaller width than in the normal program operation.

[0146] The fifth and sixth write loops (loop count n W In the program operation at voltages (V PGM0 +2ΔV1+2ΔV2), voltage (V PGM0 +2ΔV1+3ΔV2) is the program voltage V PGM Select word line WL as S 22(1), most of the threshold distribution of the memory cells MC to be written (memory cells MC to be weakly written) exceeds the sense level VH. In this case, the result of the verify operation (step S109) is determined as verify PASS.

[0147] FIG. 21 shows an example in which the program operation in the write loop is executed five times when the adjacent memory cell MC is in the erased state. WThe program operation in the cases where the write operation is performed at the write operation time points S113 (=1 to 3) is the same as that described with reference to FIG. 20. As shown in FIG. 22(2), most of the threshold distribution of the memory cells MC to be written exceeds the level VL of the verify voltage. In this case, the threshold voltage of the memory cells MC to be written approaches the target value (sense level VH) to a certain extent. Therefore, in the program operation of the next and subsequent write loops, the quick pass write program operation is normally executed. However, as described above, when the adjacent memory cell MC is in the erased state (when the data in the latch circuit TDL is corrected from "1" to "0" in step S113 of FIG. 14), the quick pass write program operation is not executed, and the normal program operation is executed.

[0148] Therefore, the fourth write loop (loop count n W In the program operation at (=4), the program voltage (V PGM0 +2ΔV1) plus the offset voltage ΔV1 (V PGM0 +3ΔV1) to the program voltage V PGM Select word line WL as S Supply to.

[0149] 5th write loop (loop count n W In the program operation at voltage (V PGM0 +4ΔV1) to the program voltage V PGM Select word line WL as S 22(2), most of the threshold voltage distribution of the memory cells MC to be written exceeds the sense level VH. In this case, the result of the verify operation (step S109) is determined as verify PASS.

[0150] The threshold distribution of the memory cells MC to be written in Fig. 22(2) is written with a larger width than the threshold distribution of the memory cells MC to be written in Fig. 22(1). Therefore, the threshold distribution of the memory cells MC to be written in Fig. 22(2) has a higher threshold voltage than the threshold distribution of the memory cells MC to be written in Fig. 22(1).

[0151] [Write operation execution order] Fig. 23 is a schematic cross-sectional view for explaining the execution order of the write operation in the first embodiment. Fig. 23 illustrates two memory blocks BLK. In addition, in the example of Fig. 23, the memory block BLK includes five word lines WL and five string units SUa to SUe. Therefore, in the example of Fig. 23, the memory block BLK includes 25 page parts PGP. The page part PGP includes a plurality of pages PG.

[0152] Fig. 23 also illustrates an example of the order in which the write operation is performed. In the example of Fig. 23, first, the write operation is performed in order on five page parts PGP corresponding to the first word line WL counting from the bottom. Next, the write operation is performed in order on five page parts PGP corresponding to the second word line WL counting from the bottom. Similarly, the write operation is performed in order on 15 page parts PGP corresponding to the third to fifth word lines WL counting from the bottom.

[0153] [effect] 23, when the adjacent memory cells MC adjacent to the memory cells MC corresponding to the second word line WL counting from the bottom are in the erased state, the threshold voltage of one of the memory cells MC corresponding to the second word line WL counting from the bottom may be downshifted. For example, when two conductive layers 110 (word lines WLn-1, WLn) are arranged in the Z direction as shown in FIG. 24, the program voltage V PGMThis is believed to be due to the fact that the supply of electrons causes electrons to move to the vicinity of the conductive layer 110 (word line WLn-1) provided below.

[0154] However, in the write operation according to the first embodiment, when the adjacent memory cell MC (word line WLn-1 in FIG. 24) adjacent to the memory cell MC to be written is in the erased state, the quick pass write program operation is not executed, and a normal program operation is executed. As a result, as described with reference to FIG. 22, the threshold distribution of the memory cell MC to be written in FIG. 22(2) has a higher threshold voltage than the threshold distribution of the memory cell MC to be written in FIG. 22(1). In this case, as shown in FIG. 25, even if a downshift of the threshold distribution of the memory cell MC to be written occurs, it is possible to prevent the threshold distribution from deviating significantly from the normal threshold distribution position.

[0155] 14, in the write operation according to the first embodiment, the process of reading data from the adjacent memory cell MC (step S112) and correcting the QPW data of the latch circuit TDL (step S113) is added. However, as described with reference to FIG. 21, the number of write loops may be smaller when a normal program operation is performed than when a quick pass write program operation is performed. Therefore, it is possible to suppress an increase in the execution time of the write operation.

[0156] [Second embodiment] Next, a semiconductor memory device according to a second embodiment will be described with reference to FIGS.

[0157] Fig. 26 is a schematic flow chart for explaining a write operation according to the second embodiment. Fig. 27 is a schematic circuit diagram showing a configuration of a sense amplifier unit SAU according to the second embodiment. Fig. 28 is a diagram for explaining a program operation and a verify operation according to the second embodiment.

[0158] In step S100 (FIG. 26), a data read operation of the adjacent memory cell MC is performed. Step S100 is the same process as step S112 in FIG. 14. The data indicating whether the adjacent memory cell MC is in an erased state or not obtained in step S100 is stored in a latch circuit DDL shown in FIG.

[0159] Moreover, steps S101 to S106 are similar to the processes described with reference to Fig. 14. Therefore, the description of these processes will be omitted.

[0160] In step S106A (FIG. 26), verify is executed at a sense level VH' that is slightly higher than the normal sense level VH.

[0161] In the write operation according to the second embodiment, when the adjacent memory cell MC adjacent to the write memory cell MC is in a state other than the erased state, one level of the verify voltage (for example, V VFYA ), two verify operations are performed, one at a sense level VL slightly lower than the normal sense level VH and the other at the normal sense level VH. That is, the processes of steps S105 and S106 are performed. On the other hand, when the adjacent memory cell MC adjacent to the write memory cell MC is in the erase state, one level of the verify voltage (for example, V VFYA ) is verified three times at a sense level VL slightly lower than the normal sense level VH, the normal sense level VH, and a sense level VH' slightly higher than the normal sense level VH. That is, the processes of steps S105, S106, and S106A are executed.

[0162] For example, as shown in Fig. 28(1), when the adjacent memory cell MC adjacent to the memory cell MC to be written is in a state other than the erased state, the program operation and verify operation in the write loop are repeatedly executed until most of the threshold distribution of the memory cell MC to be written (weakly written memory cell MC) exceeds the sense level VH. On the other hand, when the adjacent memory cell MC adjacent to the memory cell MC to be written is in the erased state, as shown in Fig. 28(2), for example, the program operation and verify operation in the write loop are repeatedly executed until most of the threshold distribution of the memory cell MC to be written (weakly written memory cell MC) exceeds the sense level VH'.

[0163] The threshold voltage distribution of the memory cells MC to be written in FIG. 28(2) is higher than the threshold voltage distribution of the memory cells MC to be written in FIG. 28(1).

[0164] In the three verify operations, the selected word line WL S The level of the verify voltage supplied to each of the three verify operations is the same. However, because the sense times in the three verify operations are different, verify operations at a sense level VL slightly lower than the normal sense level, verify operations at the normal sense level VH, and verify operations at a sense level VH' slightly higher than the normal sense level are performed in a pseudo manner.

[0165] Incidentally, the processes in steps S107 to S111 and S114 to S116 in Fig. 26 are similar to the processes described with reference to Fig. 14. Therefore, the description of these processes will be omitted.

[0166] According to this configuration, even if a downshift occurs in the threshold distribution of the memory cells MC to be written, it is possible to prevent the threshold distribution from deviating significantly from the normal position.

[0167] As described with reference to FIG. 28, the program operation and verify operation in the write loop are repeatedly executed until most of the threshold distribution of the memory cells MC to be written exceeds the sense level VH', so the number of write loops increases. However, in the write operation, the read operation (step S100) of the data of the adjacent memory cells MC is executed only once. Also, one sense level is simply added to each state, and the selected word line WL S Therefore, there is no need to perform switching such as the above, and an increase in the execution time of the write operation is suppressed.

[0168] [Third embodiment] Next, a semiconductor memory device according to a third embodiment will be described with reference to FIG.

[0169] Fig. 29 is a schematic cross-sectional view for explaining the execution order of the write operation in the third embodiment. In the execution order of the write operation shown in Fig. 29, the write operation is executed in order on five page parts PGP corresponding to the first word line WL counting from the top, and then the write operation is executed in order on 20 page parts PGP corresponding to the second to fifth word lines WL counting from the top.

[0170] In this way, the execution order of the write operation described with reference to Fig. 29 is upside down compared to the execution order of the write operation described with reference to Fig. 23. In this case, the adjacent memory cell MC is the memory cell MC adjacent to the memory cell MC to be written on the positive side in the Z direction. Other than the above configuration in Fig. 29, the configuration is the same as that in Fig. 23, so duplicated explanations will be omitted.

[0171] In this configuration, as in the first embodiment, even if a downshift of the threshold distribution of the memory cells MC to be written occurs, it is possible to prevent the threshold distribution from deviating significantly from the normal position, and also to prevent an increase in the execution time of the write operation.

[0172] [Fourth embodiment] Next, a semiconductor memory device according to a fourth embodiment will be described with reference to FIGS.

[0173] 30 is a schematic cross-sectional view for explaining the execution order of the write operation in the fourth embodiment. The write operation in the fourth embodiment executes a two-stage write operation of foggy write and fine write.

[0174] In the example of FIG. 30, first, the foggy write operation is executed in order on five page parts PGP corresponding to the first word line WL counting from the bottom. Next, the foggy write operation is executed on the page part PGP corresponding to the second word line WL and string unit SUa counting from the bottom. Next, the fine write operation is executed on the page part PGP corresponding to the first word line WL and string unit SUa counting from the bottom. Next, the foggy write operation is executed on the page part PGP corresponding to the second word line WL and string unit SUb counting from the bottom. Next, the fine write operation is executed on the page part PGP corresponding to the first word line WL and string unit SUb counting from the bottom. Similarly, the foggy write operation on the page part PGP corresponding to the second word line WL counting from the bottom and the fine write operation on the page part PGP corresponding to the first word line WL counting from the bottom are executed alternately.

[0175] Similarly, a foggy write operation to the page part PGP corresponding to the third to fifth word lines WL counting from the bottom and a fine write operation to the page part PGP corresponding to the second to fourth word lines WL counting from the bottom are executed alternately.

[0176] Next, the fine write operation is executed in sequence on the five page parts PGP corresponding to the fifth word line WL counting from the bottom.

[0177] 30, when the adjacent memory cells MC adjacent to one of the memory cells MC corresponding to the second word line WL counting from the bottom are in the erased state, the threshold voltage of one of the memory cells MC corresponding to the second word line WL counting from the bottom may be downshifted. This is because, for example, assuming three conductive layers 110 (word lines WLn-1, WLn, WLn+1) aligned in the Z direction as shown in FIG. 31, the program voltage V PGM This is believed to be due to the fact that the supply of electrons causes electrons to move to the vicinity of the conductive layer 110 (word line WLn-1) and the conductive layer 110 (word line WLn+1).

[0178] However, in the write operation according to the fourth embodiment, when the adjacent memory cell MC adjacent to the write memory cell MC (at least one of the word lines WLn-1 and WLn+1 in FIG. 31) is in the erased state, the quick pass write program operation is not executed, and the normal program operation is executed. As a result, as described with reference to FIG. 22 and FIG. 28, the threshold distribution of the write memory cell MC in FIG. 22(2) and FIG. 28(2) has a higher threshold voltage than the threshold distribution of the write memory cell MC in FIG. 22(1) and FIG. 28(1). In this case, even if a downshift of the threshold distribution of the write memory cell MC occurs as shown in FIG. 25, it is possible to prevent the threshold distribution from being significantly deviated from the normal threshold distribution position.

[0179] [Other embodiments] The semiconductor memory devices according to the first to fourth embodiments have been described above. However, these configurations are merely examples, and the specific configurations, methods, etc. can be appropriately adjusted.

[0180] For example, in the write operation according to the first embodiment, a read operation (step S112) of data from an adjacent memory cell MC is executed during a write loop (FIG. 14). However, like the write operation according to the second embodiment, a read operation (step S100 in FIG. 26) of data from an adjacent memory cell MC may be executed outside a write loop. In this case, a latch circuit DDL is provided similarly to the sense amplifier unit SAU in FIG. 27, and data indicating whether or not the adjacent memory cell MC is in an erased state, which is obtained during a read operation, is stored in the latch circuit DDL.

[0181] Also, for example, in the write operation according to the second embodiment, the data read operation (step S100) of the adjacent memory cell MC is executed outside the write loop (FIG. 26). However, like the write operation according to the first embodiment, the data read operation (see step S112 in FIG. 14) of the adjacent memory cell MC may be executed during the write loop. In this case, the latch circuit DDL may not be provided in the sense amplifier unit SAU in FIG. 27.

[0182] In the write operation according to the first to fourth embodiments, when the adjacent memory cell MC is in an erased state, a normal program operation is executed on the memory cell MC to be written instead of the quick-pass write program operation. However, when the adjacent memory cell MC is in a low state (e.g., an Er state or an A state), a normal program operation may be executed on the memory cell MC to be written instead of the quick-pass write program operation.

[0183] In the semiconductor memory devices according to the first to fourth embodiments, the chip C on the memory cell array MCA side M and the peripheral circuit PC side chip C P The semiconductor layer 120 has a top end connected to the conductive layer 100. However, this configuration is merely an example. The method of the write operation and the like described above can be applied to semiconductor memory devices having other structures.

[0184] [others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0185] MC... memory cell, MCA... memory cell array, BL... bit line, WL... word line, 132... charge storage film.

Claims

1. A substrate; a plurality of conductive layers aligned in a first direction intersecting a surface of the substrate; a first semiconductor layer extending in the first direction and facing the plurality of conductive layers; a charge storage layer provided between the plurality of conductive layers and the first semiconductor layer; a bit line electrically connected to one end of the first semiconductor layer in the first direction; a control circuit electrically connected to the plurality of conductive layers and the bit lines; Equipped with the plurality of conductive layers include a first conductive layer and a second conductive layer adjacent to the first conductive layer in the first direction; The control circuit is configured to be able to perform a write operation; the write operation includes a plurality of write loops; Each of the plurality of write loops includes: a first program operation of supplying a program voltage to the first conductive layer, supplying a write pass voltage lower than the program voltage to the second conductive layer, and supplying a first bit line voltage to the bit line; a second program operation of supplying the program voltage to the first conductive layer, supplying the write pass voltage to the second conductive layer, and supplying a second bit line voltage to the bit line, the second bit line voltage being greater than the first bit line voltage; The program voltage is increased by an offset voltage with an increase in the number of executions of the write loop; the write operation includes a state determination operation of determining whether or not the second conductive layer is controlled to a low state; When the second conductive layer is controlled to be in the low state, the first program operation is performed; When the second conductive layer is not controlled to the low state, the second program operation is performed. Semiconductor memory device.

2. The state determination operation determines whether or not the second conductive layer is controlled to be in an erased state.

2. The semiconductor memory device according to claim 1.

3. The state determination operation is included in the write loop.

2. The semiconductor memory device according to claim 1.

4. Each of the plurality of write loops includes: a verify operation of supplying a verify voltage to the first conductive layer and a read pass voltage to the second conductive layer that is smaller than the program voltage; The verify operation performs a verify operation at a first sense level which is lower than a normal sense level, and also performs a verify operation at a second sense level which is the normal sense level.

2. The semiconductor memory device according to claim 1.

5. When the result of the verify of the first sense level is verify PASS and the second conductive layer is controlled to the Low state, the first program operation is performed; When the result of the verify of the first sense level is verify PASS and the second conductive layer is not controlled to the Low state, the second program operation is performed.

2. The semiconductor memory device according to claim 1.

6. The second conductive layer is adjacent to the first conductive layer on at least one of the positive side and the negative side in the first direction.

2. The semiconductor memory device according to claim 1.

7. A substrate; a plurality of conductive layers aligned in a first direction intersecting a surface of the substrate; a first semiconductor layer extending in the first direction and facing the plurality of conductive layers; a charge storage layer provided between the plurality of conductive layers and the first semiconductor layer; a bit line electrically connected to one end of the first semiconductor layer in the first direction; a control circuit electrically connected to the plurality of conductive layers and the bit lines; Equipped with the plurality of conductive layers include a first conductive layer and a second conductive layer adjacent to the first conductive layer in the first direction; The control circuit is configured to be able to perform a write operation; the write operation includes a plurality of write loops; Each of the plurality of write loops includes: a first program operation of supplying a program voltage to the first conductive layer, supplying a write pass voltage lower than the program voltage to the second conductive layer, and supplying a first bit line voltage to the bit line; a second program operation of supplying the program voltage to the first conductive layer, supplying the write pass voltage to the second conductive layer, and supplying a second bit line voltage to the bit line, the second bit line voltage being greater than the first bit line voltage; a verify operation of supplying a verify voltage to the first conductive layer and a read pass voltage, which is smaller than the program voltage, to the second conductive layer; The program voltage is increased by an offset voltage with an increase in the number of executions of the write loop; the write operation includes a state determination operation of determining whether or not the second conductive layer is controlled to a low state; the verify operation includes performing a verify operation at a first sense level lower than a normal sense level, performing a verify operation at a second sense level which is the normal sense level, and performing a verify operation at a third sense level which is higher than the normal sense level; If the result of the verify of the first sense level is a verify FAIL, the first program operation is performed; when the result of the verify of the first sense level is verify PASS and the second conductive layer is not controlled to the Low state, performing the second program operation until the result of the verify of the second sense level is verify PASS; When the verify result of the first sense level is verify PASS and the second conductive layer is controlled to the Low state, the second program operation is performed until the verify result of the second sense level is verify PASS. Semiconductor memory device.

8. The state determination operation determines whether or not the second conductive layer is controlled to be in an erased state.

8. The semiconductor memory device according to claim 7.

9. The state determination operation is not included in the write loop.

8. The semiconductor memory device according to claim 7.

10. The second conductive layer is adjacent to the first conductive layer on at least one of the positive side and the negative side in the first direction.

8. The semiconductor memory device according to claim 7.

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