Multilayer ceramic capacitor and method of manufacturing the same

Abstract

To provide a multilayer ceramic capacitor with improved internal electrode connectivity by alleviating sintering mismatching between a dielectric layer and an internal electrode layer.SOLUTION: There are provided a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor includes a capacitor body including a dielectric layer and an internal electrode layer, and an external electrode disposed outside the capacitor body. The dielectric layer includes barium titanate-based main ingredient including barium (Ba) and titanium (Ti), and gallium (Ga). Peak intensity ratio of Ba / Ga (IBa / IGa), obtained by TEM-EDS analysis of an interface neighborhood region that is defined as a region from an interface between the dielectric layer and the internal electrode layer to a depth surface of 10 nm to 500 nm into the dielectric layer, is 1.0 to 5.0.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to a multilayer ceramic capacitor and a manufacturing method thereof. [Background technology]

[0002] Electronic components using ceramic materials include capacitors, inductors, piezoelectric elements, varistors, thermistors, etc. Among these ceramic electronic components, multilayer ceramic capacitors (MLCCs) have the advantages of being small, having high capacitance, and being easy to mount, and can be used in a variety of electronic devices.

[0003] For example, the multilayer ceramic capacitor can be used as a chip-type capacitor that is mounted on substrates of various electronic products such as imaging devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light-emitting diodes (OLEDs), computers, personal portable terminals, and smartphones, and serves to charge and discharge electricity.

[0004] Recently, with the trend of miniaturization and thinning of multilayer ceramic capacitors, the thickness of dielectrics and internal electrodes is reduced, which frequently causes short circuit defects. Summary of the Invention [Problem to be solved by the invention]

[0005] An embodiment provides a multilayer ceramic capacitor in which sintering mismatching between dielectric layers and internal electrode layers is alleviated, thereby improving connectivity of the internal electrodes.

[0006] Another embodiment provides a method for manufacturing the multilayer ceramic capacitor. [Means for solving the problem]

[0007] One embodiment includes a capacitor body including a dielectric layer and an internal electrode layer, and an external electrode disposed on the outside of the capacitor body, the dielectric layer including a barium titanate-based main component including barium (Ba) and titanium (Ti), and gallium (Ga), and a peak intensity ratio of Ba / Ga during a TEM-EDS analysis of a region near the interface, defined as a region from an interface between the dielectric layer and the internal electrode layer to a depth surface of 10 nm to 500 nm into the dielectric layer, is determined. Ba / I Ga ) is 1.0 to 5.0.

[0008] During TEM-EDS analysis of the region near the interface, the Ti / Ga peak intensity ratio (I Ti / I Ga ) may be 1.0 to 5.0.

[0009] The dielectric layer may further include a minor component, and the minor component may include aluminum (Al), silicon (Si), magnesium (Mg), V (vanadium), Mn (manganese), or a combination thereof.

[0010] The subcomponent may include aluminum (Al), and when a TEM-EDS analysis of the region near the interface is performed, the peak intensity ratio of Al / Ga (I Al / I Ga ) may be 1.0 to 5.0.

[0011] The subcomponent may include silicon (Si), and when a TEM-EDS analysis of the region near the interface is performed, the Si / Ga peak intensity ratio (I Si / I Ga ) may be 1.0 to 5.0.

[0012] The subcomponent may include magnesium (Mg), and when a TEM-EDS analysis of the region near the interface is performed, the peak intensity ratio of Mg / Ga (I Mg / I Ga) may be 0.4 to 2.0.

[0013] The gallium (Ga) can exist as a secondary phase in combination with the minor component.

[0014] The gallium (Ga) is contained in an amount of 0.01 to 10 parts by mol with respect to 100 parts by mol of the barium titanate-based main component.

[0015] The dielectric layer may include a plurality of grains and grain boundaries located between adjacent grains, and the gallium (Ga) may be present at the grain boundaries.

[0016] The molar ratio of gallium (Ga) present in the crystal grain boundaries to gallium (Ga) present in the crystal grains may be 5:1 to 50:1.

[0017] The gallium (Ga) is formed from a gallium (Ga) complex compound.

[0018] The capacitor body is formed by sintering at a temperature of 1000°C to 1200°C.

[0019] The capacitor body may have an active portion in which the dielectric layers and the internal electrode layers are alternately arranged, and a connectivity of the internal electrodes in the active portion, defined by the following Equation 1, may be greater than or equal to 80% and less than or equal to 100%.

[0020] [Formula 1] Connectivity of internal electrodes (%) = (total length of connected parts excluding discontinuous parts in multiple internal electrode layers / total length of multiple internal electrode layers) x 100

[0021] The capacitor body further has side margin portions arranged on both opposing ends of the active portion, and the connectivity of the internal electrodes in a region near the side margin portion, which is defined as a region from a boundary surface between the active portion and the side margin portion to a depth surface corresponding to a point corresponding to 5% to 20% of the entire length of the active portion, may be greater than or equal to 80% and less than or equal to 100%.

[0022] Another embodiment of the present invention includes the steps of: preparing a dielectric slurry by mixing a barium titanate-based main component powder and a gallium (Ga) complex compound; preparing a dielectric green sheet using the dielectric slurry and forming a conductive paste layer on a surface of the dielectric green sheet; laminating the dielectric green sheets on which the conductive paste layer is formed to prepare a dielectric green sheet laminate; sintering the dielectric green sheet laminate to prepare a capacitor body including a dielectric layer and an internal electrode layer; and forming an external electrode on one surface of the capacitor body, wherein the dielectric layer includes a barium titanate-based main component including barium (Ba) and titanium (Ti), and gallium (Ga), and a peak intensity ratio of Ba / Ga is obtained by TEM-EDS analysis of a region near the interface, defined as a region from an interface between the dielectric layer and the internal electrode layer to a depth surface of 10 nm to 500 nm into the dielectric layer. Ba / I Ga ) is 1.0 to 5.0.

[0023] The gallium (Ga) complex compound may include a gallium carboxylate in ionic form.

[0024] The gallium (Ga) complex compound is mixed so that the amount of gallium (Ga) is 0.01 to 10 parts by mole with respect to 100 parts by mole of the barium titanate-based main component powder.

[0025] The dielectric slurry may be prepared by further mixing with auxiliary component powders including aluminum oxide (Al2O3), silicon dioxide (SiO2), magnesium oxide (MgO), vanadium oxide (V2O5), manganese oxide (MnO2), or a combination thereof.

[0026] With respect to 100 molar parts of the barium titanate-based main component powder, 0.01 to 5 molar parts of the aluminum oxide (Al2O3), 0.01 to 5 molar parts of the silicon dioxide (SiO2), 0.01 to 5 molar parts of the magnesium oxide (MgO), 0.01 to 5 molar parts of the vanadium oxide (VO5), and 0.01 to 5 molar parts of the manganese oxide (MnO2) are mixed.

[0027] The sintering is carried out at a temperature of 1000°C to 1200°C. Effect of the Invention

[0028] The multilayer ceramic capacitor according to an embodiment has high reliability and is free from short circuits by reducing sintering mismatching between the dielectric layers and the internal electrode layers, thereby minimizing electrode breakage and improving connectivity of the internal electrodes. [Brief description of the drawings]

[0029] [Figure 1] 1 is a perspective view illustrating a multilayer ceramic capacitor according to an embodiment; [Diagram 2] 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line II' in FIG. [Diagram 3] 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line II-II' in FIG. [Figure 4] FIG. 4 is an enlarged view of region A in FIG. [Diagram 5] 3 is a TEM-EDS analysis image of the multilayer ceramic capacitor according to Example 1. [Figure 6]1 is a TEM-EDS analysis image of a multilayer ceramic capacitor according to Comparative Example 1. [Figure 7] 11 shows a result of STEM-EDS mapping analysis of an active part of the multilayer ceramic capacitor according to Example 3. [Figure 8] 4 shows SEM images of active parts of multilayer ceramic capacitors according to Examples 1 and 2 and Comparative Example 2. [Figure 9] 1 shows SEM images of regions near side margins of multilayer ceramic capacitors according to Examples 1 and 2 and Comparative Example 2. [Figure 10] 1 is a graph showing the change in density depending on the sintering temperature of the dielectric layers according to Examples 1 to 3 and Comparative Example 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Hereinafter, with reference to the accompanying drawings, an embodiment of the present invention will be described in detail so that a person having ordinary skill in the art to which the present invention pertains can easily carry out the present invention. In the drawings, parts that are unnecessary for the explanation are omitted in order to clearly explain the present invention, and the same reference numerals are used for the same or similar components throughout the specification. In addition, in the accompanying drawings, some components are exaggerated, omitted, or shown in a schematic manner, and the size of each component does not completely reflect the actual size.

[0031] It should be understood that the attached drawings are merely intended to facilitate understanding of the embodiments disclosed in this specification, and do not limit the technical ideas disclosed in this specification, but include all modifications, equivalents, or alternatives included in the idea and technical scope of the present invention.

[0032] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0033] In addition, when a part such as a layer, film, region, or plate is said to be "above" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Furthermore, being "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" the opposite direction of gravity.

[0034] It should be understood that, throughout the specification, the terms "comprise" or "have" are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Thus, when a part "comprises" a certain element, this means that it can further include other elements, but not to the exclusion of other elements, unless specifically stated to the contrary.

[0035] Also, throughout the specification, "on a plane" means when the subject part is viewed from above, and "on a cross section" means when the subject part is cut vertically and viewed from the side.

[0036] Furthermore, throughout the specification, when the term "connected" is used, this does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected via other components, and can mean not only that they are physically connected but also that they are electrically connected, or that they are referred to by different names depending on their position or function.

[0037] Hereinafter, a multilayer ceramic capacitor according to an embodiment will be described with reference to FIGS.

[0038] FIG. 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment, FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line II' in FIG. 1, FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor taken along line II-II' in FIG. 1, and FIG. 4 is an enlarged view of region A in FIG. 3.

[0039] The L axis, W axis, and T axis shown in Figs. 1 to 3 respectively indicate the longitudinal direction, width direction, and thickness direction of the capacitor body 110. Here, the thickness direction (T axis direction) may be a direction perpendicular to the wide surface (main surface) of the sheet-shaped component, and may be used in the same concept as the lamination direction in which the dielectric layers 111 are laminated, for example. The longitudinal direction (L axis direction) is a direction extending in parallel to the wide surface (main surface) of the sheet-shaped component and approximately perpendicular to the thickness direction (T axis direction), and may be, for example, a direction in which the first external electrode 131 and the second external electrode 132 are located on both sides. The width direction (W axis direction) may be a direction extending in parallel to the wide surface (main surface) of the sheet-shaped component and approximately perpendicular to the thickness direction (T axis direction) and the longitudinal direction (L axis direction), and the length of the longitudinal direction (L axis direction) of the sheet-shaped component is longer than the length of the width direction (W axis direction).

[0040] 1 to 4, a multilayer ceramic capacitor 100 according to an embodiment includes a capacitor body 110 and external electrodes 131, 132 disposed on the outer side of the capacitor body 110. The external electrodes 131, 132 may include a first external electrode 131 and a second external electrode 132 disposed on opposite ends of the capacitor body 110 in a longitudinal direction (L-axis direction).

[0041] For example, the capacitor body 110 may have a substantially hexahedral shape.

[0042] For the convenience of describing one embodiment, in capacitor body 110, the two surfaces that face each other in the thickness direction (T-axis direction) are defined as the first surface and the second surface, and the two surfaces that are connected to the first surface and the second surface, the two surfaces that face each other in the longitudinal direction (L-axis direction) are defined as the third surface and the fourth surface, and the two surfaces that are connected to the first surface and the second surface and the third surface and the fourth surface, and the two surfaces that face each other in the width direction (W-axis direction) are defined as the fifth surface and the sixth surface.

[0043] As an example, the first surface of the lower surface is the surface facing the mounting direction. The first to sixth surfaces may be flat, but the embodiment is not limited to this. For example, the first to sixth surfaces may be curved surfaces with a convex center, and the corners that are the boundaries between the surfaces may be rounded.

[0044] The shape and size of the capacitor body 110 and the number of laminated dielectric layers 111 are not limited to those shown in the figure of this embodiment.

[0045] The capacitor body 110 includes a plurality of dielectric layers 111 and internal electrode layers 121 and 122. Specifically, the capacitor body 110 includes a plurality of dielectric layers 111, and first internal electrodes 121 and second internal electrodes 122 that are alternately arranged in the thickness direction (T-axis direction) with the dielectric layers 111 sandwiched between them.

[0046] At this time, the boundaries between the adjacent dielectric layers 111 of the capacitor body 110 are integrated to such an extent that it is difficult to confirm them without using a scanning electron microscope (SEM).

[0047] The capacitor body 110 may have an active portion A. The active portion A is a region where the dielectric layers 111 and the internal electrode layers 121, 122 are alternately arranged, and is a portion that contributes to forming the capacitance of the multilayer ceramic capacitor 100. Specifically, the active portion A may be a region where the first internal electrodes 121 or the second internal electrodes 122 stacked along the thickness direction (T-axis direction) overlap each other.

[0048] In addition, the capacitor body 110 may further include a cover portion and a side margin portion 140 .

[0049] The cover portion is a margin portion in the thickness direction, and can be located in the thickness direction (T-axis direction) on the first and second surface sides of the active portion A. Such a cover portion can be a single dielectric layer 111 or two or more dielectric layers 111 laminated on the upper and lower surfaces of the active portion A, respectively.

[0050] The side margin portion 140 may be regarded as a side cover portion, and may be located on both ends of the active portion A facing each other in the width direction (W-axis direction), i.e., on the fifth and sixth surfaces, respectively. The side margin portion 140 is formed by applying a conductive paste layer for an internal electrode layer only to a part of the surface of the dielectric green sheet when applying a conductive paste layer for the internal electrode layer to the surface of the dielectric green sheet, laminating dielectric green sheets on both side surfaces of the surface of the dielectric green sheet without applying a conductive paste layer, and then sintering the laminate, but is not limited to such a forming method.

[0051] The cover portion and the side margin portion 140 serve to prevent the first internal electrode 121 and the second internal electrode 122 from being damaged due to physical or chemical stress.

[0052] The dielectric layer 111 according to one embodiment includes a barium titanate-based main component including barium (Ba) and titanium (Ti), and gallium (Ga).

[0053] The capacitor body 110 is formed by sintering a laminate in which a plurality of dielectric layers 111 and internal electrode layers 121, 122 are stacked in the thickness direction (T-axis direction). At this time, the metal-based internal electrode layers 121, 122 are sintered at a relatively lower temperature than the ceramic material dielectric layer 111, so that the internal electrode layers 121, 122 may be oversintered when the dielectric layer 111 is sintered, and may shrink excessively and cause breakage. According to an embodiment, gallium (Ga) may act as a low-temperature sintering agent that reduces sintering mismatching between the dielectric layer 111 and the internal electrode layers 121, 122.

[0054] The main component of the barium titanate-based material is a dielectric base material having a high dielectric constant, and contributes to the formation of the dielectric constant of the multilayer ceramic capacitor 100 .

[0055] Gallium (Ga) may be formed from a gallium (Ga) complex compound, i.e., it may be an element derived from the material added to the dielectric base material. When gallium (Ga) is formed from a gallium (Ga) complex compound, gallium (Ga) is stably added and allows for uniform distribution in atomic units, thereby increasing the low-temperature sintering effect of the dielectric layer. This reduces sintering mismatch between the dielectric layer and the internal electrode layer, minimizing electrode breakage and improving the connectivity of the internal electrodes.

[0056] In addition, gallium (Ga) is a metal element with a low melting point of 29.76°C and can exist in liquid form at temperatures above 30°C. This can accelerate phenomena such as heat transfer and mass transfer, providing a low-temperature sintering effect for the dielectric layer.

[0057] Specifically, when a TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) was analyzed in the region R near the interface between the dielectric layer 111 and the internal electrode layers 121 and 122, the peak intensity ratio of Ba / Ga (I Ba / I Ga) may be 1.0 to 5.0, for example, 1.1 to 3.0, or 1.2 to 2.0. Ba / I Ga When the ratio is within the above range, sintering mismatch between the dielectric layers and the internal electrode layers is alleviated, electrode breakage is minimized, and the connectivity of the internal electrodes is improved, thereby ensuring a multilayer ceramic capacitor with high reliability without short circuits.

[0058] Here, the interface vicinity region R is defined as a region starting from the interface between the dielectric layer 111 and the internal electrode layers 121, 122 to a surface 10 nm to 500 nm deep, for example, 50 nm to 200 nm deep, from the interface into the dielectric layer 111. FIG. 4 is shown for the purpose of understanding the interface vicinity region R, and only one interface vicinity region R is shown for convenience, but the present invention is not limited to such a drawing. In other words, the interface vicinity region R can be present anywhere where the interface between the dielectric layer 111 and the internal electrode layers 121, 122 exists, and can be present on the other surface of one internal electrode layer in addition to one surface of the other.

[0059] The TEM-EDS analysis is performed as follows: Specifically, the multilayer ceramic capacitor 100 is immersed in an epoxy mixture and hardened, and then the W-axis and T-axis faces (WT faces) of the capacitor body 110 are polished to 1 / 2 points in the L-axis direction, and then fixed and maintained in a vacuum atmosphere chamber to obtain a cross-sectional sample so that the active part where the dielectric layer 111 and the internal electrode layers 121 and 122 intersect can be observed.

[0060] Next, the central portion of the active portion of the cross-sectional sample can be measured by a transmission electron microscope (TEM). The transmission electron microscope uses a Xe-FIB (focused ion beam) under conditions of an acceleration voltage of 200 kV and an analysis magnification of 110 kx, and can measure so that at least one, three, five, and ten dielectric layers 111 and internal electrode layers 121 and 122 are detected.

[0061] Next, the peak intensities of gallium (Ga) and barium (Ba) are obtained by EDS analysis in the transmission electron microscope (TEM) image of the measured cross-sectional sample. The peak intensity ratio of Ba / Ga (I Ba / I Ga ) is a value obtained by dividing the peak intensity of barium (Ba) appearing in a TEM-EDS analysis by the peak intensity of gallium (Ga). The peak intensity ratio of Ba / Ga may be an average value measured in the interface near region R at at least one point, two points, three points, or five points in the active part, or, when measured in the interface near region R at, for example, two points, it may be an average value of the peak intensity ratios of Ba / Ga at each point.

[0062] In addition, when the TEM-EDS in the region R near the interface was analyzed by the same method as described above, the Ti / Ga peak intensity ratio (I Ti / I Ga ) may be 1.0 to 5.0, for example, 1.1 to 3.0, or 1.2 to 2.0. Ti / I Ga When the ratio is within the above range, sintering mismatch between the dielectric layer and the internal electrode layer is alleviated, electrode breakage is minimized, and the connectivity of the internal electrodes is improved.

[0063] The gallium (Ga) is included in the dielectric layer 111 in an amount of 0.01 to 10 molar parts, for example, 0.05 to 8 molar parts, or 0.1 to 5 molar parts, relative to 100 molar parts of the barium titanate-based main component. When the gallium (Ga) is included within the above content range, the low-temperature sintering effect of the dielectric layer is increased, thereby reducing sintering mismatch between the dielectric layer and the internal electrode layer, minimizing electrode breakage, and improving the connectivity of the internal electrodes. Therefore, a multilayer ceramic capacitor with high reliability without short circuit can be obtained.

[0064] The dielectric layer 111 according to one embodiment may further include minor components including aluminum (Al), silicon (Si), magnesium (Mg), vanadium (V), manganese (Mn), or combinations thereof. Gallium (Ga) may also be present as a secondary phase in combination with these minor components.

[0065] The minor component can be derived from a metal oxide that is added as a minor component to the dielectric matrix.

[0066] When the TEM-EDS was analyzed in the region R near the interface between the dielectric layer 111 and the internal electrode layers 121 and 122 by the same method as described above, the peak intensity ratio of Al / Ga (I Al / I Ga ) may be 1.0 to 5.0, for example, 1.0 to 4.0, or 1.2 to 3.0. Al / I Ga When the ratio is within the above range, sintering mismatch between the dielectric layer and the internal electrode layer is alleviated, electrode breakage is minimized, and the connectivity of the internal electrodes is improved.

[0067] In addition, when the TEM-EDS was analyzed in the region R near the interface between the dielectric layer 111 and the internal electrode layers 121 and 122 by the same method as described above, the peak intensity ratio of Si / Ga (I Si / I Ga ) may be 1.0 to 5.0, for example, 1.0 to 4.0, or 1.5 to 3.0. Si / I Ga When the ratio is within the above range, sintering mismatch between the dielectric layer and the internal electrode layer is alleviated, electrode breakage is minimized, and the connectivity of the internal electrodes is improved.

[0068] In addition, when the TEM-EDS was analyzed in the region R near the interface between the dielectric layer 111 and the internal electrode layers 121 and 122 by the same method as described above, the peak intensity ratio of Mg / Ga (I Mg / I Ga) may be 0.4 to 2.0, for example, 0.4 to 1.5, or 0.5 to 1.0. Mg / I Ga When the ratio is within the above range, sintering mismatch between the dielectric layer and the internal electrode layer is alleviated, electrode breakage is minimized, and the connectivity of the internal electrodes is improved.

[0069] The minor component aluminum (Al) is contained in an amount of 0.01 to 5 mol parts relative to 100 mol parts of the barium titanate-based main component, silicon (Si) is contained in an amount of 0.01 to 5 mol parts relative to 100 mol parts of the barium titanate-based main component, magnesium (Mg) is contained in an amount of 0.01 to 5 mol parts relative to 100 mol parts of the barium titanate-based main component, V (vanadium) is contained in an amount of 0.01 to 5 mol parts relative to 100 mol parts of the barium titanate-based main component, and Mn (manganese) is contained in an amount of 0.01 to 5 mol parts relative to 100 mol parts of the barium titanate-based main component. When the minor components are contained within the above content ranges, a secondary phase is easily formed with gallium (Ga), thereby increasing the low-temperature sintering effect of the dielectric layer. Therefore, sintering mismatch between the dielectric layer and the internal electrode layer is alleviated, electrode breakage is minimized, and the connectivity of the internal electrodes is improved.

[0070] The dielectric layer 111 may include a plurality of grains and grain boundaries located between adjacent grains.

[0071] The grains may include a barium titanate based main component.

[0072] Gallium (Ga) may be present in both the crystal grains and the crystal grain boundaries in the dielectric layer 111, for example, in the crystal grain boundaries. Gallium (Ga) may also be present in the form of a secondary phase in the crystal grain boundaries. Specifically, the molar ratio of gallium (Ga) present in the crystal grains to gallium (Ga) present in the crystal grains may be 5:1 to 50:1, for example, 10:1 to 30:1. When the molar ratio of gallium (Ga) present in the crystal grain boundaries to gallium (Ga) present in the crystal grains is within the above range, sintering mismatch between the dielectric layer and the internal electrode layer is alleviated, electrode breakage is minimized, and the connectivity of the internal electrodes is improved.

[0073] The average thickness (average length in the T-axis direction) of the dielectric layers 111 may be 2.0 μm to 8.0 μm, for example, 2.4 μm to 7.8 μm. When the average thickness of the dielectric layers 111 is within the above range, the multilayer ceramic capacitor has excellent reliability.

[0074] The average thickness of the dielectric layer 111 is measured by immersing the multilayer ceramic capacitor 100 in an epoxy mixture, curing the multilayer ceramic capacitor 100, polishing the multilayer ceramic capacitor 100, and then performing ion milling and analyzing the multilayer ceramic capacitor 100 with a scanning electron microscope (SEM). The scanning electron microscope may be, for example, a Verios G4 product from Thermofisher Scientific, with measurement conditions of 10 kV, 0.2 nA, and an analysis magnification of 100 times, and may be measured so that at least one, three, five, or ten dielectric layers 111 are obtained. In the scanning electron microscope (SEM) image, the central point of the dielectric layer 111 in the longitudinal direction (L-axis direction) or width direction (W-axis direction) is set as a reference point, and the average thickness may be an arithmetic average value of the thickness of the dielectric layer 111 at ten points spaced apart from the reference point at a predetermined interval. The interval between the 10 points can be adjusted according to the scale of a scanning electron microscope (SEM) image, and may be, for example, 1 μm to 100 μm, 1 μm to 50 μm, or 1 μm to 10 μm. In this case, all of the 10 points must be located within the dielectric layer 111, and if all of the 10 points are not located within the dielectric layer 111, the position of the reference point can be changed or the interval between the 10 points can be adjusted.

[0075] The first internal electrode 121 and the second internal electrode 122 are electrodes having different polarities and are alternately arranged so as to face each other along the T-axis direction with the dielectric layer 111 in between, and one end can be exposed through the third and fourth surfaces of the capacitor body 110, respectively.

[0076] The first internal electrode 121 and the second internal electrode 122 can be electrically insulated from each other by a dielectric layer 111 disposed therebetween.

[0077] Ends of the first internal electrode 121 and the second internal electrode 122 alternately exposed through the third and fourth surfaces of the capacitor body 110 can be electrically connected to the first external electrode 131 and the second external electrode 132, respectively.

[0078] The first internal electrode 121 and the second internal electrode 122 include a conductive metal, and may include, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy thereof, for example, an Ag-Pd alloy.

[0079] Furthermore, the first internal electrode 121 and the second internal electrode 122 may contain dielectric particles of the same composition as the ceramic material contained in the dielectric layer 111 .

[0080] The first internal electrode 121 and the second internal electrode 122 are formed using a conductive paste containing a conductive metal. The conductive paste can be printed by screen printing or gravure printing.

[0081] The average thickness of the first internal electrode 121 and the second internal electrode 122 may be 0.1 μm to 2 μm. The average thickness of the first internal electrode 121 and the second internal electrode 122 is measured by scanning electron microscope (SEM) analysis. Here, the scanning electron microscope (SEM) analysis is the same as the method used to measure the average thickness of the dielectric layer 111 described above, and therefore a description thereof will be omitted.

[0082] As described above, the capacitor body 110 is formed by sintering a laminate in which a plurality of dielectric layers 111 and internal electrode layers 121, 122 are stacked. Specifically, the capacitor body 110 is formed by sintering at a temperature of 1000° C. to 1200° C., for example, at a temperature of 1050° C. to 1150° C. Since the capacitor body 110 is sintered at a low temperature within the above temperature range, sintering mismatch between the dielectric layers 111 and the internal electrode layers 121, 122 is mitigated, thereby minimizing electrode breakage and improving the connectivity of the internal electrodes.

[0083] In the multilayer ceramic capacitor 100 according to an embodiment, the connectivity of the internal electrodes in the active part A may be 80% or more and 100% or less, for example, 82% to 95%, or 84% to 93%. When the connectivity of the internal electrodes in the active part A is within the above range, the occurrence of electrode disconnection is minimized, and a multilayer ceramic capacitor having high reliability without short circuiting can be obtained. Here, the active part A is a region in which the dielectric layers 111 and the internal electrode layers 121 and 122 are alternately arranged, as shown in FIG. 3 described above.

[0084] The connectivity of the internal electrodes is measured as follows.

[0085] First, the multilayer ceramic capacitor 100 is placed in an epoxy mixture and hardened, and then the W-axis and T-axis surfaces (WT surfaces) of the capacitor body 110 are polished to the 1 / 2 point in the L-axis direction, fixed, and maintained in a vacuum atmosphere chamber to obtain a cross-sectional sample so that the active part where the dielectric layer 111 and the internal electrode layers 121 and 122 intersect can be observed.

[0086] Next, the active portion of the cross-sectional sample can be ion milled and measured with a scanning electron microscope (SEM). The scanning electron microscope can be, for example, a Verios G4 product from Thermofisher Scientific, with measurement conditions of 10 kV and 0.2 nA and an analysis magnification of 100 times, and can measure so that at least one, three, five, or ten dielectric layers 111 are exposed.

[0087] The connectivity of the internal electrodes measured in this manner can be calculated using the following Equation 1.

[0088] [Formula 1] Connectivity of internal electrodes (%) = (total length of connected parts excluding discontinuous parts in multiple internal electrode layers / total length of multiple internal electrode layers) x 100

[0089] In Equation 1, the denominator is the total length of all the internal electrode layers present in the active section A, including all of the connecting sections L and the discontinuous sections C. In Equation 1, the numerator is the total length of the connecting sections L in the multiple internal electrode layers, excluding the discontinuous sections C. For reference, in FIG. 4, the connecting sections L and the discontinuous sections C are shown in only one place for convenience, and are omitted from other portions.

[0090] In addition, in the multilayer ceramic capacitor 100 according to an embodiment, the connectivity of the internal electrodes in the side margin adjacent region B may be 80% or more and 100% or less, for example, 82% to 95%, or 84% to 93%. When the connectivity of the internal electrodes in the side margin adjacent region B is within the above range, the occurrence of electrode disconnection is minimized, and a multilayer ceramic capacitor having high reliability without short circuit can be ensured.

[0091] Here, the side margin vicinity region B refers to a region starting from the boundary surface between the active portion A and the side margin portion 140 to a depth surface corresponding to 5% to 20%, for example 8% to 15%, of the entire length of the active portion A in the width direction (W-axis direction) from the boundary surface to the active portion A, as shown in Fig. 3. The method of measuring the connectivity of the internal electrodes and the definition in Equation 1 are as described above.

[0092] The first external electrode 131 and the second external electrode 132 are provided with voltages of different polarities and are electrically connected to exposed portions of the first internal electrode 121 and the second internal electrode 122, respectively.

[0093] With this configuration, when a predetermined voltage is applied to the first external electrode 131 and the second external electrode 132, charges are stored between the opposing first internal electrode 121 and second internal electrode 122. At this time, the capacitance of the multilayer ceramic capacitor 100 is proportional to the overlap area of ​​the first internal electrode 121 and the second internal electrode 122 that overlap each other along the T-axis direction in the active part A.

[0094] The first external electrode 131 and the second external electrode 132 may each include first and second connection portions arranged on the third and fourth surfaces of the capacitor body 110 and connected to the first internal electrode 121 and the second internal electrode 122, respectively, and first and second band portions arranged at corners where the third and fourth surfaces of the capacitor body 110 meet the first and second surfaces or the fifth and sixth surfaces.

[0095] The first and second band portions may extend from the first and second connection portions to parts of the first and second faces or the fifth and sixth faces of the capacitor body 110. The first and second band portions may serve to improve the bonding strength between the first external electrode 131 and the second external electrode 132.

[0096] The first external electrode 131 and the second external electrode 132 may each include a sintered metal layer in contact with the capacitor body 110, a conductive resin layer arranged to cover the sintered metal layer, and a plating layer arranged to cover the conductive resin layer.

[0097] The sintered metal layer can include a conductive metal and glass.

[0098] The conductive metal may include copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), lead (Pb), alloys thereof, or combinations thereof, for example, copper (Cu) may include copper (Cu) alloys. When the conductive metal includes copper, the metal other than copper is included in an amount of 5 molar parts or less per 100 molar parts of copper.

[0099] The glass may include a mixed oxide composition, such as one or more selected from the group consisting of silicon oxide, boron oxide, aluminum oxide, transition metal oxide, alkali metal oxide, and alkaline earth metal oxide. The transition metal may be selected from the group consisting of zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), and nickel (Ni), the alkali metal may be selected from the group consisting of lithium (Li), sodium (Na), and potassium (K), and the alkaline earth metal may be one or more selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).

[0100] Alternatively, the conductive resin layer may be formed on the sintered metal layer, for example, to completely cover the sintered metal layer. Alternatively, the first external electrode 131 and the second external electrode 132 may not include a sintered metal layer, in which case the conductive resin layer may be in direct contact with the capacitor body 110.

[0101] The conductive resin layer extends on the first and second surfaces or the fifth and sixth surfaces of the capacitor body 110, and the length of the region (i.e., band portion) where the conductive resin layer is arranged extending on the first and second surfaces or the fifth and sixth surfaces of the capacitor body 110 is longer than the length of the region (i.e., band portion) where the sintered metal layer is arranged extending on the first and second surfaces or the fifth and sixth surfaces of the capacitor body 110. In other words, the conductive resin layer is formed on the sintered metal layer to completely cover the sintered metal layer.

[0102] The conductive resin layer includes a resin and a conductive metal.

[0103] The resin contained in the conductive resin layer is not particularly limited as long as it has bonding and impact absorbing properties and can be mixed with the conductive metal powder to form a paste, and may include, for example, a phenolic resin, an acrylic resin, a silicone resin, an epoxy resin, or a polyimide resin.

[0104] The conductive metal contained in the conductive resin layer serves to electrically connect with the first internal electrode 121 and the second internal electrode 122 or the sintered metal layer.

[0105] The conductive metal contained in the conductive resin layer may have a spherical shape, a flake shape, or a combination thereof, that is, the conductive metal may be only flake-shaped, only spherical, or a mixture of flake-shaped and spherical shapes.

[0106] Here, the term "spherical" may include shapes that are not completely spherical, and may include shapes in which the ratio of the major axis to the minor axis (major axis / minor axis) is 1.45 or less. The term "flaky powder" refers to a powder having a flat and elongated shape, and is not particularly limited, and may include shapes in which the ratio of the major axis to the minor axis (major axis / minor axis) is 1.95 or more, for example.

[0107] The first external electrode 131 and the second external electrode 132 may further include a plating layer disposed on the outer side of the conductive resin layer.

[0108] The plating layer may include nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), or lead (Pb) alone or in combination with an alloy thereof. For example, the plating layer may be a nickel (Ni) plating layer or a tin (Sn) plating layer, or may be a layer in which a nickel (Ni) plating layer and a tin (Sn) plating layer are sequentially laminated, or a layer in which a tin (Sn) plating layer, a nickel (Ni) plating layer, and a tin (Sn) plating layer are sequentially laminated. The plating layer may include a plurality of nickel (Ni) plating layers and / or a plurality of tin (Sn) plating layers.

[0109] The plating layer can improve the mountability of the multilayer capacitor 100 on a substrate, structural reliability, durability against the outside, heat resistance, and equivalent series resistance (ESR).

[0110] A method for manufacturing the multilayer ceramic capacitor 100 according to an embodiment will now be described.

[0111] The multilayer ceramic capacitor 100 according to an embodiment can be manufactured by the steps of: mixing a barium titanate-based main component powder and a gallium (Ga) complex compound to prepare a dielectric slurry; preparing a dielectric green sheet using the dielectric slurry and forming a conductive paste layer on a surface of the dielectric green sheet; laminating the dielectric green sheets on which the conductive paste layer is formed to prepare a dielectric green sheet laminate; sintering the dielectric green sheet laminate to prepare a capacitor body including a dielectric layer and an internal electrode layer; and forming an external electrode on one surface of the capacitor body.

[0112] The dielectric slurry can be produced by mixing a barium titanate-based main component powder and a gallium (Ga) complex compound.

[0113] The gallium (Ga) complex compound is a compound in which gallium (Ga) is dispersed in a polycarboxylic acid compound and has an ionic form, and may include gallium carboxylate in an ionic form.

[0114] The gallium (Ga) complex compound is mixed with 100 mol parts of the barium titanate-based main component powder so that gallium (Ga) is 0.01 mol parts to 10 mol parts, for example, 0.05 mol parts to 8 mol parts, 0.1 mol parts to 5 mol parts. When the gallium (Ga) complex compound is mixed within the above content range, gallium (Ga) is stably added to barium titanate corresponding to the dielectric base material, enabling uniform distribution in atomic units, thereby increasing the low-temperature sintering effect of the dielectric layer. This reduces sintering mismatch between the dielectric layer and the internal electrode layer, minimizing electrode breakage and improving the connectivity of the internal electrodes.

[0115] The dielectric slurry can be prepared by additionally mixing the powder of the minor component, which may be used in the form of a sol dispersed in an organic solvent.

[0116] The secondary component powder may be aluminum oxide (Al2O3), silicon dioxide (SiO2), magnesium oxide (MgO), vanadium oxide (VO5), manganese oxide (MnO2), or a combination thereof. The secondary component powder may be used in the form of a sol dispersed in an organic solvent.

[0117] Aluminum oxide (Al2O3) is mixed with 0.01 to 5 molar parts per 100 molar parts of the barium titanate-based main component powder, silicon dioxide (SiO2) is mixed with 0.01 to 5 molar parts per 100 molar parts of the barium titanate-based main component powder, magnesium oxide (MgO) is mixed with 0.01 to 5 molar parts per 100 molar parts of the barium titanate-based main component powder, vanadium oxide (VO5) is mixed with 0.01 to 5 molar parts per 100 molar parts of the barium titanate-based main component powder, and manganese oxide (MnO2) is mixed with 0.01 to 5 molar parts per 100 molar parts of the barium titanate-based main component powder. When the auxiliary component powders are mixed within the above content ranges, a secondary phase with gallium (Ga) is easily formed, which increases the low-temperature sintering effect of the dielectric layer.

[0118] The dielectric slurry may be prepared by additionally mixing additives such as a dispersant, a binder, a plasticizer, a lubricant, an antistatic agent, and a solvent.

[0119] The dispersant may include, for example, a phosphate-based dispersant, a polycarboxylic acid-based dispersant, or a combination thereof. The dispersant is mixed in an amount of 0.1 to 5 parts by weight, for example, 0.3 to 3 parts by weight, relative to 100 parts by weight of the total amount of the barium titanate and the gallium (Ga) complex compound. When the dispersant is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the manufactured dielectric layer can be reduced.

[0120] The binder may be, for example, an acrylic resin, a polyvinyl butyral resin, a polyvinyl acetal resin, an ethyl cellulose resin, etc. The binder is added in an amount of 0.1 to 50 parts by weight, for example, 3 to 30 parts by weight, relative to 100 parts by weight of the total amount of the barium titanate and the gallium (Ga) complex compound. When the binder is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the manufactured dielectric layer can be reduced.

[0121] The plasticizer may be, for example, a phthalic acid compound such as dioctyl phthalate, benzyl butyl phthalate, dibutyl phthalate, dihexyl phthalate, di(2-ethylhexyl) phthalate, or di(2-ethylbutyl) phthalate; an adipic acid compound such as dihexyl adipate or di(2-ethylhexyl) adipate; a glycol compound such as ethylene glycol, diethylene glycol, or triethylene glycol; or a glycol ester compound such as triethylene glycol dibutyrate, triethylene glycol di(2-ethylbutyrate), or triethylene glycol di(2-ethylhexanoate). The plasticizer is added in an amount of 0.1 to 20 parts by weight, for example, 1 to 10 parts by weight, relative to 100 parts by weight of the total amount of the barium titanate and the gallium (Ga) complex compound. When the plasticizer is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the manufactured dielectric layer can be reduced.

[0122] The solvent may be an aqueous solvent such as water; an alcoholic solvent such as ethanol, methanol, benzyl alcohol, or methoxyethanol; a glycol solvent such as ethylene glycol or diethylene glycol; a ketone solvent such as acetone, methyl ethyl ketone, methyl isobutyl ketone, or cyclohexanone; an ester solvent such as butyl acetate, ethyl acetate, carbitol acetate, or butyl carbitol acetate; an ether solvent such as methyl cellosolve, ethyl cellosolve, butyl ether, or tetrahydrofuran; or an aromatic solvent such as benzene, toluene, or xylene. The solvent may be an alcoholic solvent or an aromatic solvent, for example, taking into consideration the solubility and dispersibility of various additives contained in the dielectric slurry. The solvent is mixed in an amount of 50 parts by weight to 1000 parts by weight, for example, 100 parts by weight to 500 parts by weight, relative to 100 parts by weight of the total amount of barium titanate and gallium (Ga) complex compound. When the solvent is mixed within the above content range, the dielectric slurry components are sufficiently mixed, and the solvent can be easily removed thereafter.

[0123] A wet ball mill or an agitation mill can be used to mix the barium titanate-based main component powder, the gallium (Ga) complex compound, and optionally the subcomponent powder. When using zirconia balls in a wet ball mill, the mixture can be wet mixed for 8 to 48 hours or 10 to 24 hours using multiple zirconia balls with diameters of 0.1 to 10 mm.

[0124] The prepared dielectric slurry is formed into a dielectric layer after sintering.

[0125] The produced dielectric slurry can be molded into a sheet shape using a tape molding method such as a doctor blade method or a calendar roll method, for example, a head-discharging on-roll molding coater, and then the molded body can be dried to obtain a dielectric green sheet.

[0126] To form a conductive paste layer that will become an internal electrode layer after sintering, a conductive paste can be manufactured by mixing a conductive powder made of a conductive metal or its alloy, a binder, and a solvent. If necessary, barium titanate powder can be mixed in as a co-material. The co-material can suppress the sintering of the conductive powder during the sintering process. The conductive paste is applied in a predetermined pattern to the surface of the dielectric green sheet by various printing methods such as screen printing or transfer methods to form a conductive paste layer.

[0127] Next, the dielectric green sheets on which the internal electrode patterns are formed are laminated in a plurality of layers, and then pressed in the lamination direction to manufacture a dielectric green sheet laminate. At this time, the dielectric green sheets and the internal electrode patterns can be laminated so that the dielectric green sheets are located on the upper and lower surfaces of the dielectric green sheet laminate in the lamination direction.

[0128] The manufactured dielectric green sheet laminate may be selectively cut into a predetermined size by dicing or the like.

[0129] Furthermore, the dielectric green sheet laminate can be solidified and dried to remove plasticizers, etc., as necessary, and after solidification and drying, can be barrel polished using a horizontal centrifugal barrel machine, etc. In barrel polishing, the dielectric green sheet laminate is placed in a barrel container together with media and polishing liquid, and unnecessary parts such as burrs generated during cutting can be polished by applying rotational motion, vibration, etc. to the barrel container. Furthermore, after barrel polishing, the dielectric green sheet laminate can be washed with a cleaning liquid such as water and dried.

[0130] The dielectric greensheet stack can then be debindered and sintered to produce a capacitor body.

[0131] The binder removal treatment conditions can be appropriately adjusted depending on the components of the dielectric layers and the internal electrode layers. For example, the temperature rise rate during the binder removal treatment may be 5°C / hour to 300°C / hour, the support temperature may be 180°C to 400°C, and the temperature maintenance time may be 0.5 hours to 24 hours. The atmosphere during the binder removal treatment may be air or a reducing atmosphere.

[0132] The dielectric green sheet laminate is sintered at a temperature of 1000° C. to 1200° C., for example, at a temperature of 1050° C. to 1150° C. When the sintering is performed at a temperature within the above range, sintering mismatch between the dielectric layers and the internal electrode layers is alleviated, thereby minimizing electrode breakage and improving the connectivity of the internal electrodes.

[0133] The sintering is performed for 0.5 to 8 hours, for example, 1 to 3 hours. The sintering is performed in a reducing atmosphere, for example, an atmosphere of a humidified mixed gas of nitrogen and hydrogen. When the internal electrode contains nickel (Ni) or a nickel (Ni) alloy, the oxygen partial pressure in the sintering atmosphere is 1.0×10 -14 MPa~1.0×10 -10 It may be MPa.

[0134] After sintering, annealing can be carried out as necessary. Annealing is a process for reoxidizing the dielectric layer, and can be carried out when sintering is carried out in a reducing atmosphere. The conditions of the annealing process can also be appropriately adjusted depending on the components of the dielectric layer. For example, the annealing temperature may be 950°C to 1150°C, the annealing time may be 0 hours to 20 hours, and the heating rate may be 50°C / hour to 500°C / hour. The annealing atmosphere may be a humidified nitrogen gas (N2) atmosphere, and the oxygen partial pressure may be 1.0×10 -9 MPa~1.0×10 -5 It may be MPa.

[0135] In the binder removal treatment, sintering treatment, or annealing treatment, for example, a wetter can be used to moisten the nitrogen gas or mixed gas, and in this case, the water temperature may be 5° C. to 75° C. The binder removal treatment, sintering treatment, and annealing treatment may be performed consecutively or independently.

[0136] Optionally, surface treatment such as sandblasting, laser irradiation, barrel polishing, etc. may be performed on the third and fourth faces of the manufactured capacitor body 110. By performing such surface treatment, the ends of the first and second internal electrodes are exposed on the outermost surfaces of the third and fourth faces, which improves the electrical connection between the first and second external electrodes and the first and second internal electrodes, making it easier to form an alloy part.

[0137] Next, an external electrode is formed on one surface of the manufactured capacitor body 110 .

[0138] As an example, a paste for forming a sintered metal layer can be applied to the external electrodes and then sintered to form a sintered metal layer.

[0139] The paste for forming the sintered metal layer may include a conductive metal and glass. The conductive metal and glass have been described above, and therefore will not be described again. The paste for forming the sintered metal layer may selectively include a binder, a solvent, a dispersant, a plasticizer, an oxide powder, and the like. The binder may be, for example, ethyl cellulose, acrylic, butyral, and the solvent may be, for example, an organic solvent or an aqueous solvent such as terpineol, butyl carbitol, alcohol, methyl ethyl ketone, acetone, or toluene.

[0140] The method of applying the sintered metal layer forming paste to the outer surface of the capacitor body 110 can be a dipping method, various printing methods such as screen printing, an application method using a dispenser, a spraying method using a spray, etc. The sintered metal layer forming paste is applied to at least the third and fourth surfaces of the capacitor body 110, and is selectively applied to parts of the first, second, fifth, or sixth surfaces on which the band portions of the first and second external electrodes are formed.

[0141] Thereafter, the capacitor body 110 on which the paste for forming a sintered metal layer is applied is dried and sintered at a temperature of 700° C. to 1000° C. for 0.1 to 3 hours to form a sintered metal layer.

[0142] Alternatively, a conductive resin layer forming paste may be applied to the outer surface of the obtained capacitor body 110 and then cured to form a conductive resin layer.

[0143] The paste for forming the conductive resin layer may include a resin, and optionally a conductive metal or a non-conductive filler. The conductive metal and the resin have been described above, and therefore will not be described again. The paste for forming the conductive resin layer may optionally include a binder, a solvent, a dispersant, a plasticizer, an oxide powder, and the like. Examples of the binder include ethyl cellulose, acrylic, butyral, and the like, and examples of the solvent include organic solvents or aqueous solvents such as terpineol, butyl carbitol, alcohol, methyl ethyl ketone, acetone, and toluene.

[0144] As an example, the conductive resin layer may be formed by dipping the capacitor body 110 in a paste for forming the conductive resin layer and then curing it, or by printing the paste for forming the conductive resin layer on the surface of the capacitor body 110 using a screen printing method or a gravure printing method, or by applying the paste for forming the conductive resin layer on the surface of the capacitor body 110 and then curing it.

[0145] Next, a plating layer is formed on the outside of the conductive resin layer.

[0146] As an example, the plating layer is formed by a plating method, and may be formed by sputtering or electric deposition.

[0147] The above-mentioned embodiments will be described in more detail with reference to the following examples, which are merely for illustrative purposes and are not intended to limit the scope of the invention.

[0148] (Manufacturing of multilayer ceramic capacitors) Examples 1 to 3 and Comparative Examples 1 and 2 Barium titanate (BaTiO3) powder, gallium raw material, and subcomponent powders of aluminum oxide (Al2O3), silicon dioxide (SiO2), magnesium oxide (MgO), vanadium oxide (V2O5), and manganese oxide (MnO2) were mixed according to the composition shown in Table 1 below to prepare a dielectric slurry. In this case, gallium carboxylate (Ga-COO) in the form of ions was used as the gallium raw material in Examples 1 to 3, gallium oxide (Ga2O3) was used in Comparative Example 1, and no gallium raw material was used in Comparative Example 2. The mixture was mechanically milled after adding ethanol / toluene and polyvinyl butyral (PVB) resin as a wetting dispersant and binder using zirconium balls (ZrO2balls) as a dispersion medium.

[0149] The prepared dielectric slurry was used in a head-discharging on-roll forming coater to prepare a dielectric green sheet.

[0150] A conductive paste layer containing nickel (Ni) was printed on the surface of a dielectric green sheet, and the dielectric green sheets (width x length x height = 3.2 mm x 2.5 mm x 2.5 mm) on which the conductive paste layer was formed were stacked and pressed to produce a dielectric green sheet laminate.

[0151] The dielectric green sheet laminate was subjected to a plasticization process in a nitrogen atmosphere at 400°C or less, and then sintered under conditions of a sintering temperature of 1300°C or less and a hydrogen concentration of 1.0% H2 or less.

[0152] Next, a multilayer ceramic capacitor was manufactured through processes such as forming external electrodes and plating.

[0153] [Table 1]

[0154] Evaluation 1: TEM-EDS analysis The multilayer ceramic capacitors manufactured in Example 1 and Comparative Example 1 were subjected to TEM-EDS (Transmission Electron Microscopy-Energy Dispersive Spectroscopy) analysis, and the peak intensity of each detected element and the peak intensity ratio between two elements are shown in the following Tables 2 and 3. The results for Example 1 are shown in Table 2 below, and the results for Comparative Example 1 are shown in Table 3 below.

[0155] The TEM-EDS analysis was performed as follows. The multilayer ceramic capacitors manufactured in Example 1 and Comparative Example 1 were immersed in an epoxy mixture and cured, and then the W-axis and T-axis faces (WT faces) of the capacitor body 110 were polished to 1 / 2 points in the L-axis direction, and then fixed and maintained in a vacuum atmosphere chamber to obtain a cross-section sample so that the active part where the dielectric layer and the internal electrode layer intersect can be observed. The center part of the active part of the cross-section sample was measured by TEM. TEM was performed using Xe-FIB (focused ion beam) at an acceleration voltage of 200 kV and an analysis magnification of 110 kx, and measurements were performed so that at least five layers of dielectric layers and internal electrode layers could be seen. In the TEM image of the measured cross-section sample, EDS analysis was performed on the region R near the interface, that is, the region starting from the interface between the dielectric layer and the internal electrode layer to a depth of 100 nm from the interface into the dielectric layer, to measure the peak intensity ratio between elements. The peak intensity ratio between elements was measured in the interface vicinity region R at two points in the active part, and the average value of the peak intensity ratio between elements at each point was calculated.

[0156] The peak intensity for each element and the peak intensity ratio between two elements shown in Tables 2 and 3 below are average values ​​measured at two points shown in Figures 5 and 6. Figure 5 is a TEM-EDS analysis image of the multilayer ceramic capacitor according to Example 1, and Figure 6 is a TEM-EDS analysis image of the multilayer ceramic capacitor according to Comparative Example 1.

[0157] In Tables 2 and 3 below, E1 is the peak intensity value of each element at point 1, and E2 is the peak intensity value of each element at point 2. After each peak intensity value is determined, the Ga peak intensity is set as the denominator to determine the ratio, and the average indicates the average value of the E1 / Ga ratio and the E2 / Ga ratio.

[0158] [Table 2]

[0159] [Table 3]

[0160] Referring to Tables 2 and 3, in the case of Example 1 in which a gallium complex compound was applied according to one embodiment, the peak intensity ratio of Ba / Ga (I Ba / I Ga ) is in the range of 1.0 to 5.0, whereas in the case of Comparative Example 1 in which Ga in the form of a metal oxide is applied, the Ba / Ga peak intensity ratio (I Ba / I Ga ) is found to be 0.21.

[0161] In addition, in the case of Comparative Example 1 in which Ga in the form of metal oxide is applied, the Ga peak intensity is high in the region R near the interface between the dielectric layer and the internal electrode layer, which suggests the possibility that Ga exists locally and independently. In contrast, referring to Table 2, in the case of Example 1 in which a gallium complex is applied, the Ga peak intensity is relatively low in the region R near the interface between the dielectric layer and the internal electrode layer, which means that Ga forms a secondary glass phase with elements such as Mg, Al, and Si and is distributed uniformly. The formation of a glass phase can be seen from the fact that the peak intensity ratio of Al / Ga and the peak intensity ratio of Si / Ga are 1 or more.

[0162] Evaluation 2: STEM-EDS analysis The active part of the multilayer ceramic capacitor manufactured in Example 3 was subjected to STEM-EDS (Scanning Transmission Electron Microscopy-Energy Dispersive Spectroscopy) mapping analysis, and the results are shown in FIG.

[0163] The STEM-EDS analysis was performed as follows. A cross-sectional sample was obtained from the multilayer ceramic capacitor manufactured in Example 3 in the same manner as in Evaluation 1, and the center of the active part of the cross-sectional sample was measured by STEM. STEM was performed using a Xe-FIB (focused ion beam) at an acceleration voltage of 200 kV and an analysis magnification of 110 kx. In the STEM image of the measured cross-sectional sample, EDS analysis was performed on the region R near the interface, i.e., a region starting from the interface between the dielectric layer and the internal electrode layer to a depth of 100 nm from the interface into the dielectric layer.

[0164] FIG. 7 shows a result of STEM-EDS mapping analysis of the active part of the multilayer ceramic capacitor according to the third embodiment.

[0165] Referring to FIG. 7, it can be seen that Ga is uniformly distributed throughout the active portion of the multilayer ceramic capacitor according to an embodiment, Ga is distributed more at the grain boundaries than in the grains, and Ga also exists in the form of a secondary glass phase at the grain boundaries.

[0166] Evaluation 3: Internal electrode connectivity The multilayer ceramic capacitors manufactured in Examples 1 and 2 and Comparative Example 2 were analyzed by scanning electron microscope (SEM) to evaluate the connectivity of the internal electrodes. The results are shown in FIGS.

[0167] FIG. 8 is an SEM image of the active portion of the multilayer ceramic capacitors according to Examples 1 and 2 and Comparative Example 2, and FIG. 9 is an SEM image of the region near the side margin portion of the multilayer ceramic capacitors according to Examples 1 and 2 and Comparative Example 2.

[0168] Specifically, in relation to Fig. 8, cross-sectional samples were obtained from the multilayer ceramic capacitors manufactured in Examples 1 and 2 and Comparative Example 2 in the same manner as in Evaluation 1, and then ion milling was performed on the active portion A of the cross-sectional sample to perform SEM analysis, and the connectivity of the internal electrodes was measured. The SEM analysis was performed using a Verios G4 product from Thermofisher Scientific, with the measurement conditions being 10 kV, 0.2 nA, and the analysis magnification being 100x, and the measurement was performed so that about 20 dielectric layers were visible.

[0169] 9, a SEM analysis was performed on the region B near the side margin of the obtained cross-sectional sample to measure the connectivity of the internal electrodes. Here, the region B near the side margin refers to a region from the boundary between the active section and the side margin section to a depth surface corresponding to 10% of the entire width of the active section.

[0170] The connectivity of the internal electrodes was calculated by the following Equation 1.

[0171] [Formula 1] Connectivity of internal electrodes (%) = (total length of connected parts excluding discontinuous parts in multiple internal electrode layers / total length of multiple internal electrode layers) x 100

[0172] 8 and 9, when gallium (Ga) is included in the dielectric layer, the peak intensity ratio of Ba / Ga (I Ba / I Ga In the case of Examples 1 and 2, where the value of gallium (Ga) is in the range of 1.0 to 5.0, it can be seen that the connectivity of the internal electrodes is excellent in all of the areas near the active section and the side margin section, compared to the case of Comparative Example 2, where no gallium (Ga) is contained in the dielectric layer.

[0173] Evaluation 4: Low-temperature sintering effect FIG. 10 is a graph showing the change in density depending on the sintering temperature of the dielectric layers according to Examples 1 to 3 and Comparative Example 2.

[0174] Referring to FIG. 10, in the cases of Examples 1 to 3, the target density value of 5.8 g / cm 3 It can be seen that the sintering temperature reached in the case of Comparative Example 2 is about 1100°C, whereas the target density value cannot be reached even if the sintering temperature exceeds 1150°C. In other words, it can be seen that in the cases of Examples 1 to 3, a low-temperature sintering effect of about 50°C or more is shown to be achieved in reaching the target density value compared to Comparative Example 2. Therefore, when gallium (Ga) is contained in the dielectric layer, and the peak intensity ratio of Ba / Ga (I Ba / I Ga It can be seen that in the cases of Examples 1 to 3 in which the value of 1.0 to 5.0 is within the range, the low-temperature sintering effect of the dielectric layer is excellent compared to Comparative Example 2 in which no gallium (Ga) is contained in the dielectric layer.

[0175] Although the preferred embodiment of the present invention has been described above, the present invention is not limited thereto, and various modifications can be made within the scope of the claims, the description of the invention, and the accompanying drawings, which of course also fall within the scope of the present invention. [Explanation of symbols]

[0176] 100: Multilayer ceramic capacitor 110: Capacitor body 111: Dielectric layer 121: 1st internal electrode 122:Second internal electrode 131: 1st external electrode 132:Second external electrode

Claims

1. a capacitor body including a dielectric layer and an internal electrode layer; an external electrode disposed on an outer side of the capacitor body; The dielectric layer contains a barium titanate-based main component containing barium (Ba) and titanium (Ti), and gallium (Ga); The region near the interface, defined as a region from the interface between the dielectric layer and the internal electrode layer to a depth of 10 nm to 500 nm into the dielectric layer, is analyzed by TEM-EDS to determine the Ba / Ga peak intensity ratio (I Ｂａ / I Ｇａ ) is 1.0 to 5.

0.

2. During TEM-EDS analysis of the region near the interface, the Ti / Ga peak intensity ratio (I Ｔｉ / I Ｇａ 2. The multilayer ceramic capacitor according to claim 1, wherein the coefficient of friction coefficient is 1.0 to 5.

0.

3. The dielectric layer further comprises a minor component, 2. The multilayer ceramic capacitor according to claim 1, wherein the minor components include aluminum (Al), silicon (Si), magnesium (Mg), vanadium (V), manganese (Mn), or a combination thereof.

4. The auxiliary component includes aluminum (Al), In the TEM-EDS analysis of the region near the interface, the peak intensity ratio of Al / Ga (I Ａｌ / I Ｇａ 4. The multilayer ceramic capacitor according to claim 3, wherein the ratio of the ratio ...

5. The auxiliary component includes silicon (Si), In the TEM-EDS analysis of the region near the interface, the Si / Ga peak intensity ratio (I Ｓｉ / I Ｇａ 4. The multilayer ceramic capacitor according to claim 3, wherein the ratio of the ratio ...

6. The auxiliary component includes magnesium (Mg), In the TEM-EDS analysis of the region near the interface, the peak intensity ratio of Mg / Ga (I Ｍｇ / I Ｇａ 4. The multilayer ceramic capacitor according to claim 3, wherein the ratio of the ratio ...

7. The multilayer ceramic capacitor according to claim 3 , wherein the gallium (Ga) exists as a secondary phase in combination with the minor component.

8. 2. The multilayer ceramic capacitor according to claim 1, wherein the gallium (Ga) is contained in an amount of 0.01 to 10 parts by mol per 100 parts by mol of the barium titanate-based main component.

9. the dielectric layer includes a plurality of grains and a grain boundary located between adjacent grains; The multilayer ceramic capacitor according to claim 1 , wherein the gallium (Ga) is present at the grain boundaries.

10. 10. The multilayer ceramic capacitor according to claim 9, wherein a molar ratio of the gallium (Ga) present at the grain boundaries to the gallium (Ga) present in the grains is 5:1 to 50:

1.

11. The multilayer ceramic capacitor according to claim 1 , wherein the gallium (Ga) is formed from a gallium (Ga) complex compound.

12. The multilayer ceramic capacitor according to claim 1 , wherein the capacitor body is formed by sintering at a temperature of 1000° C. to 1200° C.

13. the capacitor body has an active portion in which the dielectric layers and the internal electrode layers are alternately arranged; 2. The multilayer ceramic capacitor of claim 1, wherein the connectivity of the internal electrodes in the active portion is defined by the following Equation 1 and is in the range of 80% to 100%: [Formula 1] Connectivity of internal electrodes (%)=(total length of connecting parts excluding discontinuous parts in a plurality of internal electrode layers / total length of entire plurality of internal electrode layers)×100

14. the capacitor body further includes side margin portions disposed on both opposing ends of the active portion; 14. The multilayer ceramic capacitor of claim 13, wherein the connectivity of the internal electrodes in a region adjacent to the side margin portion, which is defined as a region from a boundary between the active portion and the side margin portion to a depth surface corresponding to a point corresponding to 5% to 20% of an entire length of the active portion, is 80% or more and 100% or less, as defined by Equation 1.

15. A step of preparing a dielectric slurry by mixing a barium titanate-based main component powder and a gallium (Ga) complex compound; preparing a dielectric green sheet using the dielectric slurry, and forming a conductive paste layer on a surface of the dielectric green sheet; laminating the dielectric green sheets having the conductive paste layers formed thereon to manufacture a dielectric green sheet laminate; sintering the dielectric green sheet laminate to produce a capacitor body including dielectric layers and internal electrode layers; and forming an external electrode on one surface of the capacitor body; The dielectric layer contains a barium titanate-based main component containing barium (Ba) and titanium (Ti), and gallium (Ga); The region near the interface, defined as a region from the interface between the dielectric layer and the internal electrode layer to a depth of 10 nm to 500 nm into the dielectric layer, is analyzed by TEM-EDS to determine the Ba / Ga peak intensity ratio (I Ｂａ / I Ｇａ ) is 1.0 to 5.

0.

16. The method of claim 15, wherein the gallium (Ga) complex compound comprises gallium carboxylate in an ionic form.

17. The method for producing a multilayer ceramic capacitor according to claim 15, wherein the gallium (Ga) complex compound is mixed so that gallium (Ga) is 0.01 mol parts to 10 mol parts relative to 100 mol parts of the barium titanate-based main component powder.

18. The dielectric slurry is made of aluminum oxide (Al ２ O ３ ), silicon dioxide (SiO ２ ), magnesium oxide (MgO), vanadium oxide (V ２ O ５ ), manganese oxide (MnO ２ 16. The method for producing a multilayer ceramic capacitor according to claim 15, further comprising mixing a powder of a minor component including:

19. For 100 mol parts of the barium titanate-based main component powder, The aluminum oxide (Al ２ O ３ ) is mixed in 0.01 to 5 mole parts, The silicon dioxide (SiO ２ ) is mixed in 0.01 to 5 mole parts, The magnesium oxide (MgO) is mixed in an amount of 0.01 to 5 parts by mole, The vanadium oxide (V ２ O ５ ) is mixed in 0.01 to 5 mole parts, The manganese oxide (MnO ２ 19. The method for producing a multilayer ceramic capacitor according to claim 18, wherein 0.01 to 5 parts by mole of the above-mentioned is mixed.

20. The method for producing a multilayer ceramic capacitor according to claim 15, wherein the sintering is performed at a temperature of 1000°C to 1200°C.

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