Magnetic storage device

Abstract

To provide a magnetic storage device having excellent characteristics and reliability.SOLUTION: A magnetic storage device according to an embodiment includes first wiring 10 extending in a first direction, second wiring 20 provided on the upper layer side of the first wiring and extending in a second direction intersecting the first direction, a memory cell 30 provided between the first wiring and the second wiring, having a lower surface connected to the first wiring and an upper surface connected to the second wiring, and including a magnetoresistance effect element 31 and a switching element 36 stacked in a third direction intersecting the first and second directions, and a contact 40 having an upper surface connected to the second wiring, the upper surface of the contact being located higher than the upper surface of the memory cell.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE The present invention relates to a magnetic storage device. [Background technology]

[0002] 2. Description of the Related Art There has been proposed a magnetic memory device in which a plurality of memory cells, each of which includes a magnetoresistance effect element and a selector (switching element), are integrated on a semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2021 / 0257404 Summary of the Invention [Problem to be solved by the invention]

[0004] A magnetic storage device having excellent characteristics and reliability is provided. [Means for solving the problem]

[0005] A magnetic memory device according to an embodiment is a magnetic memory device comprising: a first wiring extending in a first direction; a second wiring provided on an upper layer side of the first wiring and extending in a second direction intersecting the first direction; a memory cell provided between the first wiring and the second wiring, having a lower surface connected to the first wiring and an upper surface connected to the second wiring, the memory cell including a magnetoresistive effect element and a switching element stacked in a third direction intersecting the first and second directions; and a contact having an upper surface connected to the second wiring, wherein the upper surface of the contact is located higher than the upper surface of the memory cell. [Brief description of the drawings]

[0006] [Figure 1] 2 is a planar pattern diagram seen from the Z direction, which diagrammatically illustrates the configuration of the magnetic memory device according to the first embodiment. FIG. [Diagram 2] 1 is a cross-sectional view perpendicular to the X direction, illustrating a schematic configuration of a magnetic memory device according to a first embodiment. [Diagram 3] 1 is a cross-sectional view perpendicular to the Y direction, illustrating a schematic configuration of a magnetic memory device according to a first embodiment. [Figure 4] 1 is a cross-sectional view perpendicular to the Y direction, illustrating a schematic configuration of a magnetic memory device according to a first embodiment. [Diagram 5] 1 is a cross-sectional view showing a schematic basic configuration of a magnetoresistive effect element of a magnetic memory device according to a first embodiment. [Figure 6A] 5A to 5C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing the magnetic memory device according to the first embodiment. [Figure 6B] 5A to 5C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing the magnetic memory device according to the first embodiment. [Figure 7A] 5A to 5C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing the magnetic memory device according to the first embodiment. [Figure 7B] 5A to 5C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing the magnetic memory device according to the first embodiment. [Figure 8A] 5A to 5C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing the magnetic memory device according to the first embodiment. [Figure 8B] 5A to 5C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing the magnetic memory device according to the first embodiment. [Figure 9] 11 is a planar pattern diagram seen from the Z direction, which diagrammatically illustrates the configuration of a magnetic memory device according to a second embodiment. FIG. [Figure 10] 11 is a cross-sectional view perpendicular to the X direction, illustrating a schematic configuration of a magnetic memory device according to a second embodiment. FIG. [Figure 11] 11 is a cross-sectional view perpendicular to the Y direction, illustrating a schematic configuration of a magnetic memory device according to a second embodiment. FIG. [Figure 12] 11 is a cross-sectional view perpendicular to the Y direction, illustrating a schematic configuration of a magnetic memory device according to a second embodiment. FIG. [Figure 13A]10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a magnetic memory device according to a second embodiment. [Figure 13B] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a magnetic memory device according to a second embodiment. [Figure 14A] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a magnetic memory device according to a second embodiment. [Figure 14B] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a magnetic memory device according to a second embodiment. [Figure 15A] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a magnetic memory device according to a second embodiment. [Figure 15B] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a magnetic memory device according to a second embodiment. [Figure 16A] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a magnetic memory device according to a second embodiment. [Figure 16B] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a magnetic memory device according to a second embodiment. [Figure 17A] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a magnetic memory device according to a second embodiment. [Figure 17B] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a magnetic memory device according to a second embodiment. [Figure 18A] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a magnetic memory device according to a second embodiment. [Figure 18B] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a magnetic memory device according to a second embodiment. [Figure 19] 11 is a cross-sectional view perpendicular to the Y direction, illustrating a schematic configuration of a magnetic memory device according to a third embodiment. FIG. [Figure 20] 11 is a cross-sectional view perpendicular to the Y direction, illustrating a schematic configuration of a magnetic memory device according to a third embodiment. FIG. [Figure 21A] 11A to 11C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a magnetic memory device according to a third embodiment. [Figure 21B]11A to 11C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a magnetic memory device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings.

[0008] (First embodiment) Fig. 1 is a planar pattern diagram seen from the Z direction, which diagrammatically illustrates the configuration of the magnetic memory device according to the first embodiment, i.e., Fig. 1 is a planar pattern diagram diagrammatically illustrating the planar patterns of each of a plurality of components included in the magnetic memory device.

[0009] Fig. 2 is a cross-sectional view perpendicular to the X direction, which shows a schematic configuration of the magnetic memory device according to this embodiment, and corresponds to the cross section along the line AA in Fig. 1. Fig. 3 is a cross-sectional view perpendicular to the Y direction, which shows a schematic configuration of the magnetic memory device according to this embodiment, and corresponds to the cross section along the line BB in Fig. 1. Fig. 4 is a cross-sectional view perpendicular to the Y direction, which shows a schematic configuration of the magnetic memory device according to this embodiment, and corresponds to the cross section along the line CC in Fig. 1. Note that in Figs. 3 and 4, the region below the memory cell 30 is omitted, but in reality, word lines 10 and the like are provided as in Fig. 2.

[0010] In addition, the X direction, the Y direction, and the Z direction shown in each drawing are directions that intersect with each other. Specifically, the X direction, the Y direction, and the Z direction are perpendicular to each other.

[0011] The magnetic memory device of this embodiment includes a plurality of word lines (first wirings) 10, a plurality of bit lines (second wirings) 20, a plurality of memory cells 30, a plurality of contacts 40, a plurality of lower wirings 50, and a plurality of insulating layers 61 to 66. Each of the above-mentioned components is provided on a semiconductor substrate (not shown).

[0012] The word lines 10 are arranged in the Y direction at the same pitch, and each extends in the X direction.

[0013] The plurality of bit lines 20 are provided on the upper layer side of the plurality of word lines 10, are arranged in the X direction at the same pitch, and each extends in the Y direction.

[0014] A plurality of memory cells 30 are arranged in the X direction and the Y direction. Each memory cell 30 is provided between a corresponding word line 10 and a corresponding bit line 20, and has a lower surface connected to the word line 10 and an upper surface connected to the bit line 20.

[0015] Each memory cell 30 includes a magnetoresistance effect element 31, a selector material layer (switching material layer) 32, a lower electrode 33, an upper electrode 34, and an intermediate electrode 35, and these components are stacked in the Z direction. The selector material layer 32, the lower electrode 33, and the intermediate electrode 35 essentially constitute a selector (switching element) 36, and the magnetoresistance effect element 31 is stacked on the upper layer side of the selector 36.

[0016] FIG. 5 is a cross-sectional view that illustrates a basic configuration of the magnetoresistance effect element 31. As shown in FIG.

[0017] The magnetoresistance effect element 31 is an MTJ (magnetic tunnel junction) element and includes a memory layer (first magnetic layer) 31a, a reference layer (second magnetic layer) 31b, and a tunnel barrier layer (non-magnetic layer) 31c, and has a structure in which the memory layer 31a, the reference layer 31b, and the tunnel barrier layer 31c are stacked in the Z direction.

[0018] The memory layer 31a is a ferromagnetic layer having a variable magnetization direction. The variable magnetization direction means that the magnetization direction changes with respect to a given write current. The reference layer 31b is a ferromagnetic layer having a fixed magnetization direction. The fixed magnetization direction means that the magnetization direction does not change with respect to a given write current. The tunnel barrier layer 31c is an insulating layer provided between the memory layer 31a and the reference layer 31b.

[0019] When the magnetization direction of the memory layer 31a is parallel to the magnetization direction of the reference layer 31b, the magnetoresistance effect element 31 exhibits a low resistance state having a relatively low resistance. When the magnetization direction of the memory layer 31a is antiparallel to the magnetization direction of the reference layer 31b, the magnetoresistance effect element 31 exhibits a high resistance state having a relatively high resistance. Therefore, the magnetoresistance effect element 31 can store binary data according to its resistance state.

[0020] In the example shown in FIG. 5, a bottom-free type magnetoresistance effect element in which the memory layer 31a is located below the reference layer 31b is shown, but a top-free type magnetoresistance effect element in which the memory layer 31a is located above the reference layer 31b may also be used.

[0021] The selector 36 is a two-terminal switching element, and is composed of a selector material layer 32, a lower electrode 33, and an intermediate electrode 35. For example, the selector material layer 32 is formed of silicon oxide doped with arsenic (As) or the like. The selector 36 has a characteristic of transitioning from an OFF state to an ON state when the voltage applied between the two terminals becomes equal to or higher than a threshold voltage. In Figs. 2 and 3, when the voltage applied between the lower electrode 33 and the intermediate electrode 35 becomes equal to or higher than the threshold voltage, the resistance value of the selector material layer 32 is significantly reduced, and the selector 36 transitions from an OFF state to an ON state.

[0022] When a voltage is applied between the word line 10 and the bit line 20 and the voltage applied to the selector 36 becomes equal to or higher than the threshold voltage, the selector 36 transitions from the OFF state to the ON state. As a result, a current flows through the magnetoresistance effect element 31 connected in series to the selector 36, making it possible to write to or read from the magnetoresistance effect element 31.

[0023] The contact 40 functions as a contact electrode for the bit line 20, is made of a metal material such as tungsten (W), and includes a first contact portion 41 and a second contact portion 42. The contact 40 has an upper surface connected to the bit line 20, and the upper surface of the contact 40 is located higher than the upper surface of the memory cell 30. The lower surface of the contact 40 is connected to the lower wiring 50. Therefore, a signal is transmitted between the memory cell 30 and the lower wiring 50 via the bit line 20 and the contact 40. Note that the contact 40 may be made of molybdenum (Mo), copper (Cu), or the like.

[0024] The maximum width of the contact 40 in the X direction is larger than the maximum width of the bit line 20 in the X direction. Strictly speaking, the maximum width of the contact 40 is larger than the maximum width of the bit line 20 in a direction perpendicular to the extension direction (Y direction) of the bit line 20. Therefore, a part of the pattern of the contact 40 is located outside the pattern of the bit line 20 when viewed from the Z direction.

[0025] As shown in FIG. 4, the contact 40 (first contact portion 41 in the illustrated example) includes an upper portion 40a including an upper surface connected to the bit line 20, and a lower portion 40b located below the upper portion 40a. When viewed from the Y direction, the side surface of the upper portion 40a of the contact 40 is aligned with the side surface of the bit line 20. At the boundary between the upper portion 40a of the contact 40 and the lower portion 40b of the contact 40, the width in the X direction of the upper portion 40a (strictly speaking, the width in the direction perpendicular to the Y direction) is smaller than the width in the X direction of the lower portion 40b (strictly speaking, the width in the direction perpendicular to the Y direction). Therefore, a step exists in the boundary region between the upper portion 40a and the lower portion 40b.

[0026] As already described, the upper surface of the contact 40 is located higher than the upper surface of the memory cell 30. Specifically, a recess 70 is provided in the region where the multiple memory cells 30 are arranged, and a part of the bottom surface of the recess 70 corresponds to the upper surface of the memory cell 30. Since the bit line 20 is connected to the upper surface of the memory cell 30 and the upper surface of the contact 40, the thickness of the bit line 20 at the position connected to the upper surface of the memory cell 30 is thicker than the thickness of the bit line 20 at the position connected to the upper surface of the contact 40.

[0027] Therefore, in terms of the thickness direction (height direction, Z direction) of the bit line 20, the bit line 20 includes an upper portion 21 and a lower portion 22. The upper portion 21 is provided over the entire extension direction (Y direction) of the bit line 20, and the lower portion 22 is provided within the recess 70. In other words, the upper portion 21 of the bit line 20 is located between a first plane including a connection surface between the contact 40 and the bit line 20 and the upper surface of the bit line 20, and the lower portion 22 of the bit line 20 is located between a second plane including a connection surface between the memory cell 30 and the bit line 20 and the first plane. In this embodiment, the upper portion 21 and the lower portion 22 of the bit line 20 are formed by a common patterning process. Therefore, when viewed from the Y direction, a pair of side surfaces of the lower portion 22 of the bit line 20 are aligned with a pair of side surfaces of the upper portion 21 of the bit line 20.

[0028] In this embodiment, the upper portion 21 and the lower portion 22 of the bit line 20 are formed of the same conductive material. Specifically, both the upper portion 21 and the lower portion 22 of the bit line 20 are formed of a metal material such as tungsten (W). Molybdenum (Mo) or copper (Cu) may be used instead of tungsten. Moreover, the word line 10 may also be formed of a metal material such as tungsten, molybdenum, or copper.

[0029] The insulating layers 61 to 66 function as interlayer insulating layers, etc. For example, the insulating layers 61, 63, 65 and 66 are made of silicon oxide, and the insulating layers 62 and 64 are made of silicon nitride.

[0030] Next, a method for manufacturing a magnetic memory device according to this embodiment will be described with reference to the cross-sectional views shown in Fig. 6A, and Fig. 6B to Fig. 8A and Fig. 8B, as well as Fig. 1 to Fig. 4. Fig. 6A to Fig. 8A are cross-sectional views taken at a position corresponding to the position of the cross section shown in Fig. 3, and Fig. 6B to Fig. 8B are cross-sectional views taken at a position corresponding to the position of the cross section shown in Fig. 4.

[0031] 6A and 6B, a structure including memory cells 30, contacts 40, insulating layers 61 and 62, etc. is formed on a lower structure (not shown) including a semiconductor substrate. The upper surface of the structure shown in Figures 6A and 6B is planarized, and the upper surface of contact 40 is exposed.

[0032] 7A and 7B, a part of the insulating layer 62 is etched. As a result, a recess 70 is formed in the region where the multiple memory cells 30 are arranged, and the upper surface of the memory cell 30 (the upper surface of the upper electrode 34) is exposed. The insulating layer 61 and the insulating layer 62 are formed of different materials. For example, the insulating layer 61 is formed of silicon oxide, and the insulating layer 62 is formed of silicon nitride. Therefore, the recess 70 can be formed by selectively etching the insulating layer 62 with respect to the insulating layer 61.

[0033] 8A and 8B, a metal layer (e.g., a tungsten layer) is formed as a conductive layer 20s for the bit line 20 on the structure obtained in the steps of Fig. 7A and 7B. Specifically, the conductive layer 20s is formed on the entire surface and then planarized by CMP (chemical mechanical polishing), thereby obtaining a conductive layer 20s having a planarized upper surface.

[0034] Thereafter, as shown in FIG. 3 and FIG. 4, the material of the conductive layer 20s is selectively etched to pattern the conductive layer 20s into a line shape, thereby forming a plurality of bit lines 20. At this time, the conductive layer 20s is thicker in the region where the memory cells 30 are provided (the region where the recesses 70 are provided) than in the region where the contacts 40 are provided. The conductive layer 20s is patterned so that the width of the bit lines 20 is smaller than the width of the contacts 40 when viewed from the Y direction. The bit lines 20 and the contacts 40 are formed of the same conductive material (metal material such as tungsten). Therefore, a part of the upper portion 40a of the contacts 40 is also etched, so that the side surface of the upper portion 40a of the contacts 40 is aligned with the side surface of the bit lines 20, and the width of the upper portion 40a of the contacts 40 is smaller than the width of the lower portion 40b of the contacts 40.

[0035] Furthermore, by forming an insulating layer 66, a magnetic memory device having the structure shown in FIGS. 1 to 4 is obtained.

[0036] As described above, in this embodiment, the upper surfaces of the contacts 40 are positioned higher than the upper surfaces of the memory cells 30. This makes it possible to obtain a magnetic memory device with excellent characteristics and reliability, as described below.

[0037] As already mentioned, since the width of the contact 40 is larger than the width of the bit line 20, it is important to ensure isolation between the contact 40 and the bit line 20 adjacent to the contact 40. Therefore, when forming the pattern of the bit line 20 by etching, it is preferable to reduce the width of the upper portion 40a of the contact 40 by overetching.

[0038] On the other hand, if excessive over-etching is performed at the location where the memory cell 30 is provided, the memory cell 30 may be damaged by etching, which may adversely affect the characteristics and reliability of the memory cell 30. In particular, when the magnetoresistance effect element 31 is stacked on the upper layer side of the selector 36, the characteristics and reliability of the magnetoresistance effect element 31 may be significantly degraded.

[0039] In this embodiment, the upper surface of the contact 40 is located higher than the upper surface of the memory cell 30. That is, the upper surface of the memory cell 30 is located lower than the upper surface of the contact 40. Therefore, even if the conductive layer 20s for the bit line 20 is sufficiently overetched in the region where the contact 40 is provided, the amount of overetching of the conductive layer 20s in the region where the memory cell 30 is provided can be appropriately suppressed.

[0040] Therefore, in this embodiment, the conductive layer 20s for the bit line 20 can be accurately etched in both the region where the contacts 40 are provided and the region where the memory cells 30 are provided, making it possible to obtain a magnetic memory device with excellent characteristics and reliability.

[0041] Second Embodiment Next, a magnetic storage device according to a second embodiment will be described. Note that the basic features are the same as those of the first embodiment, and therefore the description of the features described in the first embodiment will be omitted.

[0042] FIG. 9 is a planar pattern diagram showing a schematic configuration of the magnetic memory device according to this embodiment, as viewed from the Z direction.

[0043] Fig. 10 is a cross-sectional view perpendicular to the X direction, which shows a schematic configuration of the magnetic memory device according to this embodiment, and corresponds to the cross section taken along line AA in Fig. 9. Fig. 11 is a cross-sectional view perpendicular to the Y direction, which shows a schematic configuration of the magnetic memory device according to this embodiment, and corresponds to the cross section taken along line BB in Fig. 9. Fig. 12 is a cross-sectional view perpendicular to the Y direction, which shows a schematic configuration of the magnetic memory device according to this embodiment, and corresponds to the cross section taken along line CC in Fig. 9. Note that in Figs. 11 and 12, the region below the memory cell 30 is omitted, but in reality, word lines 10 and the like are provided in the same manner as in Fig. 10.

[0044] In the first embodiment, the upper portion 21 and the lower portion 22 of the bit line 20 are formed of the same conductive material, but in this embodiment, the upper portion 21 and the lower portion 22 of the bit line 20 are formed of different conductive materials. Specifically, in this embodiment, the upper portion 21 of the bit line 20 is formed of a metal material such as tungsten (W) as in the first embodiment. The lower portion 22 of the bit line 20 is formed of a conductive material containing carbon (C), ruthenium (Ru) or silicon (Si). More specifically, the lower portion 22 of the bit line 20 is formed of a conductive material containing carbon as a main component, a conductive material containing ruthenium as a main component, or a conductive material containing silicon as a main component. In this embodiment, the lower portion 22 of the bit line 20 is formed of a conductive material containing substantially only carbon.

[0045] Next, a manufacturing method of the magnetic memory device according to this embodiment will be described with reference to the cross-sectional views shown in Fig. 13A and Fig. 13B to Fig. 18A and Fig. 18B as well as Fig. 9 to Fig. 12. Fig. 13A to Fig. 18A are cross-sectional views taken at a position corresponding to the position of the cross section shown in Fig. 11, and Fig. 13B to Fig. 18B are cross-sectional views taken at a position corresponding to the position of the cross section shown in Fig. 12.

[0046] The processes of Figures 13A and 13B and the processes of Figures 14A and 14B are the same as the processes of Figures 6A and 6B and the processes of Figures 7A and 7B in the first embodiment, respectively, and as shown in Figures 14A and 14B, a recess 70 is formed in an area in which multiple memory cells 30 are arranged.

[0047] Next, as shown in FIGS. 15A and 15B, a carbon layer is formed as a conductive layer 22s for the lower portion 22 of the bit line 20 on the structure obtained by the steps of FIGS. 14A and 14B.

[0048] 16A and 16B, a planarization process is performed by CMP to planarize the upper surface of the conductive layer 22s. As a result of this planarization process, the conductive layer 22s remains only in the recesses 70.

[0049] Next, as shown in FIGS. 17A and 17B, a metal layer (eg, a tungsten layer) is formed as a conductive layer 21s for the upper portion 21 of the bit line 20 on the structure obtained by the steps of FIGS. 16A and 16B.

[0050] 18A and 18B, the material of the conductive layer 21s is selectively etched to pattern the conductive layer 21s into lines, thereby forming the upper portions 21 of the multiple bit lines 20. At this time, the etching is performed under conditions where the etching rate of the conductive layer 21s is sufficiently higher than the etching rate of the conductive layer 22s. As a result, in the region where the memory cells 30 are provided (the region where the recesses 70 are provided), the conductive layer 22s functions as an etching stopper, and the conductive layer 22s is hardly etched, and the conductive layer 21s is selectively etched.

[0051] On the other hand, in the region where the contact 40 is provided, as described in the first embodiment, the conductive layer 21s is patterned so that the width of the bit line 20 is smaller than the width of the contact 40 when viewed from the Y direction. Moreover, the upper portion 21 of the bit line 20 and the contact 40 are formed of the same metal material (e.g., tungsten). Therefore, a part of the upper portion 40a of the contact 40 is also etched, so that the side surface of the upper portion 40a of the contact 40 is aligned with the side surface of the upper portion 21 of the bit line 20, and the width of the upper portion 40a of the contact 40 is smaller than the width of the lower portion 40b of the contact 40.

[0052] 11 and 12, the material of the conductive layer 22s is selectively etched to form the lower portions 22 of the bit lines 20. At this time, since the upper portions 21 of the bit lines 20 function as an etching mask, a pair of side surfaces of the lower portions 22 of the bit lines 20 are aligned with a pair of side surfaces of the upper portions 21 of the bit lines 20 when viewed from the Y direction.

[0053] Furthermore, by forming an insulating layer 66, a magnetic memory device having a structure as shown in FIGS. 9 to 12 is obtained.

[0054] As described above, the basic structure of this embodiment is similar to that of the first embodiment, and the same effects as those of the first embodiment can be obtained in this embodiment. In addition, in this embodiment, the conductive material of the lower portion 22 of the bit line 20 is different from the conductive material of the upper portion 21 of the bit line 20, and when forming a pattern of the upper portion 21 of the bit line 20, the conductive layer 22s of the lower portion 22 of the bit line 20 functions as an etching stopper. Therefore, it is possible to more accurately suppress overetching of the bit line 20 in the region where the memory cell 30 is provided.

[0055] (Third embodiment) Next, a magnetic storage device according to a third embodiment will be described. Note that the basic features are similar to those of the first and second embodiments, and therefore the description of the features described in the first and second embodiments will be omitted.

[0056] A planar pattern diagram of the magnetic memory device according to this embodiment as viewed from the Z direction is similar to the planar pattern diagram of the second embodiment shown in Fig. 9. Also, a cross-sectional diagram perpendicular to the X direction of the magnetic memory device according to this embodiment (a cross-sectional diagram corresponding to a cross section along line AA in Fig. 9) is similar to the cross-sectional diagram of the second embodiment shown in Fig. 10.

[0057] Fig. 19 is a cross-sectional view perpendicular to the Y direction of the magnetic memory device according to this embodiment, and corresponds to the cross section taken along line BB in Fig. 9. Fig. 20 is a cross-sectional view perpendicular to the Y direction of the magnetic memory device according to this embodiment, and corresponds to the cross section taken along line CC in Fig. 9. Note that, although the region below the memory cell 30 is omitted in Figs. 19 and 20, word lines 10 and the like are actually provided in the same manner as in Fig. 10.

[0058] In this embodiment, similarly to the second embodiment, the upper portion 21 and the lower portion 22 of the bit line 20 are formed of different conductive materials. The conductive materials of the upper portion 21 and the lower portion 22 are similar to those in the second embodiment.

[0059] In this embodiment, a pair of sidewall layers 80 are provided along a pair of side surfaces of the upper portion 21 of the bit line 20. When viewed from the Y direction, a pair of side surfaces of the lower portion 22 of the bit line 20 are aligned with a pair of side surfaces of the pair of sidewall layers 80. The pair of sidewall layers 80 are formed of an insulating material such as silicon nitride.

[0060] Next, a method for manufacturing a magnetic memory device according to this embodiment will be described with reference to the cross-sectional views shown in Figures 21A and 21B as well as Figures 19 and 20. Figure 21A is a cross-sectional view taken at a position corresponding to the position of the cross section shown in Figure 19, and Figure 21B is a cross-sectional view taken at a position corresponding to the position of the cross section shown in Figure 20.

[0061] First, steps similar to those of the second embodiment shown in FIGS. 13A and 13B to 18A and 18B are performed to form a structure as shown in FIGS. 18A and 18B.

[0062] Next, as shown in Figures 21A and 21B, a pair of sidewall layers 80 are formed along a pair of side surfaces of the upper portion 21 of the bit line 20. Specifically, an insulating layer for the sidewall layer 80 is formed on the structure obtained in the steps of Figures 18A and 18B, and the formed insulating layer is etched by anisotropic etching such as RIE (reactive ion etching), thereby forming a pair of sidewall layers 80 along a pair of side surfaces of the upper portion 21 of the bit line 20. Note that in the region where the contact 40 is provided, the sidewall layer 80 is also formed on the side surfaces of the upper portion 40a of the contact 40, etc.

[0063] 19 and 20, the material of the conductive layer 22s is selectively etched to form the lower portions 22 of the bit lines 20. At this time, the upper portions 21 of the bit lines 20 and the pair of sidewall layers 80 function as an etching mask. Therefore, a pair of side surfaces of the lower portions 22 of the bit lines 20 are aligned with a pair of side surfaces of the pair of sidewall layers 80 when viewed from the Y direction.

[0064] Furthermore, by forming an insulating layer 66, a magnetic memory device having a structure as shown in FIGS. 9, 10, 19 and 20 is obtained.

[0065] As described above, the basic structure of this embodiment is similar to that of the first and second embodiments, and the same effects as those of the first and second embodiments can be obtained in this embodiment. In addition, in this embodiment, when the conductive layer 22s is etched to form the lower portion 22 of the bit line 20, a pair of sidewall layers 80 can protect a pair of side surfaces of the upper portion 21 of the bit line 20. For example, when carbon is used as the material of the conductive layer 22s, the conductive layer 22s is etched using oxygen gas. In such a case, by providing the sidewall layer 80, it is possible to suppress the upper portion 21 of the bit line 20 from being oxidized.

[0066] In the first to third embodiments described above, the magnetoresistance effect element 31 is laminated on the upper layer side of the selector 36, but the selector 36 may be laminated on the upper layer side of the magnetoresistance effect element 31.

[0067] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0068] 10...Word line (first wiring) 20: bit line (second wiring) 21: upper portion 22: lower portion 30... memory cell 31... magnetoresistance effect element 32...Selector material layer (switching material layer) 33...Lower electrode 34...Upper electrode 35...Intermediate electrode 36...Selector (switching element) 40: Contact 40a: Upper portion 40b: Lower portion 41: first contact portion; 42: second contact portion 50…Lower wiring 61, 62, 63, 64, 65, 66...Insulating layer 70: recess; 80: sidewall layer

Claims

1. A first wiring extending in a first direction; a second wiring provided on an upper layer side of the first wiring and extending in a second direction intersecting the first direction; a memory cell provided between the first wiring and the second wiring, having a lower surface connected to the first wiring and an upper surface connected to the second wiring, and including a magnetoresistance effect element and a switching element stacked in a third direction intersecting the first and second directions; a contact having an upper surface connected to the second wiring; A magnetic storage device comprising: The upper surface of the contact is located higher than the upper surface of the memory cell.

1. A magnetic storage device comprising:

2. The thickness of the second wiring at a position where the second wiring is connected to the upper surface of the memory cell is greater than the thickness of the second wiring at a position where the second wiring is connected to the upper surface of the contact.

2. The magnetic storage device according to claim 1.

3. The maximum width of the contact in a direction perpendicular to the second direction is greater than the maximum width of the second wiring in a direction perpendicular to the second direction.

2. The magnetic storage device according to claim 1.

4. the contact includes an upper portion having a side surface matching a side surface of the second wiring when viewed from the second direction, and a lower portion located below the upper portion; At a boundary between an upper portion of the contact and a lower portion of the contact, a width of the upper portion of the contact in a direction perpendicular to the second direction is smaller than a width of the lower portion of the contact in a direction perpendicular to the second direction.

2. The magnetic storage device according to claim 1.

5. The second wiring includes an upper portion located between a first plane including a connection surface between the contact and the second wiring and an upper surface of the second wiring, and a lower portion located between a second plane including a connection surface between the memory cell and the second wiring and the first plane.

2. The magnetic storage device according to claim 1.

6. When viewed from the second direction, a pair of side surfaces of a lower portion of the second wiring are aligned with a pair of side surfaces of an upper portion of the second wiring.

6. The magnetic storage device according to claim 5.

7. The upper portion of the second wiring is formed of a metal material.

6. The magnetic storage device according to claim 5.

8. The upper portion of the second wiring and the lower portion of the second wiring are formed of the same conductive material.

6. The magnetic storage device according to claim 5.

9. The upper portion of the second wiring and the lower portion of the second wiring are formed of different conductive materials.

6. The magnetic storage device according to claim 5.

10. The lower portion of the second wiring is formed of a conductive material containing carbon, ruthenium, or silicon.

10. The magnetic storage device according to claim 9.

11. A pair of sidewall layers are provided along a pair of side surfaces of the upper portion of the second wiring.

10. The magnetic storage device according to claim 9.

12. When viewed from the second direction, a pair of side surfaces of the lower portion of the second wiring are aligned with a pair of side surfaces of the pair of sidewall layers.

12. The magnetic storage device according to claim 11.

13. The magnetoresistive element is laminated on the upper layer side of the switching element.

2. The magnetic storage device according to claim 1.

14. The magnetoresistance effect element includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a non-magnetic layer provided between the first magnetic layer and the second magnetic layer.

2. The magnetic storage device according to claim 1.

15. The switching element is a two-terminal switching element and has a characteristic of transitioning from an off state to an on state when a voltage applied between the two terminals becomes equal to or higher than a threshold voltage.

2. The magnetic storage device according to claim 1.

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