Semiconductor structure and method for manufacturing the same

Abstract

To provide an innovative semiconductor structure and a method for manufacturing the same that improve the metal spillage and planarity problems that occur in the ohmic contact alloy process and increase process yields.SOLUTION: The present invention is a semiconductor structure 10 having a substrate 100, a channel layer 130, a barrier layer 140, a source electrode 150, a gate electrode 180, a drain electrode 160, and a cover layer 170. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source electrode, the gate electrode and the drain electrode are disposed on the barrier layer. The cover layer covers the areas other than the top of the source and drain electrodes.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates to semiconductor structures and methods of manufacture, and more particularly to High Electron Mobility Transistor (HEMT) structures and methods of manufacture. [Background technology]

[0002] In recent years, the demand for high-frequency and high-power products has been increasing. Gallium nitride-based semiconductor power components, such as aluminum gallium nitride / gallium nitride (AlGaN / GaN), can achieve very fast switching speeds due to their wide band gap and fast-moving electrons. They also operate at high frequencies, high power, and high temperatures, and are widely used in high-power semiconductor structures, especially for radio frequency and power applications. Traditionally, high-electron mobility transistors are made by stacking III-V semiconductors and forming heterojunctions at their interfaces. Since the energy band of the heterojunction is bent, a potential well is formed deep in the bend of the conduction band, and a two-dimensional electron gas (2DEG) is formed in the potential well.

[0003] Generally, high electron mobility transistors are normally-on (D-mode) or depletion mode devices, which require a negative bias voltage to turn off the device. In addition to being relatively inconvenient to use, the range of use of the device is also limited. Meanwhile, another enhancement-mode transistor with high electron mobility has also been proposed. This type of transistor is made by destroying the lattice structure of the aluminum gallium nitride layer by fluorine ion bombardment or etching to form a recess in the aluminum gallium nitride layer before forming a metal gate. This transistor does not require an additional bias voltage to turn off the normally-off (E-mode) device of the two-dimensional electron gas, because the gate stack structure of the P-type impurity gallium nitride layer exists in the epitaxial crystal at the bottom of the recess.

[0004] Currently, when manufacturing the above two types of semiconductor devices, titanium / aluminum is commonly used as the electrode material for the source and drain electrodes of the device. High-temperature heating is performed between these electrodes and an aluminum gallium nitride barrier layer to form an ohmic contact in the alloy between the electrode and gallium nitride. If the temperature of the alloy is too low, it is not easy to form an ohmic contact between the electrode and gallium nitride. On the other hand, if the temperature of the alloy is too high, the metal is likely to flow out due to the low melting point of aluminum in the electrode, which has a negative effect on the process yield. The dotted lines in Figure 1 show the lateral metal flow and the upward metal flow caused by high temperature in the process of forming an ohmic contact between the source and drain electrodes of a conventional HEMT device. Figure 1A is a microscope enlarged image of the lateral metal flow. If the metal flows out laterally during the process, it may cause a short circuit between the gate and the source during the subsequent formation of the gate electrode. On the other hand, Figure 1B is a microscope enlarged image of the upward metal flow. If metal flows out in the upward direction during the process, it adversely affects the flatness of the surface of the metal layer, which is detrimental to the subsequent metal lamination process.

[0005] In order to overcome the above problems, it has become an urgent task in the industry to develop an innovative semiconductor structure and a manufacturing method thereof that can improve the metal flow and flatness problems that occur in the ohmic contact alloy process and increase the process yield. Summary of the Invention

[0006] The main objective of the present invention is to provide an innovative semiconductor structure and a method for manufacturing the same that improves the metal flow and planarity problems that occur in the process of ohmic contact alloys in the manufacture of heterostructure field effect transistors, thereby improving the process yield.

[0007] In order to achieve the above object, the present invention provides a semiconductor structure including a substrate, a channel layer, a barrier layer, a source electrode, a gate electrode, a drain electrode, and a cover layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source electrode, the gate electrode, and the drain electrode are disposed on the barrier layer. The cover layer covers the source electrode and the drain electrode except for their upper portions.

[0008] In an embodiment of the present invention, the material of the source and drain electrodes of the semiconductor structure is one selected from the group consisting of titanium, aluminum, nickel, and gold.

[0009] In an embodiment of the present invention, the material of the cover layer of the semiconductor structure is one selected from the group consisting of silicon nitride, silicon dioxide, and silicon oxynitride.

[0010] In an embodiment of the present invention, the semiconductor device further includes a first metal layer disposed above the source electrode and the drain electrode and electrically connected to the source electrode and the drain electrode.

[0011] In an embodiment of the present invention, the semiconductor structure further includes a padding layer covering a portion of the barrier layer, the cover layer, the first metal layer, and the gate electrode, except for a top portion of the first metal layer.

[0012] In an embodiment of the present invention, the material of the padding layer of the semiconductor structure is one selected from the group consisting of silicon nitride, silicon dioxide, aluminum nitride, and silicon carbide.

[0013] In an embodiment of the present invention, the semiconductor structure further includes a through structure and a second metal layer sequentially disposed above the first metal layer and electrically connected to the first metal layer.

[0014] In an embodiment of the present invention, the material of the barrier layer of the semiconductor structure is aluminum indium gallium nitride (Al x In y Ga (1-x-y) N), where 0≦x<1, 0≦x+y≦1.

[0015] In an embodiment of the present invention, the semiconductor structure further comprises a two-dimensional electron gas located at the interface between the channel layer and the barrier layer.

[0016] In an embodiment of the present invention, the material of the substrate of the semiconductor structure is one selected from the group consisting of silicon, sapphire, and silicon carbide.

[0017] To achieve the above objectives, the present invention provides a semiconductor structure including a substrate, a channel layer, a barrier layer, a source electrode, a gate electrode, a drain electrode, and a conductive cover layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source electrode, the gate electrode, and the drain electrode are disposed on the barrier layer. The conductive cover layer covers the source electrode and the drain electrode.

[0018] In an embodiment of the present invention, the material of the conductive cover layer of the semiconductor structure is one selected from the group consisting of titanium nitride, titanium tungsten, titanium tungsten nitride, aluminum nitride, and graphite.

[0019] In an embodiment of the present invention, the semiconductor structure further includes a first metal layer disposed on the conductive cover layer above the source electrode and the drain electrode and electrically connected to the conductive cover layer, the source electrode, and the drain electrode.

[0020] In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor structure, including the steps of sequentially forming a channel layer and a barrier layer on a substrate, and forming a two-dimensional electron gas at the interface between the channel layer and the barrier layer, forming a source electrode and a drain electrode on the barrier layer, forming a cover layer covering the source electrode and the drain electrode, and heating the source electrode and the drain electrode to form ohmic contacts between the source electrode and the barrier layer and between the barrier layer and the barrier layer.

[0021] In an embodiment of the present invention, the method for manufacturing a semiconductor structure further includes forming a gate electrode on the barrier layer between the source electrode and the drain electrode, and forming a first metal layer in a region above the source electrode and the drain electrode, the first metal layer being electrically connected to the source electrode and the drain electrode.

[0022] In an embodiment of the present invention, the method for manufacturing a semiconductor structure further includes forming a padding layer covering the first metal layer, a portion of the barrier layer, the cover layer, and the gate electrode; removing a portion of the padding layer on the first metal layer to expose an upper region of the first metal layer; and high temperature annealing the exposed upper region of the first metal layer.

[0023] Those skilled in the art can understand other objects of the present invention, as well as the technical means and embodiments of the present invention, by referring to the drawings and the embodiments described below. [Brief description of the drawings]

[0024] [Figure 1] Schematic showing lateral and upward metal outflow in the source and drain electrodes of a conventional high electron mobility transistor. [Figure 1A]Microscopic magnification of lateral metal spillover in a conventional high electron mobility transistor. [Figure 1B] Microscopic magnification of upward metal flow in a conventional high electron mobility transistor [Diagram 2] 1 illustrates the steps of fabricating a semiconductor structure according to an embodiment of the present invention; [Diagram 3] 1 illustrates the steps of fabricating a semiconductor structure according to an embodiment of the present invention; [Figure 4] 1 illustrates the steps of fabricating a semiconductor structure according to an embodiment of the present invention; [Figure 5A] 1 illustrates the steps of fabricating a semiconductor structure according to an embodiment of the present invention; [Figure 5B] 1 illustrates the steps of fabricating a semiconductor structure according to an embodiment of the present invention; [Figure 6] 1 illustrates the steps of fabricating a semiconductor structure according to an embodiment of the present invention; [Figure 7] 1 illustrates the steps of fabricating a semiconductor structure according to an embodiment of the present invention; [Figure 8] 1 illustrates the steps of fabricating a semiconductor structure according to an embodiment of the present invention; [Figure 9] 1 illustrates the steps of fabricating a semiconductor structure according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] The contents of the present invention will be described below through examples. The examples of the present invention are examples of embodiments, and are not intended to limit the present invention to the environments, applications, or specific aspects described in the examples. Therefore, the explanation of the examples is for explaining the present invention, but does not limit the present invention. In the embodiments and drawings, components that are not directly related to the present invention are omitted and not shown. The dimensional relationship between the components in the drawings is for ease of understanding, and does not limit the actual dimensions.

[0026] FIG. 2 shows a semiconductor structure and a method for manufacturing the same according to an embodiment of the present invention. A nucleation layer 110, a buffer layer 120, a channel layer 130, and a barrier layer 140 are sequentially formed on a substrate 100. The material of the substrate 100 is silicon, sapphire, gallium nitride, silicon carbide, gallium arsenide, etc. The nucleation layer 110 is disposed on the substrate 100. The thickness of the nucleation layer 110 is about tens of nanometers to hundreds of nanometers, and the lattice difference between the substrate 100 and the barrier layer 140 can be reduced. The nucleation layer 110 is a III-V material including, for example, aluminum nitride, gallium nitride, aluminum gallium nitride, and other materials. The buffer layer 120 is disposed on the nucleation layer 110. The thickness of the buffer layer 120 is about several micrometers to tens of micrometers, and is made of a III-V material, which can similarly reduce the lattice difference between the substrate 100 and the barrier layer 140 and reduce the lattice difference. In this embodiment, the buffer layer 120 is a single layer or a multilayer structure, for example, a multilayer superlattice multilayer, or a single layer of III-V semiconductor material such as aluminum nitride, gallium nitride, or aluminum gallium nitride.

[0027] The channel layer 130 is formed on the buffer layer 120 and has a first energy gap. The barrier layer 140 is formed on the channel layer 130 and has a second energy gap. The second energy gap is higher than the first energy gap. The barrier layer 140 has a smaller lattice constant than the channel layer 130. In this embodiment, the material of the channel layer 130 and the barrier layer 140 is aluminum indium gallium nitride (Al x In y Ga (1-x-y)N), where 0≦x<1, 0≦x+y≦1. In this embodiment, the channel layer 130 is a gallium nitride layer, and the barrier layer 140 is an aluminum gallium nitride layer or an indium gallium nitride layer. A two-dimensional electron gas 132 is formed at the heterojunction between the channel layer 130 and the barrier layer 140 due to spontaneous polarization in the channel layer 130 and the barrier layer 140 and piezoelectric polarization between the channel layer 130 and the barrier layer 140.

[0028] As shown in FIG. 2, a source electrode 150 and a drain electrode 160 are formed on the barrier layer 140. The material of the source electrode and the drain electrode is one selected from the group consisting of titanium, aluminum, nickel, gold, and alloys thereof. Next, as shown in FIG. 3, a cover layer 170 is formed to cover the source electrode 150 and the drain electrode 160. The material of the cover layer 170 is a hard insulating dielectric material, or a hard conductive ceramic or metal material. For example, it is one selected from the group consisting of silicon nitride, silicon dioxide, silicon oxynitride, titanium nitride, titanium tungsten, titanium tungsten nitride, aluminum nitride, and graphite. The material of the cover layer 170 prevents lateral and upward metal outflow in the source electrode and the drain electrode in the subsequent high-temperature process of ohmic contact. Next, a high-temperature heat treatment is performed at a temperature of about 850° C. to form an ohmic contact between a metal alloy and a metal such as titanium or aluminum of the source electrode 150 and the drain electrode 160 and the barrier layer 140 of aluminum gallium nitride. In detail, since the source electrode 150 and the drain electrode 160 are covered by the cover layer 170, lateral metal outflow or upward metal outflow caused by melting or flowing of the electrodes in the semiconductor process does not occur even at high temperatures. In the subsequent manufacturing of the gate, the short circuit problem between the source electrode and the drain electrode can also be avoided. In addition, the occurrence of metal outflow above the source electrode and the drain electrode, which may adversely affect the flatness of the surface, can also be avoided, making the subsequent metal stacking process easier.

[0029] In a specific embodiment, an insulating ion implantation process is then performed between the elements on the wafer to destroy any two-dimensional electron gas that may be present between the elements to ensure insulation between the elements. Specifically, a boron ion beam is used for the insulating ion implantation. The boron ion concentration is 1E15 / cm. 3 The energy of the ion implantation is controlled to about 180 Kev. As shown in FIG. 4, the step of forming a gate electrode is next performed. The gate electrode 180 is formed on the barrier layer 140 between the source electrode 150 and the drain electrode 160. In a preferred embodiment of the present invention, a field plate 182 may be added to the gate structure to effectively increase the breakdown voltage and reduce the gate leakage current. Again, in the semiconductor structure disclosed in the present invention, the periphery of the source electrode 150 and the drain electrode 160 is covered by the cover layer 170, so that lateral metal outflow can be avoided when performing the subsequent high temperature alloy process of the ohmic contact. As a result, the short circuit problem between the lateral metal outflow and the gate electrode is avoided, and the process yield is improved.

[0030] Next, a metal lamination process is performed on the source electrode and the drain electrode. The metal lamination process varies depending on the conductivity of the cover layer. As shown in FIG. 5A, when the cover layer 170 is an insulating dielectric material such as silicon nitride, silicon dioxide, silicon oxynitride, etc., as mentioned above, before performing the metal lamination process, a part of the cover layer 170 above the source electrode 150 and the drain electrode 160 is removed in advance to expose the upper regions of the source electrode 150 and the drain electrode 160, respectively. Then, a first metal layer 190 is formed on the upper regions of the source electrode 150 and the drain electrode 160. The lamination height of the first metal layer 190 should be higher than the height of the field effect board 182 and the gate electrode 180. This can prevent the gate electrode from being damaged in the subsequent planarization process. The material of the first metal layer 190 includes aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, tantalum carbide, tantalum silicon nitride, tantalum carbonitride, titanium aluminide, aluminum titanium nitride, metal alloy, or other suitable conductive materials. On the other hand, as shown in FIG. 5B, when the cover layer 170 is a conductive material such as the above-mentioned titanium nitride, titanium tungsten, titanium tungsten nitride, aluminum nitride, graphite, etc., since the cover layer 170 has conductivity and is a conductive cover layer, when performing the metal lamination process, there is no need to remove the cover layer 170 on the source electrode 150 and the drain electrode 160 in advance, and the first metal layer 190 can be formed directly on the cover layer 170 on the source electrode 150 and the drain electrode 160. Similarly, the lamination height of the first metal layer 190 must be higher than the height of the field effect board 182 and the gate electrode 180.

[0031] Although the above process may differ depending on the conductivity of the cover layer 170, the process of the semiconductor structure of the present invention is generally the same. For the sake of simplicity, the following embodiment will be described in which the cover layer 170 is insulating. Those skilled in the art should be able to easily deduce specific embodiments in which the cover layer 170 is conductive from the above disclosure of the present invention. Therefore, the description thereof is omitted.

[0032] As shown in FIG. 6, a padding layer 200 is formed to cover the first metal layer 190, a part of the barrier layer 140, the cover layer 170, and the gate electrode 180. Then, as shown in FIG. 7, an inner dielectric layer 210 is formed to cover the entire wafer surface, and then a planarization process is performed. Specifically, as shown in FIG. 8, the planarization process uses the padding layer 200 above the first metal layer 190 as a stop layer, and removes the padding layer 200 on the first metal layer 190 by chemical mechanical polishing or etch-back to expose the upper region of the first metal layer 190. Specifically, the height of the metal stack of the first metal layer 190 is higher than the height of the gate electrode 180 and the field effect board 182, and the above-mentioned planarization process stops at the padding layer 200 above the first metal layer 190, so that the planarization process does not damage the gate electrode 180 and the field effect board 182. Then, the upper region of the first metal layer 190 is planarized by a high-temperature annealing process. In a preferred embodiment, the surface flatness of the top region of the high temperature annealed first metal layer 190 is less than 0.1 micrometers, which facilitates subsequent metal build-up processes.

[0033] Next, as shown in FIG. 9, the metal stack of the electrodes is connected to each other. A dielectric layer 220 is formed on the padding layer 200. Next, a through structure 230 is formed in the dielectric layer 220. Finally, a second metal layer 240 is formed, which is electrically connected to the through structure 230 and the first metal layer 190. The second metal layer 240 is electrically connected to the source electrode 150 and the drain electrode 160, respectively. In this way, the semiconductor structure 10 of the present invention is completed. The materials of the through structure 230 and the second metal layer 240 may be the same as the materials of the first metal layer 190, but the description thereof will be omitted.

[0034] The above description is merely an example of an embodiment of the present invention. The above-mentioned structure disclosed in the present invention can be applied to normally open type or normally off type elements of high electron mobility transistors, for example, a Schottky gate structure commonly found in normally open type elements, a metal-insulator-semiconductor gate structure, or a recess gate structure commonly found in normally off type elements, and a p-type doped gallium nitride gate (pGaN gate) structure. When manufacturing these various gate structures, the isolation function of the above-mentioned cover layer 170 of the present invention can be applied. During the manufacturing process of these elements, it is possible to prevent a short circuit between the source electrode and the gate electrode due to lateral metal outflow from the source electrode. In the subsequent metal lamination process, the flatness of the metal electrode surface can also be ensured, improving the process yield.

[0035] The above examples are for explaining the embodiments of the present invention and for explaining the characteristic configuration of the present invention. The present invention is not limited to the above examples. Modifications or equivalent arrangements that can be easily made by those skilled in the art are also within the scope of the present invention. The scope of protection of the rights of the present invention is based on the claims. [Explanation of symbols]

[0036] 10 Semiconductor Structure 100 Substrates 110 Nucleation layer 120 Buffer Layer 130 Channel Layer 132 Two-dimensional electron gas 140 Barrier Layer 150 Source Electrode 160 Drain electrode 170 Cover Layer 180 Gate electrode 182 Field Effect Board 190 1st metal layer 200 padding layers 210 Inner dielectric layer 220 Dielectric layer 230 Communication structure 240 2nd metal layer

Claims

1. 1. A semiconductor structure comprising: A substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a source electrode, a gate electrode, and a drain electrode disposed on the barrier layer; a cover layer; The cover layer covers all but the top portions of the source electrode and the drain electrode.

2. 2. The semiconductor structure of claim 1, wherein the material of the source electrode and the drain electrode is one selected from the group consisting of titanium, aluminum, nickel, and gold.

3. 2. The semiconductor structure of claim 1, wherein the material of the cover layer is one selected from the group consisting of silicon nitride, silicon dioxide, and silicon oxynitride.

4. 2. The semiconductor structure of claim 1, further comprising a first metal layer disposed above and electrically connected to said source electrode and said drain electrode.

5. 5. The semiconductor structure of claim 4, further comprising a padding layer covering a portion of the barrier layer, the cover layer, the first metal layer, and the gate electrode except for a top portion of the first metal layer.

6. 6. The semiconductor structure of claim 5, wherein the material of the padding layer is one selected from the group consisting of silicon nitride, silicon dioxide, aluminum nitride, and silicon carbide.

7. 5. The semiconductor structure of claim 4, further comprising a through structure and a second metal layer disposed sequentially above the first metal layer and electrically connected to the first metal layer.

8. 10. The semiconductor structure of claim 1 further comprising a two-dimensional electron gas located at an interface between said channel layer and said barrier layer.

9. The material of the barrier layer is aluminum indium gallium nitride (Al ｘ In ｙ G （１－ｘ－ｙ） N), where 0≦x<1, 0≦x+y≦1.

10. 2. The semiconductor structure of claim 1, wherein the material of the substrate is one selected from the group consisting of silicon, sapphire, and silicon carbide.

11. 1. A semiconductor structure comprising: A substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a source electrode, a gate electrode, and a drain electrode disposed on the barrier layer; a conductive cover layer; The conductive cover layer covers the source electrode and the drain electrode.

12. 12. The semiconductor structure of claim 11, wherein the material of the conductive cover layer is a member selected from the group consisting of titanium nitride, titanium tungsten, titanium tungsten nitride, aluminum nitride, and graphite.

13. 12. The semiconductor structure of claim 11, further comprising a first metal layer disposed on the conductive cover layer over the source electrode and the drain electrode and electrically connected to the conductive cover layer, the source electrode, and the drain electrode.

14. 1. A method for manufacturing a semiconductor structure, comprising the steps of: Sequentially forming a channel layer and a barrier layer on a substrate, and forming a two-dimensional electron gas at an interface between the channel layer and the barrier layer; forming a source electrode and a drain electrode on the barrier layer; forming a cover layer covering the source electrode and the drain electrode; and heating the source and drain electrodes to form ohmic contacts between the source and drain electrodes and the barrier layer.

15. forming a gate electrode on the barrier layer between the source electrode and the drain electrode; 15. The method of claim 14, further comprising forming a first metal layer in an area above the source electrode and the drain electrode, the first metal layer being electrically connected to the source electrode and the drain electrode.

16. forming a padding layer covering the first metal layer, a portion of the barrier layer, the cover layer, and the gate electrode; removing a portion of the padding layer over the first metal layer to expose an upper region of the first metal layer; 16. The method of claim 15, further comprising: high temperature annealing the exposed upper region of the first metal layer.

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