Storage device and manufacturing method for storage device

Abstract

To provide a storage device with smaller variation in electrical characteristics.SOLUTION: In a storage device, a first structure 100 includes a substrate 21 of a semiconductor such as silicon, a MOS transistor Tr, a conductor set 22, and an insulator 23. The insulator 23 is provided in a region from an upper surface of the substrate 21 to an upper surface of a bonded pad PD1. The transistor Tr is located in a region including the upper surface of the substrate 21 and on the upper surface. The conductor set 22 includes a plurality of conductors. The conductors that are adjacent along a Z direction are in contact with each other, and at an upper end, are bonded to the bonded pad PD1. A second structure 200 includes a cell region CA and a peripheral region PA. The cell region is a region including a memory cell transistor. The peripheral region is a region not including the memory cell transistor. The peripheral region surrounds the cell region CA when the storage device is viewed in a -Z direction. In the second structure 200, in the cell region, a conductor set 26 and the plurality of conductors and the plurality of insulators are arranged alternately.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE FIELD Embodiments generally relate to memory devices and methods for manufacturing memory devices. [Background technology]

[0002] A memory device in which memory cells are arranged in three dimensions is known. In order to increase the memory capacity of the memory device, the components of the memory device are being miniaturized. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-25878 A Summary of the Invention [Problem to be solved by the invention]

[0004] A storage device with small variations in electrical characteristics is provided. [Means for solving the problem]

[0005] A memory device according to an embodiment includes a plurality of first conductors, a plurality of first insulators, a plurality of second insulators, a memory pillar, a second conductor, a first film, and a second film. The plurality of first insulators alternate with the plurality of first conductors one by one in a first region in a first direction. The plurality of second insulators alternate with the plurality of first insulators one by one in a second region in the first direction. The memory pillar includes a film that penetrates the plurality of first conductors and the plurality of first insulators in the first region and surrounds a semiconductor and a side surface of the semiconductor. The semiconductor has a groove at an end on a side of the first direction. The second conductor contacts a first surface of the memory pillar on the side of the first direction, includes a first portion and a second portion connected to the first portion, and includes a portion located in the groove and contacts the semiconductor at a side surface of the second portion. The first film extends along the first direction in the second region. The second film extends along the first direction and is in contact with the first film. At least one of the second insulators includes a portion extending along the first film and the second film in the second region. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 shows an example of components of a storage device according to a first embodiment and connections between the components. [Diagram 2] FIG. 2 shows components and connections of the components in one block of the storage device of the first embodiment. [Diagram 3] FIG. 3 shows a schematic diagram of the basic structure of the storage device of the first embodiment. [Figure 4] FIG. 4 illustrates an example of a cross-sectional structure of a portion of the memory device of the first embodiment. [Diagram 5] FIG. 5 shows an example of the cross-sectional structure of a memory pillar of the storage device of the first embodiment. [Figure 6] FIG. 6 shows an example of a cross-sectional structure of a portion of the memory device of the first embodiment. [Figure 7] FIG. 7 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 8]FIG. 8 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 9] FIG. 9 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 10] FIG. 10 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 11] FIG. 11 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 12] FIG. 12 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 13] FIG. 13 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 14] FIG. 14 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 15] FIG. 15 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 16] FIG. 16 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 17] FIG. 17 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 18] FIG. 18 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 19] FIG. 19 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 20] FIG. 20 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 21] FIG. 21 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 22] FIG. 22 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 23] FIG. 23 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 24] FIG. 24 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Diagram 25] FIG. 25 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 26] FIG. 26 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 27] FIG. 27 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 28] FIG. 28 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Figure 29] FIG. 29 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device of the first embodiment. [Diagram 30] FIG. 30 illustrates an example of a cross-sectional structure of a portion of the memory device of the second embodiment. [Diagram 31] FIG. 31 shows an example of a cross-sectional structure of a portion of the memory device of the second embodiment. [Diagram 32] FIG. 32 shows an example of a cross-sectional structure of a portion during the manufacture of the memory device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In an embodiment or different embodiments, a plurality of components having substantially the same functions and configurations may be distinguished from each other by adding an additional number or letter to the end of the reference numeral. In the embodiment following a certain described embodiment, the differences from the described embodiment will be mainly described. All descriptions of one embodiment are applicable to the description of another embodiment, unless expressly or obviously excluded.

[0008] The drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, the drawings may include parts with different dimensional relationships, arrangements, and / or ratios.

[0009] 1. First embodiment 1.1.Configuration (Structure) 1 shows an example of components and connections of the components of a storage device according to a first embodiment. The storage device 1 is a device that uses memory cells to store data. The storage device 1 is controlled by an external memory controller. The storage device 1 operates based on a command CMD and address information ADD received from, for example, the memory controller. The storage device 1 receives data DAT to be written and outputs data stored in the storage device 1.

[0010] The memory device 1 includes components such as a memory cell array 10, a row decoder 11, a register 12, a sequencer 13, a voltage generating circuit 14, a driver 15, and a sense amplifier 17.

[0011] The memory cell array 10 is a set of arranged memory cells. The memory cell array 10 includes a plurality of memory blocks (blocks) BLK. Each block BLK includes a plurality of memory cell transistors MT (not shown). The memory cell array 10 also includes wiring such as word lines WL (not shown) and bit lines BL (not shown).

[0012] The row decoder 11 is a circuit for selecting a block BLK. The row decoder 11 transfers a voltage supplied from a driver 15 to one block BLK selected based on a block address received by the row decoder 11 from a register 12.

[0013] The register 12 is a circuit that holds the command CMD and address information ADD received by the memory device 1. The command CMD instructs the sequencer 13 to perform various operations including data read, data write, and data erase. The address information ADD specifies the target of access in the memory cell array 10.

[0014] The sequencer 13 is a circuit that controls the overall operation of the memory device 1. Based on a command CMD received by the sequencer 13, the sequencer 13 controls the row decoder 11, the driver 15, and the sense amplifier 17 to execute various operations including data read, data write, and data erase.

[0015] The voltage generation circuit 14 is a circuit that generates a plurality of voltages of different magnitudes. The voltage generation circuit 14 receives a power supply voltage from outside the memory device 1 and generates a plurality of voltages from the power supply voltage. The voltage generation circuit 14 supplies the generated voltages to components such as the memory cell array 10, the driver 15, and the sense amplifier 17.

[0016] The driver 15 is a circuit that applies various voltages required for the operation of the memory device 1 to several components. The driver 15 receives a plurality of voltages from the voltage generating circuit 14 and supplies a selected one of the plurality of voltages to one or more row decoders 11.

[0017] The sense amplifier 17 is a circuit that outputs a signal based on the data stored in the memory cell array 10. The sense amplifier 17 senses the state of the memory cell transistor MT and generates read data based on the sensed state. The sense amplifier 17 applies a voltage based on the write data to the bit line BL.

[0018] 1.1.1.Memory Cell Array 2 shows components and connections of components in one block of the storage device of the first embodiment. A plurality of blocks BLK, for example, all blocks BLK, include the components and connections shown in FIG.

[0019] One block BLK includes a plurality of string units SU. Fig. 2 shows an example of five string units SU_0 to SU_4.

[0020] 2, m bit lines BL_0 to BL_m-1 are each connected to one NAND string NS from each of the string units SU_0 to SU_4 in each block BLK, where m is a positive integer.

[0021] Each NAND string NS includes one select gate transistor ST, n memory cell transistors MT (MT_0 to MT_n-1), and one select gate transistor DT (DT0, DT1, DT2, DT3, or DT4), where n is a positive integer. The memory cell transistor MT is an element that stores data in a non-volatile manner. The memory cell transistor MT includes a control gate electrode or a gate electrode (word line WL), and a charge storage film insulated from the surroundings, and stores data in a non-volatile manner based on the charge in the charge storage film. Data is written to the memory cell transistor MT by injecting electrons into the charge storage film.

[0022] The select gate transistor ST, the memory cell transistors MT_0 to MT_n-1, and the select gate transistor DT are connected in series in this order between a source line SL and one bit line BL.

[0023] A plurality of NAND strings NS respectively connected to different bit lines BL constitute one string unit SU. In each string unit SU, the control gate electrodes of memory cell transistors MT_0 to MT_n-1 are respectively connected to word lines WL_0 to WL_n-1. A set of memory cell transistors MT sharing a word line WL in one string unit SU is called a cell unit CU.

[0024] The select gate transistors DT0 to DT4 belong to the string units SU_0 to SU_4, respectively. In FIG. 2, the select gate transistors DT2, DT3, and DT4 are omitted from the illustration. The gate of the select gate transistor DT0 of each of the multiple NAND strings NS of the string unit SU_0 is connected to a select gate line SGDL0. Similarly, the gates of the select gate transistors DT1, DT2, DT3, and DT4 of each of the multiple NAND strings NS of the string units SU_1, SU_2, SU_3, and SU_4 are connected to select gate lines SGDL1, SGDL2, SGDL3, and SGDL4.

[0025] The gate of the select gate transistor ST is connected to a select gate line SGSL.

[0026] 1.1.2. Basic Structure of Storage Device FIG. 3 is a schematic diagram showing a basic structure of a storage device according to a first embodiment. As shown in FIG. 3, the storage device 1 includes a first structure 100 and a second structure 200 aligned along the Z axis. The first structure and the second structure extend along a certain plane. The plane along which the first structure and the second structure extend is called the XY plane. The XY plane is made up of an X axis and a Y axis that are perpendicular to each other. The direction along the X axis is called the X direction or +X direction. The direction along the Y axis is called the Y direction or +Y direction. The direction perpendicular to the XY plane and extending from the first structure 100 to the second structure 200 is called the Z direction or +Z direction.

[0027] The first structure 100 and the second structure 200 are manufactured separately and then bonded to each other. Specifically, a structure that is inverted with respect to the XY plane of the second structure 200 is formed, and the formed structure is inverted with respect to the XY plane to bond the first structure 100 and the second structure 200. For the sake of ease of understanding, Fig. 3 shows the state before bonding.

[0028] The first structure 100 includes a plurality of conductive bonding pads BP1. The second structure 200 includes a plurality of conductive bonding pads BP2. Each bonding pad BP1 of the first structure 100 faces one bonding pad BP2 of the second structure 200. As a result of bonding the first structure 100 and the second structure 200, each bonding pad BP1 of the first structure contacts one bonding pad BP2 of the second structure 200.

[0029] In one example, the first structure 100 includes structures that function as components of a memory cell array 10. In one example, the second structure 200 includes structures that function as components of a row decoder 11, a register 12, a sequencer 13, a voltage generation circuit 14, a driver 15, and a sense amplifier 17.

[0030] 1.1.3. Structure of the storage device FIG. 4 is a schematic diagram showing an example of a cross-sectional structure of a portion of the storage device of the first embodiment. FIG. 4 shows a structure along the XZ plane. A portion of the structure shown in FIG. 4 will be described in detail later. In the description of FIG. 4, the Z direction points up, the -Z direction points down, the Y direction points right, and the -Y direction points left.

[0031] As shown in FIG. 4, the first structure 100 further includes a substrate 21 of a semiconductor such as silicon, a MOS (Metal Oxide Semiconductor) transistor Tr, a set of conductors 22, and an insulator 23.

[0032] The transistor Tr is located in a region including the upper surface of the substrate 21 and on the upper surface. The conductor set 22 includes a plurality of conductors. The conductors adjacent to each other along the Z direction in the conductor set 22 are in contact with each other. The conductor set 22 is connected to the bonding pad PD1 at the upper end.

[0033] In the first structure 100, an area from the upper surface of the substrate 21 to the upper surface of the bonding pad PD1 is provided with an insulator 23. In one example, the insulator 23 includes silicon oxide.

[0034] The second structure 200 includes a cell area CA and a peripheral area PA. The cell area CA is an area that includes memory cell transistors MT. The peripheral area PA is an area that does not include memory cell transistors MT. The peripheral area PA surrounds the cell area CA when the memory device 1 is viewed in the -Z direction.

[0035] The second structure 200 further includes conductor set 26, conductor 27, conductor 28, conductor 31, insulator 30, insulator 32, conductor 33, insulator 34, insulator 36, conductor 38, insulator 39, insulator 41, conductor 42, insulator 43, insulator 45, conductor 46, and conductor 47 in the cell area CA.

[0036] The lower surface of the bonding pad PD2 is in contact with the upper surface of the bonding pad PD1.

[0037] The conductor set 26 includes a plurality of conductors. The conductors adjacent to each other along the Z direction in the conductor set 26 are in contact with each other. The lower surface of the conductor set 26 is connected to the upper surface of one of the bonding pads PD2.

[0038] Each conductor 27 is disposed on the top surface of one conductor set 26. The conductor 27 functions as one bit line BL. In one example, the conductor 27 includes tungsten. Each conductor 28 is disposed on the top surface of the conductor 27.

[0039] The conductor 31 is disposed above the layer of conductors 28 in the cell area CA. The conductor 31 extends along the XY plane and has a plate-like shape. The conductor 31 functions as at least a part of the select gate line SGDL. In one example, the conductor 31 includes tungsten. The conductor 31 may include an additional conductor, such as aluminum oxide, on the surface.

[0040] The insulator 30 is disposed in a region from the lower surface of the second structure 200 to the conductor 31. The insulator 30 extends across the cell region CA and the peripheral region PA. In one example, the insulator 30 includes silicon oxide.

[0041] The insulator 32 is disposed on the upper surface of the conductor 31. The insulator 32 extends along the XY plane and has a plate-like shape. The insulator 32 extends across the cell area CA and the peripheral area PA. In one example, the insulator 32 includes silicon oxide.

[0042] The plurality of conductors 33 and the plurality of insulators 34 are alternately arranged one by one along the Z direction on the upper surface of the insulator 32 in the cell region CA. Thus, the conductors 33 are arranged along the Z direction, separated from each other or spaced apart. The conductors 33 and the insulators 34 extend along the XY plane and have a plate-like shape. Each conductor 33 functions as at least a part of the word line WL. In one example, the conductor 33 includes tungsten. The conductor 33 may include an additional conductor, such as aluminum oxide, on the surface. In one example, the insulator 34 includes silicon oxide.

[0043] The insulator 36 is disposed on the upper surface of the uppermost conductor 33. The insulator 36 extends along the XY plane and has a plate-like shape. The insulator 36 extends across the cell region CA and the peripheral region PA. In one example, the insulator 36 includes silicon oxide. The insulator 36 includes a recess 361 and a protrusion 362 in the peripheral region PA. The recess 361 is recessed in the Z direction. The protrusion 362 is located above the recess 361.

[0044] The plurality of conductors 38 and the plurality of insulators 39 are alternately arranged one by one along the Z direction on the upper surface of the insulator 36 in the cell region CA. Thus, the conductors 38 are arranged along the Z direction, separated from each other or spaced apart. The conductors 38 and the insulators 39 extend along the XY plane and have a plate-like shape. Each conductor 38 functions as at least a part of the word line WL. In one example, the conductors 38 include tungsten. The conductors 38 may include an additional conductor, such as aluminum oxide, on the surface. In one example, the insulators 39 include silicon oxide.

[0045] The insulator 41 is disposed on the upper surface of the uppermost conductor 38. The insulator 41 extends along the XY plane and has a plate-like shape. The insulator 41 extends across the cell area CA and the peripheral area PA. In one example, the insulator 41 includes silicon oxide.

[0046] The conductor 42 is disposed on the upper surface of the insulator 41. The conductor 42 extends along the XY plane and has a plate-like shape. The conductor 42 functions as at least a part of the select gate line SGSL. In one example, the conductor 42 includes tungsten. The conductor 42 may include an additional conductor, such as aluminum oxide, on the surface.

[0047] The insulator 43 is disposed on the upper surface of the conductor 42. The insulator 43 extends along the XY plane and has a plate-like shape. The insulator 43 extends across the cell area CA and the peripheral area PA. In one example, the insulator 43 includes silicon oxide.

[0048] The memory pillar MP is disposed in the cell region CA. The memory pillar MP extends along the Z direction and has a pillar shape. The memory pillar MP is disposed in a stacked structure consisting of conductors 31, 33, 38, and 42 and insulators 30, 32, 34, 36, 39, 41, and 43. The memory pillar MP penetrates the set of conductors 31, 33, 38, and 42 and insulators 30, 32, 34, 36, 39, 41, and 43. The memory pillar MP has a lower surface located in the insulator 30.

[0049] Each memory pillar MP includes a memory pillar LMP and a memory pillar UMP. The lower surface of the memory pillar LMP is in contact with the upper surface of the memory pillar UMP. The memory pillar LMP penetrates the set of conductors 38 and 42 and insulators 36, 39, 41, and 43. The memory pillar LMP has an upper surface located in the insulator 45 and a lower surface located in the insulator 36. The memory pillar UMP penetrates the set of conductors 31 and 33 and insulators 30, 32, 34, and 36. The memory pillar UMP has a lower surface located in the insulator 30.

[0050] Each of the memory pillars LMP and UMP has an XY area that decreases from the bottom surface to the top surface. The XY area is the area of ​​the surface along the XY plane. The XY area of ​​the bottom surface of the memory pillar LMP is larger than the XY area of ​​the top surface of the memory pillar UMP. Therefore, the side surface of the memory pillar LMP is offset from and does not coincide with the extension line of the side surface of the memory pillar UMP. Therefore, the XY area of ​​the memory pillar MP changes continuously with the change in position on the Z axis in the Z direction, while it changes discontinuously before and after the position of the boundary between the memory pillars LMP and UMP. The offset between the side surface of the memory pillar LMP and the extension line of the side surface of the memory pillar UMP occurs not only in the XZ cross section shown in FIG. 4, but also in other cross sections including the Z axis.

[0051] Each memory pillar MP includes a core 50, a semiconductor 51, and a stack 52. The core 50 extends along the Z direction and has a pillar shape. The side of the core 50 extends along the side of the memory pillar MP. That is, the core 50 includes a portion included in the memory pillar LMP and a portion included in the memory pillar UMP. The lower surface of the portion of the core 50 included in the memory pillar LMP and the upper surface of the portion of the core 50 included in the memory pillar UMP are connected. Each of the portion of the core 50 included in the memory pillar LMP and the portion of the core 50 included in the memory pillar UMP has an XY area that decreases from the lower surface to the upper surface. In one example, the core 50 includes silicon oxide.

[0052] The semiconductor 51 covers the surface of the core 50. The side surface of the semiconductor 51 extends along the side surface of the memory pillar MP. In one example, the semiconductor 51 includes silicon. The semiconductor 51 has a groove 511 at the top. The groove 511 extends along the Z direction. The upper end of the groove 511 reaches above the top surface of the insulator 43. The top of the semiconductor 51 extends along the XY plane above the insulator 43. The structure of the top of the semiconductor 51 will be described in detail later with reference to FIG. 6.

[0053] The stacked body 52 covers the side surface of the semiconductor 51. The side surface of the stacked body 52 extends along the side surface of the memory pillar MP. The top surface of the stacked body 52 is located above the upper surface of the insulator 43.

[0054] A portion where the memory pillar MP and the conductor 31 face each other functions as a select gate transistor DT. A portion where the memory pillar MP and one of the conductors 33 or 38 face each other functions as one memory cell transistor MT. A portion where the memory pillar MP and the conductor 42 face each other functions as one select gate transistor DT. A plurality of conductors 31 may be provided, and the portions where the plurality of conductors 31 and the memory pillar MP face each other may function as a plurality of select gate transistors DT connected in series. A plurality of conductors 42 may be provided, and the portions where the plurality of conductors 42 and the memory pillar MP face each other may function as a plurality of select gate transistors ST connected in series.

[0055] The insulator 45 is disposed on the upper surface of the insulator 43. The insulator 45 extends along the XY plane and has a plate-like shape. The insulator 45 extends across the cell region CA and the peripheral region PA. The insulator 45 has an opening 451 that reaches from the upper surface to the lower surface above the memory pillar MP. The top of the memory pillar MP is located in the opening 451. In one example, the insulator 45 includes silicon oxide.

[0056] The conductor 46 is disposed on the upper surface of the insulator 43. The conductor 46 has a portion located on the side of the insulator 45 within the opening 451 of the insulator 45. The conductor 46 covers the surface of the groove 511 of the semiconductor 51, and covers the semiconductor 51 within the groove 511. In one example, the conductor 46 includes titanium and / or titanium nitride. The structure of the portion of the conductor 46 above the memory pillar MP will be described in detail later with reference to FIG. 6.

[0057] The conductor 47 covers the conductor 46. The conductor 47 functions as at least a part of the source line SL. In one example, the conductor 47 includes tungsten.

[0058] The second structure 200 further includes insulators SM1, SM2, SM3, SM4 and spacer films 61, 62, 63, and 64 in the peripheral region PA.

[0059] The insulator SM1 is disposed between the insulator 30 and the insulator 32. The insulator SM1 extends along the XY plane and has a plate-like shape. In one example, the insulator SM1 includes silicon nitride.

[0060] The multiple insulators SM2 and the multiple insulators 34 are alternately arranged one by one along the Z direction on the upper surface of the insulator 32. Thus, the insulators SM2 are arranged along the Z direction, separated from each other or spaced apart. The insulator SM2 spreads along the XY plane and has a plate-like shape. In one example, the insulator SM2 includes silicon nitride. Some of the insulators SM2 arranged along the Z direction, including the top one, and some of the adjacent insulators 34, including the top one, have portions protruding in the Z direction in the recess 361.

[0061] The insulator 36 is disposed on the upper surface of the top insulator SM2 in the peripheral area PA.

[0062] The multiple insulators SM3 and the multiple insulators 39 are alternately arranged one by one along the Z direction on the upper surface of the insulator 36. Thus, the insulators SM3 are arranged along the Z direction, separated from each other or spaced apart. The insulator SM3 spreads along the XY plane and has a plate-like shape. In one example, the insulator SM3 includes silicon nitride. Some of the insulators SM3 arranged along the Z direction, including the bottom one, and some of the insulators 39 arranged along the Z direction, including the bottom one, have portions protruding in the Z direction along the protruding portion 362.

[0063] The insulator 41 is disposed on the upper surface of the uppermost insulator SM3. The insulator 41 has a portion that protrudes along the protrusion 362 in the Z direction.

[0064] The insulator SM4 is disposed on the upper surface of the insulator 41. The insulator SM4 extends along the XY plane and has a plate-like shape. In one example, the insulator SM4 includes silicon nitride. The insulator SM4 has a portion that protrudes in the Z direction along the protrusion 362.

[0065] The spacer film 61 is located in the insulator 36. The spacer film 61 extends along the Z direction and has an angle with respect to the Z axis. The two spacer films 61 are originally two independent parts of one film. The two spacer films 61 have an axisymmetric relationship with respect to the YZ plane. The distance between the upper ends of the two spacer films 61 is narrower than the distance between the lower ends of the two spacer films 61. The two spacer films 61 are located in the recess 361. The two spacer films 61 surround the parts of the insulators SM2 and 34 that protrude in the Z direction. The parts of the insulators SM2 and 34 that protrude in the Z direction have parts that extend along each spacer film 61. The lower end of the spacer film 61 is aligned with the boundary between the memory pillar LMP and the memory pillar UMP. Examples of the spacer film 61 include polysilicon, silicon oxide, and carbon.

[0066] The spacer film 62 extends along the Z direction and has an angle with respect to the Z axis. The two spacer films 62 are originally two independent parts of one film. The two spacer films 62 have an axisymmetric relationship with respect to the YZ plane. The distance between the upper ends of the two spacer films 62 is narrower than the distance between the lower ends of the two spacer films 62. The lower ends of the spacer films 62 are aligned with the boundary between the memory pillar LMP and the memory pillar UMP. The set of two spacer films 62 is located inside the set of two spacer films 61. Each spacer film 62 is disposed on a side surface of one spacer film 61. The left spacer film 62 is disposed on the right side surface of the left spacer film 61. The right spacer film 62 is disposed on the left side surface of the right spacer film 61. The material of the spacer film 62 is different from the material of the insulators SM2, 34, 32, SM1, and 30. In one example, the spacer film 62 includes carbon or metal.

[0067] The spacer film 63 is located in the insulator 45. The spacer film 63 extends along the Z direction and has an angle with respect to the Z axis. The two spacer films 63 are originally two independent parts of one film. The two spacer films 63 have an axisymmetric relationship with respect to the YZ plane. The distance between the upper ends of the two spacer films 63 is narrower than the distance between the lower ends of the two spacer films 63. The two spacer films 61 surround the parts of the insulators SM3, SM4, and 39 that protrude in the Z direction. The parts of the insulators SM3 and 39 that protrude in the Z direction have parts that extend along each spacer film 63. The spacer film 63 is disposed in the Z direction from the layer of the conductor 42. In one example, the spacer film 63 includes polysilicon.

[0068] The spacer film 64 extends along the Z direction and has an angle with respect to the Z axis. The two spacer films 64 are originally two independent parts of one film. The two spacer films 64 have an axisymmetric relationship with respect to the YZ plane. The distance between the upper ends of the two spacer films 64 is narrower than the distance between the lower ends of the two spacer films 64. The set of two spacer films 64 is located inside the set of two spacer films 63. Each spacer film 64 is disposed on a side surface of one spacer film 63. The left spacer film 64 is disposed on the right side surface of the left spacer film 63. The right spacer film 64 is disposed on the left side surface of the right spacer film 63. The material of the spacer film 64 is different from the material of the insulators 43, SM4, 41, SM3, 39, and 36. In one example, the spacer film 64 includes carbon or metal.

[0069] Fig. 5 shows an example of a cross-sectional structure of a memory pillar of the memory device of the first embodiment. Specifically, Fig. 5 shows a cross section taken along line VV in Fig. 4. As shown in Fig. 5, in one example, the stack 52 includes a tunnel insulator 53, a charge storage film 54, and a block insulator 55.

[0070] The tunnel insulator 53 surrounds the side surface of the semiconductor 51. The charge storage film 54 surrounds the side surface of the tunnel insulator 53. The block insulator 55 surrounds the side surface of the charge storage film 54. The conductor 33 surrounds the side surface of the block insulator 55.

[0071] The semiconductor 51 functions as a channel (current path) of the memory cell transistor MT and the select gate transistors DT and ST. Each of the tunnel insulator 53 and the block insulator 55 includes, for example, silicon oxide. The charge storage film 54 stores charges. The charge storage film 54 includes, for example, silicon nitride.

[0072] Fig. 6 shows an example of a cross-sectional structure of a portion of the memory device of the first embodiment. Fig. 6 shows an enlarged view of the top of the structure shown in Fig. 5, showing the cell area CA. In the description of Fig. 6, the Z direction points up, the -Z direction points down, the Y direction points right, and the -Y direction points left.

[0073] At the top, block insulator 55 includes a portion that is located on the top surface of insulator 43 and a portion that is located on the side surface of insulator 45 .

[0074] The charge storage film 54, at the uppermost part, has a shape that follows the shape of the block insulator 55 and covers the surface of the block insulator 55. That is, the charge storage film 54, at the uppermost part, includes a portion that extends along the XY plane above the insulator 43 and a portion that extends along the Z direction.

[0075] The tunnel insulator 53 has a shape that follows the shape of the charge storage film 54 at the uppermost part, and covers the surface of the charge storage film 54. That is, the tunnel insulator 53 includes, at the uppermost part, a portion that extends along the XY plane above the insulator 43 and a portion that extends along the Z direction.

[0076] The bottom of the groove 511 in the semiconductor 51 contacts the upper surface of the core 50. A portion of the semiconductor 51 surrounding the side surface of the groove 511 covers the surface of the tunnel insulator 53. The semiconductor 51 has a shape that follows the shape of the tunnel insulator 53 at the uppermost portion, and covers the surface of the tunnel insulator 53. That is, the semiconductor 51 includes, at the uppermost portion, a portion that extends along the XY plane above the insulator 43 and a portion that extends along the Z direction.

[0077] Conductor 46 covers the upper surface of insulator 45, the portion of the side of insulator 45 that is not covered by block insulator 55, the upper surface of block insulator 55, the upper surface of charge storage film 54, the upper surface of tunnel insulator 53, the upper surface of semiconductor 51, and the surface of groove 511 in semiconductor 51.

[0078] The conductor 47 covers the surface of the conductor 46. The conductor 47 includes a first portion 471, a plurality of second portions 472, and a plurality of third portions 473. The first portion 471 occupies the uppermost portion of the conductor 47, has a straight line shape, and extends in the X direction. Each of the second portions 472 occupies a portion inside the opening 451 of the insulator 45. Each of the second portions 472 is connected at its upper end to the lower surface of the first portion 471. Each of the third portions 473 occupies a portion inside one of the grooves 511 of the semiconductor 51. The third portion 473 extends along the Z direction. Each of the third portions 473 is connected at its upper end to the lower end of one of the second portions 472.

[0079] 1.2. Manufacturing method 7 to 29 show the cross-sectional structure of the memory device according to the first embodiment during manufacture in sequence. Fig. 7 to Fig. 25 show the area shown in Fig. 4 and illustrate the first structure 100. Fig. 26 to Fig. 29 show the area shown in Fig. 6.

[0080] The first structure 100 is formed sequentially along the -Z direction, and then the in-process first structure 100 is inverted with respect to the XY plane and laminated to the second structure 200. Figures 7 to 25 show the orientation of the first structure 100 shown in Figure 4 and a state in which it is inverted upside down. That is, in the descriptions of Figures 7 to 25, "up" refers to the -Z direction and "down" refers to the Z direction.

[0081] As shown in Fig. 7, an insulator 72 is deposited on the top surface of a substrate 71, such as silicon. An example of a deposition method includes CVD (Chemical Vapor Deposition). The substrate 71 and the insulator 72 extend along the XY plane. In one example, the insulator 72 includes silicon oxide.

[0082] A film 73 is formed on the top surface of the insulator 72. The film 73 extends along the XY plane. The film 73 comprises the same material as the spacer film 63.

[0083] An insulator 45A is formed on the upper surface of the film 73. The insulator 45A is an element that will be molded into the insulator 45 in a later process. The insulator 45A extends along the XY plane.

[0084] As shown in FIG. 8, the insulator 45A is partially removed to form an opening 451. Specifically, a mask having an opening is formed on the upper surface of the insulator 45A above a region where the opening 451 is to be formed, and the insulator 45 is partially removed by anisotropic etching through the opening of the mask. An example of anisotropic etching includes RIE (Reactive Ion Etching). The opening 451 reaches from the upper surface to the lower surface of the insulator 45A. The formation of the opening 451 leaves the insulator 45B of the insulator 45A. In one example, the opening 451 has an XY area at the upper end that is smaller than that at the lower end. The XY area is an area along the XY plane.

[0085] As shown in Fig. 9, a film 63A is deposited. An example of a deposition method includes CVD. The film 63A is an element that will be formed into the spacer film 63 in a later step. The film 63A covers the top surface of the insulator 45B and also fills the opening 451 in the cell area CA. The film 63A covers the surface of the opening 451 in the peripheral area PA.

[0086] As shown in FIG. 10, the film 63A is partially removed by etching back. The portion of the film 63A on the upper surface of the insulator 45B is removed. The film 63A remains in the opening 451 in the cell region CA and becomes the film 63B. The film 63B is located only at the lower part in the opening 451. The height of the portion of the film 63A that is removed from the upper surface is very small compared to the height of the memory pillar MP. Therefore, the variation in the position of the upper surface of the film 63B is small.

[0087] In the peripheral region PA, the film 63A is removed from the bottom surface of the opening 451. The film 63A is thinned in the portions on the side surfaces of the opening 451 in the peripheral region PA, forming the spacer film 63.

[0088] As shown in FIG. 11, a film 64A is deposited. An example of a deposition method includes CVD. The film 64A is an element that will be formed into the spacer film 64 in a later step. The material of the film 64A includes a material different from the materials of the insulators 43, SM4, 41, SM3, 39, and 36. The film 64A covers the top surface of the insulator 45B. The film 64A also fills the area of ​​the opening 451 in the cell area CA that is not filled by the film 63B. The film 64A covers the spacer film 63 and covers the bottom surface of the opening 451 in the peripheral area PA.

[0089] As shown in FIG. 12, the film 64A is partially removed by etching back. The portion of the film 64A on the upper surface of the insulator 45B is removed. The film 64A remains in the opening 451 in the cell region CA and becomes the film 64B. Since the variation in the position of the upper surface of the film 63B is small as described above with reference to FIG. 9, the variation in the position of the lower surface of the film 64B is also small. The film 64A is removed in the peripheral region PA and becomes the bottom surface of the opening 451. The portion of the film 64A on the spacer film 63 remains and becomes the spacer film 64.

[0090] As shown in FIG. 13, a stack of insulators 43, SM4, 41, SM3, 39, and 36 is deposited. An example of a deposition method includes CVD. Insulator SM4 is deposited on the top surface of insulator 43. Insulator 41 is deposited on the top surface of insulator SM4. Insulators SM3 and 39 are alternately deposited one by one on the top surface of insulator 41. Insulator 36 is deposited on the top surface of the top insulator SM3. Insulator SM4 occupies the area where conductor 42 is to be formed. Insulator SM3 occupies the area where conductor 38 is to be formed. The stack is formed on the top surfaces of insulator 45B and film 64B in cell area CA. In peripheral area PA, a part of the bottom of the stack is located in opening 451. Opening 451 in peripheral area PA is filled by a part of the stack. Since a part of the lower portion of the laminate is located in the opening 451 , a recess 361 and a protrusion 362 of the insulator 36 are formed above the opening 451 .

[0091] As shown in FIG. 14, the memory hole LMH is formed. Specifically, a mask is first formed. The mask has an opening above an area where the memory pillar LMP is to be formed. Anisotropic etching such as RIE is performed using the mask. As a result, a stacked body consisting of the insulators 43, SM4, 41, SM3, 39, and 36 is partially removed, and the memory hole LMH is formed. The memory hole LMH extends along the Z direction and reaches below the insulator 43.

[0092] The material of the film 64B is different from the materials of the insulators 43, SM4, 41, SM3, 39, and 36. Therefore, the film 64B functions as a stopper against etching of the insulators 43, SM4, 41, SM3, 39, and 36. That is, even when the insulators 43, 43, SM4, 41, SM3, 39, and 36 are etched, the film 64B is etched only a small amount. Therefore, the variation in the position of the bottom of the memory hole LMH is suppressed.

[0093] 15, the mask and the film 64B in the cell area CA are removed. As a result, the upper part of the opening 451 is formed again in the cell area CA. The position of the bottom of the upper part of the opening 451 depends on the position of the upper surface of the film 64B, and as described above with reference to FIG. 9, the variation in the position of the upper surface of the film 64B is small. Therefore, the variation in the position of the bottom of the upper part of the opening 451 is small.

[0094] As shown in FIG. 16, a film 61A is deposited. An example of a deposition method includes CVD. The film 61A is an element that will be formed into the spacer film 61 in a later process. The film 61A covers the upper surface of the insulator 36. The film 61A fills the upper portion of the opening 451 and the memory hole LMH in the cell region CA. The film 61A covers the surface of the recess 361 in the peripheral region PA.

[0095] As shown in FIG. 17, the film 61A is partially removed by etching back. The portion of the film 61A on the upper surface of the insulator 36 is removed. The portion of the film 61A inside the memory hole LMH is removed at the top. As a result, a space is formed at the top of the memory hole LMH. The portion of the film 61A other than the top in the memory hole LMH remains and becomes the film 61B. In the peripheral region PA, the portion of the film 61A on the bottom surface of the recess 361 is removed. The portion of the film 61A on the side surface of the recess 361 remains and becomes the spacer film 61.

[0096] As shown in FIG. 18, a film 62A is deposited. An example of a deposition method includes CVD. The film 62A is an element that will be formed into the spacer film 62 in a later process. The material of the film 62A is different from the materials of the insulators SM2, 34, 32, SM1, and 30. The film 62A covers the upper surface of the insulator 36. The film 62A fills the top of the memory hole LMH. The film 62A covers the spacer film 61 in the peripheral region PA and covers the bottom of the recess 361.

[0097] 19, the film 62A is partially removed by etching back. A portion of the film 62A on the upper surface of the insulator 36 is removed. The film 62A remains on the uppermost part of the memory hole LMH and becomes a film 62B. In the peripheral region PA, a portion of the film 62A on the bottom surface of the opening 451 is removed. A portion of the film 62A on the spacer film 61 remains and becomes a spacer film 62.

[0098] As shown in Fig. 20, the top of the insulator 36 is deposited on the top surface of the insulator 36 and the film 62B, and then a stack of insulators SM2, 34, 32, SM1, and 30 is deposited. An example of a deposition method includes CVD. The top of the insulator 36 covers the surface of the recess 361. The insulators SM2 and 34 are alternately deposited one by one on the top surface of the insulator 36. The insulator SM2 occupies the area where the conductor 33 is to be formed. The insulator SM1 occupies the area where the conductor 31 is to be formed.

[0099] Insulator 32 is deposited on top of the top insulator SM2. Insulator SM1 is deposited on top of insulator 32. Insulator SM1 occupies the area where conductor 31 is to be formed. Insulator 30 is deposited on top of insulator SM1.

[0100] In the peripheral region PA, a part of the bottom of the stack is located in the recess 361. The recess 361 is filled with a part of the stack.

[0101] As shown in FIG. 21, a memory hole UMH is formed. Specifically, a mask 77 is first formed. The mask 77 has an opening above an area where the memory pillar UMP is to be formed. Anisotropic etching such as RIE is performed using the mask 77. As a result, a stack of insulators SM2, 34, 32, SM1, and 30 is partially removed, and the memory hole UMH is formed. The memory hole UMH extends along the Z direction and reaches below the lowest insulator SM2.

[0102] The material of the film 62B is different from the material of the insulators SM2, 34, 32, SM1, and 30. Therefore, the film 62B acts as a stopper against the etching of the insulators SM2, 34, 32, SM1, and 30. The top part of the film 62B is removed by etching.

[0103] 22, the mask 77 and the film 62B are removed. An example of the removal method includes wet etching. As a result of removing the film 62B, the top of the memory hole LMH is formed again and the upper surface of the film 61B is exposed.

[0104] 23, the film 61B is removed. Examples of the removal method include wet etching and ashing. As a result of removing the film 61B, the entire memory hole LMH and the upper part of the opening 451 are formed again.

[0105] As shown in Figures 24 and 26, a stack 52A, a semiconductor 51A, and a core 50A are deposited. The stack 52A is an element that will be formed into a stack 52 in a later step. The semiconductor 51A is an element that will be formed into a semiconductor 51 in a later step. The core 50A is an element that will be formed into a core 50 in a later step.

[0106] Specifically, first, the block insulator 55A, the charge storage film 54A, the tunnel insulator 53A, the semiconductor 51A, and the core 50A are deposited on the surfaces of the memory holes UMH and LMH. An example of the deposition method includes CVD. The block insulator 55A is an element that will be formed into the block insulator 55 in a later process. The charge storage film 54A is an element that will be formed into the charge storage film 54 in a later process. The tunnel insulator 53A is an element that will be formed into the tunnel insulator 53 in a later process. By depositing the core 50A on the surface of the semiconductor 51A, the centers of the memory holes UMH and LMH and the center of the upper part of the opening 451 are filled with the core 50A.

[0107] The upper portion of the core 50A is removed, and a semiconductor 51A is formed in the removed portion. The upper surface of the semiconductor 51 is planarized together with the upper surface of the insulator 30. An example of a planarization method includes CMP (Chemical Mechanical Polishing).

[0108] As shown in FIG. 25, in the cell region CA, the insulator SM1 is replaced by the conductor 31, the insulator SM2 is replaced by the conductor 33, the insulator SM4 is replaced by the conductor 42, and the insulator SM3 is replaced by the conductor 38. Specifically, first, the insulators SM1, SM2, SM3, and SM4 are removed. An example of a removal method includes wet etching. The wet etching solution reaches the insulators SM1, SM2, SM3, and SM4 in a slit (not shown) extending along the Z direction similarly to the pair of memory holes UMH and LMH, and removes the insulators SM1, SM2, SM3, and SM4. As a result, a space is formed in the region where the insulators SM1, SM2, SM3, and SM4 were located. Next, the conductors 31, 33, 38, and 42 are formed in the space. An example of a formation method includes CVD.

[0109] During the subsequent steps of Figures 27 to 29, the peripheral area is covered by a mask.

[0110] 27, the substrate 71 is stripped and then the insulator 72 is removed. An example of a method of removal includes wet etching.

[0111] Film 63B is removed. An example of a method for removing includes wet etching. As a result of the removal, the top of opening 451 is formed again, and the top surface of block insulator 55A is exposed.

[0112] As shown in FIG. 28, the block insulator 55A, the charge storage film 54A, the tunnel insulator 53A, the semiconductor 51A, and the top of the core 50A are removed. An example of a removal method includes RIE. The removal is performed until the core 50A is exposed. As a result of the removal, the block insulator 55, the charge storage film 54, the tunnel insulator 53, the semiconductor 51, and the core 50B are formed. During the removal, the top of the insulator 45B is also removed, forming the insulator 45.

[0113] 29, the top of the core 50B is removed. An example of a method of removal includes wet etching. The removal forms the groove 511 in the removed area and forms the core 50.

[0114] 4 and 6, a conductor 46 is deposited. An example of a deposition method includes PVD (Physical Vapor Deposition). A conductor 47 is deposited. An example of a deposition method includes CVD.

[0115] 1.3. Advantages (Effects) According to the first embodiment, as described below, a memory device with small variations in electrical characteristics is provided.

[0116] A comparative reference structure similar to the first structure 100 may be fabricated in the following manner. That is, insulator 45A is formed on the upper surface of substrate 71 in a process corresponding to the process described above with reference to FIG. 7. A stack of insulators 43, SM1, 41, SM2, 39, and 36 is deposited on the upper surface of insulator 45A. Then, memory hole LMH is formed by the same process as described above with reference to FIG. 14. Insulator 45A, insulators 43, SM4, 41, SM3, 39, and 36 all contain the same material (silicon), and therefore the selectivity to etching between insulator 45A and insulators 43, SM4, 41, SM3, 39, and 36 is small. Therefore, the upper surface of substrate 71 is removed by etching, and a groove is formed in substrate 71 below memory hole LMH. In general, etching inevitably proceeds at different speeds depending on the location, and therefore the depth of the groove varies. In particular, the deeper the trench is, such as in the case of the memory hole LMH, the greater the variation in the position of the bottom of the trench. Next, the trench is filled with a semiconductor such as silicon by epitaxial growth. The variation in the trench depth causes the height of the top surface of the semiconductor to vary.

[0117] Next, memory pillars are formed on the upper surface of the semiconductor by processes similar to those shown in FIG. 15 and subsequent processes. Since the memory pillars are located on the upper surface of the semiconductor, the positions of the bottoms of the memory pillars vary.

[0118] 27 to 29, grooves 511 are formed in the uppermost part of core 50. At this time, since the positions of the bottoms of the memory pillars vary as described above, the depth of grooves 511 varies. The depth of grooves 511 affects the area of ​​the surface where pairs of conductors 46 and 47 come into contact with semiconductor 51, and the variation in the groove depth causes the contact area to vary. This leads to variation in the electrical characteristics of the memory pillars.

[0119] According to the first embodiment, spacer films 63 and 64 are provided. The spacer film 63 remains as a film 63B during the process described with reference to FIG. 10, and the film 63B is formed by etching back the film 63A. The height of the part of the film 63A that is removed from the upper surface is very small, and therefore the variation in height of the film 63B is small. The spacer film 64 is located as a film 64B at the bottom of the region where the memory hole LMH is to be formed during the etching process for forming the memory hole LMH. And, since the film 64B is located on the upper surface of the film 63B, which has a small variation in height, the variation in height of the lower surface of the film 64B is small. And, since the material of the film 64B is different from the material of the insulators 43, SM4, 41, SM3, 39, and 36, the film 64B functions as a stopper against the etching of the insulators 43, SM4, 41, SM3, 39, and 36, the upper surface of the film 63B is not scraped off, and the small variation in the height of the film 63B is maintained. Therefore, the variation in the height of the upper surface of the core 50B exposed by etching in the process described above with reference to FIG. 27 and FIG. 28 is small. Therefore, the variation in the depth of the groove 511 formed in the process described above with reference to FIG. 29 is small. Therefore, the variation in the contact area between the pair of the conductors 46 and 47 and the semiconductor 51 is small. This suppresses the variation in the electrical characteristics of the memory pillar MP. Therefore, a memory device 1 with small variation in the electrical characteristics can be provided.

[0120] 2. Second embodiment The second embodiment is based on the first embodiment, but differs from the first embodiment in the structure of the memory pillars.

[0121] Fig. 30 is a schematic diagram showing an example of a cross-sectional structure of a portion of a memory device according to a second embodiment. Fig. 31 shows a cross-sectional structure of a portion of the memory device according to a second embodiment, and shows an enlarged portion of Fig. 30. In the description of Figs. 30 and 31, the Z direction points up, the -Z direction points down, the Y direction points right, and the -Y direction points left.

[0122] The memory pillar UMPb of the memory device 1b of the second embodiment includes a first portion UMPb1 and a second portion UMPb2. The lower surface of the first portion UMPb1 is in contact with the upper surface of the second portion UMPb2. Each of the first portion UMPb1 and the second portion UMPb2 has an XY area that decreases from the lower surface to the upper surface. The XY area of ​​the lower surface of the first portion UMPb1 is larger than the XY area of ​​the upper surface of the second portion UMPb2. Therefore, the side surface of the first portion UMPb1 is shifted from the extension line of the side surface of the second portion UMPb2 and does not coincide. The XY area of ​​the lower surface of the memory pillar LMP is larger than the XY area of ​​the upper surface of the first portion UMPb1. Therefore, the side surface of the memory pillar LMP is shifted from the extension line of the side surface of the first portion UMPb1 and does not coincide. Therefore, the XY area of ​​the memory pillar MP changes continuously in the Z direction with the change in position on the Z axis, while it changes discontinuously at the boundary between the first portion UMPb1 and the second portion UMPb2 and at the boundary between the side surface of the LMP and the first portion UMPb1. The misalignment between the extension line of the side surface of the first portion UMPb1 and the side surface of the second portion UMPb2, and the misalignment between the extension line of the side surface of the memory pillar LMP and the side surface of the first portion UMPb1 occur not only in the XZ cross section shown in FIG. 30, but also in other cross sections including the Z axis.

[0123] In the process described above with reference to Fig. 21 in the first embodiment, the center of the memory hole UMH and the center of the memory hole LMH are inevitably misaligned due to unavoidable positional misalignment of the mask in the photolithography process for forming the opening of the mask 77. For this reason, in reality, the center line CLL of the memory pillar LMP is misaligned with the center line CLU of the memory pillar UMPb (UMPb1 and UMpb2) as shown in Fig. 31. The occurrence of the misalignment between the center line CLL of the memory pillar LMP and the center line CLU of the memory pillar UMP also applies to the first embodiment.

[0124] The side surfaces of the core 50b, the semiconductor 51b, and the stack 52b extend along the side surface of the memory pillar MPb.

[0125] Figure 32 shows a cross-sectional structure during fabrication of a memory device of the second embodiment. The area shown in Figure 30 is shown for the first structure 100. Figure 32 shows the structure during a step subsequent to that described above with reference to Figure 21 of the first embodiment. In the description of Figure 32, "up" refers to the -Z direction and "down" refers to the Z direction.

[0126] To manufacture the memory device 1b, first, the steps described above with reference to FIGS. 7 to 21 of the first embodiment are performed. Next, as shown in FIG. 32, a spacer film 79 is deposited. An example of the deposition method includes CVD. In one example, the spacer film 79 includes silicon oxide and / or carbon. The spacer film 79 covers the upper surface of the insulator 30 and the side surface of the upper portion of the memory hole UMH. At the lower portion of the memory hole UMH, the insulators SM2 and 34 are exposed.

[0127] At the bottom of the memory hole UMH, the insulators SM2 and 34 are partially removed. An example of a removal method includes wet etching. By removing the insulators SM2 and 34, the XY area of ​​the region not covered by the spacer film 79 at the bottom of the memory hole UMH is expanded. This forms a region in which the first portion UMPb1 of the memory pillar UMPb is to be formed.

[0128] After the steps described with reference to Figure 32, the steps described above with reference to Figures 22 to 28 of the first embodiment are carried out, resulting in the structure shown in Figure 30.

[0129] According to the second embodiment, in addition to the same advantages as the first embodiment, the following advantages are obtained.

[0130] To increase the capacity of the memory device, the memory pillar MP is very long along the Z direction. Therefore, the difference between the XY area of ​​the lower part and the XY area of ​​the upper part of the memory holes UMH and LMH formed by anisotropic etching is large. This leads to a large variation in the characteristics of the memory cell transistor depending on the layer in which the memory cell transistor is located. Therefore, it is preferable that the variation in the XY area of ​​the memory hole in each layer is small. For that purpose, it is considered to widen the XY area of ​​the lowermost part of the memory hole UMH after the process described above with reference to FIG. 21. During the widening of the XY area, if the film 61B in the memory hole LMH is exposed at the bottom of the upper memory hole UMH, the film 61B is removed, and then the lower memory hole UMH is also widened. This unintentionally increases the difference in the XY area throughout the memory pillar MP.

[0131] According to the second embodiment, a spacer film 62 is provided. The spacer film 62 remains as a film 62B during the process described above with reference to FIG. 31, and the film 62B covers the upper surface of the film 61B. Thus, during the enlargement of the width of the memory hole UMH, the film 61B is removed, thereby avoiding an unintended increase in the XY area of ​​the memory hole LMH. Thus, a memory device 1b with small variations in electrical characteristics is provided.

[0132] 3. Modifications, etc. The memory pillar MP may include three or more connected parts, in which case at the boundary of each two connected parts, spacer films 61 and 62 are provided, and films 61A and 62A are provided which are molded into the spacer films 61 and 62 during the manufacturing process.

[0133] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0134] 1...Storage device, CA: cell area; PA: Peripheral area, PD1, PD2: Lamination pad, 21...Substrate, Tr: transistor, 22, 26...conductor set, 23, 32, 34, 36, 39, 41, 43, 45…Insulator, 27, 28, 31, 33, 38, 42, 46, 47...Conductor, MP, LMP, UMP...Memory pillar, 50…Core, 51...Semiconductors, 52...Laminate, 45…insulator, 53...Tunnel insulator, 54...charge storage film, 55...Block insulator, 451...Aperture, 511...Groove, 61, 62, 63, 64...Spacer films, SM1, SM2, SM3, SM4…insulators

Claims

1. A plurality of first conductors; a plurality of first insulators arranged alternately with the plurality of first conductors in a first direction in a first region; a plurality of second insulators arranged alternately with the plurality of first insulators in the first direction in a second region; A memory pillar penetrating the plurality of first conductors and the plurality of first insulators in the first region, the memory pillar including a semiconductor and a film surrounding a side surface of the semiconductor, the semiconductor having a groove at an end on a side in the first direction; a second conductor in contact with a first surface of the memory pillar in the first direction, including a first portion and a second portion connected to the first portion, the second portion including a portion located in the groove, and in contact with the semiconductor at a side surface of the second portion; a first film extending along the first direction in the second region; a second film extending along the first direction and in contact with the first film; Equipped with At least one of the plurality of second insulators includes a portion extending along the first film and the second film in the second region. storage device.

2. a third film extending along the first direction in the second region; a fourth film extending along the first direction and in contact with a side surface of the third film in a second direction; Further equipped with the first film is in contact with a side surface of the second film in the second direction, The pair of the first film and the second film is located in the second direction from the pair of the third film and the fourth film. The storage device according to claim 1 .

3. The set of the first film and the second film is aligned along the second direction with the set of the third film and the fourth film. The storage device according to claim 2.

4. a distance between an upper end of the second film and an upper end of the fourth film is smaller than a distance between a lower end of the second film and a lower end of the fourth film; The storage device according to claim 3.

5. a fifth film extending along the first direction in the second region; a sixth film extending along the first direction and in contact with the fifth film; Further equipped with the first film and the second film are located in the first direction relative to the fifth film and the sixth film, At least one of the plurality of second insulators includes a portion extending along the fifth film and the sixth film in the second region. The storage device according to claim 2.

6. a seventh film extending along the first direction in the second region; an eighth film extending along the first direction and in contact with a side surface of the seventh film in the second direction; Further equipped with the fifth film is in contact with a side surface of the sixth film in the second direction, The set of the fifth film and the sixth film is located in the second direction from the set of the seventh film and the eighth film. The storage device according to claim 5 .

7. The set of the fifth film and the sixth film is aligned along the second direction with the set of the seventh film and the eighth film. The storage device according to claim 6.

8. a material of the first film, a material of the second film, a material of the third film, a material of the fourth film, a material of the fifth film, a material of the sixth film, a material of the seventh film, and a material of the eighth film are different from a material of the plurality of first insulators and a material of the plurality of second insulators; The storage device according to claim 6.

9. the first film, the third film, the fifth film, and the seventh film include silicon; the second film, the fourth film, the sixth film, and the eighth film contain carbon or a metal, the first insulators include silicon oxide; the second insulators include silicon nitride; The storage device according to claim 6.

10. the memory pillar includes a first portion and a second portion connected to the first portion in the first direction relative to the first portion; an area of ​​a surface of the memory pillar intersecting with the first direction changes in the first direction and discontinuously changes at a boundary between the first portion and the second portion; The fifth film and the sixth film are aligned along the boundary and the second direction. The storage device according to claim 5 .

11. the memory pillar includes a first portion, a second portion connected to the first portion in the first direction from the first portion, and a third portion connected to the first portion in the first direction from the first portion, an area of ​​a surface of the memory pillar intersecting with the first direction changes in the first direction and discontinuously changes at a boundary between the first portion and the second portion and at a boundary between the second portion and the third portion; The storage device according to claim 5 .

12. a material of the first film and a material of the second film are different from a material of the first insulators and a material of the second insulators; The storage device according to any one of claims 1 to 7, 10 and 11.

13. the first film includes silicon; the second film includes carbon or metal; the first insulators include silicon oxide; the second insulators include silicon nitride; The storage device according to claim 1 , wherein the first and second storage devices are arranged in a first and second direction.

14. forming a first insulator including a first opening; forming a first film in a portion of the first opening; forming a second film on a portion of a first direction side of the first opening; forming a first hole penetrating a plurality of third insulators and a plurality of fourth insulators that are formed on the first insulator and the second film and are alternately arranged one by one in the first direction and reaching the second film; removing the second film to form a first space; forming second holes penetrating a plurality of fifth insulators and a plurality of sixth insulators that are formed on the first direction side of the plurality of third insulators and the plurality of fourth insulators and that are alternately arranged one by one in the first direction and reaching a first hole; forming a stacked body including a semiconductor in the first hole, the first space, and the second hole; exposing a first surface of the laminate on a second direction side opposite to the first direction; exposing a side surface of the semiconductor; forming a first conductor in contact with the exposed side of the semiconductor; A manufacturing method of a storage device comprising:

15. exposing the first surface of the stack in the second direction includes removing the first film from a side in the second direction; The method for manufacturing the storage device according to claim 14.

16. the stack further includes a seventh insulator covered by the semiconductor; Exposing the side surface of the semiconductor includes: Partially removing the stack from the second direction side; removing a portion of the seventh insulator on the second direction side in the first direction; Including, The method for manufacturing the storage device according to claim 15 .

17. After forming the first space and before forming the stack, forming an eighth insulator in a first portion within the first hole and the first space; forming a third film on the eighth insulator; Further equipped with forming the second hole removing the third film; removing the eighth insulator; and Including, The method for manufacturing the storage device according to claim 16.

18. and widening a portion of the second hole after forming the third film and before removing the third film. The method for manufacturing the storage device according to claim 17.

19. Enlarging the portion of the second hole includes: covering a part of a side surface of the second hole in the second direction with a fourth film; partially removing a portion of the side surface of the second hole that is not covered with the fourth film in a direction in which the second hole is widened; Equipped with The method for manufacturing the storage device according to claim 18.

20. and further comprising replacing each of the plurality of fourth insulators and the sixth insulators with a second conductor. A method for manufacturing the storage device according to any one of claims 15 to 19.

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