Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing power consumption while suppressing malfunctions due to noise.SOLUTION: A semiconductor device according to an embodiment includes a first terminal, a first circuit and a second circuit. The first terminal is connected to a first node, and a control signal is externally input to the first terminal. The first circuit is connected to the first node, switches, based on a logic level of the first node, between a first state where a first voltage is not output to a second node and a second state where the first voltage is output to the second node, and controls a slew rate of an output voltage at a time of switching from the first state to the second state. The second circuit includes a switch that has one end connected to the first node and another end to which a second voltage is applied, the second circuit controlling the switch based on a voltage at the second node.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] A pull-down circuit that fixes the voltage of a node is known as a semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-188257 A Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a semiconductor device that suppresses malfunction due to noise while suppressing power consumption. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first terminal, a first circuit, and a second circuit. The first terminal is connected to a first node, and a control signal is input from the outside. The first circuit is connected to the first node, and switches between a first state in which a first voltage is not output to a second node and a second state in which the first voltage is output to the second node based on the logic level of the first node, and controls the slew rate of the output voltage when switching from the first state to the second state. The second circuit includes a switch having one end connected to the first node and the other end to which a second voltage is applied, and controls the switch based on the voltage of the second node. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of the configuration of a semiconductor device according to a first embodiment. [Diagram 2]FIG. 2 is a block diagram showing a specific example of the configuration of an output circuit and a control circuit according to the first embodiment. [Diagram 3] 4 is a timing chart showing an example of the operation of the semiconductor device according to the first embodiment. [Figure 4] FIG. 11 is a block diagram showing a specific example of the configuration of an output circuit and a pull-down circuit according to a first modification of the first embodiment. [Diagram 5] FIG. 11 is a circuit diagram showing an example of the configuration of a semiconductor device according to a second embodiment. [Figure 6] 10 is a timing chart showing an example of the operation of the semiconductor device according to the second embodiment. [Figure 7] FIG. 11 is a block diagram showing an example of the configuration of a semiconductor device according to a third embodiment. [Figure 8] 10 is a timing chart showing an example of the operation of the semiconductor device according to the third embodiment. [Figure 9] FIG. 13 is a block diagram showing a specific example of the configuration of a semiconductor device according to a first modification of the third embodiment. [Figure 10] FIG. 13 is a block diagram showing an example of the configuration of a semiconductor device according to a fourth embodiment. [Figure 11] FIG. 13 is a block diagram showing a specific example of the configuration of an output circuit and a control circuit according to a fourth embodiment. [Figure 12] 13 is a timing chart showing an example of the operation of the semiconductor device according to the fourth embodiment. [Figure 13] FIG. 11 is a block diagram showing an example of a configuration of a semiconductor device according to a second modification of the first embodiment. [Figure 14] FIG. 13 is a block diagram showing an example of a configuration of a semiconductor device according to a first modification of the fourth embodiment. [Figure 15] FIG. 11 is a block diagram showing an example of a configuration of a semiconductor device according to a third modification of the first embodiment. [Figure 16] FIG. 13 is a block diagram showing an example of a configuration of a semiconductor device according to a second modification of the fourth embodiment. [Figure 17] FIG. 13 is a block diagram showing an example of a configuration of a semiconductor device according to a third modification of the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In the description, components having substantially the same functions and configurations are given the same reference numerals. The embodiments described below are merely examples of technical ideas. The materials, shapes, structures, arrangements, etc. of the components are not specified in the embodiments. Various modifications can be made to the embodiments.

[0008] <1> First embodiment The semiconductor device according to the first embodiment will be described.

[0009] <1-1> Configuration 1 is a block diagram showing an example of the configuration of a semiconductor device according to a first embodiment. The semiconductor device 1 according to the first embodiment is a load switch having a slew rate control function for supplying power to a load. The semiconductor device 1 is an IC (Integrated Circuit) chip that switches between enabling and disabling an output based on a control signal input from the outside.

[0010] The semiconductor device 1 includes terminals TEN and TOUT, an output circuit 2, and a pull-down circuit 3. The terminal TEN is a control signal input terminal of the semiconductor device 1. The terminal TEN is configured to be connectable to the outside of the semiconductor device 1. The terminal TEN is connected to a node N1. A control signal is input to the terminal TEN from a previous stage circuit (not shown) provided outside the semiconductor device 1. The terminal TOUT is an output terminal of the semiconductor device 1. The terminal TOUT is configured to be connectable to the outside of the semiconductor device 1. Power is supplied from the terminal TOUT to the outside of the semiconductor device 1. The terminal TOUT is connected to a node N2.

[0011] The output circuit 2 is a circuit that realizes the function of the load switch of the semiconductor device 1. A voltage VDD, which is a power supply voltage, and a ground voltage GND are applied to the output circuit 2. The output circuit 2 is connected to each of the nodes N1 and N2. The output circuit 2 switches between an ON state (second state) in which the voltage VDD is output to the node N2 and an OFF state (first state) in which the voltage VDD is not output to the node N2 according to the logic level of the node N1. Specifically, the output circuit 2 is in the OFF state when the logic level of the node N1 is at an L (Low) level, and is in the ON state when the logic level of the node N1 is at an H (High) level. The output circuit 2 has a slew rate control function. That is, when switching from an OFF state to an ON state, the output circuit 2 controls the rising speed of the voltage that switches the output voltage from 0V (a state in which no voltage is output) to the voltage VDD. More specifically, the output circuit 2 is configured to take, for example, 30 μsec or more to reach 1 / 2 of the final voltage from 0V, that is, to reach 1 / 2 of the voltage VDD from 0V.

[0012] The pull-down circuit 3 pulls down the node N1. Specifically, the pull-down circuit 3 switches between an ON state where the node N1 is pulled down and an OFF state where the node N1 is not pulled down based on the voltage of the node N2. Hereinafter, the case where the pull-down circuit 3 is in the ON state is referred to as a state where the pull-down circuit 3 is connected to the node N1. Also, the case where the pull-down circuit 3 is in the OFF state is referred to as a state where the pull-down circuit 3 is disconnected from the node N1. The pull-down circuit 3 includes a resistor R1, a switch SW1, and a control circuit 4. The resistor R1 and the switch SW1 are connected in series. In the example shown in FIG. 1, one end of the resistor R1 is connected to the node N1, the other end of the resistor R1 is connected to one end of the switch SW1, and the other end of the switch SW1 is grounded. In other words, one end of the switch SW1 is connected to the node N1 via the resistor R1, and the ground voltage GND is applied to the other end of the switch SW1. The control circuit 4 controls the switch SW1 based on the voltage of the node N2. Specifically, when the control circuit 4 detects that the output circuit 2 is outputting a voltage equal to or greater than a preset threshold to the node N2, the control circuit 4 turns off the switch SW1. When the control circuit 4 detects that the output circuit 2 is not outputting a voltage equal to or greater than the threshold to the node N2, the control circuit 4 turns on the switch SW1. That is, when a voltage equal to or greater than the threshold is applied to the node N2, the pull-down circuit 3 is disconnected from the node N1, and when a voltage equal to or greater than the threshold is not applied to the node N2, the pull-down circuit 3 is connected to the node N1.

[0013] Fig. 2 is a block diagram showing a specific example of the configuration of the output circuit 2 and the control circuit 4 according to the first embodiment. As shown in Fig. 2, the output circuit 2 according to the first embodiment includes a non-inverting logic circuit 20, transistors MN1, MP1, and MP2, and a current source CS1. The transistor MN1 is an N-channel type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The transistors MP1 and MP2 are P-channel type MOSFETs.

[0014] A voltage VDD and a ground voltage GND are applied to the non-inverting logic circuit 20. A signal input terminal of the non-inverting logic circuit 20 is connected to the node N1, and a signal output terminal is connected to the gates of the transistors MP1 and MN1. The non-inverting logic circuit 20 applies a voltage based on the logic level of the node N1 to the gates of the transistors MP1 and MN1. For example, when an H-level voltage is applied to the node N1, the non-inverting logic circuit 20 outputs an H-level voltage. In that case, the transistor MP1 is turned off, and the transistor MN1 is turned on. Also, for example, when an L-level voltage is applied to the node N1, the non-inverting logic circuit 20 outputs an L-level voltage. In that case, the transistor MP1 is turned on, and the transistor MN1 is turned off.

[0015] A voltage VDD is applied to the source of transistor MP1. The drains of transistors MP1 and MN1 are connected to the gate of transistor MP2. For example, when the non-inverting logic circuit 20 outputs an L-level voltage, transistor MP1 is turned on and transistor MN1 is turned off. As a result, transistor MP2 is turned off. On the other hand, when the non-inverting logic circuit 20 outputs an H-level voltage, transistor MP1 is turned off and transistor MN1 is turned on. As a result, transistor MP2 is turned on.

[0016] A current source CS1 is connected to the source of the transistor MN1. The current source CS1 is configured to cause a current to flow from the source of the transistor MN1 to the ground voltage GND.

[0017] A voltage VDD is applied to the source of the transistor MP2. The drain of the transistor MP2 is connected to the node N2. In the ON state, the transistor MP2 applies the voltage VDD to the node N2, and in the OFF state, the transistor MP2 does not apply the voltage VDD to the node N2. The transistors MP1 and MN1 and the current source CS1 function as a gate driver that drives the gate of the transistor MP2. In this gate driver, the current source CS1 controls the amount of current when driving the gate of the transistor MP2 from the H level to the L level. Thus, in the output circuit 2, the length of time it takes for the transistor MP2 to switch from the OFF state to the ON state is controlled. That is, in the output circuit 2 according to the first embodiment, the slew rate of the output voltage when switching from the OFF state to the ON state is controlled.

[0018] 2, the configuration of the control circuit 4 included in the pull-down circuit 3 will be described. As shown in FIG. 2, the control circuit 4 according to the first embodiment includes a comparator 40 and a voltage source 41. The voltage source 41 outputs a voltage VREF1. The voltage VREF1 is higher than the ground voltage GND and lower than the voltage VDD. The voltage VREF1 is, for example, 1 / 2 the voltage VDD. The positive output terminal of the voltage source 41 is connected to the non-inverting input terminal of the comparator 40. The negative output terminal of the voltage source 41 is grounded.

[0019] The inverting input terminal of the comparator 40 is connected to the node N2. The output terminal of the comparator 40 is connected to the switch SW1. The switch SW1 is controlled based on the output of the comparator 40. More specifically, when the output of the comparator 40 is at H level, the switch SW1 is in an ON state. When the output of the comparator 40 is at L level, the switch SW1 is in an OFF state.

[0020] <1-2> Operation The operation of the semiconductor device 1 according to the first embodiment will be described. Note that the voltage at the terminal TEN is referred to as the voltage VEN, and the voltage at the terminal TOUT is referred to as the voltage VOUT.

[0021] Fig. 3 is a timing chart showing an example of the operation of the semiconductor device 1 according to the first embodiment. Fig. 3 shows the operation when noise is applied to the terminal TEN, and the operation of the semiconductor device 1 is switched when an H-level signal is applied to the terminal TEN. Fig. 3 shows, from the top, the states of the voltage VEN, the voltage VOUT, and the switch SW1.

[0022] In Fig. 3, the timing chart starts when the terminal TEN is switched from an L level applied by the preceding device to a high impedance state. In this state, the voltage VEN is 0V, the voltage VOUT is 0V, and the switch SW1 is on. Since the switch SW1 is on, the node N1 is pulled down to 0V by the pull-down circuit 3. Since the voltage of the node N1 is 0V, i.e., the L level, the output circuit 2 is off and the voltage VOUT is 0V.

[0023] At time t11, noise is applied to the terminal TEN, causing the voltage VEN to rise sharply. For example, the peak of the voltage VEN exceeds 1 / 2 of the voltage VDD. The voltage VEN then drops and becomes 0V at time t12. The period from time t11 to time t12 is, for example, several μsec. The period from time t11 to time t12 is shorter than the time it takes for the output of the output circuit 2 to switch from 0V to the voltage VDD. Therefore, the output circuit 2 maintains an output of 0V. Since the voltage VOUT is maintained at 0V, the switch SW1 also maintains an on state from time t11 to time t12.

[0024] At time t13, the previous stage device connected to terminal TEN outputs voltage VDD as an H level, and voltage VEN becomes voltage VDD. After time t13, voltage VEN is maintained at voltage VDD. Because voltage VEN becomes higher than half voltage VDD, output circuit 2 starts outputting voltage VDD at time t13. During the period from time t13 to time t15, voltage VOUT rises from 0V to voltage VDD with the slew rate controlled by output circuit 2. Note that at time t13, voltage VOUT is lower than voltage VREF1, so switch SW1 remains on.

[0025] At time t14, voltage VOUT becomes greater than voltage VREF1, and switch SW1 changes from the on state to the off state. After time t14, switch SW1 maintains the off state. As switch SW1 turns off, the power consumed by pull-down circuit 3 decreases. Specifically, the power consumed by resistor R1 is no longer consumed. Note that the period from time t13 to time t14 is the time required for voltage VOUT to rise from 0V to 1 / 2 of voltage VDD, which is the final voltage, and is therefore 30 μsec or more.

[0026] At time t15, the voltage VOUT reaches the voltage VDD and the increase of the voltage VOUT stops. After time t15, the voltage VOUT is maintained at the voltage VDD.

[0027] <1-3> Effects According to the semiconductor device 1 of the first embodiment described above, it is possible to suppress malfunctions caused by noise while suppressing power consumption. The effects of the semiconductor device 1 of the first embodiment will be described in detail below.

[0028] A pull-down circuit stabilizes the voltage of a node to which the pull-down circuit is connected, and prevents the logic level of the node from being disturbed by external disturbances such as noise. However, when an H-level signal is applied to the node to which the pull-down circuit is connected, a current flows through the pull-down circuit, consuming power. While the node to which the pull-down circuit is connected continues to be driven to the H level, it is preferable to cut off the pull-down circuit from the node to suppress power consumption.

[0029] Furthermore, the voltage of the node to which the pull-down circuit is connected may rise momentarily due to noise, or may rise when driven to an H level by a circuit in the preceding stage. If the pull-down circuit is disconnected when the voltage of the node rises momentarily due to noise, the voltage of the node may become unstable, causing the circuit to malfunction. It is preferable that the pull-down circuit maintains connection to the node when the voltage of the node rises momentarily due to noise, and disconnects from the node when the voltage of the node is driven to an H level by a circuit in the preceding stage.

[0030] The semiconductor device 1 of the first embodiment includes a terminal TEN connected to a node N1 and to which a control signal is input from outside, an output circuit 2 connected to the node N1 and switching between a first state in which a voltage VDD is not output to a node N2 and a second state in which a voltage VDD is output to the node N2 based on the logical level of the node N1, and controlling the slew rate of the output voltage when switching from the first state to the second state, and a pull-down circuit 3 including a switch SW1 having one end connected to the node N1 and the other end to which a ground voltage GND is applied, and controlling the switch SW1 based on the voltage of the node N2.

[0031] The output circuit 2 can control the slew rate of the output voltage so that the voltage of node N2 does not rise even if the voltage of node N1 rises momentarily due to noise. Because the voltage of node N2 does not change, the pull-down circuit 3 keeps the switch SW1 on even if the voltage of node N1 rises momentarily due to noise. In other words, the pull-down circuit 3 keeps the node N1 pulled down.

[0032] On the other hand, when node N1 is driven to voltage VDD by the circuit in the previous stage, output circuit 2 switches to the ON state, and the voltage of node N2 rises. Then, when the voltage of node N2 becomes higher than voltage VREF1, pull-down circuit 3 turns switch SW1 to the OFF state. In other words, pull-down circuit 3 puts node N1 in a state where it is not pulled down.

[0033] In this way, the semiconductor device 1 according to the first embodiment maintains the connection of the pull-down circuit 3 when there is an instantaneous voltage rise due to noise, and when a control signal is applied, the output circuit 2 operates, and the output voltage exceeds the threshold, the semiconductor device 1 according to the first embodiment disconnects the pull-down circuit 3. Thus, the semiconductor device 1 according to the first embodiment can suppress power consumption while suppressing malfunctions due to noise.

[0034] Furthermore, in the semiconductor device 1 according to the first embodiment, after a control signal is applied, the output circuit 2 starts operating and disconnects the pull-down circuit 3 at the timing when the output voltage exceeds the threshold. That is, the semiconductor device 1 waits from the time when the control signal becomes H level until the output of the output circuit 2 exceeds the threshold, and then disconnects the pull-down circuit 3. This waiting time prevents the pull-down circuit 3 from being disconnected when a momentary voltage rise occurs.

[0035] For example, a circuit may be configured using a low-pass filter, which waits for a certain period of time after the control signal becomes H level, and then disconnects the pull-down circuit 3. In this case, an area for configuring the low-pass filter on the chip is required. Also, the wait time may vary due to manufacturing variations in the elements that configure the low-pass filter. In contrast, in the semiconductor device 1 according to the first embodiment, the pull-down circuit 3 monitors the output of the output circuit 2, thereby generating the wait time. Therefore, in the semiconductor device 1 according to the first embodiment, an area for configuring the filter is not required, and the wait time does not vary.

[0036] Furthermore, the semiconductor device 1 according to the first embodiment disconnects the pull-down circuit 3 after the output circuit 2 starts operating and the output exceeds the voltage VREF1. In other words, the pull-down circuit 3 is disconnected not before the output circuit 2 starts operating or after the output of the output circuit 2 reaches the voltage VDD, but at the timing when the output of the output circuit 2 exceeds the threshold. In this way, the semiconductor device 1 according to the first embodiment can set the standby time according to the operation timing of the circuit.

[0037] <1-4> Variations In the first embodiment, the control circuit 4 of the pull-down circuit 3 includes a comparator 40 and a voltage source 41. The configuration of the control circuit 4 is not limited to this. For example, the control circuit 4 may be configured by an inverter. Furthermore, the switch SW1 of the pull-down circuit 3 may be configured by a transistor. FIG. 4 is a block diagram showing a specific example of the configuration of an output circuit and a pull-down circuit according to a first modification of the first embodiment. The semiconductor device 1a according to the first modification of the first embodiment is different from the semiconductor device 1 according to the first embodiment in that the switch SW1 of the pull-down circuit 3 is configured by a transistor MN2 and the control circuit 4 is configured by an inverter 42.

[0038] The pull-down circuit 3a includes a resistor R1, a transistor MN2, and a control circuit 4a. The control circuit 4a includes an inverter 42. One end of the resistor R1 is connected to a node N1. The other end of the resistor R1 is connected to the drain of the transistor MN2. The source of the transistor MN2 is grounded. The input end of the inverter 42 is connected to the node N2. The output end of the inverter 42 is connected to the gate of the transistor MN2. The inverter 42 inverts the logic level of the node N2 and outputs the inverted logic level to the gate of the transistor MN2. A voltage VDD is applied to the positive power supply end of the inverter. The negative power supply end of the inverter is grounded.

[0039] The inverter 42 is used as a comparator that compares 1 / 2 the applied power supply voltage with the input signal and outputs the relative magnitude as an H level or an L level. The transistor MN2 is used as a switch that is turned off when an L level is applied to its gate and turned on when an H level is applied to its gate.

[0040] Even if the pull-down circuit 3 is configured in this way, the same effects as those of the semiconductor device 1 according to the first embodiment can be obtained.

[0041] <2> Second embodiment The configuration of the semiconductor device according to the second embodiment is different from that of the semiconductor device according to the first embodiment in that the output circuit 2 is replaced with an output circuit 2a and the pull-down circuit 3 is replaced with a pull-down circuit 3b. The following describes the differences between the semiconductor device 1b according to the second embodiment and the first embodiment.

[0042] <2-1> Configuration 5 is a circuit diagram showing an example of the configuration of a semiconductor device 1b according to the second embodiment. In the semiconductor device 1b according to the second embodiment, the output circuit 2 of the semiconductor device 1 described in the first embodiment is replaced with an output circuit 2a, and the pull-down circuit 3 is replaced with a pull-down circuit 3b.

[0043] The semiconductor device 1b according to the second embodiment is a linear regulator having a slew rate control function and supplying power to a load. More specifically, the semiconductor device 1b according to the second embodiment is a low saturation linear regulator, also called an LDO (Low Dropout).

[0044] The output circuit 2a is a circuit that realizes the function of the semiconductor device 1b as a linear regulator. A voltage VDD, which is a power supply voltage, and a ground voltage GND are applied to the output circuit 2a. The output circuit 2a is connected to each of the nodes N1 and N2. The output circuit 2a switches between an ON state (second state) in which the voltage VLD is output to the node N2 and an OFF state (first state) in which the voltage VLD is not output to the node N2 according to the logic level of the node N1. The voltage VLD is a voltage lower than the voltage VDD and higher than the ground voltage GND. Specifically, the output circuit 2a is in the OFF state when the logic level of the node N1 is at the L level, and is in the ON state when the logic level of the node N1 is at the H level. The output circuit 2a has a slew rate control function. That is, when the output circuit 2a switches from the OFF state to the ON state, it controls the rising speed of the voltage at which the output voltage is switched from 0V (a state in which no voltage is output) to the voltage VLD. More specifically, the output circuit 2a is configured so that it takes, for example, 30 μsec or more to reach ½ of the final voltage from 0 V, that is, to reach ½ of the voltage VLD from 0 V.

[0045] The pull-down circuit 3b pulls down the node N1. The pull-down circuit 3b switches between an ON state where the node N1 is pulled down and an OFF state where the node N1 is not pulled down based on the voltage of the node N2. The pull-down circuit 3b includes a resistor R1, a switch SW1, and a control circuit 4b. The resistor R1 and the switch SW1 are connected in series. In the example shown in FIG. 5, one end of the resistor R1 is connected to the node N1, the other end of the resistor R1 is connected to one end of the switch SW1, and the other end of the switch SW1 is grounded. In other words, one end of the switch SW1 is connected to the node N1 via the resistor R1, and the ground voltage GND is applied to the other end of the switch SW1. The control circuit 4b controls the switch SW1 based on the voltage of the node N2. Specifically, when the control circuit 4b detects that the output circuit 2a is outputting a voltage equal to or higher than a preset threshold to the node N2, it turns off the switch SW1. When the control circuit 4b detects that the output circuit 2a is not outputting a voltage equal to or higher than the threshold to the node N2, the control circuit 4b turns on the switch SW1.

[0046] Continuing to refer to Fig. 5, a specific example of the configuration of the output circuit 2a will be described. As shown in Fig. 5, the output circuit 2a according to the second embodiment includes transistors MN3 to MN8, transistors MP3 to MP9, current sources CS2 to CS5, resistors R2 and R3, a capacitor 21, and a voltage source 22. The transistors MN3 to MN8 are N-channel MOSFETs. The transistors MP3 to MP9 are P-channel MOSFETs. The voltage source 22 outputs a voltage VREF2. The voltage VREF2 is higher than the ground voltage GND and lower than the voltage VDD.

[0047] A voltage VDD is applied to the source of the transistor MP3. A gate of the transistor MP3 is connected to the node N1. A gate of the transistor MN3 is connected to the node N1. A current source CS2 is connected to the source of the transistor MN3. The current source CS2 is configured to flow a current from the source of the transistor MN3 toward the ground voltage GND. A drain of the transistor MP3, a drain of the transistor MN3, a gate of the transistor MP4, and a gate of the transistor MN4 are connected. A current source CS3 is connected to the source of the transistor MP4. The current source CS3 is configured to flow a current from the voltage VDD toward the source of the transistor MP4. The source of the transistor MN4 is grounded. A drain of the transistor MP4, a drain of the transistor MN4, a gate of the transistor MP5, and one electrode of the capacitor 21 are connected. The other electrode of the capacitor 21 is grounded. A current source CS4 is connected to the source of the transistor MP5. The current source CS4 is configured to flow a current from the voltage VDD toward the source of the transistor MP5.

[0048] The source of transistor MN5 is grounded. The gate of transistor MN5 is connected to node N1. The drain of transistor MN5 is connected to current source CS5. The source of transistor MN6 is grounded. The gate of transistor MN6 is connected to node N1. The sources of transistors MN7, MN8, and current source CS5 are connected. The current source CS5 is configured to flow a current from the sources of transistors MN7 and MN8 to the drain of transistor MN5. The positive output terminal of voltage source 22 is connected to the gate of transistor MN8. The negative output terminal of voltage source 22 is connected to the drain of transistor MN6. The drain of transistor MN7, the gate of transistor MP6, the drain of transistor MP6, and the gate of transistor MP7 are connected. The voltage VDD is applied to the source of transistor MP6. The voltage VDD is applied to the source of transistor MP7. The voltage VDD is applied to the source of transistor MP8. The gate of transistor MP8 is connected to node N1. A voltage VDD is applied to the source of the transistor MP9. The drain of the transistor MP9 is connected to the node N2. The drains of the transistors MP5, MN8, MP7, MP8, and MP9 are connected together. One end of the resistor R2 is connected to the node N2. The other end of the resistor R2, one end of the resistor R3, and the gate of the transistor MN7 are connected together. The other end of the resistor R3 is grounded.

[0049] The output circuit 2a generates a voltage VLD from the voltage VDD by controlling the gate voltage of the transistor MP9, and outputs the voltage VLD to the node N2. More specifically, the transistors MN7 and MN8, the transistors MP6 and MP7, and the current source CS5 constitute a differential amplifier circuit. This differential amplifier circuit controls the gate voltage of the transistor MP9 so that the voltage of the node N2 divided by the resistors R2 and R3 is equal to the voltage VREF2 of the voltage source 22. The transistors MN5 and MN6 are turned on when the voltage of the node N1 is at H level to enable the differential amplifier circuit, and turned off when the voltage of the node N1 is at L level to disable the differential amplifier circuit. The transistor MP8 is turned off when the voltage of the node N1 is at H level to not function, and is turned on when the voltage of the node N1 is at L level to fix the gate voltage of the transistor MP9 to the voltage VDD. That is, the transistor MP9 is turned off.

[0050] The transistors MN3 and MN4, the transistors MP3 to MP5, the current sources CS2 to CS4, and the capacitor 21 control the slew rate of the output voltage of the output circuit 2a. More specifically, the current sources CS2 and CS3, and the capacitor 21 control the length of time for the gate of the transistor MP5 to switch from L level to H level when the node N1 switches from L level to H level. As a result, when the node N1 switches from L level to H level, the current source CS4 and the transistor MP5 continue to inject current into the gate of the transistor MP9 for a while, slowing down the change in the gate voltage of the transistor MP9. Therefore, in the output circuit 2a according to the second embodiment, the slew rate of the output voltage when switching from the OFF state to the ON state is controlled.

[0051] Continuing to refer to FIG. 5, the configuration of the control circuit 4b included in the pull-down circuit 3b will be described. As shown in FIG. 5, the control circuit 4b according to the second embodiment includes a comparator 40 and a voltage source 41a. The voltage source 41a outputs a voltage VREF3. The voltage VREF3 is higher than the ground voltage GND and lower than the voltage VLD. The voltage VREF3 is, for example, 1 / 2 the voltage VLD. The positive output terminal of the voltage source 41a is connected to the non-inverting input terminal of the comparator 40. The negative output terminal of the voltage source 41a is grounded.

[0052] The inverting input terminal of the comparator 40 is connected to the node N2. The output terminal of the comparator 40 is connected to the switch SW1. The switch SW1 is controlled based on the output of the comparator 40. More specifically, when the output of the comparator 40 is at an H level, the switch SW1 is in an ON state. When the output of the comparator 40 is at an L level, the switch SW1 is in an OFF state.

[0053] <2-2> Operation The operation of the semiconductor device 1b according to the second embodiment will be described. Fig. 6 is a timing chart showing an example of the operation of the semiconductor device 1b according to the second embodiment. Fig. 6 shows the operation when noise is applied to the terminal TEN, and the operation of the semiconductor device 1b is switched when an H-level signal is applied to the terminal TEN.

[0054] In Fig. 6, the timing chart starts when the terminal TEN is switched from an L level applied by the preceding device to a high impedance state. In this state, the voltage VEN is 0V, the voltage VOUT is 0V, and the switch SW1 is on. Because the switch SW1 is on, the node N1 is pulled down to 0V by the pull-down circuit 3b. Because the voltage of the node N1 is 0V, i.e., the L level, the output circuit 2a is off and the voltage VOUT is 0V.

[0055] At time t21, noise is applied to the terminal TEN, causing the voltage VEN to rise sharply. For example, the peak of the voltage VEN exceeds 1 / 2 of the voltage VDD. The voltage VEN then drops and becomes 0V at time t22. The period from time t21 to time t22 is, for example, several μsec. The period from time t21 to time t22 is shorter than the time it takes for the output of the output circuit 2a to switch from 0V to the voltage VLD. Therefore, the output circuit 2a maintains an output of 0V. Since the voltage VOUT is maintained at 0V, the switch SW1 also maintains an on state from time t21 to time t22.

[0056] During the period from time t22 to time t23, no change occurs in the situation, so the voltage VEN is maintained at 0 V, the voltage VOUT is maintained at 0 V, and the switch SW1 is maintained in the on state.

[0057] At time t23, the preceding device connected to terminal TEN outputs voltage VDD as an H level, and voltage VEN becomes voltage VDD. After time t23, voltage VEN is maintained at voltage VDD. Because voltage VEN becomes higher than 1 / 2 voltage VDD, output circuit 2a starts outputting voltage VLD at time t23. During the period from time t23 to time t25, voltage VOUT rises from 0V to voltage VLD with the slew rate controlled by output circuit 2a. Note that at time t23, voltage VOUT is lower than voltage VREF3, so switch SW1 remains on.

[0058] At time t24, the voltage VOUT becomes greater than the voltage VREF3, and the switch SW1 changes from the on state to the off state. After time t24, the switch SW1 maintains the off state. As the switch SW1 turns off, the power consumed by the pull-down circuit 3b decreases. Specifically, the power consumed by the resistor R1 is no longer consumed. Note that the period from time t23 to time t24 is the time required for the voltage VOUT to rise from 0V to 1 / 2 the voltage VLD, which is the final voltage, and is therefore 30 μsec or more.

[0059] At time t25, the voltage VOUT reaches the voltage VLD and the increase of the voltage VOUT stops. After time t25, the voltage VOUT is maintained at the voltage VLD.

[0060] <2-3> Effects According to the semiconductor device 1b of the second embodiment described above, it is possible to suppress malfunctions caused by noise and reduce power consumption, similarly to the semiconductor device 1 of the first embodiment. The effects of the semiconductor device 1b of the second embodiment will be described in detail below.

[0061] In the semiconductor device 1b according to the second embodiment, the slew rate of the output voltage of the output circuit 2a is controlled, as in the semiconductor device 1 according to the first embodiment. Therefore, even if the voltage of the node N1 rises momentarily due to noise, the pull-down circuit 3b maintains the state in which the node N1 is pulled down. Also, when an H-level control signal is applied to the node N1 and the output circuit 2a makes the voltage of the node N2 higher than the threshold, the pull-down circuit 3b turns off the switch SW1, and the pull-down circuit 3b puts the node N1 in a state in which it is not pulled down. Therefore, the semiconductor device 1b according to the second embodiment can suppress power consumption while suppressing malfunctions due to noise.

[0062] Similarly to the semiconductor device 1 according to the first embodiment, the semiconductor device 1b according to the second embodiment waits from when the control signal becomes H level until the output of the output circuit 2a actually exceeds the threshold, and then disconnects the pull-down circuit 3b. In other words, the pull-down circuit 3b generates a wait time by monitoring the output of the output circuit 2a. This makes it possible to set the wait time according to the operation timing of the circuit.

[0063] <3> Third embodiment The configuration of the semiconductor device according to the third embodiment is different from that of the semiconductor device according to the first embodiment in that the output circuit 2 is replaced with an output circuit 2b and the pull-down circuit 3 is replaced with a pull-down circuit 3c. The following describes the differences between the semiconductor device 1c according to the third embodiment and the first embodiment.

[0064] <3-1> Configuration 7 is a block diagram showing an example of a configuration of a semiconductor device 1c according to the third embodiment. In the semiconductor device 1c according to the third embodiment, the output circuit 2 of the semiconductor device 1 described in the first embodiment is replaced with an output circuit 2b, and the pull-down circuit 3 is replaced with a pull-down circuit 3c.

[0065] The semiconductor device 1c according to the third embodiment is a logic IC that outputs a clock signal.

[0066] The output circuit 2b is a circuit that realizes the function of the semiconductor device 1c as a logic IC. A voltage VDD, which is a power supply voltage, and a ground voltage GND are applied to the output circuit 2b. The output circuit 2b is connected to each of the nodes N1 and N2. The output circuit 2b switches between an ON state (second state) in which a signal CLK, which is a clock signal, is output to the node N2 and an OFF state (first state) in which the signal CLK is not output to the node N2 according to the logic level of the node N1. Specifically, the output circuit 2b is in the OFF state when the logic level of the node N1 is at the L level, and is in the ON state when the logic level of the node N1 is at the H level.

[0067] The pull-down circuit 3c pulls down the node N1. The pull-down circuit 3c switches between an ON state where the node N1 is pulled down and an OFF state where the node N1 is not pulled down based on a signal applied to the node N2. The pull-down circuit 3c includes a resistor R1, a switch SW1, and a control circuit 4c. The resistor R1 and the switch SW1 are connected in series. For example, one end of the resistor R1 is connected to the node N1, the other end of the resistor R1 is connected to one end of the switch SW1, and the other end of the switch SW1 is grounded. In other words, one end of the switch SW1 is connected to the node N1 via the resistor R1, and a ground voltage GND is applied to the other end of the switch SW1. The control circuit 4c receives the signal CLK applied to the node N2 and counts the toggles of the signal CLK. When the count value of the toggles exceeds a preset number of determinations, for example, 10 times, the control circuit 4c turns off the switch SW1. The count value is reset at regular intervals. The control circuit 4c turns on the switch SW1 if the toggle count value does not exceed a preset determination count until the count value finishes a cycle and is reset.

[0068] <3-2> Operation The operation of the semiconductor device 1c according to the third embodiment will be described. Fig. 8 is a timing chart showing an example of the operation of the semiconductor device 1c according to the third embodiment. Fig. 8 shows the operation when noise is applied to the terminal TEN, and the operation of the semiconductor device 1c being switched when an H-level signal is applied to the terminal TEN.

[0069] In Fig. 8, the timing chart starts when the terminal TEN is switched from an L level applied by the preceding device to a high impedance state. In this state, the voltage VEN is 0V, the voltage VOUT is 0V, and the switch SW1 is on. Since the switch SW1 is on, the node N1 is pulled down to 0V by the pull-down circuit 3c. Since the voltage of the node N1 is 0V, i.e., the L level, the output circuit 2b is off and the voltage VOUT is 0V.

[0070] At time t31, noise is applied to the terminal TEN, and the voltage VEN rises sharply. For example, the peak of the voltage VEN exceeds 1 / 2 of the voltage VDD. After that, the voltage VEN drops and becomes 0V at time t32. The period from time t31 to time t32 is, for example, several μsec. The period from time t31 to time t32 is shorter than the time required for the control circuit 4c to count the toggles of the signal CLK from 0 to the determination number. Therefore, the switch SW1 maintains the ON state during the period from time t31 to time t32. The output circuit 2b may output, for example, two toggles of the signal CLK in response to the noise during the period from time t31 to time t32, but maintains the output of 0V in the example shown in FIG. 8.

[0071] During the period from time t32 to time t33, no change occurs in the situation, so the voltage VEN is maintained at 0 V, the voltage VOUT is maintained at 0 V, and the switch SW1 is maintained in the on state.

[0072] At time t33, the preceding device connected to terminal TEN outputs voltage VDD as an H level, and voltage VEN becomes voltage VDD. After time t33, voltage VEN is maintained at voltage VDD. Because voltage VEN becomes higher than 1 / 2 of voltage VDD, output circuit 2b starts outputting signal CLK at time t33. Note that, because control circuit 4c is not able to count toggles of the clock signal at time t33, switch SW1 remains on.

[0073] At time t34, the number of toggles of the signal CLK counted by the control circuit 4c exceeds the determination count, so the switch SW1 changes from the on state to the off state. With the switch SW1 in the off state, the power consumed by the pull-down circuit 3c decreases. Specifically, the power consumed by the resistor R1 is no longer consumed. Since the output circuit 2b continues to output the signal CLK even after time t34, the count value of the control circuit 4c exceeds the determination count, and the switch SW1 remains in the off state.

[0074] <3-3> Effects According to the semiconductor device 1c of the third embodiment described above, it is possible to suppress malfunctions caused by noise while suppressing power consumption, similar to the semiconductor device 1 of the first embodiment. The effects of the semiconductor device 1c of the third embodiment will be described in detail below.

[0075] The semiconductor device 1c according to the third embodiment includes a control circuit 4c that counts the toggles of a clock signal. The semiconductor device 1c according to the third embodiment waits until the toggle count exceeds a determination number after the control signal goes high and the output circuit 2b outputs the signal CLK, and then disconnects the pull-down circuit 3c. In other words, the pull-down circuit 3c monitors the output of the output circuit 2b to generate a wait time. By appropriately setting the determination number, it is possible to set a wait time that matches the operation timing of the circuit.

[0076] Due to this waiting time, the semiconductor device 1c according to the third embodiment maintains the connection of the pull-down circuit 3c when there is an instantaneous voltage rise due to noise. In contrast, when a control signal is applied and the output circuit 2b continues to operate for a period of time longer than the count value exceeds the determination number, the pull-down circuit 3c is disconnected. Thus, the semiconductor device 1c according to the third embodiment can reduce power consumption while suppressing malfunctions due to noise.

[0077] <3-4> Variations In the third embodiment, the control circuit 4c of the pull-down circuit 3c counts the toggles of the clock signal. The configuration of the control circuit 4c is not limited to this. For example, the control circuit 4c may process the clock signal with a low-pass filter and determine the presence or absence of the clock signal by judging the processed signal with a comparator. FIG. 9 is a block diagram showing a specific example of the configuration of the semiconductor device according to the first modification of the third embodiment. The semiconductor device 1d according to the first modification of the third embodiment is different from the semiconductor device 1c according to the third embodiment in that the pull-down circuit 3c is replaced with a pull-down circuit 3d including a control circuit 4d instead of the control circuit 4c.

[0078] The pull-down circuit 3d includes a resistor R1, a switch SW1, and a control circuit 4d. One end of the resistor R1 is connected to a node N1. The other end of the resistor R1 is connected to one end of a switch SW1. The other end of the switch SW1 is grounded. The control circuit 4d includes a comparator 40, a voltage source 41b, a resistor R4, and a capacitor 43. One end of the resistor R4 is connected to a node N2. The other end of the resistor R2 is connected to one electrode of the capacitor 43 and an inverting input terminal of the comparator 40. The other electrode of the capacitor 43 is grounded. The positive output terminal of the voltage source 41b is connected to the non-inverting input terminal of the comparator 40. The negative output terminal of the voltage source 41b is grounded. The voltage source 41b outputs a voltage VREF4. The voltage VREF4 is lower than the voltage VDD and higher than the ground voltage GND, for example, the voltage VREF4 is smaller than 1 / 2 of the voltage VDD. The output terminal of the comparator 40 is connected to the switch SW1. The switch SW1 is turned on when the output of the comparator 40 is at H level, and is turned off when the output of the comparator 40 is at L level.

[0079] The resistor R4 and the capacitor 43 form a low-pass filter. The input terminal of this low-pass filter is one terminal of the resistor R4, and the output terminal is the other terminal of the resistor R4 and one electrode of the capacitor 43. When the signal CLK output by the output circuit 2c passes through this filter, it is converted into a DC voltage with a height that is approximately half the amplitude of the signal CLK. The comparator 40 compares this DC voltage with the voltage VREF4, making it possible to determine whether the signal CLK is being output.

[0080] Even if the pull-down circuit 3d is configured in this way, the same effects as those of the semiconductor device 1c according to the third embodiment can be obtained.

[0081] <4> Fourth embodiment The configuration of the semiconductor device according to the fourth embodiment differs from that of the semiconductor device according to the first embodiment in that the output circuit 2 is replaced with an output circuit 2c, and the pull-down circuit 3 is replaced with a pull-up circuit 5. The following describes the differences between the semiconductor device 1e according to the fourth embodiment and the first embodiment.

[0082] <4-1> Configuration 10 is a block diagram showing an example of a configuration of a semiconductor device 1e according to the fourth embodiment. In the semiconductor device 1e according to the fourth embodiment, the output circuit 2 of the semiconductor device 1 described in the first embodiment is replaced with an output circuit 2c, and the pull-down circuit 3 is replaced with a pull-up circuit 5.

[0083] A semiconductor device 1e according to the fourth embodiment is a load switch having a slew rate control function and supplying power to a load.

[0084] The semiconductor device 1e includes terminals TEN and TOUT, an output circuit 2c, and a pull-up circuit 5. The terminal TEN is a control signal input terminal of the semiconductor device 1e. The terminal TEN is connected to a node N1. A control signal is applied to the terminal TEN from a previous stage circuit (not shown) provided outside the semiconductor device 1e. The terminal TOUT is an output terminal of the semiconductor device 1e. Power is supplied from the terminal TOUT to the outside of the semiconductor device 1e. The terminal TOUT is connected to a node N2.

[0085] The output circuit 2c is a circuit that realizes the function of the semiconductor device 1e as a load switch. A voltage VDD, which is a power supply voltage, and a ground voltage GND are applied to the output circuit 2c. The output circuit 2c is connected to each of the nodes N1 and N2. The output circuit 2c switches between an ON state (second state) in which the voltage VDD is output to the node N2 and an OFF state (first state) in which the voltage VDD is not output to the node N2 according to the logic level of the node N1. Specifically, the output circuit 2c is in the ON state when the logic level of the node N1 is at the L level, and is in the OFF state when the logic level of the node N1 is at the H level. The output circuit 2c has a slew rate control function. That is, the output circuit 2c controls the rising speed of the voltage that switches the output voltage from 0V (a state in which no voltage is output) to the voltage VDD when switching from the OFF state to the ON state. More specifically, the output circuit 2c is configured so that it takes, for example, 30 μsec or more to reach ½ of the final voltage from 0 V, that is, to reach ½ of the voltage VDD from 0 V.

[0086] The pull-up circuit 5 pulls up the node N1. Specifically, the pull-up circuit 5 switches between an ON state in which the node N1 is pulled up and an OFF state in which the node N1 is not pulled up, based on the voltage of the node N2. The pull-up circuit 5 includes a resistor R5, a switch SW2, and a control circuit 6. The resistor R5 and the switch SW2 are connected in series. In the example shown in FIG. 10, one end of the resistor R1 is connected to the node N1, the other end of the resistor R1 is connected to one end of the switch SW1, and a voltage VDD is applied to the other end of the switch SW1. In other words, one end of the switch SW2 is connected to the node N1 via the resistor R5, and a voltage VDD, which is a power supply voltage, is applied to the other end of the switch SW2. The control circuit 6 controls the switch SW1 based on the voltage of the node N2. Specifically, when the control circuit 6 detects that the output circuit 2c is outputting a voltage equal to or higher than a preset threshold to the node N2, it turns off the switch SW2. When the control circuit 6 detects that the output circuit 2c is not outputting a voltage equal to or higher than the threshold to the node N2, the control circuit 6 turns on the switch SW2.

[0087] FIG. 11 is a block diagram showing a specific example of the configuration of the output circuit 2c and the control circuit 6 according to the fourth embodiment. As shown in FIG. 11, the output circuit 2c according to the fourth embodiment is different from the output circuit 2 according to the first embodiment in that the non-inverting logic circuit 20 is replaced with an inverting logic circuit 20a. A voltage VDD and a ground voltage GND are applied to the inverting logic circuit 20a. An input signal terminal of the inverting logic circuit 20a is connected to a node N1, and a signal output terminal is connected to the gates of the transistors MP1 and MN1. The inverting logic circuit 20a detects the logic level of the node N1, inverts the detected logic level, and applies a voltage based on the inverted logic level to the gates of the transistors MP1 and MN1. For example, when an H-level voltage is applied to the node N1, the inverting logic circuit 20a outputs an L-level voltage. Also, for example, when an L-level voltage is applied to the node N1, the inverting logic circuit 20a outputs an H-level voltage. The other configurations of the output circuit 2c are the same as those of the output circuit 2 according to the first embodiment.

[0088] Continuing to refer to FIG. 11, the configuration of the control circuit 6 included in the pull-up circuit 5 will be described. As shown in FIG. 11, the control circuit 6 according to the fourth embodiment includes a comparator 60 and a voltage source 61. The voltage source 61 outputs a voltage VREF5. The voltage VREF5 is higher than the ground voltage GND and lower than the voltage VDD. The voltage VREF5 is, for example, 1 / 2 the voltage VDD. The positive output terminal of the voltage source 61 is connected to the non-inverting input terminal of the comparator 60. The negative output terminal of the voltage source 61 is grounded.

[0089] The inverting input terminal of the comparator 60 is connected to the node N2. The output terminal of the comparator 60 is connected to the switch SW2. The switch SW2 is controlled based on the output of the comparator 60. More specifically, when the output of the comparator 60 is at H level, the switch SW2 is in the ON state. When the output of the comparator 60 is at L level, the switch SW2 is in the OFF state.

[0090] <4-2>Operation The operation of the semiconductor device 1e according to the fourth embodiment will be described. Fig. 12 is a timing chart showing an example of the operation of the semiconductor device 1e according to the fourth embodiment. Fig. 12 shows the operation when noise is applied to the terminal TEN, and the operation of the semiconductor device 1e is switched when an L-level signal is applied to the terminal TEN. Fig. 12 shows, from the top, the states of the voltage VEN, the voltage VOUT, and the switch SW2.

[0091] In Fig. 12, the timing chart starts when the terminal TEN is switched from a state in which the preceding device applies an H level to a high impedance state. In this state, the voltage VEN is voltage VDD, the voltage VOUT is 0V, and the switch SW2 is on. Since the switch SW2 is on, the node N1 is pulled up to the voltage VDD by the pull-up circuit 5. Since the voltage of the node N1 is voltage VDD, i.e., the H level, the output circuit 2c is in the off state, and the voltage VOUT is 0V.

[0092] At time t41, noise is applied to the terminal TEN, causing the voltage VEN to suddenly drop. For example, the peak of the drop in the voltage VEN falls below 1 / 2 of the voltage VDD. Thereafter, the voltage VEN rises and becomes the voltage VDD at time t42. The period from time t41 to time t42 is, for example, several μsec. The period from time t41 to time t42 is shorter than the time it takes for the output of the output circuit 2c to switch from 0V to the voltage VDD. Therefore, the output circuit 2c maintains an output of 0V. Since the voltage VOUT is maintained at 0V, the switch SW2 also maintains an on state during the period from time t41 to time t42.

[0093] During the period from time t42 to time t43, no change occurs in the situation, so the voltage VEN is maintained at the voltage VDD, the voltage VOUT is maintained at 0 V, and the switch SW2 is maintained in the on state.

[0094] At time t43, the previous stage device connected to terminal TEN outputs 0V as an L level, and voltage VEN becomes 0V. After time t43, voltage VEN is maintained at 0V. Because voltage VEN becomes lower than 1 / 2 of voltage VDD, output circuit 2c starts outputting voltage VDD at time t43. During the period from time t43 to time t45, voltage VOUT rises from 0V to voltage VDD with the slew rate controlled by output circuit 2c. Note that at time t43, voltage VOUT is lower than voltage VREF5, and switch SW2 remains on.

[0095] At time t44, the voltage VOUT becomes greater than the voltage VREF5, and the switch SW2 changes from the on state to the off state. After time t44, the switch SW2 maintains the off state. As the switch SW2 turns off, the power consumed by the pull-up circuit 5 decreases. Specifically, the power consumed by the resistor R5 is no longer consumed. Note that the period from time t43 to time t44 is the time required for the voltage VOUT to rise from 0V to 1 / 2 the voltage VDD, which is the final voltage, and is therefore 30 μsec or more.

[0096] At time t45, the voltage VOUT reaches the voltage VDD and the increase of the voltage VOUT stops. After time t45, the voltage VOUT is maintained at the voltage VDD.

[0097] <4-3> Effects According to the semiconductor device 1e of the fourth embodiment described above, it is possible to suppress malfunctions caused by noise and reduce power consumption, similar to the semiconductor device 1 of the first embodiment. The effects of the semiconductor device 1e of the fourth embodiment will be described in detail below.

[0098] In the semiconductor device 1e according to the fourth embodiment, the slew rate of the output voltage of the output circuit 2c is controlled, as in the semiconductor device 1 according to the first embodiment. Therefore, even if the voltage of the node N1 drops instantaneously due to noise, the pull-up circuit 5 maintains the state in which the node N1 is pulled up. Also, when an L-level control signal is applied to the node N1 and the output circuit 2c makes the voltage of the node N2 higher than the threshold, the pull-up circuit 5 turns off the switch SW2, and the pull-up circuit 5 puts the node N1 in a state in which it is not pulled up. Therefore, the semiconductor device 1e according to the fourth embodiment can suppress power consumption while suppressing malfunctions due to noise.

[0099] Furthermore, like the semiconductor device 1 according to the first embodiment, the semiconductor device 1e according to the fourth embodiment waits from when the control signal goes to L level until the output of the output circuit 2c actually exceeds the threshold, and then disconnects the pull-up circuit 5. In other words, the pull-up circuit 5 generates a wait time by monitoring the output of the output circuit 2c. This makes it possible to set the wait time according to the operation timing of the circuit.

[0100] <5> Other variations In the above embodiment and modified examples, the pull-down circuit and the pull-up circuit include resistors. The pull-down circuit and the pull-up circuit are not limited to this. The pull-down circuit and the pull-up circuit may include a current source instead of a resistor.

[0101] 13 is a block diagram showing an example of the configuration of a semiconductor device according to a second modification of the first embodiment. The semiconductor device 1f according to the second modification of the first embodiment is different from the semiconductor device 1 according to the first embodiment in that the pull-down circuit 3 is replaced with a pull-down circuit 3e.

[0102] The pull-down circuit 3e according to the second modification of the first embodiment differs from the pull-down circuit 3 according to the first embodiment in that the resistor R1 is replaced with a current source CS6. The current source CS6 is connected to a node N1. The current source CS6 is connected to one end of a switch SW1. The current source CS6 is configured to pass a current from the node N1 to one end of the switch SW1. The other configurations are the same as those of the pull-down circuit 3 according to the first embodiment.

[0103] In this way, even if a current source is used instead of a resistor, the pull-down circuit 3e according to the second modification of the first embodiment functions in the same way as the pull-down circuit 3 according to the first embodiment.

[0104] 14 is a block diagram showing an example of a configuration of a semiconductor device according to a first modification of the fourth embodiment. The semiconductor device 1g according to the first modification of the fourth embodiment differs from the semiconductor device 1e according to the fourth embodiment in that the pull-up circuit 5 is replaced with a pull-up circuit 5a.

[0105] The pull-up circuit 5a according to the first modification of the fourth embodiment differs from the pull-up circuit 5 according to the fourth embodiment in that the resistor R5 is replaced with a current source CS7. The current source CS7 is connected to a node N1. The current source CS7 is connected to one end of a switch SW2. The current source CS7 is configured to pass a current from one end of the switch SW2 to the node N1. The other configurations are the same as those of the pull-up circuit 5 according to the fourth embodiment.

[0106] In this way, even if a current source is used instead of a resistor, the pull-up circuit 5a according to the first modification of the fourth embodiment functions in the same way as the pull-up circuit 5 according to the fourth embodiment.

[0107] In the above embodiment, the pull-down circuit includes a switch. In the first modification of the first embodiment, a single N-channel transistor is used as a specific example of the switch. The configuration of the pull-down circuit is not limited to this. For example, the switch SW1 of the pull-down circuit may be configured by combining an N-channel transistor and a P-channel transistor.

[0108] 15 is a block diagram showing an example of the configuration of a semiconductor device according to a third modification of the first embodiment. The semiconductor device 1h according to the third modification of the first embodiment is different from the semiconductor device 1 according to the first embodiment in that the pull-down circuit 3 is replaced with a pull-down circuit 3f.

[0109] The pull-down circuit 3f according to the third modification of the first embodiment includes a resistor R1, transistors MN9 and MP10, an inverter INV1, and a control circuit 4e. The transistor MN9 is an N-channel transistor. The transistor MP10 is a P-channel transistor. One end of the resistor R1 is connected to a node N1. The other end of the resistor R1 is connected to the drain of the transistor MN9 and the source of the transistor MP10. The source of the transistor MN9 and the drain of the transistor MP10 are grounded. The gate of the transistor MN9 is connected to the input end of the inverter INV1. The output end of the inverter INV1 is connected to the gate of the transistor MP10. The input end of the control circuit 4e is connected to a node N2. The output end of the control circuit 4e is connected to the gate of the transistor MN9 and the input end of the inverter INV1. The control circuit 4e controls the voltages of the gate of the transistor MN9 and the input end of the inverter INV1 based on the voltage of the node N2. Specifically, when the control circuit 4e detects that the output circuit 2 is outputting a voltage equal to or greater than a preset threshold to the node N2, the control circuit 4e sets the voltages at the gate of the transistor MN9 and the input terminal of the inverter INV1 to the L level. When the control circuit 4e detects that the output circuit 2 is not outputting a voltage equal to or greater than the threshold to the node N2, the control circuit 4e sets the voltages at the gate of the transistor MN9 and the input terminal of the inverter INV1 to the H level.

[0110] In this way, even if the N-channel transistor MN9 and the P-channel transistor MP10 are combined as the switch SW1, the pull-down circuit 3f according to the third modification of the first embodiment functions in the same manner as the pull-down circuit 3 according to the first embodiment.

[0111] In the above embodiment, the pull-up circuit includes a switch. The pull-up circuit is not limited to this. For example, the switch SW2 of the pull-up circuit may be configured using a P-channel transistor, or may be configured by combining an N-channel transistor and a P-channel transistor.

[0112] 16 is a block diagram showing an example of a configuration of a semiconductor device according to a second modification of the fourth embodiment. The semiconductor device 1i according to the second modification of the fourth embodiment differs from the semiconductor device 1e according to the fourth embodiment in that the pull-up circuit 5 is replaced with a pull-up circuit 5b.

[0113] The pull-up circuit 5b according to the second modification of the fourth embodiment includes a resistor R5, a transistor MP11, and a control circuit 6a. The transistor MP11 is a P-channel transistor. One end of the resistor R5 is connected to a node N1. The other end of the resistor R5 is connected to the drain of the transistor MP11. A voltage VDD is applied to the source of the transistor MP11. An input end of the control circuit 6a is connected to a node N2. An output end of the control circuit 6a is connected to the gate of the transistor MP11. The control circuit 6a controls the voltage of the gate of the transistor MP11 based on the voltage of the node N2. Specifically, when the control circuit 6a detects that the output circuit 2c is outputting a voltage equal to or greater than a preset threshold to the node N2, the control circuit 6a sets the voltage of the gate of the transistor MP11 to an H level. When the control circuit 6a detects that the output circuit 2c is not outputting a voltage equal to or greater than the threshold to the node N2, the control circuit 6a sets the voltage of the gate of the transistor MP11 to an L level.

[0114] In this way, even if the P-channel transistor MP11 is used as the switch SW2, the pull-up circuit 5b according to the second modification of the fourth embodiment functions in the same manner as the pull-up circuit 5 according to the fourth embodiment.

[0115] 17 is a block diagram showing an example of a configuration of a semiconductor device according to a third modification of the fourth embodiment. The semiconductor device 1j according to the third modification of the fourth embodiment differs from the semiconductor device 1e according to the fourth embodiment in that the pull-up circuit 5 is replaced with a pull-up circuit 5c.

[0116] The pull-up circuit 5c according to the third modification of the fourth embodiment includes a resistor R5, transistors MN10 and MP12, an inverter INV2, and a control circuit 6b. The transistor MN10 is an N-channel transistor. The transistor MP12 is a P-channel transistor. One end of the resistor R5 is connected to a node N1. The other end of the resistor R5 is connected to a source of the transistor MN10 and a drain of the transistor MP12. A voltage VDD is applied to the drain of the transistor MN10 and the source of the transistor MP12. The gate of the transistor MN10 is connected to an input end of the inverter INV2. The output end of the inverter INV2 is connected to a gate of the transistor MP12. The input end of the control circuit 6b is connected to a node N2. The output end of the control circuit 6b is connected to a gate of the transistor MN10 and an input end of the inverter INV2. The control circuit 6b controls the voltages of the gate of the transistor MN10 and the input end of the inverter INV2 based on the voltage of the node N2. Specifically, when the control circuit 6b detects that the output circuit 2c is outputting a voltage equal to or greater than a preset threshold to the node N2, the control circuit 6b sets the voltages at the gate of the transistor MN10 and the input terminal of the inverter INV2 to the L level. When the control circuit 6b detects that the output circuit 2c is not outputting a voltage equal to or greater than the threshold to the node N2, the control circuit 6b sets the voltages at the gate of the transistor MN10 and the input terminal of the inverter INV2 to the H level.

[0117] In this way, even if the N-channel transistor MN10 and the P-channel transistor MP12 are combined and used as the switch SW2, the pull-up circuit 5c according to the third modification of the fourth embodiment functions in the same manner as the pull-up circuit 5 according to the fourth embodiment.

[0118] In the above embodiment and modified example, the semiconductor device includes the terminal TOUT. The configuration of the semiconductor device is not limited to this. The terminal TOUT does not have to be provided. Specifically, the output of the output circuit may be used only inside the semiconductor device.

[0119] In this specification, "connected" means electrically connected, and does not exclude, for example, the presence of another element between them. Also, "electrically connected" may be via an insulator as long as it is possible for it to operate in the same way as an electrically connected transistor. Also, in this specification, "on state" means that a voltage equal to or greater than the threshold voltage of the corresponding transistor is applied to the gate of the corresponding transistor. "Off state" means that a voltage less than the threshold voltage of the corresponding transistor is applied to the gate of the corresponding transistor, and does not exclude the flow of a minute current such as a transistor leakage current.

[0120] Note that the above-described embodiment and the above-described modified examples, in whole or in part, may be described as in the following notes, but are not limited to the following. [Appendix 1] a first terminal connected to the first node and receiving an external control signal; a first circuit connected to the first node, switching between a first state in which a first voltage is not output to a second node and a second state in which the first voltage is output to the second node based on a logic level of the first node, and controlling a slew rate of an output voltage when switching from the first state to the second state; a second circuit including a switch having one end connected to the first node and the other end to which a second voltage is applied, the second circuit controlling the switch based on the voltage of the second node; A semiconductor device comprising: [Appendix 2] the second voltage is a ground voltage; The semiconductor device of claim 1, wherein the second circuit brings the switch into a disconnected state when the voltage of the second node is higher than a third voltage, and brings the switch into a connected state when the voltage of the second node is lower than the third voltage. [Appendix 3] the second voltage is a power supply voltage; The semiconductor device of claim 1, wherein the second circuit brings the switch into a disconnected state when the voltage of the second node is higher than a third voltage, and brings the switch into a connected state when the voltage of the second node is lower than the third voltage. [Appendix 4] the second voltage is a ground voltage; the second circuit further includes an inverter having an input terminal connected to the second node; the switch is a first transistor, and an output terminal of the inverter is connected to a gate of the first transistor; 2. The semiconductor device according to claim 1. [Appendix 5] 5. The semiconductor device according to claim 1, wherein the first voltage is equal to a power supply voltage applied to the first circuit. [Appendix 6] 5. The semiconductor device according to claim 1, wherein the first voltage is lower than a power supply voltage applied to the first circuit. [Appendix 7] a first terminal connected to the first node and receiving an external control signal; a first circuit that switches between a first state in which a first signal is not output to a second node and a second state in which the first signal is output to the second node based on a logic level of the first node; a second circuit including a switch having one end connected to the first node and the other end to which a second voltage is applied, the second circuit controlling the switch based on the first signal applied to the second node; A semiconductor device comprising: [Appendix 8] 8. The semiconductor device according to claim 7, wherein the second circuit counts toggles of the first signal applied to the second node, and controls the switch based on the counted number. [Appendix 9] 8. The semiconductor device according to claim 7, wherein the second circuit further includes a low-pass filter having an input terminal connected to the second node, and controls the switch based on an output of the low-pass filter. [Appendix 10] The second circuit further includes a resistive element connected in series with the one end of the switch. 10. The semiconductor device according to claim 1, [Appendix 11] the second circuit further includes a current source connected in series with the one end of the switch. 10. The semiconductor device according to claim 1,

[0121] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0122] 1... semiconductor device, 2... output circuit, 3... pull-down circuit, 4... control circuit, TEN, TOUT... terminals, R1... resistor, SW1... switch.

Claims

1. a first terminal connected to the first node and receiving an external control signal; a first circuit connected to the first node, switching between a first state in which a first voltage is not output to a second node and a second state in which the first voltage is output to the second node based on a logic level of the first node, and controlling a slew rate of an output voltage when switching from the first state to the second state; a second circuit including a switch having one end connected to the first node and the other end to which a second voltage is applied, the second circuit controlling the switch based on the voltage of the second node; A semiconductor device comprising:

2. the second voltage is a ground voltage; 2. The semiconductor device according to claim 1, wherein the second circuit brings the switch into a non-connected state when the voltage at the second node is higher than a third voltage, and brings the switch into a connected state when the voltage at the second node is lower than the third voltage.

3. the second voltage is a power supply voltage; 2. The semiconductor device according to claim 1, wherein the second circuit brings the switch into a non-connected state when the voltage at the second node is higher than a third voltage, and brings the switch into a connected state when the voltage at the second node is lower than the third voltage.

4. the second voltage is a ground voltage; the second circuit further includes an inverter having an input terminal connected to the second node; the switch is a first transistor, and an output terminal of the inverter is connected to a gate of the first transistor; The semiconductor device according to claim 1 .

5. 2. The semiconductor device according to claim 1, wherein said first voltage is equal to a power supply voltage applied to said first circuit.

6. 2. The semiconductor device according to claim 1, wherein said first voltage is lower than a power supply voltage applied to said first circuit.

7. a first terminal connected to the first node and receiving an external control signal; a first circuit that switches between a first state in which a first signal is not output to a second node and a second state in which the first signal is output to the second node based on a logic level of the first node; a second circuit including a switch having one end connected to the first node and the other end to which a second voltage is applied, the second circuit controlling the switch based on the first signal applied to the second node; A semiconductor device comprising:

8. 8. The semiconductor device according to claim 7, wherein the second circuit counts toggles of the first signal applied to the second node, and controls the switch based on the counted number.

9. 8. The semiconductor device according to claim 7, wherein said second circuit further includes a low-pass filter having an input terminal connected to said second node, and controls said switch based on an output of said low-pass filter.

10. the second circuit further includes a resistive element connected in series with the one end of the switch. The semiconductor device according to claim 1 .

11. the second circuit further includes a current source connected in series with the one end of the switch. The semiconductor device according to claim 1 .

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