Semiconductor light-emitting device

Abstract

To provide a semiconductor light-emitting device capable of improving a light output when a high-current is implanted.SOLUTION: A semiconductor light-emitting device 1 comprises: a current constriction layer 15; and a semiconductor light-emitting lamination body 20. The semiconductor light-emitting lamination body 20 is arranged onto the current constriction layer 15, and includes a bottom surface 20a in contact with the current constriction layer 15. The current constriction layer 15 contains: an insulation layer 16; and a plurality of conductive parts 17. The plurality of conductive parts 17 are arranged in the insulation layer 16, and in contact with the bottom surface 20a. An area ratio of the plurality of conductive parts 17 to the bottom surface 20a is 7% or more and 15% or less.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor light emitting devices. [Background technology]

[0002] Japanese Patent Application Laid-Open No. 2020-65041 (Patent Document 1) discloses a semiconductor light emitting device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-65041 A [Summary]

[0004] An object of the present disclosure is to provide a semiconductor light emitting device that can improve light output when a high current is injected.

[0005] The semiconductor light emitting device of the present disclosure includes a current confinement layer and a semiconductor light emitting stack. The semiconductor light emitting stack is disposed on the current confinement layer and has a bottom surface in contact with the current confinement layer. The current confinement layer includes an insulating layer and a plurality of conductive portions. The plurality of conductive portions are disposed in the insulating layer and in contact with the bottom surface. The area ratio of the plurality of conductive portions to the bottom surface is 7% or more and 15% or less. The area ratio is the ratio of a second area of ​​the plurality of conductive portions overlapping the bottom surface in a plan view of the bottom surface to a first area of ​​the bottom surface. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor light emitting device according to an embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view of the semiconductor light-emitting device according to the embodiment taken along the cross-sectional line II-II shown in FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor light emitting device according to the embodiment. [Figure 4]FIG. 4 is a schematic enlarged partial cross-sectional view showing a step subsequent to the step shown in FIG. 3 in the method for manufacturing the semiconductor light emitting device according to the embodiment. [Figure 5] FIG. 5 is a schematic enlarged partial cross-sectional view showing a step subsequent to the step shown in FIG. 4 in the method for manufacturing the semiconductor light emitting device according to the embodiment. [Figure 6] FIG. 6 is a schematic enlarged partial cross-sectional view showing a step subsequent to the step shown in FIG. 5 in the method for manufacturing the semiconductor light emitting device according to the embodiment. [Figure 7] FIG. 7 is a schematic partial enlarged cross-sectional view showing a step subsequent to the step shown in FIG. 6 in the method for manufacturing the semiconductor light emitting device according to the embodiment. [Figure 8] FIG. 8 is a schematic enlarged partial cross-sectional view showing a step subsequent to the step shown in FIG. 7 in the method for manufacturing the semiconductor light emitting device according to the embodiment. [Figure 9] FIG. 9 is a schematic partial enlarged cross-sectional view showing a step subsequent to the step shown in FIG. 8 in the method for manufacturing the semiconductor light emitting device according to the embodiment. [Figure 10] FIG. 10 is a schematic partial enlarged cross-sectional view showing a step subsequent to the step shown in FIG. 9 in the method for manufacturing the semiconductor light emitting device according to the embodiment. [Figure 11] FIG. 11 is a schematic enlarged partial cross-sectional view showing a step subsequent to the step shown in FIG. 10 in the method for manufacturing the semiconductor light emitting device according to the embodiment. [Figure 12] FIG. 12 is a graph showing the relationship between the area ratio of the plurality of conductive portions to the bottom surface of the semiconductor light emitting laminate and the light output of the semiconductor light emitting device. [Figure 13] FIG. 13 is a graph showing the relationship between the carrier concentration in the p-type contact layer and the forward voltage of the semiconductor light emitting device. [Figure 14] FIG. 14 is a schematic plan view of a semiconductor light emitting device according to a first modified example of the embodiment. [Figure 15] FIG. 15 is a schematic plan view of a semiconductor light emitting device according to a second modification of the embodiment. [Figure 16] 16 is a schematic plan view of a semiconductor light emitting device according to a third modification of the embodiment.

[0007] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated. At least some of the configurations of the embodiments described below may be combined in any manner.

[0008] 1 and 2, a semiconductor light emitting device 1 according to an embodiment will be described. The semiconductor light emitting device 1 is, for example, a light emitting diode (LED). The semiconductor light emitting device 1 includes a substrate 10, an anode electrode 13, a reflective layer 14, a current constriction layer 15, a semiconductor light emitting stack 20, and a cathode electrode 40.

[0009] The substrate 10 includes a main surface 11 and a main surface 12 opposite to the main surface 11. The substrate 10 is, for example, p ++ The substrate may be a semiconductor substrate such as a silicon (Si) substrate, or a conductive substrate such as a metal substrate containing at least one of aluminum (Al), copper (Cu), gold (Au), or silver (Ag).

[0010] The reflective layer 14 is disposed on the primary surface 11 of the substrate 10. The reflective layer 14 is disposed on the surface of the current confinement layer 15 opposite to the semiconductor light-emitting stack 20. The reflective layer 14 reflects light emitted from the semiconductor light-emitting stack 20. The thickness of the reflective layer 14 is, for example, 0.1 μm to 3.0 μm. The reflective layer 14 is formed of, for example, Au or an alloy containing Au. The reflective layer 14 may be a single layer of an Au layer, a single layer of an Au alloy layer, a laminate of an Au layer and another metal layer, or a laminate of an Au alloy layer and another metal layer. When the reflective layer 14 is a laminate, the outermost surface of the reflective layer 14 that comes into contact with the semiconductor light-emitting stack 20 is preferably formed of an Au layer or an Au alloy layer (e.g., a gold-beryllium-nickel (AuBeNi) alloy, etc.). When the reflective layer 14 is a laminate, the reflective layer 14 is, for example, a laminate of Au (on the current confinement layer 15 side) / Ti (on the substrate 10 side).

[0011] The reflective layer 14 may be formed by bonding a growth substrate 45 (see FIG. 6) to the substrate 10 and joining a first metal layer 14a (see FIG. 6) to a second metal layer 14b (see FIG. 6). Therefore, a boundary (bonding surface) between the first metal layer 14a and the second metal layer 14b may be present in the reflective layer 14. Furthermore, when the reflective layer 14 is formed of multiple metal materials, there may not be a clear boundary between the multiple metal materials, and the compositions of the multiple metal materials may gradually change in the thickness direction of the reflective layer 14.

[0012] The current confinement layer 15 is disposed on the reflective layer 14. The current confinement layer 15 includes an insulating layer 16 and a plurality of conductive portions 17. The insulating layer 16 is made of, for example, silicon dioxide (SiO2).

[0013] The plurality of conductive portions 17 are disposed in the insulating layer 16. Specifically, the plurality of conductive portions 17 are formed in a plurality of through holes formed in the insulating layer 16. The plurality of conductive portions 17 are, for example, a plurality of conductive pillars. The plurality of conductive portions 17 are in contact with the reflective layer 14 and the bottom surface 20a of the semiconductor light-emitting stack 20, electrically connecting the reflective layer 14 and the semiconductor light-emitting stack 20. Specifically, the plurality of conductive portions 17 are in contact with the reflective layer 14 and the p-type contact layer 22, electrically connecting the reflective layer 14 and the p-type contact layer 22. In a plan view of the main surface 11, each of the plurality of conductive portions 17 has a diameter of, for example, 5 μm or more and 15 μm or less. In a plan view of the main surface 11, the plurality of conductive portions 17 may be uniformly disposed.

[0014] The plurality of conductive portions 17 are formed of, for example, a metal material such as Au or an alloy such as a gold-beryllium (AuBe) alloy. When the wavelength of light emitted from the semiconductor light emitting layers (first semiconductor light emitting layer 25 and second semiconductor light emitting layer 33) is 800 nm or more and 1000 nm or less, the plurality of conductive portions 17 made of Au have a higher reflectivity for the light emitted from the semiconductor light emitting layers than the plurality of conductive portions 17 made of AuBe. Therefore, the plurality of conductive portions 17 made of Au increase the light output of the semiconductor light emitting device 1.

[0015] The semiconductor light emitting stack 20 includes a bottom surface 20a in contact with the current confinement layer 15. A mesa structure 2 may be formed in the semiconductor light emitting stack 20. The semiconductor light emitting stack 20 includes a first p-type layer 21, a first semiconductor light emitting layer 25, a first n-type layer 26, a tunnel diode layer 28, a second p-type layer 31, a second semiconductor light emitting layer 33, and a second n-type layer 35.

[0016] The first p-type layer 21 is disposed on the current confinement layer 15. The first p-type layer 21 includes a p-type contact layer 22, a p-type window layer 23, and a first p-type cladding layer 24.

[0017] The p-type contact layer 22 is disposed on the current confinement layer 15. The p-type contact layer 22 is a low-resistance layer for making ohmic contact with the plurality of conductive portions 17. The p-type contact layer 22 is, for example, the layer with the highest p-type dopant concentration or carrier concentration (hole concentration) among the first p-type layer 21. The p-type contact layer 22 is, for example, an AlGaAsP layer doped with a p-type dopant such as carbon (C), or a GaP layer doped with a p-type dopant such as zinc (Zn). The carrier concentration (hole concentration) of the p-type contact layer 22 is, for example, 1×10 19 cm -3 The carrier concentration (hole concentration) of the p-type contact layer 22 is 2×10 19 cm -3 May be more than 5 x 10 19 cm -3 It may be more than that.

[0018] The p-type window layer 23 is disposed on the p-type contact layer 22. The p-type window layer 23 is, for example, an AlGaAs layer doped with carbon (C).

[0019] The first p-type cladding layer 24 is disposed on the p-type window layer 23. The first p-type cladding layer 24 is, for example, an AlGaAs layer doped with carbon (C). The Al composition ratio of the first p-type cladding layer 24 is higher than the Al composition ratio of the p-type window layer 23.

[0020] The first semiconductor light emitting layer 25 is disposed on the first p-type layer 21 (first p-type cladding layer 24). The first semiconductor light emitting layer 25 is a layer that emits light when a current is injected into the semiconductor light emitting device 1. The wavelength of the light emitted from the first semiconductor light emitting layer 25 is, for example, not less than 800 nm and not more than 1000 nm. The first semiconductor light emitting layer 25 is, for example, a multiple quantum well (MQW) layer. The first semiconductor light emitting layer 25 is, for example, an MQW layer in which InGaAs well layers and AlGaAsP barrier layers are alternately stacked. The first semiconductor light emitting layer 25 is, for example, an undoped layer.

[0021] The first n-type layer 26 is disposed on the first semiconductor light emitting layer 25. The first n-type layer 26 is, for example, a first n-type cladding layer 27. The first n-type cladding layer 27 is, for example, an AlGaAs layer doped with selenium (Se). The Al composition ratio of the first n-type cladding layer 27 is high, similar to the Al composition ratio of the first p-type cladding layer 24.

[0022] The tunnel diode layer 28 is disposed between the first n-type layer 26 and the second p-type layer 31, and is in contact with the first n-type layer 26 and the second p-type layer 31. The tunnel diode layer 28 passes holes injected from the anode electrode 13 toward the second semiconductor light emitting layer 33, and passes electrons injected from the cathode electrode 40 toward the first semiconductor light emitting layer 25. Therefore, electrons and holes are injected into each of the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33, causing the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33 to emit light.

[0023] The tunnel diode layer 28 is, for example, an n-type cladding layer disposed on the first n-type cladding layer 27. ++ Tunnel layer 29 and n ++ p disposed on the tunnel layer 29 ++ and a tunnel layer 30. ++ The tunnel layer 29 is, for example, an AlGaAs layer doped with tellurium (Te). ++ The tunnel layer 30 is, for example, an AlGaAs layer doped with carbon (C). ++ The Al composition ratio and p of the tunnel layer 29 ++The Al composition ratio of the tunnel layer 30 is low, similar to the Al composition ratio of the p-type window layer 23 .

[0024] The second p-type layer 31 is a tunnel diode layer 28 (p ++ The second p-type layer 31 is disposed on the first p-type cladding layer 24. The second p-type layer 31 is, for example, a second p-type cladding layer 32. The second p-type cladding layer 32 is, for example, an AlGaAs layer doped with carbon (C). The Al composition ratio of the second p-type cladding layer 32 is high, similar to the Al composition ratio of the first p-type cladding layer 24.

[0025] The second semiconductor light emitting layer 33 is disposed on the second p-type layer 31 (second p-type cladding layer 32). The second semiconductor light emitting layer 33 is a layer that emits light when a current is injected into the semiconductor light emitting device 1. The wavelength of the light emitted from the second semiconductor light emitting layer 33 is, for example, 800 nm or more and 1000 nm or less. For example, the second semiconductor light emitting layer 33 has the same configuration as the first semiconductor light emitting layer 25 and emits light having the same wavelength as the first semiconductor light emitting layer 25. Since light is emitted from the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33, the optical output of the semiconductor light emitting device 1 increases. The second semiconductor light emitting layer 33 is, for example, a multiple quantum well (MQW) layer. The second semiconductor light emitting layer 33 is, for example, an MQW layer in which InGaAs well layers and AlGaAsP barrier layers are alternately stacked. The second semiconductor light emitting layer 33 is, for example, an undoped layer.

[0026] The second n-type layer 35 is disposed on the second semiconductor light emitting layer 33. The second n-type layer 35 includes a second n-type cladding layer 36, an n-type window layer 37, and an n-type contact layer 38.

[0027] The second n-type cladding layer 36 is disposed on the second semiconductor light emitting layer 33. The second n-type cladding layer 36 is, for example, an AlGaAs layer doped with selenium (Se). The Al composition ratio of the second n-type cladding layer 36 is high, similar to the Al composition ratio of the first n-type cladding layer 27.

[0028] The n-type window layer 37 is disposed on the second n-type cladding layer 36. The n-type window layer 37 is, for example, an AlGaAs layer doped with silicon (Si). The Al composition ratio of the n-type window layer 37 is lower than that of the second n-type cladding layer 36. The Al composition ratio of the n-type window layer 37 is low, similar to that of the p-type window layer 23. A concave-convex structure 37a is formed on the surface of the n-type window layer 37 in a portion exposed from the n-type contact layer 38 and the cathode electrode 40. The concave-convex structure 37a improves the light extraction efficiency of the semiconductor light emitting device 1.

[0029] The n-type contact layer 38 is disposed on the n-type window layer 37. The n-type contact layer 38 is a low-resistance layer for making ohmic contact with the cathode electrode 40. The n-type contact layer 38 is, for example, the layer with the highest n-type dopant concentration or carrier concentration (electron concentration) among the second n-type layer 35. The n-type contact layer 38 is, for example, a GaAs layer doped with silicon (Si).

[0030] The anode electrode 13 is disposed on the main surface 12 of the substrate 10. The anode electrode 13 is formed of, for example, a metal material such as Au or an alloy containing Au. In this embodiment, the anode electrode 13 is, for example, a Ti / Au laminate (on the substrate 10 side).

[0031] The cathode electrode 40 is formed of, for example, a metal material such as Au or an alloy containing Au. In this embodiment, the cathode electrode 40 is, for example, a stack of AuGeNi / Au (on the n-type contact layer 38 side). The cathode electrode 40 includes a pad electrode 41 and a branched electrode 42. A conductive wire (not shown) is bonded to the pad electrode 41 to inject current into the semiconductor light-emitting device 1. The branched electrode 42 extends in a branch-like manner from the pad electrode 41 so as to divide the semiconductor light-emitting stack 20 into a plurality of regions in a plan view of the main surface 11.

[0032] The area ratio of the plurality of conductive portions 17 to the bottom surface 20a of the semiconductor light emitting stack 20 is 7% or more and 15% or less. In this specification, the area ratio of the plurality of conductive portions 17 to the bottom surface 20a of the semiconductor light emitting stack 20 is the ratio of the area of ​​the plurality of conductive portions 17 overlapping the bottom surface 20a of the semiconductor light emitting stack 20 in a planar view of the main surface 11 to a first area of ​​the bottom surface 20a of the semiconductor light emitting stack 20. The planar view of the main surface 11 of the substrate 10 is the planar view of the bottom surface 20a of the semiconductor light emitting stack 20.

[0033] An example of a method for manufacturing the semiconductor light emitting device 1 of this embodiment will be described with reference to FIGS.

[0034] 3, the semiconductor light-emitting stack 20 is formed on a growth substrate 45. The growth substrate 45 includes a support substrate 46 and an etching stop layer 47. The support substrate 46 is made of, for example, GaAs. The etching stop layer 47 is disposed on the support substrate 46. The etching stop layer 47 is made of, for example, AlInGaP. The etching stop layer 47 is formed on the support substrate 46 by an epitaxial growth method such as metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0035] The semiconductor light-emitting stack 20 is formed on a growth substrate 45 (etching stop layer 47) by epitaxial growth, such as metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The layers are, in order from the growth substrate 45 side, an n-type contact layer 38, an n-type window layer 37, a second n-type cladding layer 36, a second semiconductor light-emitting layer 33, a second p-type cladding layer 32, and a p ++ Tunnel layer 30, n ++ The semiconductor light emitting stack 20 is formed by stacking the tunnel layer 29, the first n-type cladding layer 27, the first semiconductor light emitting layer 25, the first p-type cladding layer 24, the p-type window layer 23 and the p-type contact layer 22.

[0036] 4, the current confinement layer 15 is formed on the p-type contact layer 22. Specifically, an insulating layer 16 is formed on the p-type contact layer 22 by chemical vapor deposition (CVD). A plurality of through holes are formed in the insulating layer 16 by etching a portion of the insulating layer 16. A plurality of conductive portions 17 are formed in the plurality of through holes by vapor deposition. In this way, the current confinement layer 15 is formed.

[0037] 5, a first metal layer 14a is formed on the current confinement layer 15 by vapor deposition. The first metal layer 14a is made of Au or an alloy containing Au. At least the outermost surface of the first metal layer 14a is made of Au. In this way, a stack including the semiconductor light-emitting stack 20, the current confinement layer 15, and the first metal layer 14a is formed on the growth substrate 45.

[0038] Referring to FIG. 6, the substrate 10 is bonded to the laminate formed on the growth substrate 45. Specifically, a second metal layer 14b is formed on the main surface 11 of the substrate 10 by vapor deposition. The second metal layer 14b is made of Au or an alloy containing Au. At least the outermost surface of the second metal layer 14b is made of Au. Then, the first metal layer 14a and the second metal layer 14b are bonded together. The first metal layer 14a and the second metal layer 14b are bonded together by, for example, thermocompression bonding. The first metal layer 14a and the second metal layer 14b are bonded together to form the reflective layer 14.

[0039] Referring to FIG. 7, the growth substrate 45 is removed. Specifically, the support substrate 46 is removed by wet etching. The etching stop layer 47 is hardly etched by this wet etching and functions as an etching stop layer against this wet etching. Then, the etching stop layer 47 is removed by another etching. In this way, the growth substrate 45 is removed.

[0040] 8, the n-type contact layer 38 is patterned. Specifically, a resist 48 is formed on the n-type contact layer 38. The resist 48 has, for example, the same pattern as the cathode electrode 40. Then, the n-type contact layer 38 is etched using the resist 48 as a mask. A portion of the n-type contact layer 38 exposed from the resist 48 is removed to form the n-type contact layer 38 having the same pattern as the cathode electrode 40. The n-type window layer 37 is exposed from the resist 48 and the n-type contact layer 38 through the openings in the resist 48 and the n-type contact layer 38.

[0041] 9, for example, by frost treatment, a concave-convex structure 37a is formed on the surface of the n-type window layer 37 exposed from the resist 48. The frost treatment may be performed by wet etching or dry etching.

[0042] 10, the resist 48 is removed. The cathode electrode 40 is formed on the n-type contact layer 38. The cathode electrode 40 is formed, for example, by vapor deposition of a metal layer and removing a portion of the metal layer by a lift-off method.

[0043] 11, a mesa structure 2 is formed in the semiconductor light-emitting stack 20. The mesa structure 2 is formed, for example, by wet etching the side surface of the semiconductor light-emitting stack 20. Then, an anode electrode 13 is formed on the main surface 12 of the substrate 10, for example, by vapor deposition. In this way, the semiconductor light-emitting device 1 is obtained.

[0044] The operation of the semiconductor light emitting device 1 of this embodiment will be described.

[0045] A voltage higher than that of the cathode electrode 40 is applied to the anode electrode 13, and a forward bias voltage V f A forward current I is applied to the anode electrode 13 and the cathode electrode 40. f In this embodiment, the forward current I fis a high current of 3 amperes or more, and the light output of the semiconductor light emitting device 1 is a high light output of 1 W or more. Holes are injected into the semiconductor light emitting device 1 from the anode electrode 13 through the substrate 10, the reflective layer 14, and the plurality of conductive portions 17. Electrons are injected into the semiconductor light emitting device 1 from the cathode electrode 40. The electrons and holes tunnel through the tunnel diode layer 28. As a result, carriers (electrons and holes) are injected into the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33.

[0046] Electrons and holes combine in the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33, causing light to be emitted from the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33. The light emitted from the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33 is reflected by the reflective layer 14 and the plurality of conductive portions 17. The light emitted from the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33 is extracted to the outside of the semiconductor light emitting device 1 by the uneven structure 37a and the like. In this way, the semiconductor light emitting device 1 emits light.

[0047] 12 and 13, the operation of the semiconductor light emitting device 1 of this embodiment will be described. The sample of the semiconductor light emitting device 1 includes a reflective layer 14 made of Au and a p-type contact layer 22 made of AlGaAsP doped with carbon (C). In the sample, the diameter of each of the plurality of conductive portions 17 is 10 μm, the bottom surface 20a of the semiconductor light emitting stack 20 has a size of 1020 μm × 1020 μm in plan view of the main surface 11, and the wavelength of light emitted from the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33 is 940 nm.

[0048] 12 is a graph showing the relationship between the area ratio of the plurality of conductive portions 17 to the bottom surface 20a of the semiconductor light-emitting stack 20 and the light output of the semiconductor light-emitting device 1. The light output of the semiconductor light-emitting device 1 shown in FIG. f is the optical output P5 of the semiconductor light emitting device 1 when the above-mentioned

[0049] 12, when the area ratio is less than 7%, the light output P5 of the semiconductor light emitting device 1 is lower than the light output P5 of the semiconductor light emitting device 1 when the area ratio is 7% or more and 15% or less, for the following reasons.

[0050] The holes do not pass through the insulating layer 16 of the current confinement layer 15, but pass through the multiple conductive portions 17 of the current confinement layer 15. Therefore, when the area ratio is less than 7%, the holes are locally concentrated in the semiconductor light-emitting stack 20. When a high current such as 5 amperes is injected into the semiconductor light-emitting device 1, non-radiative recombination of carriers (electrons and holes) occurs more frequently, and the luminous efficiency of the semiconductor light-emitting device 1 decreases. That is, when the area ratio is less than 7%, the droop phenomenon occurs. On the other hand, when the area ratio is 7% or more, the local concentration of holes in the semiconductor light-emitting stack 20 is alleviated. Therefore, even when a high current such as 5 amperes is injected into the semiconductor light-emitting device 1, the non-radiative recombination of carriers is suppressed, and the luminous efficiency of the semiconductor light-emitting device 1 increases. That is, when the area ratio is 7% or more, the droop phenomenon is suppressed.

[0051] 12, when the area ratio is greater than 15%, the light output P5 of the semiconductor light emitting device 1 is lower than when the area ratio is between 7% and 15%. This is because when the area ratio is greater than 15%, the current density in the semiconductor light emitting stack 20 becomes too low, resulting in a decrease in the light emitting efficiency of the semiconductor light emitting device 1.

[0052] 13 shows the relationship between the carrier concentration (hole concentration) of the p-type contact layer 22 and the forward voltage V f 13 is a graph showing the relationship between the forward voltage V f is the forward current I of 1 ampere f When the semiconductor light emitting device 1 is injected with f1is.

[0053] As shown in FIG. 13, the carrier concentration of the p-type contact layer 22 is 1.0×10 19 cm -3 In the above case, the ohmic contact between the plurality of conductive portions 17 and the p-type contact layer 22 is improved, so that the forward voltage V f For example, by forming the p-type contact layer 22 from AlGaAsP doped with carbon (C), it becomes possible to dope more carbon (C) into the p-type contact layer 22 made of AlGaAsP, and the carrier concentration of the p-type contact layer 22 becomes 1.0×10 19 cm -3 The above can be easily achieved.

[0054] On the other hand, when the carrier concentration of the p-type contact layer 22 is 1.0×10 19 cm -3 If the ohmic contact between the plurality of conductive portions 17 and the p-type contact layer 22 is insufficient, the forward voltage V f For example, if the p-type contact layer 22 is made of GaP doped with zinc (Zn), the carrier concentration of the p-type contact layer 22 increases to 1.0×10 19 cm -3 It will be less than that.

[0055] A modification of this embodiment will now be described.

[0056] The arrangement of the branched electrodes 42 is not limited to the arrangement of the branched electrodes 42 shown in Fig. 1. For example, the arrangement of the branched electrodes 42 shown in Fig. 14 or the arrangement of the branched electrodes 42 shown in Fig. 15 may also be used.

[0057] 16, the plurality of conductive portions 17 may be arranged non-uniformly in a plan view of the principal surface 11. For example, as shown in FIG. 16, a first area ratio of the plurality of conductive portions 17 in the central portion of the semiconductor light emitting stack 20 may be smaller than a second area ratio of the plurality of conductive portions 17 in the peripheral portion of the semiconductor light emitting stack 20. The first area ratio is the ratio of the area of ​​the plurality of conductive portions 17 overlapping the central portion of the semiconductor light emitting stack 20 in a plan view of the principal surface 11 to the area of ​​the central portion of the semiconductor light emitting stack 20. The second area ratio is the ratio of the area of ​​the plurality of conductive portions 17 overlapping the peripheral portion of the semiconductor light emitting stack 20 in a plan view of the principal surface 11 to the area of ​​the peripheral portion of the semiconductor light emitting stack 20.

[0058] The semiconductor light emitting device 1 includes two semiconductor light emitting layers (first semiconductor light emitting layer 25 and second semiconductor light emitting layer 33), but may include one semiconductor light emitting layer or three or more semiconductor light emitting layers. The semiconductor light emitting device 1 may be a laser diode (LD).

[0059] The effects of the semiconductor light emitting device 1 of this embodiment will be described.

[0060] The semiconductor light emitting device 1 of the present disclosure includes a current constriction layer 15 and a semiconductor light emitting stack 20. The semiconductor light emitting stack 20 is disposed on the current constriction layer 15 and has a bottom surface 20a in contact with the current constriction layer 15. The current constriction layer 15 includes an insulating layer 16 and a plurality of conductive portions 17. The plurality of conductive portions 17 are disposed in the insulating layer 16 and in contact with the bottom surface 20a. The area ratio of the plurality of conductive portions 17 to the bottom surface 20a is 7% or more and 15% or less. The area ratio is the ratio of a second area of ​​the plurality of conductive portions 17 overlapping the bottom surface 20a in a plan view of the bottom surface 20a to a first area of ​​the bottom surface 20a.

[0061] Because the area ratio is 7% or more, local concentration of holes in the semiconductor light-emitting stack 20 is alleviated. Even when a high current is injected into the semiconductor light-emitting device 1, non-radiative recombination of carriers (electrons and holes) is suppressed, and the light-emitting efficiency of the semiconductor light-emitting device 1 increases. That is, when the area ratio is 7% or more, the droop phenomenon is suppressed. Furthermore, because the area ratio is 15% or less, the current density in the semiconductor light-emitting stack 20 is prevented from becoming too low. The light-emitting efficiency of the semiconductor light-emitting device 1 increases. Therefore, the light output of the semiconductor light-emitting device 1 improves when a high current is injected.

[0062] In the semiconductor light emitting device 1 of this embodiment, the plurality of conductive portions 17 are made of gold (Au).

[0063] Therefore, the reflectivity of the plurality of conductive portions 17 for the light emitted from the semiconductor light emitting layer (first semiconductor light emitting layer 25) increases. The light is reflected by the plurality of conductive portions 17 and emitted to the outside of the semiconductor light emitting device 1 without being absorbed by the substrate 10. The light output of the semiconductor light emitting device 1 increases.

[0064] In the semiconductor light emitting device 1 of this embodiment, the semiconductor light emitting stack 20 includes a p-type contact layer 22 that is in contact with the plurality of conductive portions 17. The carrier concentration of the p-type contact layer 22 is 1×10 19 cm -3 That's all.

[0065] Therefore, the ohmic contact between the plurality of conductive portions 17 and the p-type contact layer 22 is improved. f decreases.

[0066] In the semiconductor light emitting device 1 of this embodiment, the p-type contact layer 22 is made of p-AlGaAsP doped with a p-type dopant.

[0067] Therefore, the carrier concentration of the p-type contact layer 22 is set to 1×10 19 cm -3The ohmic contact between the plurality of conductive portions 17 and the p-type contact layer 22 is improved. f decreases.

[0068] The semiconductor light emitting device 1 of this embodiment further includes a reflective layer 14 disposed on the surface of the current confinement layer 15 opposite to the semiconductor light emitting stack 20. The plurality of conductive portions 17 are in contact with the reflective layer 14.

[0069] The light emitted from the semiconductor light-emitting stack 20 is reflected by the reflective layer 14 and is emitted to the outside of the semiconductor light-emitting device 1 without being absorbed by the substrate 10. The light output of the semiconductor light-emitting device 1 increases.

[0070] In the semiconductor light emitting device 1 of this embodiment, the plurality of conductive portions 17 are uniformly arranged in a plan view of the bottom surface 20a.

[0071] This allows the semiconductor light emitting device 1 to emit light uniformly, increasing the light output of the semiconductor light emitting device 1.

[0072] In the semiconductor light emitting device 1 of this embodiment, a first area ratio of the plurality of conductive portions 17 in the central portion of the semiconductor light emitting stack 20 is smaller than a second area ratio of the plurality of conductive portions 17 in the peripheral portion of the semiconductor light emitting stack 20. The first area ratio is the ratio of the area of ​​the plurality of conductive portions 17 overlapping the central portion of the semiconductor light emitting stack 20 in a plan view of the bottom surface 20a to the area of ​​the central portion of the semiconductor light emitting stack 20. The second area ratio is the ratio of the area of ​​the plurality of conductive portions 17 overlapping the peripheral portion of the semiconductor light emitting stack 20 in a plan view of the bottom surface 20a to the area of ​​the peripheral portion of the semiconductor light emitting stack 20.

[0073] This reduces the concentration of carriers in the center of the semiconductor light-emitting stack 20. Even when a high current is injected into the semiconductor light-emitting device 1, non-radiative recombination of carriers is suppressed, thereby increasing the light-emitting efficiency of the semiconductor light-emitting device 1. The droop phenomenon is suppressed. The light output of the semiconductor light-emitting device 1 when a high current is injected is improved.

[0074] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) a current confinement layer; a semiconductor light emitting stack disposed on the current confinement layer and having a bottom surface in contact with the current confinement layer; the current confinement layer includes an insulating layer and a plurality of conductive portions disposed in the insulating layer and in contact with the bottom surface; an area ratio of the plurality of conductive portions to the bottom surface is 7% or more and 15% or less; The area ratio is a ratio of a second area of ​​the plurality of conductive portions overlapping the bottom surface in a plan view of the bottom surface to a first area of ​​the bottom surface. (Appendix 2) 2. The semiconductor light-emitting device according to claim 1, wherein the conductive portions are made of gold. (Appendix 3) the semiconductor light emitting stack includes a p-type contact layer in contact with the plurality of conductive portions, The carrier concentration of the p-type contact layer is 1×10 19 cm -3 The semiconductor light emitting device according to claim 1 or 2. (Appendix 4) 4. The semiconductor light-emitting device according to claim 3, wherein the p-type contact layer is formed of p-AlGaAsP doped with a p-type dopant. (Appendix 5) a reflective layer disposed on a surface of the current confinement layer opposite to the semiconductor light emitting stack, 5. The semiconductor light emitting device according to claim 1, wherein the conductive portions are in contact with the reflective layer. (Appendix 6) 6. The semiconductor light emitting device according to claim 1, wherein the plurality of conductive portions are uniformly arranged in the plan view of the bottom surface. (Appendix 7) a first area ratio of the plurality of conductive portions in a central portion of the semiconductor light emitting stack is smaller than a second area ratio of the plurality of conductive portions in a peripheral portion of the semiconductor light emitting stack; the first area ratio is a ratio of an area of ​​the plurality of conductive portions overlapping the central portion of the semiconductor light emitting stack in the planar view of the bottom surface to an area of ​​the central portion of the semiconductor light emitting stack, A semiconductor light-emitting device described in any one of Appendix 1 to Appendix 5, wherein the second area ratio is the ratio of the area of ​​the multiple conductive portions that overlap the peripheral portion of the semiconductor light-emitting stack in the planar view of the bottom surface to the area of ​​the peripheral portion of the semiconductor light-emitting stack.

[0075] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0076] 1 semiconductor light emitting device, 2 mesa structure, 10 substrate, 11, 12 main surface, 13 anode electrode, 14 reflective layer, 14a first metal layer, 14b second metal layer, 15 current confinement layer, 16 insulating layer, 17 conductive portion, 20 semiconductor light emitting stack, 20a bottom surface, 21 first p-type layer, 22 p-type contact layer, 23 p-type window layer, 24 first p-type cladding layer, 25 first semiconductor light emitting layer, 26 first n-type layer, 27 first n-type cladding layer, 28 tunnel diode layer, 29 n ++ Tunnel layer, 30 p ++ Tunnel layer, 31 second p-type layer, 32 second p-type cladding layer, 33 second semiconductor light-emitting layer, 35 second n-type layer, 36 second n-type cladding layer, 37 n-type window layer, 37a uneven structure, 38 n-type contact layer, 40 cathode electrode, 41 pad electrode, 42 branched electrode, 45 growth substrate, 46 support substrate, 47 etching stop layer, 48 resist.

Claims

1. A current confinement layer; a semiconductor light emitting stack disposed on the current confinement layer and having a bottom surface in contact with the current confinement layer; the current confinement layer includes an insulating layer and a plurality of conductive portions disposed in the insulating layer and in contact with the bottom surface; an area ratio of the plurality of conductive portions to the bottom surface is 7% or more and 15% or less; The area ratio is a ratio of a second area of ​​the plurality of conductive portions overlapping the bottom surface in a plan view of the bottom surface to a first area of ​​the bottom surface.

2. The semiconductor light emitting device according to claim 1 , wherein the conductive portions are made of gold.

3. the semiconductor light emitting stack includes a p-type contact layer in contact with the plurality of conductive portions, The carrier concentration of the p-type contact layer is 1×10 １９ cm －３ The semiconductor light emitting device according to claim 1 .

4. 4. The semiconductor light emitting device according to claim 3, wherein the p-type contact layer is made of p-AlGaAsP doped with a p-type dopant.

5. a reflective layer disposed on a surface of the current confinement layer opposite to the semiconductor light emitting stack, The semiconductor light emitting device according to claim 1 , wherein the conductive portions are in contact with the reflective layer.

6. The semiconductor light emitting device according to claim 1 , wherein the conductive portions are uniformly arranged in the plan view of the bottom surface.

7. a first area ratio of the plurality of conductive portions in a central portion of the semiconductor light emitting stack is smaller than a second area ratio of the plurality of conductive portions in a peripheral portion of the semiconductor light emitting stack; the first area ratio is a ratio of an area of ​​the plurality of conductive portions overlapping the central portion of the semiconductor light emitting stack in the planar view of the bottom surface to an area of ​​the central portion of the semiconductor light emitting stack, 5. The semiconductor light-emitting device according to claim 1, wherein the second area ratio is a ratio of an area of ​​the plurality of conductive portions overlapping the peripheral portion of the semiconductor light-emitting stack in the planar view of the bottom surface to an area of ​​the peripheral portion of the semiconductor light-emitting stack.

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