Control device, detection method, and detection program

Abstract

To provide a control device, a detection method, and a detection program capable of detecting whether a power source is cut off during writing of data for writing in a non-rewritable storage unit, and capable of restoring the stored data for writing.SOLUTION: A control device causes a processor to acquire data for writing and store the data for writing in a first area of a non-volatile storage unit with an error detection code as first data for writing, store the first data for writing in a second area of a non-rewritable storage unit as second data for writing, and store the second data for writing in a third area of a non-volatile storage unit as third data for writing.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a control device, a detection method, and a detection program. [Background technology]

[0002] Generally, data that should not be deleted, such as logs, may be stored in a non-rewritable storage unit such as an OTP (One Time Programmable ROM). There are cases where the power supply is cut off while data to be written is being stored in the non-rewritable storage unit. If the power supply is cut off while data to be written is being written to the non-rewritable storage unit, the data may be stored in an incomplete state, an incorrect state, or in other abnormal states.

[0003] For such a case, there is known a technique for checking whether or not the correct write data is stored. For example, Patent Document 1 describes a technique that has a first area in which circuit information is stored and a second area in which circuit information different from the circuit information in the first area is stored, and when the power is turned on, reads the circuit information from the first area and checks whether the correct circuit information is stored in the second area using the circuit information. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 01-265343 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the conventional technology, there are cases where it is not possible to determine whether the stored write data is normal or not. For example, in the technology described in Patent Document 1, if a power interruption occurs when storing circuit information in the first area and the stored circuit information becomes abnormal, it is not possible to detect whether the circuit information stored in the second area is normal or not. In this way, if it is not possible to properly detect whether the circuit information is normal or not, a problem occurs in that the abnormal write data cannot be repaired. Therefore, there is a demand for a technology that can properly detect whether an abnormality occurs in the stored write data due to a power interruption while the write data is being written.

[0006] The present disclosure aims to provide a control device, a detection method, and a detection program that can detect whether power has been cut off while writing write data to a non-rewritable memory unit, and enable the stored write data to be restored. [Means for solving the problem]

[0007] In order to achieve the above object, the control device of the present disclosure has a processor that acquires write data, adds an error detection code to the write data as first write data and stores the write data in a first area of ​​a non-volatile memory unit, stores the first write data in a second area of ​​a non-rewritable memory unit as second write data, and stores the second write data in a third area of ​​the non-volatile memory unit as third write data.

[0008] In addition, in order to achieve the above-mentioned object, the detection method disclosed herein is a detection method for detecting whether or not power is cut off during a process in which a processor of a control device stores write data in a non-rewritable memory unit, and includes the steps of: acquiring the write data, adding an error detection code to the write data as first write data and storing the write data in a first area of ​​a non-volatile memory unit, storing the first write data in a second area of ​​the non-rewritable memory unit as second write data, storing the second write data in a third area of ​​the non-volatile memory unit as third write data, and determining whether or not power is cut off when writing based on a comparison result obtained by comparing the first write data, the second write data, and the third write data.

[0009] In addition, in order to achieve the above-mentioned object, the detection program disclosed herein causes a processor of a control device, which detects whether or not power was cut off during a process of storing write data in a non-rewritable memory unit, to acquire write data, add an error detection code to the write data as first write data and store the data in a first area of ​​a non-volatile memory unit, store the first write data in a second area of ​​the non-rewritable memory unit as second write data, store the second write data in a third area of ​​the non-volatile memory unit as third write data, and execute a process of determining whether or not power was cut off when writing based on a comparison result of comparing the first write data, the second write data, and the third write data. Effect of the Invention

[0010] According to the present disclosure, it is possible to detect whether or not power has been cut off while writing data to be written to a non-rewritable storage section, and to make it possible to recover the stored data to be written. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram illustrating an example of a configuration of a memory system according to an embodiment. [Diagram 2]11 is a flowchart illustrating an example of the flow of a writing process. [Diagram 3] 11 is a flowchart illustrating an example of the flow of a detection process. [Figure 4] 11 is a flowchart illustrating an example of the flow of a normality determination process. [Diagram 5] 13 is a flowchart illustrating an example of the flow of a first writing determination process. [Figure 6] 13 is a flowchart illustrating an example of the flow of a second writing determination process. [Figure 7] 13 is a flowchart illustrating an example of the flow of a third writing determination process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the technology of the present disclosure is not limited to the following embodiments.

[0013] First, an example of the configuration of a memory system of this embodiment will be described with reference to Fig. 1. Fig. 1 shows a block diagram showing an example of the configuration of a memory system 1 of this embodiment. The memory system 1 of this embodiment includes a control device 10, a nonvolatile memory 12, and an OTP (One Time Programmable ROM) 14. The nonvolatile memory 12 of this embodiment is an example of a nonvolatile storage unit of the present disclosure, and the OTP 14 of this embodiment is an example of a non-rewritable storage unit of the present disclosure.

[0014] In the memory system 1, the write data WD is stored in the OTP 14 under the control of the control device 10. The write data stored in the OTP 14 is output to the outside of the memory system 1 and used by a device external to the memory system 1.

[0015] The control device 10 includes a CPU (Central Processing Unit) 11, and the CPU 11 performs processing for writing the write data WD to the OTP 14. Note that the CPU 11 of the present embodiment is an example of a processor of the present disclosure.

[0016] The non-volatile memory 12 and the OTP 14 are provided in the same semiconductor device (not shown). The non-volatile memory 12 includes a first area 20 and a third area 23 as areas to which data is written. The write data WD is written in the first area 20 under the control of the CPU 11 of the control device 10. In this embodiment, a checksum such as CRC (Cyclic Redundancy Checking) is added to the write data WD and the write data WD is stored in the first area 20. In this embodiment, the write data WD stored in the first area 20 is referred to as "first write data WD_1". The checksum in this embodiment is an example of an error detection code in the present disclosure.

[0017] Further, the second write data WD_2 read from the second area 22 of the OTP 14 is written to the third area 23 under the control of the CPU 11 of the control device 10. In this embodiment, the second write data WD_2 stored in the third area 23 is referred to as "third write data WD_3." In this embodiment, the second write data WD_2 is stored in the third area 23 with a checksum such as CRC added.

[0018] In this embodiment, the addresses of the first area 20 and the third area 23 are output to the control device 10. The CPU 11 can recognize the areas in which the first write data WD_1 and the third write data WD_3 are stored by referring to the addresses.

[0019] The OTP 14 is a storage unit in which written data cannot be rewritten. The OTP 14 includes a second area 22. First write data WD_1 read from the first area 20 of the non-volatile memory 12 is written to the second area 22 under the control of the CPU 11 of the control device 10. In this embodiment, the write data WD stored in the second area 22 is referred to as "second write data."

[0020] In this embodiment, the address of the second area 22 is output to the control device 10. The CPU 11 can recognize the area in which the second data to write WD_2 is stored by referring to the address.

[0021] In the following description, the data to write WD, the first data to write WD_1, the second data to write WD_2, and the third data to write WD_3 will be collectively referred to simply as "data to write" when they are not distinguished from one another.

[0022] In this manner, in the memory system 1 of the present embodiment, first, under the control of the CPU 11 of the control device 10, the write data WD is written to the first area 20 of the nonvolatile memory 12 and stored as the first write data WD_1. Next, under the control of the CPU 11, the first write data WD_1 read from the first area 20 of the nonvolatile memory 12 is written to the second area 22 of the OTP 14 and stored as the second write data WD_2. Furthermore, under the control of the CPU 11, the second write data WD_2 read from the second area 22 of the OTP 14 is written to the third area 23 of the nonvolatile memory 12 and stored as the third write data WD_3.

[0023] When all the data are written normally, the data to be written WD, the first data to be written WD_1, the second data to be written WD_2, and the third data to be written WD_3 are the same data. On the other hand, when the power is cut off during writing, normal data may not be written. For example, the data to be written may not be written at all, or may be in an incomplete state, and the read value (0 or 1) may differ every time the data is read. That is, when an abnormality such as a power cut off occurs during writing, at least one of the first data to be written WD_1, the second data to be written WD_2, and the third data to be written WD_3 is not normal. Therefore, by comparing the first data to be written WD_1, the second data to be written WD_2, and the third data to be written WD_3, it is possible to determine to which area the power was cut off when writing the data to be written. In addition, when written data, in other words stored data, is said to be "not normal" or "abnormal," this includes cases where the data is different from the original data, as well as cases where the data does not exist.

[0024] Specifically, in the memory system 1 of this embodiment, if a power interruption occurs during writing, the following occurs.

[0025] (1) When power is not cut off when writing write data to any of the first area 20, the second area 22, and the third area 23, i.e., when the write data is written normally to all areas. In this case, the first data to be written WD_1 and the third data to be written WD_3 are the same.

[0026] (2) A case where the power supply is interrupted when the write data WD is written to the first area 20 of the non-volatile memory 12 to become the first write data WD_1. In this case, the second write data WD_2 is different from the first write data WD_1 and is the same as the third write data WD_3, and the first write data WD_1 is abnormal. In this case, the control device 10 writes write data to the first area 20, the second area 22, and the third area 23, thereby recovering the write data stored in each area.

[0027] (3) A case where the power supply is interrupted when the first write data WD_1 is written into the second area 22 of the OTP 14 and becomes the second write data WD_2. In this case, the second write data WD_2 is different from the first write data WD_1 and is the same as the third write data WD_3, and the first write data WD_1 is normal, or the first write data WD_1, the second write data WD_2, and the third write data WD_3 are all different, and the first write data WD_1 is normal. In this case, the control device 10 writes the write data to the second area 22 and the third area 23, thereby recovering the write data stored in the second area 22 and the third area 23.

[0028] (4) A case where the power supply is interrupted when the second write data WD_2 is written to the third area 23 of the non-volatile memory 12 to become the third write data WD_3. In this case, the first write data WD_1 is the same as the second write data WD_2 and is different from the third write data WD_3. In this case, the control device 10 writes the write data to the third area 23, thereby recovering the write data stored in the third area 23.

[0029] Therefore, the control device 10 of this embodiment compares the first write data WD_1, the second write data WD_2, and the third write data WD_3 to determine to which area the power interruption occurred when writing the write data, and repairs the stored write data if necessary.

[0030] The operation of the control device 10 of this embodiment will be described with reference to the drawings. First, with reference to Fig. 2, a write process in which the CPU 11 of the control device 10 writes the write data WD will be described. Fig. 2 shows a flowchart showing an example of the flow of the write process executed by the CPU 11. In this embodiment, the CPU 11 executes a write process program (not shown) stored in the control device 10, thereby executing the write process shown in Fig. 2.

[0031] 2, the CPU 11 acquires the write data WD. The source from which the write data WD is acquired is not limited. For example, the CPU 11 acquires the write data WD from outside the memory system 1.

[0032] In the next step S102, the CPU 11 writes the write data WD to the first area 20 of the non-volatile memory 12 as described above. As a result, the first write data WD_1 is stored in the first area 20 of the non-volatile memory 12.

[0033] In the next step S104, as described above, the CPU 11 writes the first data to be written WD_1 to the second area 22 of the OTP 14. As a result, the second data to be written WD_2 is stored in the second area 22 of the OTP 14.

[0034] In the next step S106, the CPU 11 writes the second data to be written WD_2 to the third area 23 of the non-volatile memory 12 as described above. As a result, the third data to be written WD_3 is stored in the third area 23 of the non-volatile memory 12. When the process of step S106 ends, the write process shown in FIG. 2 ends.

[0035] Next, the detection process, which is a process for detecting whether or not a power interruption has occurred and recovering write data as necessary, will be described with reference to Fig. 3. Fig. 3 shows a flowchart illustrating an example of the flow of the detection process executed by the CPU 11. In this embodiment, the detection process shown in Fig. 3 is executed by the CPU 11 executing a detection process program (not shown) stored in the control device 10. The detection process shown in Fig. 3 is executed, for example, when the control device 10 is powered on.

[0036] In step S200 in Fig. 3, the CPU 11 executes a normality determination process shown in Fig. 4, the details of which will be described later. The normality determination process is a process for determining whether or not the power supply has never been interrupted and the write data has been normally stored in all of the first area 20, the second area 22, and the third area 23.

[0037] In the next step S202, the CPU 11 determines whether or not the power supply has been interrupted.

[0038] If the power supply has not been cut off, the process in step S200 becomes positive, and the detection process shown in Fig. 3 ends. On the other hand, if the power supply has been cut off, the determination in step S202 becomes negative, and the process proceeds to step S204.

[0039] In step S204, the CPU 11 executes a first write determination process shown in Fig. 5, the details of which will be described later. The first write determination process is a process for determining whether or not the power supply was interrupted when the write data WD was written to the first area 20 of the non-volatile memory 12 to become the first write data WD_1, and for recovering the stored write data as necessary.

[0040] In the next step S206, the CPU 11 determines whether or not the power was interrupted when writing the write data WD to the first area 20 of the nonvolatile memory 12 to become the first write data WD_1. If the power was interrupted, the determination in step S206 is affirmative, and the detection process shown in Fig. 3 is terminated. On the other hand, if the power was not interrupted, the determination in step S206 is negative, and the process proceeds to step S208.

[0041] In step S208, the CPU 11 executes a second write determination process shown in Fig. 6, the details of which will be described later. The second write determination process is a process for determining whether or not the power supply was interrupted when the first write data WD_1 was written to the second area 22 of the OTP 14 to become the second write data WD_2, and for recovering the stored write data as necessary.

[0042] In the next step S210, the CPU 11 determines whether or not the power was interrupted when the first write data WD_1 was written to the second area 22 of the OTP 14 to become the second write data WD_2. If the power was interrupted, the determination in step S210 is affirmative, and the detection process shown in Fig. 3 is terminated. On the other hand, if the power was not interrupted, the determination in step S210 is negative, and the process proceeds to step S212.

[0043] In step S212, the CPU 11 executes a third write determination process shown in Fig. 7, the details of which will be described later. The third write determination process is a process for determining whether or not the power supply was interrupted when the second write data WD_2 was written to the third area 23 of the non-volatile memory 12 to become the third write data WD_3, and for recovering the stored write data as necessary. When the process of step S212 ends, the detection process shown in Fig. 3 ends.

[0044] Next, the above-mentioned normality determination process will be described with reference to FIG. In step S300 of the normality determination process in Fig. 4, the CPU 11 determines whether the first data to write WD_1 is the same as the third data to write WD_3. If the first data to write WD_1 and the third data to write WD_3 are not the same, the determination in step S300 is negative, the normality determination process shown in Fig. 4 is terminated, and the process proceeds to step S202 (see Fig. 3) of the detection process described above. On the other hand, if the first data to write WD_1 and the third data to write WD_3 are the same, the determination in step S300 is positive, and the process proceeds to step S302.

[0045] In step S302, the CPU 11 determines that the power was not interrupted when writing the write data to any of the first area 20, the second area 22, and the third area 23. In other words, the CPU 11 determines that the write data was normally written to all of the first area 20, the second area 22, and the third area 23. When the process of step S302 ends, the normality determination process shown in Fig. 4 ends, and the process proceeds to step S202 (see Fig. 3) of the detection process described above.

[0046] Next, the above-mentioned first write determination process will be described with reference to FIG. In step S320 of the first write determination process in Fig. 5, the CPU 11 determines whether or not the second data to be written WD_2 is different from the first data to be written WD_1 and is the same as the third data to be written WD_3. If the second data to be written WD_2 is different from the first data to be written WD_1 and is the same as the third data to be written WD_3, the determination in step S320 is positive, the first write determination process shown in Fig. 5 is terminated, and the process proceeds to step S206 (see Fig. 3) of the detection process described above. On the other hand, if the determination in step S320 is negative, the process proceeds to step S322.

[0047] In step S322, the CPU 11 judges whether the first data for writing WD_1 is normal or not. Specifically, the CPU 11 judges whether the first data for writing WD_1 is normal or not by using the checksum added to the first data for writing WD_1. If the first data for writing WD_1 is normal, the judgment in step S320 is an affirmative judgment, the first write judgment process shown in FIG. 5 is terminated, and the process proceeds to step S206 (see FIG. 3) of the detection process described above. On the other hand, if the judgment in step S322 is a negative judgment, the process proceeds to step S324.

[0048] In step S324, the CPU 11 determines that the power supply has been cut off when the write data WD is written into the first area 20 of the nonvolatile memory 12 to become the first write data WD_1.

[0049] In the next step S326, the CPU 11 writes the write data to all of the first area 20, the second area 22, and the third area 23. That is, the CPU 11 executes the write process shown in Fig. 2 again, and recovers each of the write data stored in the first area 20, the second area 22, and the third area 23. When the process of step S326 ends, the first write determination process shown in Fig. 5 ends, and the process proceeds to step S206 (see Fig. 3) of the detection process described above.

[0050] Next, the above-mentioned second write determination process will be described with reference to FIG.

[0051] In step S340 of the second write determination process in Fig. 6, the CPU 11 determines whether the second write data WD_2 is different from the first write data WD_1 and is the same as the third write data WD_3, or whether the first write data WD_1, the second write data WD_2, and the third write data WD_3 are all different. If the second write data WD_2 is different from the first write data WD_1 and is the same as the third write data WD_3, or if the first write data WD_1, the second write data WD_2, and the third write data WD_3 are all different, the CPU 11 determines that the second write data WD_2 is different from the first write data WD_1 and is the same as the third write data WD_3, and ... third write data WD_3, and the CPU 11 determines that the second write data WD_2 is different from the first write data WD_1 and is the same as the third write data WD_3, and the CPU 11 determines that the first write data WD_1, the second write data WD_2, and the third write data WD_3 are all different, and the CPU 11 determines that the second write determination process in Fig. 6 is ended, and the CPU 11 proceeds to step S210 (see Fig. 3) of the detection process described above. On the other hand, if the determination in step S340 is negative, the process proceeds to step S342.

[0052] In step S342, the CPU 11 judges whether the first data for writing WD_1 is normal or not. Specifically, the CPU 11 judges whether the first data for writing WD_1 is normal or not by using the checksum added to the first data for writing WD_1. If the first data for writing WD_1 is not normal, the judgment in step S340 is a negative judgment, the second write judgment process shown in FIG. 6 is terminated, and the process proceeds to step S210 (see FIG. 3) of the detection process described above. On the other hand, if the judgment in step S342 is a positive judgment, the process proceeds to step S344.

[0053] In step S344, the CPU 11 determines that the power supply has been cut off when the first data to be written WD_1 is written into the second area 22 of the OTP 14 to become second data to be written WD_2.

[0054] In the next step S346, the CPU 11 writes the first data to be written WD_1 to the second area 22 of the OTP 14, thereby recovering the second data to be written WD_2 stored in the second area 22.

[0055] In the next step S348, the CPU 11 writes the second data to be written WD_2 to the third area 23 of the non-volatile memory 12, thereby recovering the third data to be written WD_3 stored in the third area 23. When the process of step S348 ends, the second write determination process shown in Fig. 6 is ended, and the process proceeds to step S210 (see Fig. 3) of the detection process described above.

[0056] The above-mentioned third write determination process will be further described with reference to FIG.

[0057] In step S360 of the third write determination process in Fig. 7, the CPU 11 determines whether the first data to be written WD_1 is the same as the second data to be written WD_2 and different from the third data to be written WD_3. If the first data to be written WD_1 is the same as the second data to be written WD_2 and different from the third data to be written WD_3, the determination in step S360 is positive, and the third write determination process shown in Fig. 7 is terminated. In this case, the above-mentioned detection process is also terminated. On the other hand, if the determination in step S360 is negative, the process proceeds to step S362.

[0058] In step S362, the CPU 11 determines that the power supply has been cut off when the second data to be written WD_2 is to be written into the third area 23 of the nonvolatile memory 12 to become the third data to be written WD_3.

[0059] In the next step S364, the CPU 11 writes the second data to be written WD_2 to the third area 23 of the non-volatile memory 12, thereby recovering the third data to be written WD_3 stored in the third area 23. When the process of step S364 ends, the third write determination process shown in Fig. 7 ends. In this case, the above-mentioned detection process also ends.

[0060] As described above, the CPU 11 of the control device 10 of the above embodiment acquires the write data WD, and stores the write data WD as the first write data WD_1 with a checksum added in the first area 20 of the nonvolatile memory 12. The CPU 11 also stores the first write data WD_1 as the second write data WD_2 in the second area 22 of the OTP 14. Furthermore, the CPU 11 stores the second write data WD_2 in the third area 23 of the nonvolatile memory 12 as the third write data WD_3.

[0061] With the above configuration, the CPU 11 of the control device 10 of this embodiment can compare the first write data WD_1 stored in the first area 20, the second write data WD_2 stored in the second area 22, and the third write data WD_3 stored in the third area 23. Therefore, based on the comparison result, the CPU 11 can detect to which of the first area 20, the second area 22, and the third area 23 the power supply was interrupted when writing the write data, and can restore the stored write data as necessary.

[0062] Therefore, according to the control device 10 of this embodiment, it is possible to detect whether or not the power supply has been cut off while writing write data to a non-rewritable storage unit, and to make it possible to restore the stored write data.

[0063] If the power supply is interrupted while the write data is being written to the non-rewritable storage section, the data may be stored in an incomplete state, an incorrect state, or in an abnormal state. In such a case, the control device 10 of the present embodiment can detect whether the power supply was interrupted while the write data was being written to the non-rewritable storage section, as described above, and can restore the stored write data.

[0064] In the above embodiment, the CPU 11 may store within the control device 10 or output to the outside information regarding whether or not the power supply was cut off, where the power supply was cut off, and in which area the write data stored has been restored.

[0065] In this embodiment, the second data for writing WD_2 is stored as the third data for writing WD_3 in the third area 23 of the non-volatile memory 12 with a checksum added, but the third data for writing WD_3 does not necessarily need to be added with a checksum. By adding a checksum to the third data for writing WD_3 stored in the third area 23 as in this embodiment, the checksum can be used to determine whether data corruption has occurred when transferring data from the outside. The checksum can also be used to determine whether data is abnormal due to a write error when writing data, or due to data rewriting for some reason.

[0066] In the above embodiment, the OTP 14 is used as an example of the non-rewritable storage unit, but the present invention is not limited to this. For example, a fuse may be used as the non-rewritable storage unit.

[0067] The following supplementary notes are further disclosed regarding the above embodiment. (Appendix 1) The processor: Obtain the data to be written, adding an error detection code to the write data as first write data and storing the write data in a first area of ​​a non-volatile storage unit; storing the first data to be written as second data to be written in a second area of ​​a non-rewritable storage unit; The second write data is stored as third write data in a third area of ​​the non-volatile storage unit. Control device.

[0068] (Appendix 2) The processor further comprises: Based on a comparison result obtained by comparing the first write data, the second write data, and the third write data, it is determined whether or not the power supply was interrupted during writing. 2. The control device according to claim 1.

[0069] (Appendix 3) The processor, If it is determined that the first write data and the third write data are identical, it is determined that the power supply was not interrupted during writing. 3. The control device according to claim 2.

[0070] (Appendix 4) The processor, If the first write data and the second write data are different, the second write data and the third write data are identical, and it is determined that the first write data is abnormal based on the error detection code, it is determined that power was interrupted when the first write data was written to the first area. 4. The control device according to claim 2 or 3.

[0071] (Appendix 5) The processor, If it determines that the power supply has been cut off, Obtaining the writing data; The third write data is stored in the first area as the first write data with an error detection code added thereto. 5. The control device according to claim 4.

[0072] (Appendix 6) The processor, If the first write data and the second write data are different, the second write data and the third write data are identical, and it is determined that the first write data is normal based on the error detection code, Or, if the first write data, the second write data, and the third write data are all different, and it is determined that the first write data is normal based on the error detection code, It is determined that the power supply is interrupted when the second write data is written to the second area. 6. The control device according to claim 2,

[0073] (Appendix 7) The processor, If it determines that the power supply has been cut off, storing the first data to be written in the second area as the second data to be written; The second data to be written is stored in the third area as the third data to be written. 7. The control device according to claim 6.

[0074] (Appendix 8) The processor, If the first write data and the second write data are identical and the first write data and the third write data are different, It is determined that the power supply has been interrupted when the third write data is written to the third area. 8. The control device according to any one of claims 2 to 7.

[0075] (Appendix 9) The processor, If it determines that the power supply has been cut off, The second data to be written is stored in the third area as the third data to be written. The control device according to claim 8.

[0076] (Appendix 10) A detection method for detecting whether or not power is interrupted during a process in which a processor of a control device stores write data in a non-rewritable storage unit, comprising: Obtain the data to be written, adding an error detection code to the write data as first write data and storing the write data in a first area of ​​a non-volatile storage unit; storing the first data to be written as second data to be written in a second area of ​​a non-rewritable storage unit; storing the second write data in a third area of ​​the non-volatile storage unit as third write data; Based on a comparison result obtained by comparing the first write data, the second write data, and the third write data, it is determined whether or not the power supply was interrupted during writing. Detection methods.

[0077] (Appendix 11) A processor of the control device detects whether or not power is interrupted during a process of storing write data in a non-rewritable storage unit, Obtain the data to be written, adding an error detection code to the write data as first write data and storing the write data in a first area of ​​a non-volatile storage unit; storing the first data to be written as second data to be written in a second area of ​​a non-rewritable storage unit; storing the second write data in a third area of ​​the non-volatile storage unit as third write data; Based on a comparison result obtained by comparing the first write data, the second write data, and the third write data, it is determined whether or not the power supply was interrupted during writing. A detection program to execute the process. [Explanation of symbols]

[0078] 1. Memory System 10 Control device 11 CPU 12 Non-volatile memory 14 OTP 20. The First Region 22 The Second Area 23 The Third Region

Claims

1. The processor: Obtain the data to be written, adding an error detection code to the write data as first write data and storing the write data in a first area of ​​a non-volatile storage unit; storing the first data to be written as second data to be written in a second area of ​​a non-rewritable storage unit; The second write data is stored as third write data in a third area of ​​the non-volatile storage unit. Control device.

2. The processor further comprises: Based on a comparison result obtained by comparing the first write data, the second write data, and the third write data, it is determined whether or not the power supply was interrupted during writing. The control device according to claim 1 .

3. The processor, If it is determined that the first write data and the third write data are identical, it is determined that the power supply was not interrupted during writing. The control device according to claim 2.

4. The processor, When the first write data and the second write data are different, the second write data and the third write data are identical, and it is determined that the first write data is not normal based on the error detection code, it is determined that the power supply was interrupted when the first write data was written to the first area. The control device according to claim 2.

5. The processor, If it determines that the power supply has been cut off, Obtaining the writing data; The third write data is stored in the first area as the first write data with an error detection code added thereto. The control device according to claim 4.

6. The processor, If the first write data and the second write data are different, the second write data and the third write data are identical, and it is determined that the first write data is normal based on the error detection code, Or, if the first write data, the second write data, and the third write data are all different, and it is determined that the first write data is normal based on the error detection code, It is determined that the power supply has been interrupted when the second write data is written to the second area. The control device according to claim 2.

7. The processor, If it determines that the power supply has been cut off, storing the first data to be written in the second area as the second data to be written; The second data to be written is stored in the third area as the third data to be written. The control device according to claim 6.

8. The processor, When the first write data and the second write data are identical and the first write data and the third write data are different, It is determined that the power supply is interrupted when the third write data is written to the third area. The control device according to claim 2.

9. The processor, If it determines that the power supply has been cut off, The second data to be written is stored in the third area as the third data to be written. The control device according to claim 8.

10. A detection method for detecting whether or not power is interrupted during a process in which a processor of a control device stores write data in a non-rewritable storage unit, comprising: Obtain the data to be written, adding an error detection code to the write data as first write data and storing the write data in a first area of ​​a non-volatile storage unit; storing the first data to be written as second data to be written in a second area of ​​a non-rewritable storage unit; storing the second write data in a third area of ​​the non-volatile storage unit as third write data; Based on a comparison result obtained by comparing the first write data, the second write data, and the third write data, it is determined whether or not the power supply was interrupted during writing. Detection methods.

11. A processor of the control device detects whether or not power is interrupted during a process of storing write data in a non-rewritable storage unit, Obtain the data to be written, adding an error detection code to the write data as first write data and storing the write data in a first area of ​​a non-volatile storage unit; storing the first data to be written as second data to be written in a second area of ​​a non-rewritable storage unit; storing the second write data in a third area of ​​the non-volatile storage unit as third write data; Based on a comparison result obtained by comparing the first write data, the second write data, and the third write data, it is determined whether or not the power supply was interrupted during writing. A detection program to execute the process.

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