Manufacturing method of semiconductor device

Abstract

To reduce the number of steps of a mounting and a solder reflow when manufacturing a semiconductor device 1 in which a plurality of semiconductor chips 3 is bonded to a substrate 2, and which includes a lead frame 4 bonded over onto the plurality of semiconductor chips 3.SOLUTION: By using an on-substrate jig 10 having a separation 10B for a chip positioning to a gap between adjacent semiconductor chips 3 (a first semiconductor chip 3A and a second semiconductor chip 3B), and a lead frame 4 of which a corner part of each semiconductor chip 3 is viewed, and which has a notch 4D having a shape that the separation 10B is penetrated, the lead frame 4 is positioned by using the on-substrate jig 10 before the bonding of each semiconductor chip 3 to a substrate 2, and chip lower solder and chip upper solder are reflow, and thus, the substrate 2, each semiconductor chip 3, and the lead frame 4 are bonded.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] An example of a semiconductor module, which is a type of semiconductor device, is disclosed in Patent Document 1.

[0003] Patent Document 1 describes a semiconductor module in which a plurality of semiconductor chips are bonded onto a substrate, and which has a lead frame bonded across the plurality of semiconductor chips. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2023-3573 A Summary of the Invention [Problem to be solved by the invention]

[0005] Patent Document 1 does not disclose details of the manufacturing method.

[0006] In a conventional method for manufacturing a semiconductor device, when a semiconductor chip is bonded onto a substrate via solder and a lead frame is bonded onto the semiconductor chip via solder, a manufacturing method has been used in which the mounting and solder reflow processes are performed three times, as shown in, for example, FIGS. 10 to 12.

[0007] FIG. 10 is a perspective view illustrating a step of pre-soldering to a lead frame in a conventional method for manufacturing a semiconductor device.

[0008] 10, an upper jig 12 for pre-soldering a lead frame and a lower jig 13 for pre-soldering a lead frame are used to position and mount solder 5A on the chip as solder 5 on the lead frame 4. Then, the solder 5 is reflowed to pre-solder the solder 5A on the chip to the lead frame 4.

[0009] FIG. 11 is a perspective view illustrating a step of positioning a semiconductor chip using an on-substrate jig in a conventional method for manufacturing a semiconductor device.

[0010] 11, first upper-substrate jig 14 and first lower-substrate jig 15 are used to position and mount under-chip solder 5B and under-foot solder 5C as solder 5 on substrate 2, and further position and mount semiconductor chip 3 on under-chip solder 5B. Thereafter, solder 5 is reflowed to bond semiconductor chip 3 onto substrate 2 via under-chip solder 5B, and pre-soldering of under-foot solder 5C is performed on substrate 2.

[0011] FIG. 12 is a perspective view illustrating a step of positioning a lead frame using an on-substrate jig in a conventional method for manufacturing a semiconductor device.

[0012] 12, using a second upper-substrate jig 16 and a second lower-substrate jig 17, the lead frame 4 with the solder on the chip 5A pre-soldered is positioned and mounted on the substrate 2 with the semiconductor chip 3 already bonded and the solder under the feet 5C pre-soldered. Thereafter, the solder 5 is reflowed to bond the lead frame 4 onto the semiconductor chip 3 via the solder on the chip 5A, and also to bond the lead frame 4 onto the substrate 2 via the solder under the feet 5C.

[0013] However, the conventional method for manufacturing a semiconductor device shown in FIGS. 10 to 12 has a problem in that the number of mounting and solder reflow steps is large, and manufacturing takes a long time.

[0014] The problem that the present invention aims to solve is to provide a manufacturing method that reduces the number of mounting and solder reflow steps when manufacturing a semiconductor device in which multiple semiconductor chips 3 are bonded onto a substrate 2 and a lead frame 4 is bonded across the multiple semiconductor chips 3. [Means for solving the problem]

[0015] In order to solve the above-mentioned problems, a manufacturing method of a semiconductor device of the present invention is a manufacturing method of a semiconductor device including: a substrate; a first semiconductor chip bonded to an upper surface of the substrate; a second semiconductor chip disposed adjacent to the first semiconductor chip and bonded to the upper surface of the substrate; and a lead frame bonded to an upper surface of the first semiconductor chip and an upper surface of the second semiconductor chip, the lead frame having an inter-chip connection portion overlapping a gap between the first semiconductor chip and the second semiconductor chip, the method including: positioning the first semiconductor chip and the second semiconductor chip using an on-substrate jig having a partition for chip positioning in the gap between the first semiconductor chip and the second semiconductor chip; the system uses a lead frame having a notch through which the partition penetrates and through which corners of the first semiconductor chip and the second semiconductor chip are visible, and before bonding the first semiconductor chip and the second semiconductor chip to the substrate, the lead frame is positioned using the substrate jig, and chip under-solder provided between the first semiconductor chip and the substrate and between the second semiconductor chip and the substrate, and chip over-solder provided between the first semiconductor chip and the lead frame and between the second semiconductor chip and the lead frame is reflowed to bond the substrate, the first semiconductor chip, the second semiconductor chip, and the lead frame. Effect of the Invention

[0016] According to the present invention, when manufacturing a semiconductor device having a plurality of semiconductor chips 3 bonded onto a substrate 2 and a lead frame 4 bonded across the plurality of semiconductor chips 3, a manufacturing method can be realized which reduces the number of mounting and solder reflow steps. [Brief description of the drawings]

[0017] [Figure 1] 11 is a top view illustrating a step of positioning the semiconductor chip and the lead frame using an on-substrate jig in the manufacturing method of the semiconductor device according to the embodiment. FIG. [Diagram 2] FIG. 2 is an enlarged top view of part A in FIG. 1. [Diagram 3] FIG. 3 is a cross-sectional view taken along line BB in FIG. 2 . [Figure 4] FIG. 2 is a top view illustrating the shape of a lead frame according to an embodiment. [Diagram 5] 11 is a perspective view illustrating a step of pre-soldering to a lead frame in the manufacturing method of the semiconductor device according to the embodiment; FIG. [Figure 6] 11 is a perspective view illustrating a step of positioning a semiconductor chip and a lead frame using an on-substrate jig in the manufacturing method of the semiconductor device according to the embodiment; FIG. [Figure 7] 3A and 3B are a top view and an enlarged view of portions C1 to C4 for explaining the positional relationship between the outer shape of the lead frame and the semiconductor chip according to the embodiment. [Figure 8] 2A and 2B are a top view and a cross-sectional view at EE and FF for explaining the shape of a lead frame according to an embodiment. [Figure 9] FIG. 8 is a cross-sectional view taken along the line DD in FIG. [Figure 10] FIG. 13 is a perspective view illustrating a step of pre-soldering to a lead frame in a conventional method for manufacturing a semiconductor device. [Figure 11] 11 is a perspective view illustrating a step of positioning a semiconductor chip using an on-substrate jig in a conventional method for manufacturing a semiconductor device. [Figure 12] 13 is a perspective view illustrating a step of positioning a lead frame using an on-substrate jig in a conventional method for manufacturing a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In each drawing, the same or similar components are designated by the same reference numerals, and duplicated explanations will be omitted.

[0019] In a conventional method for manufacturing a semiconductor device, as shown in Figures 11 and 12, the process of bonding a semiconductor chip 3 to the upper surface of a substrate 2 and the process of bonding a lead frame 4 to the upper surfaces of the substrate 2 and the semiconductor chip 3 were carried out separately.

[0020] In contrast, in the manufacturing method of the semiconductor device of the embodiment, as shown in Figure 6 described later, the processes of joining the substrate 2, the semiconductor chip 3, and the lead frame 4 are performed all at once, thereby reducing the number of mounting and solder reflow processes.

[0021] Specifically, the manufacturing method for the semiconductor device of this embodiment uses an on-substrate jig 10 having a partition 10B for chip positioning in the gap between adjacent semiconductor chips 3 (a first semiconductor chip 3A and a second semiconductor chip 3B), and a lead frame 4 having a notch 4D through which the partition 10B penetrates and through which the corners of the semiconductor chip 3 are visible, and before bonding the semiconductor chip 3 to the substrate 2, the lead frame 4 is positioned using the on-substrate jig 10, and the solder 5B under the chip and the solder 5A over the chip are reflowed to bond the substrate 2, the semiconductor chip 3, and the lead frame 4.

[0022] The details of this embodiment will be described below.

[0023] Fig. 1 is a top view illustrating a step of positioning a semiconductor chip and a lead frame using a jig on a substrate in a manufacturing method of a semiconductor device according to an embodiment. Fig. 2 is a top view showing an enlarged view of part A in Fig. 1. Fig. 3 is a cross-sectional view taken along line BB in Fig. 2. Fig. 4 is a top view illustrating the shape of a lead frame according to an embodiment. Note that in Fig. 3, the chip-mounted electrodes 3C (see Fig. 2) and the solder 5 (see Figs. 5 and 6 described below) are omitted.

[0024] The semiconductor device 1 of the embodiment has a plurality of semiconductor chips 3 bonded onto a substrate 2, and also has a lead frame 4 bonded across the plurality of semiconductor chips 3.

[0025] More specifically, the semiconductor device 1 of the embodiment has a substrate 2, a first semiconductor chip 3A bonded to the upper surface of the substrate 2, a second semiconductor chip 3B arranged adjacent to the first semiconductor chip 3A and bonded to the upper surface of the substrate 2, and a lead frame 4 having an inter-chip connection portion 4B bonded to the upper surface of the first semiconductor chip 3A and the upper surface of the second semiconductor chip 3B and overlapping a gap 20 between the first semiconductor chip 3A and the second semiconductor chip 3B.

[0026] At the stage shown in Figure 1, positioning has been completed but solder reflow has not yet been performed, so strictly speaking the components have not yet been joined.

[0027] 3, the substrate 2 has an insulating layer 2A, a wiring layer 2B provided on the upper surface side of the insulating layer 2A, and a back-side metal layer 2C provided on the lower surface side of the insulating layer 2A. The wiring layer 2B is bonded to the wiring layer 2B that constitutes the circuit pattern.

[0028] The semiconductor chips 3 have a first semiconductor chip 3A and a second semiconductor chip 3B arranged adjacent to each other. The semiconductor chip 3 has at least a chip-up electrode 3C (see FIG. 2, not shown in FIG. 3) provided on the upper surface side and a chip-down electrode (not shown) provided on the lower surface side. The semiconductor chip 3 is bonded to the wiring layer 2B of the substrate 2 via a chip-down solder 5B (not shown in FIG. 3, see FIG. 6 described later). In this embodiment, a diode is used as the first semiconductor chip 3A, and an IGBT (Insulated Gate Bipolar Transistor) is used as the second semiconductor chip 3B, but the present invention is not limited to this. In addition, in this embodiment, as shown in FIG. 1, an example is shown in which two first semiconductor chips 3A, two second semiconductor chips 3B, and two lead frames 4 are provided on one substrate 2, but the present invention is not limited to this. In addition, in this embodiment, an example is shown in which one lead frame 4 is bonded across two semiconductor chips 3, but the present invention is not limited to this, and the lead frame 4 may be bonded across three or more semiconductor chips 3.

[0029] The lead frame 4 has a chip connection portion 4A, an inter-chip connection portion 4B, a foot portion 4C, a notch 4D, and a through hole 4E. The chip connection portion 4A has a shape recessed from the surroundings (see FIG. 9 described later), and is joined to an on-chip electrode 3C on the upper surface of the semiconductor chip 3 via on-chip solder 5A (not shown in FIG. 3, see FIG. 5 described later). The inter-chip connection portion 4B connects two chip connection portions 4A, and at least a part of the chip connection portion 4B overlaps with a gap 20 between the first semiconductor chip 3A and the second semiconductor chip 3B, as shown in FIG. 2 and FIG. 3. The inter-chip connection portion 4B is provided with a notch 4D. In addition, the inter-chip connection portion 4B is preferably provided with a through hole 4E. The notch 4D and the through hole 4E will be described in detail later. The foot portion 4C is a portion that connects the chip connection portion 4A and the substrate 2. The foot 4C is joined to the wiring layer 2B on the upper surface of the substrate 2 via under-foot solder 5C (see FIG. 5 described later). The lead frame 4 serves to provide electrical connection and to dissipate heat by thermal conduction.

[0030] The above-substrate jig 10 (see FIG. 1) and the below-substrate jig 11 (see FIG. 3) are jigs used in the manufacturing stage of the semiconductor device 1, and are used to position and mount each component on the substrate 2. The above-substrate jig 10 is disposed on the upper surface side of the substrate 2, and the below-substrate jig 11 is disposed on the lower surface side of the substrate 2.

[0031] The on-substrate jig 10 has an opening 10A and a partition 10B. The opening 10A and the partition 10B have shapes for positioning each component, and each component can be positioned and mounted by inserting it into the opening 10A. The partition 10B is provided in the gap 20 between the first semiconductor chip 3A and the second semiconductor chip 3B, and is used for chip positioning.

[0032] Specifically, the first semiconductor chip 3A and the second semiconductor chip 3B are positioned using an on-substrate jig 10 having a partition 10B for chip positioning in the gap 20 between the first semiconductor chip 3A and the second semiconductor chip 3B. The partition 10B allows the first semiconductor chip 3A and the second semiconductor chip 3B, which are adjacent to each other, to be accurately positioned while maintaining the gap 20.

[0033] Furthermore, as the lead frame 4, as shown in Figures 1 and 2, a lead frame 4 is used in which the corners of the first semiconductor chip 3A and the corners of the second semiconductor chip 3B are visible, and as shown in Figure 3, a lead frame 4 having a notch 4D shaped so that a partition 10B passes through is used, and before the first semiconductor chip 3A and the second semiconductor chip 3B are bonded to the substrate 2, the lead frame 4 is positioned using an on-substrate jig 10.

[0034] In this embodiment, in order to reduce the number of mounting and solder reflow processes, the lead frame 4 is positioned before the semiconductor chip 3 is bonded to the substrate 2, so it is necessary to position the lead frame 4 while checking whether the position of the semiconductor chip 3 is not misaligned. Therefore, if there is no notch 4D, the corners of the semiconductor chip 3 are not visible or are difficult to see, making it difficult to check whether the position of the semiconductor chip 3 is misaligned. In this embodiment, since there is the notch 4D, it is possible to check the positions of the corners of the semiconductor chip 3, and it is possible to position the lead frame 4 while checking whether the position of the semiconductor chip 3 is not misaligned.

[0035] Furthermore, the cutout 4D is shaped so that the partition 10B for maintaining the gap 20 penetrates therethrough, so that the two adjacent semiconductor chips 3 can be accurately positioned while avoiding interference with the partition 10B.

[0036] It is also possible to narrow the overall width of the lead frame 4 without providing the notch 4D, but in that case, the width of the portion including the chip connection portion 4A would be narrowed, which would cause a problem of reduced electrical connection and heat dissipation effects by thermal conduction. Therefore, the configuration in this embodiment in which the portion including the chip connection portion 4A is made wide enough to cover almost the entire semiconductor chip 3 and the notch 4D is provided in the chip-to-chip connection portion 4B provides better electrical connection and heat dissipation effects by thermal conduction.

[0037] Although the explanation is omitted, the solder 5 is also mounted separately at an appropriate timing. Then, after mounting each member, the under-chip solder 5B provided between the first semiconductor chip 3A and the substrate 2 and between the second semiconductor chip 3B and the substrate 2, and the over-chip solder 5A provided between the first semiconductor chip 3A and the lead frame 4 and between the second semiconductor chip 3B and the lead frame 4 are reflowed to bond the substrate 2, the first semiconductor chip 3A, the second semiconductor chip 3B, and the lead frame 4. At the same time, the under-foot solder 5C provided between the substrate 2 and the lead frame 4 is also reflowed to bond the substrate 2 and the lead frame 4.

[0038] According to this embodiment, when manufacturing a semiconductor device 1 having a plurality of semiconductor chips 3 bonded onto a substrate 2 and a lead frame 4 bonded across the plurality of semiconductor chips 3, the number of mounting and solder reflow processes can be reduced.

[0039] Next, further details of this embodiment and modifications will be described.

[0040] As shown in Fig. 1, it is desirable that the lead frame 4 has a shape that allows at least two diagonal corners of the first semiconductor chip 3A and two diagonal corners of the second semiconductor chip 3B to be visible. By allowing the two diagonal corners of the semiconductor chip 3 to be visible, it is possible to more accurately check for misalignment of the semiconductor chip 3. Fig. 1 shows an example in which three corners excluding the corners corresponding to the feet 4C are visible, but this is not limiting.

[0041] In this embodiment, it is assumed that when positioning the lead frame 4, the on-chip solder 5A is pre-soldered to the lead frame 4. Hereinafter, a description will be given with reference to Figs.

[0042] FIG. 5 is a perspective view illustrating a step of pre-soldering to a lead frame in the manufacturing method of a semiconductor device according to the embodiment.

[0043] As shown in Fig. 5, an upper jig 12 for pre-soldering a lead frame and a lower jig 13 for pre-soldering a lead frame are used to position and mount solder 5A on the chip and solder 5C under the foot on the lead frame 4 as solder 5. Then, the solder 5 is reflowed to pre-solder the solder 5A on the chip and solder 5C under the foot on the lead frame 4. Note that this differs from the conventional method shown in Fig. 10 in that pre-soldering of solder 5C under the foot is also performed.

[0044] FIG. 6 is a perspective view illustrating a step of positioning a semiconductor chip and a lead frame using an on-substrate jig in the manufacturing method of a semiconductor device according to the embodiment.

[0045] As shown in Fig. 6, using the above-substrate jig 10 and the below-substrate jig 11 of this embodiment, the under-chip solder 5B is positioned and mounted on the substrate 2 as the solder 5. Then, the semiconductor chip 3 is positioned and mounted on the under-chip solder 5B. Then, the pre-soldered lead frame 4 shown in Fig. 5 is positioned and mounted on the substrate 2 and the semiconductor chip 3. Thereafter, the solder 5 is reflowed to bond the substrate 2, the semiconductor chip 3, and the lead frame 4 together. According to this embodiment, the conventional steps of Figs. 11 and 12 can be combined into one step of Fig. 6, and the number of mounting and solder reflow steps can be reduced.

[0046] In addition, when a lead frame 4 with pre-soldering is used, the number of mounting and solder reflow steps is two as shown in FIG. 5 and FIG. 6, but it is not limited to this, and the lead frame 4 may not have pre-soldered solder 5A on the chip when it is positioned. That is, FIG. 5 and FIG. 6 may be combined and the number of mounting and solder reflow steps may be one. However, in that case, the upper jig 12 for pre-soldering lead frame having an opening for positioning the foot under solder 5C shown in FIG. 5 cannot be used, so the difficulty of positioning the foot under solder 5C increases. Therefore, depending on whether it is important to reduce the number of mounting and solder reflow steps or to reliably position the foot under solder 5C, it is only necessary to select which manufacturing method to adopt.

[0047] FIG. 7 is a top view for explaining the positional relationship between the outer shape of the lead frame and the semiconductor chip in the embodiment, and an enlarged view of portions C1 to C4.

[0048] 7 shows a state in which the joining is completed and the upper-substrate jig 10 and the lower-substrate jig 11 are removed. Therefore, the insulating layer 2A and the wiring layer 2B of the substrate 2 are also shown.

[0049] As shown in FIG. 7, the lead frame 4 of this embodiment preferably has an outer shape in which at least the peripheral portion of the notch 4D outside the notch 4D is set back by 0.1 mm or more from the first semiconductor chip 3A or the second semiconductor chip 3B, like the setback portion 4F. This shape takes into consideration the processing accuracy of the lead frame 4 and the expansion at the solder melting temperature. In addition, the material of the on-board jig 10 is, for example, carbon, but the shape of this embodiment can prevent interference with the on-board jig 10 and suppress the generation of carbon debris around the semiconductor chip 3. By using the lead frame 4 of this embodiment, the semiconductor chip 3 and the lead frame 4 can be positioned and mounted using the same on-board jig 10.

[0050] FIG. 8 is a top view illustrating the shape of a lead frame according to an embodiment, and cross-sectional views taken along lines EE and FF.

[0051] As shown in FIG. 8, the lead frame 4 of this embodiment has a foot 4C joined to the upper surface of the substrate 2, and it is desirable that the cross-sectional area of ​​the interchip connection portion 4B (cross-sectional area at EE) ≧ the cross-sectional area of ​​the foot 4C (cross-sectional area at FF). The lead frame 4 has a role of dissipating heat by thermal conduction. The rate of heat dissipation by thermal conduction is determined by the cross-sectional area, and the larger the cross-sectional area, the higher the effect of heat dissipation by thermal conduction. For example, assuming that the heat generated by the second semiconductor chip 3B is greater than the heat generated by the first semiconductor chip 3A, by making the cross-sectional area of ​​the interchip connection portion 4B ≧ the cross-sectional area of ​​the foot 4C, the heat generated by the second semiconductor chip 3B can be easily dissipated by thermal conduction not only via the foot 4C at the lower right of FIG. 8, but also via the interchip connection portion 4B and the foot 4C at the upper left of FIG. 8.

[0052] FIG. 9 is a cross-sectional view taken along line DD in FIG.

[0053] As shown in Fig. 4 and Fig. 9, the lead frame 4 of this embodiment preferably has a through hole 4E in the inter-chip connection portion 4B at a position different from the notch 4D. The manufacturing method of this embodiment preferably includes a step of sealing the substrate 2, the first semiconductor chip 3A, the second semiconductor chip 3B, and the lead frame 4 with a sealing resin (not shown) after bonding the substrate 2, the first semiconductor chip 3A, the second semiconductor chip 3B, and the lead frame 4. At this time, the sealing resin can infiltrate through the through hole 4E as shown by the sealing resin infiltration path 21. Therefore, the through hole 4E can improve the permeability of the sealing resin to the area around the semiconductor chip 3 below the lead frame 4 and improve the adhesion.

[0054] Although the embodiment of the present invention has been described above, the present invention is not limited to the configurations described in the embodiment, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in the embodiment may be combined and applied. [Explanation of symbols]

[0055] 1 Semiconductor device 2. Board 2A Insulation Layer 2B wiring layer 2C Backside metal layer 3. Semiconductor chips 3A First Semiconductor Chip 3B Second semiconductor chip 3C Electrode on chip 4 Lead Frame 4A Chip Connection 4B Inter-chip connection 4C Foot 4D notch 4E Through hole 4F rear section 5 Solder 5A Chip top solder 5B Chip bottom solder 5C Foot bottom solder 10. Circuit board jig 10A aperture 10B Partition 11 Substrate jig 12 Lead frame spare soldering jig 13 Lead frame spare soldering jig 14 First board jig 15 First board lower jig 16 Second board jig 17 Second board lower jig 20 gap 21 Sealing resin intrusion route

Claims

1. 1. A method for manufacturing a semiconductor device comprising: a substrate; a first semiconductor chip bonded to an upper surface of the substrate; a second semiconductor chip disposed adjacent to the first semiconductor chip and bonded to an upper surface of the substrate; and a lead frame having an inter-chip connection portion bonded to an upper surface of the first semiconductor chip and an upper surface of the second semiconductor chip and overlapping a gap between the first semiconductor chip and the second semiconductor chip, positioning the first semiconductor chip and the second semiconductor chip using a substrate jig having a partition for chip positioning in the gap between the first semiconductor chip and the second semiconductor chip; a lead frame having a notch through which the partition passes and through which a corner of the first semiconductor chip and a corner of the second semiconductor chip are visible is used as the lead frame, and the lead frame is positioned using an on-substrate jig before the first semiconductor chip and the second semiconductor chip are bonded to the substrate; A method for manufacturing a semiconductor device, comprising the steps of: reflowing under-chip solder provided between the first semiconductor chip and the substrate and between the second semiconductor chip and the substrate, and over-chip solder provided between the first semiconductor chip and the lead frame, and between the second semiconductor chip and the lead frame, to join the substrate, the first semiconductor chip, the second semiconductor chip, and the lead frame.

2. In claim 1, A method for manufacturing a semiconductor device, wherein the lead frame is shaped so that at least two diagonal corners of the first semiconductor chip and two diagonal corners of the second semiconductor chip are visible.

3. In claim 1, A method for manufacturing a semiconductor device, wherein the lead frame has an outer shape in which at least the peripheral portion of the notch outside the notch is recessed by 0.1 mm or more from the first semiconductor chip or the second semiconductor chip.

4. In claim 1, The method for manufacturing a semiconductor device, wherein the lead frame has a foot portion to be joined to an upper surface of the substrate, and a cross-sectional area of ​​the inter-chip connection portion is greater than or equal to a cross-sectional area of ​​the foot portion.

5. In claim 1, 2 is a diagram showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention; FIG. 3 is a diagram showing a semiconductor device manufacturing method according to the first embodiment of the present invention;

6. In claim 5, A method for manufacturing a semiconductor device, comprising: after bonding the substrate, the first semiconductor chip, the second semiconductor chip, and the lead frame, sealing the substrate, the first semiconductor chip, the second semiconductor chip, and the lead frame with sealing resin.

7. In claim 1, 4. A method of manufacturing a semiconductor device, comprising the steps of: positioning said lead frame; and forming said lead frame on said chip;

8. In claim 1, 4. A method of manufacturing a semiconductor device, comprising the steps of: positioning said lead frame; and forming said lead frame on said chip;

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