Phase-locked loop circuit and phased array antenna

Abstract

To reliably control the reset timing and reliably determine the initial phase for an output divider and output divider reset unit even when the variation in the delay amount of a trigger signal is large depending on the variations in manufacturing, power supply and temperature of a phase-locked loop because the path length from a trigger signal synchronization unit is long.SOLUTION: Regardless of whether the edge timing of a trigger signal fSYNC varies earlier or later than the edge timing of a reference signal fOSC, the reset timing of an output divider 7 is controlled to be the same timing, and the initial phase of the output divider 7 is determined to be the same phase.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present disclosure relates to a technique for controlling output signals of a plurality of phase-locked loop circuits to be in phase with each other. [Background technology]

[0002] In a phased array antenna system or the like, a technique for controlling output signals of a plurality of phase-locked loop circuits to have the same phase is disclosed in Patent Document 1 and Non-Patent Documents 1 and 2. Non-Patent Documents 1 and 2 will be mainly described as the conventional techniques. The configuration of a phased array antenna system of the conventional technique is shown in Fig. 1. The phased array antenna system S includes phase-locked loop circuits P1-PN and phased array antennas A1-AN.

[0003] Each of the phase-locked loop circuits P1 to PN includes an input divider 1, a phase comparator 2, an oscillator 3, a pre-divider 4, a feedback divider 5, a ΔΣ modulator 6, an output divider 7, a trigger signal synchronization unit 8, and an output divider reset unit 9. In the phase-locked loop circuits P1 to PN, the input divider 1 receives a reference signal f ОSC are input in phase by equal length wiring, and the trigger signal synchronizing unit 8 receives the trigger signal f SYNC are input in phase with equal length wiring, and the output divider 7 outputs the output signal f ОUT In the phased array antennas A1 to AN, the output signal f ОUT are input in phase.

[0004] The input divider 1 divides the reference signal f ОSC The phase comparator 2, the oscillator 3, the pre-divider 4 and the feedback divider 5 constitute a phase locked loop. The oscillator 3 outputs an oscillation signal f VCO and the prescaler 4 outputs the output signal f DIV The feedback divider 5, together with the ΔΣ modulator 6 (located outside the phase-locked loop), realizes fractional division. The output divider 7 outputs the output signal f DIVIt covers high and low frequency ranges and reduces spurious noise in fractional division.

[0005] Here, since the pre-divider 4 and the feedback divider 5 are arranged inside the phase-locked loop, the output phase is determined after the phase lock of the phase-locked loop is established. However, since the input divider 1, the ΔΣ modulator 6, and the output divider 7 are arranged outside the phase-locked loop, the output phase is not determined but is merely determined probabilistically due to element variations such as transistors and noise in the elements even after the phase lock of the phase-locked loop is established.

[0006] The trigger signal synchronizing unit 8 generates a trigger signal f for determining the initial phase of the input frequency divider 1, the ΔΣ modulator 6, and the output frequency divider 7 after the phase synchronization of the phase-locked loop is established. SYNC The reference signal f ОSC Then, the output divider reset unit 9 controls the reset timing of the output divider 7 and determines the initial phase of the output divider 7. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2022-061783 A [Non-patent literature]

[0008] [Non-Patent Document 1] “HMC835 Datasheet”, [оnline], Analog Devices, [Retrieved August 2, 2023], Internet<URL:https: / / www.analog.com / jp / products / hmc835.html> [Non-Patent Document 2] “Reference design for phase synchronization of multiple PLL synthesizers”, [оnline], TI Designs, [Retrieved August 2, 2023], Internet <URL:https: / / www.tij.co.jp / jp / lit / ug / jaju290 / jaju290.pdf?ts=1604888182781&ref_url=https%253A%252F%252Fwww.google.co.jp%252F> Summary of the Invention [Problem to be solved by the invention]

[0009] Here, for the input divider 1 and the ΔΣ modulator 6, the path length from the trigger signal synchronization unit 8 is short, so that the trigger signal f SYNC The variation in the delay amount is small regardless of the manufacturing, power supply, and temperature variations of the phase-locked loops P1 to PN. SYNC The edge timing of the reference signal f ОSC In the low frequency region, whether the edge timing varies earlier or later has a smaller effect than the edge timing of the first embodiment. Therefore, regardless of whether the edge timing varies earlier or later, the reset timing can be controlled to be the same, and the initial phase can be determined to be the same.

[0010] On the other hand, for the output divider 7 and the output divider reset unit 9, the path length from the trigger signal synchronization unit 8 is long, so that the trigger signal f SYNC The variation in the delay amount of the phase-locked loops P1 to PN is large depending on the manufacturing, power supply, and temperature variations. SYNC The edge timing of the reference signal f ОSC In the high frequency range, whether the edge timing varies earlier or later than the edge timing of the input signal has a large effect. Therefore, depending on whether the edge timing varies earlier or later than the edge timing of the input signal, it may not be possible to control the reset timing to be simultaneous, and it may not be possible to determine the initial phase to be the same (see the explanations of Figures 2 to 5).

[0011] A method for determining the initial output phase of a phase-locked loop circuit according to the prior art is shown in FIG. 2. In FIG. 2, the division factor f OUT / f ОSC is N (an integer), and there is one type of fractional division output code.

[0012] In columns 1 to 5 of Figure 2, the only output code of the fractional division is the reference signal f ОSC At the falling edge of the oscillation signal f VCO The phase of the output signal f DIV The phase of the output signal f OUT The phase of is either 0 or π and is not determined.

[0013] First, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC The following describes the case where the timing of the falling edge of the trigger signal f varies "early" by the delay amount variation Δt. SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the trigger signal f SYNC Compared to the rising edge timing of the output signal f, the delay variation is Δt or more (= DIV The reset timing of the output divider 7 is delayed by about π (rad) of the trigger signal f SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the output signal f OUT The phase determination timing is π / 2 (rad) after that.

[0014] Next, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC This section explains the case where the timing of the falling edge of the trigger signal f varies "later" by about the delay amount variation Δt. SYNC The output signal f immediately after the rising edge of DIVThe falling edge timing of the trigger signal f SYNC Compared to the rising edge timing of the output signal f, the delay variation is Δt or more (= DIV The reset timing of the output divider 7 is delayed by the time delay of the trigger signal f SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the output signal f OUT The phase determination timing is π / 2 (rad) after that.

[0015] Therefore, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC Regardless of whether the variation is "early" or "late" compared to the falling edge timing of the output divider 7, the reset timing of the output divider 7 can be made to be the same timing, and the initial phase of the output divider 7 can be determined to be the same phase.

[0016] A method for determining the initial output phase of a phase-locked loop circuit according to the prior art is also shown in FIG. OUT / f ОSC is N+1 / 2, and there are two types of fractional division output codes.

[0017] In columns 2 and 4 of Figure 3, the reference signal f is used as one output code of the fractional division. ОSC At the falling edge of the oscillation signal f VCO The phase of the output signal f DIV The phase of the output signal f OUT The phase of is either π or 0 and is not determined.

[0018] First, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC The following describes the case where the timing of the falling edge of the trigger signal f f varies "early" by the delay amount variation Δt. SYNC The output signal f immediately after the rising edge ofDIV The falling edge timing of the trigger signal f SYNC Compared to the rising edge timing of the output signal f, the delay variation is Δt or more (= DIV The reset timing of the output divider 7 is delayed by about π (rad) of the trigger signal f SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the output signal f OUT The phase determination timing is π / 2 (rad) after that.

[0019] Next, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC This section explains the case where the timing of the falling edge of the trigger signal f varies "later" by about the delay amount variation Δt. SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the trigger signal f SYNC Compared to the rising edge timing of the output signal f, the delay variation is Δt or more (= DIV The reset timing of the output divider 7 is delayed by the time delay of the trigger signal f SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the output signal f OUT The phase determination timing is π / 2 (rad) after that.

[0020] Therefore, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC 3, regardless of whether the variation is "early" or "late" compared with the falling edge timing of the output divider 7, the reset timing of the output divider 7 can be made to be the same timing, and the initial phase of the output divider 7 can be determined to be the same phase. In the first, third, and fifth columns of FIG. 3, substantially the same effect as in the second and fourth columns of FIG. 3 can be obtained.

[0021] A method for determining the initial output phase of a phase-locked loop circuit according to the prior art is also shown in FIG. OUT / f ОSC is N+1 / 4, and there are four output codes for fractional division.

[0022] In the second column of Figure 4, the reference signal f is used as one output code of the fractional division. ОSC At the falling edge of the oscillation signal f VCO The phase of the output signal f DIV has a phase of π (which may include jitter), and the output signal f OUT The phase of is either π / 2 or 3π / 2 and is not certain.

[0023] First, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC The following describes the case where the timing of the falling edge of the trigger signal f f varies "early" by the delay amount variation Δt. SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the trigger signal f SYNC The reset timing of the output divider 7 is delayed by less than the delay amount variation Δt compared to the rising edge timing of the trigger signal f SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the output signal f OUT The phase determination timing is π / 2 (rad) after that.

[0024] Next, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC This section explains the case where the timing of the falling edge of the trigger signal f varies "later" by about the delay amount variation Δt. SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the trigger signal f SYNC Compared to the rising edge timing of the output signal f, the delay variation is Δt or more (= DIVThe reset timing of the output divider 7 is delayed by about 2π (rad) of the trigger signal f SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the output signal f OUT The phase determination timing is π / 2 (rad) after that.

[0025] Therefore, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC In the fourth column of Fig. 4, almost the same problem occurs as in the second column of Fig. 4. In the first, third and fifth columns of Fig. 4, almost the same effect as in the columns of Fig. 2 and Fig. 3 can be obtained.

[0026] A method for determining the initial output phase of a phase-locked loop circuit according to the prior art is also shown in FIG. OUT / f ОSC is N+1 / 8, and there are eight possible fractional division output codes.

[0027] In the third column of Figure 5, the reference signal f is used as one output code of the fractional division. ОSC At the falling edge of the oscillation signal f VCO The phase of the output signal f DIV has a phase of π (which may include jitter), and the output signal f OUT The phase of is either π / 2 or 3π / 2 and is not certain.

[0028] First, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC The following describes the case where the timing of the falling edge of the trigger signal f f varies "early" by the delay amount variation Δt. SYNC The output signal f immediately after the rising edge ofDIV The falling edge timing of the trigger signal f SYNC The reset timing of the output divider 7 is delayed by less than the delay amount variation Δt compared to the rising edge timing of the trigger signal f SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the output signal f OUT The phase determination timing is π / 2 (rad) after that.

[0029] Next, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC This section explains the case where the timing of the falling edge of the trigger signal f varies "later" by about the delay amount variation Δt. SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the trigger signal f SYNC Compared to the rising edge timing of the output signal f, the delay variation is Δt or more (= DIV The reset timing of the output divider 7 is delayed by about 2π (rad) of the trigger signal f SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the output signal f OUT The phase determination timing is π / 2 (rad) after that.

[0030] Therefore, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC 5, depending on whether the variation is "early" or "late" compared with the falling edge timing of the output divider 7, the reset timing of the output divider 7 cannot be made to be simultaneous, and the initial phase of the output divider 7 cannot be determined to be the same phase. In columns 1, 2, 4, and 5 of Figure 5, substantially the same effects can be obtained as in each column of Figures 2 and 3.

[0031] Furthermore, the division factor f OUT / fОSC When the decimal point division is smaller than 1 / 8, the initial phase of the output frequency divider 7 cannot be determined, resulting in a metastable state. Therefore, in order to control the output phases of the phase-locked loop circuits P1 to PN to be the same phase, techniques for calibrating the output phases of the phase-locked loop circuits P1 to PN are disclosed in Non-Patent Documents 1 and 2, etc.

[0032] The configuration of a conventional phase calibration circuit is shown in FIG. 6. The phase calibration circuit C includes multipliers 11 and 12, a 90° hybrid 13, and a phase calibration unit 14. Any of the phase-locked loop circuits P1 to PN is connected in order to the phase calibration circuit C. Any of the phase-locked loop circuits P1 to PN and a phase reference generating circuit R receive a reference signal f ОSC Any of the phase-locked loop circuits P1 to PN receives a trigger signal f SYNC Enter.

[0033] The 90° hybrid 13 receives the output signal of the phase reference generating circuit R and outputs the I signal and the Q signal. The multiplier 11 receives the output signal of one of the phase locked loop circuits P1 to PN and the I signal, and outputs the multiplication result V I The multiplier 12 receives the output signal of one of the phase-locked loop circuits P1 to PN and the Q signal, and outputs the multiplication result V Q The phase calibration unit 14 outputs the multiplication result V I , V Q is input, and the phase calibration amount Δθ of one of the phase-locked loop circuits P1 to PN is expressed as Δθ=tan -1 (V Q / V I ) to output.

[0034] The configuration of a phase calibration circuit of the prior art is also shown in FIG. 7. The phase calibration circuit C includes an adder 15 and a phase calibration unit 16. Any of the phase-locked loop circuits P1 to PN is connected in sequence to the phase calibration circuit C. Any of the phase-locked loop circuits P1 to PN and a phase reference generating circuit R receive a reference signal f ОSC Any of the phase-locked loop circuits P1 to PN receives a trigger signal f SYNCis input and the output phase is swept.

[0035] The adder 15 receives the output signal of one of the phase-locked loop circuits P1 to PN and the output signal of the phase reference generating circuit R, and outputs the sum P SUM The phase calibration unit 16 outputs the addition result P SUM is input, and the sum result P is used as the phase calibration amount Δθ of one of the phase-locked loop circuits P1 to PN. SUM The phase correction amount Δθ that maximizes is output.

[0036] However, the cost and the circuit size increase because additional circuits such as the phase reference generating circuit R and the phase calibration circuit C are required. Moreover, the phase locked loop circuits P1 to PN are connected to the phase calibration circuit C in order, which increases the cost and the testing time, making this unrealistic.

[0037] Therefore, in order to solve the above problem, the present disclosure aims to reliably control the reset timing and reliably determine the initial phase for an output divider and an output divider reset unit, even when the path length from the trigger signal synchronization unit is long and the variation in the delay amount of the trigger signal is large depending on the manufacturing, power supply, and temperature variations of the phase-locked loop. [Means for solving the problem]

[0038] In order to solve the above problem, regardless of whether the edge timing of the trigger signal varies earlier or later than the edge timing of the reference signal, the reset timing of the output divider is controlled to be simultaneous, and the initial phase of the output divider is determined to be the same phase.

[0039] Specifically, the present disclosure relates to a phase-locked loop circuit comprising: a phase-locked loop having a phase comparator, an oscillator, and a feedback divider; an output divider for an output signal to the outside of the phase-locked loop; a trigger signal synchronization unit that synchronizes a trigger signal for determining the initial phase of the output divider with a reference signal of the phase-locked loop after phase synchronization of the phase-locked loop is established; and an output divider reset unit that controls the reset timing of the output divider to be simultaneous, regardless of whether the edge timing of the trigger signal varies earlier or later than the edge timing of the reference signal, and determines the initial phase of the output divider to be the same phase.

[0040] According to this configuration, since the path length from the trigger signal synchronization unit to the output divider and output divider reset unit is long, even when the variation in the delay amount of the trigger signal is large due to manufacturing, power supply, and temperature variations of the phase-locked loop, the reset timing can be reliably controlled and the initial phase can be reliably determined.

[0041] The present disclosure also relates to a phase-locked loop circuit characterized in that, when the edge timing (falling or rising timing) of the output signal immediately after the edge timing of the trigger signal is delayed compared to the edge timing of the trigger signal by less than a predetermined period of a threshold, the output divider reset unit controls the reset timing of the output divider not at the edge timing of the output signal immediately after the edge timing of the trigger signal, but at the next edge timing of the output signal.

[0042] According to this configuration, when the edge timing of the trigger signal varies earlier than the edge timing of the reference signal, the reset timing of the output divider can be reliably controlled and the initial phase of the output divider can be reliably determined.

[0043] The present disclosure also provides a phase-locked loop circuit characterized in that, when the edge timing (falling or rising timing) of the output signal immediately after the edge timing of the trigger signal is delayed by more than the threshold value for the specified period compared to the edge timing of the trigger signal, the output divider reset unit controls the reset timing of the output divider at the edge timing of the output signal immediately after the edge timing of the trigger signal, without waiting for the next edge timing of the output signal.

[0044] According to this configuration, when the edge timing of the trigger signal varies to be slower than the edge timing of the reference signal, the reset timing of the output divider can be reliably controlled and the initial phase of the output divider can be reliably determined.

[0045] The present disclosure also relates to a phase-locked loop circuit further comprising: a ring oscillator that acquires the output signal, forms a ring circuit, and includes a plurality of delay elements, controls the delay amounts of the plurality of delay elements, and oscillates the output signal; a variation measuring unit that calculates a correlation between the delay signals of the plurality of delay elements and the trigger signal over one round period of an output code of a fractional division of the feedback divider, and measures a variation between the edge timing of the trigger signal and the edge timing of the reference signal; and a predetermined period threshold setting unit that sets the predetermined period threshold so that it is wider than the variation between the edge timing of the trigger signal and the edge timing of the reference signal.

[0046] With this configuration, it is possible to determine whether the edge timing of the trigger signal varies earlier or later than the edge timing of the reference signal, based on a statistical index that also takes momentary disturbances into account.

[0047] The present disclosure also provides a phased array antenna including a plurality of the phase-locked loop circuits described above, wherein the reference signal and the trigger signal are input in the same phase in each of the phase-locked loop circuits, and the reference signal and the trigger signal are output in the same phase from the output divider.

[0048] According to this configuration, in a phased array antenna system, the output signals of a plurality of phase-locked loop circuits can be controlled to be in phase. Although an internal circuit such as an output divider reset unit is required, the output divider reset unit is not involved in the main signal path, phase noise is not an issue, and the cost and circuit size are reduced. Furthermore, since the phase-locked loop circuits are automatically controlled by the output divider reset unit, the cost and control time are reduced, making this a practical solution.

[0049] The above disclosed inventions can be combined to the greatest extent possible. Effect of the Invention

[0050] In this way, the present disclosure is capable of reliably controlling the reset timing and reliably determining the initial phase for the output divider and output divider reset unit, even when the path length from the trigger signal synchronization unit is long and the variation in the delay amount of the trigger signal is large due to manufacturing, power supply, and temperature variations in the phase-locked loop. [Brief description of the drawings]

[0051] [Figure 1] FIG. 1 is a diagram showing the configuration of a phased array antenna system according to a conventional technology. [Diagram 2] FIG. 1 is a diagram showing a method for determining an initial output phase of a phase-locked loop circuit according to the prior art; [Diagram 3] FIG. 1 is a diagram showing a method for determining an initial output phase of a phase-locked loop circuit according to the prior art; [Figure 4] FIG. 1 is a diagram showing a method for determining an initial output phase of a phase-locked loop circuit according to the prior art; [Diagram 5] FIG. 1 is a diagram showing a method for determining an initial output phase of a phase-locked loop circuit according to the prior art; [Figure 6] FIG. 1 is a diagram showing a configuration of a phase calibration circuit according to a conventional technique. [Figure 7] FIG. 1 is a diagram showing a configuration of a phase calibration circuit according to a conventional technique. [Figure 8] FIG. 1 is a diagram showing a configuration of a phased array antenna system according to the present disclosure. [Figure 9] FIG. 2 is a diagram showing a procedure of a phase-locked loop process according to the present disclosure. [Figure 10] FIG. 11 is a diagram showing a procedure for output divider reset processing according to the present disclosure. [Figure 11] FIG. 2 is a diagram showing a method for determining an initial output phase of the phase-locked loop circuit of the present disclosure. [Figure 12] FIG. 2 is a diagram showing a method for determining an initial output phase of the phase-locked loop circuit of the present disclosure. [Figure 13] 1 is a diagram showing a method for determining an initial output phase of a phase-locked loop circuit according to the present disclosure; [Figure 14] 1 is a diagram showing a method for determining an initial output phase of a phase-locked loop circuit according to the present disclosure; [Figure 15] FIG. 13 is a diagram illustrating a configuration of a predetermined period threshold setting unit according to the present disclosure. [Figure 16] FIG. 11 is a diagram showing a procedure of a predetermined period threshold setting process according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0052] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present disclosure will be described with reference to the accompanying drawings. The embodiments described below are examples of the present disclosure, and the present disclosure is not limited to the following embodiments.

[0053] (Configuration of the Phased Array Antenna System of the Present Disclosure) The configuration of the phased array antenna system of the present disclosure is shown in Fig. 8. The phased array antenna system S includes phase locked loop circuits P1-PN and phased array antennas A1-AN. ​​The phase locked loop circuits P1-PN include an input divider 1, a phase comparator 2, an oscillator 3, a pre-divider 4, a feedback divider 5, a ΔΣ modulator 6, an output divider 7, a trigger signal synchronizer 8, an output divider reset unit 9, and a predetermined period threshold setting unit 10.

[0054] The phase-locked loop circuits P1 to PN can be realized using an FPGA or the like that executes the processes shown in Figs. 9, 10, and 16. In this disclosure, the output divider 7 is a 1 / 2 divider (covering the high frequency range), but as a modified example, it may be a 1 / 4 divider, a 1 / 8 divider, etc. (covering the low frequency range). In this disclosure, the input divider 1 is placed in the phase-locked loop circuits P1 to PN, but as a modified example, it may not be placed in the phase-locked loop circuits P1 to PN. Below, differences of the present disclosure compared to the conventional technology will be mainly described.

[0055] As described later, in the phased array antenna system S, the output signals of the multiple phase-locked loop circuits P1 to PN can be controlled to be in phase. Although an internal circuit such as an output divider reset unit 9 is required, it is not involved in the main signal path, phase noise is not an issue, and the cost and circuit size are reduced. Furthermore, each phase-locked loop circuit is automatically controlled by the output divider reset unit 9, so the cost and control time are reduced, making it practical.

[0056] (Phase-locked loop processing procedure of the present disclosure) The procedure of the phase-locked loop process of the present disclosure is shown in FIG. 9. The process shown in FIG. 9 is a process having a "higher concept" than the process shown in FIG. 10. After the phase lock of the phase-locked loop is established (step S1), the trigger signal synchronization unit 8 generates a trigger signal f SYNC The reference signal f OSC (step S2).

[0057] The output divider reset unit 9 receives a trigger signal f SYNC The edge timing of the reference signal f OSC In this disclosure, it is determined whether the edge timing of the trigger signal f varies "early" or varies "late" (step S3). SYNC The rising edge timing of the reference signal f ОSC However, as a modified example, the timing of the falling edge of the trigger signal f SYNC The edge timing of the reference signal f ОSC The edge timing may be approximately synchronized with any of the other edge timings.

[0058] The output divider reset unit 9 receives a trigger signal f SYNC The edge timing of the reference signal f ОSC Regardless of whether the variation is "early" or "late" compared to the edge timing of the output divider 7 ("early" and "late" in step S4), the reset timing of the output divider 7 is controlled to be "simultaneous" (step S5), and the initial phase of the output divider 7 is determined to be the "same" phase (step S6).

[0059] In this way, since the path length from the trigger signal synchronization unit 8 to the output divider 7 and the output divider reset unit 9 is long, the trigger signal f SYNC Even when the variation in delay amount is large due to the variation in the manufacturing, power supply, and temperature of the phase-locked loop, the reset timing can be reliably controlled and the initial phase can be reliably determined.

[0060] The procedure of the output divider reset process of the present disclosure is shown in FIG. 10. The process shown in FIG. 10 is a process that is a "lower concept" process compared to the process shown in FIG. 9. The output divider reset unit 9 resets the output divider in response to a trigger signal f SYNC The output signal f immediately after the edge timing DIV The edge timing of the trigger signal f SYNC (Step S11). Here, in this disclosure, the output signal fDIV The falling edge timing of the trigger signal f SYNC However, as a variant, the output signal f DIV The edge timing of the trigger signal f SYNC The edge timing may be compared with any of the above.

[0061] The output divider reset unit 9 receives a trigger signal f SYNC The output signal f immediately after the edge timing DIV The edge timing of the trigger signal f SYNC It is determined whether the timing is delayed by "only less than the predetermined period threshold Δt" or "more than the predetermined period threshold Δt" compared with the edge timing of the trigger signal f (step S12). SYNC Edge timing and reference signal f OSC (See the explanations of FIG. 15 and FIG. 16.) Then, the edge timing of the trigger signal f SYNC It is desirable to ensure a sufficient period as the set time and hold time of the timing control and to specify a period shorter than the predetermined period threshold Δt.

[0062] The output divider reset unit 9 receives the trigger signal f SYNC The output signal f immediately after the edge timing DIV The edge timing (falling or rising timing) of the trigger signal f SYNC When the timing is delayed by "only less than the predetermined period threshold value Δt" compared with the edge timing of the trigger signal f SYNC The output signal f immediately after the edge timing DIV The edge timing of the next output signal f DIV At the edge timing of the clock signal, the reset timing of the output frequency divider 7 is controlled (step S14).

[0063] On the other hand, the output divider reset unit 9 receives a trigger signal f SYNC The output signal f immediately after the edge timingDIV The edge timing (falling or rising timing) of the trigger signal f SYNC If the timing is delayed by "a predetermined period threshold value Δt or more" compared to the edge timing of the trigger signal f SYNC The output signal f immediately after the edge timing DIV At the edge timing of the next output signal f DIV Without waiting for the edge timing, the reset timing of the output frequency divider 7 is controlled (step S15).

[0064] Thus, the trigger signal f SYNC The edge timing of the reference signal f ОSC In comparison with the edge timing of the output frequency divider 7, regardless of whether the variation is "early" or "late," the reset timing of the output frequency divider 7 can be reliably controlled and the initial phase of the output frequency divider 7 can be reliably determined.

[0065] (Procedure for output divider reset process of the present disclosure) A method for determining the initial output phase of the phase-locked loop circuit of the present disclosure is shown in FIG. OUT / f ОSC is N (an integer), and there is one type of fractional division output code.

[0066] In columns 1 to 5 of FIG. 11, the only output code of the fractional division is the reference signal f ОSC At the falling edge of the oscillation signal f VCO The phase of the output signal f DIV The phase of the output signal f OUT The phase of is either 0 or π and is not determined.

[0067] First, the trigger signal f SYNC The rising edge timing of the reference signal f ОSCThe case will be described where the timing varies "early" by about a predetermined period threshold Δt (=about the variation in the delay amount Δt, see the explanations of FIG. 15 and FIG. 16) compared to the falling edge timing of the trigger signal f ("early" in step S4). SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the trigger signal f SYNC Compared to the rising edge timing of the output signal f, the DIV The reset timing of the output divider 7 is delayed by a time period of π (rad) of the trigger signal f + a predetermined period threshold value Δt (step S13: “or more”). SYNC The output signal f immediately after the rising edge of DIV The timing of the falling edge of the next output signal f DIV (Step S15). OUT The phase determination timing is π / 2 (rad) after that.

[0068] Next, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC A case will be described in which the timing varies "later" by about a predetermined period threshold Δt (=about the variation in the delay amount Δt, see the explanations of FIG. 15 and FIG. 16) compared to the falling edge timing of the trigger signal f ("later" in step S4). SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the trigger signal f SYNC Compared to the rising edge timing of the output signal f, the DIV The reset timing of the output frequency divider 7 is delayed by a time of π (rad) of the trigger signal f−about the predetermined period threshold value Δt (step S13: “or more”). SYNC The output signal f immediately after the rising edge of DIV The timing of the falling edge of the next output signal f DIV (Step S15). OUTThe phase determination timing is π / 2 (rad) after that.

[0069] Therefore, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC Regardless of whether the variation is "early" or "late" compared to the falling edge timing of the output divider 7, the reset timing of the output divider 7 can be made to be the same timing, and the initial phase of the output divider 7 can be determined to be the same phase.

[0070] A method for determining the initial output phase of the phase-locked loop circuit of the present disclosure is also shown in FIG. OUT / f ОSC is N+1 / 2, and there are two types of fractional division output codes.

[0071] In the second and fourth columns of FIG. 12, the reference signal f ОSC At the falling edge of the oscillation signal f VCO The phase of the output signal f DIV The phase of the output signal f OUT The phase of is either π or 0 and is not determined.

[0072] First, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC The case will be described where the timing varies "early" by about a predetermined period threshold Δt (=about the variation in the delay amount Δt, see the explanations of FIG. 15 and FIG. 16) compared to the falling edge timing of the trigger signal f ("early" in step S4). SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the trigger signal f SYNC Compared to the rising edge timing of the output signal f, the DIV The reset timing of the output divider 7 is delayed by a time period of π (rad) of the trigger signal f + a predetermined period threshold value Δt (step S13: “or more”). SYNCThe output signal f immediately after the rising edge of DIV The timing of the falling edge of the next output signal f DIV (Step S15). OUT The phase determination timing is π / 2 (rad) after that.

[0073] Next, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC A case will be described in which the timing varies "later" by about a predetermined period threshold Δt (=about the variation in the delay amount Δt, see the explanations of FIG. 15 and FIG. 16) compared to the falling edge timing of the trigger signal f ("later" in step S4). SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the trigger signal f SYNC Compared to the rising edge timing of the output signal f, the DIV The reset timing of the output frequency divider 7 is delayed by a time of π (rad) of the trigger signal f−about the predetermined period threshold value Δt (step S13: “or more”). SYNC The output signal f immediately after the rising edge of DIV The timing of the falling edge of the next output signal f DIV (Step S15). OUT The phase determination timing is π / 2 (rad) after that.

[0074] Therefore, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC 12. In either case of "early" or "late" variation compared to the falling edge timing of the input signal, the reset timing of the output divider 7 can be made to be the same, and the initial phase of the output divider 7 can be determined to be the same phase. In the first, third and fifth columns of FIG. 12, substantially the same effect as in the second and fourth columns of FIG. 12 can be obtained.

[0075] A method for determining the initial output phase of the phase-locked loop circuit of the present disclosure is also shown in FIG. OUT / f ОSC is N+1 / 4, and there are four output codes for fractional division.

[0076] In the second column of FIG. 13, the reference signal f is used as one output code of the fractional division. ОSC At the falling edge of the oscillation signal f VCO The phase of the output signal f DIV has a phase of π (which may include jitter), and the output signal f OUT The phase of is either π / 2 or 3π / 2 and is not certain.

[0077] First, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC The case will be described where the timing varies "early" by about a predetermined period threshold Δt (=about the variation in the delay amount Δt, see the explanations of FIG. 15 and FIG. 16) compared to the falling edge timing of the trigger signal f ("early" in step S4). SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the trigger signal f SYNC The reset timing of the output divider 7 is delayed by less than the predetermined period threshold value Δt compared to the rising edge timing of the trigger signal f SYNC The output signal f immediately after the rising edge of DIV The timing of the falling edge of the next output signal f DIV The output signal f OUT The phase determination timing is π / 2 (rad) after that.

[0078] Next, the trigger signal f SYNC The rising edge timing of the reference signal f ОSCA case will be described in which the timing varies "later" by about a predetermined period threshold Δt (=about the variation in the delay amount Δt, see the explanations of FIG. 15 and FIG. 16) compared to the falling edge timing of the trigger signal f ("later" in step S4). SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the trigger signal f SYNC Compared to the rising edge timing of the output signal f, the DIV The reset timing of the output frequency divider 7 is delayed by a time period of 2π (rad) of the trigger signal f−about the predetermined period threshold value Δt (step S13: “or more”). SYNC The output signal f immediately after the rising edge of DIV The timing of the falling edge of the next output signal f DIV (Step S15). OUT The phase determination timing is π / 2 (rad) after that.

[0079] Therefore, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC 13, regardless of whether the variation is "early" or "late" compared with the falling edge timing of the output divider 7, the reset timing of the output divider 7 can be made to be simultaneous, and the initial phase of the output divider 7 can be determined to be the same phase. In the first, third, fourth, and fifth columns of FIG. 13, substantially the same effect as in the second column of FIG. 13 can be obtained.

[0080] A method for determining the initial output phase of the phase-locked loop circuit of the present disclosure is also shown in FIG. OUT / f ОSC is N+1 / 8, and there are eight possible fractional division output codes.

[0081] In the third column of FIG. 14, the reference signal f is used as one output code of the fractional division. ОSC At the falling edge of the oscillation signal f VCO The phase of the output signal f DIVhas a phase of π (which may include jitter), and the output signal f OUT The phase of is either π / 2 or 3π / 2 and is not certain.

[0082] First, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC The case will be described where the timing varies "early" by about a predetermined period threshold Δt (=about the variation in the delay amount Δt, see the explanations of FIG. 15 and FIG. 16) compared to the falling edge timing of the trigger signal f ("early" in step S4). SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the trigger signal f SYNC The reset timing of the output divider 7 is delayed by less than the predetermined period threshold value Δt compared to the rising edge timing of the trigger signal f SYNC The output signal f immediately after the rising edge of DIV The timing of the falling edge of the next output signal f DIV The output signal f OUT The phase determination timing is π / 2 (rad) after that.

[0083] Next, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC A case will be described in which the timing varies "later" by about a predetermined period threshold Δt (=about the variation in the delay amount Δt, see the explanations of FIG. 15 and FIG. 16) compared to the falling edge timing of the trigger signal f ("later" in step S4). SYNC The output signal f immediately after the rising edge of DIV The falling edge timing of the trigger signal f SYNC Compared to the rising edge timing of the output signal f, the DIV The reset timing of the output frequency divider 7 is delayed by a time period of 2π (rad) of the trigger signal f−about the predetermined period threshold value Δt (step S13: “or more”). SYNC The output signal f immediately after the rising edge ofDIV The timing of the falling edge of the next output signal f DIV (Step S15). OUT The phase determination timing is π / 2 (rad) after that.

[0084] Therefore, the trigger signal f SYNC The rising edge timing of the reference signal f ОSC 14, regardless of whether the variation is "early" or "late" compared with the falling edge timing of the output divider 7, the reset timing of the output divider 7 can be made to be simultaneous, and the initial phase of the output divider 7 can be determined to be the same phase. In the first, second, fourth, and fifth columns of FIG. 14, substantially the same effect as in the third column of FIG. 14 can be obtained.

[0085] And the division factor f OUT / f ОSC Even if the decimal point division is smaller than 1 / 8, the initial phase of the output divider 7 can be determined and a metastable state does not occur. Furthermore, in order to control the output phases of the phase-locked loop circuits P1 to PN to be in phase, additional circuits such as the phase reference generating circuit R and the phase calibration circuit C shown in Figures 6 and 7 are not required, and only internal circuits such as the output divider reset unit 9 and the predetermined period threshold setting unit 10 shown in Figure 8 are required.

[0086] (Configuration of the Predetermined Period Threshold Setting Unit of the Present Disclosure) The configuration of the predetermined period threshold setting unit of the present disclosure is shown in Fig. 15. The procedure of the predetermined period threshold setting process of the present disclosure is shown in Fig. 16. The predetermined period threshold setting unit 10 includes, in its preceding stage, a ring oscillator 17 and a variation measuring unit 18. The ring oscillator 17 is a DLL (Delay-Locked-Loop) circuit or the like, and includes a phase comparator 19 and a delay unit 20. The variation measuring unit 18 includes a correlator 21 and an inter-signal correlation calculation unit 22.

[0087] The ring oscillator 17 outputs a signal f DIVThe delay amount of the multiple delay devices 20 is controlled to obtain an output signal f DIV (Step S21). Here, the phase comparator 19 detects whether the total delay amount in the ring oscillator 17 is equal to the output signal f DIV In other words, the currents of the multiple delay elements 20 are controlled so that the phases of the output signal and the feedback signal to the ring oscillator 17 are in phase with each other, and the delay amounts of the multiple delay elements 20 are controlled.

[0088] The variation measurement unit 18 uses a correlator 21 to measure the delay signals of the multiple delay devices 20 and the trigger signal f over one round cycle (or an integer multiple thereof) of the output code of the fractional frequency division of the feedback frequency divider 5 and the ΔΣ modulator 6. SYNC Here, the cycle of the output code of the fractional frequency division of the feedback frequency divider 5 and the ΔΣ modulator 6 is calculated as follows in FIG. 11, FIG. 12, FIG. 13, and FIG. 14: SYNC These periods are 1, 2, 4 and 8 times the length of one cycle.

[0089] The variation measurement unit 18 uses the signal correlation calculation unit 22 to calculate the trigger signal f SYNC Edge timing and reference signal f ОSC Here, the inter-signal correlation calculation unit 22 measures the deviation between the edge timing of the delay signals of the multiple delay devices 20 and the edge timing of the trigger signal f, taking into consideration which output code is output from the feedback frequency divider 5 and the ΔΣ modulator 6 in one round cycle of the fractional frequency division. SYNC Based on the correlation between the trigger signal f SYNC Edge timing and reference signal f ОSC The deviation between the edge timing of the

[0090] The predetermined period threshold setting unit 10 receives a trigger signal f SYNC Edge timing and reference signal f ОSC The predetermined period threshold value Δt is set so as to be wider than the variation between the edge timing of the trigger signal f (step S24). SYNC Edge timing and reference signal f ОSCCreate a histogram of the offset between the edge timing of the trigger signal f SYNC Edge timing and reference signal f ОSC The dispersion width of the variation between the edge timings is evaluated, and the predetermined period threshold Δt is set to a sufficiently wide width.

[0091] Thus, the trigger signal f SYNC The edge timing of the reference signal f ОSC It is possible to determine whether the variation is "early" or "late" compared to the edge timing of the signal, based on a statistical index that also takes momentary disturbances into consideration. [Industrial Applicability]

[0092] According to the phase-locked loop circuit and phased array antenna of the present disclosure, in a system including a plurality of phase-locked loop circuits, such as a phased array antenna system, the output signals of the plurality of phase-locked loop circuits can be controlled to be in phase. [Explanation of symbols]

[0093] S: Phased array antenna system P1, PN: Phase-locked loop circuit A1, AN: Phased array antenna C: Phase calibration circuit R: Phase reference generator 1: Input divider 2: Phase comparator 3: Oscillator 4: Prescaler 5: Feedback divider 6: Delta-Sigma Modulator 7: Output divider 8: Trigger signal synchronization section 9: Output divider reset section 10: Predetermined period threshold setting unit 11, 12: Multiplier 13:90°Hybrid 14: Phase calibration section 15: Adder 16: Phase calibration section 17: Ring oscillator 18: Variation measurement section 19: Phase comparator 20: Delay device 21: Correlator 22: Signal correlation calculation unit

Claims

1. a phase locked loop including a phase comparator, an oscillator and a feedback divider; an output divider for an output signal external to the phase locked loop; a trigger signal synchronizing unit that synchronizes a trigger signal for determining an initial phase of the output frequency divider with a reference signal of the phase locked loop after the phase lock of the phase locked loop is established; an output divider reset unit that controls the reset timing of the output divider to be the same regardless of whether the edge timing of the trigger signal varies earlier or later than the edge timing of the reference signal, and determines the initial phase of the output divider to be the same phase; A phase-locked loop circuit comprising:

2. When the edge timing (falling or rising timing) of the output signal immediately after the edge timing of the trigger signal is delayed by less than a threshold value for a predetermined period compared to the edge timing of the trigger signal, the output divider reset unit controls the reset timing of the output divider not at the edge timing of the output signal immediately after the edge timing of the trigger signal but at the next edge timing of the output signal.

2. The phase locked loop circuit of claim 1.

3. When the edge timing (falling or rising timing) of the output signal immediately after the edge timing of the trigger signal is delayed by the predetermined period threshold or more compared to the edge timing of the trigger signal, the output divider reset unit controls the reset timing of the output divider at the edge timing of the output signal immediately after the edge timing of the trigger signal, without waiting for the next edge timing of the output signal.

3. The phase locked loop circuit of claim 2.

4. a ring oscillator that receives the output signal, forms a ring circuit, includes a plurality of delay elements, controls the delay amounts of the plurality of delay elements, and oscillates the output signal; a variation measuring unit that calculates correlations between the delay signals of the plurality of delay devices and the trigger signal over one round cycle of an output code of the fractional division of the feedback divider, and measures a variation between an edge timing of the trigger signal and an edge timing of the reference signal; a predetermined period threshold setting unit that sets the predetermined period threshold so that the predetermined period threshold is wider than a variation between an edge timing of the trigger signal and an edge timing of the reference signal; 4. The phase locked loop circuit according to claim 2, further comprising:

5. 2. A phased array antenna comprising a plurality of phase-locked loop circuits according to claim 1, wherein the reference signal and the trigger signal are input in the same phase to each of the phase-locked loop circuits, and the reference signal and the trigger signal are output in the same phase from the output divider.

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