Photo detector

Abstract

To make it possible to suppress interference between a plurality of wiring layers disposed on an interlayer insulating layer, thereby improving the degree of freedom in pixel design.SOLUTION: A photo detector includes a first substrate on which a photoelectric conversion element that accumulates an electric charge according to the amount of incident light is disposed, a second substrate stacked on the first substrate and on which at least a part of a pixel circuit that generates a pixel signal according to the electric charge accumulated in the photoelectric conversion element is disposed, and an interlayer insulating layer disposed between the first substrate and the second substrate and having two or more stacked wiring layers.SELECTED DRAWING: Figure 5B

Description

[Technical field]

[0001] The present disclosure relates to a light detection element. [Background technology]

[0002] An imaging element with a three-layer structure has been proposed in which a first substrate on which photoelectric conversion elements are arranged, a second substrate on which pixel circuits are arranged, and a third substrate on which circuits that perform signal processing on pixel signals are arranged are stacked (see Patent Document 1).

[0003] By disposing the pixel circuits on the second substrate different from the photoelectric conversion elements, the size of the photoelectric conversion elements disposed on the first substrate can be increased, and sensitivity can be improved. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2019 / 130702A1 Summary of the Invention [Problem to be solved by the invention]

[0005] In an image sensor with a three-layer structure, an interlayer insulating layer is disposed between a first substrate and a second substrate. In the interlayer insulating layer, a wiring layer for transferring the electric charge accumulated in the floating diffusion to the pixel circuit of the second substrate and a wiring layer connected to the ground node of the first substrate are disposed.

[0006] In existing three-layer image sensors, only one wiring layer can be arranged on the interlayer insulating layer. It is necessary to arrange multiple wiring layers, each of which has a different connection destination, on the interlayer insulating layer, which shortens the distance between the wiring layers and makes interference more likely to occur. In particular, it is desirable to arrange wiring layers with different types or amounts of impurities as far apart as possible to avoid interference, but when multiple wiring layers are arranged on only one layer, it becomes difficult to avoid interference between the wiring layers. In addition, when multiple wiring layers are arranged on one layer, layout design is time-consuming and design costs increase.

[0007] Therefore, the present disclosure provides a photodetector element capable of suppressing interference between a plurality of wiring layers disposed in an interlayer insulating layer and improving the degree of freedom in pixel design. [Means for solving the problem]

[0008] In order to solve the above problems, according to the present disclosure, there is provided a liquid crystal display device comprising: a first substrate on which a photoelectric conversion element is disposed; a second substrate that is stacked on the first substrate and has at least a part of a pixel circuit that generates a pixel signal according to the charge output from the photoelectric conversion element disposed thereon; and an interlayer insulating layer having two or more stacked wiring layers disposed between the first substrate and the second substrate. A light detecting element is provided.

[0009] The pixel circuit on the second substrate may have a pixel transistor including at least one of an amplification transistor, a reset transistor, or a selection transistor.

[0010] The wiring layer may be a polysilicon layer or a metal layer.

[0011] At least one of the type and concentration of impurity ions contained in the two or more wiring layers may be different from each other.

[0012] At least some of the two or more wiring layers may be disposed so as to intersect when viewed in a plan view.

[0013] The two or more wiring layers may include a floating diffusion to which charges generated in the photoelectric conversion element in the first substrate are transferred, a well region of a different conductivity type from the floating diffusion, a transfer transistor that switches whether or not to transfer charges generated in the photoelectric conversion element in the first substrate to the floating diffusion, or a plurality of wiring layers that are each connected to at least two of the pixel boundary regions of the first substrate.

[0014] The two or more wiring layers may include two or more wiring layers arranged in different layers of the interlayer insulating layer, and two or more wiring layers arranged in the same layer of the interlayer insulating layer.

[0015] The interlayer insulating layer is a plurality of first contacts each extending from at least a portion of the two or more wiring layers to the second substrate; and a plurality of second contacts extending from the plurality of wiring layers to the first substrate.

[0016] the interlayer insulating layer has a charge storage section that stores charges transferred from the photoelectric conversion element separately from a floating diffusion; The charge storage section may be configured using two wiring layers that are arranged opposite to each other among the two or more wiring layers.

[0017] A conversion efficiency switching transistor is provided for switching the photoelectric conversion efficiency, The charge storage section may store charges transferred from the photoelectric conversion element when the conversion efficiency switching transistor is on.

[0018] a third contact extending from a wiring layer disposed closer to the second substrate, of the two wiring layers constituting the charge storage unit, to the second substrate; A wiring layer disposed closer to the second substrate and a source of the conversion efficiency switching transistor may be electrically connected via the third contact.

[0019] a plurality of the conversion efficiency switching transistors capable of switching the photoelectric conversion efficiency in three or more stages and a plurality of the charge storage units are provided; The plurality of charge accumulation units may be disposed on the interlayer insulating layer, or some of the plurality of charge accumulation units may be disposed on the interlayer insulating layer and the remaining charge accumulation units may be disposed on the second substrate.

[0020] At least one of the two or more wiring layers may be a light-shielding layer that blocks light that has passed through the photoelectric conversion element and that blocks light from the second substrate.

[0021] The light blocking layer may be set to a predetermined reference potential.

[0022] Of the two or more wiring layers, the light-shielding layer and a wiring layer arranged in a layer different from the light-shielding layer may be arranged to cover the entire area of ​​the first substrate when viewed in a plane.

[0023] Of the two or more wiring layers, the light-shielding layer may have an area larger than an area of ​​a wiring layer disposed in a layer different from the light-shielding layer.

[0024] The light-shielding layer may have a solid pattern, a mesh pattern, or a slit pattern.

[0025] According to the present disclosure, a first substrate on which a photoelectric conversion element is arranged; a second substrate that is stacked on the first substrate and has at least a part of a pixel circuit that generates a pixel signal according to the charge output from the photoelectric conversion element disposed thereon; an interlayer insulating layer disposed between the first substrate and the second substrate and having one or more wiring layers; The wiring layer contains arsenic (As) and phosphorus (P). A light detecting element is provided.

[0026] The concentration of arsenic (As) in the wiring layer may be higher than the concentration of phosphorus (P).

[0027] According to the present disclosure, a first substrate on which a photoelectric conversion element is arranged; a second substrate that is stacked on the first substrate and has at least a part of a pixel circuit that generates a pixel signal according to the charge output from the photoelectric conversion element disposed thereon; an interlayer insulating layer disposed between the first substrate and the second substrate; The interlayer insulating layer is A wiring layer; a first contact extending from the wiring layer to the second substrate; an insulating layer disposed in a predetermined region including a connection portion of the wiring layer with the first contact; A light detecting element is provided. [Brief description of the drawings]

[0028] [Figure 1] FIG. 1 is a diagram showing a schematic configuration of a photodetector according to the present disclosure. [Diagram 2] FIG. 2 is a diagram showing an example of a pixel circuit according to the first embodiment. [Diagram 3] FIG. 2 is a diagram showing an example of a longitudinal sectional configuration (vertical sectional configuration) of a light detection element according to the present disclosure. [Figure 4] FIG. 2 is a planar layout diagram of the light detection element according to the first embodiment. [Figure 5A] 5 is a cross-sectional view of the substrate in the depth direction taken along line A-A'-B'-B in FIG. 4. [Figure 5B] FIG. 5 is a cross-sectional view of line CD in FIG. 4 in the substrate depth direction. [Figure 6] FIG. 2 is a plan view of a first wiring layer and a second wiring layer. [Figure 7] FIG. 4 is a planar layout diagram of a photodetector according to a comparative example. [Figure 8A] 8 is a cross-sectional view taken along line A-A'-B'-B in FIG. 7 in the substrate depth direction. [Figure 8B] 8 is a cross-sectional view of line CD in FIG. 7 in the substrate depth direction. [Figure 9A] FIG. 2 is a planar layout diagram showing the arrangement of color filters according to the first example. [Figure 9B] FIG. 2 is a circuit diagram of a pixel and a pixel circuit according to a first example. [Figure 10A] FIG. 11 is a planar layout diagram showing the arrangement of color filters according to the second example. [Figure 10B] FIG. 11 is a circuit diagram of a pixel and a pixel circuit according to a second example. [Figure 11A] FIG. 11 is a planar layout diagram showing the arrangement of color filters according to a third example. [Figure 11B] FIG. 11 is a circuit diagram of a pixel and a pixel circuit according to a third example. [Figure 12] FIG. 11 is a cross-sectional view showing locations of a first wiring layer and a second wiring layer in a photodetector element according to a second embodiment. [Figure 13A] FIG. 11 is a planar layout diagram showing the distance between a first through contact on a second wiring layer and a second through contact on a third wiring layer. [Figure 13B] FIG. 4 is a planar layout diagram showing an empty area of ​​the second substrate. [Figure 14] FIG. 4 is a cross-sectional view showing locations of a first wiring layer, a second wiring layer, and a third wiring layer in a photodetector element according to a comparative example. [Figure 15A] FIG. 11 is a planar layout diagram showing the distance between a first via contact and a second via contact in a comparative example. [Figure 15B] FIG. 11 is a planar layout diagram showing a space area of ​​a second substrate in a comparative example. [Figure 16A] FIG. 11 is a planar layout diagram of a first substrate of a light detection element according to a third embodiment. [Figure 16B] FIG. 13 is a planar layout diagram of a second substrate of a light detection element according to a third embodiment. [Figure 17A] FIG. 4 is a planar layout diagram of a first substrate according to a comparative example. [Figure 17B] FIG. 11 is a planar layout diagram of a second substrate according to a comparative example. [Figure 18] FIG. 11 is a cross-sectional view of a light detection element according to a fourth embodiment. [Figure 19] FIG. 4 is a cross-sectional view of a photodetector according to a comparative example. [Figure 20A]13A to 13C are cross-sectional views showing the manufacturing process of the photodetector according to the fifth embodiment. [Figure 20B] 20B is a cross-sectional view showing a manufacturing process subsequent to FIG. 20A. [Figure 20C] 20C is a cross-sectional view showing a manufacturing process subsequent to FIG. 20B. [Figure 20D] 20D is a cross-sectional view showing a manufacturing process subsequent to FIG. 20C. [Figure 20E] 20E is a cross-sectional view showing a manufacturing process subsequent to FIG. 20D. [Figure 20F] 20E is a cross-sectional view showing a manufacturing process subsequent to FIG. 20E. [Figure 20G] 20F , in cross-sectional view showing the manufacturing process following FIG. 20F . [Figure 20H] 20G; FIG. [Figure 20I] 20H is a cross-sectional view showing a manufacturing process subsequent to FIG. 20H. [Figure 20J] 20I; FIG. 20I is a cross-sectional view showing a manufacturing process following FIG. [Figure 20K] 20A to 20J are cross-sectional views showing the manufacturing process following FIG. 20J. [Figure 20L] 20K is a cross-sectional view showing a manufacturing process subsequent to FIG. 20K. [Figure 20M] 20B is a cross-sectional view showing a manufacturing process subsequent to FIG. 20L. [Figure 20N] 20A to 20C are cross-sectional views showing the manufacturing process following FIG. 20M. [Figure 20O] 20N; FIG. [Figure 21A] FIG. 13 is a circuit diagram of a pixel circuit included in a photodetector element according to a sixth embodiment. [Figure 21B] 22B is a cross-sectional view taken along line AB in FIG. 22A in the substrate depth direction. [Figure 22A] FIG. 13 is a planar layout diagram of a light detection element according to a sixth embodiment. [Figure 22B] 22B is a cross-sectional view taken along line AB in FIG. 22A in the substrate depth direction. [Figure 23A] FIG. 4 is a planar layout diagram of a photodetector according to a comparative example. [Figure 23B] 23B is a cross-sectional view taken along line AB in FIG. 23A in the substrate depth direction. [Figure 24A]FIG. 23 is a planar layout diagram of a light detecting element according to a modified example of the sixth embodiment. [Figure 24B] 24B is a cross-sectional view taken along line AB in FIG. 24A in the substrate depth direction. [Figure 25A] FIG. 25A is a planar layout diagram showing an example in which each tooth of the comb extends in the second direction. [Figure 25B] FIG. 4 is a planar layout diagram showing an example in which each tooth of a comb extends in a first direction. [Figure 26] FIG. 13 is a planar layout diagram of one pixel circuit of a photodetector according to a sixth embodiment. [Figure 27A] FIG. 23 is a circuit diagram of a pixel circuit of a photodetector according to a first modified example of the sixth embodiment. [Figure 27B] FIG. 27B is a planar layout diagram of the pixel circuit in FIG. 27A. [Figure 28A] FIG. 23 is a circuit diagram of a pixel circuit of a photodetector according to a second modified example of the sixth embodiment. [Figure 28B] 13 is a diagram showing the correspondence relationship between the on / off state of a conversion efficiency switching transistor and the conversion efficiency of a pixel circuit according to a second modified example. [Figure 28C] FIG. 11 is a planar layout diagram of a pixel circuit according to a second modified example. [Figure 29A] FIG. 23 is a circuit diagram of a pixel circuit of a photodetector according to a third modified example of the sixth embodiment. [Figure 29B] FIG. 13 is a planar layout diagram of a pixel circuit according to a third modified example. [Figure 30A] FIG. 23 is a circuit diagram of a pixel circuit of a photodetector according to a fourth modified example of the sixth embodiment. [Figure 30B] FIG. 13 is a diagram showing the correspondence relationship between the on / off state of a conversion efficiency switching transistor and the conversion efficiency of a pixel circuit according to a fourth modified example. [Figure 30C] FIG. 13 is a planar layout diagram of a pixel circuit according to a fourth modified example. [Figure 31A] FIG. 23 is a circuit diagram of a pixel circuit of a photodetector element according to a fifth modified example of the sixth embodiment. [Figure 31B] FIG. 13 is a planar layout diagram of a pixel circuit according to a fifth modified example. [Diagram 32] FIG. 13 is a cross-sectional view of a pixel circuit of a photodetector according to a sixth modified example. [Diagram 33]33 is a cross-sectional view of a pixel circuit having a cross-sectional structure of a second charge retaining portion different from that of FIG. 32. [Diagram 34] FIG. 23 is a diagram summarizing features of pixel circuits according to first to sixth modified examples of the sixth embodiment. [Diagram 35] 11 is a cross-sectional view for explaining a problem that occurs when a second substrate on which pixel transistors are arranged is laminated on a first substrate. [Diagram 36] FIG. 13 is a cross-sectional view of a photodetector according to a seventh embodiment, taken in a depth direction of a substrate. [Figure 37] 37A is a plan view of the optical shield layer, FIG. 37B is a cross-sectional view in the substrate depth direction along line AB in FIG. 37A, FIG. 37C is a cross-sectional view in the substrate depth direction along line CD in FIG. 37A, and FIG. 37D is a plan view of the optical shield layer and the first wiring layer combined. [Figure 38] 38A is a plan view of the optical shield layer, FIG. 38B is a cross-sectional view in the substrate depth direction along line AB in FIG. 38A, FIG. 38C is a cross-sectional view in the substrate depth direction along line CD in FIG. 38A, and FIG. 38D is an external view of a portion of the chip of the photodetector 1. [Figure 39] 39A is a plan view of the optical shield layer, FIG. 39B is a cross-sectional view in the substrate depth direction taken along line AB in FIG. 39A, and FIG. 39C is a cross-sectional view in the substrate depth direction taken along line CD in FIG. 39A. [Diagram 40] 40A is a plan view of the optical shield layer, FIG. 40B is a cross-sectional view in the substrate depth direction along line AB in FIG. 40A, FIG. 40C is a cross-sectional view in the substrate depth direction along line CD in FIG. 40A, and FIG. 40D is an external view of a portion of a light detecting element chip. [Diagram 41] 41A is a plan view of the optical shield layer, FIG. 41B is a cross-sectional view in the substrate depth direction taken along line AB in FIG. 41A, and FIG. 41C is a cross-sectional view in the substrate depth direction taken along line CD in FIG. 41A. [Diagram 42] 42A is a plan view of the optical shield layer, FIG. 42B is a cross-sectional view in the substrate depth direction along line AB in FIG. 42A, FIG. 42C is a cross-sectional view in the substrate depth direction along line CD in FIG. 42A, and FIG. 42D is an external view of a portion of the chip of the photodetector 1. [Diagram 43] 43A is a plan view of the optical shield layer, FIG. 43B is a cross-sectional view in the substrate depth direction taken along line AB in FIG. 43A, and FIG. 43C is a cross-sectional view in the substrate depth direction taken along line CD in FIG. 43A. [Diagram 44]44A is a plan view of the optical shield layer, FIG. 44B is a cross-sectional view in the substrate depth direction along line AB in FIG. 44A, FIG. 44C is a cross-sectional view in the substrate depth direction along line CD in FIG. 44A, and FIG. 44D is an external view of a portion of chip 21 of photodetector 1. [Diagram 45] 45A is a plan view of the optical shield layer, FIG. 45B is a cross-sectional view in the substrate depth direction taken along line AB in FIG. 45A, and FIG. 45C is a cross-sectional view in the substrate depth direction taken along line CD in FIG. 45A. [Figure 46] 46A is a plan view of the optical shield layer, FIG. 46B is a cross-sectional view in the substrate depth direction along line AB in FIG. 46A, FIG. 46C is a cross-sectional view in the substrate depth direction along line CD in FIG. 46A, and FIG. 46D is an external view of a portion of the chip of the photodetector 1. [Figure 47] 47A is a plan view of the optical shield layer, FIG. 47B is a cross-sectional view in the substrate depth direction taken along line AB in FIG. 47A, and FIG. 47C is a cross-sectional view in the substrate depth direction taken along line CD in FIG. 47A. [Figure 48] 48A is a plan view of the optical shield layer, FIG. 48B is a cross-sectional view in the substrate depth direction along line AB in FIG. 48A, FIG. 48C is a cross-sectional view in the substrate depth direction along line CD in FIG. 48A, and FIG. 48D is an external view of a portion of the chip of the photodetector 1. [Figure 49] 49A is a plan view of the optical shield layer, FIG. 49B is a cross-sectional view in the substrate depth direction taken along line AB in FIG. 49A, and FIG. 49C is a cross-sectional view in the substrate depth direction taken along line CD in FIG. 49A. [Figure 50] 50A is a plan view of the optical shield layer, FIG. 50B is a cross-sectional view in the substrate depth direction along line AB in FIG. 50A, FIG. 50C is a cross-sectional view in the substrate depth direction along line CD in FIG. 50A, and FIG. [Figure 51] 51A is a plan view of the optical shield layer, FIG. 51B is a cross-sectional view in the substrate depth direction taken along line AB in FIG. 51A, and FIG. 51C is a cross-sectional view in the substrate depth direction taken along line CD in FIG. 51A. [Figure 52] 52A is a plan view of the optical shield layer, FIG. 52B is a cross-sectional view in the substrate depth direction along line AB in FIG. 52A, FIG. 52C is a cross-sectional view in the substrate depth direction along line CD in FIG. 52A, and FIG. 52D is an external view of a portion of the chip of the photodetector 1. [Figure 53]53A is a plan view of the optical shield layer, FIG. 53B is a cross-sectional view in the substrate depth direction taken along line AB in FIG. 53A, and FIG. 53C is a cross-sectional view in the substrate depth direction taken along line CD in FIG. 53A. [Figure 54] 54A is a plan view of the optical shield layer, FIG. 54B is a cross-sectional view in the substrate depth direction along line AB in FIG. 54A, FIG. 54C is a cross-sectional view in the substrate depth direction along line CD in FIG. 54A, and FIG. 54D is an external view of a portion of the chip of the photodetector 1. [Figure 55] 55A is a plan view of the optical shield layer, FIG. 55B is a cross-sectional view in the substrate depth direction taken along line AB in FIG. 55A, and FIG. 55C is a cross-sectional view in the substrate depth direction taken along line CD in FIG. 55A. [Figure 56] 56A is a plan view of the optical shield layer, FIG. 56B is a cross-sectional view in the substrate depth direction along line AB in FIG. 56A, FIG. 56C is a cross-sectional view in the substrate depth direction along line CD in FIG. 56A, and FIG. 56D is an external view of a portion of the chip of the photodetector 1. [Figure 57] 57A is a plan view of the optical shield layer, FIG. 57B is a cross-sectional view in the substrate depth direction taken along line AB in FIG. 57A, FIG. 57C is a cross-sectional view in the substrate depth direction taken along line CD in FIG. 57A, and FIG. 57D is a cross-sectional view in the substrate depth direction taken along line EF. [Figure 58] FIG. 23 is a diagram summarizing various modified examples of the seventh embodiment. [Figure 59A] A comparison of the sheet resistance of arsenic (As) and phosphorus (P) ions. [Figure 59B] A comparison of the diffusion lengths in silicon doped with arsenic (As) and phosphorus (P) ions. [Figure 60] FIG. 13 is a cross-sectional view of a light detection element according to an eighth embodiment. [Figure 61] FIG. 23 is a cross-sectional view of a light detecting element according to a first modified example of the eighth embodiment. [Figure 62] FIG. 23 is a cross-sectional view of a light detecting element according to a second modified example of the eighth embodiment. [Figure 63] FIG. 23 is a cross-sectional view of the photodetector 1 according to a third modified example of the eighth embodiment. [Fig. 64A] 13A to 13C are cross-sectional views showing steps of manufacturing the photodetector according to the eighth embodiment. [Figure 64B] 64B is a cross-sectional view of a manufacturing process following FIG. 64A. [Fig. 64C]64C is a cross-sectional view of a manufacturing process following FIG. 64B. [Fig.64D] Cross-sectional view of the manufacturing process following Figure 64C. [Figure 64E] Cross-sectional view of the manufacturing process following Figure 64D. [Fig.64F] Cross-sectional view of the manufacturing process following Figure 64E. [Figure 64G] Cross-sectional view of the manufacturing process following Figure 64F. [Fig.64H] Cross-sectional view of the manufacturing process following Figure 64G. [Fig.64I] Cross-sectional view of the manufacturing process following Figure 64H. [Figure 65A] FIG. 13 is a vertical sectional view of a light detection element according to a ninth embodiment. [Figure 65B] A cross-sectional view taken along line AB in Figure 65A. [Figure 66A] FIG. 23 is a vertical sectional view of a light detecting element according to a first modified example of the ninth embodiment. [Figure 66B] A cross-sectional view taken along line AB in Figure 66A. [Figure 67A] FIG. 23 is a vertical sectional view of a light detecting element according to a second modified example of the ninth embodiment. [Figure 67B] A cross-sectional view taken along line AB in Figure 67A. [Figure 68A] FIG. 23 is a vertical sectional view of a light detecting element according to a third modified example of the ninth embodiment. [Figure 68B] A cross-sectional view taken along line AB in Figure 68A. [Figure 69A] FIG. 23 is a vertical sectional view of a photodetector according to a fourth modified example of the ninth embodiment. [Figure 69B] A cross-sectional view taken along line AB in Figure 69A. [Figure 70A] FIG. 23 is a vertical sectional view of a photodetector according to a fifth modified example of the ninth embodiment. [Figure 70B] A cross-sectional view taken along line AB in Figure 70A. [Figure 71A] FIG. 23 is a vertical sectional view of a photodetector according to a sixth modified example of the ninth embodiment. [Figure 71B] A cross-sectional view taken along line AB in Figure 71A. [Figure 72A]13A and 13B are plan views and cross-sectional views illustrating a manufacturing process of a photodetector element according to a ninth embodiment. [Fig. 72B] 72B is a plan view and cross-sectional views showing a manufacturing process subsequent to FIG. 72A. [Fig. 72C] 72C and 72D are plan and cross-sectional views showing the manufacturing process following FIG. 72B. [Fig. 72D] 72D and 72E are plan and cross-sectional views showing the manufacturing process following FIG. 72C. [Fig. 72E] 72D and 72C are plan views and cross-sectional views showing the manufacturing process following FIG. 72D. [Fig. 72F] 72E and 72F are plan views and cross-sectional views showing the manufacturing process following FIG. 72E. [Fig. 72G] 72F and 72C are plan and cross-sectional views showing the manufacturing process following FIG. 72F. [Fig. 72H] 72C and 72D are plan views and cross-sectional views showing the manufacturing process following FIG. 72G. [Fig. 72I] 72H and 72H are plan and cross-sectional views showing the manufacturing process following FIG. 72H. [Fig. 72J] 72I and 72I-II. [Figure 72K] 72J; FIG. 72C is a plan view and cross-sectional views showing the manufacturing process following FIG. 72J; [Fig. 72L] 72K. FIG. 72K is a plan view and cross-sectional views showing the manufacturing process. [Figure 73] FIG. 1 is a block diagram showing an example of a schematic configuration of a vehicle control system. [Figure 74] FIG. 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, an embodiment of a light detection element will be described with reference to the drawings. The following description will focus on the main components of the light detection element, but the light detection element may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0030] (Schematic configuration of the photodetector element) FIG. 1 is a diagram showing a schematic configuration of a light detection element 1 according to the present disclosure. As shown in FIG. 1, the light detection element 1 includes three substrates, namely, a first substrate 10, a second substrate 20, and a third substrate 30. The structure of the light detection element 1 is a three-dimensional structure formed by bonding together the three substrates, the first substrate 10, the second substrate 20, and the third substrate 30. The first substrate 10, the second substrate 20, and the third substrate 30 are laminated in the order described. The first substrate 10 is the first layer, the second substrate 20 is the second layer, and the third substrate 30 is the third layer.

[0031] The first substrate 10 includes a semiconductor substrate 11 and a plurality of sensor pixels 12 that perform photoelectric conversion. Hereinafter, the sensor pixels 12 will be simply referred to as pixels. The semiconductor substrate 11 has a plurality of pixels 12. These pixels 12 are arranged in a matrix (two-dimensional array) in a pixel region 13 in the first substrate 10. Each pixel 12 has a photoelectric conversion element and a transfer transistor, as described later. A pixel circuit is connected to each pixel 12.

[0032] The second substrate 20 includes a semiconductor substrate 21, a pixel circuit 22 that outputs a pixel signal, a plurality of pixel drive lines 23 extending in the row direction, and a plurality of vertical signal lines 24 extending in the column direction. The semiconductor substrate 21 has one pixel circuit 22 for every four pixels 12. This pixel circuit 22 outputs a pixel signal based on the charge output from the pixel 12. The pixel circuit 22 is also called a readout circuit.

[0033] The third substrate 30 includes a semiconductor substrate 31 and a logic circuit 32 that processes pixel signals. The semiconductor substrate 31 includes the logic circuit 32. The logic circuit 32 includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36.

[0034] The logic circuit 32 outputs to the outside an output voltage Vout for each pixel 12. In the logic circuit 32, for example, a low-resistance region made of silicide such as CoSi2 or NiSi formed by a salicide (Self Aligned Silicide) process may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.

[0035] The vertical drive circuit 33, for example, selects the pixels 12 in sequence on a row-by-row basis.

[0036] The column signal processing circuit 34 performs, for example, correlated double sampling (CDS) processing on pixel signals output from each pixel 12 in a row selected by the vertical drive circuit 33. For example, the column signal processing circuit 34 extracts a signal level of each pixel signal by executing the CDS processing, and holds pixel data according to the amount of light received by each pixel 12.

[0037] The horizontal drive circuit 35 sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside, for example.

[0038] The system control circuit 36 ​​controls the driving of each block in the logic circuit 32 (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35), for example.

[0039] (An example of a pixel circuit) Next, an example of a pixel circuit according to the first embodiment will be described with reference to Fig. 2. Fig. 2 is a diagram showing an example of a pixel circuit according to the first embodiment.

[0040] 2, four pixels 12 share one pixel circuit 22. Here, "shared" means that the four pixels 12 are electrically connected to a common pixel circuit 22, that is, the outputs of the four pixels 12 are input to the common pixel circuit 22.

[0041] Each pixel 12 has components in common with the others. In Fig. 2, in order to distinguish the components of each pixel 12 from one another, an identification number (1, 2, 3, 4) is added to the end of the reference numeral of the component of each pixel 12. In the following, when it is necessary to distinguish the components of each pixel 12 from one another, an identification number is added to the end of the reference numeral of the component of each pixel 12, but when it is not necessary to distinguish the components of each pixel 12 from one another, the identification number at the end of the reference numeral of the component of each pixel 12 is omitted.

[0042] Each pixel 12 has, for example, a photodiode PD and a transfer transistor TR electrically connected to the photodiode PD. These pixels 12 share a floating diffusion FD electrically connected to each transfer transistor TR. Here, "shared" means that the individual photodiode PD of each pixel 12 is electrically connected to the floating diffusion FD. The photodiode PD, transfer transistor TR, floating diffusion FD, etc. are provided on, for example, the first substrate 10.

[0043] The photodiode PD performs photoelectric conversion to generate charges according to the amount of light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The photodiode PD is an example of a photoelectric conversion element.

[0044] The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR, that is, the transfer gate TG, is electrically connected to the pixel drive line 23 (see FIG. 1). The transfer transistor TR is, for example, a CMOS (Complementary Metal Oxide Semiconductor) transistor.

[0045] The floating diffusion FD is common to each pixel 12 that shares one pixel circuit 22, and is electrically connected to the input terminal of the pixel circuit 22 common to those pixels 12. This floating diffusion FD temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The floating diffusion FD is an example of a floating diffusion layer.

[0046] The pixel circuit 22 has, for example, a reset transistor RST, a selection transistor SEL, an amplification transistor AMP, and an FD transfer transistor FDG. The reset transistor RST, the selection transistor SEL, the amplification transistor AMP, the FD transfer transistor FDG, and the like are provided, for example, on the second substrate 20 or the third substrate 30. The reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the FD transfer transistor FDG are, for example, CMOS transistors. Note that the selection transistor SEL and the FD transfer transistor FDG may be omitted as necessary.

[0047] The source of the FD transfer transistor FDG (the input terminal of the pixel circuit 22) is electrically connected to the floating diffusion FD, and the drain of the FD transfer transistor FDG is electrically connected to the source of the reset transistor RST. The gate of the FD transfer transistor FDG is electrically connected to the pixel drive line 23 (see FIG. 1).

[0048] The drain of the reset transistor RST is electrically connected to a power supply line VDD, and the gate of the reset transistor RST is electrically connected to a pixel drive line 23 (see FIG. 1).

[0049] The source of the amplifier transistor AMP is electrically connected to the drain of the selection transistor SEL, the drain of the amplifier transistor AMP is electrically connected to a power supply line VDD, and the gate of the amplifier transistor AMP is electrically connected to the source of the FD transfer transistor FDG.

[0050] The drain of the selection transistor SEL (the output terminal of the pixel circuit 22) is electrically connected to a vertical signal line 24 (VSL in FIG. 2), and the gate of the selection transistor SEL is electrically connected to a pixel drive line 23 (see FIG. 1).

[0051] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD.

[0052] The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 22.

[0053] The amplification transistor AMP generates a pixel signal whose voltage corresponds to the level of the charge held in the floating diffusion FD. The amplification transistor AMP constitutes a source-follower type amplifier, and outputs a pixel signal whose voltage corresponds to the level of the charge generated in the photodiode PD.

[0054] When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage according to the potential to the column signal processing circuit 34 (see FIG. 1) via the vertical signal line 24.

[0055] The FD transfer transistor FDG is used to switch the conversion efficiency. Generally, pixel signals are small when shooting in dark places. Based on Q=CV, when performing charge-to-voltage conversion, if the capacitance of the floating diffusion FD (FD capacitance C) is large, V when converted to voltage by the amplifier transistor AMP will be small. On the other hand, in bright places, the pixel signal is large, so if the FD capacitance C is not large, the floating diffusion FD will not be able to receive the charge of the photodiode PD. Furthermore, the FD capacitance C needs to be large so that V when converted to voltage by the amplifier transistor AMP does not become too large (in other words, so that it becomes small).

[0056] In other words, when the FD transfer transistor FDG is turned on, the gate capacitance of the FD transfer transistor FDG increases, and the overall FD capacitance C increases. On the other hand, when the FD transfer transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the FD transfer transistor FDG on and off, the FD capacitance C can be made variable, and the conversion efficiency can be switched.

[0057] (Cross-sectional structure of photodetector element 1) An example of a cross-sectional configuration of a light detection element 1 according to the present disclosure will be described with reference to Fig. 3. Fig. 3 is a diagram showing an example of a longitudinal cross-sectional configuration (cross-sectional configuration in the vertical direction) of a light detection element 1 according to the present disclosure.

[0058] 3, the photodetector 1 is configured by laminating a first substrate 10, a second substrate 20, and a third substrate 30 in the stated order, and further includes a color filter 40 and a light receiving lens 50 on the back surface side (light incident surface side) of the first substrate 10. For example, one color filter 40 and one light receiving lens 50 are each provided for each pixel 12. In other words, the photodetector 1 is a back-illuminated type.

[0059] The first substrate 10 is configured by laminating an insulating layer 46 on a semiconductor substrate 11. The insulating layer 46 is also called an interlayer insulating layer. The insulating layer 46 is provided in the gap between the semiconductor substrate 11 and a semiconductor substrate 21, which will be described later.

[0060] The semiconductor substrate 11 is made of a silicon substrate. The semiconductor substrate 11 has, for example, a p-well layer 42 in a part of the surface and in the vicinity thereof, and has a photodiode PD of a different conductivity type from the p-well layer 42 in the other region (region deeper than the p-well layer 42). The p-well layer 42 is made of a p-type semiconductor region. The photodiode PD is made of a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42. The semiconductor substrate 11 has a floating diffusion FD in the p-well layer 42 as a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42.

[0061] In the example of Fig. 3, one floating diffusion FD has four adjacent diffusion layers (floating diffusion layers) FDa and one connection layer FDb. The diffusion layer FDa is provided for each photodiode PD, and the diffusion layers FDa of the four adjacent photodiodes PD are electrically connected by one connection layer FDb. The connection layer FDb is positioned above each diffusion layer FDa so as to be in contact with each diffusion layer FDa, and is provided in the insulating layer 46. This connection layer FDb is formed of the same material (e.g., polysilicon) as the transfer gate TG.

[0062] The first substrate 10 has a photodiode PD and a transfer transistor TR for each pixel 12, and further has a floating diffusion FD and a well tap WT shared by four pixels 12. The transfer transistor TR, the floating diffusion FD, and the well tap WT are provided on the front surface side (the side opposite to the light incident surface side, the second substrate 20 side) of the semiconductor substrate 11. The well tap WT is electrically connected to the p-well layer 42 (for example, a well contact formed in the p-well layer 42).

[0063] The first substrate 10 has an element isolation portion 43 that isolates each pixel 12. The element isolation portion 43 is formed so as to extend in a normal direction of the semiconductor substrate 11 (a direction perpendicular to the surface of the semiconductor substrate 11). The element isolation portion 43 is provided between two adjacent pixels 12. The element isolation portion 43 electrically isolates the adjacent pixels 12. The element isolation portion 43 is made of, for example, silicon oxide. The element isolation portion 43 penetrates, for example, the semiconductor substrate 11 (full trench), and completely isolates two or more adjacent pixels 12 electrically.

[0064] The color filter 40 is provided on the back surface side of the semiconductor substrate 11. The color filter 40 is provided, for example, in contact with the back surface of the semiconductor substrate 11 and at a position facing the pixels 12. The light receiving lens 50 is provided, for example, in contact with the back surface of the color filter 40 and at a position facing the pixels 12 with the color filter 40 interposed therebetween.

[0065] The second substrate 20 is configured by laminating an insulating layer 52 on a semiconductor substrate 21. The insulating layer 52 is also called an interlayer insulating layer. The insulating layer 52 is provided in the gap between the semiconductor substrate 21 and a semiconductor substrate 31 described below. The semiconductor substrate 21 is configured by a silicon substrate.

[0066] The second substrate 20 has one pixel circuit 22 for every four pixels 12 (see FIGS. 2 and 3). The pixel circuits 22 are provided on the back surface side (first substrate 10 side) of the semiconductor substrate 21. The second substrate 20 is bonded to the first substrate 10 with the back surface of the semiconductor substrate 21 facing the front surface side of the semiconductor substrate 11. In other words, the second substrate 20 is bonded to the first substrate 10 face-to-back.

[0067] The second substrate 20 further includes an insulating layer 53 that is in the same layer as the semiconductor substrate 21 and penetrates the semiconductor substrate 21. The insulating layer 53 is also called an interlayer insulating layer. The insulating layer 53 is provided so as to cover the side surfaces of the through wiring 54 described below.

[0068] As described above, the laminated body made up of the first substrate 10 and the second substrate 20 has the interlayer insulating layer 51 including the insulating layer 46, the insulating layer 52, and the insulating layer 53, and the through wiring 54 provided in the interlayer insulating layer 51. The above laminated body has one through wiring 54 for every four pixels 12. The through wiring 54 extends in the normal direction of the semiconductor substrate 21, and is provided so as to penetrate a portion of the interlayer insulating layer 51 including the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other by the through wiring 54. The through wiring 54 is, for example, a through contact for the floating diffusion FD (FD1 to FD4).

[0069] The laminated body consisting of the first substrate 10 and the second substrate 20 also has another through-wiring (not shown) provided in the interlayer insulating layer 51. Like the above-mentioned through-wiring 54, this through-wiring also extends in the normal direction of the semiconductor substrate 21 and is provided penetrating a portion of the interlayer insulating layer 51 that includes an insulating layer having the same configuration as the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other by the through-wiring. This through-wiring is, for example, a through contact for the transfer gate TG or a through contact for the well tap WT.

[0070] The second substrate 20 has, for example, a plurality of connection parts 59 electrically connected to the pixel circuits 22 and the semiconductor substrate 21 in the insulating layer 52. Furthermore, the second substrate 20 has, for example, a wiring layer 56 on the insulating layer 52. The wiring layer 56 has, for example, an insulating layer 57, and a plurality of pixel driving lines 23 and a plurality of vertical signal lines 24 provided in the insulating layer 57. The wiring layer 56 further has, for example, connection wiring 55 in the insulating layer 57 for each floating diffusion FD. The connection wiring 55 is electrically connected to the through wiring 54 connected to the floating diffusion FD.

[0071] Here, the total number of through wirings 54 functioning as through contacts for the floating diffusion FD is smaller than the total number of pixels 12 included in the first substrate 10, and for example, since the number of pixels 12 sharing the floating diffusion FD is four, it is 1 / 4 times the total number of pixels 12 included in the first substrate 10. Similarly, the total number of through wirings (not shown) functioning as through contacts for the transfer gates TG and the total number of through wirings (not shown) functioning as through contacts for the well taps WT are, for example, 1 / 4 times the total number of pixels 12 included in the first substrate 10.

[0072] The wiring layer 56 further has, for example, a plurality of pad electrodes 58 in the insulating layer 57. Each pad electrode 58 is formed of, for example, a metal such as Cu (copper) or Al (aluminum). Each pad electrode 58 is exposed on the surface of the wiring layer 56. Each pad electrode 58 is used for electrical connection between the second substrate 20 and the third substrate 30 and for bonding the second substrate 20 and the third substrate 30 together. Each pad electrode 58 is provided, for example, for each pixel driving line 23 and each vertical signal line 24.

[0073] The third substrate 30 is configured, for example, by laminating an interlayer insulating layer 61 on a semiconductor substrate 31. The semiconductor substrate 31 is configured of a silicon substrate. As described later, the third substrate 30 is bonded to the second substrate 20 with their front surfaces facing each other, and therefore, when describing the internal configuration of the third substrate 30, the description of the top and bottom is reversed from the top and bottom direction in the drawings.

[0074] The third substrate 30 is configured such that a logic circuit 32 is provided on a portion of the front surface side of a semiconductor substrate 31. The third substrate 30 has, for example, a wiring layer 62 on an interlayer insulating layer 61. The wiring layer 62 has, for example, an insulating layer 63 and a plurality of pad electrodes 64 provided in the insulating layer 63. Each pad electrode 64 is electrically connected to the logic circuit 32. Each pad electrode 64 is formed of, for example, Cu (copper). Each pad electrode 64 is exposed on the surface of the wiring layer 62. Each pad electrode 64 is used for electrical connection between the second substrate 20 and the third substrate 30 and for bonding the second substrate 20 and the third substrate 30 together. The number of pad electrodes 64 does not necessarily have to be multiple.

[0075] The third substrate 30 and the second substrate 20 are electrically connected to each other by bonding the pad electrodes 58, 64. The third substrate 30 is bonded to the second substrate 20 with the front surface of the semiconductor substrate 31 facing the front surface of the semiconductor substrate 21. In other words, the third substrate 30 is bonded to the second substrate 20 face-to-face.

[0076] (First embodiment) As described above, an insulating layer (interlayer insulating layer) 46 is disposed between the first substrate 10 and the second substrate 20. In this specification, the insulating layer 46 may be referred to as an intermediate layer 70. In the cross-sectional structure of the photodetector 1 shown in FIG. 3, all the wiring layers 71 disposed in the intermediate layer 70 have the same layer height (hereinafter referred to as layers). In the intermediate layer 70, a plurality of wiring layers 71 are disposed, including a wiring layer 71a for setting the p-well layer 42 of the first substrate 10 to a ground potential, a wiring layer 71b for transferring the charge accumulated in the floating diffusion FD to the pixel circuit 22 of the second substrate 20, and a wiring layer 71c connected to the transfer gate TG. The potentials of these wiring layers 71 are not the same, and their electrical characteristics such as resistance values ​​are also different, and the type and amount of impurity ions doped into each wiring layer 71 are also different. For this reason, in order to dispose a plurality of wiring layers 71 in the same layer of the intermediate layer 70, it is necessary to separate the wiring layers 71 as far as possible to suppress interference, which makes it impossible to reduce the area of ​​the intermediate layer 70.

[0077] Each wiring layer 71 disposed in the intermediate layer 70 is formed of a polysilicon layer or a metal layer. In this specification, an example in which each wiring layer 71 disposed in the intermediate layer 70 is formed of a polysilicon layer will be mainly described.

[0078] Furthermore, at least one of the type and concentration of impurity ions contained in each wiring layer 71 arranged in the intermediate layer 70 may differ from one another. At least a portion of two or more wiring layers 71 arranged in different layers among the multiple wiring layers 71 arranged in the intermediate layer 70 may be arranged to overlap or intersect when viewed in a plan view.

[0079] Fig. 4 is a planar layout diagram of the photodetector 1 according to the first embodiment. Fig. 4 shows an example in which a floating diffusion FD and a pixel circuit 22 are shared by four pixels 12. The black circles in Fig. 4 are through contacts 72 (72b) extending from the wiring layer 71 of the intermediate layer 70 to the second substrate 20, and may be simply referred to as contacts in this specification.

[0080] Fig. 5A is a cross-sectional view in the substrate depth direction taken along line A-A'-B'-B in Fig. 4, and Fig. 5B is a cross-sectional view in the substrate depth direction taken along line CD in Fig. 4. The photodetector element 1 according to the first embodiment has a structure in which two or more wiring layers 71 are laminated on an intermediate layer 70. In the examples of Figs. 5A and 5B, a first wiring layer 71a, a second wiring layer 71b, and a third wiring layer 71c are arranged on the intermediate layer 70.

[0081] The first wiring layer 71a, the second wiring layer 71b, and the third wiring layer 71c are disposed in different layers of the intermediate layer 70. More specifically, the first wiring layer 71a is disposed on a side of the intermediate layer 70 closer to the first substrate 10. The second wiring layer 71b and the third wiring layer 71c are disposed on a side of the intermediate layer 70 closer to the second substrate 20. That is, the second wiring layer 71b and the third wiring layer 71c are disposed above (on the front surface side of) the first wiring layer 71a.

[0082] As described later, the photodetector element 1 according to this embodiment may employ a modified example in which the first wiring layer 71a, the second wiring layer 71b, and the third wiring layer 71c are arranged in reverse order.

[0083] The first wiring layer 71a is connected to the p-well layer 42 of the first substrate 10 via the first contact 73a. The second wiring layer 71b is connected to the floating diffusion FD of the first substrate 10 via the second contact 73b. The third wiring layer 71c is connected to the transfer gate TG of the first substrate 10 via the third contact 73c. ​​A first through contact 72a extending from the intermediate layer 70 toward the second substrate 20 is connected to the second wiring layer 71b. The first through contact 72a extends upward through the insulating layer 29 of the second substrate 20. A second through contact 72b extending from the intermediate layer 70 toward the second substrate 20 is connected to the third wiring layer 71c. The first through contact 72a and the second through contact 72b are connected to the pixel circuit 22 disposed on the second substrate 20. In this specification, the through contact may be called a TCS (Through Contact Substrate).

[0084] 5A and 5B, of the first to third wiring layers 71a, 71b, and 71c arranged on the intermediate layer 70, the first wiring layer 71a is arranged on a layer different from the second wiring layer 71b and the third wiring layer 71c. This makes it possible to widen the intervals between the first to third wiring layers 71a, 71b, and 71c, suppress interference between the first to third wiring layers 71a, 71b, and 71c, and eliminate the problem of the resistance values ​​of the first to third wiring layers 71a, 71b, and 71c increasing due to interference.

[0085] FIG. 6 is a plan view of the first wiring layer 71a and the second wiring layer 71b. More specifically, FIG. 6A is a plan view of the first wiring layer 71a, FIG. 6B is a plan view of the second wiring layer 71b, and FIG. 6C is a plan view of the first wiring layer 71a and the second wiring layer 71b superimposed on each other. As shown in FIG. 6A, the first wiring layer 71a connected to the p-well layer 42 is disposed along the boundary region of the pixel 12. The second wiring layer 71b connected to the floating diffusion FD is disposed so as to straddle two pixels 12 on each of the upper, lower, left and right sides. Since the first wiring layer 71a and the second wiring layer 71b are disposed on different layers of the intermediate layer 70, there is no risk of the first wiring layer 71a and the second wiring layer 71b being short-circuited even if the first wiring layer 71a and the second wiring layer 71b are crossed when viewed in a plan view as in FIG. 6C.

[0086] Fig. 7 is a planar layout diagram of a photodetector 100 according to a comparative example. Fig. 8A is a cross-sectional view in the substrate depth direction taken along line AA'-B'-B in Fig. 7, and Fig. 8B is a cross-sectional view in the substrate depth direction taken along line CD in Fig. 7.

[0087] In the photodetector element 100 according to the comparative example, the layers of the multiple wiring layers 71 arranged in the intermediate layer 70 are the same. For this reason, as shown in Fig. 8A, it is necessary to separate the multiple wiring layers 71 (71b) doped with different impurity ions as far as possible. However, in some places, as shown in Fig. 8B, the distance between the multiple wiring layers 71 (71c) cannot be sufficiently secured, causing interference and causing problems such as an increase in the resistance value of the wiring layers 71.

[0088] In the photodetector element 1 of the first embodiment, multiple wiring layers 71 (71a to 71c) having different types or doping amounts of impurity ions are arranged in different layers of the intermediate layer 70, making it easier to ensure the distance between the wiring layers 71 and suppressing interference.

[0089] In the photodetector 1 according to this embodiment, a floating diffusion FD and a pixel circuit 22 may be arranged for each pixel 12, or a set of floating diffusion FD and pixel circuit 22 may be shared by a plurality of pixels 12. The number of pixels 12 sharing a floating diffusion FD and a pixel circuit 22 is arbitrary, and various modified examples are possible.

[0090] 9A and 9B are circuit diagrams of a first example of a pixel 12 and a pixel circuit 22, with Fig. 9A being a planar layout diagram showing the arrangement of a color filter 40 according to the first example, and Fig. 9B being a circuit diagram of a pixel 12 and a pixel circuit 22 according to the first example. In the first example, 4 x 4 = 16 pixels 12 share one set of a floating diffusion FD and a pixel circuit 22. In Fig. 9A, differences in color of the color filter 40 are represented by differences in shading.

[0091] As shown in Fig. 9A, in the first example, color filters 40 of the same color are arranged in units of four pixels 12 in a first direction (horizontal direction) X and a second direction (vertical direction) Y. Also, as shown in Fig. 9B, in the first example, a set of floating diffusion FD and pixel circuit 22 is shared by a unit of 4 × 4 = 16 pixels 12 of the same color.

[0092] 9B, each pixel 12 has a photodiode PD and a transfer transistor TR. Each pixel circuit 22 has a plurality of pixel transistors including an amplifier transistor AMP, a reset transistor RST, a selection transistor SEL, and a conversion efficiency switching transistor FDG. The conversion efficiency switching transistor FDG may be omitted.

[0093] 10A and 10B are circuit diagrams of a second example of the pixel 12 and the pixel circuit 22, where Fig. 10A is a planar layout diagram showing the arrangement of the color filter 40 according to the second example, and Fig. 10B is a circuit diagram of the pixel 12 and the pixel circuit 22 according to the second example. In the second example, the floating diffusion FD and the pixel circuit 22 are shared by 4 x 2 = 8 pixels 12.

[0094] 10A, in the second example, color filters 40 of the same color are arranged in a unit of four pixels 12 in the first direction (horizontal direction) X and two pixels 12 in the second direction (vertical direction) Y. Also, in the second example, a set of floating diffusion FD and pixel circuit 22 is shared by a unit of 4×2=8 pixels 12 of the same color, as shown in FIG 10B.

[0095] 11A and 11B are circuit diagrams of a third example of a pixel 12 and a pixel circuit 22, where Fig. 11A is a planar layout diagram showing the arrangement of a color filter 40 according to the third example, and Fig. 11B is a circuit diagram of a pixel 12 and a pixel circuit 22 according to the third example. In the third example, one set of floating diffusion FD and pixel circuit 22 is shared by 8 x 4 = 32 pixels 12.

[0096] 11A, in the third example, color filters 40 of the same color are arranged for each unit of 8 pixels 12 in the first direction (horizontal direction) X and 4 pixels 12 in the second direction (vertical direction) Y. Also, in the third example, as shown in FIG 11B, a floating diffusion FD and a pixel circuit 22 are shared by each unit of 8×4=32 pixels 12 of the same color.

[0097] The pixel 12 and the pixel circuit 22 may have a circuit configuration other than the first to third examples described above.

[0098] In this way, in the first embodiment, since a plurality of wiring layers 71 each having a different layer are laminated in the intermediate layer 70 (interlayer insulating layer) between the first substrate 10 and the second substrate 20, it is easy to ensure the distance between the wiring layers 71, and interference between the plurality of wiring layers 71 can be suppressed to prevent problems such as an increase in resistance value. According to this embodiment, since the plurality of wiring layers 71 can be arranged so as to overlap one above the other in a plan view, the degree of freedom in the arrangement of the plurality of wiring layers 71 in the intermediate layer 70 is increased, and the layout design of pixels is facilitated.

[0099] Second embodiment As in the first embodiment, the photodetector element 1 of the second embodiment has two or more wiring layers 71 stacked on an intermediate layer 70 consisting of an insulating layer (interlayer insulating layer) 46 between the first substrate 10 and the second substrate 20.

[0100] In the photodetector 1 according to the second embodiment, for example, a first wiring layer 71a connected to the p-well layer 42, a second wiring layer 71b connected to the floating diffusion FD, and a third wiring layer 71c connected to the transfer gate TG of the transfer transistor TR are arranged in the intermediate layer 70. The first wiring layer 71a, the second wiring layer 71b, and the third wiring layer 71c are arranged in different layers of the intermediate layer 70.

[0101] In this way, by arranging the first wiring layer 71a, the second wiring layer 71b, and the third wiring layer 71c in different layers of the intermediate layer 70, the location of the third wiring layer 71c connected to the transfer gate TG of the transfer transistor TR can be determined regardless of the location of the first wiring layer 71a connected to the p-well layer 42.

[0102] This allows the distance between the contact on the second wiring layer 71b connected to the floating diffusion FD (hereinafter referred to as the first through contact 72a) and the contact on the third wiring layer 71c connected to the transfer gate TG (hereinafter referred to as the second through contact 72b) to be as large as possible, thereby suppressing capacitive coupling between the first through contact 72a and the second through contact 72b.

[0103] Fig. 12 is a cross-sectional view showing the locations of the first wiring layer 71a and the second wiring layer 71b in the photodetector element 1 according to the second embodiment, Fig. 13A is a planar layout diagram showing the distance between the first through contact 72a on the second wiring layer 71b and the second through contact 72b on the third wiring, and Fig. 13B is a planar layout diagram showing an empty region of the second substrate 20. The empty region is a region where no through contact 72 exists and where a pixel transistor can be formed.

[0104] 12, the first wiring layer 71a connected to the p-well layer 42 and the third wiring layer 71c connected to the transfer gate TG are disposed in different layers of the intermediate layer 70, so that the first wiring layer 71a and the third wiring layer 71c can be disposed so that at least a part of them overlap each other vertically when viewed in a plan view. Therefore, as shown in FIG. 12, the second through contact 72b extending from the third wiring layer 71c to the second substrate 20 can be disposed directly above the p-well layer 42. This allows the distance between the second through contact 72a extending from the first wiring layer 71a connected to the floating diffusion FD to the second substrate 20 and the above-mentioned second through contact 72b to be as large as possible.

[0105] The first through contact 72a and the second through contact 72b are connected to the pixel circuit 22 of the second substrate 20. As shown in Figures 13A and 13B, the first through contact 72a is disposed near both ends of the center line of the four pixels 12 to be shared, and the second through contact 72b is disposed in the center of the four pixels 12 to be shared. Therefore, in the second substrate 20, a region 74 where the first through contact 72a and the second through contact 72b are not present becomes wider, and this region 74 can be used as a formation region for pixel transistors, increasing the layout margin for pixel transistors.

[0106] FIG. 14 is a cross-sectional view showing the locations of the first wiring layer 71a, the second wiring layer 71b, and the third wiring layer 71c in a photodetector element 100 according to one comparative example, FIG. 15A is a planar layout diagram showing the distance between the first through contact 72a and the second through contact 72b in one comparative example, and FIG. 15B is a planar layout diagram showing the free space 74 of the second substrate 20 in one comparative example.

[0107] In the photodetector element 100 according to the comparative example, as shown in FIG. 14, all the wiring layers 71 formed in the intermediate layer 70 are arranged in the same layer, so that the distance between the first wiring layer 71a connected to the p-well layer 42 and the third wiring layer 71c connected to the transfer gate TG cannot be made very close. Therefore, the distance between the second through contact 72b extending from the third wiring layer 71c to the second substrate 20 and the first through contact 72a extending from the third wiring layer 71c connected to the floating diffusion FD to the second substrate 20 cannot be made large, and there is a risk of capacitive coupling occurring. In addition, as shown in FIG. 15A and FIG. 15B, the second through contact 72b is arranged inside the vicinity of the boundary of the pixel group including the four pixels 12 to be shared, so that the free area 74 available for forming the pixel transistors on the second substrate 20 is narrower than the area 74 of the present embodiment shown in FIG. 13B.

[0108] In this way, in the second embodiment, by arranging the third wiring layer 71c connected to the transfer gate TG directly above the first wiring layer 71a connected to the p-well layer 42, the distance between the second through contact 72b extending from the third wiring layer 71c to the second substrate 20 and the first through contact 72a extending from the second wiring layer 71b connected to the floating diffusion FD to the second substrate 20 can be increased, thereby suppressing capacitive coupling between the first through contact 72a and the second through contact 72b and expanding the area in which pixel transistors can be formed on the second substrate 20.

[0109] (Third embodiment) The photodetector element 1 according to the third embodiment is characterized in that two or more wiring layers 71 are laminated on an intermediate layer 70 (interlayer insulating layer) in the same manner as in the first and second embodiments.

[0110] A first wiring layer 71a is connected to the p-well layer 42 via a first contact 73a. The first wiring layer 71a can be connected to, for example, a ground node to set the p-well layer 42 to a ground potential. Usually, the p-well layer 42 of each pixel 12 is set to the same potential. Therefore, the photodetector element 1 according to the third embodiment is characterized in that, instead of connecting the first contact 73a to the p-well layer 42 of each pixel 12 individually, all the p-well layers 42 are set to the same potential (for example, ground potential) by connecting the first contact 73a to some of the p-well layers 42.

[0111] FIG. 16A is a planar layout diagram of the first substrate 10 of the photodetector 1 according to the third embodiment, and FIG. 16B is a planar layout diagram of the second substrate 20 of the photodetector 1 according to the third embodiment. As shown in FIG. 16A and FIG. 16B, a first through contact 72a and a second through contact 72b are provided between the first substrate 10 and the second substrate 20. The first through contact 72a is connected to the second wiring layer 71b, and the second wiring layer 71b is connected to the floating diffusion FD via the second contact 73b. The first through contact 72a is provided for each of the four pixels 12 to be shared. The second through contact 72b is connected to the third wiring layer 71c, and the third wiring layer 71c is connected to the transfer gate TG via the third contact 73c. ​​The second through contact 72b is provided for each of the pixels 12.

[0112] 16A and 16B, the p-well layer 42 of each pixel 12 is connected by the first substrate 10, and the first contact 73a and the first wiring layer 71a connected individually to each pixel 12 are omitted. This also makes the through contact 72 extending from the first wiring layer 71a corresponding to each pixel 12 to the second substrate 20 unnecessary. Therefore, the first through contact 72a and the second through contact 72b are arranged on the second substrate 20, but the through contact 72 for connecting to the p-well layer 42 is not arranged.

[0113] The p-well layers 42 of the pixels 12 are connected to the first substrate 10, and the p-well layers 42 of the pixels 12 can be set to any potential by providing contacts (hereinafter, third through contacts) 72c extending from any one or more locations of the multiple first wirings connected to the p-well layers 42 to the second substrate 20. The third through contacts 72c may be provided at any one or more locations within the pixel region, or may be disposed outside the pixel region.

[0114] In this way, since there is no need to provide an area for arranging the through contact 72 for connecting to the p-well layer 42 within the pixel region on the second substrate 20, the second through contact 72b can be arranged on the boundary side of the pixel region, thereby expanding the free space on the second substrate 20.

[0115] 17A is a planar layout diagram of the first substrate 10 according to a comparative example, and FIG. 17B is a planar layout diagram of the second substrate 20 according to the comparative example. In the comparative example, a contact (third through contact 72c) is provided for each pixel 12, extending from the first wiring layer 71a connected to the p-well layer 42 to the second substrate 20. These third through contacts 72c are arranged at the corners of each pixel 12, as shown in FIG. 17B. Therefore, the second through contact 72b has to be arranged inside the third through contact 72c, and on the second substrate 20, the region surrounded by the first through contact 72a and the second through contact 72b becomes a vacant region in which a pixel transistor can be formed, and the vacant region becomes narrow.

[0116] In this way, in the third embodiment, the p-well layers 42 of the pixels 12 are connected to the first substrate 10, and the contacts (third through contacts) 72c extending from the first wiring layers 71a connected to the p-well layers 42 to the second substrate 20 are not provided for each pixel 12. This makes it possible to reduce the number of contacts 72 connected to the second substrate 20, and ensures a sufficient area on the second substrate 20 for forming pixel transistors.

[0117] (Fourth embodiment) The photodetector 1 according to the fourth embodiment suppresses capacitive coupling between the wiring layer 71 disposed on the intermediate layer 70 and the gate of the pixel transistor disposed on the second substrate 20.

[0118] In the photodetector element 1 according to the fourth embodiment, similarly to the first to third embodiments, two or more wiring layers 71 are laminated on an intermediate layer 70. More specifically, in the intermediate layer 70, a first wiring layer 71a connected to the p-well layer 42, a second wiring layer 71b connected to the floating diffusion FD, and a third wiring layer 71c connected to the transfer gate TG are arranged.

[0119] When a pixel transistor having a FIN gate made of SOI (Silicon On Insulator) is disposed on the second substrate 20, a p-well layer is not disposed on the second substrate 20. The second wiring layer 71b and the third wiring layer 71c of the intermediate layer 70 contain a large amount of n-type impurity ions. Therefore, there is a risk of capacitive coupling occurring between the FIN gate of the second substrate 20 and the second wiring layer 71b or the third wiring layer 71c of the intermediate layer 70.

[0120] FIG. 18 is a cross-sectional view of the photodetector 1 according to the fourth embodiment. In the photodetector 1 according to the fourth embodiment, the first wiring layer 71a is disposed between the second wiring layer 71b and the third wiring layer 71c of the intermediate layer 70 and the FIN gate 25 of the second substrate 20. That is, the second wiring layer 71b and the third wiring layer 71c in the intermediate layer 70 are disposed on the side closer to the first substrate 10, and the first wiring layer 71a in the intermediate layer 70 is disposed on the side closer to the second substrate 20. The second wiring layer 71b and the third wiring layer 71c contain a large amount of n-type impurity ions, whereas the first wiring layer 71a contains a large amount of p-type impurity ions. According to this embodiment, the first wiring layer 71a is disposed between the second wiring layer 71b and the third wiring layer 71c and the FIN gate 25, and the capacitive coupling between the second wiring layer 71b and the third wiring layer 71c and the FIN gate 25 can be suppressed.

[0121] 19 is a cross-sectional view of a photodetector element 100 according to a comparative example. In the photodetector element 100 according to the comparative example, all of the wiring layers 71 arranged in the intermediate layer 70 are arranged in the same layer. For this reason, the first wiring layer 71a cannot be arranged between the second wiring layer 71b and the third wiring layer 71c and the FIN gate 25, and there is a risk of capacitive coupling occurring between the second wiring layer 71b and the third wiring layer 71c and the FIN gate 25.

[0122] In this way, in the fourth embodiment, the first wiring layer 71a containing a large amount of p-type impurity ions is arranged between the second wiring layer 71b and the third wiring layer 71c containing a large amount of n-type impurity ions arranged in the intermediate layer 70 and the FIN gate 25 arranged on the second substrate 20, thereby suppressing capacitive coupling between the second wiring layer 71b and the third wiring layer 71c and the FIN gate 25.

[0123] Fifth embodiment The fifth embodiment relates to a manufacturing process for the photodetector 1 according to the first to fourth embodiments described above.

[0124] 20A to 20O are cross-sectional views showing the manufacturing process of the photo-detector element 1 according to the fifth embodiment, and show the manufacturing process after the transfer transistor TR is formed.

[0125] Fig. 20A is a cross-sectional view of a process of forming a transfer transistor TR on the first substrate 10. A SiO2 layer 75 is formed on the upper surface of the first substrate 10 by a high density plasma (HDP) method, and the surface of the SiO2 layer 75 is planarized by chemical vapor deposition (CMP) (Fig. 20B).

[0126] Next, an organic film 76 is formed on the SiO2 layer 75, a resist layer 77 is disposed thereon, and the resist layer 77 is patterned by photolithography (FIG. 20C). The resist layer 77 is patterned to match the position of the contact 73.

[0127] Next, the organic film 76 is partially removed by dry etching to form a trench 78, and after removing the resist layer 77 and the organic film 76, the inside of the trench 78 is filled with polysilicon to form a contact 73, and a polysilicon layer 79 is also formed on the upper surface of the SiO2 layer 75, and an SiO2 layer 80 is formed thereon using TEOS (Tetra Ethoxy Silane) (Figure 20D).

[0128] Next, a mask pattern is placed on the top surface of the SiO2 layer 80, and impurity ions are implanted into the contacts 73 (FIG. 20E). At this stage, no heat treatment is performed to activate the impurity ions.

[0129] Next, a SiN layer 81, an NSG (Non-doped Silicon Glass) layer 82, an organic layer 83, and a SiO2 layer 84 are formed in this order, and a resist layer 85 is disposed thereon and patterned (FIG. 20F).

[0130] Next, a wiring layer 71 (first wiring layer 71a) made of a first layer of polysilicon in the intermediate layer 70 is formed by photolithography and dry etching (FIG. 20G). Although only one wiring layer 71 is shown in FIG. 20G, a plurality of wiring layers 71 may be formed in the first layer of the intermediate layer 70, each of which is spaced apart from one another.

[0131] Next, a SiO2 layer 86 is formed on the entire upper surface of the first substrate 10 by the HDP method, and the surface of the SiO2 layer 86 is planarized by CMP (FIG. 20H).

[0132] Next, an organic layer 87 and an SiO2 layer 88 are formed on the upper surface of the SiO2 layer 86, and a resist layer 89 is disposed thereon and patterned (FIG. 20I). The resist layer 89 is patterned to match the position of a contact connected to the first wiring layer 71a.

[0133] Next, the organic layer 87 and the SiO2 layer 88 are partially removed by dry etching to form a trench, and after removing the resist layer 89 and the organic layer 87, the inside of the trench is filled with polysilicon to form a contact 73, and a polysilicon layer 91 is also formed on the upper surface of the SiO2 layer 86, and an SiO2 layer 92 is formed thereon using TEOS (Tetra Ethoxy Silane) (FIG. 20J).

[0134] Next, a mask pattern is placed on the top surface of the SiO2 layer 92, and impurity ions are implanted into the contacts 73 (FIG. 20K).

[0135] Next, a heat treatment is performed to activate the region where the impurity ions are implanted (Fig. 20L). In this way, instead of performing a heat treatment every time an impurity ion is implanted, by performing the heat treatment after the second step of implanting the impurity ions, the number of heat treatments can be reduced, and damage to the substrate can be reduced.

[0136] Next, an NSG layer 93, an organic layer 94, and an SiO2 layer 95 are formed in this order on the SiO2 layer 92, and a resist layer 96 is disposed on the SiO2 layer 95 and patterned (FIG. 20M). The resist layer 96 is patterned to match the position of the second wiring layer 71 (the second wiring layer 71b and the third wiring layer 71c) in the intermediate layer 70.

[0137] Next, the second wiring layer 71 (the second wiring layer 71b and the third wiring layer 71c) in the intermediate layer 70 is formed by lithography and dry etching (FIG. 20N). The second wiring layer 71b and the third wiring layer 71c are polysilicon layers into which impurity ions are implanted.

[0138] Next, the side and top surfaces of the second wiring layer 71 in the intermediate layer 70 are covered with a SiO2 layer 97 by HDP, and the top surface of the SiO2 layer 97 is protected with a SiN layer 98 (FIG. 20O).

[0139] When the impurity ions are implanted in the steps of Fig. 20E and Fig. 20K, multiple types of impurity ions may be implanted. For example, as described in the eighth embodiment to be described later, arsenic (As) and phosphorus (P) ions may be implanted into polysilicon. Also, the impurity concentration may be different for each of the wiring layers 71 (71a, 71b, 71c).

[0140] Thus, in the fifth embodiment, when forming the intermediate layer 70 after forming the transfer transistor TR on the first substrate 10, a heat treatment process is performed after the impurity ion implantation process for forming the first wiring layer 71 (71a) and the impurity ion implantation process for forming the second wiring layer 71 (71b, 71c) are completed, so that the impurity ions contained in the first wiring layer 71 (71a) and the contact 73 (73a) and the second wiring layer 71 (71b, 71c) and the contact 73 (73b, 73c) can be activated together, simplifying the manufacturing process.

[0141] Sixth embodiment The photodetector 1 according to the sixth embodiment is characterized in that a charge retention section is formed in the intermediate layer 70, the charge retention section being provided separately from the floating diffusion FD.

[0142] Fig. 21A is a circuit diagram of a pixel circuit 22 included in a photodetector element 1 according to the sixth embodiment. As shown in Fig. 21A, a pixel 12 includes a photodiode PD and a transfer transistor TR, and a pixel circuit 22 includes a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, a conversion efficiency switching transistor FDG, a floating diffusion FD, and a charge holding unit 15. One end of the charge holding unit 15 is connected to the reset transistor RST and the conversion efficiency switching transistor FDG, and the other end of the charge holding unit 15 is connected to, for example, a ground node.

[0143] 21B is a diagram showing the correspondence relationship between the on / off state of the conversion efficiency switching transistor FDG and the conversion efficiency. When the conversion efficiency switching transistor FDG is off, the conversion efficiency is set to a high state (HCG), and when the conversion efficiency switching transistor FDG is on, the conversion efficiency is set to a low state (LCG). The charge holding unit 15 holds the charge transferred from the photodiode PD when the conversion efficiency switching transistor FDG is on.

[0144] Fig. 22A is a planar layout diagram of a photodetector 1 according to a sixth embodiment. Fig. 22B is a cross-sectional view taken along line AB in Fig. 22A in the substrate depth direction.

[0145] As shown in FIG. 22B, two wiring layers 71 in different layers are arranged in the intermediate layer 70. Hereinafter, these two wiring layers 71 are referred to as a first wiring layer 71a and a second wiring layer 71b. The first wiring layer 71a is connected to a p-well layer 42 of the first substrate 10. The p-well layer 42 is set to, for example, a ground potential. A through contact (third contact) 72c is connected to the second wiring layer 71b. The through contact 72c is connected to the source of the conversion efficiency switching transistor FDG via the wiring layer 20a and the contact 20b of the second substrate 20.

[0146] The first wiring layer 71a and the second wiring layer 71b are arranged parallel to each other so as to overlap vertically in a plan view, and function as both electrodes of the charge holding section (charge accumulation section) 15. That is, the charge holding section 15 is composed of the first wiring layer 71a, the second wiring layer 71b, and the insulating layer 46 between the first wiring layer 71a and the second wiring layer 71b.

[0147] In the intermediate layer 70, one or more wiring layers 71 other than the first wiring layer 71a and the second wiring layer 71b constituting the charge retention unit 15 are arranged. For example, a wiring layer connected to the floating diffusion FD described in the first to fifth embodiments and a wiring layer connected to the transfer gate TG are provided.

[0148] FIG. 23A is a planar layout diagram of a photodetector 100 according to a comparative example, and FIG. 23B is a cross-sectional view of the substrate depth direction along line AB in FIG. 23A. As shown in FIG. 23B, in the photodetector 100 according to the comparative example, the wiring layer 71 arranged in the intermediate layer 70 is arranged in the same layer. Therefore, the charge holding portion 15 like the photodetector 1 according to the sixth embodiment cannot be formed in the intermediate layer 70. In the photodetector 100 according to the comparative example, for example, the charge holding portion 15 is formed in the second substrate 20 using a metal layer. Therefore, an area for forming the charge holding portion 15 must be secured in the second substrate 20, and the formation area of ​​the pixel transistor is reduced, which makes it difficult to design the layout of the pixel circuit 22.

[0149] Fig. 24A is a planar layout diagram of a photodetector 1 according to a modification of the sixth embodiment, and Fig. 24B is a cross-sectional diagram in the substrate depth direction along line AB in Fig. 24A. In the photodetector 1 according to the modification, a wiring layer 71b for the charge holding portion 15 is formed in parallel to a wiring layer 71 (third wiring layer 71c) connected to the transfer gate TG. The wiring layer 71b for the charge holding portion 15 is arranged, for example, in a comb-like shape.

[0150] 25A and 25B are planar layout views of comb-shaped wiring layer 71b, in which Fig. 25A shows an example in which each tooth of the comb extends in second direction Y, and Fig. 25B shows an example in which each tooth of the comb extends in first direction X. In Figs. 25A and 25B, the comb-shaped wiring layers 71b for charge retention units 15 are arranged to be combined with each other.

[0151] Fig. 26 is a planar layout diagram of one pixel circuit 22 of a photodetector element 1 according to the sixth embodiment. As shown in Fig. 26, two wiring layers 71a and 71b constituting the charge holding unit 15 overlap each other in a planar view. In addition to these wiring layers 71a and 71b, a wiring layer (FD wiring layer) 71d that connects the source of the conversion efficiency switching transistor FDG and the gate of the amplification transistor AMP is provided in the intermediate layer 70.

[0152] The circuit configuration of the pixel circuit 22 of the photodetector element 1 according to the sixth embodiment is not limited to that shown in FIG. 21A, and various circuit configurations are possible.

[0153] Fig. 27A is a circuit diagram of a pixel circuit 22 of a photodetector element 1 according to a first modified example of the sixth embodiment. The pixel circuit 22 in Fig. 27A differs from the pixel circuit 22 in Fig. 21A in that a reset transistor RST and a conversion efficiency switching transistor FDG are connected in parallel.

[0154] Fig. 27B is a planar layout diagram of the pixel circuit 22 in Fig. 27A. As can be seen by comparing Fig. 27B with Fig. 26, the location of the FD wiring layer 71d is different. In addition, the location of the through contact 72 connecting the second wiring layer 71b and the second substrate 20 is also different.

[0155] FIG. 28A is a circuit diagram of a pixel circuit 22 of a photodetector element 1 according to a second modification of the sixth embodiment. The pixel circuit 22 of FIG. 28A has two conversion efficiency switching transistors FDG (hereinafter, first conversion efficiency switching transistor FDG1 and second conversion efficiency switching transistor FDG2). More specifically, a reset transistor RST, a second conversion efficiency switching transistor FDG2, and a first conversion efficiency switching transistor FDG1 are connected in series between a power supply voltage node and a floating diffusion FD. A first charge holding unit 15a is connected between a connection node between the reset transistor RST and the second conversion efficiency switching transistor FDG2 and a ground node. A second charge holding unit 15b is connected between a connection node between the first conversion efficiency switching transistor FDG1 and the second conversion efficiency switching transistor FDG2 and a ground node. The first charge holding unit 15a is formed by two wiring layers 71 (71a, 71b) in different layers of the intermediate layer 70. The second charge retaining portion 15b is formed on the second substrate 20 in a metal-insulator-metal (MIM) structure using, for example, a metal material.

[0156] 28B is a diagram showing a correspondence relationship between the on / off state of the conversion efficiency switching transistor FDG of the pixel circuit 22 according to the second modification and the conversion efficiency. When the first conversion efficiency switching transistor FDG1 and the second conversion efficiency switching transistor FDG2 are both off, the conversion efficiency is set to maximum (HCG). When the first conversion efficiency switching transistor FDG1 is on and the second conversion efficiency switching transistor FDG2 is off, the conversion efficiency is set to medium (MCG). When the first conversion efficiency switching transistor FDG1 and the second conversion efficiency switching transistor FDG2 are both on, the conversion efficiency is set to minimum (LCG).

[0157] Fig. 28C is a planar layout diagram of a pixel circuit 22 according to a second modified example. As shown in Fig. 28C, a through contact 72 extending to the second substrate 20 is connected to a connection node between the first conversion efficiency switching transistor FDG1 and the second conversion efficiency switching transistor FDG2, and this through contact 72 is connected to a metal layer on the second substrate 20. The second charge retention unit 15b is formed using this metal layer.

[0158] 29A is a circuit diagram of a pixel circuit 22 of a photodetector element 1 according to a third modified example of the sixth embodiment. In the pixel circuit 22 according to the third modified example, as shown in FIG. 29A, a first conversion efficiency switching transistor FDG1, a first charge holding unit 15a, a second conversion efficiency switching transistor FDG2, and a second charge holding unit 15b are connected in series between a floating diffusion FD connected to the source of a reset transistor RST and a ground node. The first charge holding unit 15a is disposed on the second substrate 20 using, for example, a metal material. The second charge holding unit 15b is formed using, for example, two wiring layers 71 disposed in different layers of an intermediate layer 70.

[0159] Fig. 29B is a planar layout diagram of a pixel circuit 22 according to a third modified example. The location of the wiring layer 71 (FD wiring layer 71d) that connects the floating diffusion FD and the amplification transistor AMP is different from that in Fig. 28C.

[0160] FIG. 30A is a circuit diagram of a pixel circuit 22 of a photodetector element 1 according to a fourth modified example of the sixth embodiment. The pixel circuit 22 according to the fourth modified example has a first reset transistor RST1, a second reset transistor RST2, a first conversion efficiency switching transistor FDG1, and a second conversion efficiency switching transistor FDG2. The first reset transistor RST1 and the first conversion efficiency switching transistor FDG1 are connected in series between a power supply voltage node and a floating diffusion FD. The second reset transistor RST2 and the second conversion efficiency switching transistor FDG2 are connected in series between a power supply voltage node and the floating diffusion FD. A first charge holding unit 15a is connected between a connection node between the first reset transistor RST1 and the first conversion efficiency switching transistor FDG1 and a ground node. A second charge holding unit 15b is connected between a connection node between the second reset transistor RST2 and the second conversion efficiency switching transistor FDG2 and a ground node. The first charge holding unit 15a is disposed on the second substrate 20 using, for example, a metal material. The second charge retaining portion 15b is formed using two wiring layers 71 arranged in different layers of the intermediate layer 70, for example.

[0161] 30B is a diagram showing a correspondence relationship between the on / off state of the conversion efficiency switching transistor FDG of the pixel circuit 22 according to the fourth modification and the conversion efficiency. When the first conversion efficiency switching transistor FDG1 and the second conversion efficiency switching transistor FDG2 are both off, the conversion efficiency is set to the maximum (HCG). When the first conversion efficiency switching transistor FDG1 is on and the second conversion efficiency switching transistor FDG2 is off, the conversion efficiency is set to the upper middle (MHCG). When the first conversion efficiency switching transistor FDG1 is off and the second conversion efficiency switching transistor FDG2 is on, the conversion efficiency is set to the lower middle (MLCG). When the first conversion efficiency switching transistor FDG1 and the second conversion efficiency switching transistor FDG2 are both on, the conversion efficiency is set to the minimum (LCG).

[0162] 30C is a planar layout diagram of a pixel circuit 22 according to a fourth modified example. A contact connected to a connection node between the first reset transistor RST1 and the first conversion efficiency switching transistor FDG1 is connected to the second substrate 20 or a wiring layer 71 of the intermediate layer 70. This wiring layer 71 is made of, for example, a metal material. A through contact 72 connected to a connection node between the second reset transistor RST2 and the second conversion efficiency switching transistor FDG2 is connected to the wiring layer 71 of the intermediate layer 70. The second charge retention unit 15b is formed in two different wiring layers 71 (71a, 71b) of the intermediate layer 70.

[0163] Fig. 31A is a circuit diagram of a pixel circuit 22 of a photodetector element 1 according to a fifth modified example of the sixth embodiment. The pixel circuit 22 according to the fifth modified example has a first conversion efficiency switching transistor FDG1 and a first charge holding unit 15a connected in series between a floating diffusion FD connected to the source of the reset transistor RST and a ground node, and a second conversion efficiency switching transistor FDG2 and a second charge holding unit 15b connected in series between the floating diffusion FD and the ground node. The pixel circuit 22 according to the fifth modified example can switch the conversion efficiency in four stages, similar to Fig. 30B.

[0164] 31B is a planar layout diagram of a pixel circuit 22 according to the fifth modification. In the pixel 12 according to the fifth modification, a contact connected to the source of the first conversion efficiency switching transistor FDG1 is connected to the second substrate 20 or a wiring layer 71 of the intermediate layer 70. This wiring layer 71 is made of a metal material, and forms a first charge retention unit 15a. A through contact 72 connected to the source of the second conversion efficiency switching transistor FDG2 is connected to the wiring layer 71 of the intermediate layer 70. The two wiring layers 71 arranged in different layers of the intermediate layer 70 form a second charge retention unit 15b.

[0165] 32 and 33 are cross-sectional views of the pixel circuit 22 of the photodetector element 1 according to the sixth modification. The pixel circuit 22 according to the sixth modification has the same circuit configuration as the pixel circuit 22 according to the fourth or fifth modification. FIG. 32 shows an example in which the first charge retention unit 15a is disposed on the second substrate 20. A contact extending upward from the source of the first conversion efficiency switching transistor FDG1 is connected to a metal wiring on the second substrate 20. The first charge retention unit 15a having, for example, an MIM structure is formed using this metal wiring. In FIG. 32, the second charge retention unit 15b is formed by two wiring layers 71a and 71b of the intermediate layer 70.

[0166] The cross-sectional structure of the pixel circuit 22 according to the fourth or fifth modification is not limited to that shown in FIG. 32. In FIG. 33, the cross-sectional structure of the second charge retention unit 15b formed in the intermediate layer 70 is different from that in FIG. 32. In FIG. 33, three wiring layers 71a, 71b, and 71c, each of which is a different layer, are arranged in the intermediate layer 70, and the top two wiring layers 71b and 71c are connected to each other by contacts. By forming the second charge retention unit 15b having a three-layer structure as shown in FIG. 33, the amount of charge that can be stored in the second charge retention unit 15b can be increased.

[0167] 34 is a diagram summarizing the features of pixel circuits 22 according to the first to sixth modified examples of the sixth embodiment described above. The features of pixel circuits 22 according to the first to sixth modified examples can be expressed by the number of wiring layers 71 in the intermediate layer 70, the connection form between the conversion efficiency switching transistor FDG and the reset transistor RST, the number of conversion efficiency switching transistors FDG, whether or not the charge holding section 15 is disposed on the second substrate 20, and the number of conversion switching stages.

[0168] Pattern 1 in Fig. 34 corresponds to Fig. 21A, pattern 2 corresponds to Fig. 27A, pattern 3 corresponds to Fig. 28A, pattern 4 corresponds to Fig. 30A, pattern 5 corresponds to Fig. 29A, and pattern 6 corresponds to Fig. 31A. Pattern 7 is a seventh modification different from the first to sixth modifications, and describes an example in which N (N is any integer equal to or greater than 2) wiring layers 71 are arranged in different layers in the intermediate layer 70. In the photodetector element 1 according to the seventh modification, the conversion efficiency transistor and the reset transistor RST can be connected in series or in parallel, the total number of conversion efficiency transistors is any number equal to or greater than 1, the charge holding section 15 can be arranged on the second substrate 20, and the number of conversion efficiency switches is also arbitrary.

[0169] In this way, in the sixth embodiment, the charge holding section 15 for switching the conversion efficiency can be formed by using, as electrodes, two wiring layers 71 arranged in different layers of the intermediate layer 70. The two wiring layers 71 constituting the charge holding section 15 can be provided separately from the first to third wiring layers 71a, 71b, 71c in the first to fifth embodiments described above. Thus, the charge holding section 15 according to the sixth embodiment can be provided in the photodetector element 1 according to the first to fifth embodiments described above.

[0170] Seventh embodiment FIG. 35 is a cross-sectional view for explaining a problem that occurs when a second substrate 20 on which pixel transistors are arranged is laminated on a first substrate 10 on which photoelectric conversion elements (photodiodes) PD are arranged.

[0171] When the second substrate 20, on which pixel transistors are arranged, is laminated on the first substrate 10, on which photodiodes PD are arranged, there is a risk that light emitted by the second substrate 20 may enter the photodiode PD of the first substrate 10 due to a defect in the pixel transistors or the like (arrow line y1 in FIG. 35). In addition, there is a risk that light that passes through the photodiode PD may be reflected by the second substrate 20 and enter the photodiode PD of the adjacent pixel 12 of the first substrate 10, causing color mixing (arrow line y2 in FIG. 35). The photodetector 1 according to the seventh embodiment is characterized in that it prevents the above-mentioned defects.

[0172] 36 is a cross-sectional view of a photodetector 1 according to the seventh embodiment in a substrate depth direction. As with the first to sixth embodiments, the photodetector 1 according to the seventh embodiment is characterized in that it includes a plurality of different wiring layers 71 (71a and 71b) in an intermediate layer 70 (interlayer insulating layer) between a first substrate 10 and a second substrate 20. The plurality of wiring layers 71 are formed of, for example, polysilicon.

[0173] 36 shows an example in which two wiring layers 71 (a first wiring layer 71a and a second wiring layer 71b) are arranged in the intermediate layer 70. The first wiring layer 71a and the second wiring layer 71b are arranged in different layers of the intermediate layer 70. The first wiring layer 71a is arranged closer to the first substrate 10 than the second wiring layer 71b. The second wiring layer 71b is arranged closer to the second substrate 20 than the first wiring layer 71a.

[0174] The first wiring layer 71a is connected to, for example, a floating diffusion FD of the first substrate 10 via a contact 73a. Note that a plurality of wiring layers 71 can be arranged in the same layer as the first wiring layer 71a. More specifically, the plurality of wiring layers 71 include a wiring layer 71 connected to a transfer gate TG, a wiring layer 71 connected to a p-well layer 42, and the like.

[0175] A first through contact 72a extending to the second substrate 20 is connected to the first wiring layer 71a. The first through contact 72a is connected to a wiring layer 16 of the second substrate 20. This wiring layer 16 is connected to the pixel transistor 18 via another contact 17. In this manner, the first wiring layer 71a is electrically connected to the pixel transistor 18 of the second substrate 20.

[0176] The second wiring layer (light shielding layer) 71b is an optical shield layer. The second wiring layer 71b may be a petapattern covering most of the first substrate 10, a mesh pattern, a slit pattern, or a pattern of other shapes. When the second wiring layer 71b is a solid pattern, an opening 71h is provided around the first through contact 72a extending from the first wiring layer 71a to the second substrate 20. The second wiring layer 71b is connected to the second contact 72b extending to the second substrate 20. The second wiring layer 71b is set to a predetermined potential (for example, ground potential) via the second contact 72b. The second wiring layer 71b functioning as an optical shield layer may be larger in area than a wiring layer (for example, the first wiring layer 71a) arranged in a layer other than the second wiring layer 71b.

[0177] By providing the second wiring layer 71b that functions as an optical shield layer, the light that has passed through the photodiode PD of the first substrate 10 can be blocked by the second wiring layer 71b, and the light that has passed through the photodiode PD will not enter the second substrate 20. Even if the pixel transistor 18 of the second substrate 20 emits light due to some malfunction, the light can be blocked by the second wiring layer 71b, and the light from the second substrate 20 will not enter the photodiode PD.

[0178] The second wiring layer 71b functioning as an optical shield layer is provided separately from the multiple wiring layers 71 arranged in the intermediate layer 70 described in the first to sixth embodiments. Therefore, the optical shield layer according to the seventh embodiment can be provided in the photodetector 1 according to the first to sixth embodiments.

[0179] There may be various variations in the number of layers and shape of the optical shield layer (second wiring layer) 71b disposed on the intermediate layer 70. Below, the number of layers and shapes of representative optical shield layers (second wiring layers) 71b will be described in order, but the number of layers and shapes of the optical shield layers are not limited to those shown below.

[0180] Fig. 37 is a diagram showing a photodetector 1 according to a first modified example of the seventh embodiment. Fig. 37A is a plan view of an optical shield layer (second wiring layer) 71b, Fig. 37B is a cross-sectional view taken along line AB in Fig. 37A in the substrate depth direction, Fig. 37C is a cross-sectional view taken along line CD in Fig. 37A in the substrate depth direction, and Fig. 37D is a plan view of the optical shield layer and first wiring layer 71a combined.

[0181] FIG. 37 shows a cross-sectional structure in the case where one floating diffusion FD and pixel transistor 18 are shared by a plurality of pixels 12 (for example, four pixels 12).

[0182] In the intermediate layer 70, for example, a second wiring layer 71b functioning as an optical shield layer is laminated on a first wiring layer 71a connected to the floating diffusion FD. As shown in Fig. 37A, the second wiring layer 71b is a solid pattern, and an opening 71h is provided in a part of the second wiring layer 71b. A first contact 72a extending from the first wiring layer 71a to the second substrate 20 is disposed in the opening 71h.

[0183] A second contact 72b extending to the second substrate 20 is connected to the second wiring layer 71b. The second wiring layer 71b is set to a predetermined potential (for example, ground potential) via the second contact 72b. If a second contact 72b is provided for each second wiring layer 71b, the number of second contacts 72b increases. Therefore, as described below, the number of second contacts 72b may be reduced by conducting a plurality of second wiring layers 71b in the intermediate layer 70 and providing one or a plurality of second contacts 72b at any location.

[0184] 37D, the first wiring layer 71a is disposed directly below the opening 71h of the second wiring layer 71b. The first wiring layer 71a is connected to, for example, a floating diffusion FD. The first wiring layer 71a may be connected to the transfer gate TG or the p-well layer 42.

[0185] By disposing the first wiring layer 71a directly under the second wiring layer 71b, for example, even if light from the second substrate 20 passes through the opening 71h of the second wiring layer 71b, it can be blocked by the first wiring layer 71a. Also, light that passes through the photodiode PD of the first substrate 10 is blocked by the first wiring layer 71a and cannot pass through the opening 71h of the second wiring layer 71b.

[0186] In this manner, by disposing the first wiring layer 71a directly under the opening 71h of the second wiring layer 71b, the light blocking effect can be improved.

[0187] The area of ​​the first wiring layer 71a and the area of ​​the second wiring layer 71b do not necessarily have to be the same. For example, the first wiring layer 71a may be divided into a plurality of wiring layers 71.

[0188] Fig. 38 is a diagram showing a photodetector 1 according to a second modified example of the seventh embodiment. Fig. 38A is a plan view of the optical shield layer (second wiring layer 71b), Fig. 38B is a cross-sectional view in the substrate depth direction along line AB in Fig. 38A, Fig. 38C is a cross-sectional view in the substrate depth direction along line CD in Fig. 38A, and Fig. 38D is an external view of a portion of chip 21 of photodetector 1.

[0189] In the photodetector 1 according to the second modification, instead of connecting the second contact 72b to each second wiring layer 71b functioning as an optical shield layer, a plurality of contacts 21c are provided at a predetermined interval on the periphery of the chip 21 of the photodetector 1, and these contacts 21c are connected to the plurality of second wiring layers 71b and set to a predetermined potential (for example, ground potential). It is desirable that the plurality of contacts 21c are arranged at as equal intervals as possible on the periphery of the chip 21, but the number of the plurality of contacts 21c does not need to be the same as the number of the plurality of second wiring layers 71b. Typically, the number of contacts 21c provided is smaller than the number of the plurality of second wiring layers 71b. This allows the number of contacts 21c to be reduced.

[0190] In the photodetector 1 of the second modified example, since there is no need to provide a second contact 72b for each second wiring layer 71b, the number of second contacts 72b arranged on the second substrate 20 can be reduced, and the free space on the second substrate 20 can be increased.

[0191] In the first and second modified examples, the second wiring layer 71b is a solid pattern. If the second wiring layer 71b is a solid pattern, a capacitance is formed between the first wiring layer 71a and the second wiring layer 71b, which may cause problems such as a decrease in photoelectric conversion efficiency.

[0192] Fig. 39 is a diagram showing a photodetector 1 according to a third modified example of the seventh embodiment. Fig. 39A is a plan view of the optical shield layer (second wiring layer 71b), Fig. 39B is a cross-sectional view in the substrate depth direction along line AB in Fig. 39A, and Fig. 39C is a cross-sectional view in the substrate depth direction along line CD in Fig. 39A.

[0193] In the intermediate layer 70 in the photodetector 1 according to the third modification, for example, a second wiring layer 71b functioning as an optical shield layer is laminated on a first wiring layer 71a connected to a floating diffusion FD. The second wiring layer 71b has a mesh pattern. In a part of the mesh pattern, an opening 71h is provided through which a first contact 72a extending from the first wiring layer 71a to the second substrate 20 passes. The size of the opening 71h is larger than the hole of the mesh pattern. By forming the second wiring layer 71b in a mesh pattern, the capacitance between the first wiring layer 71a and the second wiring layer 71b can be made smaller than when the second wiring layer 71b is formed into a solid pattern, and a decrease in photoelectric conversion efficiency can be suppressed.

[0194] Fig. 40 is a diagram showing a photodetector 1 according to a fourth modified example of the seventh embodiment. Fig. 40A is a plan view of the optical shield layer (second wiring layer 71b), Fig. 40B is a cross-sectional view in the substrate depth direction along line AB in Fig. 40A, Fig. 40C is a cross-sectional view in the substrate depth direction along line CD in Fig. 40A, and Fig. 40D is an external view of a portion of chip 21 of photodetector 1.

[0195] The photodetector 1 according to the fourth modification has a second wiring layer 71b in a mesh pattern. Similarly to the photodetector 1 according to the second modification, instead of connecting a second contact 72b to each second wiring layer 71b, a plurality of contacts 21c are provided at a predetermined interval on the periphery of the chip 21 of the photodetector 1 to set the plurality of second wiring layers 71b to a predetermined potential (for example, ground potential).

[0196] In the photodetector 1 of the fourth modified example, since there is no need to provide a second contact 72b for each second wiring layer 71b, the number of second contacts 72b arranged on the second substrate 20 can be reduced, and the free space on the second substrate 20 can be increased.

[0197] Fig. 41 is a diagram showing a photodetector 1 according to a fifth modified example of the seventh embodiment. Fig. 41A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 41B is a cross-sectional view in the substrate depth direction along line AB in Fig. 41A, and Fig. 41C is a cross-sectional view in the substrate depth direction along line CD in Fig. 41A.

[0198] In the intermediate layer 70 in the photodetector 1 according to the fifth modification, for example, a second wiring layer 71b functioning as an optical shield layer is laminated on a first wiring layer 71a connected to a floating diffusion FD. The second wiring layer 71b has a slit-like pattern shape extending in one direction. In a part of the slit-like pattern, an opening 71h is provided through which a first contact 72a extending from the first wiring layer 71a to the second substrate 20 passes. By forming the second wiring layer 71b in a slit-like pattern, the capacitance can be reduced and the decrease in photoelectric conversion efficiency can be further suppressed compared to forming the second wiring layer 71b in a solid pattern or a mesh pattern.

[0199] Fig. 42 is a diagram showing a photodetector 1 according to a sixth modified example of the seventh embodiment. Fig. 42A is a plan view of the optical shield layer (second wiring layer 71b), Fig. 42B is a cross-sectional view in the substrate depth direction along line AB in Fig. 42A, Fig. 42C is a cross-sectional view in the substrate depth direction along line CD in Fig. 42A, and Fig. 42D is an external view of a portion of chip 21 of photodetector 1.

[0200] The photodetector 1 according to the sixth modification has a second wiring layer 71b in a slit-like pattern. Similarly to the photodetector 1 according to the second modification, instead of connecting a second contact 72b to each second wiring layer 71b, a plurality of contacts 21c are provided at a predetermined interval on the periphery of the chip 21 of the photodetector 1 to set the plurality of second wiring layers 71b to a predetermined potential (for example, ground potential).

[0201] In the photodetector element 1 of the sixth modified example, since there is no need to provide a second contact 72b for each second wiring layer 71b, the number of second contacts 72b arranged on the second substrate 20 can be reduced, and the free space on the second substrate 20 can be increased.

[0202] Fig. 43 is a diagram showing a photodetector 1 according to a seventh modified example of the seventh embodiment. Fig. 43A is a plan view of the optical shield layer (second wiring layer 71b), Fig. 43B is a cross-sectional view in the substrate depth direction along line AB in Fig. 43A, and Fig. 43C is a cross-sectional view in the substrate depth direction along line CD in Fig. 43A.

[0203] In the intermediate layer 70 of the photodetector 1 according to the seventh modification, a second wiring layer 71b functioning as an optical shield layer is laminated on a first wiring layer 71a connected to the floating diffusion FD. The second wiring layer 71b has a slit-like pattern shape extending in a direction different by 90 degrees from the second wiring layer 71b according to the fifth modification. In a part of the slit-like pattern, an opening 71h is provided through which a first contact 72a extending from the first wiring layer 71a to the second substrate 20 passes. By forming the second wiring layer 71b in a slit-like pattern, the capacitance can be made smaller than when the second wiring layer 71b is formed in a solid pattern or a mesh pattern.

[0204] Fig. 44 is a diagram showing a photodetector 1 according to an eighth modified example of the seventh embodiment. Fig. 44A is a plan view of the optical shield layer (second wiring layer 71b), Fig. 44B is a cross-sectional view in the substrate depth direction along line AB in Fig. 44A, Fig. 44C is a cross-sectional view in the substrate depth direction along line CD in Fig. 44A, and Fig. 44D is an external view of a part of chip 21 of photodetector 1.

[0205] The photodetector 1 according to the eighth modification has a second wiring layer 71b in a slit-like pattern extending in a direction different by 90 degrees from that of the photodetector 1 according to the sixth modification. Similarly to the photodetector 1 according to the second modification, instead of connecting a second contact 72b to each second wiring layer 71b, a plurality of contacts 21c are provided at predetermined intervals on the periphery of the chip 21 of the photodetector 1 to set the plurality of second wiring layers 71b to a predetermined potential (for example, ground potential).

[0206] In the photodetector 1 of the eighth variant, there is no need to provide a second contact 72b for each second wiring layer 71b, so the number of second contacts 72b arranged on the second substrate 20 can be reduced and the free space on the second substrate 20 can be increased.

[0207] Fig. 45 is a diagram showing a photodetector 1 according to a ninth modified example of the seventh embodiment. Fig. 45A is a plan view of the optical shield layer (second wiring layer 71b), Fig. 45B is a cross-sectional view in the substrate depth direction along line AB in Fig. 45A, and Fig. 45C is a cross-sectional view in the substrate depth direction along line CD in Fig. 45A.

[0208] In the intermediate layer 70 of the photodetector 1 according to the ninth modification, a second wiring layer 71b and a third wiring layer 71c functioning as an optical shield layer are laminated on a first wiring layer 71a connected to the floating diffusion FD. In this manner, the optical shield layer according to the ninth modification has a laminated structure of the second wiring layer 71b and the third wiring layer 71c.

[0209] The second wiring layer 71b and the third wiring layer 71c are both solid patterns, and openings 71h are formed in the locations where they overlap when viewed in a plan view. First contacts 72a extending from the first wiring layer 71a to the second substrate 20 are disposed in these openings 71h. Second contacts 72b extending to the second substrate 20 are connected to the second wiring layer 71b and the third wiring layer 71c. The second contacts 72b set the second wiring layer 71b and the third wiring layer 71c to a predetermined potential (for example, ground potential).

[0210] In this way, by forming the optical shield layer into a laminated structure of the second wiring layer 71b and the third wiring layer 71c, it is possible to further improve the shielding effect against the light that has passed through the photodiode PD and the light from the second substrate 20. However, there is a risk that a larger capacitance will be added by providing the second wiring layer 71b and the third wiring layer 71c.

[0211] Fig. 46 is a diagram showing a photodetector 1 according to a tenth modified example of the seventh embodiment. Fig. 46A is a plan view of the optical shield layer (second wiring layer 71b), Fig. 46B is a cross-sectional view in the substrate depth direction along line AB in Fig. 46A, Fig. 46C is a cross-sectional view in the substrate depth direction along line CD in Fig. 46A, and Fig. 46D is an external view of a part of chip 21 of photodetector 1.

[0212] In the photodetector element 1 according to the tenth modification, similarly to the ninth modification, the optical shield layer provided in the intermediate layer 70 has a laminated structure of the second wiring layer 71b and the third wiring layer 71c.

[0213] Furthermore, in the photodetector element 1 of the tenth modified example, instead of connecting a second contact 72b to each second wiring layer 71b, multiple contacts 21c are provided at predetermined intervals on the periphery of the chip 21 of the photodetector element 1, and the multiple second wiring layers 71b are set to a predetermined potential (e.g., ground potential).

[0214] In the photodetector 1 of the tenth variant, there is no need to provide a second contact 72b for each second wiring layer 71b, so the number of second contacts 72b arranged on the second substrate 20 can be reduced, and the free space on the second substrate 20 can be increased.

[0215] Fig. 47 is a diagram showing a photodetector 1 according to an eleventh modified example of the seventh embodiment. Fig. 47A is a plan view of the optical shield layer (second wiring layer 71b), Fig. 47B is a cross-sectional view in the substrate depth direction along line AB in Fig. 47A, and Fig. 47C is a cross-sectional view in the substrate depth direction along line CD in Fig. 47A.

[0216] In the intermediate layer 70 of the photodetector 1 according to the eleventh modification, a second wiring layer 71b and a third wiring layer 71c functioning as an optical shield layer are laminated on a first wiring layer 71a connected to the floating diffusion FD. In this manner, the optical shield layer according to the eleventh modification has a laminated structure of the second wiring layer 71b and the third wiring layer 71c.

[0217] The second wiring layer 71b and the third wiring layer 71c are both in a mesh pattern, and openings 71h are formed in the areas where they overlap when viewed in a plan view. First contacts 72a extending from the first wiring layer 71a to the second substrate 20 are disposed in these openings 71h. Second contacts 72b extending to the second substrate 20 are connected to the second wiring layer 71b and the third wiring layer 71c. The second contacts 72b set the second wiring layer 71b and the third wiring layer 71c to a predetermined potential (for example, ground potential).

[0218] In this way, by forming the optical shield layer into a laminated structure of the second wiring layer 71b and the third wiring layer 71c, it is possible to further improve the shielding effect against the light that has passed through the photodiode PD and the light from the second substrate 20. Furthermore, by forming the second wiring layer 71b and the third wiring layer 71c into a mesh pattern, it is possible to reduce the capacitance compared to a solid pattern.

[0219] Fig. 48 is a diagram showing a photodetector 1 according to a twelfth modified example of the seventh embodiment. Fig. 48A is a plan view of the optical shield layer (second wiring layer 71b), Fig. 48B is a cross-sectional view in the substrate depth direction along line AB in Fig. 48A, Fig. 48C is a cross-sectional view in the substrate depth direction along line CD in Fig. 48A, and Fig. 48D is an external view of a portion of chip 21 of photodetector 1.

[0220] In the photodetector 1 according to the twelfth modification, similarly to the eleventh modification, the optical shield layer provided in the intermediate layer 70 has a laminated structure of the second wiring layer 71b and the third wiring layer 71c. The second wiring layer 71b and the third wiring layer 71c have a mesh pattern.

[0221] Furthermore, in the photodetector element 1 of the twelfth modified example, instead of connecting a second contact 72b to each second wiring layer 71b, a plurality of contacts 21c are provided at a predetermined interval on the periphery of the chip 21 of the photodetector element 1, and the plurality of second wiring layers 71b are set to a predetermined potential (e.g., ground potential).

[0222] In the photodetector 1 of the twelfth variant, there is no need to provide a second contact 72b for each second wiring layer 71b, so the number of second contacts 72b arranged on the second substrate 20 can be reduced and the free space on the second substrate 20 can be increased.

[0223] Fig. 49 is a diagram showing a photodetector 1 according to a thirteenth modified example of the seventh embodiment. Fig. 49A is a plan view of the optical shield layer (second wiring layer 71b), Fig. 49B is a cross-sectional view in the substrate depth direction along line AB in Fig. 49A, and Fig. 49C is a cross-sectional view in the substrate depth direction along line CD in Fig. 49A.

[0224] In the intermediate layer 70 of the photodetector 1 according to the 13th modification, a second wiring layer 71b and a third wiring layer 71c functioning as an optical shield layer are laminated on a first wiring layer 71a connected to the floating diffusion FD. In this manner, the optical shield layer according to the 13th modification has a laminated structure of the second wiring layer 71b and the third wiring layer 71c.

[0225] The second wiring layer 71b and the third wiring layer 71c are both slit-shaped patterns, and openings 71h are formed where they overlap when viewed in a plan view. First contacts 72a extending from the first wiring layer 71a to the second substrate 20 are disposed in these openings 71h. Second contacts 72b extending to the second substrate 20 are connected to the second wiring layer 71b and the third wiring layer 71c. The second contacts 72b set the second wiring layer 71b and the third wiring layer 71c to a predetermined potential (for example, ground potential).

[0226] In this way, by forming the optical shield layer into a laminated structure of the second wiring layer 71b and the third wiring layer 71c, it is possible to further improve the shielding effect against the light that has passed through the photodiode PD and the light from the second substrate 20. Furthermore, by forming the second wiring layer 71b and the third wiring layer 71c into a slit-like pattern, it is possible to reduce the capacitance compared to a solid pattern or a mesh pattern.

[0227] Fig. 50 is a diagram showing a photodetector 1 according to a fourteenth modified example of the seventh embodiment. Fig. 50A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 50B is a cross-sectional view in the substrate depth direction along line AB in Fig. 50A, Fig. 50C is a cross-sectional view in the substrate depth direction along line CD in Fig. 50A, and Fig. 50D is an external view of a part of chip 21 of photodetector 1.

[0228] In the photodetector 1 according to the fourteenth modification, similarly to the thirteenth modification, the optical shield layer provided on the intermediate layer 70 has a laminated structure of the second wiring layer 71b and the third wiring layer 71c. The second wiring layer 71b and the third wiring layer 71c have a slit-shaped pattern.

[0229] In addition, in the photodetector element 1 of the 14th variant, instead of connecting a second contact 72b to each second wiring layer 71b, multiple contacts 21c are provided at a predetermined interval on the periphery of the chip 21 of the photodetector element 1, and the multiple second wiring layers 71b are set to a predetermined potential (e.g., ground potential).

[0230] In the photodetector 1 of the fourteenth variant, there is no need to provide a second contact 72b for each second wiring layer 71b, so the number of second contacts 72b arranged on the second substrate 20 can be reduced and the free space on the second substrate 20 can be increased.

[0231] Fig. 51 is a diagram showing a photodetector 1 according to a fifteenth modification of the seventh embodiment. Fig. 51A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 51B is a cross-sectional view in the substrate depth direction along line AB in Fig. 51A, and Fig. 51C is a cross-sectional view in the substrate depth direction along line CD in Fig. 51A.

[0232] In the intermediate layer 70 of the photodetector 1 according to the fifteenth modification, a second wiring layer 71b and a third wiring layer 71c functioning as an optical shield layer are laminated on a first wiring layer 71a connected to the floating diffusion FD. In this manner, the optical shield layer according to the fifteenth modification has a laminated structure of the second wiring layer 71b and the third wiring layer 71c.

[0233] The second wiring layer 71b and the third wiring layer 71c according to the fifteenth modification are both slit-shaped patterns extending in a direction different by 90 degrees from the second wiring layer 71b and the third wiring layer 71c according to the thirteenth modification, and openings 71h are formed at the locations where they overlap when viewed in a plan view. In these openings 71h, first contacts 72a extending from the first wiring layer 71a to the second substrate 20 are disposed. In addition, second contacts 72b extending to the second substrate 20 are connected to the second wiring layer 71b and the third wiring layer 71c. The second contacts 72b set the second wiring layer 71b and the third wiring layer 71c to a predetermined potential (for example, ground potential).

[0234] In this way, by forming the optical shield layer into a laminated structure of the second wiring layer 71b and the third wiring layer 71c, it is possible to further improve the shielding effect against the light that has passed through the photodiode PD and the light from the second substrate 20. Furthermore, by forming the second wiring layer 71b and the third wiring layer 71c into a slit-like pattern, it is possible to reduce the capacitance compared to a solid pattern or a mesh pattern.

[0235] Fig. 52 is a diagram showing a photodetector 1 according to a sixteenth modified example of the seventh embodiment. Fig. 52A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 52B is a cross-sectional view in the substrate depth direction along line AB in Fig. 52A, Fig. 52C is a cross-sectional view in the substrate depth direction along line CD in Fig. 52A, and Fig. 52D is an external view of a part of chip 21 of photodetector 1.

[0236] In the photodetector 1 according to the 16th modification, the optical shield layer provided on the intermediate layer 70 has a laminated structure of a second wiring layer 71b and a third wiring layer 71c, similar to the 15th modification. The second wiring layer 71b and the third wiring layer 71c according to the 16th modification are slit-shaped patterns extending in a direction different by 90 degrees from the second wiring layer 71b and the third wiring layer 71c according to the 14th modification.

[0237] In addition, in the photodetector element 1 of the 16th variant, instead of connecting a second contact 72b to each second wiring layer 71b, multiple contacts 21c are provided at a predetermined interval on the periphery of the chip 21 of the photodetector element 1, and the multiple second wiring layers 71b are set to a predetermined potential (e.g., ground potential).

[0238] In the photodetector 1 of the sixteenth variant, there is no need to provide a second contact 72b for each second wiring layer 71b, so the number of second contacts 72b arranged on the second substrate 20 can be reduced and the free space on the second substrate 20 can be increased.

[0239] Fig. 53 is a diagram showing a photodetector 1 according to a seventeenth modified example of the seventh embodiment. Fig. 53A is a plan view of the optical shield layer (second wiring layer 71b), Fig. 53B is a cross-sectional view in the substrate depth direction along line AB in Fig. 53A, and Fig. 53C is a cross-sectional view in the substrate depth direction along line CD in Fig. 53A.

[0240] In the intermediate layer 70 of the photodetector 1 according to the seventeenth modification, a second wiring layer 71b and a third wiring layer 71c functioning as an optical shield layer are laminated on a first wiring layer 71a connected to the floating diffusion FD. In this manner, the optical shield layer according to the seventeenth modification has a laminated structure of the second wiring layer 71b and the third wiring layer 71c.

[0241] The second wiring layer 71b and the third wiring layer 71c are both slit-shaped patterns and are arranged to be shifted from each other in the short direction. This makes it possible to make the area where neither the second wiring layer 71b nor the third wiring layer 71c exists as small as possible when viewed in a plane, and to reduce light leaking from the gap between the second wiring layer 71b and the third wiring layer 71c as much as possible. Openings 71h are formed in parts of the second wiring layer 71b and the third wiring layer 71c. First contacts 72a extending from the first wiring layer 71a to the second substrate 20 are arranged in these openings 71h. In addition, second contacts 72b extending to the second substrate 20 are connected to the second wiring layer 71b and the third wiring layer 71c. The second contacts 72b set the second wiring layer 71b and the third wiring layer 71c to a predetermined potential (for example, ground potential).

[0242] In this way, in the seventeenth modification, the second wiring layer 71b and the third wiring layer 71c are formed in a slit-shaped pattern, so that the capacitance can be reduced. Also, the second wiring layer 71b and the third wiring layer 71c are arranged offset in the short side direction, so that the amount of light leaking from the gap between the second wiring layer 71b and the third wiring layer 71c can be reduced.

[0243] Fig. 54 is a diagram showing a photodetector 1 according to an 18th modified example of the seventh embodiment. Fig. 54A is a plan view of the optical shield layer (second wiring layer 71b), Fig. 54B is a cross-sectional view in the substrate depth direction along line AB in Fig. 54A, Fig. 54C is a cross-sectional view in the substrate depth direction along line CD in Fig. 54A, and Fig. 54D is an external view of a part of chip 21 of photodetector 1.

[0244] In the photodetector 1 according to the 18th modification, similarly to the 17th modification, the optical shield layer provided on the intermediate layer 70 has a laminated structure of a second wiring layer 71b and a third wiring layer 71c. The second wiring layer 71b and the third wiring layer 71c have slit-shaped patterns and are arranged to be shifted from each other in the short side direction.

[0245] Furthermore, in the photodetector element 1 of the 18th variant, instead of connecting a second contact 72b to each second wiring layer 71b, multiple contacts 21c are provided at predetermined intervals on the periphery of the chip 21 of the photodetector element 1, and the multiple second wiring layers 71b are set to a predetermined potential (e.g., ground potential).

[0246] In the photodetector 1 of the 18th variant, there is no need to provide a second contact 72b for each second wiring layer 71b, so the number of second contacts 72b arranged on the second substrate 20 can be reduced and the free space on the second substrate 20 can be increased.

[0247] Fig. 55 is a diagram showing a photodetector 1 according to a 19th modified example of the seventh embodiment. Fig. 55A is a plan view of the optical shield layer (second wiring layer 71b), Fig. 55B is a cross-sectional view in the substrate depth direction along line AB in Fig. 55A, and Fig. 55C is a cross-sectional view in the substrate depth direction along line CD in Fig. 55A.

[0248] In the intermediate layer 70 of the photodetector 1 according to the 19th modification, a second wiring layer 71b and a third wiring layer 71c functioning as an optical shield layer are laminated on a first wiring layer 71a connected to the floating diffusion FD. In this manner, the optical shield layer according to the 19th modification has a laminated structure of the second wiring layer 71b and the third wiring layer 71c.

[0249] The second wiring layer 71b and the third wiring layer 71c are both slit-shaped patterns and are arranged to be shifted from each other in the short side direction. The second wiring layer 71b and the third wiring layer 71c according to the 19th modification extend in a direction that is 90 degrees different from the second wiring layer 71b and the third wiring layer 71c according to the 17th modification.

[0250] According to the 19th modification, the area where neither the second wiring layer 71b nor the third wiring layer 71c exists can be made as small as possible when viewed in a plan view, and light leaking from the gap between the second wiring layer 71b and the third wiring layer 71c can be reduced as much as possible. Openings 71h are formed in parts of the second wiring layer 71b and the third wiring layer 71c. First contacts 72a extending from the first wiring layer 71a to the second substrate 20 are disposed in these openings 71h. In addition, second contacts 72b extending to the second substrate 20 are connected to the second wiring layer 71b and the third wiring layer 71c. The second contacts 72b set the second wiring layer 71b and the third wiring layer 71c to a predetermined potential (for example, ground potential).

[0251] In this way, in the 19th modification, the second wiring layer 71b and the third wiring layer 71c are formed into a slit-shaped pattern, so that the capacitance can be reduced. Also, the second wiring layer 71b and the third wiring layer 71c are arranged offset in the short side direction, so that the amount of light leaking from the gap between the second wiring layer 71b and the third wiring layer 71c can be reduced.

[0252] Fig. 56 is a diagram showing a photodetector 1 according to a twentieth modification of the seventh embodiment. Fig. 56A is a plan view of the optical shield layer (second wiring layer 71b), Fig. 56B is a cross-sectional view in the substrate depth direction along line AB in Fig. 56A, Fig. 56C is a cross-sectional view in the substrate depth direction along line CD in Fig. 56A, and Fig. 56D is an external view of a portion of chip 21 of photodetector 1.

[0253] In the photodetector element 1 according to the 20th modification, similarly to the 19th modification, the optical shield layer provided on the intermediate layer 70 has a laminated structure of a second wiring layer 71b and a third wiring layer 71c. The second wiring layer 71b and the third wiring layer 71c have slit-shaped patterns and are arranged to be shifted from each other in the short side direction. The second wiring layer 71b and the third wiring layer 71c according to the 20th modification extend in a direction different by 90 degrees from the second wiring layer 71b and the third wiring layer 71c according to the 18th modification.

[0254] Furthermore, in the photodetector element 1 of the 20th variant, instead of connecting a second contact 72b to each second wiring layer 71b, multiple contacts 21c are provided at predetermined intervals on the periphery of the chip 21 of the photodetector element 1, and the multiple second wiring layers 71b are set to a predetermined potential (e.g., ground potential).

[0255] In the photodetector 1 of the 20th variant, there is no need to provide a second contact 72b for each second wiring layer 71b, so the number of second contacts 72b arranged on the second substrate 20 can be reduced, and the free space on the second substrate 20 can be increased.

[0256] Fig. 57 is a diagram showing a photodetector 1 according to a twenty-first modified example of the seventh embodiment. Fig. 57A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 57B is a cross-sectional view in the substrate depth direction along line AB in Fig. 57A, Fig. 57C is a cross-sectional view in the substrate depth direction along line CD in Fig. 57A, and Fig. 57D is a cross-sectional view in the substrate depth direction along line EF.

[0257] The photodetector 1 according to the twenty-first modification includes a first wiring layer 71a and a second wiring layer 71b in an intermediate layer 70. The first wiring layer 71a is connected to a floating diffusion FD, and the second wiring layer 71b functions as an optical shield layer.

[0258] The second wiring layer 71b has a solid pattern, but is cut out along the contour of the first wiring layer 71a. When viewed from above the intermediate layer 70, the first wiring layer 71a and the second wiring layer 71b are arranged without overlapping or gaps as shown in FIG.

[0259] According to the twenty-first modification, the light that has passed through the photodiode PD can be blocked by the first wiring layer 71a or the second wiring layer 71b, and the light from the second substrate 20 can be blocked by the first wiring layer 71a or the second wiring layer 71b. This makes it possible to prevent color mixing and the like due to leaked light.

[0260] Fig. 58 is a diagram summarizing various modified examples of the seventh embodiment described above. Pattern A1 in Fig. 58 corresponds to Fig. 37, pattern A-2 to Fig. 39, pattern A-3 to Fig. 41, and pattern A-4 to Fig. 43. Pattern B-1 corresponds to Fig. 45, pattern B-2 to Fig. 47, pattern B-3 to Fig. 49, pattern B-4 to Fig. 51, pattern B-5 to Fig. 53, and pattern B-6 to Fig. 55. Pattern A-1-T corresponds to Fig. 38, pattern A-2-T to Fig. 40, pattern A-3-T to Fig. 42, and pattern A-4-T to Fig. 44. Pattern B-1-T corresponds to Fig. 46, pattern B-2-T to Fig. 48, pattern B-3-T to Fig. 50, pattern B-4-T to Fig. 52, pattern B-5-T to Fig. 54, pattern B-6-T to Fig. 56, and pattern AF-1 to Fig. 57.

[0261] The wiring layer 71 made of polysilicon in the intermediate layer 70 has one or more optical shield layers in addition to the wiring layer 71 connected to the floating diffusion FD, etc. The shape of the optical shield layer includes a solid pattern, a mesh pattern, and a slit (straight line) pattern. The connection point between the optical shield layer and the contact is the pixel 12 sharing unit or the chip 21 end.

[0262] In this way, in the seventh embodiment, the wiring layer 71a and the optical shield layer 71b are disposed in different layers of the intermediate layer 70, so that the light that has passed through the photodiode PD and the light that has been emitted by the second substrate 20 for some reason can be blocked by the optical shield layer 71b, and deterioration of image quality due to color mixing and noise light can be prevented. In addition, by devising the shape of the optical shield layer 71b, an increase in capacitance due to the provision of the optical shield layer 71b can be suppressed, and a decrease in photoelectric conversion efficiency can be suppressed. Furthermore, by forming the optical shield layer 71b and the wiring layer 71a in a shape other than a solid pattern and displacing the optical shield layer 71b and the wiring layer 71a, unnecessary light can be blocked, the capacitance can be reduced, and a decrease in photoelectric conversion efficiency can be suppressed.

[0263] Eighth embodiment The light-detecting element 1 according to the eighth embodiment is characterized in that, when the wiring layer 71 is made of polysilicon, the polysilicon contains arsenic (As) and phosphorus (P).

[0264] FIG. 59A is a graph comparing the sheet resistance of arsenic (As) and phosphorus (P) ions, and FIG. 59B is a graph comparing the diffusion length in silicon doped with arsenic (As) and phosphorus (P) ions.

[0265] 59A and 59B, when phosphorus (P) ions are implanted into polysilicon, the resistance of the polysilicon decreases. Therefore, for example, it is possible to suppress deterioration of noise characteristics due to an increase in the gate resistance of the amplification transistor AMP.

[0266] On the other hand, when arsenic (As) ions are implanted into polysilicon, arsenic (As) does not easily diffuse in polysilicon, so no problems due to diffusion do occur. Therefore, for example, it is possible to suppress the generation of false signals due to the impurities in the wiring layer 71 connected to the FD side diffusing to the vicinity of the transfer gate TG and the increase in the electric field near the transfer gate TG.

[0267] Therefore, in this embodiment, impurity ions consisting of arsenic (As) and phosphorus (P) are contained in the polysilicon, thereby reducing the resistance of the wiring layer 71 consisting of polysilicon and suppressing the diffusion of the impurity ions in the polysilicon.

[0268] 60 is a cross-sectional view of a photodetector 1 according to the eighth embodiment. In the photodetector 1 according to the eighth embodiment, pixels 12 including photodiodes PD are arranged on a first substrate 10, and pixel circuits 22 including pixel transistors 18 are arranged on a second substrate 20. One or more wiring layers 71 are arranged in an intermediate layer 70 (interlayer insulating layer) arranged between the first substrate 10 and the second substrate 20. The wiring layer 71 of the intermediate layer 70 is formed of polysilicon containing arsenic (As) and phosphorus (P).

[0269] In the intermediate layer 70, one or more wiring layers 71 are arranged in the same or different layers, but only one wiring layer 71 (hereinafter, the first wiring layer 71a) is shown in Fig. 60. The first wiring layer 71a is connected to the floating diffusion FD of the first substrate 10 via a first contact 73a. In addition, a second contact 72a extending to the second substrate 20 is connected to the first wiring layer 71a, and the second contact 72b is connected to the pixel transistor 18 via the wiring layer 71 of the second substrate 20.

[0270] The floating diffusion FD shown in Fig. 60 is formed by implanting impurity ions including arsenic (As) and phosphorus (P) into a silicon substrate. A SiO2 layer is disposed on the silicon substrate, and a trench is formed by etching away a portion of the SiO2 layer in accordance with the positions of the first wiring layer 71a and the first contact 73a, and the inside of the trench is filled with polysilicon to form the first wiring and the first contact 73a.

[0271] The method of forming the floating diffusion FD is not limited to that shown in FIG.

[0272] FIG. 61 is a cross-sectional view of a photodetector 1 according to a first modification of the eighth embodiment. In the photodetector 1 according to the first modification, a trench is formed in a portion of a silicon substrate where a floating diffusion FD is to be formed, SiO2, which is the material of the element isolation portion 43, is filled inside the trench, and polysilicon is then filled thereon, and impurity ions containing arsenic (As) and phosphorus (P) are injected into the polysilicon-filled region and thermally diffused. As a result, an impurity diffusion region is formed in the sidewall direction of the polysilicon-filled region, forming a floating diffusion FD. This manufacturing method is called a side contact 27. The FD capacitance only needs to have a capacity that can hold the accumulated charge of the photodiode PD, and if there is a capacity larger than that, it becomes a factor that increases noise. By forming a floating diffusion FD using the side contact 27, the FD capacitance can be reduced, and noise can be reduced.

[0273] In this embodiment, the arsenic (As) concentration in the first wiring layer 71a is set higher than the phosphorus (P) concentration, which suppresses the diffusion of impurity ions in the floating diffusion FD to the silicon substrate, thereby suppressing noise by reducing the FD capacitance and reducing the leak current by reducing the electric field near the TG.

[0274] 62 is a cross-sectional view of a photodetector 1 according to a second modified example of the eighth embodiment. In the photodetector 1 according to the second modified example, a first wiring layer 71a and a second wiring layer 71b are arranged in the same layer of the intermediate layer 70. The first wiring layer 71a is connected to the floating diffusion FD of the first substrate 10 via a first contact 73a, and is connected to the pixel transistor 18 of the second substrate 20 via a second contact 72b. The second wiring layer 71b is connected to the transfer transistor TR of the first substrate 10 via a third contact 73c, and is connected to the gate voltage control line of the transfer transistor TR via a fourth contact.

[0275] Both the first wiring layer 71a and the second wiring layer 71b are formed of polysilicon containing impurity ions made of arsenic (As) and phosphorus (P). The impurity ion concentrations contained in the first wiring layer 71a and the impurity ion concentrations contained in the second wiring layer 71b are different from each other.

[0276] More specifically, the arsenic (As) concentration of the first wiring layer 71a is higher than the arsenic (As) concentration of the second wiring layer 71b. Alternatively, the phosphorus (P) concentration of the first wiring layer 71a is lower than the phosphorus (P) concentration of the second wiring layer 71b. This can reduce the FD capacitance and the resistance of the second wiring layer 71b.

[0277] Moreover, the phosphorus (P) concentration of the second wiring layer 71b is higher than the arsenic (As) concentration, which allows the second wiring layer 71b to have a low resistance, enabling the transfer transistor TR to operate at a high speed.

[0278] 63 is a cross-sectional view of a photodetector 1 according to a third modified example of the eighth embodiment. The photodetector 1 according to the third modified example includes a peripheral region disposed outside the pixel region. In addition to the first wiring layer 71a and the second wiring layer 71b described above, a third wiring layer 71c is provided in the intermediate layer 70. The first wiring layer 71a, the second wiring layer 71b, and the third wiring layer 71c may be disposed in the same layer of the intermediate layer 70, or may be disposed in two or more layers.

[0279] The third wiring layer 71c is connected to a diffusion layer in the peripheral region of the first substrate 10 via a fifth contact.

[0280] In the light detection element 1 according to the third modification, the first wiring layer 71a, the second wiring layer 71b, and the third wiring layer 71c are all formed of polysilicon containing arsenic (As) and phosphorus (P) ions. The impurity concentration contained in the first wiring layer 71a is different from the impurity concentration contained in the third wiring layer 71c.

[0281] More specifically, the arsenic (As) concentration of the first wiring layer 71a is higher than the arsenic (As) concentration of the third wiring layer 71c. Alternatively, the phosphorus (P) concentration of the first wiring layer 71a is lower than the phosphorus (P) concentration of the third wiring layer 71c. This makes it possible to achieve both a reduction in FD capacitance and a reduction in resistance of the third wiring layer 71c.

[0282] Furthermore, the phosphorus (P) concentration of the third wiring layer 71c is higher than the arsenic (As) concentration, which allows the third wiring layer 71c to have a low resistance, stabilizes the reference voltage, and improves image quality.

[0283] 64A to 64I are cross-sectional views showing the steps of manufacturing the photodetector 1 according to the eighth embodiment. First, a pixel 12 including a photodiode PD, a transfer transistor TR, and a floating diffusion FD is formed on a silicon substrate, which is a first substrate 10 (FIG. 64A).

[0284] Next, a SiO2 film 46 is formed on the upper surface of the first substrate 10, and a portion of the SiO2 film 46 is removed by photolithography to form a trench 38. The inside of the trench 38 is filled with polysilicon, and a wiring layer 71 made of polysilicon is formed on the upper surface of the SiO2 film. Next, impurity ions containing arsenic (As) and phosphorus (P) are implanted into the wiring layer 71 (FIG. 64B). When implanting the impurity ions, the impurity ions may be implanted separately using a resist mask (FIG. 64C).

[0285] Next, the wiring layer 71 is patterned by photolithography using dry etching to form a first wiring layer 71a and a second wiring layer 71b (FIG. 64D).

[0286] Next, a heat treatment is performed to activate the impurity ions implanted into the first wiring layer 71a and the second wiring layer 71b (FIG. 64E).

[0287] Next, the second substrate 20 is attached (FIG. 64F). Next, a readout circuit (pixel circuit 22) is formed on the second substrate 20 (FIG. 64G). Next, a trench 38 is formed in the second substrate 20 by photolithography (FIG. 64H), and contacts 72a, 72b and metal wiring 39 are formed (FIG. 64H).

[0288] In this way, in the eighth embodiment, the wiring layer 71 disposed in the intermediate layer 70 is formed of polysilicon containing arsenic (As) and phosphorus (P), so that it is possible to achieve both low resistance of the wiring layer 71 and suppression of diffusion of impurity ions into the polysilicon. When a plurality of wiring layers 71 are disposed in the intermediate layer 70, the impurity concentrations of arsenic (As) and phosphorus (P) are controlled for each wiring layer 71, thereby further improving the image quality of the captured image.

[0289] Forming each of the wiring layers 71 disposed in the intermediate layer 70 from polysilicon containing arsenic (As) and phosphorus (P) is also applicable to the photodetector elements 1 according to the first to seventh embodiments described above. By optimizing the impurity concentrations of arsenic (As) and phosphorus (P) for each of the wiring layers 71 disposed in the intermediate layer 70, it is possible to improve the quality of the captured image generated by the photodetector elements 1 according to the first to seventh embodiments and increase the charge transfer speed.

[0290] Ninth embodiment When the photodetector 1 has a laminated structure of the first substrate 10 and the second substrate 20, the first substrate 10 and the second substrate 20 are not necessarily at the same potential, and therefore an electric field is applied between the first substrate 10 and the second substrate 20. For example, if the power supply voltage of the first substrate 10 fluctuates for some reason, the power supply voltage of the second substrate 20 also fluctuates, adversely affecting the electrical characteristics of the photodetector 1. Therefore, in the ninth embodiment, a wiring layer 71 functioning as a shielding layer is disposed in an interlayer insulating layer (intermediate layer) 70 between the first substrate 10 and the second substrate 20 to shield the above-mentioned electric field.

[0291] FIG. 65A is a vertical cross-sectional view of a photodetector 1 according to the ninth embodiment, and FIG. 65B is a horizontal cross-sectional view taken along line AB in FIG. 65A.

[0292] As shown in FIG. 65A, the photodetector 1 according to the ninth embodiment includes a first substrate 10 and a second substrate 20 that are stacked, and an interlayer insulating layer (intermediate layer) 70 that is disposed between the first substrate 10 and the second substrate 20. A photodiode PD, a transfer transistor TR, a floating diffusion FD, and the like are disposed on the first substrate 10. Pixel transistors 18, such as an amplification transistor AMP and a selection transistor SEL, are disposed on the second substrate 20. Although omitted in FIG. 9A, a reset transistor RST, a conversion efficiency switching transistor FDG, and the like may be disposed on the second substrate 20. The pixel transistor 18 may be of a planar type, may have a FIN-FET structure, or may have a gate-all-around structure.

[0293] A wiring layer 71 is disposed on the intermediate layer 70. The wiring layer 71 functions as a shield layer that shields an electric field generated between the first substrate 10 and the second substrate 20. The wiring layer 71 is formed of, for example, polysilicon. As will be described later, the wiring layer 71 can also be formed of a conductive material other than polysilicon.

[0294] The wiring layer 71 is provided with an opening 65 for the first contact 72a extending from the floating diffusion FD of the first substrate 10 to the second substrate 20. The opening 65 is larger than the outer diameter of the first contact 72a. An insulating layer 66 is disposed around the opening 65 in the wiring layer 71. That is, the insulating layer 66 is disposed in a predetermined region including a connection portion with the first contact 72a in the wiring layer 71. The size and shape of the predetermined region are arbitrary. In FIG. 65B, the insulating layer 66 is rectangular, but may be other shapes, for example, circular. By disposing the insulating layer 66 around the opening 65 of the wiring layer 71, the first contact 72a and the wiring layer 71 can be electrically insulated, and there is no risk of the first contact 72a and the wiring layer 71 being short-circuited.

[0295] The insulating layer 66 may include two or more types of insulators having different dielectric constants. For example, the insulating layer 66 may include an air layer 67 arranged to surround the first contact 72a. More specifically, the insulating layer 66 may include a first insulating layer 66a and a second insulating layer 66b in addition to the air layer 67. The first insulating layer 66a is arranged to surround the first contact 72a at a location closer to the first contact 72a than the air layer 67, and includes an insulator having a higher dielectric constant than the air layer 67. The second insulating layer 66b is arranged to surround the first contact 72a at a location farther from the first contact 72a than the air layer 67, and includes an insulator having a higher dielectric constant than the air layer 67. By arranging the air layer 67 in a part of the insulating layer 66, the dielectric constant of the insulating layer 66 can be reduced, and the capacitance between the first contact 72a and the wiring layer 71 can be reduced. By reducing the capacitance between the first contact 72a and the wiring layer 71, for example, a decrease in photoelectric conversion efficiency can be suppressed.

[0296] On the other hand, the second contact 72b is disposed so as to be conductive with the wiring layer 71, and therefore the wiring layer 71 is set to a predetermined potential via the second contact 72b. The second contact 72b is connected to the p-well layer 42 of the first substrate 10, and is set to, for example, a ground potential. Therefore, by connecting the second contact 72b to the wiring layer 71, the wiring layer 71 can be set to the ground potential.

[0297] The wiring layer 71 is disposed, for example, over the entire area of ​​the horizontal cross section of the interlayer insulating layer (intermediate layer) 70. This makes it possible to shield the electric field between the first substrate 10 and the second substrate 20, regardless of the sizes of the first substrate 10 and the second substrate 20. As will be described later, a modified example in which the size of the wiring layer 71 is made smaller than the entire area of ​​the horizontal cross section of the interlayer insulating layer (intermediate layer) 70 is also possible.

[0298] 65A and 65B show two contacts (first contact 72a and second contact 72b) that cross or are connected to wiring layer 71, but other contacts may be arranged to cross or be connected to wiring layer 71. In this case, like first contact 72a, an insulating layer 66 must be provided around the contacts.

[0299] Various modifications are possible regarding the material of the insulating layer 66 disposed on a part of the wiring layer 71 .

[0300] FIG. 66A is a vertical cross-sectional view of a photodetector 1 according to a first modified example of the ninth embodiment, and FIG. 66B is a horizontal cross-sectional view taken along the line AB in FIG. 66A. In the photodetector 1 according to the first modified example, the material of the insulating layer 66 disposed in a part of the wiring layer 71 is different from that described above. The insulating layer 66L of the photodetector 1 according to the first modified example is a low-k material. By using a low-k material for the insulating layer 66L, the dielectric constant of the insulating layer 66L can be reduced, and the capacitance between the first contact 72a and the wiring layer 71 can be reduced. The dielectric constant of the insulating layer 66L is preferably, for example, 3.0 or less, and more preferably 2.8 or less. The lower limit of the dielectric constant of the insulating layer 66 is preferably 2.3 or more.

[0301] Specific examples of low-k materials that can be used include hydrogen silsesquioxane resin (HSQ (hydrogen silsesquioxane): dielectric constant 3.0), benzocyclobutene (BCB (benzocyclobutene): dielectric constant 2.7), polyarylether (PAE (polyarylether): dielectric constant 2.7), carbon-containing silicon oxide (SiOC: dielectric constant 2.9), polyarylate (PAr (polyarylate): dielectric constant 2.65), fluorine-doped silicon oxide (SiOF: dielectric constant 2.6 to 3.7), and fluorine-doped silicon oxide (SiO2 film fluorine doped silicon dioxide: dielectric constant 3.3 to 3.4 at a content of 11 at%).

[0302] Alternatively, the low-k material used for the insulating layer 66L may be SiOC or a porous material.

[0303] FIG. 67A is a vertical cross-sectional view of a photodetector 1 according to a second modification of the ninth embodiment, and FIG. 67B is a horizontal cross-sectional view taken along the line AB in FIG. 67A. In the photodetector 1 according to the second modification, the material of the insulating layer 66I disposed in a part of the wiring layer 71 is different from that described above. The insulating layer 66I of the photodetector 1 according to the second modification is formed of an insulator such as SiO2. Various impurities may be doped into SiO2. For example, fluorine-doped silicon oxide is preferable from the viewpoint of ease of manufacture. The fluorine-doped silicon oxide is an oxide film to which fluorine is added, and is formed by a plasma CVD (chemical vapor deposition) method using a source such as TEOS-C2F6 or TEFS (triethoxyfluorosilane).

[0304] The material of the wiring layer 71 can be polysilicon as described above, but other than that, a metal material or a conductive organic material may also be used.

[0305] In the above-mentioned Figures 65A to 67A and Figures 65B to 67B, an example is shown in which wiring layer 71 is arranged over the entire horizontal cross section (transverse cross section) of intermediate layer 70, but wiring layer 71 may be arranged only in the area where an electric field is generated between first substrate 10 and second substrate 20.

[0306] Fig. 68A is a vertical cross-sectional view of a photodetector 1 according to a third modified example of the ninth embodiment, and Fig. 68B is a horizontal cross-sectional view taken along line AB in Fig. 68A. The photodetector 1 according to the third modified example has a wiring layer 71 arranged only in a part of one layer of the intermediate layer 70. This wiring layer 71 is arranged in a location where an electric field is generated between the first substrate 10 and the second substrate 20. Alternatively, the wiring layer 71 is arranged in a location where the circuits and the like arranged on the first substrate 10 and the second substrate 20 may be adversely affected by the electric field generated between the first substrate 10 and the second substrate 20.

[0307] An insulating layer 46 is disposed in the same layer as the wiring layer 71 so as to surround the wiring layer 71. The insulating layer 46 is, for example, a SiO2 layer.

[0308] The wiring layer 71 according to the third modified example has an area smaller than that of the wiring layer 71 in the above-described Figures 65B to 67 B. As the material of the wiring layer 71, for example, polysilicon is used, like the above-described wiring layer 71.

[0309] An insulating layer 66 is disposed on a part of the wiring layer 71 according to the third modification. The material and shape of the insulating layer 66 are the same as those in, for example, Fig. 65B. A second contact 72b is connected to the wiring layer 71, as in Fig. 65B.

[0310] Since wiring layer 71 according to the third modification need only have a necessary minimum area, as shown in Fig. 68B, an opening may be provided between the connection point with second contact 72b and insulating layer 66. Insulating layer 66 made of SiO2 or the like is disposed in the opening.

[0311] FIG. 69A is a vertical cross-sectional view of a photodetector 1 according to a fourth modified example of the ninth embodiment, and FIG. 69B is a horizontal cross-sectional view taken along the line AB in FIG. 69A. The photodetector 1 according to the fourth modified example includes a wiring layer 71 disposed only in a portion of one layer of the intermediate layer 70, as in the third modified example. The fourth modified example differs from the third modified example in that the material of the insulating layer 66L disposed around the wiring layer 71 is a low-k material. More specifically, in the fourth modified example, both the insulating layer 66L disposed in a portion of the inner side of the wiring layer 71 and the insulating layer 66L disposed outside the wiring layer 71 are made of a low-k material. The specific material of the low-k material may be the material exemplified in the first modified example. The wiring layer 71 is formed of, for example, polysilicon.

[0312] Fig. 70A is a vertical cross-sectional view of a photodetector 1 according to a fifth modified example of the ninth embodiment, and Fig. 70B is a horizontal cross-sectional view taken along line AB in Fig. 70A. In the photodetector 1 according to the fifth modified example, the material of the insulating layer 66I around the wiring layer 71 is, for example, SiO2, instead of the low-k material of the fourth modified example. SiO2 is a commonly used material for the interlayer insulating layer (intermediate layer) 70, and is easy to manufacture.

[0313] FIG. 71A is a vertical cross-sectional view of a photodetector element 1 according to a sixth modified example of the ninth embodiment, and FIG. 71B is a horizontal cross-sectional view taken along the line AB in FIG. 71A. A first contact 72a and a second contact 72b extending in the second direction are disposed on a wiring layer 71 disposed on an intermediate layer 70. The first contact 72a is disposed facing the pixel transistor of the second substrate 20 at its sidewall portion, and a parasitic capacitance occurs between the first contact 72a and the second contact 72b. Similarly, the second contact 72b is disposed facing the pixel transistor of the second substrate 20 at its sidewall portion, and a parasitic capacitance occurs between the second contact 72b and the second contact 72b. These parasitic capacitances may adversely affect the electrical characteristics of the pixel transistor. Therefore, the sixth modified example is characterized in that the sidewall portions of the first contact 72a and the second contact 72b are covered with a sidewall insulating layer 66s. The sidewall insulating layer 66s is preferably low in dielectric constant and is formed of, for example, a low-k material. The specific low-k material may be the material exemplified in the first modified example.

[0314] By covering the sidewall portions of the first contact 72a and the second contact 72b with the sidewall insulating layer 66s, the parasitic capacitance between the first contact 72a and the second contact 72b and the pixel transistor can be reduced, and adverse effects due to the parasitic capacitance are eliminated.

[0315] In the photodetector element 1 according to the above-described ninth embodiment or the first to fifth modifications, a sidewall insulating film similar to that in the sixth modification may be provided.

[0316] Next, a manufacturing process of the photodetector 1 according to the ninth embodiment will be described. Fig. 72A to Fig. 72L are plan views and cross-sectional views showing the manufacturing process of the photodetector 1 according to the ninth embodiment. Fig. 72A shows a state in which a floating diffusion FD, a transfer transistor TR, and a p-well layer 42 are formed on a first substrate 10. An element isolation section 43 is disposed on the first substrate 10 side of the floating diffusion FD and the p-well layer 42. The element isolation section 43 has an insulating layer 43a made of SiO2 and a p-type diffusion layer 43b surrounding the insulating layer 43a. The p-type diffusion layer 43b is also called a pinning layer.

[0317] 72B, an interlayer insulating layer (intermediate layer) 70 is disposed on the first substrate 10, and a polysilicon layer 71p is disposed thereon. The interlayer insulating layer (intermediate layer) 70 is, for example, a SiO2 layer 46. The polysilicon layer 71p is to be a material for the wiring layer 71.

[0318] 72C, a resist layer 68 is applied onto the polysilicon layer 71p by photolithography, and the resist layer 68 is patterned. The resist layer 68 is patterned to match the location of the insulating layer 66 that is to be disposed in a portion of the wiring layer 71.

[0319] Next, as shown in FIG. 72D, using the resist layer 68 as a mask, a portion of the polysilicon layer 71p is removed to expose the SiO2 layer 46.

[0320] 72E, a silicon oxide film 69 is formed by, for example, HDP method on the patterned resist layer 68. The silicon oxide film 69 is, for example, a SiO film.

[0321] 72F, a resist layer 47 is applied onto the SiO film 69 and patterned by photolithography. The portions from which the resist layer 47 is removed are portions where air layers 67 are formed in the insulating layer 66. The SiO film 69 is exposed in the portions from which the resist layer 47 is removed.

[0322] Next, as shown in FIG. 72G, the SiO film 69 is partially removed using the resist layer 47 as a mask to expose the SiO2 film 46, and the resist layer 47 is removed.

[0323] 72H, a thick SiO film 69 is formed by, for example, the HDP method. Since the HDP method has poor embedding properties, an air layer 67 remains that is not filled with the SiO film 69. Through the above steps, an interlayer insulating layer (intermediate layer) 70 is formed on the first substrate 10.

[0324] Next, as shown in Fig. 72I, the second substrate 20 is bonded onto the interlayer insulating layer (intermediate layer) 70. The second substrate 20 has a laminated structure in which a p-well layer 20d and a SiO2 layer 20e are laminated in this order on a silicon substrate 20c. The SiO2 layer 20e of the second substrate 20 is disposed opposite the interlayer insulating layer (intermediate layer) 70 and bonded to it.

[0325] 72J, a trench 20f is formed which penetrates the second substrate 20 and extends to the floating diffusion FD of the first substrate 10, and a trench 20g is formed which penetrates the second substrate 20 and extends to the p-well layer 42 of the first substrate 10. These trenches 20f and 20g are aligned so as not to contact the air layer 67. In addition, a trench 20h which does not penetrate the second substrate 20 is also formed in the second substrate 20.

[0326] Next, as shown in FIG. 72K, the trenches 20f, 20g, and 20h are filled with a conductive material (eg, polysilicon or a metal material) to form a first contact 72a, a second contact 72b, and another contact 72c.

[0327] Next, as shown in FIG. 72L, the pixel transistor 18 is formed on the second substrate 20.

[0328] Thus, in the ninth embodiment, the wiring layer 71 for shielding the electric field applied between the first substrate 10 and the second substrate 20 is disposed on the interlayer insulating layer (intermediate layer 70) disposed between the first substrate 10 and the second substrate 20. This prevents the circuit elements disposed on the first substrate 10 and the second substrate 20 from being affected by the electric field. Also, the insulating layer 66 is disposed on a part of the wiring layer 71 so that the first contact 72a extending to the second substrate 20 through the wiring layer 71 is not electrically connected to the wiring layer 71, so that the first contact 72a and the wiring layer 71 can be electrically insulated from each other. Also, the parasitic capacitance between the first contact 72a and the wiring layer 71 can be reduced by providing an air layer 67 in the insulating layer 66 or by forming the insulating layer 66 from a material with a low dielectric constant.

[0329] <Applications to moving objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0330] FIG. 73 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology of the present disclosure can be applied.

[0331] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 73, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053 are illustrated.

[0332] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0333] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0334] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0335] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0336] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0337] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0338] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0339] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0340] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 73, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0341] FIG. 74 is a diagram showing an example of the installation position of the imaging unit 12031.

[0342] In FIG. 74, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0343] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield in the vehicle interior of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield in the vehicle interior mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield in the vehicle interior is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0344] 74 shows an example of the imaging ranges of the imaging units 12101 to 12104. An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and an imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0345] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of photodetection elements, or may be a photodetection element having pixels for detecting a phase difference.

[0346] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0347] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0348] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0349] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031, etc., among the configurations described above. Specifically, the photodetector 1 according to each embodiment can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, a captured image that is easier to see can be obtained, thereby reducing driver fatigue. The present technology can be configured as follows.

[0350] (1) a first substrate on which a photoelectric conversion element is disposed; a second substrate that is stacked on the first substrate and has at least a part of a pixel circuit that generates a pixel signal according to the charge output from the photoelectric conversion element disposed thereon; and an interlayer insulating layer having two or more stacked wiring layers disposed between the first substrate and the second substrate. Light detection element. (2) The pixel circuit on the second substrate has a pixel transistor including at least one of an amplification transistor, a reset transistor, or a selection transistor. The photodetector element according to (1). (3) The wiring layer is a polysilicon layer or a metal layer. The photodetector element according to (1) or (2). (4) At least one of the type and concentration of impurity ions contained in the two or more wiring layers is different from each other; The light detection element according to any one of (1) to (3). (5) At least a portion of the two or more wiring layers is arranged to intersect when viewed in a plan view. A light detection element according to any one of (1) to (4). (6) The two or more wiring layers include a floating diffusion to which charges generated in the photoelectric conversion element in the first substrate are transferred, a well region of a different conductivity type from the floating diffusion, a transfer transistor that switches whether or not to transfer charges generated in the photoelectric conversion element in the first substrate to the floating diffusion, or a plurality of wiring layers that are respectively connected to at least two of pixel boundary regions of the first substrate. A light detection element according to any one of (1) to (5). (7) The two or more wiring layers include two or more wiring layers arranged in different layers of the interlayer insulating layer, and two or more wiring layers arranged in the same layer of the interlayer insulating layer. The photodetector according to (6). (8) The interlayer insulating layer is a plurality of first contacts each extending from at least a portion of the two or more wiring layers to the second substrate; and a plurality of second contacts extending from the plurality of wiring layers to the first substrate. The photodetector element according to (6) or (7). (8-1) The first substrate is a floating diffusion to which accumulated charges of the photoelectric conversion element are transferred; a transfer transistor that switches whether or not to transfer the accumulated charge of the photoelectric conversion element to the floating diffusion; A well region of a different conductivity type from the floating diffusion, The two or more wiring layers are a first wiring layer connected to the well region; a second wiring layer connected to the floating diffusion; a third wiring layer connected to the transfer transistor; the first wiring layer, the second wiring layer, and the third wiring layer are disposed in different layers of the interlayer insulating layer; The light detection element according to any one of (1) to (7). (8-2) The first wiring layer is disposed closer to the first substrate than the second wiring layer and the third wiring layer. The photodetector according to (8-1). (8-3) A first contact is provided extending from the first wiring layer to the second substrate; the first contact is disposed within the pixel area or outside the pixel area; the well region is set to a predetermined potential via the first contact; The photodetector according to (8-1) or (8-2). (9) The interlayer insulating layer has a charge storage portion that stores charges transferred from the photoelectric conversion element separately from a floating diffusion, The charge storage unit is configured using two wiring layers arranged opposite to each other among the two or more wiring layers. A light detection element according to any one of (1) to (8). (10) A conversion efficiency switching transistor is provided for switching the photoelectric conversion efficiency, the charge accumulation unit accumulates the charge transferred from the photoelectric conversion element when the conversion efficiency switching transistor is on. The photodetector according to (9). (11) A third contact is provided extending from a wiring layer disposed closer to the second substrate, of the two wiring layers constituting the charge storage unit, to the second substrate; a wiring layer disposed closer to the second substrate and a source of the conversion efficiency switching transistor are electrically connected via the third contact; The photodetector according to (10). (12) A plurality of the conversion efficiency switching transistors and a plurality of the charge storage units are provided, the conversion efficiency switching transistors being capable of switching the photoelectric conversion efficiency in three or more stages; the plurality of charge accumulation units are disposed on the interlayer insulating layer, or some of the plurality of charge accumulation units are disposed on the interlayer insulating layer and the remaining charge accumulation units are disposed on the second substrate; The photodetector according to (10) or (11). (12-1) The charge accumulation portion is arranged in a comb shape when viewed in a plan view. The light detection element according to any one of (9) to (12). (12-2) The first substrate is a floating diffusion to which accumulated charges of the photoelectric conversion element are transferred; a transfer transistor that switches whether or not to transfer the accumulated charge of the photoelectric conversion element to the floating diffusion; A well region of a different conductivity type from the floating diffusion, the two or more wiring layers include a first wiring layer connected to the transfer transistor and a second wiring layer connected to the well region; the two wiring layers constituting the charge storage unit are arranged in parallel to at least one of the first wiring layer and the second wiring layer; The light detection element according to any one of (9) to (12). (13) At least one of the two or more wiring layers is a light-shielding layer that blocks light that has passed through the photoelectric conversion element and blocks light from the second substrate. The light detection element according to any one of (1) to (12). (14) The light-shielding layer is set to a predetermined reference potential. The photodetector according to (13). (15) Among the two or more wiring layers, the light-shielding layer and a wiring layer disposed in a layer different from the light-shielding layer are disposed so as to cover the entire area of ​​the first substrate in a plan view. The photodetector according to (13) or (14). (16) Among the two or more wiring layers, the area of ​​the light-shielding layer is larger than the area of ​​a wiring layer disposed in a layer different from the light-shielding layer. The photodetector according to (15). (17) The light-shielding layer has a solid pattern, a mesh pattern, or a slit pattern. The light detection element according to any one of (13) to (16). (17-1) The light-shielding layer is connected to a well region of the first substrate via a contact. The light detection element according to any one of (13) to (17). (17-2) The light-shielding layer is connected to the first well region of the first substrate and the second well region of the second substrate via separate contacts. The light detection element according to any one of (13) to (17). (17-3) A pixel group containing two or more pixels shares one floating diffusion. the light blocking layer is set to a predetermined potential via a contact arranged in the pixel group, with the pixel group as a unit; The light detection element according to any one of (13) to (17). (17-4) A pixel group containing two or more pixels shares one floating diffusion. the light-shielding layer is set to a predetermined potential via contacts arranged at ends of the first substrate and the second substrate; The light detection element according to any one of (13) to (17). (17-5) The two or more wiring layers have two or more of the light-shielding layers disposed in different layers of the interlayer insulating layer. The light detection element according to any one of (13) to (17). (17-6) The two or more light-shielding layers are set to the same potential. The photodetector according to (17-5). (17-7) At least one of the two or more light-shielding layers has a variable potential, When transferring charges to the floating diffusion of the first substrate, the two or more light-shielding layers are set to the same potential. The photodetector element according to (17-5). (18) A first substrate on which a photoelectric conversion element is disposed; a second substrate that is stacked on the first substrate and has at least a part of a pixel circuit that generates a pixel signal according to the charge output from the photoelectric conversion element disposed thereon; an interlayer insulating layer disposed between the first substrate and the second substrate and having one or more wiring layers; The wiring layer contains arsenic (As) and phosphorus (P). Light detection element. (19) The concentration of arsenic (As) in the wiring layer is higher than the concentration of phosphorus (P). The photodetector according to (18). (19-1) The first substrate is a floating diffusion to which accumulated charges of the photoelectric conversion element are transferred; a transfer transistor that switches whether or not to transfer the accumulated charge of the photoelectric conversion element to the floating diffusion; The one or more wiring layers include a first wiring layer connected to the floating diffusion; a second wiring layer connected to the transfer transistor; The first wiring layer and the second wiring layer have different impurity concentrations. The photodetector according to (18) or (19). (19-2) an arsenic (As) concentration in the first wiring layer is higher than an arsenic (As) concentration in the second wiring layer; The photodetector according to (19-1). (19-3) The phosphorus (P) concentration in the first wiring layer is lower than the phosphorus (P) concentration in the second wiring layer; The photodetector according to (19-1). (19-4) A concentration of arsenic (As) in each of the first wiring layer and the second wiring layer is higher than a concentration of phosphorus (P); The light detection element according to any one of (19-1) to (19-3). (19-5) The one or more wiring layers include a third wiring layer connected to a peripheral region disposed outside the pixel region, The first wiring layer and the third wiring layer have different impurity concentrations. The light detection element according to any one of (19-1) to (19-4). (19-6) The arsenic (As) concentration in the first wiring layer is higher than the arsenic (As) concentration in the third wiring layer; The photodetector according to (19-5). (19-7) A phosphorus (P) concentration in the first wiring layer is lower than a phosphorus (P) concentration in the third wiring layer; The photodetector according to (19-5). (19-8) A concentration of arsenic (As) in each of the first wiring layer and the third wiring layer is higher than a concentration of phosphorus (P); The light detection element according to any one of (19-5) to (19-7). (20) A first substrate on which a photoelectric conversion element is disposed; a second substrate that is stacked on the first substrate and has at least a part of a pixel circuit that generates a pixel signal according to the charge output from the photoelectric conversion element disposed thereon; an interlayer insulating layer disposed between the first substrate and the second substrate; The interlayer insulating layer is A wiring layer; a first contact extending from the wiring layer to the second substrate; an insulating layer disposed in a predetermined region including a connection portion of the wiring layer with the first contact; Light detection element. (21) The first contact is electrically insulated from the wiring layer. The photodetector according to (20). (22) The insulating layer includes two or more types of insulators having different dielectric constants. The photodetector according to (20) or (21). (23) The insulating layer includes an air space disposed to surround the first contact. The photodetector according to (22). (24) The insulating layer is a first insulating layer that is disposed so as to surround the first contact at a location closer to the first contact than the air layer, the first insulating layer including an insulator having a dielectric constant greater than that of the air layer; a second insulating layer that is disposed so as to surround the first contact at a location farther from the first contact than the air layer, and that includes an insulator having a dielectric constant greater than that of the air layer; The photodetector according to (23). (25) The insulating layer includes a low-k material. The photodetector according to (20) or (21). (26) A sidewall insulating layer is disposed along a sidewall surface of the first contact extending from the intermediate layer to the second substrate, the sidewall insulating layer including a low-k material. The light detection element according to any one of (21) to (25). (27) The wiring layer is disposed over the entire horizontal cross section of the interlayer insulating layer. The light detection element according to any one of (20) to (26). (28) The wiring layer is disposed in a partial region of a cross section of the interlayer insulating layer. The light detection element according to any one of (20) to (26). (29) The interlayer insulating layer has a second contact disposed apart from the first contact and extending from the wiring layer to the second substrate. The light detection element according to any one of (20) to (26). (30) The second contact is disposed so as to be electrically connected to the wiring layer and is set to a predetermined potential. The photodetector according to (29). (31) The wiring layer includes a metal material, a semiconductor material, or an organic material. The light detection element according to any one of (20) to (30). (32) The wiring layer includes polysilicon. The photodetector according to (31). (33) The interlayer insulating layer includes a silicon oxide film or a silicon nitride film. The light detection element according to any one of (1) to (32).

[0351] The aspects of the present disclosure are not limited to the above-mentioned individual embodiments, but include various modifications that may be conceived by a person skilled in the art, and the effects of the present disclosure are not limited to the above-mentioned contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0352] 1 photodetector element, 10 first substrate, 11 semiconductor substrate, 12 pixel, 15 charge retention portion, 15a first charge retention portion, 15b second charge retention portion, 16 wiring layer, 18 pixel transistor, 20 second substrate, 20a wiring layer, 20b contact, 20c silicon substrate, 20d well layer, 20f trench, 20g trench, 20h trench, 21 semiconductor substrate (chip), 21c contact, 22 pixel circuit, 23 pixel drive line, 24 vertical signal line, 25 gate, 27 side contact, 29 insulating layer, 30 third substrate, 31 semiconductor substrate, 32 logic circuit, 33 vertical drive circuit, 34 column signal processing circuit, 35 horizontal drive circuit, 36 system control circuit, 38 trench, 39 metal wiring, 40 color filter, 42 well layer, 43 element isolation portion, 43a Insulating layer, 43b Diffusion layer, 46 Insulating layer, 47 Resist layer, 50 Light receiving lens, 51 Interlayer insulating layer, 52 Insulating layer, 53 Insulating layer, 54 Through wiring, 55 Connection wiring, 56 Wiring layer, 57 Insulating layer, 58 Pad electrode, 59 Connection portion, 61 Interlayer insulating layer, 62 Wiring layer, 63 Insulating layer, 64 Pad electrode, 65 Opening, 66 Insulating layer, 66a First insulating layer, 66b Second insulating layer, 66s Sidewall insulating layer, 67 Air layer, 68 Resist layer, 69 Silicon oxide film, 70 Interlayer insulating layer (middle layer), 71 Wiring layer, 71a Wiring layer (first wiring layer), 71b Second wiring layer, 71c Third wiring layer, 71d Wiring layer, 71h Opening, 71p Polysilicon layer, 72 Through contact, 73 Contact, 73a first contact, 73b second contact, 73c third contact, 74 free area, 76 organic film, 77 resist layer, 82 NSG layer, 83 organic layer, 87 organic layer, 89 resist layer, 94 organic layer, 96 resist layer, 100 photodetector element

Claims

1. A first substrate on which a photoelectric conversion element is disposed; a second substrate that is stacked on the first substrate and has at least a part of a pixel circuit disposed thereon, the pixel circuit generating a pixel signal corresponding to the charge output from the photoelectric conversion element; an interlayer insulating layer disposed between the first substrate and the second substrate and having two or more stacked wiring layers; Light detection element.

2. The pixel circuit in the second substrate has a pixel transistor including at least one of an amplification transistor, a reset transistor, or a selection transistor. The photodetector element according to claim 1 .

3. The wiring layer is a polysilicon layer or a metal layer. The photodetector element according to claim 1 .

4. At least one of the type and concentration of impurity ions contained in the two or more wiring layers is different from each other. The photodetector element according to claim 1 .

5. At least a part of the two or more wiring layers is arranged to intersect when viewed in a plan view. The photodetector element according to claim 1 .

6. The two or more wiring layers include a floating diffusion to which charges generated in the photoelectric conversion element in the first substrate are transferred, a well region of a different conductivity type from the floating diffusion, a transfer transistor that switches whether or not to transfer charges generated in the photoelectric conversion element in the first substrate to the floating diffusion, or a plurality of wiring layers that are respectively connected to at least two of pixel boundary regions of the first substrate. The photodetector element according to claim 1 .

7. the two or more wiring layers include two or more wiring layers disposed in different layers of the interlayer insulating layer, and two or more wiring layers disposed in the same layer of the interlayer insulating layer; The photodetector element according to claim 6 .

8. The interlayer insulating layer is a plurality of first contacts each extending from at least a portion of the two or more wiring layers to the second substrate; a plurality of second contacts extending from the plurality of wiring layers to the first substrate; The photodetector element according to claim 6 .

9. the interlayer insulating layer has a charge storage section that stores charges transferred from the photoelectric conversion element separately from a floating diffusion; The charge storage unit is configured using two wiring layers that are arranged opposite to each other among the two or more wiring layers. The photodetector element according to claim 1 .

10. A conversion efficiency switching transistor is provided for switching the photoelectric conversion efficiency, the charge accumulation unit accumulates the charge transferred from the photoelectric conversion element when the conversion efficiency switching transistor is on. The light detection element according to claim 9.

11. a third contact extending from a wiring layer disposed closer to the second substrate, of the two wiring layers constituting the charge storage unit, to the second substrate; a wiring layer disposed closer to the second substrate and a source of the conversion efficiency switching transistor are electrically connected via the third contact; The light detection element according to claim 10.

12. a plurality of the conversion efficiency switching transistors capable of switching the photoelectric conversion efficiency in three or more stages and a plurality of the charge storage units are provided; the plurality of charge accumulation units are disposed on the interlayer insulating layer, or some of the plurality of charge accumulation units are disposed on the interlayer insulating layer and the remaining charge accumulation units are disposed on the second substrate; The light detection element according to claim 10.

13. At least one wiring layer among the two or more wiring layers is a light-shielding layer that blocks light that has passed through the photoelectric conversion element and blocks light from the second substrate. The photodetector element according to claim 1 .

14. The light-shielding layer is set to a predetermined reference potential. The light detection element according to claim 13.

15. Among the two or more wiring layers, the light-shielding layer and a wiring layer disposed in a layer different from the light-shielding layer are disposed so as to cover the entire area of ​​the first substrate in a plan view. The light detection element according to claim 13.

16. Among the two or more wiring layers, an area of ​​the light-shielding layer is larger than an area of ​​a wiring layer disposed in a layer different from the light-shielding layer. The light detection element according to claim 15.

17. The light-shielding layer has a solid pattern, a mesh pattern, or a slit pattern. The light detection element according to claim 13.

18. A first substrate on which a photoelectric conversion element is disposed; a second substrate that is stacked on the first substrate and has at least a part of a pixel circuit disposed thereon, the pixel circuit generating a pixel signal corresponding to the charge output from the photoelectric conversion element; an interlayer insulating layer disposed between the first substrate and the second substrate and having one or more wiring layers; The wiring layer contains arsenic (As) and phosphorus (P). Light detection element.

19. The concentration of arsenic (As) in the wiring layer is higher than the concentration of phosphorus (P); The light detection element according to claim 18.

20. A first substrate on which a photoelectric conversion element is disposed; a second substrate that is stacked on the first substrate and has at least a part of a pixel circuit disposed thereon, the pixel circuit generating a pixel signal corresponding to the charge output from the photoelectric conversion element; an interlayer insulating layer disposed between the first substrate and the second substrate; The interlayer insulating layer is A wiring layer; a first contact extending from the wiring layer to the second substrate; an insulating layer disposed in a predetermined region including a connection portion of the wiring layer with the first contact; Light detection element.

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