Liquid discharge device

Abstract

To provide a liquid discharge device capable of improving accuracy in discriminating the state of a print head.SOLUTION: Provided is a liquid discharge device comprising: a drive circuit that outputs a drive signal including a plurality of drive signal waveforms; a control circuit that outputs a discharge control signal; a first selecting circuit that selects a drive signal waveform on the basis of the discharge control signal and outputs it as a first drive voltage; a first discharge part that discharges liquid by driving of a first piezoelectric element driven by the first drive voltage; and a discharge count circuit to which the discharge control signal is inputted. The control circuit outputs the discharge control signal including selection rule data for setting a selection rule of the plurality of drive signal waveforms on the first selecting circuit, and first drive data for controlling the selection of the plurality of drive signal waveforms on the first selecting circuit on the basis of the selection rule data. The frequency of having the first piezoelectric element driven by the first drive voltage of a first drive voltage waveform outputted by the first selecting circuit is stored as a first drive frequency on the discharge count circuit.SELECTED DRAWING: Figure 25

Description

[Technical field]

[0001] The present invention relates to a liquid ejection device. [Background technology]

[0002] In recent years, from the viewpoint of reducing the environmental burden, so-called refurbished products have been attracting attention. These products are reconditioned from defective products or second-hand products, and are then reconditioned to a condition similar to that of an unused product, after which the products are redistributed on the market. Such refurbished products can reduce the amount of waste, and as a result, the environmental burden can be reduced. In response to this approach, in the case of liquid ejection devices such as inkjet printers, efforts are being made to recondition used print heads, recondition them to a condition similar to that of an unused product, and redistribute the products on the market as remanufactured machines.

[0003] For example, Patent Document 1 discloses a technique for improving the accuracy of determining the condition of a reused printhead by storing information about the usage history of the printhead in the printhead that ejects liquid. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2021-053864 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, from the perspective of further improving the accuracy of determining the condition of reused printheads, the technique described in Patent Document 1 alone is not sufficient, and there is room for improvement. [Means for solving the problem]

[0006] One aspect of the liquid ejection device according to the present invention is to A drive circuit that outputs a drive signal including a plurality of drive signal waveforms; A control circuit that outputs a discharge control signal; a first selection circuit that selects the plurality of drive signal waveforms based on the ejection control signal and outputs the selected waveform as a first drive voltage; a first ejection section including a first piezoelectric element that is driven by the first driving voltage and that ejects liquid by driving the first piezoelectric element; a discharge count circuit to which the discharge control signal is input; Equipped with the control circuit outputs the ejection control signal including selection rule data that sets a selection rule for the plurality of drive signal waveforms in the first selection circuit, and first drive data that controls selection of the plurality of drive signal waveforms in the first selection circuit based on the selection rule data; The ejection count circuit stores the number of times the first piezoelectric element is driven by the first drive voltage of the first drive voltage waveform output by the first selection circuit as a first drive count. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a schematic structure of a liquid ejection device. [Diagram 2] FIG. 2 is a diagram illustrating a functional configuration of the liquid ejection device. [Diagram 3] FIG. 2 is a diagram for explaining a schematic configuration of a discharge unit. [Figure 4] FIG. 4 is a diagram illustrating an example of a configuration of a drive signal selection circuit. [Diagram 5] 5A to 5C are diagrams for explaining specific examples of a latch signal, a change signal, a clock signal, and a head control signal. [Figure 6] 5 is a diagram showing an example of a data configuration of a head control signal. FIG. [Figure 7] FIG. 4 illustrates an example of a functional configuration of a selection control circuit; [Figure 8] 11 is a diagram showing an example of decoded contents of a decoder included in a selection signal output unit; FIG. [Figure 9] FIG. 4 is a diagram showing an example of the configuration of a selection circuit corresponding to a discharge unit. [Figure 10] 6A and 6B are diagrams illustrating an example of signal waveforms of drive signals in a high-speed print mode. [Figure 11] FIG. 11 is a diagram showing an example of a head control signal in a high-speed printing mode. [Figure 12] FIG. 13 is a diagram showing the decoded contents of a decoder in a high-speed print mode. [Figure 13] 6A and 6B are diagrams for explaining the operation of the drive signal selection circuit in a high-speed print mode. [Figure 14] 10A and 10B are diagrams illustrating an example of signal waveforms of drive signals in a high-definition printing mode. [Figure 15] FIG. 11 is a diagram showing an example of a head control signal in a high-definition printing mode. [Figure 16] FIG. 13 is a diagram showing the decoded contents of a decoder in a high-definition printing mode. [Figure 17] 11 is a diagram for explaining the operation of the drive signal selection circuit in a high-definition printing mode. FIG. [Figure 18] FIG. 11 is a diagram showing an example of a head control signal in a first flushing mode. [Figure 19] FIG. 13 is a diagram showing the decoded contents of a decoder in a first flushing mode. [Figure 20] 6A to 6C are diagrams for explaining the operation of the drive signal selection circuit in the first flushing mode. [Figure 21] FIG. 11 is a diagram showing an example of a head control signal in a second flushing mode. [Figure 22] FIG. 13 is a diagram showing the decoded contents of the decoder in the second flushing mode. [Diagram 23] 10A and 10B are diagrams for explaining the operation of the drive signal selection circuit in the second flushing mode. [Figure 24] FIG. 4 is a diagram illustrating an example of a configuration of a discharge count circuit. [Diagram 25] 2 is a diagram illustrating a storage area of ​​a storage circuit; FIG. [Figure 26] FIG. 11 is a diagram illustrating an example of the operation of a count circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings are used for the convenience of explanation. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0009] Furthermore, the liquid ejection device according to the present invention is a printing device that ejects ink as a liquid, and will be described using an inkjet printer as an example; however, the liquid ejection device is not limited to inkjet printers, and may be, for example, a color material ejection device used in the manufacture of color filters for liquid crystal displays and the like, an electrode material ejection device used in the formation of electrodes for organic electroluminescence displays, surface-emitting displays and the like, a bioorganic matter ejection device used in the manufacture of biochips, etc.

[0010] 1. Overview of the liquid ejection device 1 is a diagram showing a schematic structure of a liquid ejection device 1. The liquid ejection device 1 in this embodiment is a so-called line printing type inkjet printer that transports a medium P along a transport direction and ejects ink, which is an example of a liquid, onto the transported medium P using print heads 21-1 to 21-7 arranged in a row along a main scanning direction intersecting the transport direction, thereby forming an image on the medium P. Such a liquid ejection device 1 can use any printing target, such as printing paper, a resin film, or a fabric, as the medium P. Note that the liquid ejection device 1 is not limited to a line printing type inkjet printer, and may also be a serial printing type inkjet printer.

[0011] As shown in FIG. 1, the liquid ejection device 1 includes an ink container 5, a control mechanism 10, an ejection mechanism 20, and a transport mechanism 40.

[0012] The ink container 5 stores ink of a plurality of colors to be ejected onto the medium P. Examples of the colors of ink stored in the ink container 5 include black k, cyan c, magenta m, and yellow y. As the ink container 5, an ink cartridge, a bag-shaped ink pack formed of a flexible film, an ink tank that can be refilled with ink, and the like can be used.

[0013] The control mechanism 10 includes a processing circuit such as a CPU (Central Processing Unit) or an FPGA (Field Programmable Gate Array), and a storage circuit such as a semiconductor memory. The control mechanism 10 controls each element of the liquid ejection device 1 including the ejection mechanism 20.

[0014] The ejection mechanism 20 has print heads 21-1 to 21-7. The print heads 21-1 to 21-7 are arranged in a staggered pattern in the order of print head 21-1, print head 21-2, print head 21-3, print head 21-4, print head 21-5, print head 21-6, and print head 21-7 along a scanning direction that intersects with the transport direction in which the medium P is transported.

[0015] The ejection mechanism 20 receives the control signal Ctrl-H, drive signal COM, and reference voltage signal VBS output by the control mechanism 10. The control signal Ctrl-H, drive signal COM, and reference voltage signal VBS are input to each of the print heads 21-1 to 21-7. Ink stored in the ink container 5 is supplied to each of the print heads 21-1 to 21-7 via a tube or the like (not shown). Each of the print heads 21-1 to 21-7 ejects ink supplied from the ink container 5 based on the input control signal Ctrl-H, drive signal COM, and reference voltage signal VBS.

[0016] The transport mechanism 40 includes a transport motor 41 and a transport roller 42. The transport motor 41 is driven to rotate based on a control signal Ctrl-T input from the control mechanism 10. The transport roller 42 rotates in accordance with the rotational drive of the transport motor 41. As the transport roller 42 rotates, the medium P is transported in the transport direction.

[0017] As described above, in the liquid ejection device 1 of this embodiment, the control mechanism 10 controls the transportation of the medium P and the ejection of ink from the ejection mechanism 20. That is, the ejection mechanism 20 ejects ink at a timing linked to the transportation of the medium P by the transport mechanism 40. As a result, the ink ejected from the ejection mechanism 20 lands at a desired position on the medium P. As a result, a desired image is formed on the medium P.

[0018] 2. Functional configuration of the liquid ejection device Next, a description will be given of the functional configuration of the liquid ejection device 1. Fig. 2 is a diagram showing the functional configuration of the liquid ejection device 1. As shown in Fig. 2, the liquid ejection device 1 includes a control mechanism 10, an ejection mechanism 20, and a transport mechanism 40.

[0019] The control mechanism 10 includes a drive circuit 50 , a reference voltage circuit 52 , and a control circuit 100 .

[0020] The control circuit 100 includes a processor such as a microcontroller, and is communicatively connected to an external device such as a host computer (not shown) that is provided outside the liquid ejection device 1. An image information signal including image data to be formed on the medium P is input from the external device to the control circuit 100. The control circuit 100 performs predetermined image processing on the input image information signal to generate various data for controlling the liquid ejection device 1 and signals corresponding to the data, and outputs the data to corresponding components.

[0021] The control circuit 100 generates a control signal Ctrl-T for controlling the transport of the medium P, and outputs it to the transport mechanism 40. This causes the transport motor 41 of the transport mechanism 40 to rotate, controlling the transport along the transport direction of the medium P. Here, the control signal Ctrl-T output by the control circuit 100 may be converted into a signal by a driver circuit (not shown), and then input to the transport motor 41.

[0022] Furthermore, the control circuit 100 generates a latch signal LAT, a change signal CH, a clock signal SCK, and head control signals DI1 to DI7 as control signals Ctrl-H for controlling the emission mechanism 20 based on the input image information signal, and outputs them to the emission mechanism 20. That is, the control circuit 100 outputs the head control signals DI1 to DI7. The latch signal LAT, the change signal CH, the clock signal SCK, and the head control signals DI1 to DI7 will be described in detail later.

[0023] The control circuit 100 also outputs a basic drive signal dA, which is a digital signal, to the drive circuit 50. The drive circuit 50 converts the basic drive signal dA, which is an input digital signal, into a digital / analog signal, and then generates a drive signal COM including one or more signal waveforms by D-class amplifying the converted analog signal. Then, the drive circuit 50 outputs the generated drive signal COM to the discharge mechanism 20. That is, the drive circuit 50 outputs a drive signal COM including multiple signal waveforms. Here, the basic drive signal dA is a digital signal for defining the signal waveform of the drive signal COM, and the drive circuit 50 generates the drive signal COM by D-class amplifying the signal waveform defined by the basic drive signal dA. Therefore, the basic drive signal dA may be an analog signal as long as it can define the signal waveform of the drive signal COM. Also, the drive circuit 50 only needs to amplify the signal waveform defined by the basic drive signal dA and output it as the drive signal COM. Therefore, the drive circuit 50 may generate the drive signal COM by amplifying the signal waveform defined by the basic drive signal dA through class A amplification, class B amplification, or class AB amplification.

[0024] The reference voltage circuit 52 generates a reference voltage signal VBS that serves as a reference potential for driving a piezoelectric element 60 (described later) of the emission mechanism 20. Then, the reference voltage circuit 52 outputs the generated reference voltage signal VBS to the emission mechanism 20. Such a reference voltage signal VBS is a signal with a constant voltage value, and may be, for example, a signal with a ground potential value of 0V, or a DC voltage signal with a voltage value of 5.5V, 6V, or the like.

[0025] The emission mechanism 20 has print heads 21-1 to 21-7 and an emission count circuit 300. Furthermore, the print head 21-i (i is any of 1 to 7) includes a drive signal selection circuit 200 and emission units 600[1] to 600[n].

[0026] The drive signal selection circuit 200 is configured to include one or more integrated circuit devices. The latch signal LAT, the change signal CH, the clock signal SCK, the head control signal DIi, and the drive signal COM are input to the drive signal selection circuit 200. The drive signal selection circuit 200 generates and outputs drive voltages VOUT[1] to VOUT[n] that individually correspond to each of the ejection sections 600[1] to 600[n] by selecting or not selecting the signal waveform of the drive signal COM based on the input latch signal LAT, the change signal CH, the clock signal SCK, and the head control signal DIi. The configuration and operation of the drive signal selection circuit 200 will be described in detail later.

[0027] Here, the print heads 21-1 to 21-7 are all similarly configured, and may be referred to as print head 21 when there is no need to distinguish them. In this case, the description will be made on the assumption that a head control signal DI is input to the print head 21 as head control signals DI1 to DI7. Also, the ejection units 600[1] to 600[n] of the print head 21 are all similarly configured, and may be referred to simply as ejection unit 600 when there is no need to distinguish them. In this case, the description will be made on the assumption that a drive voltage VOUT is supplied to the ejection units 600 as drive voltages VOUT[1] to VOUT[n].

[0028] Here, a configuration of the discharge unit 600 to which the driving voltage VOUT is supplied will be described. Fig. 3 is a diagram for explaining a schematic configuration of the discharge unit 600. In addition to the discharge unit 600, a nozzle plate 632, a reservoir 641, and a supply port 661 are also illustrated in Fig. 3.

[0029] As shown in FIG. 3, the ejection section 600 includes a piezoelectric element 60, a vibration plate 621, a cavity 631, and a nozzle 651. The piezoelectric element 60 includes a piezoelectric body 601 and electrodes 611 and 612. The electrodes 611 and 612 are positioned so as to sandwich the piezoelectric body 601, thereby forming the piezoelectric element 60. The piezoelectric element 60 is driven so that the central portion is displaced in the vertical direction in response to the potential difference between the voltage supplied to the electrode 611 and the voltage supplied to the electrode 612. Specifically, the electrode 611 is supplied with a drive voltage VOUT based on the drive signal COM, and the electrode 612 is supplied with a reference voltage signal VBS. When the voltage value of the drive voltage VOUT supplied to the electrode 611 changes, the potential difference between the drive voltage VOUT supplied to the electrode 611 and the reference voltage signal VBS supplied to the electrode 612 changes. As a result, the piezoelectric element 60 is driven so that the central portion is displaced in the vertical direction.

[0030] The diaphragm 621 is located below the piezoelectric element 60 in Fig. 3. In other words, the piezoelectric element 60 is formed on the upper surface of the diaphragm 621 in Fig. 3. Such a diaphragm 621 is displaced in the vertical direction as the piezoelectric element 60 is driven in the vertical direction.

[0031] A cavity 631 is located below the vibration plate 621 in FIG. 3. Ink is supplied to the cavity 631 from a reservoir 641. In addition, ink stored in an ink container 5 is introduced into the reservoir 641 via a supply port 661. That is, the inside of the cavity 631 is filled with ink stored in the ink container 5. The internal volume of such a cavity 631 expands or contracts with the vertical displacement of the vibration plate 621. That is, the vibration plate 621 functions as a diaphragm that changes the internal volume of the cavity 631, and the cavity 631 functions as a pressure chamber in which the pressure changes with the vertical displacement of the vibration plate 621.

[0032] The nozzle 651 is an opening provided in the nozzle plate 632, and communicates with the cavity 631. When the internal volume of the cavity 631 changes, ink filled inside the cavity 631 is ejected from the nozzle 651 in accordance with the change in the internal volume.

[0033] In the ejection section 600 configured as above, when the piezoelectric element 60 is driven to bend upward, the vibration plate 621 is displaced upward. This causes the internal volume of the cavity 631 to expand, and as a result, the ink stored in the reservoir 641 is drawn into the cavity 631. On the other hand, when the piezoelectric element 60 is driven to bend downward, the vibration plate 621 is displaced downward. This causes the internal volume of the cavity 631 to shrink, and as a result, an amount of ink according to the degree of shrinkage of the internal volume of the cavity 631 is ejected from the nozzle 651.

[0034] That is, the ejection unit 600[1] includes a piezoelectric element 60 driven by a driving voltage VOUT[1] and ejects ink by driving the piezoelectric element 60, and the ejection unit 600[2] includes a piezoelectric element 60 driven by a driving voltage VOUT[2] and ejects ink by driving the piezoelectric element 60.

[0035] Note that the piezoelectric element 60 is not limited to the structure shown in FIG. 3 as long as it is driven by being supplied with a drive voltage VOUT corresponding to the drive signal COM and is capable of ejecting ink from the nozzle 651 by being driven.

[0036] Returning to FIG. 2, head control signals DI1 to DI7 are input to the discharge count circuit 300. Based on the input head control signal DIi, the discharge count circuit 300 counts the number of times the piezoelectric element 60 is driven in association with the discharge of ink, which is the number of times the ink is discharged from each of the discharge units 600[1] to 600[n] of the print head 21-i. Then, the discharge count circuit 300 stores the counted number of times the ink is discharged from each of the discharge units 600[1] to 600[n]. That is, based on the input head control signals DI1 to DI7, the discharge count circuit 300 counts the number of times the piezoelectric element 60 included in each of the discharge units 600[1] to 600[n] of the print heads 21-1 to 21-7 is driven, and stores the counted number of times. The configuration and operation of the discharge count circuit 300 will be described in detail later.

[0037] 3. Drive signal selection circuit configuration Next, we will explain the configuration of the drive signal selection circuit 200. Fig. 4 is a diagram showing an example of the configuration of the drive signal selection circuit 200. As shown in Fig. 4, the drive signal selection circuit 200 has a selection control circuit 210 and selection circuits 230[1] to 230[n].

[0038] A clock signal SCK, a latch signal LAT, a change signal CH, and a head control signal DI are input to the selection control circuit 210. The selection control circuit 210 generates selection signals S[1] to S[n] based on the input clock signal SCK, latch signal LAT, change signal CH, and head control signal DI, and outputs them to the corresponding selection circuits 230[1] to 230[n].

[0039] The selection circuits 230[1] to 230[n] are provided corresponding to the discharge units 600[1] to 600[n], respectively. The selection circuits 230[1] to 230[n] receive the drive signal COM and the corresponding selection signals S[1] to S[n], respectively. The selection circuits 230[1] to 230[n] select or deselect the drive signal COM based on the input selection signals S[1] to S[n], respectively, to generate the corresponding drive voltages VOUT[1] to VOUT[n] and output them to the corresponding discharge units 600[1] to 600[n].

[0040] Specifically, the selection signal S[j] output by the selection control circuit 210 and the drive signal COM are input to the selection circuit 230[j] (j is any of 1 to n). The selection circuit 230[j] then selects or deselects the drive signal COM based on the selection signal S[j] to generate the drive voltage VOUT[j] and outputs it to the discharge section 600[j].

[0041] Here, the selection circuits 230[1] to 230[n] all have the same configuration, and when there is no need to distinguish between them, they may be simply referred to as the selection circuit 230. The selection circuit 230 is provided corresponding to the discharge unit 600 among the discharge units 600[1] to 600[n], and the selection circuit 230 is described as receiving the selection signal S among the selection signals S[1] to S[n].

[0042] The following describes the details of the configuration of the drive signal selection circuit 200 configured as above. First, the following describes the details of the configuration of the selection control circuit 210 included in the drive signal selection circuit 200. Here, in describing the detailed configuration of the selection control circuit 210, specific examples of the latch signal LAT, change signal CH, clock signal SCK, and head control signal DI input to the selection control circuit 210 will be described.

[0043] FIG. 5 is a diagram for explaining specific examples of the latch signal LAT, the change signal CH, the clock signal SCK, and the head control signal DI.

[0044] 5, the latch signal LAT is a pulse signal output by the control circuit 100 for each latch period Plat. The latch signal LAT is generated by the control circuit 100 in response to the transport position of the transported medium P, and is output to the drive signal selection circuit 200.

[0045] The change signal CH is a pulse signal that divides the latch cycle Plat into m periods p1 to pm. The control circuit 100 determines the number of divisions of the latch cycle Plat according to the operation mode of the liquid ejection device 1 described later and the signal waveform included in the drive signal COM output by the drive circuit 50, and outputs the change signal CH to the drive signal selection circuit 200. Here, in the liquid ejection device 1 of this embodiment, the control circuit 100 outputs a maximum of three change signals CH in the latch cycle Plat. That is, in this embodiment, the control circuit 100 divides the latch cycle Plat into a maximum of four periods p1 to p4. Note that the maximum number of divisions of the latch cycle Plat is not limited to four, and may be five or more or three or less.

[0046] The head control signal DI is a signal synchronized with the clock signal SCK, and includes an ejection information signal SI and a setting information signal SP in serial. The ejection information signal SI defines the amount of ink ejected from the nozzles 651 of each of the ejection sections 600[1] to 600[n]. The setting information signal SP defines the relationship between the amount of ink ejected and the ejection information signal SI during periods p1 to pm defined by the latch signal LAT and the change signal CH. The head control signal DI is generated by the control circuit 100 based on image data input from an external device, and is output every latch period Plat.

[0047] That is, in the liquid ejection device 1 of this embodiment, the latch period Plat is defined by the latch signal LAT based on the transport position of the medium P, the change signal CH is used to divide the latch period Plat into a plurality of periods p1 to pm, and the head control signal DI defines the amount of ink ejected in each of the periods p1 to pm defined by the latch signal LAT and the change signal CH. As a result, dots of a size defined by the head control signal DI are formed on the medium P for each latch period Plat. That is, the latch period Plat for forming dots of a size defined by the head control signal DI on the medium P corresponds to the dot formation period in the liquid ejection device 1.

[0048] Here, a specific example of the head control signal DI including the ejection information signal SI and the setting information signal SP will be described. Fig. 6 is a diagram showing an example of the data configuration of the head control signal DI. As shown in Fig. 6, the head control signal DI includes the ejection information signal SI and the setting information signal SP in serial.

[0049] The ejection information signal SI includes, in series, upper order ejection data SIH1 to SIHn and lower order ejection data SIL1 to SILn for individually defining the amount of ink ejected from the nozzles 651 of each of the ejection sections 600[1] to 600[n].

[0050] In detail, the discharge information signal SI includes upper discharge data SIH1 corresponding to the discharge section 600[1], upper discharge data SIH2 corresponding to the discharge section 600[2], ..., upper discharge data SIHn-1 corresponding to the discharge section 600[n-1], and upper discharge data SIHn corresponding to the discharge section 600[n], in the order of upper discharge data SIHn, SIHn-1, ..., SIH2, SIH1. Also, the discharge information signal SI includes lower discharge data SIL1 corresponding to the discharge section 600[1], lower discharge data SIL2 corresponding to the discharge section 600[2], ..., lower discharge data SILn-1 corresponding to the discharge section 600[n-1], and lower discharge data SILn corresponding to the discharge section 600[n], in the order of lower discharge data SILn, SILn-1, ..., SIL2, SIL1.

[0051] In this case, the upper ejection data SIHn, SIHn-1, ..., SIH2, SIH1 and the lower ejection data SILn, SILn-1, ..., SIL2, SIL1 are serially included in the ejection information signal SI in the order of the upper ejection data SIHn, SIHn-1, ..., SIH2, SIH1, and the lower ejection data SILn, SILn-1, ..., SIL2, SIL1. In other words, the ejection information signal SI includes a maximum of 2n bits of data.

[0052] In this case, the amount of ink ejected from the nozzle 651 corresponding to the ejection unit 600[j] is determined by two bits, the upper ejection data SIHj and the lower ejection data SILj. In this case, the upper ejection data SIHj and the lower ejection data SILj may be collectively referred to as the ejection data SIdj[SIHj, SILj].

[0053] In the following description, the ejection unit 600 corresponds to the upper ejection data SIH and the lower ejection data SIL. That is, the ejection amount of ink ejected from the ejection unit 600 is defined by two bits, the upper ejection data SIH and the lower ejection data SIL. In this case, the upper ejection data SIH and the lower ejection data SIL may be collectively referred to as the ejection data SId[SIH, SIL].

[0054] The setting information signal SP includes information that defines the relationship between the ejection information signal SI during each of the periods p1 to pm and the amount of ink ejected from the nozzle 651. Specifically, the setting information signal SP defines the relationship between the combination of logical levels of the ejection data SId[SIH, SIL] included in the ejection information signal SI and the logical level of the selection signal S input to the corresponding selection circuit 230.

[0055] In detail, the setting information signal SP includes setting data PA00 to PA03 that define the relationship between the logical level of the selection signal S in the period p1 and the combination of the logical levels of the ejection data SId [SIH, SIL], which is the drive pattern of the piezoelectric element 60 of the ejection section 600 in the period p1, and setting data PA10 to PA13 that define the relationship between the logical level of the selection signal S in the period p2 and the combination of the logical levels of the ejection data SId [SIH, SIL], which is the drive pattern of the piezoelectric element 60 of the ejection section 600 in the period p2. A13 includes setting data PA20 to PA23 which specify the drive pattern of the piezoelectric element 60 of the ejection section 600 during period p3 and which specifies the relationship between the logical level of the selection signal S during period p3 and the combination of the logical levels of the ejection data SId[SIH, SIL], and setting data PA30 to PA33 which specify the drive pattern of the piezoelectric element 60 of the ejection section 600 during period p4 and which specifies the relationship between the logical level of the selection signal S during period p4 and the combination of the logical levels of the ejection data SId[SIH, SIL].

[0056] Such setting data PA00-PA03, PA10-PA13, PA20-PA23, PA30-PA33 are serially included in the setting information signal SP in the following order: setting data PA33, PA32, PA31, PA30, PA23, PA22, PA21, PA20, PA13, PA12, PA11, PA10, PA03, PA02, PA01, PA00. Here, the setting information signal SP in this embodiment will be described as including 16-bit data of setting data PA00-PA03, PA10-PA13, PA20-PA23, PA30-PA33, but the amount of data included in the setting information signal SP is not limited to 16 bits.

[0057] As described above, the selection control circuit 210 receives the latch signal LAT that defines the latch period Plat corresponding to the dot formation period, the change signal CH that divides the latch period Plat into periods p1 to pm, the ejection information signal SI that individually defines the amount of ink ejected from each of the n nozzles 651 onto the medium P in each of the periods p1 to pm, and the head control signal DI that serially includes the setting information signal SP for defining the relationship between the ejection information signal SI and the drive pattern of the piezoelectric element 60, and the clock signal SCK that propagates the head control signal DI. The selection control circuit 210 generates selection signals S[1] to S[n] corresponding to each of the ejection sections 600[1] to 600[n] based on the input latch signal LAT, change signal CH, clock signal SCK, and head control signal DI, and outputs them to the corresponding selection circuits 230[1] to 230[n].

[0058] Next, a specific example of the configuration of the selection control circuit 210 will be described. Fig. 7 is a diagram showing an example of the functional configuration of the selection control circuit 210. As shown in Fig. 7, the selection control circuit 210 has a control logic circuit 260 and selection signal output units 270[1] to 270[n] provided corresponding to the discharge units 600[1] to 600[n]. The selection control circuit 210 generates and outputs selection signals S[1] to S[n] corresponding to the discharge units 600[1] to 600[n], respectively, based on the head control signal DI during each of periods p1 to p4 defined by the latch signal LAT and the change signal CH.

[0059] The control logic circuit 260 includes a group of SP registers 262 and a selection control signal generation unit 264 .

[0060] The SP register group 262 includes a plurality of registers connected in series. The head control signal DI is input to the SP register group 262 in synchronization with the clock signal SCK. The SP register group 262 propagates the head control signal DI to the subsequent registers in sequence in synchronization with the clock signal SCK. In other words, the SP register group 262 includes a so-called shift register.

[0061] Then, when the supply of the clock signal SCK stops, the setting data PA33-PA30, PA23-PA20, PA13-PA10, and PA03-PA00 included in the setting information signal SP of the head control signal DI are held in the SP register group 262. The selection control signal generator 264 latches the setting data PA33-PA30, PA23-PA20, PA13-PA10, and PA03-PA00 held in the SP register group 262 all at once at the rising edge of the latch signal LAT, and generates and outputs setting signals Q1-Q4 based on the latched setting data PA33-PA30, PA23-PA20, PA13-PA10, and PA03-PA00.

[0062] Specifically, the selection control signal generation unit 264 generates a setting signal Q1 including setting data PA00 to PA03, a setting signal Q2 including setting data PA10 to PA13, a setting signal Q3 including setting data PA20 to PA23, and a setting signal Q4 including setting data PA30 to PA33, and outputs them to the decoders 226 included in each of the selection signal output units 270[1] to 270[n].

[0063] The setting signal Q1 defines the relationship between the combination of the logic levels of the ejection data SId[SIH, SIL] in the period p1 and the logic level of the selection signal S based on the setting data PA00 to PA03. The setting signal Q2 defines the relationship between the combination of the logic levels of the ejection data SId[SIH, SIL] in the period p2 and the logic level of the selection signal S based on the setting data PA10 to PA13. The setting signal Q3 defines the relationship between the combination of the logic levels of the ejection data SId[SIH, SIL] in the period p3 and the logic level of the selection signal S based on the setting data PA20 to PA23. The setting signal Q4 defines the relationship between the combination of the logic levels of the ejection data SId[SIH, SIL] in the period p4 and the logic level of the selection signal S based on the setting data PA30 to PA33.

[0064] In the following description, setting signal Q1 including setting data PA00 to PA03 may be referred to as setting signal Q1 [PA00, PA01, PA02, PA03], setting signal Q2 including setting data PA10 to PA13 may be referred to as setting signal Q2 [PA10, PA11, PA12, PA13], setting signal Q3 including setting data PA20 to PA23 may be referred to as setting signal Q3 [PA20, PA21, PA22, PA23], and setting signal Q4 including setting data PA30 to PA33 may be referred to as setting signal Q4 [PA30, PA31, PA32, PA33].

[0065] Each of the selection signal output units 270[1] to 270[n] includes a first register 222a, a second register 222b, a first latch circuit 224a, a second latch circuit 224b, and a decoder 226. In the following description, when there is no need to distinguish between the selection signal output units 270[1] to 270[n], they may be simply referred to as the selection signal output unit 270. In this case, the description will be given assuming that the selection signal output unit 270 is provided in correspondence with the discharge unit 600.

[0066] The second register 222b included in the selection signal output unit 270[1] is connected to the rear stage of the SP register group 262. The second register 222b included in the selection signal output unit 270[2] is connected to the rear stage of the second register 222b included in the selection signal output unit 270[1]. The second register 222b included in the selection signal output unit 270[j] is connected to the rear stage of the second register 222b included in the selection signal output unit 270[j-1].

[0067] Also, the first register 222a included in the selection signal output unit 270[1] is connected to the rear stage of the second register 222b included in the selection signal output unit 270[n]. The first register 222a included in the selection signal output unit 270[2] is connected to the rear stage of the first register 222a included in the selection signal output unit 270[1]. The first register 222a included in the selection signal output unit 270[j] is connected to the rear stage of the first register 222a included in the selection signal output unit 270[j-1]. And the first register 222a included in the selection signal output unit 270[n] is connected to the rear stage of the first register 222a included in the selection signal output unit 270[n-1].

[0068] That is, the second registers 222b owned by each of the selection signal output units 270[1] to 270[n] are connected in series in the order of the second register 222b owned by the selection signal output unit 270[1], the second register 222b owned by the selection signal output unit 270[2], ..., the second register 222b owned by the selection signal output unit 270[n], and the first registers 222a owned by each of the selection signal output units 270[1] to 270[n] are connected in series in the order of the first register 222a owned by the selection signal output unit 270[1], the first register 222a owned by the selection signal output unit 270[2], ..., the first register 222a owned by the selection signal output unit 270[n]. In the selection control circuit 210, the multiple registers connected in series included in the SP register group 262, the second register 222b owned by each of the serially connected selection signal output units 270[1] to 270[n], and the first register 222a owned by each of the serially connected selection signal output units 270[1] to 270[n] are connected in series in the following order: the multiple registers connected in series included in the SP register group 262, the second register 222b owned by each of the serially connected selection signal output units 270[1] to 270[n], and the first register 222a owned by each of the serially connected selection signal output units 270[1] to 270[n]. That is, the multiple registers included in the SP register group 262, the second registers 222b included in each of the selection signal output units 270[1] to 270[n], and the first registers 222a included in each of the selection signal output units 270[1] to 270[n] configure a shift register. As a result, the head control signal DI input to the selection control circuit 210 is propagated in synchronization with the clock signal SCK through the SP register group 262, the n second registers 222b included in each of the selection signal output units 270[1] to 270[n], and the n first registers 222a included in each of the selection signal output units 270[1] to 270[n] in that order.

[0069] Thereafter, the supply of the clock signal SCK is stopped, so that the second register 222b included in the selection signal output unit 270 holds the lower ejection data SIL corresponding to the ejection unit 600, and the first register 222a included in the selection signal output unit 270 holds the upper ejection data SIH corresponding to the ejection unit 600.

[0070] Then, at the rising edge of the latch signal LAT, the upper ejection data SIH held in the first register 222a of the selection signal output section 270 is latched by the first latch circuit 224a of the selection signal output section 270, and the lower ejection data SIL held in the second register 222b of the selection signal output section 270 is latched by the second latch circuit 224b of the selection signal output section 270. The first latch circuit 224a of the selection signal output section 270 outputs the latched upper ejection data SIH as latch data LTa to the decoder 226 of the selection signal output section 270, and the second latch circuit 224b of the selection signal output section 270 outputs the latched lower ejection data SIL as latch data LTb to the decoder 226 of the selection signal output section 270.

[0071] Here, in the following explanation, the latch data LTaj and latch data LTbj input to the decoder 226 of the selection signal output unit 270[j] may be collectively referred to as latch data LTdj[LTaj, LTbj], and the latch data LTa and latch data LTb input to the decoder 226 of the selection signal output unit 270 may be collectively referred to as latch data LTd[LTa, LTb].

[0072] The decoder 226 of the selection signal output unit 270 receives the setting signal Q1 [PA00, PA01, PA02, PA03], setting signal Q2 [PA10, PA11, PA12, PA13], setting signal Q3 [PA20, PA21, PA22, PA23], setting signal Q4 [PA30, PA31, PA32, PA33], and latch data LTd [LTa, LTb] corresponding to the ejection data SId [SIH, SIL] output from the selection control signal generation unit 264. The decoder 226 of the selection signal output unit 270 generates a selection signal S by decoding the latch data LTd [LTa, LTb] based on the setting signals Q1 to Q4, and outputs the selection signal S to the selection circuit 230.

[0073] 8 is a diagram showing an example of the decoded contents of the decoder 226 of the selection signal output unit 270. As shown in FIG. 8, the decoder 226 of the selection signal output unit 270 outputs a selection signal S obtained by decoding the latch data LTd[LTa, LTb] based on the setting signal Q1[PA00, PA01, PA02, PA03] during a period p1, outputs a selection signal S obtained by decoding the latch data LTd[LTa, LTb] based on the setting signal Q2[PA10, PA11, PA12, PA13] during a period p2, outputs a selection signal S obtained by decoding the latch data LTd[LTa, LTb] based on the setting signal Q3[PA20, PA21, PA22, PA23] during a period p3, and outputs a selection signal S obtained by decode the latch data LTd[LTa, LTb] based on the setting signal Q4[PA30, PA31, PA32, PA33] during a period p4.

[0074] Specifically, for example, when latch data LTd[LTa,LTb]=[0,1] corresponding to ejection data SId[SIH,SIL]=[0,1] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 decodes the latch data LTd[LTa,LTb]=[0,1] to output a selection signal S of a logic level defined by the setting data PA01 in the period p1, output a selection signal S of a logic level defined by the setting data PA11 in the period p2, output a selection signal S of a logic level defined by the setting data PA21 in the period p3, and output a selection signal S of a logic level defined by the setting data PA31 in the period p4. That is, the decoded contents of the decoder 226 of the selection signal output unit 270 are defined by the setting signals Q1 to Q4 output by the selection control signal generation unit 264.

[0075] Next, a description will be given of the configuration of the selection circuits 230[1] to 230[n] to which the selection signals S[1] to S[n] are respectively input. Fig. 9 is a diagram showing an example of the configuration of the selection circuit 230 corresponding to the discharge section 600. As shown in Fig. 9, the selection circuit 230 has an inverter INV, which is a NOT circuit, and a transfer gate TG.

[0076] The selection signal S output by the selection control circuit 210 is input to a positive control terminal not marked with a circle in the transfer gate TG, and is also input to a negative control terminal marked with a circle in the transfer gate TG after its logical level is inverted by an inverter INV. A drive signal COM is also supplied to the input terminal of the transfer gate TG.

[0077] When an H-level selection signal S is input to such a selection circuit 230, the transfer gate TG makes the input terminal and the output terminal conductive, and when an L-level selection signal S is input, the transfer gate TG makes the input terminal and the output terminal non-conductive. That is, when an H-level selection signal S is input, the selection circuit 230 outputs the drive signal COM supplied to the input terminal of the transfer gate TG as the drive voltage VOUT from the output terminal, and when an L-level selection signal S is input, the selection circuit 230 does not output the drive signal COM supplied to the input terminal of the transfer gate TG as the drive voltage VOUT from the output terminal. That is, the selection circuit 230 switches whether or not to output the drive signal COM as the drive voltage VOUT depending on the logical level of the input selection signal S.

[0078] In the drive signal selection circuit 200 configured as described above, the selection control circuit 210 generates selection signals S[1] to S[n] corresponding to each of the selection circuits 230[1] to 230[n] individually based on the head control signal DI during each of the periods p1 to p4 defined by the latch signal LAT and the change signal CH, and outputs them to the corresponding selection circuits 230[1] to 230[n]. The selection circuits 230[1] to 230[n] switch whether or not to output the drive signal COM as the drive voltages VOUT[1] to VOUT[n] during each of the periods p1 to p4, depending on the logical levels of the input selection signals S[1] to S[n].

[0079] That is, the drive signal selection circuit 200 includes a selection circuit 230[1] that selects a signal waveform included in the drive signal COM based on the head control signal DI and outputs it as a drive voltage VOUT[1], and a selection circuit 230[2] that selects a signal waveform included in the drive signal COM based on the head control signal DI and outputs it as a drive voltage VOUT[2]. The control circuit 100 outputs a head control signal DI that includes a setting information signal SP that sets the selection rules for the signal waveform of the drive signal COM in the selection circuits 230[1] to 230[n], ejection data SId1[SIH1, SIL1] that controls the selection of the signal waveform included in the drive signal COM in the selection circuit 230[1] based on the setting information signal SP, and ejection data SId2[SIH2, SIL2] that controls the selection of the signal waveform included in the drive signal COM in the selection circuit 230[2] based on the setting information signal SP.

[0080] 4. Operation Mode of Liquid Ejector The liquid ejection device 1 of the present embodiment configured as described above has a high-speed printing mode and a high-definition printing mode as operation modes for forming an image on the medium P. The high-speed printing mode is an operation mode for the purpose of forming an image on the medium P at high speed, and can form an image on the medium P at a higher speed than the high-definition printing mode. The high-definition printing mode is an operation mode for the purpose of forming a high-definition image on the medium P, and can form dots with a higher number of gradations on the medium P than the high-speed printing mode. That is, in the high-speed printing mode, the gradation of the dots formed on the medium P by the ink ejected by the ejection unit 600[1] of the print head 21-i is different from the gradation of the dots formed on the medium P by the ink ejected by the ejection unit 600[1] of the print head 21-i in the high-definition mode. Note that whether the liquid ejection device 1 operates in the high-speed printing mode or the high-definition printing mode may be determined by the selection of the user of the liquid ejection device 1, and may be selected according to the material of the medium P on which the ink is ejected and the type of ink to be ejected.

[0081] In addition, the liquid ejection device 1 of this embodiment has an operating mode for performing maintenance processing, and has a flushing mode for performing a flushing operation in which the ink stored in the ejection section 600 is ejected simultaneously from the multiple ejection sections 600 in order to reduce the risk of the ink drying out or thickening.The flushing mode has a first flushing mode and a second flushing mode in which the amount of ink ejected from the multiple ejection sections 600 differs.

[0082] Here, specific examples of the operation of the drive signal selection circuit 200 in each of the high-speed printing mode, the high-resolution printing mode, the first flushing mode, and the second flushing mode will be described. In the following description, when explaining the logical levels of various data, the bit data of an H-level signal may be referred to as "1" and the bit data of an L-level signal may be referred to as "0".

[0083] 4.1 Fast mode An example of the operation of the liquid ejection device 1 when the operating mode of the liquid ejection device 1 is the high-speed print mode will be described.

[0084] Fig. 10 is a diagram showing an example of a signal waveform of the drive signal COM in the high-speed print mode. In the following description, the drive signal COM output by the drive circuit 50 in the high-speed print mode may be referred to as the drive signal ComA. As shown in Fig. 10, the drive signal ComA includes a signal waveform in which a drive waveform Adp1 arranged in a period p1 and a drive waveform Adp2 arranged in a period p2 are consecutive. That is, the drive circuit 50 outputs the drive signal COM including a plurality of signal waveforms, and in the high-speed print mode, the drive circuit 50 outputs the drive signal ComA including the drive waveforms Adp1 and Adp2 as the drive signal COM as a plurality of signal waveforms.

[0085] The drive waveform Adp1 is a signal waveform that, when supplied to the electrode 611 of the piezoelectric element 60, causes a predetermined amount of ink to be ejected from the nozzle 651 corresponding to the piezoelectric element 60. The drive waveform Adp2 is a signal waveform that, when supplied to the electrode 611 of the piezoelectric element 60, causes an amount of ink less than a predetermined amount to be ejected from the nozzle 651 corresponding to the piezoelectric element 60. In the drive signal ComA, the drive waveforms Adp1 and Adp2 each start and end at voltage Vc. In other words, the drive waveforms Adp1 and Adp2 are signal waveforms that have a common voltage value of Vc at both the start and end timings.

[0086] As described above, the drive signal ComA in the high-speed print mode includes the drive waveforms Adp1 and Adp2 arranged in the periods p1 to p2. Therefore, the control circuit 100 outputs a change signal CH that divides the latch period Plat into two so that each of the drive waveforms Adp1 and Adp2 arranged in the periods p1 to p2 can be selected.

[0087] In the following description, the amount of ink ejected from the nozzle 651 when the driving waveform Adp1 is supplied to the electrode 611 may be referred to as a large amount, and the amount of ink ejected from the nozzle 651 when the driving waveform Adp2 is supplied to the electrode 611 may be referred to as a small amount.

[0088] In the high-speed printing mode, the drive signal selection circuit 200 generates drive voltages VOUT[1] to VOUT[n] by selecting or deselecting each of the drive waveforms Adp1, Adp2 included in the drive signal ComA based on the head control signal DI during each of the periods p1 to p2 defined by the latch signal LAT and the change signal CH, and outputs them to the corresponding ejection sections 600[1] to 600[n].

[0089] FIG. 11 is a diagram showing an example of the head control signal DI in the high-speed print mode.

[0090] As described above, the ejection information signal SI included in the head control signal DI defines the amount of ink ejected from the nozzles 651 of each of the ejection sections 600[1] to 600[n]. Therefore, the logical level of the ejection information signal SI in the high-speed printing mode changes appropriately according to the amount of ink ejected from the corresponding nozzle 651 during the period in which the liquid ejection device 1 is executing so-called printing control for ejecting ink onto the medium P.

[0091] On the other hand, the setting information signal SP included in the head control signal DI in the high-speed printing mode changes depending on the operating mode, and in the high-speed printing mode, as shown in FIG. 11, serially includes “0” as setting data PA33, “0” as setting data PA32, “0” as setting data PA31, “0” as setting data PA30, “0” as setting data PA23, “0” as setting data PA22, “0” as setting data PA21, “0” as setting data PA20, “0” as setting data PA13, “1” as setting data PA12, “0” as setting data PA11, “0” as setting data PA10, “1” as setting data PA03, “0” as setting data PA02, “0” as setting data PA01, and “0” as setting data PA00.

[0092] That is, when the operating mode of the liquid ejector 1 is the high-speed print mode, the head control signal DI includes a 16-bit setting information signal SP whose logical level is "0000 0000 0100 1000". Here, in the following description, the setting information signal SP included in the head control signal DI when the operating mode of the liquid ejector 1 is the high-speed print mode may be referred to as 0x0048 in hexadecimal notation. In other words, in the high-speed print mode, the control circuit 100 outputs the head control signal DI including the setting information signal SP of 0x0048 that specifies the selection rule for the drive waveforms Adp1, Adp2 in the selection circuit 230[1] as the setting information signal SP.

[0093] The head control signal DI including the setting information signal SP described above is input to the drive signal selection circuit 200. The setting information signals SP input to the drive signal selection circuit 200 are held in an SP register group 262, and then latched all at once by the selection control signal generation unit 264 at the rising edge of the latch signal LAT. Then, the selection control signal generation unit 264 generates setting signal Q1[PA00, PA01, PA02, PA03]=[0,0,0,1], setting signal Q2[PA10, PA11, PA12, PA13]=[0,0,1,0], setting signal Q3[PA20, PA21, PA22, PA23]=[0,0,0,0], and setting signal Q4[PA30, PA31, PA32, PA33]=[0,0,0,0] from the latched setting information signal SP, and outputs them to the decoders 226 included in each of the selection signal output units 270[1] to 270[n].

[0094] 12 is a diagram showing the decoded contents of the decoder 226 in the high-speed print mode. The decoder 226 of the selection signal output unit 270 outputs a selection signal S of a predetermined logic level by decoding the latch data LTd[LTa, LTb] corresponding to the input ejection data SId[SIH, SIL] with the contents shown in FIG. 12. For example, when the latch data LTd[LTa, LTb]=[1,0] corresponding to the ejection data SId[SIH, SIL]=[1,0] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 outputs a selection signal S of L level in period p1, outputs a selection signal S of H level in period p2, outputs a selection signal S of L level in period p3, and outputs a selection signal S of L level in period p4.

[0095] 13 is a diagram for explaining the operation of the drive signal selection circuit 200 in the high-speed print mode. The head control signal DI input to the drive signal selection circuit 200 is synchronized with the clock signal SCK and sequentially propagates through multiple registers included in the SP register group 262, the second registers 222b of each of the selection signal output units 270[1] to 270[n], and the first registers 222a.

[0096] Then, when the supply of the clock signal SCK stops, the setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, and PA03 to PA00 are held in multiple registers included in the SP register group 262, the lower ejection data SIL1 to SILn are held in the corresponding second registers 222b, and the upper ejection data SIH1 to SIHn are held in the corresponding first registers 222a.

[0097] Then, at the rising edge of the latch signal LAT, the setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, and PA03 to PA00 held in multiple registers included in the SP register group 262 are latched simultaneously by the selection control signal generating unit 264, the lower ejection data SIL1 to SILn held in the second registers 222b of each of the selection signal output units 270[1] to 270[n] are latched simultaneously by the corresponding second latch circuits 224b, and the upper ejection data SIH1 to SIHn held in the first registers 222a of each of the selection signal output units 270[1] to 270[n] are latched simultaneously by the corresponding first latch circuits 224a.

[0098] The selection control signal generating unit 264 generates setting signals Q1-Q4 from the latched setting data PA33-PA30, PA23-PA20, PA13-PA10, and PA03-PA00, and outputs them to the decoders 226 of the selection signal output units 270[1]-270[n]. The second latch circuits 224b of the selection signal output units 270[1]-270[n] output the lower ejection data SIL1-SILn latched by each of them as latch data LTb1-LTbn to the corresponding decoders 226, and the first latch circuits 224a of the selection signal output units 270[1]-270[n] output the upper ejection data SIH1-SIHn latched by each of them as latch data LTa1-LTan to the corresponding decoders 226.

[0099] That is, the decoder 226 of the selection signal output unit 270 receives the setting signal Q1 [PA00, PA01, PA02, PA03] = [0, 0, 0, 1], the setting signal Q2 [PA10, PA11, PA12, PA13] = [0, 0, 1, 0], the setting signal Q3 [PA20, PA21, PA22, PA23] = [0, 0, 0, 0], the setting signal Q4 [PA30, PA31, PA32, PA33] = [0, 0, 0, 0], and the latch data LTd [LTa, LTb]. That is, the decoder 226 of the selection signal output unit 270 decodes the inputted latch data LTd [LTa, LTb] as shown in FIG.

[0100] Specifically, when the ejection data SId[SIH,SIL]=[0,0] and the latch data LTd[LTa,LTb]=[0,0] is input to the decoder 226, the decoder 226 outputs a selection signal S of L level in period p1, and outputs a selection signal S of L level in period p2. Therefore, the input terminal and the output terminal of the corresponding selection circuit 230 are controlled to be non-conductive in period p1, and are controlled to be non-conductive in period p2. As a result, the drive signal selection circuit 200 outputs a drive voltage VOUT that is constant at voltage Vc in period p1 and constant at voltage Vc in period p2. At this time, ink is not ejected from the nozzle 651 of the corresponding ejection section 600.

[0101] In the case where the ejection data SId[SIH,SIL]=[0,1] and the latch data LTd[LTa,LTb]=[0,1] is input to the decoder 226, the decoder 226 outputs a selection signal S of L level in period p1, and outputs a selection signal S of L level in period p2. Therefore, the input terminal and the output terminal of the corresponding selection circuit 230 are controlled to be non-conductive in period p1, and are controlled to be non-conductive in period p2. As a result, the drive signal selection circuit 200 outputs a drive voltage VOUT that is constant at voltage Vc in period p1 and constant at voltage Vc in period p2. At this time, ink is not ejected from the nozzle 651 of the corresponding ejection section 600.

[0102] In the case where the discharge data SId[SIH,SIL]=[1,0] is input to the decoder 226, the decoder 226 outputs a selection signal S of L level in period p1 and outputs a selection signal S of H level in period p2. Therefore, the input terminal and the output terminal of the corresponding selection circuit 230 are controlled to be non-conductive in period p1 and to be conductive in period p2. As a result, the drive signal selection circuit 200 outputs a drive voltage VOUT that is constant at voltage Vc in period p1 and has a drive waveform Adp2 in period p2. At this time, a small amount of ink is discharged from the nozzle 651 of the corresponding discharge section 600. Here, in the following description, in the high-speed print mode, the signal waveform of the drive voltage VOUT output by the drive signal selection circuit 200 when the discharge data SId[SIH,SIL]=[1,0] is input may be referred to as a drive voltage waveform Asd.

[0103] In the case of ejection data SId[SIH,SIL]=[1,1], when latch data LTd[LTa,LTb]=[1,1] is input to the decoder 226, the decoder 226 outputs a selection signal S of H level in period p1, and outputs a selection signal S of L level in period p2. Therefore, the input terminal and the output terminal of the corresponding selection circuit 230 are controlled to be conductive in period p1, and are controlled to be non-conductive in period p2. As a result, the drive signal selection circuit 200 outputs a drive voltage VOUT that becomes a drive waveform Adp1 in period p1 and is constant at a voltage Vc in period p2. At this time, a large amount of ink is ejected from the nozzle 651 of the corresponding ejection unit 600. Here, in the following description, in the high-speed print mode, the signal waveform of the drive voltage VOUT output by the drive signal selection circuit 200 when ejection data SId[SIH,SIL]=[1,0] is input may be referred to as a drive voltage waveform Ald.

[0104] As described above, when the operating mode is the high-speed printing mode, the liquid ejection device 1 forms on the medium P, during the latch period Plat consisting of periods p1 and p2, large dots corresponding to a large amount of ink, small dots corresponding to a small amount of ink, and three-level dots that are not printed by not ejecting ink.

[0105] 4.2 High-resolution print mode Next, an example of the operation of the liquid ejection device 1 when the operating mode of the liquid ejection device 1 is the high-resolution printing mode will be described.

[0106] Fig. 14 is a diagram showing an example of a signal waveform of the drive signal COM in the high-definition printing mode. In the following description, the drive signal COM output by the drive circuit 50 in the high-definition printing mode may be referred to as the drive signal ComB. As shown in Fig. 14, the drive signal ComB includes a signal waveform in which a drive waveform Bdp1 arranged in a period p1, a drive waveform Bdp2 arranged in a period p2, and a drive waveform Bdp3 arranged in a period p3 are successively arranged.

[0107] That is, the drive circuit 50 outputs a drive signal COM including a plurality of signal waveforms, and in the high-definition printing mode, the drive circuit 50 outputs as the drive signal COM a drive signal ComB including drive waveforms Bdp1, Bdp2, and Bdp3 as the plurality of signal waveforms.

[0108] The driving waveform Bdp1 is a signal waveform that, when supplied to the electrode 611 of the piezoelectric element 60, causes a larger amount of ink to be ejected from the nozzle 651 corresponding to the piezoelectric element 60 than a predetermined amount. The driving waveform Bdp2 is a signal waveform that, when supplied to the electrode 611 of the piezoelectric element 60, causes a larger amount of ink to be ejected from the nozzle 651 corresponding to the piezoelectric element 60. The driving waveform Bdp3 is a signal waveform that, when supplied to the electrode 611 of the piezoelectric element 60, causes a smaller amount of ink to be ejected from the nozzle 651 corresponding to the piezoelectric element 60 than a predetermined amount. In the driving signal ComB, each of the driving waveforms Bdp1, Bdp2, and Bdp3 starts and ends at the voltage Vc. That is, the driving waveforms Bdp1, Bdp2, and Bdp3 are signal waveforms that have a common voltage value of Vc at the start timing and end timing.

[0109] As described above, the drive signal ComB in the high-definition print mode includes the drive waveforms Bdp1, Bdp2, and Bdp3 arranged in the periods p1 to p3. Therefore, the control circuit 100 outputs a change signal CH that divides the latch period Plat into three so that each of the drive waveforms Bdp1, Bdp2, and Bdp3 arranged in the periods p1 to p3 can be selected.

[0110] In the following description, the amount of ink ejected from nozzle 651 when drive waveform Bdp1 is supplied to electrode 611 may be referred to as a large amount, the amount of ink ejected from nozzle 651 when drive waveform Bdp2 is supplied to electrode 611 may be referred to as a medium amount, and the amount of ink ejected from nozzle 651 when drive waveform Bdp3 is supplied to electrode 611 may be referred to as a small amount.

[0111] Note that a predetermined amount of ink ejected from the nozzle 651 corresponding to the piezoelectric element 60 when the drive waveform Bdp2 is supplied to the electrode 611 of the piezoelectric element 60 may be the same as or different from a predetermined amount of ink ejected from the nozzle 651 corresponding to the piezoelectric element 60 when the above-mentioned drive waveform Adp1 is supplied to the electrode 611 of the piezoelectric element 60. Also, the large amount ejected in the high-speed printing mode and the large amount ejected in the high-definition printing mode may be the same as or different from each other, and similarly, the small amount ejected in the high-speed printing mode and the small amount ejected in the high-definition printing mode may be the same as or different from each other.

[0112] Here, as shown in FIG. 10, the driving signal ComA output by the driving circuit 50 in the high-speed printing mode includes two signal waveforms, Adp1 and Adp2, which are arranged in the periods p1 to p2 defined by the latch signal LAT and the change signal CH, whereas as shown in FIG. 14, the driving signal ComB output by the driving circuit 50 in the high-definition printing mode includes three signal waveforms, Bdp1, Bdp2, and Bdp3, which are arranged in the periods p1 to p3 defined by the latch signal LAT and the change signal CH. As a result, in the high-speed printing mode, the latch period Plat can be shortened, and the dot formation period in which dots are formed on the medium P can be shortened. As a result, in the high-speed printing mode, high-speed image formation on the medium P can be realized. On the other hand, in the high-definition printing mode, since the latch period Plat includes three signal waveforms, Bdp1, Bdp2, and Bdp3, which have different ink ejection amounts, multi-tone dots can be formed on the medium P compared to the high-speed printing mode. As a result, in the high definition printing mode, high definition image formation on the medium P can be realized.

[0113] In addition, the signal waveforms contained in the drive signal ComA and the signal waveforms contained in the drive signal ComB are not limited to the examples shown in Figures 10 and 14, and any signal waveform can be used depending on the type of ink to be ejected, the material of the medium P, etc.

[0114] In the high-definition printing mode, the drive signal selection circuit 200 generates drive voltages VOUT[1] to VOUT[n] by selecting or deselecting each of the drive waveforms Bdp1, Bdp2, and Bdp3 included in the drive signal ComB based on the head control signal DI during each of the periods p1 to p3 defined by the latch signal LAT and the change signal CH, and outputs them to the corresponding ejection sections 600[1] to 600[n].

[0115] FIG. 15 is a diagram showing an example of the head control signal DI in the high-resolution printing mode.

[0116] As described above, the ejection information signal SI included in the head control signal DI defines the amount of ink ejected from the nozzles 651 of each of the ejection sections 600[1] to 600[n]. Therefore, the logical level of the ejection information signal SI in the high-definition printing mode changes appropriately according to the amount of ink ejected from the corresponding nozzle 651 during the period in which the liquid ejection device 1 is executing so-called printing control for ejecting ink onto the medium P.

[0117] On the other hand, the setting information signal SP included in the head control signal DI in the high-definition printing mode changes depending on the operation mode, and is different from the setting information signal SP included in the head control signal DI in the high-speed printing mode. Specifically, in the high-definition printing mode, as shown in Fig. 15, "0" as the setting data PA33, "0" as the setting data PA32, "0" as the setting data PA31, "0" as the setting data PA30, "0" as the setting data PA23, "0" as the setting data PA22, "1" as the setting data PA21, "0" as the setting data PA20, "0" as the setting data PA13, "1" as the setting data PA12, "0" as the setting data PA11, "0" as the setting data PA10, "1" as the setting data PA03, "0" as the setting data PA02, "0" as the setting data PA01, and "0" as the setting data PA00 are serially included.

[0118] That is, when the operating mode of the liquid ejector 1 is the high-definition printing mode, the head control signal DI includes a 16-bit setting information signal SP whose logical level is "0000 0010 0100 1000". Here, in the following description, the setting information signal SP included in the head control signal DI when the operating mode of the liquid ejector 1 is the high-definition printing mode may be referred to as 0x0248 in hexadecimal notation. In other words, in the high-definition printing mode, the control circuit 100 outputs, as the setting information signal SP, a head control signal DI including a setting information signal SP of 0x0248 that specifies the selection rules for the drive waveforms Bdp1, Bdp2, and Bdp3 in the selection circuit 230[1].

[0119] The head control signal DI including the setting information signal SP described above is input to the drive signal selection circuit 200. The setting information signals SP input to the drive signal selection circuit 200 are held in an SP register group 262, and then latched all at once by the selection control signal generation unit 264 at the rising edge of the latch signal LAT. Then, the selection control signal generation unit 264 generates setting signal Q1[PA00, PA01, PA02, PA03]=[0,0,0,1], setting signal Q2[PA10, PA11, PA12, PA13]=[0,0,1,0], setting signal Q3[PA20, PA21, PA22, PA23]=[0,1,0,0], and setting signal Q4[PA30, PA31, PA32, PA33]=[0,0,0,0] from the latched setting information signal SP, and outputs them to the decoders 226 included in each of the selection signal output units 270[1] to 270[n].

[0120] 16 is a diagram showing the decoded contents of the decoder 226 in the high-definition printing mode. The decoder 226 of the selection signal output unit 270 outputs a selection signal S of a predetermined logic level by decoding the latch data LTd[LTa, LTb] corresponding to the input ejection data SId[SIH, SIL] with the contents shown in FIG. 16. For example, when the latch data LTd[LTa, LTb]=[1,0] corresponding to the ejection data SId[SIH, SIL]=[1,0] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 outputs the selection signal S of L level in period p1, outputs the selection signal S of H level in period p2, outputs the selection signal S of L level in period p3, and outputs the selection signal S of L level in period p4.

[0121] 17 is a diagram for explaining the operation of the drive signal selection circuit 200 in the high-resolution print mode. The head control signal DI input to the drive signal selection circuit 200 is synchronized with the clock signal SCK and sequentially propagates through a plurality of registers included in the SP register group 262, the second registers 222b of each of the selection signal output units 270[1] to 270[n], and the first registers 222a.

[0122] Then, when the supply of the clock signal SCK stops, the setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, and PA03 to PA00 are held in multiple registers included in the SP register group 262, the lower ejection data SIL1 to SILn are held in the corresponding second registers 222b, and the upper ejection data SIH1 to SIHn are held in the corresponding first registers 222a.

[0123] Thereafter, at the rising edge of the latch signal LAT, the setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, and PA03 to PA00 held in a plurality of registers included in the SP register group 262 are latched simultaneously by the selection control signal generating unit 264, the lower ejection data SIL1 to SILn held in the second registers 222b of each of the selection signal output units 270[1] to 270[n] are latched simultaneously by the corresponding second latch circuits 224b, and the upper ejection data SIH1 to SIHn held in the first registers 222a of each of the selection signal output units 270[1] to 270[n] are latched simultaneously by the corresponding first latch circuits 224a.

[0124] The selection control signal generating unit 264 generates setting signals Q1-Q4 from the latched setting data PA33-PA30, PA23-PA20, PA13-PA10, and PA03-PA00, and outputs them to the decoders 226 of the selection signal output units 270[1]-270[n]. The second latch circuits 224b of the selection signal output units 270[1]-270[n] output the lower ejection data SIL1-SILn latched by each of them as latch data LTb1-LTbn to the corresponding decoders 226, and the first latch circuits 224a of the selection signal output units 270[1]-270[n] output the upper ejection data SIH1-SIHn latched by each of them as latch data LTa1-LTan to the corresponding decoders 226.

[0125] That is, the decoder 226 of the selection signal output unit 270 receives the setting signal Q1 [PA00, PA01, PA02, PA03] = [0, 0, 0, 1], the setting signal Q2 [PA10, PA11, PA12, PA13] = [0, 0, 1, 0], the setting signal Q3 [PA20, PA21, PA22, PA23] = [0, 1, 0, 0], the setting signal Q4 [PA30, PA31, PA32, PA33] = [0, 0, 0, 0], and the latch data LTd [LTa, LTb]. That is, the decoder 226 of the selection signal output unit 270 decodes the inputted latch data LTd [LTa, LTb] as shown in FIG.

[0126] Specifically, in the case where the discharge data SId[SIH,SIL]=[0,0] and the latch data LTd[LTa,LTb]=[0,0] is input to the decoder 226, the decoder 226 outputs a selection signal S of L level in period p1, outputs a selection signal S of L level in period p2, and outputs a selection signal S of L level in period p3. Therefore, the input terminal and the output terminal of the corresponding selection circuit 230 are controlled to be non-conductive in period p1, controlled to be non-conductive in period p2, and controlled to be non-conductive in period p3. As a result, the drive signal selection circuit 200 outputs a drive voltage VOUT that is constant at voltage Vc in period p1, constant at voltage Vc in period p2, and constant at voltage Vc in period p3. At this time, ink is not discharged from the nozzle 651 of the corresponding discharge section 600.

[0127] In the case where the discharge data SId[SIH,SIL]=[0,1] and the latch data LTd[LTa,LTb]=[0,1] is input to the decoder 226, the decoder 226 outputs a selection signal S of L level in period p1, outputs a selection signal S of L level in period p2, and outputs a selection signal S of H level in period p3. Therefore, the input terminal and the output terminal of the corresponding selection circuit 230 are controlled to be non-conductive in period p1, controlled to be non-conductive in period p2, and controlled to be conductive in period p3. As a result, the drive signal selection circuit 200 outputs a drive voltage VOUT that is constant at voltage Vc in period p1, constant at voltage Vc in period p2, and has a drive waveform Bdp3 in period p3. At this time, a small amount of ink is discharged from the nozzle 651 of the corresponding discharge section 600. Here, in the following description, in high-resolution printing mode, the signal waveform of the drive voltage VOUT output by the drive signal selection circuit 200 when the ejection data SId[SIH, SIL]=[0, 1] is input may be referred to as the drive voltage waveform Bsd.

[0128] In the case where the discharge data SId[SIH,SIL]=[1,0] and the latch data LTd[LTa,LTb]=[1,0] is input to the decoder 226, the decoder 226 outputs a selection signal S of L level in period p1, outputs a selection signal S of H level in period p2, and outputs a selection signal S of L level in period p3. Therefore, the input terminal and the output terminal of the corresponding selection circuit 230 are controlled to be non-conductive in period p1, controlled to be conductive in period p2, and controlled to be non-conductive in period p3. As a result, the drive signal selection circuit 200 outputs a drive voltage VOUT that is constant at voltage Vc in period p1, has a drive waveform Bdp2 in period p2, and is constant at voltage Vc in period p3. At this time, a medium amount of ink is discharged from the nozzle 651 of the corresponding discharge section 600. Here, in the following description, in high-resolution printing mode, the signal waveform of the drive voltage VOUT output by the drive signal selection circuit 200 when the ejection data SId[SIH, SIL]=[1, 0] is input may be referred to as the drive voltage waveform Bmd.

[0129] In the case where the discharge data SId[SIH,SIL]=[1,1] and the latch data LTd[LTa,LTb]=[1,1] is input to the decoder 226, the decoder 226 outputs a selection signal S of H level in period p1, outputs a selection signal S of L level in period p2, and outputs a selection signal S of L level in period p3. Therefore, the input terminal and the output terminal of the corresponding selection circuit 230 are controlled to be conductive in period p1, controlled to be non-conductive in period p2, and controlled to be non-conductive in period p3. As a result, the drive signal selection circuit 200 outputs a drive voltage VOUT that becomes a drive waveform Adp1 in period p1, is constant at voltage Vc in period p2, and is constant at voltage Vc in period p3. At this time, a large amount of ink is discharged from the nozzle 651 of the corresponding discharge section 600. Here, in the following description, in high-resolution printing mode, the signal waveform of the drive voltage VOUT output by the drive signal selection circuit 200 when the ejection data SId[SIH, SIL]=[1, 1] is input may be referred to as the drive voltage waveform Bld.

[0130] As described above, when the operating mode is the high-resolution printing mode, the liquid ejection device 1 forms on the medium P, during the latch cycle Plat consisting of periods p1, p2, and p3, large dots corresponding to a large amount of ink, medium dots corresponding to a medium amount of ink, small dots corresponding to a small amount of ink, and four levels of dots that are not printed by not ejecting ink.

[0131] 4.3 First flushing mode Next, an example of the operation of the liquid ejection device 1 when the operation mode is a flushing mode, which is one of the maintenance processes, will be described. As described above, the liquid ejection device 1 of this embodiment has a first flushing mode and a second flushing mode in which the ejection amount of ink ejected from the multiple ejection units 600 is different as flushing modes for performing maintenance of the liquid ejection device 1. In the liquid ejection device 1 of this embodiment, the flushing mode when the drive signal COM output by the drive circuit 50 is the drive signal ComA corresponds to the first flushing mode, and the flushing mode when the drive signal COM output by the drive circuit 50 is the drive signal ComB corresponds to the second flushing mode. Such first and second flushing modes may be selected depending on, for example, whether the printing mode is a high-speed printing mode or a high-definition printing mode, or may be selected depending on the physical properties of the ink ejected from the ejection units 600 or the state of the ejection units 600 that perform the flushing operation. In addition, during the first flushing mode and the second flushing mode, the drive signal COM output by the drive circuit 50 is not limited to the drive signals ComA and ComB. For example, the drive circuit 50 may output a drive signal COM having a signal waveform dedicated to the flushing mode.

[0132] FIG. 18 is a diagram showing an example of the head control signal DI in the first flushing mode.

[0133] As shown in FIG. 18, in the first flushing mode, the setting information signal SP included in the head control signal DI serially includes “0” as setting data PA33, “0” as setting data PA32, “0” as setting data PA31, “0” as setting data PA30, “0” as setting data PA23, “0” as setting data PA22, “0” as setting data PA21, “0” as setting data PA20, “1” as setting data PA13, “0” as setting data PA12, “1” as setting data PA11, “0” as setting data PA10, “0” as setting data PA03, “0” as setting data PA02, “0” as setting data PA01, and “0” as setting data PA00.

[0134] That is, when the liquid ejection device 1 is in the first flushing mode, the head control signal DI includes a 16-bit setting information signal SP whose logical level is "0000 0000 1010 0000". Here, in the following description, the setting information signal SP included in the head control signal DI when the operating mode of the liquid ejection device 1 is the first flushing mode may be referred to as 0x00A0 in hexadecimal notation. In other words, in the first flushing mode in which a flushing operation is performed in which a predetermined amount of ink is ejected from the multiple ejection units 600 including the ejection unit 600[1], the control circuit 100 outputs the head control signal DI including the setting information signal SP of 0x00A0 corresponding to the flushing operation in which a predetermined amount of ink is ejected as the setting information signal SP.

[0135] The head control signal DI including the setting information signal SP described above is input to the drive signal selection circuit 200. The setting information signals SP input to the drive signal selection circuit 200 are held in an SP register group 262, and then latched all at once by the selection control signal generation unit 264 at the rising edge of the latch signal LAT. Then, the selection control signal generation unit 264 generates setting signal Q1[PA00, PA01, PA02, PA03]=[0,0,0,0], setting signal Q2[PA10, PA11, PA12, PA13]=[0,1,0,1], setting signal Q3[PA20, PA21, PA22, PA23]=[0,0,0,0], and setting signal Q4[PA30, PA31, PA32, PA33]=[0,0,0,0] from the latched setting information signal SP, and outputs them to the decoders 226 included in each of the selection signal output units 270[1] to 270[n].

[0136] 19 is a diagram showing the decoded contents of the decoder 226 in the first flushing mode. The decoder 226 of the selection signal output unit 270 outputs a selection signal S of a predetermined logic level by decoding the latch data LTd[LTa, LTb] corresponding to the input discharge data SId[SIH, SIL] with the contents shown in FIG. 19. For example, when the latch data LTd[LTa, LTb]=[0,1] corresponding to the discharge data SId[SIH, SIL]=[0,1] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 outputs the selection signal S of L level in period p1, outputs the selection signal S of H level in period p2, outputs the selection signal S of L level in period p3, and outputs the selection signal S of L level in period p4.

[0137] Here, as shown in FIG. 19, in the first flushing mode, the decoder 226 outputs the selection signal S of the same logic level in each of the periods p1 to p4 when the latch data LTd[LTa, LTb]=[0,0] is input and when the latch data LTd[LTa, LTb]=[1,0] is input, and outputs the selection signal S of the same logic level in each of the periods p1 to p4 when the latch data LTd[LTa, LTb]=[0,1] is input and when the latch data LTd[LTa, LTb]=[1,1] is input. That is, in the first flushing mode, the selection control circuit 210 outputs the selection signal S of the same logic level regardless of the upper ejection data SIH1 to SIHn. Therefore, the control circuit 100 may output the head control signal DI including the setting information signal SP and the lower ejection data SIL1 to SILn. In other words, the higher-order ejection data SIH1-SIHn may not be included in the head control signal DI output by the control circuit 100. This reduces the number of bits of the head control signal DI, and as a result, the processing load on the control circuit 100 is reduced.

[0138] In the following explanation, the latch data LTd[LTa,LTb]=[0,0] and the latch data LTd[LTa,LTb]=[1,0] may be collectively referred to as the latch data LTd[LTa,LTb]=[*,0], and the latch data LTd[LTa,LTb]=[1,0] and the latch data LTd[LTa,LTb]=[1,1] may be collectively referred to as the latch data LTd[LTa,LTb]=[*,1]. Similarly, the ejection data SId[SIH,SIL]=[0,0] and the ejection data SId[SIH,SIL]=[1,0] may be collectively referred to as the ejection data SId[SIH,SIL]=[*,0], and the ejection data SId[SIH,SIL]=[1,0] and the ejection data SId[SIH,SIL]=[1,1] may be collectively referred to as the ejection data SId[SIH,SIL]=[*,0].

[0139] 20 is a diagram for explaining the operation of the drive signal selection circuit 200 in the first flushing mode. The head control signal DI input to the drive signal selection circuit 200 is synchronized with the clock signal SCK and sequentially propagates through multiple registers included in the SP register group 262, the second registers 222b of each of the selection signal output units 270[1] to 270[n], and the first registers 222a.

[0140] Then, when the supply of the clock signal SCK stops, the setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, and PA03 to PA00 are held in multiple registers included in the SP register group 262, the lower ejection data SIL1 to SILn are held in the corresponding second registers 222b, and the upper ejection data SIH1 to SIHn are held in the corresponding first registers 222a.

[0141] Thereafter, at the rising edge of the latch signal LAT, the setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, and PA03 to PA00 held in a plurality of registers included in the SP register group 262 are latched simultaneously by the selection control signal generating unit 264, the lower ejection data SIL1 to SILn held in the second registers 222b of each of the selection signal output units 270[1] to 270[n] are latched simultaneously by the corresponding second latch circuits 224b, and the upper ejection data SIH1 to SIHn held in the first registers 222a of each of the selection signal output units 270[1] to 270[n] are latched simultaneously by the corresponding first latch circuits 224a.

[0142] The selection control signal generating unit 264 generates setting signals Q1-Q4 from the latched setting data PA33-PA30, PA23-PA20, PA13-PA10, and PA03-PA00, and outputs them to the decoders 226 of the selection signal output units 270[1]-270[n]. The second latch circuits 224b of the selection signal output units 270[1]-270[n] output the lower ejection data SIL1-SILn latched by each of them as latch data LTb1-LTbn to the corresponding decoders 226, and the first latch circuits 224a of the selection signal output units 270[1]-270[n] output the upper ejection data SIH1-SIHn latched by each of them as latch data LTa1-LTan to the corresponding decoders 226.

[0143] That is, the decoder 226 of the selection signal output unit 270 receives the setting signal Q1 [PA00, PA01, PA02, PA03] = [0, 0, 0, 0], the setting signal Q2 [PA10, PA11, PA12, PA13] = [0, 1, 0, 1], the setting signal Q3 [PA20, PA21, PA22, PA23] = [0, 0, 0, 0], the setting signal Q4 [PA30, PA31, PA32, PA33] = [0, 0, 0, 0], and the latch data LTd [LTa, LTb]. That is, the decoder 226 of the selection signal output unit 270 decodes the inputted latch data LTd [LTa, LTb] as shown in FIG.

[0144] Specifically, in the case where the ejection data SId[SIH,SIL]=[*,0] and the latch data LTd[LTa,LTb]=[*,0] is input to the decoder 226, the decoder 226 outputs a selection signal S of L level in period p1, and outputs a selection signal S of L level in period p2. Therefore, the input terminal and the output terminal of the corresponding selection circuit 230 are controlled to be non-conductive in period p1, and are controlled to be non-conductive in period p2. As a result, the drive signal selection circuit 200 outputs a drive voltage VOUT that is constant at voltage Vc in period p1 and constant at voltage Vc in period p2. At this time, ink is not ejected from the nozzle 651 of the corresponding ejection unit 600, and the flushing operation is not performed for the corresponding ejection unit 600.

[0145] In the case of ejection data SId[SIH,SIL]=[*,1], when latch data LTd[LTa,LTb]=[*,1] is input to the decoder 226, the decoder 226 outputs a selection signal S of L level in period p1, and outputs a selection signal S of H level in period p2. Therefore, the input terminal and the output terminal of the corresponding selection circuit 230 are controlled to be non-conductive in period p1, and controlled to be conductive in period p2. As a result, the drive signal selection circuit 200 outputs a drive voltage VOUT that is constant at voltage Vc in period p1 and has a drive waveform Adp2 in period p3. At this time, a flushing operation is performed in which a small amount of ink is ejected from the nozzle 651 of the corresponding ejection unit 600. Here, in the following description, in the first flushing mode, the signal waveform of the drive voltage VOUT output by the drive signal selection circuit 200 when ejection data SId[SIH,SIL]=[*,1] is input may be referred to as a drive voltage waveform FL1.

[0146] FIG. 21 is a diagram showing an example of the head control signal DI in the second flushing mode.

[0147] As shown in FIG. 21, in the second flushing mode, the setting information signal SP included in the head control signal DI serially includes “0” as setting data PA33, “0” as setting data PA32, “0” as setting data PA31, “0” as setting data PA30, “1” as setting data PA23, “0” as setting data PA22, “1” as setting data PA21, “0” as setting data PA20, “1” as setting data PA13, “0” as setting data PA12, “1” as setting data PA11, “0” as setting data PA10, “0” as setting data PA03, “0” as setting data PA02, “0” as setting data PA01, and “0” as setting data PA00.

[0148] That is, when the liquid ejection device 1 is in the second flushing mode, the head control signal DI includes a 16-bit setting information signal SP whose logical level is "0000 1010 1010 0000". Here, in the following description, the setting information signal SP included in the head control signal DI when the operating mode of the liquid ejection device 1 is the second flushing mode may be referred to as 0x0AA0 in hexadecimal notation. In other words, in the second flushing mode in which a flushing operation is performed in which an amount of ink different from the predetermined amount in the first flushing mode is ejected from the multiple ejection units 600 including the ejection unit 600[1], the control circuit 100 outputs the head control signal DI including the setting information signal SP of 0x0AA0 corresponding to the flushing operation in which an amount of ink different from the predetermined amount is ejected as the setting information signal SP.

[0149] The head control signal DI including the setting information signal SP described above is input to the drive signal selection circuit 200. The setting information signals SP input to the drive signal selection circuit 200 are held in an SP register group 262, and then latched all at once by the selection control signal generation unit 264 at the rising edge of the latch signal LAT. Then, the selection control signal generation unit 264 generates setting signal Q1[PA00, PA01, PA02, PA03]=[0,0,0,0], setting signal Q2[PA10, PA11, PA12, PA13]=[0,1,0,1], setting signal Q3[PA20, PA21, PA22, PA23]=[0,1,0,1], and setting signal Q4[PA30, PA31, PA32, PA33]=[0,0,0,0] from the latched setting information signal SP, and outputs them to the decoders 226 included in each of the selection signal output units 270[1] to 270[n].

[0150] 22 is a diagram showing the decoded contents of the decoder 226 in the second flushing mode. The decoder 226 of the selection signal output unit 270 outputs a selection signal S of a predetermined logic level by decoding the latch data LTd[LTa, LTb] corresponding to the input ejection data SId[SIH, SIL] with the contents shown in FIG. 22. For example, when the latch data LTd[LTa, LTb]=[0,1] corresponding to the ejection data SId[SIH, SIL]=[0,1] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 outputs the selection signal S of L level in period p1, outputs the selection signal S of H level in period p2, outputs the selection signal S of H level in period p3, and outputs the selection signal S of L level in period p4.

[0151] Here, as shown in FIG. 22, in the second flushing mode, the decoder 226 outputs the selection signal S of the same logic level in each of the periods p1 to p4 when the latch data LTd[LTa, LTb]=[0,0] is input and when the latch data LTd[LTa, LTb]=[1,0] is input, and outputs the selection signal S of the same logic level in each of the periods p1 to p4 when the latch data LTd[LTa, LTb]=[0,1] is input and when the latch data LTd[LTa, LTb]=[1,1] is input. That is, in the second flushing mode, the selection control circuit 210 outputs the selection signal S of the same logic level regardless of the upper ejection data SIH1 to SIHn. Therefore, the control circuit 100 may output the head control signal DI including the setting information signal SP and the lower ejection data SIL1 to SILn. In other words, the higher-order ejection data SIH1-SIHn may not be included in the head control signal DI output by the control circuit 100. This reduces the number of bits of the head control signal DI, and as a result, the processing load on the control circuit 100 is reduced.

[0152] In the following explanation, the latch data LTd[LTa,LTb]=[0,0] and the latch data LTd[LTa,LTb]=[1,0] may be collectively referred to as the latch data LTd[LTa,LTb]=[*,0], and the latch data LTd[LTa,LTb]=[1,0] and the latch data LTd[LTa,LTb]=[1,1] may be collectively referred to as the latch data LTd[LTa,LTb]=[*,1]. Similarly, the ejection data SId[SIH,SIL]=[0,0] and the ejection data SId[SIH,SIL]=[1,0] may be collectively referred to as the ejection data SId[SIH,SIL]=[*,0], and the ejection data SId[SIH,SIL]=[1,0] and the ejection data SId[SIH,SIL]=[1,1] may be collectively referred to as the ejection data SId[SIH,SIL]=[*,0].

[0153] 23 is a diagram for explaining the operation of the drive signal selection circuit 200 in the second flushing mode. The head control signal DI input to the drive signal selection circuit 200 is synchronized with the clock signal SCK and sequentially propagates through multiple registers included in the SP register group 262, the second registers 222b of each of the selection signal output units 270[1] to 270[n], and the first registers 222a.

[0154] Then, when the supply of the clock signal SCK stops, the setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, and PA03 to PA00 are held in multiple registers included in the SP register group 262, the lower ejection data SIL1 to SILn are held in the corresponding second registers 222b, and the upper ejection data SIH1 to SIHn are held in the corresponding first registers 222a.

[0155] Thereafter, at the rising edge of the latch signal LAT, the setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, and PA03 to PA00 held in a plurality of registers included in the SP register group 262 are latched simultaneously by the selection control signal generating unit 264, the lower ejection data SIL1 to SILn held in the second registers 222b of each of the selection signal output units 270[1] to 270[n] are latched simultaneously by the corresponding second latch circuits 224b, and the upper ejection data SIH1 to SIHn held in the first registers 222a of each of the selection signal output units 270[1] to 270[n] are latched simultaneously by the corresponding first latch circuits 224a.

[0156] The selection control signal generating unit 264 generates setting signals Q1-Q4 from the latched setting data PA33-PA30, PA23-PA20, PA13-PA10, and PA03-PA00, and outputs them to the decoders 226 of the selection signal output units 270[1]-270[n]. The second latch circuits 224b of the selection signal output units 270[1]-270[n] output the lower ejection data SIL1-SILn latched by each of them as latch data LTb1-LTbn to the corresponding decoders 226, and the first latch circuits 224a of the selection signal output units 270[1]-270[n] output the upper ejection data SIH1-SIHn latched by each of them as latch data LTa1-LTan to the corresponding decoders 226.

[0157] That is, the decoder 226 of the selection signal output unit 270 receives the setting signal Q1 [PA00, PA01, PA02, PA03] = [0, 0, 0, 0], the setting signal Q2 [PA10, PA11, PA12, PA13] = [0, 1, 0, 1], the setting signal Q3 [PA20, PA21, PA22, PA23] = [0, 1, 0, 1], the setting signal Q4 [PA30, PA31, PA32, PA33] = [0, 0, 0, 0], and the latch data LTd [LTa, LTb]. That is, the decoder 226 of the selection signal output unit 270 decodes the inputted latch data LTd [LTa, LTb] as shown in FIG.

[0158] Specifically, in the case where the ejection data SId[SIH,SIL]=[*,0] and the latch data LTd[LTa,LTb]=[*,0] is input to the decoder 226, the decoder 226 outputs a selection signal S of L level in period p1, outputs a selection signal S of L level in period p2, and outputs a selection signal S of L level in period p3. Therefore, the input terminal and the output terminal of the corresponding selection circuit 230 are controlled to be non-conductive in period p1, controlled to be non-conductive in period p2, and controlled to be non-conductive in period p3. As a result, the drive signal selection circuit 200 outputs a drive voltage VOUT that is constant at voltage Vc in period p1, constant at voltage Vc in period p2, and constant at voltage Vc in period p3. At this time, ink is not ejected from the nozzle 651 of the corresponding ejection unit 600, and a flushing operation is not performed for the corresponding ejection unit 600.

[0159] In the case where the ejection data SId[SIH,SIL]=[*,1] and the latch data LTd[LTa,LTb]=[*,1] is input to the decoder 226, the decoder 226 outputs a selection signal S of L level in period p1, outputs a selection signal S of H level in period p2, and outputs a selection signal S of H level in period p3. Therefore, the input terminal and the output terminal of the corresponding selection circuit 230 are controlled to be non-conductive in period p1, controlled to be conductive in period p2, and controlled to be conductive in period p3. As a result, the drive signal selection circuit 200 outputs a drive voltage VOUT that is constant at voltage Vc in period p1, has a drive waveform Bdp2 in period p2, and has a drive waveform Bdp3 in period p3. At this time, a flushing operation is performed in which a medium amount and a small amount of ink are ejected from the nozzle 651 of the corresponding ejection unit 600. Here, in the following description, in the second flushing mode, the signal waveform of the drive voltage VOUT output by the drive signal selection circuit 200 when the ejection data SId[SIH, SIL] = [*, 1] is input may be referred to as the drive voltage waveform FL2.

[0160] As described above, when the operation mode is the first flushing mode, a small amount of ink is ejected from the corresponding ejection units 600 in a latch cycle Plat consisting of periods p1 and p2, and when the operation mode is the second flushing mode, a medium amount of ink and a small amount of ink are ejected from the corresponding ejection units 600 in a latch cycle Plat consisting of periods p1, p2, and p3. This refreshes the ink stored in the target ejection units 600, reducing the risk of the ink stored in the target ejection units 600 drying out or thickening. Note that the amount of ink ejected from the corresponding ejection units 600 in the first flushing mode and the second flushing mode is not limited to the example described above.

[0161] 5. Configuration and operation of the discharge count circuit As described above, in the liquid ejection device 1 of this embodiment, the control circuit 100 generates and outputs head control signals DI1 to DI7 including setting information signals SP corresponding to the high-speed printing mode, the high-resolution printing mode, the first flushing mode, and the second flushing mode. The head control signals DI1 to DI7 output by the control circuit 100 are input to the drive signal selection circuits 200 included in each of the print heads 21-1 to 21-7. The drive signal selection circuits 200 included in each of the print heads 21-1 to 21-7 generate drive voltages VOUT corresponding to the high-speed printing mode, the high-resolution printing mode, the first flushing mode, and the second flushing mode based on the input head control signals DI1 to DI7, and output them to the corresponding ejection units 600. As a result, the multiple ejection units 600 included in each of the print heads 21-1 to 21-7 eject ink in amounts corresponding to the high-speed printing mode, the high-resolution printing mode, the first flushing mode, and the second flushing mode.

[0162] At this time, the head control signals DI1 to DI7 output by the control circuit 100 are also input to the discharge count circuit 300. Based on the input head control signals DI1 to DI7, the discharge count circuit 300 counts the number of times that ink is discharged from each of the discharge units 600[1] to 600[n] of the print heads 21-1 to 21-7, that is, the number of times that the piezoelectric elements 60 included in each of the discharge units 600[1] to 600[n] of the print heads 21-1 to 21-7 are driven, and stores the number of times as discharge count information CI. Here, in the following description, among the discharge count information CI stored in the discharge count circuit 300, the discharge count information CI corresponding to the print head 21-1 may be referred to as discharge count information CI1, and the discharge count information CI corresponding to the print head 21-i may be referred to as discharge count information CIi.

[0163] 24 is a diagram showing an example of the configuration of the discharge count circuit 300. As shown in FIG.

[0164] The head control signals DI1 to DI7 output by the control circuit 100 are input to the count circuit 310. Based on the input head control signal DI1, the count circuit 310 counts the number of times ink is discharged from each of the discharge sections 600[1] to 600[n] of the print head 21-1 for each of the discharge sections 600[1] to 600[n] of the print head 21-1. The count circuit 310 then generates discharge count information CI1 according to the count results for each of the discharge sections 600[1] to 600[n] of the print head 21-1. After that, the count circuit 310 generates a memory control signal MC for storing the generated discharge count information CI1 in the memory circuit 320, and outputs the signal to the memory circuit 320 at a predetermined timing.

[0165] Similarly, the count circuit 310 counts the number of times ink is discharged from each of the discharge units 600[1]-600[n] of the print head 21-i based on the input head control signal DIi. The count circuit 310 then generates discharge count information CIi based on the count results for each of the discharge units 600[1]-600[n] of the print head 21-i. The count circuit 310 then generates a memory control signal MC for storing the generated discharge count information CIi in the memory circuit 320, and outputs the signal to the memory circuit 320 at a predetermined timing.

[0166] The memory circuit 320 is a non-volatile memory, and is configured to include, for example, an EEPROM (Electrically Erasable Programmable Read-Only Memory), a flash memory, etc. The memory circuit 320 stores the ejection count information CI1 to CIj based on a memory control signal MC input from the count circuit 310.

[0167] Here, the memory control signal MC is a signal that transmits information between the count circuit 310 and the storage circuit 320, and also functions as a signal for the count circuit 310 to control the storage circuit 320. Therefore, the memory control signal MC can be used not only when storing predetermined information in the storage circuit 320, but also when reading out information stored in the storage circuit 320. In other words, the memory control signal MC includes a signal for writing predetermined information to the storage circuit 320 and a signal for reading out predetermined information from the storage circuit 320. In addition, the storage circuit 320 may be capable of communicating with the outside of the liquid ejection device 1 without going through the count circuit 310.

[0168] Here, an example of the configuration of the storage circuit 320 in which the discharge count information CI1 to CIj are stored will be described. Fig. 25 is a diagram for explaining the storage areas of the storage circuit 320. As shown in Fig. 25, the storage circuit 320 has storage areas corresponding to the head control signals DI1 to DI7, including a storage area in which the discharge count information CI1 corresponding to the print head 21-1 is stored, a storage area in which the discharge count information CI2 corresponding to the print head 21-2 is stored, a storage area in which the discharge count information CI3 corresponding to the print head 21-3 is stored, a storage area in which the discharge count information CI4 corresponding to the print head 21-4 is stored, a storage area in which the discharge count information CI5 corresponding to the print head 21-5 is stored, a storage area in which the discharge count information CI6 corresponding to the print head 21-6 is stored, and a storage area in which the discharge count information CI7 corresponding to the print head 21-7 is stored.

[0169] Here, the memory areas in which the discharge count information CI1 to CI7 are stored have the same configuration. Therefore, in the explanation of Fig. 25, the memory area in which the discharge count information CI1 corresponding to the print head 21-1 is stored will be mainly explained, and the explanation of the memory areas in which the discharge count information CI2 to CI7 are stored will be simplified or omitted.

[0170] 25, the memory area in which the discharge count information CI1 is stored includes memory areas corresponding to each of the discharge units 600[1] to 600[n] of the print head 21-1. The memory area corresponding to the discharge unit 600[j] of the print head 21-1 includes memory areas corresponding to each of the drive voltage waveforms Asd, Ald, Bsd, Bmd, Bld, FL1, and FL2, which are signal waveforms of the drive voltage VOUT supplied to the discharge unit 600[j] of the print head 21-1.

[0171] Then, in the memory area corresponding to the drive voltage waveform Asd within the memory area corresponding to the ejection section 600[j] of the print head 21-1, a count value Casd[j] is stored as the number of times that the drive voltage VOUT including the drive voltage waveform Asd was supplied to the ejection section 600[j] of the print head 21-1, and as the number of times that ink was ejected from the ejection section 600[j] of the print head 21-1 by the drive voltage VOUT including the drive voltage waveform Asd.

[0172] Further, a count value Cald[j] is stored in a memory area corresponding to the drive voltage waveform Ald within the memory area corresponding to the ejection portion 600[j] of the print head 21-1 as the number of times that the drive voltage VOUT including the drive voltage waveform Ald was supplied to the ejection portion 600[j] of the print head 21-1, and as the number of times that ink was ejected from the ejection portion 600[j] of the print head 21-1 by the drive voltage VOUT including the drive voltage waveform Ald.

[0173] In addition, a count value Cbsd[j] is stored in a memory area corresponding to the drive voltage waveform Bsd within the memory area corresponding to the ejection section 600[j] of the print head 21-1 as the number of times that a drive voltage VOUT including the drive voltage waveform Bsd was supplied to the ejection section 600[j] of the print head 21-1, and as the number of times that ink was ejected from the ejection section 600[j] of the print head 21-1 by the drive voltage VOUT including the drive voltage waveform Bsd.

[0174] In addition, a count value Cbmd[j] is stored in a memory area corresponding to the drive voltage waveform Bmd within the memory area corresponding to the ejection section 600[j] of the print head 21-1 as the number of times that a drive voltage VOUT including the drive voltage waveform Bmd was supplied to the ejection section 600[j] of the print head 21-1, and as the number of times that ink was ejected from the ejection section 600[j] of the print head 21-1 by the drive voltage VOUT including the drive voltage waveform Bmd.

[0175] Further, in the memory area corresponding to the ejection section 600[j] of the print head 21-1, a count value Cbld[j] is stored in a memory area corresponding to the drive voltage waveform Bld as the number of times that the drive voltage VOUT including the drive voltage waveform Bld was supplied to the ejection section 600[j] of the print head 21-1, and as the number of times that ink was ejected from the ejection section 600[j] of the print head 21-1 by the drive voltage VOUT including the drive voltage waveform Bld.

[0176] Additionally, a count value Cfl1[j] is stored in a memory area corresponding to the drive voltage waveform FL1 within the memory area corresponding to the ejection section 600[j] of the print head 21-1 as the number of times that a drive voltage VOUT including the drive voltage waveform FL1 was supplied to the ejection section 600[j] of the print head 21-1, and as the number of times that ink was ejected from the ejection section 600[j] of the print head 21-1 by the drive voltage VOUT including the drive voltage waveform FL1.

[0177] Additionally, a count value Cfl2[j] is stored in a memory area corresponding to the drive voltage waveform FL2 within the memory area corresponding to the ejection section 600[j] of the print head 21-1 as the number of times that a drive voltage VOUT including the drive voltage waveform FL2 was supplied to the ejection section 600[j] of the print head 21-1, and as the number of times that ink was ejected from the ejection section 600[j] of the print head 21-1 by the drive voltage VOUT including the drive voltage waveform FL2.

[0178] In other words, the memory area in which the ejection count information CI1 is stored contains the number of times that ink has been ejected from each of the ejection sections 600[1] to 600[n] of the print head 21-1, and the number of times that the piezoelectric elements 60 of each of the ejection sections 600[1] to 600[n] of the print head 21-1 have been driven, stored in correspondence with each of the drive voltage waveforms Asd, Ald, Bsd, Bmd, Bld, FL1, and FL2, which are the signal waveforms of the drive voltage VOUT supplied to the piezoelectric elements 60.

[0179] Similarly, the memory area in which the ejection count information CI2 to CI7 is stored stores the number of times that ink has been ejected from each of the ejection sections 600[1] to 600[n] of each of the print heads 21-2 to 21-7, that is, the number of times that the piezoelectric elements 60 of each of the ejection sections 600[1] to 600[n] of each of the print heads 21-2 to 21-7 have been driven, corresponding to each of the drive voltage waveforms Asd, Ald, Bsd, Bmd, Bld, FL1, and FL2, which are the signal waveforms of the drive voltage VOUT supplied to the piezoelectric elements 60.

[0180] That is, in the high-speed printing mode, the discharge count circuit 300 stores the number of times that the piezoelectric element 60 included in the discharge unit 600[1] is driven by the drive voltage VOUT[1] of the drive voltage waveform Asd output by the selection circuit 230[1] as a count value Casd[1], and the number of times that the piezoelectric element 60 included in the discharge unit 600[1] is driven by the drive voltage VOUT[1] of the drive voltage waveform Ald output by the selection circuit 230[1] as a count value Cald[1]. In the high-resolution printing mode, the number of times that the piezoelectric element 60 included in the discharge unit 600[1] is driven by the drive voltage VOUT[1] of the drive voltage waveform Bsd output by the selection circuit 230[1] is stored as a count value Cbsd[1], and the number of times that the piezoelectric element 60 included in the discharge unit 600[1] is driven by the drive voltage VOUT[1] of the drive voltage waveform Bmd output by the selection circuit 230[1] is stored as a count value Cbsd[1]. In this manner, the number of times that the piezoelectric element 60 included in the discharge section 600[1] has been driven is stored as a count value Cbmd[1], the number of times that the piezoelectric element 60 included in the discharge section 600[1] has been driven by the drive voltage VOUT[1] of the drive voltage waveform Bld output by the selection circuit 230[1] is stored as a count value Cbld[1], in the first flushing mode, the number of times that the piezoelectric element 60 included in the discharge section 600[1] has been driven by the drive voltage VOUT[1] of the drive voltage waveform FL1 output by the selection circuit 230[1] is stored as a count value Cfl1[1], and in the second flushing mode, the number of times that the piezoelectric element 60 included in the discharge section 600[1] has been driven by the drive voltage VOUT[1] of the drive voltage waveform FL2 output by the selection circuit 230[1] is stored as a count value Cfl2[1].

[0181] Similarly, in the discharge count circuit 300, in the high-speed print mode, the number of times that the piezoelectric element 60 included in the discharge unit 600[2] has been driven by the drive voltage VOUT[2] of the drive voltage waveform Asd output by the selection circuit 230[2] is stored as a count value Casd[2], and the number of times that the piezoelectric element 60 included in the discharge unit 600[2] has been driven by the drive voltage VOUT[2] of the drive voltage waveform Ald output by the selection circuit 230[2] is stored as a count value Cald[2]. In the high-resolution print mode, the number of times that the piezoelectric element 60 included in the discharge unit 600[2] has been driven by the drive voltage VOUT[2] of the drive voltage waveform Bsd output by the selection circuit 230[2] is stored as a count value Cbsd[2], and the number of times that the piezoelectric element 60 included in the discharge unit 600[2] has been driven by the drive voltage VOUT[2] of the drive voltage waveform Bmd output by the selection circuit 230[2] is stored as a count value Cbsd[2]. Thus, the number of times the piezoelectric element 60 included in the discharge section 600[2] has been driven is stored as a count value Cbmd[2], the number of times the piezoelectric element 60 included in the discharge section 600[2] has been driven by the drive voltage VOUT[2] of the drive voltage waveform Bld output by the selection circuit 230[2] is stored as a count value Cbld[2], in the first flushing mode, the number of times the piezoelectric element 60 included in the discharge section 600[2] has been driven by the drive voltage VOUT[2] of the drive voltage waveform FL1 output by the selection circuit 230[2] is stored as a count value Cfl1[2], and in the second flushing mode, the number of times the piezoelectric element 60 included in the discharge section 600[2] has been driven by the drive voltage VOUT[2] of the drive voltage waveform FL2 output by the selection circuit 230[2] is stored as a count value Cfl2[2].

[0182] That is, in the high-speed printing mode, the discharge count circuit 300 stores the number of times that the piezoelectric element 60 included in the discharge unit 600[j] has been driven by the drive voltage VOUT[j] of the drive voltage waveform Asd output by the selection circuit 230[j] as a count value Casd[j], and the number of times that the piezoelectric element 60 included in the discharge unit 600[j] has been driven by the drive voltage VOUT[j] of the drive voltage waveform Ald output by the selection circuit 230[j] as a count value Cald[j]. In the high-resolution printing mode, the discharge count circuit 300 stores the number of times that the piezoelectric element 60 included in the discharge unit 600[j] has been driven by the drive voltage VOUT[j] of the drive voltage waveform Bsd output by the selection circuit 230[j] as a count value Cbsd[j], and the number of times that the piezoelectric element 60 included in the discharge unit 600[j] has been driven by the drive voltage VOUT[j] of the drive voltage waveform Bmd output by the selection circuit 230[j]. Thus, the number of times the piezoelectric element 60 included in the discharge section 600[j] has been driven is stored as a count value Cbmd[j], the number of times the piezoelectric element 60 included in the discharge section 600[j] has been driven by the drive voltage VOUT[j] of the drive voltage waveform Bld output by the selection circuit 230[j] is stored as a count value Cbld[j], in the first flushing mode, the number of times the piezoelectric element 60 included in the discharge section 600[j] has been driven by the drive voltage VOUT[j] of the drive voltage waveform FL1 output by the selection circuit 230[j] is stored as a count value Cfl1[j], and in the second flushing mode, the number of times the piezoelectric element 60 included in the discharge section 600[j] has been driven by the drive voltage VOUT[j] of the drive voltage waveform FL2 output by the selection circuit 230[j] is stored as a count value Cfl2[j].

[0183] Next, an example of a method for counting the number of times each of the ejection units 600[1] to 600[n] of the print head 21-i has been driven, that is, the number of times ink has been ejected from each of the ejection units 600[1] to 600[n] of the print head 21-i, in the count circuit 310 will be described.

[0184] Fig. 26 is a diagram showing an example of the operation of the count circuit 310. As shown in Fig. 26, the count circuit 310 reads out the ejection count information CIi stored in the memory circuit 320 (step S10). Here, the timing at which the count circuit 310 reads out the ejection count information CIi from the memory circuit 320 may be, for example, the timing at which an image information signal including image data is input to the liquid ejection device 1, or the timing at which the supply of power supply voltage to the liquid ejection device 1 begins.

[0185] Specifically, the count circuit 310 generates a memory control signal MC for reading the discharge count information CIi from the memory circuit 320 at a predetermined timing for reading the discharge count information CIi from the memory circuit 320, and outputs the signal to the memory circuit 320. As a result, the count circuit 310 acquires, as the discharge count information CIi, the count values ​​Casd[1] to Casd[n], Cald[1] to Cald[n], Cbsd[1] to Cbsd[n], Cbmd[1] to Cbmd[n], Cbld[1] to Cbld[n], Cfl1[1] to Cfl1[n], and Cfl2[1] to Cfl2[n] from the memory area of ​​the memory circuit 320 in which the discharge count information CIi is stored.

[0186] Thereafter, the control circuit 100 generates and outputs a head control signal DIi in response to image data input from an external device of the liquid ejection device 1 and a user's operation. The head control signal DIi output by the control circuit 100 is input to the count circuit 310 (step S20).

[0187] The count circuit 310 identifies the operation mode of the liquid ejection device 1 from the setting information signal SP included in the input head control signal DIi (step S30). For example, when the setting information signal SP included in the head control signal DIi input to the count circuit 310 is 0x0248, the count circuit 310 identifies the operation mode of the liquid ejection device 1 as the high-definition printing mode. When the setting information signal SP included in the head control signal DIi input to the count circuit 310 is 0x00A0, the count circuit 310 identifies the operation mode of the liquid ejection device 1 as the first flushing mode.

[0188] Thereafter, the counting circuit 310 identifies the signal waveform of the drive voltage VOUT supplied to the piezoelectric element 60 of the ejection portion 600[j] from the identified operation mode of the liquid ejection device 1 and the ejection information signal SI included in the head control signal DIi (step S40). For example, if the counting circuit 310 identifies that the operation mode of the liquid ejection device 1 is the high-speed print mode, and further, the ejection data SIdj[SIHj,SILj]=[1,0] of the ejection information signal SI included in the head control signal DIi input to the counting circuit 310, the counting circuit 310 identifies that the drive voltage VOUT including the drive voltage waveform Asd is supplied to the ejection portion 600[j] of the print head 21-i. Furthermore, when the counting circuit 310 determines that the operating mode of the liquid ejection device 1 is the second flushing mode, and further, the ejection data SIdj[SIHj,SILj]=[1,1] of the ejection information signal SI contained in the head control signal DIi input to the counting circuit 310, the counting circuit 310 determines that a driving voltage VOUT including a driving voltage waveform FL2 is supplied to the ejection section 600[j] of the print head 21-i.

[0189] Then, the count circuit 310 adds a count value of the number of times the ejection unit 600[j] corresponding to the identified signal waveform of the driving voltage VOUT is driven (step S50). For example, when the count circuit 310 determines that the ejection unit 600[j] of the print head 21-i is supplied with a driving voltage VOUT including a driving voltage waveform Ald, the count circuit 310 adds "1" to the count value Cald[j]. When the count circuit 310 determines that the ejection unit 600[j] of the print head 21-i is supplied with a driving voltage VOUT including a driving voltage waveform Bmd, the count circuit 310 adds "1" to the count value Cbmd[j].

[0190] Thereafter, the count circuit 310 determines whether the next head control signal DIi is input (step S60). For example, the count circuit 310 may add up the number of times the ejection section 600[j] corresponding to the identified signal waveform of the drive voltage VOUT in step S50, and then determine whether the next head control signal DIi is input based on whether the next head control signal DIi is input within a predetermined period. Alternatively, the control circuit 100 may output a completion signal indicating that processing based on the image information signal or a user request has been completed, and the count circuit 310 may determine whether the next head control signal DIi is input based on whether the completion signal has been input from the control circuit 100.

[0191] When the count circuit 310 determines that the next head control signal DIi has been input (Y in step S60), the count circuit 310 executes the above-mentioned steps S30, S40, and S50 for the input head control signal DIi. On the other hand, when the count circuit 310 determines that the next head control signal DIi has not been input (N in step S60), the count circuit 310 generates discharge count information CIi including count values ​​Casd[1] to Casd[n], Cald[1] to Cald[n], Cbsd[1] to Cbsd[n], Cbmd[1] to Cbmd[n], Cbld[1] to Cbld[n], Cfl1[1] to Cfl1[n], and Cfl2[1] to Cfl2[n] corresponding to the print head 21-i. Then, the count circuit 310 stores the generated discharge count information CIi in the memory circuit 320. As a result, the discharge count information CIi is stored in the memory circuit 320.

[0192] 26, only the head control signal DIi among the head control signals DI1 to DI7 has been described, but the count circuit 310 performs similar processing for all of the head control signals DI1 to DI7. That is, the count circuit 310 counts the number of times for each signal waveform of the drive voltage VOUT supplied to the ejection sections 600[1] to 600[n] of each of the print heads 21-1 to 21-7. Then, the counting circuit 310 generates ejection count information CI1 to CI7 which is the counting results corresponding to each of the print heads 21-1 to 21-7 and includes count values ​​Casd[1] to Casd[n], Cald[1] to Cald[n], Cbsd[1] to Cbsd[n], Cbmd[1] to Cbmd[n], Cbld[1] to Cbld[n], Cfl1[1] to Cfl1[n], and Cfl2[1] to Cfl2[n] corresponding to each of the print heads 21-1 to 21-7, and outputs the generated ejection count information CI1 to CI7 to the memory circuit 320.

[0193] As a result, the memory circuit 320 stores the ejection count information CI1 to CI7.

[0194] Here, the head control signal DI is an example of an ejection control signal, the setting information signal SP included in the head control signal DI is an example of selection rule data, the ejection data SId1[SIH1, SIL1] of the ejection information signal SI included in the head control signal DI is an example of first drive data, and the ejection data SId2[SIH2, SIL2] of the ejection information signal SI included in the head control signal DI is an example of second drive data. Also, the setting information signal SP including information of 0x0048 is an example of first selection rule data, the setting information signal SP including information of 0x0248 is an example of second selection rule data, the setting information signal SP including information of 0x00A0 is an example of first flushing selection rule data, and the setting information signal SP including information of 0x0AA0 is an example of second flushing selection rule data.

[0195] Furthermore, among the drive signals COM, the drive signal ComA is an example of a first drive signal, among the drive signals COM, the drive signal ComB is an example of a second drive signal, the signal waveform including the drive waveforms Adp1, Adp2, Bdp1 to Bdp3 included in the drive signal COM is an example of a plurality of drive signal waveforms, the drive waveforms Adp1 and Adp2 are an example of a plurality of first drive signal waveforms, and the drive waveforms Bdp1 to Bdp3 are an example of a plurality of second drive signal waveforms.

[0196] Moreover, the drive voltage VOUT[1] is an example of a first drive voltage, the selection circuit 230[1] that outputs the drive voltage VOUT[1] is an example of a first selection circuit, the discharge section 600[1] to which the drive voltage VOUT[1] is input is an example of a first discharge section, and the piezoelectric element 60 included in the discharge section 600[1] is an example of a first piezoelectric element. Moreover, the drive voltage VOUT[2] is an example of a second drive voltage. The selection circuit 230[2] that outputs the drive voltage VOUT[2] is an example of a second selection circuit, the discharge section 600[2] to which the drive voltage VOUT[2] is input is an example of a second discharge section, and the piezoelectric element 60 included in the discharge section 600[2] is an example of a second piezoelectric element.

[0197] In addition, at least one of the drive voltage waveforms Ald, Bld as the signal waveform of the drive voltage VOUT[1] is an example of a first drive voltage waveform, at least one of the drive voltage waveforms Asd, Bsd as the signal waveform of the drive voltage VOUT[1] is an example of a second drive voltage waveform, at least one of the drive voltage waveforms Asd, Ald, Bsd, Bmd, Bld as the signal waveform of the drive voltage VOUT[2] is an example of a third drive voltage waveform, at least one of the drive voltage waveforms Asd, Ald as the signal waveform of the drive voltage VOUT[1] is an example of a fourth drive voltage waveform, at least one of the drive voltage waveforms Bsd, Bmd, Bld as the signal waveform of the drive voltage VOUT[1] is an example of a fifth drive voltage waveform, the drive voltage VOUT[1] output in the first flushing mode is an example of a sixth drive voltage waveform, and the drive voltage VOUT[1] output in the second flushing mode is an example of a seventh drive voltage waveform.

[0198] In addition, at least one of the count values ​​Cald[1], Cbld[1] is an example of a first drive number, at least one of the count values ​​Casd[1], Cbsd[1] is an example of a second drive number, at least one of the count values ​​Casd[2], Cald[2], Cbsd[2], Cbmd[2], Cbld[2] is an example of a third drive number, at least one of the count values ​​Casd[1], Cald[1] is an example of a fourth drive number, at least one of the count values ​​Cbsd[1], Cbmd[1], Cbld[1] is an example of a fifth drive number, the count value Cfl1[1] is an example of a sixth drive number, and the count value Cfl1[1] is an example of a seventh drive number.

[0199] The high-speed printing mode is an example of a first operating mode, the high-resolution printing mode is an example of a second operating mode, the flushing operation performed in the first flushing mode is an example of a first flushing operation, and the flushing operation performed in the second flushing mode is an example of a second flushing operation.

[0200] 6. Effects In the liquid ejection device 1 of the present embodiment configured as described above, the ejection count circuit 300 stores the number of times the piezoelectric element 60 of the ejection unit 600[1] has been driven by the driving voltage VOUT[1] output by the selection circuit 230[1]. That is, the ejection count circuit 300 stores the number of times the ejection unit 600[1] has been driven, that is, the number of times ink has been ejected from the ejection unit 600[1], for each ejection unit 600[1]. This allows the state of the print heads 21-1 to 21-7 of the liquid ejection device 1 to be grasped in detail, compared to a case where the state of the print heads is collectively stored. As a result, when the print heads 21-1 to 21-7 of the liquid ejection device 1 of the present embodiment or the ejection mechanism 20 including the print heads 21-1 to 21-7 are reused, the accuracy of determining the state of the print heads 21-1 to 21-7 and the ejection mechanism 20 including the print heads 21-1 to 21-7 is improved.

[0201] In addition, in the liquid ejection device 1 of this embodiment, the ejection count circuit 300 separately stores the number of times that the piezoelectric element 60 of the ejection unit 600[1] is driven by the driving voltage VOUT[1] of the driving voltage waveform Asd output by the selection circuit 230[1], and the number of times that the piezoelectric element 60 of the ejection unit 600[1] is driven by the driving voltage VOUT[1] of the driving voltage waveform Ald output by the selection circuit 230[1]. This allows the state of the print heads 21-1 to 21-7 of the liquid ejection device 1 to be grasped in more detail. As a result, when the print heads 21-1 to 21-7 of the liquid ejection device 1 of this embodiment or the ejection mechanism 20 including the print heads 21-1 to 21-7 are reused, the accuracy of determining the state of the print heads 21-1 to 21-7 and the ejection mechanism 20 including the print heads 21-1 to 21-7 is further improved.

[0202] Furthermore, in the liquid ejection device 1 of this embodiment, the ejection count circuit 300 separately stores the number of times that the piezoelectric element 60 of the ejection unit 600[1] is driven by the driving voltage VOUT[1] output by the selection circuit 230[1] and the number of times that the piezoelectric element 60 of the ejection unit 600[2] is driven by the driving voltage VOUT[2] output by the selection circuit 230[2]. This allows the state of the print heads 21-1 to 21-7 of the liquid ejection device 1 to be grasped in more detail. As a result, when the print heads 21-1 to 21-7 of the liquid ejection device 1 of this embodiment or the ejection mechanism 20 including the print heads 21-1 to 21-7 are reused, the accuracy of determining the state of the print heads 21-1 to 21-7 and the ejection mechanism 20 including the print heads 21-1 to 21-7 is further improved.

[0203] Furthermore, the liquid ejection device 1 of this embodiment has a high-speed printing mode and a high-resolution printing mode in which the gradations of the dots formed on the medium P are different. This allows the user to select the optimum operation mode according to the purpose of the user, the material of the medium P onto which the ink is ejected, and the physical properties of the ejected ink. As a result, the versatility of the liquid ejection device 1 is increased.

[0204] Even in the case of a high-speed printing mode and a high-resolution printing mode with different dot gradations as in the liquid ejection device 1 of the present embodiment, the ejection counting circuit 300 stores the number of times that the piezoelectric element 60 of the ejection unit 600[1] is driven by the driving voltage VOUT[1] output by the selection circuit 230[1] in the high-speed printing mode and the number of times that the piezoelectric element 60 of the ejection unit 600[1] is driven by the driving voltage VOUT[1] output by the selection circuit 230[1] in the high-resolution printing mode, respectively, so that the state of the print heads 21-1 to 21-7 of the liquid ejection device 1 can be grasped in more detail. As a result, when the print heads 21-1 to 21-7 of the liquid ejection device 1 of the present embodiment or the ejection mechanism 20 including the print heads 21-1 to 21-7 are reused, the accuracy of determining the state of the print heads 21-1 to 21-7 and the ejection mechanism 20 including the print heads 21-1 to 21-7 is further improved.

[0205] Furthermore, the liquid ejection device 1 of this embodiment has a first flushing mode and a second flushing mode for executing a flushing process, which is a maintenance process for the liquid ejection device 1, and the ejection count circuit 300 separately stores the number of times that the piezoelectric element 60 of the ejection unit 600[1] is driven by the drive voltage VOUT[1] output by the selection circuit 230[1] in the first flushing mode, and the number of times that the piezoelectric element 60 of the ejection unit 600[1] is driven by the drive voltage VOUT[1] output by the selection circuit 230[1] in the second flushing mode. This allows the state of the print heads 21-1 to 21-7 of the liquid ejection device 1 of this embodiment to be grasped in more detail. As a result, when the print heads 21-1 to 21-7 of the liquid ejection device 1 of this embodiment, or the ejection mechanism 20 including the print heads 21-1 to 21-7, are reused, the accuracy of determining the state of the print heads 21-1 to 21-7 and the ejection mechanism 20 including the print heads 21-1 to 21-7 is further improved.

[0206] As described above, in the liquid ejection device 1 of the present embodiment, the state of the print heads 21-1 to 21-7 of the liquid ejection device 1 can be grasped in more detail, and when the print heads 21-1 to 21-7 of the liquid ejection device 1 or the ejection mechanism 20 including the print heads 21-1 to 21-7 are reused, the accuracy of determining the state of the print heads 21-1 to 21-7 and the ejection mechanism 20 including the print heads 21-1 to 21-7 is further improved. As a result, the ejection mechanism 20 including the print heads 21-1 to 21-7 or the print heads 21-1 to 21-7 can be reused in a more appropriate state, thereby reducing the amount of waste of the ejection mechanism 20 including the print heads 21-1 to 21-7 or the print heads 21-1 to 21-7, and contributing to the achievement of Goal 12 "Responsible Consumption and Production" of the Sustainable Development Goals (SDGs) led by the United Nations.

[0207] 7. Variations In the liquid ejection device 1 of the present embodiment described above, one ejection count circuit 300 counts the count values ​​Casd[1] to Casd[n], Cald[1] to Cald[n], Cbsd[1] to Cbsd[n], Cbmd[1] to Cbmd[n], Cbld[1] to Cbld[n], Cfl1[1] to Cfl1[n], and Cfl2[1] to Cfl2[n] corresponding to each of the print heads 21-1 to 21-7 based on the head control signals DI1 to DI7 corresponding to each of the print heads 21-1 to 21-7, and stores the ejection count information CI1 to CI7 including the count results in the memory circuit 320. In contrast, the liquid ejection device 1 may have a plurality of ejection count circuits 300 corresponding to each of the print heads 21-1 to 21-7, and the corresponding ejection count circuits 300 may count the count values ​​Casd[1] to Casd[n], Cald[1] to Cald[n], Cbsd[1] to Cbsd[n], Cbmd[1] to Cbmd[n], Cbld[1] to Cbld[n], Cfl1[1] to Cfl1[n], and Cfl2[1] to Cfl2[n] of the print head 21 based on the corresponding head control signal DI, and store ejection count information CI including the count results in the memory circuit 320.

[0208] Specifically, the liquid ejection device 1 may have ejection count circuits 300-1 to 300-7 as the ejection count circuit 300 corresponding to the print heads 21-1 to 21-7, respectively. The ejection count circuit 300-1 counts the count values ​​Casd[1] to Casd[n], Cald[1] to Cald[n], Cbsd[1] to Cbsd[n], Cbmd[1] to Cbmd[n], Cbld[1] to Cbld[n], Cfl1[1] to Cfl1[n], and Cfl2[1] to Cfl2[n] of the print head 21-1 based on the head control signal DI1, and stores ejection count information CI1 including the count results in a memory circuit 320 included in the ejection count circuit 300-1. The ejection counting circuit 300-i may count the count values ​​Casd[1] to Casd[n], Cald[1] to Cald[n], Cbsd[1] to Cbsd[n], Cbmd[1] to Cbmd[n], Cbld[1] to Cbld[n], Cfl1[1] to Cfl1[n], and Cfl2[1] to Cfl2[n] of the print head 21-i based on the head control signal DIi, and store the ejection count information CIi including the counting results in the memory circuit 320 included in the ejection counting circuit 300-i.

[0209] This reduces the processing load on each of the ejection count circuits 300-1 to 300-7, and in addition to the above-mentioned effects, the stability of the operation of the liquid ejection device 1 is improved.

[0210] Although the embodiments and modifications have been described above, the present invention is not limited to these embodiments, and can be embodied in various forms without departing from the spirit of the present invention. For example, the above embodiments can be appropriately combined.

[0211] The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations with the same functions, methods and results, or configurations with the same purpose and effect). The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments or that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0212] The following can be derived from the above-described embodiment and modified examples.

[0213] One aspect of the liquid ejection device is A drive circuit that outputs a drive signal including a plurality of drive signal waveforms; A control circuit that outputs a discharge control signal; a first selection circuit that selects the plurality of drive signal waveforms based on the ejection control signal and outputs the selected waveform as a first drive voltage; a first ejection section including a first piezoelectric element that is driven by the first driving voltage and that ejects liquid by driving the first piezoelectric element; a discharge count circuit to which the discharge control signal is input; Equipped with the control circuit outputs the ejection control signal including selection rule data that sets a selection rule for the plurality of drive signal waveforms in the first selection circuit, and first drive data that controls selection of the plurality of drive signal waveforms in the first selection circuit based on the selection rule data; The ejection count circuit stores the number of times the first piezoelectric element is driven by the first drive voltage of the first drive voltage waveform output by the first selection circuit as a first drive count.

[0214] According to this liquid ejection device, the number of times the first piezoelectric element is driven by the first driving voltage of the first driving voltage waveform output by the first selection circuit is individually stored in the ejection count circuit as the first driving count, so that the state of the first ejection section can be grasped in detail compared to the case where the driving counts of multiple piezoelectric elements are stored collectively.

[0215] In one aspect of the liquid ejection device, The ejection count circuit may store, as a second drive count, the number of times the first piezoelectric element is driven by the first drive voltage having a second drive voltage waveform different from the first drive voltage waveform output by the first selection circuit.

[0216] According to this liquid ejection device, the ejection counting circuit separately stores the first drive count in which the first piezoelectric element is driven by the first drive voltage of the first drive voltage waveform output by the first selection circuit, and the second drive count in which the first piezoelectric element is driven by the first drive voltage of the second drive voltage waveform different from the first drive voltage waveform output by the first selection circuit, thereby making it possible to grasp the state of the first ejection section in more detail.

[0217] In one aspect of the liquid ejection device, a second selection circuit that selects the plurality of drive signal waveforms based on the ejection control signal and outputs the selected waveform as a second drive voltage; a second ejection section including a second piezoelectric element that is driven by the second driving voltage and that ejects liquid by driving the second piezoelectric element; Equipped with the control circuit outputs the ejection control signal including second drive data that controls selection of the plurality of drive signal waveforms in the second selection circuit based on the selection rule data; The ejection count circuit may store, as a third drive count, the number of times the second piezoelectric element is driven by the second drive voltage of the third drive voltage waveform output by the second selection circuit.

[0218] According to this liquid ejection device, the ejection counting circuit separately stores the first drive count in which the first piezoelectric element is driven by the first drive voltage of the first drive voltage waveform output by the first selection circuit, and the third drive count in which the second piezoelectric element is driven by the second drive voltage of the third drive voltage waveform output by the second selection circuit, thereby making it possible to grasp in detail the state of the second ejection section in addition to the first ejection section.

[0219] In one aspect of the liquid ejection device, The drive circuit includes: In a first operating mode, a first drive signal including a plurality of first drive signal waveforms is output as the drive signal; In a second operating mode, a second drive signal including a plurality of second drive signal waveforms is output as the drive signal; The control circuit includes: In the first operation mode, the ejection control signal is output, the ejection control signal including, as the selection rule data, first selection rule data that sets a selection rule for the plurality of first drive signal waveforms in the first selection circuit; In the second operation mode, the ejection control signal is output, the ejection control signal including, as the selection rule data, second selection rule data that sets a selection rule for the plurality of second drive signal waveforms in the first selection circuit; The discharge count circuit includes: In the first operation mode, the number of times that the first piezoelectric element is driven by the first drive voltage of the fourth drive voltage waveform output by the first selection circuit is stored as a fourth drive number, In the second operation mode, the number of times the first piezoelectric element is driven by the first drive voltage of a fifth drive voltage waveform output by the first selection circuit may be stored as a fifth drive count.

[0220] According to this liquid ejection device, the ejection counting circuit separately stores the fourth drive count number of times that the first piezoelectric element is driven by the first drive voltage of the fourth drive voltage waveform output by the first selection circuit in the first operating mode, and the fifth drive count number of times that the first piezoelectric element is driven by the first drive voltage of the fifth drive voltage waveform output by the first selection circuit in a second operating mode different from the first mode, so that in addition to the first ejection section, the state of the second ejection section can also be grasped in detail.

[0221] In one aspect of the liquid ejection device, In the first operating mode, the gradation of dots formed on a medium by the liquid ejected by the first ejection section may be different from the gradation of dots formed on a medium by the liquid ejected by the first ejection section in the second operating mode.

[0222] According to this liquid ejection device, by having a first operation mode and a second operation mode which have different dot gradations, the versatility of the liquid ejection device is increased.

[0223] In one aspect of the liquid ejection device, In a first flushing mode in which a first flushing operation is performed to eject a predetermined amount of liquid from a plurality of ejection parts including the first ejection part, the control circuit outputs the ejection control signal including first flushing selection rule data corresponding to the first flushing operation as the selection rule data, and the number of times the first piezoelectric element is driven by the first flushing operation is stored in the ejection count circuit as a sixth drive number, In a second flushing mode in which a second flushing operation is performed in which an amount of liquid different from the predetermined amount is ejected from the multiple ejection parts including the first ejection part, the control circuit outputs the ejection control signal including second flushing selection rule data corresponding to the second flushing operation as the selection rule data, and the ejection counting circuit may store the number of times the first piezoelectric element is driven by the second flushing operation as a seventh driving count.

[0224] According to this liquid ejection device, the ejection counting circuit separately stores the sixth driving number of times that the first piezoelectric element was driven in a first flushing mode in which a first flushing operation is performed in which a predetermined amount of liquid is ejected from a plurality of ejection units including the first ejection unit, and the seventh driving number of times that the first piezoelectric element was driven in a second flushing mode in which a second flushing operation is performed in which an amount of liquid different from the predetermined amount is ejected from a plurality of ejection units including the first ejection unit, thereby making it possible to grasp in detail the state of the second ejection unit in addition to the first ejection unit. [Explanation of symbols]

[0225] 1...liquid ejection device, 5...ink container, 10...control mechanism, 20...ejection mechanism, 21...print head, 21-1 to 21-7...print heads, 40...transport mechanism, 41...transport motor, 42...transport roller, 50...drive circuit, 52...reference voltage circuit, 60...piezoelectric element, 100...control circuit, 200...drive signal selection circuit, 210...selection control circuit, 222a...first register, 222b...second register, 224a...first latch circuit, 224b...second latch circuit, 226...decoder , 230... selection circuit, 260... control logic circuit, 262... SP register group, 264... selection control signal generation unit, 270... selection signal output unit, 300... discharge count circuit, 310... count circuit, 320... memory circuit, 600... discharge unit, 601... piezoelectric body, 611, 612... electrodes, 621... vibration plate, 631... cavity, 632... nozzle plate, 641... reservoir, 651... nozzle, 661... supply port, INV... inverter, P... medium, TG... transfer gate

Claims

1. A drive circuit that outputs a drive signal including a plurality of drive signal waveforms; A control circuit that outputs a discharge control signal; a first selection circuit that selects the plurality of drive signal waveforms based on the ejection control signal and outputs the selected drive signal waveform as a first drive voltage; a first ejection unit including a first piezoelectric element that is driven by the first driving voltage and that ejects liquid by driving the first piezoelectric element; a discharge count circuit to which the discharge control signal is input; Equipped with the control circuit outputs the ejection control signal including selection rule data that sets a selection rule for the plurality of drive signal waveforms in the first selection circuit, and first drive data that controls selection of the plurality of drive signal waveforms in the first selection circuit based on the selection rule data; the ejection count circuit stores, as a first drive count, the number of times that the first piezoelectric element has been driven by the first drive voltage of the first drive voltage waveform output by the first selection circuit; A liquid ejection device comprising:

2. the ejection count circuit stores, as a second drive count, the number of times that the first piezoelectric element has been driven by the first drive voltage having a second drive voltage waveform different from the first drive voltage waveform output by the first selection circuit; The liquid ejection device according to claim 1 .

3. a second selection circuit that selects the plurality of drive signal waveforms based on the ejection control signal and outputs the selected waveform as a second drive voltage; a second ejection section including a second piezoelectric element that is driven by the second driving voltage and that ejects liquid by driving the second piezoelectric element; Equipped with the control circuit outputs the ejection control signal including second drive data for controlling selection of the plurality of drive signal waveforms in the second selection circuit based on the selection rule data; the ejection count circuit stores the number of times that the second piezoelectric element has been driven by the second drive voltage of the third drive voltage waveform output by the second selection circuit as a third drive number; The liquid ejection device according to claim 1 .

4. The drive circuit includes: In a first operating mode, a first drive signal including a plurality of first drive signal waveforms is output as the drive signal; In a second operating mode, a second drive signal including a plurality of second drive signal waveforms is output as the drive signal; The control circuit includes: In the first operation mode, the ejection control signal is output, the ejection control signal including first selection rule data that sets a selection rule for the plurality of first drive signal waveforms in the first selection circuit as the selection rule data; In the second operation mode, the ejection control signal is output, the ejection control signal including, as the selection rule data, second selection rule data that sets a selection rule for the plurality of second drive signal waveforms in the first selection circuit; The discharge count circuit includes: In the first operation mode, the number of times that the first piezoelectric element is driven by the first drive voltage of the fourth drive voltage waveform output by the first selection circuit is stored as a fourth drive number, In the second operation mode, the number of times that the first piezoelectric element is driven by the first drive voltage of the fifth drive voltage waveform output by the first selection circuit is stored as a fifth drive number. The liquid ejection device according to claim 1 .

5. a gradient of dots formed on a medium by the liquid ejected by the first ejection unit in the first operation mode is different from a gradient of dots formed on a medium by the liquid ejected by the first ejection unit in the second operation mode; 5. The liquid ejection device according to claim 4.

6. In a first flushing mode in which a first flushing operation is performed to eject a predetermined amount of liquid from a plurality of ejection parts including the first ejection part, the control circuit outputs the ejection control signal including first flushing selection rule data corresponding to the first flushing operation as the selection rule data, and the number of times that the first piezoelectric element has been driven by the first flushing operation is stored in the ejection count circuit as a sixth drive number, In a second flushing mode in which a second flushing operation is performed in which an amount of liquid different from the predetermined amount is discharged from the plurality of discharge parts including the first discharge part, the control circuit outputs the discharge control signal including second flushing selection rule data corresponding to the second flushing operation as the selection rule data, and the number of times the first piezoelectric element has been driven by the second flushing operation is stored in the discharge count circuit as a seventh drive number. The liquid ejection device according to claim 1 .

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