Switching element and manufacturing method of them

Abstract

To provide a switching element having a field relaxation layer, capable of reducing a channel resistance.SOLUTION: A switching element includes: a gate insulation film and a gate electrode that are arranged in a trench. A semiconductor substrate includes: a source layer, a body layer, nad a drift layer that are contacted to the gate insulation film on the side surface of the trench. The semiconductor substrate includes a field relaxation layer arranged to the lower part of the bottom surface of the trench. An angle A on the side surface against a substrate flat surface is defined that it is measured in a direction that it becomes A>90° when the side surface becomes a reverse taper. In at least one part within a range where the source layer is contacted to the gate insulation film, A>90° is satisfied. In a range where the body layer is contacted to the gate insulation film, a range containing the lower end of the body layer is 87°≤A≤90°. In a range where the drift layer is contacted to the gate insulation film, it is A≤90°.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a switching element and a manufacturing method thereof.

[0002] Patent Document 1 discloses a switching element having a trench-type gate electrode. Patent Document 1 also discloses that an electric field relaxation layer (also called a bottom protection layer) is formed at the bottom of the trench by injecting impurities into the bottom of the trench. By forming the electric field relaxation layer at the bottom of the trench, the electric field strength in the vicinity of the bottom of the trench can be reduced. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-253929 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the process of forming the electric field relaxation layer, impurities are implanted not only into the bottom surface of the trench but also into the side surface of the trench. The side surface of the trench within the range of the body layer is the region where the channel is formed. Therefore, when impurities are implanted into the side surface of the trench, the channel resistance of the switching element increases. In this specification, a technology is proposed for reducing the channel resistance in a switching element having an electric field relaxation layer. [Means for solving the problem]

[0005] The switching element disclosed in this specification includes a semiconductor substrate having a trench on its upper surface, a gate insulating film covering the inner surface of the trench, and a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate includes a source layer of a first conductivity type in contact with the gate insulating film on a side surface of the trench, a body layer of a second conductivity type in contact with the gate insulating film on the side surface below the source layer, a drift layer of a first conductivity type in contact with the gate insulating film on the side surface below the body layer, and an electric field relaxation layer of a second conductivity type disposed below the bottom surface of the trench. When the angle A of the side surface with respect to the substrate plane is defined as being measured in a direction such that A>90° when the side surface is inversely tapered, the following condition is satisfied, i.e., A>90° in at least a part of the area where the source layer is in contact with the gate insulating film; Within a range including a lower end of the body layer within a range in which the body layer contacts the gate insulating film, 87°≦A≦90°. Within the range where the drift layer contacts the gate insulating film, A≦90°; The following condition is satisfied.

[0006] In this specification, the substrate plane means a plane parallel to the upper surface of the semiconductor substrate. In addition, in this specification, one of the first and second conductivity types is n-type, and the other is p-type.

[0007] In this switching element, an inverted tapered portion with A>90° is formed on at least a part of the side of the trench within the source layer. Therefore, when impurities are injected into the bottom surface of the trench, the side of the trench within the body layer is in the shadow of the inverted tapered portion. This suppresses the injection of impurities into the side of the trench within the body layer. In addition, a portion with 87°≦A≦90° (i.e., approximately perpendicular to the substrate plane) is provided on the side of the trench within the body layer, so that the channel length is short. Therefore, according to the structure of this switching element, the channel resistance can be reduced.

[0008] This specification also discloses a method for manufacturing a switching element. The manufacturing method includes a trench forming step, an electric field relaxation layer forming step, and a gate electrode forming step. In the trench forming step, a trench is formed in a surface of a semiconductor substrate having a source layer of a first conductivity type, a body layer of a second conductivity type located below the source layer, and a drift layer of a first conductivity type located below the body layer, penetrating the source layer and the body layer to reach the drift layer. In the trench forming step, when the angle A of the side surface with respect to the substrate plane is defined as being measured in a direction such that A>90° when the side surface is inversely tapered, the following condition is satisfied, namely: A>90° in at least a part of the area where the source layer is exposed on the side surface; Within the range in which the body layer is exposed to the side surface, including the lower end of the body layer, 87°≦A≦90°. Within the range where the drift layer is exposed on the side surface, A≦90°; The trench is formed so as to satisfy the condition: In the electric field buffer layer forming step, a second conductive type impurity is ion-implanted into the bottom surface of the trench to form a second conductive type electric field buffer layer below the bottom surface of the trench; In the gate electrode forming step, a gate insulating film covering the inner surface of the trench and a gate electrode insulated from the semiconductor substrate by the gate insulating film are formed in the trench.

[0009] In this manufacturing method, in the electric field relaxation layer forming step, the inverted tapered portion suppresses impurity injection into the side surface of the trench within the body layer. Also, since the side surface of the trench within the body layer is provided with a portion that satisfies 87°≦A≦90° (i.e., approximately perpendicular to the substrate plane), the channel length can be shortened. Therefore, this manufacturing method can manufacture a switching element with low channel resistance. [Brief description of the drawings]

[0010] [Figure 1] FIG. [Diagram 2] FIG. [Diagram 3] 3A to 3C are explanatory diagrams of a manufacturing process of the switching element 10. [Figure 4] 3A to 3C are explanatory diagrams of a manufacturing process of the switching element 10. [Diagram 5] 3A to 3C are explanatory diagrams of a manufacturing process of the switching element 10. [Figure 6] 3A to 3C are explanatory diagrams of a manufacturing process of the switching element 10. [Figure 7] 3A to 3C are explanatory diagrams of a manufacturing process of the switching element 10. [Figure 8] 3A to 3C are explanatory diagrams of a manufacturing process of the switching element 10. [Figure 9] 3A to 3C are explanatory diagrams of a manufacturing process of the switching element 10. [Figure 10] FIG. 4 is a cross-sectional view of a switching element according to a first modified example. [Figure 11] FIG. 11 is a cross-sectional view of a switching element according to a second modified example. [Figure 12] FIG. 13 is a cross-sectional view of a switching element according to a third modified example. [Figure 13] FIG. 13 is a cross-sectional view of a switching element according to a fourth modified example. [Figure 14] FIG. 13 is a cross-sectional view of a switching element according to a fifth modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In one example switching element disclosed in this specification, a shoulder portion located at the boundary between the top surface of the semiconductor substrate and the side surface of the trench may have a curved shape connecting the top surface of the semiconductor substrate and the side surface of the trench.

[0012] According to this configuration, the gate electrode can be suitably formed in the trench.

[0013] In one example switching element disclosed in this specification, a corner portion located at the boundary between the side surface of the trench and the bottom surface of the trench may have a curved shape connecting the side surface of the trench and the bottom surface of the trench.

[0014] According to this configuration, the gate electrode can be suitably formed in the trench.

[0015] In the switching element disclosed in the present specification, the width of the opening of the trench may be narrower than the width of the bottom surface of the trench.

[0016] According to this configuration, the implantation of impurities into the side surface of the trench can be more effectively suppressed.

[0017] In the switching element disclosed in the present specification as an example, A may be such that 87°≦A≦90° is satisfied throughout the entire area in which the body layer is in contact with the gate insulating film.

[0018] According to this configuration, the channel length can be made shorter.

[0019] The switching element 10 of the embodiment shown in FIG. 1 is a so-called MOSFET (metal-oxide-semiconductor field effect transistor). The switching element 10 has a semiconductor substrate 12. The semiconductor substrate 12 is made of silicon carbide. However, the semiconductor substrate 12 may be made of other semiconductor materials (e.g., silicon, gallium nitride, diamond, etc.). A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. The plurality of trenches 14 extend in parallel on the upper surface 12a. The inner surface of each trench 14 is covered with a gate insulating film 17. A gate electrode 18 is disposed in each trench 14. The gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 17. An interlayer insulating film 20 is provided in each trench 14 and above the gate electrode 18. The interlayer insulating film 20 covers the upper surface of the gate electrode 18. A source electrode 22 is provided on the upper portion of the semiconductor substrate 12. The source electrode 22 covers the upper surface 12a of the semiconductor substrate 12 and the upper surface of the interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. A drain electrode 24 is provided on the lower part of the semiconductor substrate 12. The drain electrode 24 covers the lower surface 12b of the semiconductor substrate 12.

[0020] The semiconductor substrate 12 includes a source layer 30, a body layer 32, a drift layer , a plurality of electric field relaxation layers , and a drain layer .

[0021] The source layer 30 is an n-type layer, and is provided in a range including the upper surface 12a of the semiconductor substrate 12. The source layer 30 is in ohmic contact with the source electrode 22. The source layer 30 is in contact with the gate insulating film 17 at the upper end of the side surface 15 of the trench 14.

[0022] The body layer 32 is a p-type layer and is disposed below the source layer 30. The body layer 32 is connected to the source electrode 22 by a p-type layer provided at a position not shown. Therefore, the body layer 32 has approximately the same potential as the source electrode 22. The body layer 32 is in contact with the gate insulating film 17 in an area of ​​the side surface 15 of the trench 14 below the source layer 30.

[0023] The drift layer 34 is an n-type layer and has a lower n-type impurity concentration than the source layer 30. The drift layer 34 is disposed below the body layer 32. The drift layer 34 is distributed across the lower parts of the multiple trenches 14. The drift layer 34 is in contact with the gate insulating film 17 in a range of the side surface 15 of the trench 14 below the body layer 32.

[0024] Each electric field relaxation layer 36 is a p-type layer, and is disposed below the corresponding trench 14. Each electric field relaxation layer 36 contacts the gate insulating film 17 at the bottom surface 16 of the corresponding trench 14. The drift layer 34 contacts the side and bottom surfaces of each electric field relaxation layer 36.

[0025] The drain layer 38 is an n-type layer and has a higher n-type impurity concentration than the drift layer 34. The drain layer 38 is disposed below the drift layer 34. The drain layer 38 is in ohmic contact with the drain electrode 24 on the lower surface 12b of the semiconductor substrate 12.

[0026] A substrate plane P indicated by a dashed line in Fig. 2 is a virtual plane parallel to the upper surface 12a of the semiconductor substrate 12. The substrate plane P can also be said to be a plane perpendicular to the thickness direction of the semiconductor substrate 12. Angle A in Fig. 2 indicates the angle of the side surface 15 of the trench 14 with respect to the substrate plane P. The angle A is measured in a direction in which the angle A is greater than 90° when the side surface 15 has an overhang shape (i.e., when the upper portion of the side surface 15 is located closer to the center of the trench 14 than the lower portion). In other words, an angle A greater than 90° means that the side surface 15 is inversely tapered, and an angle A smaller than 90° means that the side surface 15 is forwardly tapered.

[0027] As shown in FIG. 2, the angle A of the side surface 15 varies depending on the position. The side surface 15 has an inverse tapered portion 15a, a vertical portion 15b, and a forward tapered portion 15c. In the inverse tapered portion 15a, the angle A is greater than 90°. In the vertical portion 15b, the angle A is substantially equal to 90° (i.e., 87°≦A≦90°). In the forward tapered portion 15c, the angle A is smaller than 87°. The inverse tapered portion 15a is provided in a range of the side surface 15 where the source layer 30 contacts the gate insulating film 17. The vertical portion 15b is disposed below the inverse tapered portion 15a. The vertical portion 15b is provided in a range of the side surface 15 where the body layer 32 contacts the gate insulating film 17. The forward tapered portion 15c is disposed below the vertical portion 15b. The forward tapered portion 15c is provided in a range of the side surface 15 where the drift layer 34 contacts the gate insulating film 17. Vertical portion 15b and forward tapered portion 15c are disposed further outward in the width direction of trench 14 than the upper end of reverse tapered portion 15a. Therefore, width W1 of the opening of trench 14 is narrower than width W2 of bottom surface 16 of trench 14.

[0028] When the switching element 10 is used, a potential higher than that of the source electrode 22 is applied to the drain electrode 24. When a potential higher than the gate threshold is applied to the gate electrode 18, a channel is formed in the body layer 32 near the gate insulating film 17. Therefore, electrons flow from the source layer 30 to the drift layer 34 through the channel. That is, the switching element 10 is turned on. Since the vertical portion 15b is provided on the side surface 15 of the trench 14 in the body layer 32, the length of the channel is short. This reduces the channel resistance of the switching element 10. When the potential of the gate electrode 18 is reduced to less than the gate threshold, the channel disappears and the switching element 10 is turned off. Then, a depletion layer extends from the body layer 32 and the electric field relaxation layer 36 to the drift layer 34. The voltage applied between the drain electrode 24 and the source electrode 22 is held by the depletion layer in the drift layer 34. In the switching element 10, a depletion layer extends from the electric field relaxation layer 36 to the drift layer 34 near the bottom surface 16 of the trench 14, so that electric field concentration near the bottom surface 16 is suppressed. In addition, a forward tapered portion 15c is provided at the bottommost portion of the side surface 15 of the trench 14, so that a corner portion 92 at the lower end of the trench 14 (i.e., a corner portion 92 located at the boundary between the side surface 15 and the bottom surface 16) has an obtuse angle. This also suppresses electric field concentration near the bottom surface 16. Therefore, the switching element 10 has a high withstand voltage.

[0029] Next, a method for manufacturing the switching element 10 will be described. The switching element 10 is manufactured from the semiconductor substrate 12 shown in Fig. 3 (i.e., the semiconductor substrate 12 before trenches are formed). At this stage, a source layer 30, a body layer 32, a drift layer 34, and a drain layer 38 are provided inside the semiconductor substrate 12. The body layer 32 is located below the source layer 30, the drift layer 34 is located below the body layer 32, and the drain layer 38 is located below the drift layer 34.

[0030] (Trench formation process) In the manufacturing method of this embodiment, first, a trench forming step is performed. In the trench forming step, as shown in FIG. 4, an etching mask 100 is formed on the upper surface 12a of the semiconductor substrate 12. Then, anisotropic etching (e.g., reactive ion etching) is performed on the upper surface 12a through the etching mask 100 to form a shallow trench 14. The formed shallow trench 14 corresponds to the upper portion of the trench 14 shown in FIG. 1. Next, chemical dry etching is performed on the inner surface of the trench 14 to enlarge the trench 14 as shown in FIG. 5. At this time, by adjusting the conditions of the chemical dry etching, an inverse tapered portion 15a is formed on the side surface of the trench 14. Next, as shown in FIG. 6, anisotropic etching is performed on the bottom surface of the trench 14 to increase the depth of the trench 14. Here, a vertical portion 15b is formed by adjusting the conditions of the anisotropic etching so that the angle A of the side surface of the trench 14 below the inverse tapered portion 15a is 87°≦A≦90°. Next, as shown in FIG. 7, the anisotropic etching is continued to increase the depth of the trench 14. Here, the conditions of the anisotropic etching are adjusted so that the angle A of the side surface of the trench 14 below the vertical portion 15b is A<87°, thereby forming a forward tapered portion 15c. This completes the trench 14 that penetrates from the upper surface 12a through the source layer 30 and the body layer 32 to reach the drift layer 34. Here, the trench 14 is formed so that the reverse tapered portion 15a is formed in the range where the source layer 30 is exposed on the side surface 15 of the trench 14, the vertical portion 15b is formed in the range where the body layer 32 is exposed, and the forward tapered portion 15c is formed in the range where the drift layer 34 is exposed.

[0031] (Field relaxation layer formation process) Next, an electric field relaxation layer forming step is performed. In the electric field relaxation layer forming step, as shown in FIG. 8, a protective film 102 against ion implantation is formed on the upper surface 12a of the semiconductor substrate 12. If there is no problem even if impurities are implanted into the upper surface 12a, the protective film 102 may not be formed. Next, p-type impurity ions are irradiated along a direction perpendicular to the upper surface 12a of the semiconductor substrate 12. As a result, p-type impurities are ion-implanted into the bottom surface 16 of each trench 14 to form an electric field relaxation layer 36. Since the inverse tapered portion 15a is provided on the upper portion of the vertical portion 15b, the vertical portion 15b is in the shadow of the inverse tapered portion 15a during ion implantation. Therefore, the injection of p-type impurities into the vertical portion 15b (i.e., the body layer 32) is suppressed. In particular, since the width W1 of the opening of the trench 14 is narrower than the width W2 of the bottom surface 16 of the trench 14 as shown in FIG. 2, the injection of p-type impurities into the vertical portion 15b and the forward tapered portion 15c is effectively suppressed. As described above, the body layer 32 in the vicinity of the trench 14 is a region where a channel is formed (hereinafter, referred to as a channel formation region). In the electric field relaxation layer forming process of this embodiment, the injection of p-type impurities into the channel formation region is suppressed, so that an increase in channel resistance can be suppressed. In addition, by suppressing the injection of p-type impurities into the channel formation region, the variation in the gate threshold can also be suppressed.

[0032] In addition, in order to further suppress the injection of p-type impurities into the channel formation region, a protective film (e.g., an oxide film) may be formed on the side surface 15 of the trench 14, and the electric field relaxation layer formation process may be performed in a state in which the side surface 15 is covered with the protective film.

[0033] (Gate electrode formation process) Next, a gate electrode forming process is performed. In the gate electrode forming process, as shown in FIG. 9, a gate insulating film 17 is formed to cover the inner surface of the trench 14. Next, an electrode material is deposited and etched back to form a gate electrode 18 in the trench 14. Since the side surface 15 of the trench 14 is not inversely tapered in the lower part of the inverse tapered portion 15a (i.e., the vertical portion 15b and the forward tapered portion 15c), the electrode material can be suitably deposited in the trench 14. Therefore, the gate electrode 18 can be formed without gaps in the trench 14. After the gate electrode 18 is formed, an interlayer insulating film 20 is formed on the gate electrode 18.

[0034] After the gate electrode formation step, the source electrode 22 and the drain electrode 24 are formed, thereby completing the switching element 10 shown in FIG.

[0035] As described above, in this manufacturing method, it is possible to suppress the injection of impurities into the side surface 15 within the range of the body layer 32 in the electric field relaxation layer formation step. In addition, since the vertical portion 15b is formed on the side surface 15 within the range of the body layer 32, it is possible to shorten the channel length. Therefore, it is possible to manufacture a switching element 10 with low channel resistance.

[0036] 10, shoulder 90 located at the boundary between upper surface 12a and side surface 15 of trench 14 may have a curved shape (e.g., an arc shape) that smoothly connects upper surface 12a and side surface 15. This configuration makes it easier to fill trench 14 with an electrode material in the gate electrode formation step.

[0037] 11, corner portion 92 located at the boundary between side surface 15 and bottom surface 16 of trench 14 may have a curved shape (e.g., an arc shape) that smoothly connects side surface 15 and bottom surface 16. This configuration makes it easier to fill the trench 14 with an electrode material in the gate electrode formation step. Also, this configuration makes it possible to more effectively suppress electric field concentration in the vicinity of corner portion 92.

[0038] 2, the reverse tapered portion 15a is provided over the entire range of the source layer 30 on the side surface 15, the vertical portion 15b is provided over the entire range of the body layer 32 on the side surface 15, and the forward tapered portion 15c is provided over the entire range of the drift layer 34 on the side surface 15. However, A>90° in at least a part of the area where the source layer 30 is in contact with the gate insulating film 17; Within a range in which the body layer 32 is in contact with the gate insulating film 17 and which includes the lower end 32 a of the body layer 32, 87°≦A≦90° is satisfied. A≦90° in the range where the drift layer 34 contacts the gate insulating film 17. As long as this condition is satisfied, the shape of the side surface 15 is arbitrary.

[0039] 12, for example, the reverse tapered portion 15a may be provided across from the source layer 30 to the upper part of the body layer 32. In the configuration of Fig. 12, in a range R1 including the lower end 32a of the body layer 32, the angle A of the side surface 15 is 87°≦A≦90°.

[0040] 13, the inverted tapered portion 15a may be provided in a part of the range of the source layer 30. In the configuration of FIG. 13, in a part R2 in the range where the source layer 30 contacts the gate insulating film 17, the angle A of the side surface 15 is A>90°.

[0041] 14, vertical portion 15b may be provided across body layer 32 and drift layer 34. In the configuration of FIG. 14, in range R3 where drift layer 34 contacts gate insulating film 17, angle A of side surface 15 is A≦90°.

[0042] The technology disclosed in this specification may also be applied to an IGBT (insulated gate bipolar transistor).

[0043] The configurations of the techniques disclosed in this specification are listed below. (Configuration 1) A switching element, A semiconductor substrate (12) having a trench (14) formed on an upper surface (12a); a gate insulating film (17) covering the inner surface of the trench; a gate electrode (18) disposed in the trench and insulated from the semiconductor substrate by the gate insulating film; having The semiconductor substrate is a first conductivity type source layer (30) in contact with the gate insulating film on a side surface of the trench; a body layer (32) of a second conductivity type contacting the gate insulating film at the side surface below the source layer; a drift layer (34) of a first conductivity type contacting the gate insulating film at the side surface below the body layer; an electric field relaxation layer (36) of a second conductivity type in contact with the gate insulating film at the bottom surface of the trench; having When the angle A of the side surface with respect to the substrate plane is defined as being measured in a direction such that A>90° when the side surface is inversely tapered, the following condition is satisfied: A>90° in at least a part of the area where the source layer is in contact with the gate insulating film, Within a range including a lower end of the body layer within a range in which the body layer is in contact with the gate insulating film, 87°≦A≦90°; A≦90° in the range where the drift layer is in contact with the gate insulating film. A switching element that satisfies the above conditions. (Configuration 2) The switching element of configuration 1, wherein a shoulder portion (90) located at the boundary between the top surface of the semiconductor substrate and the side surface of the trench has a curved shape connecting the top surface of the semiconductor substrate and the side surface of the trench. (Configuration 3) 3. The switching element according to claim 1 or 2, wherein a corner portion (92) located at the boundary between the side surface of the trench and the bottom surface of the trench has a curved shape connecting the side surface of the trench and the bottom surface of the trench. (Configuration 4) 4. The switching element according to any one of configurations 1 to 3, wherein a width (W1) of the opening of the trench is narrower than a width (W2) of the bottom surface of the trench. (Configuration 5) 5. The switching element according to any one of configurations 1 to 4, wherein within the entire area where the body layer is in contact with the gate insulating film, 87°≦A≦90°.

[0044] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0045] 14: trench, 15a: inverse tapered portion, 15b: vertical portion, 15c: forward tapered portion, 16: gate insulating film, 18: gate electrode, 30: source layer, 32: body layer, 34: drift layer

Claims

1. A switching element, A semiconductor substrate (12) having a trench (14) on an upper surface (12a); A gate insulating film (17) covering the inner surface of the trench; a gate electrode (18) disposed in the trench and insulated from the semiconductor substrate by the gate insulating film; having The semiconductor substrate is a first conductive type source layer (30) contacting the gate insulating film on a side surface of the trench; a body layer (32) of a second conductivity type contacting the gate insulating film at the side surface below the source layer; a drift layer (34) of a first conductivity type contacting the gate insulating film at the side surface below the body layer; a second conductivity type electric field relaxation layer (36) disposed on a lower portion of the bottom surface of the trench; having If the angle A of the side surface with respect to the substrate plane is defined as being measured in a direction such that A>90° when the side surface is inversely tapered, then the following condition must be satisfied: A>90° in at least a part of the area where the source layer is in contact with the gate insulating film; Within a range including a lower end of the body layer within a range in which the body layer is in contact with the gate insulating film, 87°≦A≦90°. In the range where the drift layer contacts the gate insulating film, A≦90°. A switching element that satisfies the above conditions.

2. 2. The switching element of claim 1, wherein a shoulder portion (90) located at the boundary between the upper surface of the semiconductor substrate and the side surface of the trench has a curved shape connecting the upper surface of the semiconductor substrate and the side surface of the trench.

3. 3. The switching element according to claim 1, wherein a corner portion (92) located at the boundary between the side surface of the trench and the bottom surface of the trench has a curved shape connecting the side surface of the trench and the bottom surface of the trench.

4. 3. The switching element according to claim 1, wherein a width (W1) of an opening of the trench is narrower than a width (W2) of the bottom surface of the trench.

5. 3. The switching element according to claim 1, wherein A satisfies 87°≦A≦90° in the entire area where the body layer is in contact with the gate insulating film.

6. A method for manufacturing a switching element, comprising the steps of: A process for forming a trench in a surface of a semiconductor substrate having a source layer of a first conductivity type, a body layer of a second conductivity type located below the source layer, and a drift layer of the first conductivity type located below the body layer, the trench penetrating the source layer and the body layer to reach the drift layer, If the angle A of the side surface with respect to the substrate plane is defined as being measured in a direction such that A>90° when the side surface is inversely tapered, then the following condition must be satisfied: A>90° in at least a part of the range in which the source layer is exposed on the side surface; Within a range including a lower end of the body layer within the range in which the body layer is exposed to the side surface, 87°≦A≦90°. Within the range in which the drift layer is exposed on the side surface, A≦90°; forming the trench so as to satisfy the condition: forming a second conductivity type electric field relaxation layer below the bottom surface of the trench by ion-implanting a second conductivity type impurity into the bottom surface of the trench; forming, in the trench, a gate insulating film covering an inner surface of the trench, and a gate electrode insulated from the semiconductor substrate by the gate insulating film; The manufacturing method comprising the steps of:

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