Photodetector

Abstract

To suppress the increase of parasitic capacitance caused by a gate electrode.SOLUTION: A photodetector comprises a semiconductor substrate including a photoelectric conversion part, a floating diffusion formed from the surface of the semiconductor substrate to the interior of the semiconductor substrate, and a transistor provided on the semiconductor substrate, and the transistor includes a gate electrode embedded in the semiconductor substrate so that the surface is substantially flush with the surface of the semiconductor substrate.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a light detection device. [Background technology]

[0002] For example, Patent Document 1 discloses an image sensor in which a part of a gate electrode is embedded in a semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-146934 A Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the remaining part of the gate electrode is located above the surface of the semiconductor substrate, and a step occurs. This can cause various problems. For example, as miniaturization progresses, parasitic capacitance occurring between the electrode and the via becomes apparent. If these electrodes and vias are provided for the floating diffusion, the capacitance of the floating diffusion increases, and the effect of noise becomes greater. In addition, if a dummy electrode is provided on the surface of the semiconductor substrate in the latter region to fill the gap between a region where the steps are dense and a region where they are not, parasitic capacitance also occurs between the dummy electrode and other wiring.

[0005] One aspect of the present disclosure is to suppress an increase in parasitic capacitance caused by a gate electrode. [Means for solving the problem]

[0006] A photodetection device according to one aspect of the present disclosure includes a semiconductor substrate including a photoelectric conversion unit, a floating diffusion formed inside the semiconductor substrate from a surface of the semiconductor substrate, and a transistor provided in the semiconductor substrate, the transistor including a gate electrode embedded in the semiconductor substrate so as to have a surface substantially flush with the surface of the semiconductor substrate. [Brief description of the drawings]

[0007] [Figure 1] 1 is a diagram illustrating an example of a schematic configuration of a photodetector according to an embodiment. [Diagram 2] FIG. 2 is a diagram illustrating an example of a pixel circuit. [Diagram 3] FIG. 1 is a diagram illustrating an example of a schematic configuration of a light detection device. [Figure 4] FIG. [Diagram 5] FIG. 1 illustrates an example of a substantially flush configuration. [Figure 6] FIG. 2 is a diagram illustrating an example of a pixel circuit. [Figure 7] FIG. 1 is a diagram illustrating an example of a schematic configuration of a light detection device. [Figure 8] FIG. 1 is a diagram illustrating an example of a schematic configuration of a light detection device. [Figure 9] FIG. 1 is a diagram illustrating an example of a schematic configuration of a light detection device. [Figure 10] FIG. 1 is a diagram illustrating an example of a schematic configuration of a light detection device. [Figure 11] FIG. 1 is a diagram illustrating an example of a schematic configuration of a light detection device. [Figure 12] FIG. 1 is a diagram illustrating an example of a schematic configuration of a light detection device. [Figure 13] FIG. 1 is a diagram illustrating an example of a schematic configuration of a light detection device. [Figure 14] FIG. 1 is a diagram illustrating an example of a schematic configuration of a light detection device. [Figure 15] FIG. 1 is a diagram illustrating an example of a schematic configuration of a light detection device. [Figure 16] FIG. 1 is a diagram illustrating an example of a schematic configuration of a light detection device. [Figure 17] FIG. 1 is a diagram illustrating an example of a schematic configuration of a light detection device. [Figure 18] 1A to 1C are diagrams illustrating an example of a method for manufacturing a light detection device. [Figure 19] 1A to 1C are diagrams illustrating an example of a method for manufacturing a light detection device. [Figure 20] 1A to 1C are diagrams illustrating an example of a method for manufacturing a light detection device. [Figure 21] 1A to 1C are diagrams illustrating an example of a method for manufacturing a light detection device. [Figure 22] 1A to 1C are diagrams illustrating an example of a method for manufacturing a light detection device. [Figure 23] 1A to 1C are diagrams illustrating an example of a method for manufacturing a light detection device. [Figure 24] 1A to 1C are diagrams illustrating an example of a method for manufacturing a light detection device. [Diagram 25] 1A to 1C are diagrams illustrating an example of a method for manufacturing a light detection device. [Figure 26] 1A to 1C are diagrams illustrating an example of a method for manufacturing a light detection device. [Figure 27] FIG. 13 is a diagram showing an example of sharing a pixel circuit. [Figure 28] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 29] 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same elements are designated by the same reference numerals, and duplicated descriptions will be omitted.

[0009] The present disclosure will be described in the following order. 1. Embodiment 2. Variations 2.1 First modified example 2.2 Second variant 2.3 Third variant 2.4 Application Examples 3.Examples of manufacturing methods 4. Example of common pixel circuit 5. Summary 6. Mobile application examples

[0010] 1. Embodiment 1 is a diagram showing an example of a schematic configuration of a photodetector according to an embodiment. The photodetector 90 shown is a solid-state imaging device (also called an image sensor, etc.), and each element is provided in and on a semiconductor substrate, for example, of silicon. The photodetector 90 includes a photodetection region 91, a control circuit 93, a vertical drive circuit 94, a column signal processing circuit 95, a horizontal drive circuit 96, an output circuit 97, a signal line 98H, a signal line 98V, and a signal line 99.

[0011] The photodetection region 91 is a pixel region including a plurality of pixels 92, and may also be called a pixel array portion or the like. The plurality of pixels 92 are arranged in a two-dimensional array. FIG. 1 also shows an XYZ coordinate system for the photodetection region 91. The X-axis direction corresponds to the row direction of the array, for example, the lateral direction (horizontal direction) of the photodetection device 90. The Y-axis direction corresponds to the column direction of the array, for example, the longitudinal direction (vertical direction) of the photodetection device 90. The Z-axis direction corresponds to the front-rear direction (up-down direction) of the photodetection device 90, for example.

[0012] The photodetector 90 detects light incident on the photodetection region 91. Unless otherwise specified, the photodetector 90 is assumed to be a back-illuminated photodetector that detects light traveling in the positive direction of the Z axis (light incident from behind).

[0013] The pixel 92 includes a photoelectric conversion unit. The photoelectric conversion unit generates an electric charge according to the amount of incident light. An example of the photoelectric conversion unit is a photodiode (PD: Photo Diode). A circuit is also provided that generates and outputs a voltage signal (pixel signal) according to the amount of electric charge generated in the photoelectric conversion unit. The pixel 92 may be interpreted to include such a circuit, and in this case, the pixel 92 may also be called a pixel circuit.

[0014] The control circuit 93, the vertical drive circuit 94, the column signal processing circuit 95, the horizontal drive circuit 96, and the output circuit 97 constitute peripheral circuits of the photodetection region 91. The region in which these circuits are arranged is referred to as a peripheral region SR (see FIG. 3, etc., described below).

[0015] The control circuit 93 receives data instructing an input clock, an operation mode, etc., and outputs data such as internal information of the photodetector 90. The control circuit 93 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 94, the column signal processing circuit 95, the horizontal drive circuit 96, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. The control circuit 93 inputs (supplies) these generated signals to the vertical drive circuit 94, the column signal processing circuit 95, the horizontal drive circuit 96, etc.

[0016] The vertical drive circuit 94 includes, for example, a shift register. The vertical drive circuit 94 is connected to the photodetection region 91 via a plurality of signal lines 98H (horizontal signal lines) extending in the row direction (X-axis direction) of the pixels 92. Each signal line 98H extends, for example, for each pixel row, and each signal line 98H may include a plurality of signal lines. The vertical drive circuit 94 supplies a drive signal (for example, a pulse signal) for driving the pixels 92 to a selected signal line 98H.

[0017] Driving the pixels 92 by the vertical drive circuit 94 includes driving a pixel transistor (transistor 1 in FIG. 2) described later. The pixel transistor is driven to output a voltage signal (pixel signal) according to the amount of charge generated in a photoelectric conversion unit in the pixel 92 to a corresponding signal line 98V among a plurality of signal lines 98V (vertical signal lines) extending in the column direction (Y-axis direction) of the pixels 92.

[0018] The column signal processing circuit 95 is connected to the photodetection region 91 via a signal line 98V. Each signal line 98V may include a plurality of signal lines. The column signal processing circuit 95 is arranged, for example, for each pixel column, and performs signal processing such as noise removal for each pixel column on pixel signals from one row of pixels 92. The column signal processing circuit 95 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to the pixels 92, signal amplification, AD (Analog to Digital) conversion, etc. A horizontal selection switch (not shown) is connected between the output stage of the column signal processing circuit 95 and the signal line 98V.

[0019] The horizontal drive circuit 96 includes, for example, a shift register. The horizontal drive circuit 96 sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 95 in turn, and causes each of the column signal processing circuits 95 to output a pixel signal to a signal line 99.

[0020] The output circuit 97 processes and outputs pixel signals sequentially supplied from each of the column signal processing circuits 95 through a signal line 99. For example, buffering, black level adjustment, column variation correction, various digital signal processing, etc. are performed.

[0021] Fig. 2 is a diagram showing an example of a pixel circuit. A photoelectric conversion unit included in a pixel 92 is illustrated and referred to as a photoelectric conversion unit 3. As described above, the photoelectric conversion unit 3 generates charges according to the amount of incident light. In Fig. 2, the photoelectric conversion unit 3 is shown as a photodiode with an anode connected to GND (ground).

[0022] A plurality of transistors 1 and a floating diffusion 2 are exemplified as elements of a circuit (pixel circuit) provided around the photoelectric conversion unit 3. The transistors 1 can also be called pixel transistors.

[0023] Four transistors are exemplified as the plurality of transistors 1. In order to distinguish between the transistors, they are referred to as transistor 1-1, transistor 1-2, transistor 1-3, and transistor 1-4 in the drawings. When there is no need to distinguish between them, they are simply referred to as transistor 1.

[0024] The gate electrodes of several transistors 1 are illustrated with reference numbers. The gate electrode of transistor 1-1 is referred to as gate electrode 11-1 and illustrated. The gate electrode of transistor 1-2 is referred to as gate electrode 11-2 and illustrated. The gate electrode of transistor 1-4 is referred to as gate electrode 11-4 and illustrated. When there is no particular distinction between these, they are simply referred to as gate electrode 11. An example of a material for gate electrode 11 is polysilicon (polycrystalline silicon).

[0025] In the following description, when transistor 1 is connected between two elements, it means that one of the source and drain of transistor 1 is connected to one element, and the other of the source and drain is connected to the other element.

[0026] The transistor 1-1 is provided between the photoelectric conversion unit 3 and the floating diffusion 2. The transistor 1-1 is a transfer transistor that transfers the charge in the photoelectric conversion unit 3 to the floating diffusion 2. The gate electrode 11-1 of the transistor 1-1 is connected to a corresponding signal line 98H. A control signal from the signal line 98H controls the conduction and non-conduction between the drain and source of the transistor 1-1 (the on / off of the transistor 1-1). When the transistor 1-1 is on, the charge in the photoelectric conversion unit 3 is transferred to the floating diffusion 2 via the transistor 1-1.

[0027] The floating diffusion 2 accumulates the electric charge transferred from the photoelectric conversion unit 3 by the transistor 1-1, and generates a voltage signal according to the accumulated electric charge.

[0028] The transistor 1-2 is connected between the floating diffusion 2 and a node VDD. The node VDD has, for example, a voltage (power supply voltage) required for the operation of the transistor 1. The transistor 1-2 is a reset transistor that discharges the charge in the floating diffusion 2. The gate electrode 11-2 of the transistor 1-2 is connected to a corresponding signal line 98H. The on / off of the transistor 1-2 is controlled by a control signal from the signal line 98H. When the transistor 1-2 is on, the charge in the floating diffusion 2 is discharged to the node VDD via the transistor 1-2.

[0029] The transistor 1-3 is connected between the node VDD and the transistor 1-4. The gate of the transistor 1-3 is connected to the floating diffusion 2. The transistor 1-3 can also be called an amplifying transistor that amplifies and outputs the voltage generated in the floating diffusion 2.

[0030] Transistor 1-4 is connected between transistor 1-3 and signal line 98V. Transistor 1-4 is a selection transistor that selectively outputs the output voltage of transistor 1-3 to signal line 98V. Gate electrode 11-4 of transistor 1-4 is connected to a corresponding signal line 98H. The on / off of transistor 1-4 is controlled by a control signal from that signal line 98H. When transistor 1-4 is on, the output voltage of transistor 1-3 is output to signal line 98V via transistor 1-4. This voltage signal becomes the pixel signal.

[0031] 3 is a diagram showing an example of a schematic configuration of a photodetector 90, more specifically, a cross section of a part of a photodetection region 91 and a part of a peripheral region SR when viewed in the Y-axis direction.

[0032] The photodetector 90 includes a semiconductor substrate 4, a connection layer 5, and a wiring layer 6. In this example, the semiconductor substrate 4, the connection layer 5, and the wiring layer 6 are positioned in this order in the positive direction of the Z axis.

[0033] Regarding the light detection region 91, the semiconductor substrate 4 includes a photoelectric conversion unit 3. The semiconductor substrate 4 also includes a transistor 1 and a floating diffusion 2. The surface of the semiconductor substrate 4 located on the positive side of the Z axis is illustrated as a surface 4a.

[0034] 3 illustrates a transistor 1-1 and a transistor 1-2 as examples of the transistor 1 provided on the semiconductor substrate 4. A gate electrode 11-1 of the transistor 1-1 and a gate electrode 11-2 of the transistor 1-2 are also illustrated. When there is no particular distinction between these, they will be simply referred to as the transistor 1.

[0035] The surface 11a of the gate electrode 11-1 of the transistor 1-1 is illustrated as surface 11a-1. The surface 11a of the gate electrode 11-2 of the transistor 1-2 is illustrated as surface 11a-2. When there is no particular distinction between these, they are simply referred to as surface 11a.

[0036] The gate electrode 11 of the transistor 1 is embedded in the semiconductor substrate 4 so as to have a surface 11a that is substantially flush with the surface 4a of the semiconductor substrate 4. In the Z-axis direction, the surfaces 2a and 4a are located at substantially the same position (same height). For example, even if the surfaces 2a and 4a are not completely flush and are misaligned with each other, they may be considered to be substantially flush as long as the amount of misalignment is within the range of manufacturing variations, etc. Furthermore, they may be considered to be substantially flush as long as the amount of misalignment is within a range that allows the purpose of this embodiment to be achieved, which will be described later.

[0037] The floating diffusion 2 is formed inside the semiconductor substrate 4 from the surface 4a of the semiconductor substrate 4. The surface of the floating diffusion 2 on the positive side of the Z axis is referred to as the surface 2a and illustrated. The surface 2a extends in the XY plane. The surface 2a of the floating diffusion 2 may be flush with the surface 4a of the semiconductor substrate 4. In the Z axis direction, the surfaces 2a and 4a are located at the same position.

[0038] The photoelectric conversion unit 3 is formed in a semiconductor substrate 4. In the example shown in FIG.

[0039] For convenience, the wiring layer 6 and the connection layer 5 will be described in that order. The wiring layer 6 is provided above the semiconductor substrate 4. In this example, the wiring layer 6 is provided on the opposite side of the connection layer 5 to the semiconductor substrate 4. The wiring layer 6 includes wiring for electrically connecting circuit elements such as the transistor 1 and the floating diffusion 2.

[0040] Among the wires included in the wiring layer 6, the wire electrically connected to the gate electrode 11 of the transistor 1 is referred to as a wire 61. Specifically, the wire 61 electrically connected to the gate electrode 11-1 of the transistor 1-1 is referred to as a wire 61-1 and illustrated. The wire 61 electrically connected to the gate electrode 11-2 of the transistor 1-2 is referred to as a wire 61-2 and illustrated.

[0041] Of the wires included in the wiring layer 6, the wires electrically connected to the floating diffusion 2 are referred to as wires 62 and are illustrated.

[0042] In addition, in the wiring layer 6, the portion where the wiring 61 and the wiring 62 are not present may be made of an insulator.

[0043] The connection layer 5 is provided between the semiconductor substrate 4 and the wiring layer 6. The connection layer 5 includes several vias that electrically connect each element provided on the semiconductor substrate 4, such as the transistor 1 and the floating diffusion 2, to the wiring layer 6.

[0044] Among the vias included in the connection layer 5, the via that connects the wiring layer 6 and the transistor 1 is referred to as a via 51 (first via). Specifically, the via 51 that connects the wiring 61-1 of the wiring layer 6 and the gate electrode 11-1 of the transistor 1-1 is referred to and illustrated as a via 51-1. The via 51 that connects the wiring 61-2 of the wiring layer 6 and the gate electrode 11-2 of the transistor 1-2 is referred to and illustrated as a via 51-2. When there is no particular distinction between these, they are simply referred to as vias 51.

[0045] Among the vias included in the connection layer 5, the via that connects the wiring layer 6 and the floating diffusion 2 is referred to as a via 52 (second via) and illustrated. The via 52 connects the wiring 62 of the wiring layer 6 and the floating diffusion 2.

[0046] The portion of the connection layer 5 where the vias 51 and the vias 52 are not present may be made of an insulator.

[0047] As described above, the surface 11a of the gate electrode 11 of the transistor 1 is substantially flush with the surface 4a of the semiconductor substrate 4. In addition, the surface 2a of the floating diffusion 2 is substantially flush with the surface 4a of the semiconductor substrate 4. Therefore, the vias 51 and 52 have substantially the same length (length in the Z-axis direction).

[0048] Regarding the peripheral region SR, a dummy diffusion region D1 is provided in the semiconductor substrate 4. The dummy diffusion region D1 may be formed in the semiconductor substrate 4 similarly to the photoelectric conversion unit 3 in the light detection region 91. Of the wires included in the wiring layer 6, the wires located above the dummy diffusion region D1 are referred to as wires M and illustrated.

[0049] According to the photodetector 90 described above, the gate electrode 11 of the transistor 1 is embedded in the transistor 1 so as to have a surface 11a that is substantially flush with the surface 4a of the semiconductor substrate 4. This makes it possible to suppress an increase in parasitic capacitance caused by the gate electrode 11 more effectively than in the case where the gate electrode 11 is provided on the surface 4a of the semiconductor substrate 4. A comparative example will also be used for explanation.

[0050] 4 is a diagram showing a comparative example. The photodetector according to the comparative example is referred to as a photodetector 90E and illustrated. In the photodetector 90E, a transistor corresponding to the transistor 1 of the photodetector 90 (FIG. 3) is referred to as a transistor 1E. Specifically, in the photodetector 90E, transistors corresponding to the transistors 1-1 and 1-2 of the photodetector 90 are referred to as a transistor 1E-1 and a transistor 1E-2 and illustrated. When there is no particular distinction between these, they are simply referred to as transistor 1E.

[0051] In the photodetector 90E, a gate electrode corresponding to the gate electrode 11 of the transistor 1 of the photodetector 90 is referred to as a gate electrode 11E. Specifically, in the photodetector 90E, gate electrodes corresponding to the gate electrodes 11-1 and 11-2 of the photodetector 90 are referred to and illustrated as a gate electrode 11E-1 and a gate electrode 11E-2. When there is no particular distinction between these, they are simply referred to as a gate electrode 11E.

[0052] A gate electrode 11E of a transistor 1E of a photodetector device 90E is provided on a semiconductor substrate 4 (on a surface 4a). The gate electrode 11E is not embedded in the semiconductor substrate 4.

[0053] In the photodetector 90E, a via corresponding to the via 51 of the photodetector 90 is illustrated as a via 51E. Specifically, a via connecting the wiring 61-1 of the wiring layer 6 and the gate electrode 11E-1 is illustrated as a via 51E-1. A via connecting the wiring 61-2 and the gate electrode 11E-2 is illustrated as a via 51E-2.

[0054] As can be seen from FIG. 4, the length of the via 51E of the photodetector 90E is shorter than the length of the via 52 by the thickness of the gate electrode 11E (the length in the Z-axis direction).

[0055] In the photodetector 90E, a dummy electrode D2 is provided on the peripheral region SR, more specifically, on the dummy diffusion region D1 in this example. The dummy electrode D2 is provided to suppress a step that may be generated due to the gate electrode 11E between the photodetection region 91 where the gate electrodes 11E are densely provided and the peripheral region SR where they are not.

[0056] In the photodetector 90E, unintended parasitic capacitance occurs due to the gate electrode 11E and the dummy electrode D2. Some possible parasitic capacitances are shown by dashed lines as parasitic capacitance Cp. Specifically, since the side surface of the gate electrode 11E faces the via 52, the parasitic capacitance Cp occurs between the gate electrode 11E and the via 52. Also, since the dummy electrode D2 faces the wiring M, the parasitic capacitance Cp occurs between the dummy electrode D2 and the wiring M. Due to the parasitic capacitance Cp, problems such as noise become apparent. For example, the capacitance of the floating diffusion 2 increases by the amount of the parasitic capacitance Cp occurring between the gate electrode 11E and the via 52, which leads to deterioration of noise.

[0057] Furthermore, in the photodetector 90E, as the structure is miniaturized, an increase in the parasitic capacitance Cp becomes apparent. For example, when the distance between the gate electrode 11E and the via 52 is reduced, the parasitic capacitance Cp generated therein increases. Furthermore, when the thickness of the connection layer 5 is reduced to reduce the distance between the dummy electrode D2 and the wiring M, the parasitic capacitance Cp generated therein increases. Therefore, miniaturization becomes difficult in the configuration of the photodetector 90E.

[0058] On the other hand, in the photodetector 90 (FIG. 3) according to this embodiment, the gate electrode 11 is embedded in the semiconductor substrate 4, and therefore the side surface of the gate electrode 11 does not face the via 52. This makes it possible to suppress an increase in parasitic capacitance that may occur between the gate electrode 11 and the via 52. Furthermore, since there is no dummy electrode D2 in the peripheral region SR, it is possible to suppress an increase in parasitic capacitance that may occur between the dummy electrode D2 and the wiring M. For example, it is possible to suppress the deterioration of noise due to an increase in parasitic capacitance.

[0059] By suppressing the increase in parasitic capacitance, the possibility of miniaturizing the structure increases. For example, the distance between the gate electrode 11 and the via 51 can be reduced. Also, the thickness of the connection layer 5 can be reduced (reduced in height).

[0060] Furthermore, in the photodetector 90E, the vias 51E and 52 must be formed with different lengths (different types), which increases the number of manufacturing steps and complicates the manufacturing process. In the photodetector 90 (FIG. 3) according to this embodiment, the vias 51 and 52 have substantially the same length. The vias 51 and 52 can be formed simultaneously (collectively) in the same manufacturing process. Therefore, the manufacturing process for forming the vias can be simplified and costs can be reduced compared to the photodetector 90E.

[0061] As described above, even if the surface 11a of the gate electrode 11 of the transistor 1 is not completely flush with the surface 4a of the semiconductor substrate 4, as long as the amount of deviation is within a range that allows the object of the present embodiment to be achieved, it may be considered that the surfaces are substantially flush with each other. Description will be made with reference to FIG. 5 as well.

[0062] Fig. 5 is a diagram showing an example of a substantially flat configuration. In the example shown in Fig. 5, a surface 11a of a gate electrode 11 of a transistor 1 is located slightly above (on the positive side of the Z axis) a surface 4a of a semiconductor substrate 4. The length of a portion of the gate electrode 11 that protrudes above the surface 4a of the semiconductor substrate 4 is referred to as a deviation amount ΔZ and is shown in the figure.

[0063] Although a parasitic capacitance may occur between the gate electrode 11 and the via 52 by the amount of the deviation ΔZ, if the deviation ΔZ is small, the parasitic capacitance is also sufficiently small. Also, if the step caused by the deviation ΔZ is small, there is no need to provide the dummy electrode D2. Even if such a deviation Z exists, the object of this embodiment is achieved, so it can be said that the surface 11a of the gate electrode 11 and the surface 4a of the semiconductor substrate 4 are substantially flush with each other.

[0064] Also, the length of the via 51 is shorter than the length of the via 52 (FIG. 3) by the amount of the deviation ΔZ. However, if the vias 51 and 52 can be formed simultaneously in the same manufacturing process by absorbing the deviation ΔZ, the object of this embodiment can be achieved. In this case, too, it can be said that the surface 11a of the gate electrode 11 and the surface 4a of the semiconductor substrate 4 are substantially flush with each other.

[0065] 2. Variations 2.1 First modified example In one embodiment, elements of the pixel circuit may be provided across multiple semiconductor substrates, as will be described with reference to FIGS.

[0066] 6 is a diagram showing an example of a pixel circuit. Elements of the pixel circuit are provided separately on two semiconductor substrates 4. The first semiconductor substrate is illustrated as semiconductor substrate 4-1. The second semiconductor substrate is illustrated as semiconductor substrate 4-2.

[0067] In this example, the photoelectric conversion unit 3, the transistor 1-1, and the floating diffusion 2 are provided on a semiconductor substrate 4-1. The transistors 1-2, 1-3, and 1-4 are provided on a semiconductor substrate 4-2. The transistor 1-1 can also be called a first transistor provided on a first semiconductor substrate. The transistors 1-2, 1-3, and 1-4 can also be called second transistors provided on a second semiconductor substrate.

[0068] By providing the transistors 1-2, 1-3, and 1-4 on the semiconductor substrate 4-2, the number of transistors 1 provided on the semiconductor substrate 4-1 can be reduced. This allows, for example, a region for the photoelectric conversion unit 3 to be secured, improving the detection performance (sensitivity, etc.) of the photodetector 90. Also, the formation of the transistor 1-1 on the semiconductor substrate 4-1 can be easily performed.

[0069] 7 and 8 are diagrams showing an example of a schematic configuration of a photodetector. A photodetector 90 includes a semiconductor substrate 4-1, a connection layer 5-1, a semiconductor substrate 4-2, a connection layer 5-2, and a wiring layer 6. In this example, the semiconductor substrate 4-1, the connection layer 5-1, the semiconductor substrate 4-2, the connection layer 5-2, and the wiring layer 6 are positioned in this order in the positive direction of the Z axis.

[0070] The semiconductor substrate 4-2 is provided above the semiconductor substrate 4-1. In this example, the semiconductor substrate 4-2 is provided on the connection layer 5-1 on the opposite side of the connection layer 5-1 from the semiconductor substrate 4-1. The surface of the semiconductor substrate 4-1 facing the positive direction of the Z axis is referred to as surface 4a-1 and illustrated. The surface of the semiconductor substrate 4-2 facing the positive direction of the Z axis is referred to as surface 4a-2 and illustrated.

[0071] The semiconductor substrate 4-1 includes a photoelectric conversion unit 3, similar to the semiconductor substrate 4 (FIG. 3) described above. In addition, the semiconductor substrate 4 is provided with a floating diffusion 2 and a transistor 1-1. The transistor 1-2 is provided on the semiconductor substrate 4-2, not on the semiconductor substrate 4-1. Although not shown in FIGS. 7 and 8, the transistors 1-3 and 1-4 are also provided on the semiconductor substrate 4-2.

[0072] The drain and source of transistor 1-2 are also shown in Figure 7. The drain and source of transistor 1-2 are illustrated and designated as drain 12-2 and source 13-2.

[0073] The connection layer 5-1 is provided between the semiconductor substrate 4-1 and the semiconductor substrate 4-2. The connection layer 5-2 is provided between the semiconductor substrate 4-2 and the wiring layer 6. The via 51-1 passes through the connection layer 5-2, the semiconductor substrate 4-2, and the connection layer 5-1, and electrically connects the wiring 61-1 of the wiring layer 6 to the gate electrode 11-1 of the transistor 1-1. The via 52 passes through the connection layer 5-2, the semiconductor substrate 4-2, and the connection layer 5-1, and electrically connects the wiring 62 of the wiring layer 6 to the floating diffusion 2. The wiring 61-2 passes through the connection layer 5-2, and connects the wiring 61-2 of the wiring layer 6 to the gate electrode 11-2 of the transistor 1-2.

[0074] A gate electrode 11-1 of the transistor 1-1 is embedded in the semiconductor substrate 4-1 so as to have a surface 11a-1 that is substantially flush with a surface 4a-1 of the semiconductor substrate 4-1. In the peripheral region SR, a dummy diffusion region D1-1 is provided in the semiconductor substrate 4-1, but no dummy electrode is provided.

[0075] The transistor 1-2 may be provided on a surface 4a-2 of the semiconductor substrate 4-2, or may be embedded in the semiconductor substrate 4-2.

[0076] 7, the gate electrode 11-2 of the transistor 1-2 is provided on the surface 4a-2 of the semiconductor substrate 4-2. In the peripheral region SR, a dummy diffusion region D1-2 is provided in the semiconductor substrate 4-2, and a dummy electrode D2 is provided on the surface 4a-2 of the semiconductor substrate 4-2. The dummy electrode D2 is provided to suppress a step that may be caused by the gate electrode 11-2 between the photodetection region 91 where the gate electrodes 11-2 are densely provided and the peripheral region SR where they are not.

[0077] 8, the gate electrode 11-2 of the transistor 1-2 is embedded in the semiconductor substrate 4-2 so as to have a surface 11a-2 that is substantially flush with the surface 4a of the semiconductor substrate 4-2. There are no dummy electrodes in the peripheral region SR.

[0078] 7 and 8, it is possible to suppress an increase in parasitic capacitance that may occur between the gate electrode 11 and the wiring 62. In particular, in a configuration using two semiconductor substrates 4-1 and 4-2, the via 52 becomes longer and the parasitic capacitance is likely to increase, but in the above configuration, the thickness of the connection layer 5-1 is reduced (reduced in height) by the amount that the gate electrode 11-1 is embedded in the semiconductor substrate 4-1, and the length of the via 51 can be suppressed. This suppresses an increase in parasitic capacitance, and in turn suppresses the deterioration of noise caused by an increase in the capacitance of the floating diffusion 2.

[0079] 8, an increase in parasitic capacitance that may occur between the gate electrode 11-2 and the via 52 can be suppressed. Also, since the dummy electrode D2 is not provided in the peripheral region SR, an increase in parasitic capacitance that may occur between the dummy electrode D2 and the wiring M can be suppressed.

[0080] Furthermore, among the transistors 1, transistors other than the transistor 1-1, for example, the transistor 1-2, the transistor 1-3, and the transistor 1-4, are provided on the semiconductor substrate 4-2. Only the transistor 1-1 is provided on the semiconductor substrate 4-1. Since there is no transistor 1 other than the transistor 1-1 on the semiconductor substrate 4-1, it is easy to embed the gate electrode 11-1 of the transistor 1-1 in the semiconductor substrate 4-1.

[0081] The photodetector 90 including the two semiconductor substrates 4-1 and 4-2 as described above can be obtained, for example, by bonding the semiconductor substrates 4-1 and 4-2 together via a connection layer 5-1. The gate electrode 11-2 of the transistor 1-2 may be provided on the semiconductor substrate 4-2 after the semiconductor substrates 4-1 and 4-2 are bonded together, or may be provided on the semiconductor substrate 4-2 before the bonding.

[0082] For example, in the configuration of FIG. 8, the gate electrode 11-2 of the transistor 1-2 is provided on the semiconductor substrate 4-2 after the semiconductor substrate 4-1 and the semiconductor substrate 4-2 are bonded together, which provides the following advantages. That is, when the gate electrode 11-2 is provided after bonding, miniaturization may become difficult because planarization of the semiconductor substrate 4-2 performed after bonding may affect the formation of the gate electrode 11-2. In contrast, in the configuration of FIG. 8, the semiconductor substrate 4-2 is flat even after the gate electrode 11-2 is formed, so that the semiconductor substrate 4-1 and the semiconductor substrate 4-2 can be bonded together without planarization after the gate electrode 11-2 is formed first. Since the planarization does not affect the formation of the gate electrode 11-2, this may be advantageous for miniaturization.

[0083] 2.2 Second variant In one embodiment, a part of the gate electrode 11 of the transistor 1 is located on the element isolation portion, and the via 51 may be connected to that part. The following will be described with reference to FIG.

[0084] 9 is a diagram showing an example of a schematic configuration of a light detection device. Note that the cross-sectional view shown is a cross-sectional view seen in the X-axis direction, unlike the cross-sectional views shown so far.

[0085] The semiconductor substrate 4 includes an element isolation portion 7. In this example, the element isolation portion 7 is an oxide film provided near the surface 4a of the semiconductor substrate 4 (STI (Shallow Trench Isolation)).

[0086] The gate electrode 11 of the transistor 1 includes a central portion 111 and an end portion 112. The central portion 111 is a portion located at the center of the gate electrode 11 in the XY plane direction. The end portion 112 is a portion located at an end of the gate electrode 11 in the XY plane direction.

[0087] Of the central portion 111 and the end portion 112 of the gate electrode 11, the end portion 112 is located on the element isolation portion 7. The via 51 is connected to the end portion 112 of the gate electrode 11.

[0088] For example, when the via 51 is connected to the central portion 111 of the gate electrode 11, if the thickness (length in the Z-axis direction) of the gate electrode 11 is small, it may be difficult to form the via 51 because damage may occur below the via 51 when the via 51 is formed. By connecting the via 51 to the end portion 112 located on the element isolation portion 7, rather than to the central portion 111 of the gate electrode 11, the effect of such damage can be suppressed. Therefore, the via 51 becomes easier to form.

[0089] 2.3 Third variant In one embodiment, the gate electrode 11 of the transistor 1 may include an extending portion that extends downward. This will be described with reference to FIGS.

[0090] Fig. 10 to Fig. 13 are diagrams showing an example of a schematic configuration of a photodetector. Fig. 10 to Fig. 12 show a schematic cross section of a part of a photodetector 90 as viewed in the X-axis direction. Fig. 13 shows a schematic cross section as viewed along line XIII-XIII in Fig. 12 (as viewed in the Z-axis direction). Fig. 12 also shows a schematic cross section as viewed along line XII-XII in Fig. 13.

[0091] The gate electrode 11 of the transistor 1 includes a surface portion 113 and an extension portion 114. The extension portion 114 is a portion that has the surface 11a of the gate electrode 11. It extends from the surface portion 113 toward inside the semiconductor substrate 4 (in the negative direction of the Z axis).

[0092] The via 51 is connected to the surface portion 113 of the gate electrode 11 on the opposite side to the extending portion 114. The thickness of the portion of the gate electrode 11 to which the via 51 is connected is increased by the amount of the extending portion 114, so that the influence of damage that may occur when the via 51 is formed can be suppressed.

[0093] Moreover, since the via 51 can be brought closer to the center of the surface portion 113 of the gate electrode 11, the width (the length in the Y-axis direction in this example) of the surface portion 113 can be reduced. That is, the area occupied by the gate electrode 11, the via 51, and the wiring 61 when viewed in the Z-axis direction can be reduced (shrunk).

[0094] 10, the surface portion 113 includes the central portion 111 and the end portion 112 described above. The extension portion 114 extends downward from the central portion 111 of the surface portion 113. The width (length in the XY plane direction) of the extension portion 114 is smaller than the overall width of the central portion 111 and the end portion 112. The gate electrode 11 has a T-shape as a whole. A configuration that is smaller in size than the configuration virtually illustrated by the dashed dotted line is obtained.

[0095] 11, the surface portion 113 of the gate electrode 11 of the transistor 1 includes the central portion 111 but does not include the end portion 112 (FIG. 10). The absence of the end portion 112 allows for further shrinkage.

[0096] In the examples shown in Figures 12 and 13, the gate electrode 11 of the transistor 1 is provided so as to cover the upper surface and side surfaces of the channel region in the semiconductor substrate 4. The channel width per unit area can be increased. The gate electrode 11 of the transistor 1 includes a surface portion 113 and a pair of extension portions 114. The pair of extension portions 114 extend downward from the surface portion 113 with a gap between them. The gate electrode 11 has an inverted U-shape as a whole. In this case as well, as shown in Figure 12, a configuration that is smaller in size than the configuration virtually illustrated by the dashed line can be obtained.

[0097] 2.4 Application Examples Some application examples of the configurations described above will be described with reference to FIGS.

[0098] 14 to 17 are diagrams showing examples of schematic configurations of photodetection devices.

[0099] In the example shown in Figures 14 and 15, the gate electrode 11-1 of the transistor 1-1 is modified from the configurations of Figures 7 and 8 described above to have a T-shape. The gate electrode 11-1 includes a surface portion 113-1 and an extension portion 114-1. The surface portion 113-1 includes a central portion 111-1 and an end portion 112-1. These are similar to the surface portion 113, the extension portion 114, the central portion 111, and the end portion 112 described above with reference to Figure 10, so the description will not be repeated. The via 51-1 is connected to the central portion 111-1 of the surface portion 113-1 of the gate electrode 11-1.

[0100] In the example shown in FIG. 16, of the transistor 1-1 and the transistor 1-2 provided on the semiconductor substrate 4, the gate electrode 11-1 of the transistor 1-1 has a T-shape.

[0101] In the example shown in Fig. 17, the gate electrode 11-1 of the transistor 1-1 and the gate electrode 11-2 of the transistor 1-2 each have a shape that extends downward. Specifically, the gate electrode 11-1 of the transistor 1-1 includes a surface portion 113-1 and an extension portion 114-1. The gate electrode 11-2 of the transistor 1-2 includes a surface portion 113-2 and an extension portion 114-2. The surface portion 113-2 and the extension portion 114-2 are similar to the surface portion 113 and the extension portion 114 previously described with reference to Fig. 10, and therefore description thereof will not be repeated.

[0102] 3.Examples of manufacturing methods 18 to 26 are diagrams showing an example of a method for manufacturing a photodetector. In each diagram, (A) shows a schematic cross section as viewed in the Y-axis direction. In each diagram, (B) shows a schematic cross section as viewed in the X-axis direction.

[0103] 18 to 22 show several manufacturing steps for obtaining a gate electrode 11 including an end 112 located on an element isolation portion 7 as shown in FIG. 9 described above.

[0104] As shown in FIG. 18, a semiconductor substrate 4 is prepared. As shown in FIG. 19, an element isolation portion 7 is formed in the semiconductor substrate 4. For example, as described above, the STI technique is used. As shown in FIG. 20, a resist PR is provided on the semiconductor substrate 4. This resist PR is patterned so as to cover the semiconductor substrate 4 except for the portion in which the gate electrode 11 is embedded. A part of the semiconductor substrate 4 and the element isolation portion 7 is etched to obtain a recess 4r corresponding to the gate electrode 11. The resist PR is removed by ashing or the like, and a material of the gate electrode 11 is formed. For example, polysilicon is deposited and planarized by CMP or the like. As shown in FIG. 21, a gate electrode 11 is obtained that is embedded in the semiconductor substrate 4 so as to have a surface 11a that is substantially flush with the surface 4a of the semiconductor substrate 4. As shown in FIG. 22, a drain 12 and a source 13 of the transistor 1 are formed using the resist PR. A transistor 1 including the gate electrode 11, the drain 12, and the source 13 is obtained.

[0105] 23 to 26 show several manufacturing steps for obtaining the gate electrode 11 including a pair of surface portions 113 as shown in Fig. 12. It is assumed that the manufacturing steps shown in Figs. 18 and 19 have already been completed.

[0106] As shown in FIG. 23, a resist PR is provided on the semiconductor substrate 4. This resist PR is patterned so that the surface portion 113 of the gate electrode 11 of the semiconductor substrate 4 is obtained. A part of the semiconductor substrate 4 and the element isolation portion 7 is etched to obtain a recess 4r corresponding to the surface portion 113 of the gate electrode 11. As shown in FIG. 24, a resist PR is provided. This resist PR is patterned so that a pair of extension portions 114 of the gate electrode 11 is obtained. A part of the semiconductor substrate 4 and the element isolation portion 7 is etched to obtain a recess 4r corresponding to the pair of extension portions 114 of the gate electrode 11. The resist PR is removed, and a material of the gate electrode 11 is formed and planarized. As shown in FIG. 25, a gate electrode 11 is obtained that is embedded in the semiconductor substrate 4 so as to have a surface 11a that is substantially flush with the surface 4a of the semiconductor substrate 4. The gate electrode 11 includes a surface portion 113 and a pair of extension portions 114. As shown in FIG. 26, the drain 12 and the source 13 of the gate electrode 11 are formed using the resist PR. A transistor 1 is obtained, comprising a gate electrode 11, a drain 12 and a source 13.

[0107] 4. Example of common pixel circuit In one embodiment, a pixel circuit may be shared among a plurality of pixels 92. This will be described with reference to FIG.

[0108] Fig. 27 is a diagram showing an example of pixel circuit sharing. In the example shown in Fig. 27, four transistors 1-1 corresponding to four pixels 92 are provided. Meanwhile, one floating diffusion 2, one transistor 1-2, one transistor 1-3, and one transistor 1-4 are provided for the four pixels 92. The photoelectric conversion unit 3 of each pixel 92 is connected to the same floating diffusion 2 via the corresponding transistor 1-1. The floating diffusion 2, the transistor 1-2, the transistor 1-3, and the transistor 1-4 are shared among the four pixels 92.

[0109] 5. Summary The techniques described above are specified, for example, as follows. One of the techniques disclosed is a photodetector 90. As described with reference to Figs. 1 to 3 and Figs. 5 to 17 and the like, the photodetector 90 (for example, a solid-state imaging device) includes a semiconductor substrate 4 including a photoelectric conversion section 3, a floating diffusion 2 formed inside the semiconductor substrate 4 from a surface 4a of the semiconductor substrate 4, and a transistor 1 provided on the semiconductor substrate 4. The transistor 1 includes a gate electrode 11 embedded in the semiconductor substrate 4 so as to have a surface 11a that is substantially flush with the surface 4a of the semiconductor substrate 4. According to the photodetector 90 including the gate electrode 11 including such a gate electrode 11, as described above, it is possible to suppress an increase in parasitic capacitance caused by the gate electrode 11.

[0110] As described with reference to FIG. 2 and FIG. 3, the transistor 1 may include a transfer transistor (transistor 1-1) that transfers the charge in the photoelectric conversion unit 3 to the floating diffusion 2. For example, an increase in parasitic capacitance can be suppressed by embedding the gate electrode 11 (gate electrode 11-1 of transistor 1-1) of such a transistor 1 in the semiconductor substrate 4. Other transistors 1 provided in the same manner may include a reset transistor (transistor 1-2) that discharges the charge in the floating diffusion 2, an amplifier transistor (transistor 1-3) that amplifies and outputs the voltage generated in the floating diffusion 2, and a selection transistor (transistor 1-4) that selectively outputs the output voltage of the amplifier transistor to a signal line 98V.

[0111] As described with reference to FIG. 3 etc., the photodetector 90 includes a wiring layer 6 provided above (on the positive side of the Z-axis) the semiconductor substrate 4, a via 51 (first via) connecting the wiring layer 6 to the gate electrode 11, and a via 52 (second via) connecting the wiring layer 6 to the floating diffusion 2, and the via 51 and the via 52 may have substantially the same length. This allows the via 51 and the via 52 to be formed simultaneously in the same manufacturing process. This simplifies the manufacturing process for forming the vias, and reduces costs.

[0112] 9 and the like, the semiconductor substrate 4 may include the element isolation portion 7, the gate electrode 11 may include an end portion 112 located on the element isolation portion, and the via 51 may be connected to the end portion 112. This makes it possible to suppress the influence of damage that may occur when the via 51 is formed.

[0113] 10 to 12, the gate electrode 11 includes a surface portion 113 having a surface 11a of the gate electrode 11, and an extension portion 114 extending from the surface portion 113 toward the inside of the semiconductor substrate 4, and the via 51 may be connected to the surface portion 113 on the opposite side of the surface portion 113 to the extension portion 114. In this case as well, the influence of damage that may occur when the via 51 is formed can be suppressed.

[0114] 12 and 13, the extension portion 114 may be a pair of extension portions 114 spaced apart from each other and extending from the surface portion 113 toward the inside of the semiconductor substrate 4. By using the gate electrode 11 including such a surface portion 113 and extension portion 114, the channel width per unit area can be increased.

[0115] As described with reference to Fig. 7 and Fig. 8, the photodetector 90 may include a semiconductor substrate 4-2 (second semiconductor substrate) provided above the semiconductor substrate 4, and a transistor 1-2 (second transistor) provided on the semiconductor substrate 4-2. This allows various transistors 1 included in the photodetector 90 to be provided separately on two semiconductor substrates, 4-1 (first semiconductor substrate) and 4-2. The number of transistors 1 provided on the semiconductor substrate 4-1 can be reduced, and by that amount, for example, an area for the photoelectric conversion unit 3 can be secured, thereby improving the detection performance (sensitivity, etc.) of the photodetector 90.

[0116] As described with reference to FIG. 7 and the like, the transistor 1-2 may include a gate electrode 11-2 provided on the surface 4a-2 of the semiconductor substrate 4-2. Even in such a configuration, since the gate electrode 11-1 of the transistor 1-1 provided on the semiconductor substrate 4-1 (first semiconductor substrate) is embedded in the semiconductor substrate 4-1, an increase in parasitic capacitance caused by the gate electrode 11-1 can be suppressed. In addition, the photodetector 90 may include a dummy electrode D2 provided on the surface 4a-2 of the semiconductor substrate 4-2. This is provided, for example, to suppress a step that may be caused by the gate electrode 11-2 between the photodetection region 91 where the gate electrodes 11-2 are densely provided and the peripheral region SR where they are not.

[0117] 8 and the like, the transistor 1-2 may include a gate electrode 11-2 embedded in the semiconductor substrate 4-2 so as to have a surface 11a-2 that is substantially flush with the surface 4a-2 of the semiconductor substrate 4-2. This makes it possible to suppress an increase in parasitic capacitance caused by the gate electrode 11-2.

[0118] 2, 7, and 8, the transistor 1-1 provided in the semiconductor substrate 4-1 may be a transfer transistor that transfers the charge in the photoelectric conversion unit 3 to the floating diffusion 2, and the transistor 1-2 provided in the semiconductor substrate 4-2 may be a reset transistor that discharges the charge in the floating diffusion 2. For example, such a transfer transistor and reset transistor may be provided separately on the semiconductor substrate 4-1 and the semiconductor substrate 4-2.

[0119] 6. Mobile application examples The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0120] FIG. 28 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0121] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 28, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053 are illustrated.

[0122] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0123] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0124] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0125] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0126] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0127] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0128] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0129] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0130] The audio / video output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 28, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0131] FIG. 29 is a diagram showing an example of the installation position of the imaging unit 12031.

[0132] In FIG. 29, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0133] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield in the vehicle interior of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield in the vehicle interior mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield in the vehicle interior is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0134] 29 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0135] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0136] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0137] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0138] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0139] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 and the like among the configurations described above. Specifically, the photodetector 90 according to the embodiment can be used as the imaging unit 12031. By applying the technology according to the present disclosure, the performance of the imaging unit 12031 can be improved and the imaging unit 12031 can be made smaller. For example, a captured image that is easier to see can be obtained, thereby increasing the possibility of reducing the driver's fatigue.

[0140] Note that the effects described in this disclosure are merely examples and are not limited to the disclosed contents. Other effects may also be obtained.

[0141] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present disclosure. In addition, components of different embodiments and modifications may be appropriately combined.

[0142] The present technology can also be configured as follows. (1) A semiconductor substrate including a photoelectric conversion portion; a floating diffusion formed inside the semiconductor substrate from a surface of the semiconductor substrate; A transistor provided on the semiconductor substrate; Equipped with the transistor includes a gate electrode embedded in the semiconductor substrate so as to have a surface substantially flush with a surface of the semiconductor substrate; Light detection device. (2) The transistor includes a transfer transistor that transfers charges in the photoelectric conversion unit to the floating diffusion. The optical detection device according to (1). (3) The transistor is a reset transistor that drains the charge in the floating diffusion; an amplifying transistor that amplifies and outputs the voltage generated in the floating diffusion; And, A selection transistor that selectively outputs the output voltage of the amplification transistor to a signal line. At least one of The optical detection device according to (2). (4) A wiring layer provided above the semiconductor substrate; a first via connecting the wiring layer and the gate electrode; a second via connecting the wiring layer and the floating diffusion; Including, the first via and the second via have substantially the same length; The photodetector according to any one of (1) to (3). (5) the semiconductor substrate includes an isolation portion, the gate electrode includes an end portion located on the element isolation portion, the first via is connected to the end; The optical detection device according to (4). (6) The gate electrode is a surface portion having a surface of the gate electrode; an extension portion extending from the surface portion toward inside the semiconductor substrate; Including, the first via is connected to the surface portion on the opposite side to the extension portion across the surface portion; The optical detection device according to (4). (7) The extension portion is a pair of extension portions spaced apart from each other and extending from the surface portion toward inside the semiconductor substrate. The optical detection device according to (6). (8) a second semiconductor substrate provided above the semiconductor substrate; a second transistor provided on the second semiconductor substrate; Equipped with The photodetector according to any one of (1) to (7). (9) the second transistor includes a gate electrode provided on a surface of the second semiconductor substrate; The optical detection device according to (8). (10) The photodetector includes a dummy electrode provided on a surface of the second semiconductor substrate. An optical detection device according to (8) or (9). (11) the second transistor includes a gate electrode embedded in the second semiconductor substrate so as to have a surface substantially flush with a surface of the second semiconductor substrate; The optical detection device according to (8). (12) the transistor includes a transfer transistor that transfers charges in the photoelectric conversion unit to the floating diffusion, The second transistor includes a reset transistor that drains charge in the floating diffusion. The optical detection device according to any one of (8) to (11). (13) A solid-state imaging device. The photodetector according to any one of (1) to (12). [Explanation of symbols]

[0143] 1. Transistor 11 Gate electrode 111 Central part 112 End 113 Surface part 114 Extension 11a surface 12 Drain 13 Source 2 Floating Diffusion 3 Photoelectric conversion section 4. Semiconductor Substrates 4-1 Semiconductor substrate 4-2 Semiconductor substrates 4a surface 4r Recess 5. Connection Layer 51 Beer 52 Via 6 wiring layer 61 Wiring 62 Wiring 7. Element isolation section 90 Photodetector 91 Light detection area 92 pixels 93 Control circuit 94 Vertical drive circuit 95 Column signal processing circuit 96 Horizontal drive circuit 97 Output circuit 98H signal line 98V signal line 99 Signal Line D1 Dummy diffusion area D1-1 Dummy diffusion area D1-2 Dummy diffusion area D2 Dummy electrode M wiring PR Resist SR surrounding area

Claims

1. A semiconductor substrate including a photoelectric conversion portion; a floating diffusion formed inside the semiconductor substrate from a surface of the semiconductor substrate; A transistor provided on the semiconductor substrate; Equipped with the transistor includes a gate electrode embedded in the semiconductor substrate so as to have a surface substantially flush with a surface of the semiconductor substrate; Light detection device.

2. The transistor includes a transfer transistor that transfers charges in the photoelectric conversion unit to the floating diffusion.

2. The optical detection device according to claim 1.

3. The transistor is a reset transistor that drains the charge in the floating diffusion; an amplifying transistor that amplifies and outputs the voltage generated in the floating diffusion; And, A selection transistor that selectively outputs the output voltage of the amplification transistor to a signal line. At least one of 3. The optical detection device according to claim 2.

4. A wiring layer provided above the semiconductor substrate; a first via connecting the wiring layer and the gate electrode; a second via connecting the wiring layer and the floating diffusion; Including, the first via and the second via have substantially the same length; 2. The optical detection device according to claim 1.

5. the semiconductor substrate includes an isolation portion, the gate electrode includes an end portion located on the element isolation portion, the first via is connected to the end; 5. The optical detection device according to claim 4.

6. The gate electrode is a surface portion having a surface of the gate electrode; an extension portion extending from the surface portion toward inside the semiconductor substrate; Including, the first via is connected to the surface portion on a side opposite to the extension portion across the surface portion; 5. The optical detection device according to claim 4.

7. The extension portion is a pair of extension portions spaced apart from each other and extending from the surface portion toward inside the semiconductor substrate.

7. The optical detection device according to claim 6.

8. a second semiconductor substrate provided above the semiconductor substrate; a second transistor provided on the second semiconductor substrate; Equipped with 2. The optical detection device according to claim 1.

9. the second transistor includes a gate electrode provided on a surface of the second semiconductor substrate; 9. The optical detection device according to claim 8.

10. The photodetector includes a dummy electrode provided on a surface of the second semiconductor substrate.

9. The optical detection device according to claim 8.

11. the second transistor includes a gate electrode embedded in the second semiconductor substrate so as to have a surface substantially flush with a surface of the second semiconductor substrate; 9. The optical detection device according to claim 8.

12. the transistor includes a transfer transistor that transfers charges in the photoelectric conversion unit to the floating diffusion, The second transistor includes a reset transistor that drains charge in the floating diffusion.

9. The optical detection device according to claim 8.

13. A solid-state imaging device.

2. The optical detection device according to claim 1.

Images