Drive circuit board, and liquid discharge device

Abstract

To provide a drive circuit board in which a drive circuit is optimally arranged.SOLUTION: A drive circuit board includes a first driver circuit for outputting a first drive signal in response to a basic drive signal, a first switching element pair for outputting a first switching signal in response to the first drive signal, a second driver circuit for outputting a second drive signal in response to the basic drive signal, a second switching element pair for outputting a second switching signal in response to the second drive signal and the first switching signal, and a smooth circuit for outputting a drive signal obtained by smoothing the second switching signal, wherein a shortest distance between a source terminal of a first high potential side FET included in the second switching element pair and the smooth circuit is shorter than a shortest distance between a drain terminal of the first high potential side FET and the smooth circuit, and a shortest distance between a drain terminal of a first low potential side FET included in the second switching element pair and the smooth circuit is shorter than a shortest distance between a source terminal of the first low potential side FET and the smooth circuit.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to a drive circuit board and a liquid ejection device. [Background technology]

[0002] A liquid ejection device that ejects liquid to form an image or document on a medium is known that uses a piezoelectric element. In such a liquid ejection device, a piezoelectric element is provided corresponding to each of a plurality of nozzles that eject liquid, and each is driven according to a drive signal. When the piezoelectric element is driven, liquid is ejected from the nozzle provided corresponding to the piezoelectric element. In order to operate such a piezoelectric element, it is necessary to supply a sufficient current. Therefore, a drive circuit that outputs a drive signal that drives the piezoelectric element is configured to include an amplifier circuit that amplifies a source signal that is the basis of the drive signal by an amplifier circuit.

[0003] For example, Patent Document 1 discloses a drive circuit that has an amplifier circuit that modulates and amplifies a base drive signal that is the basis of a drive signal, and a level shift circuit that shifts a reference potential of the output of the amplifier circuit, and outputs a drive signal that drives a piezoelectric element by smoothing the output of the level shift circuit. Such a drive circuit disclosed in Patent Document 1 can reduce power consumption compared to an amplifier circuit that uses a class AB amplifier circuit or a general class D amplifier circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2022-057171 Summary of the Invention [Problem to be solved by the invention]

[0005] On the other hand, from the viewpoint of stabilizing the operation of the drive circuit that outputs the drive signal, how to mount the drive circuit on the wiring board is also an important factor. However, Patent Document 1 does not describe at all how to arrange the drive circuit on the wiring board, and there is room for further improvement. [Means for solving the problem]

[0006] One aspect of the drive circuit board according to the present invention is A drive circuit board that outputs a drive signal for driving a capacitive load, A drive circuit that outputs the drive signal corresponding to a basic drive signal; a wiring board on which the drive circuit is provided; Equipped with The drive circuit includes: a first driver circuit that outputs a first drive signal corresponding to the basic drive signal, and a first switching circuit including a first switching element pair that is driven in response to the first drive signal to output a first switching signal; a second driver circuit that outputs a second drive signal corresponding to the basic drive signal, and a second switching circuit including a second switching element pair that is driven in response to the second drive signal and outputs a second switching signal corresponding to the first switching signal; a smoothing circuit that smoothes the second switching signal and outputs the smoothed signal as the drive signal; having The wiring board includes a first side and a second side facing each other along a first direction, the second switching element pair includes a first high-side FET and a first low-side FET; The shortest distance between the source terminal of the first high potential side FET and the smoothing circuit is the shortest distance between the drain terminal of the side FET and the smoothing circuit, The shortest distance between the drain terminal of the first low potential side FET and the smoothing circuit is shorter than the shortest distance between the source terminal of the first low potential side FET and the smoothing circuit.

[0007] One aspect of the liquid ejection device according to the present invention is to a drive circuit board that outputs a drive signal for driving a capacitive load; a print head that ejects liquid by driving the capacitive load; Equipped with The drive circuit board includes: A drive circuit that outputs the drive signal corresponding to a basic drive signal; a wiring board on which the drive circuit is provided; Equipped with The drive circuit includes: a first driver circuit that outputs a first drive signal corresponding to the basic drive signal, and a first switching circuit including a first switching element pair that is driven in response to the first drive signal to output a first switching signal; a second driver circuit that outputs a second drive signal corresponding to the basic drive signal, and a second switching circuit including a second switching element pair that is driven in response to the second drive signal and outputs a second switching signal corresponding to the first switching signal; a smoothing circuit that smoothes the second switching signal and outputs the smoothed signal as the drive signal; having The wiring board includes a first side and a second side facing each other along a first direction, the second switching element pair includes a first high-side FET and a first low-side FET; the shortest distance between the source terminal of the first high potential side FET and the smoothing circuit is shorter than the shortest distance between the drain terminal of the first high potential side FET and the smoothing circuit; The shortest distance between the drain terminal of the first low potential side FET and the smoothing circuit is shorter than the shortest distance between the source terminal of the first low potential side FET and the smoothing circuit. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a schematic structure of a liquid ejection device. [Diagram 2] FIG. 2 is a diagram illustrating a functional configuration of the liquid ejection device. [Diagram 3]FIG. 2 is a diagram for explaining a schematic configuration of a discharge unit. [Figure 4] 4 is a diagram showing an example of a signal waveform of a drive signal COM. FIG. [Diagram 5] FIG. 2 is a diagram illustrating an example of a functional configuration of a drive circuit. [Figure 6] FIG. 4 is a diagram for explaining the operation of a drive circuit. [Figure 7] FIG. 4 is a diagram showing an example of the structure of a drive circuit board. [Figure 8] 10 is a diagram showing an example of a component layout of a drive circuit mounted in a drive circuit mounting area; FIG. [Figure 9] 11 is a diagram showing an example of a wiring pattern formed in a drive circuit mounting region; FIG. [Figure 10] FIG. 10 is an enlarged view of part (A) in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings are used for the convenience of explanation. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0010] The liquid ejection device according to the present invention is a printing device that ejects ink as a liquid, and will be described by taking an inkjet printer as an example. However, the liquid ejection device is not limited to an inkjet printer, and may be, for example, a color material ejection device used in the manufacture of color filters for liquid crystal displays, a color material ejection device used in the formation of electrodes for organic electroluminescence displays, surface emission displays, etc. The present invention may be applicable to an electrode material ejection device used in the manufacture of a biochip, a bioorganic material ejection device used in the manufacture of a biochip, or the like.

[0011] 1. Overview of the liquid ejection device 1 is a diagram showing a schematic structure of a liquid ejection device 1. The liquid ejection device 1 in this embodiment is a so-called line printing type inkjet printer that transports a medium P along a transport direction and ejects ink, which is an example of a liquid, onto the transported medium P using print heads 21-1 to 21-7 arranged in a row along a main scanning direction intersecting the transport direction, thereby forming an image on the medium P. Such a liquid ejection device 1 can use any printing target, such as printing paper, a resin film, or a fabric, as the medium P. Note that the liquid ejection device 1 is not limited to a line printing type inkjet printer, and may also be a serial printing type inkjet printer.

[0012] As shown in FIG. 1, the liquid ejection device 1 includes an ink container 5, a control mechanism 10, an ejection mechanism 20, and a transport mechanism 40.

[0013] The ink container 5 stores ink of a plurality of colors to be ejected onto the medium P. Examples of the colors of ink stored in the ink container 5 include black k, cyan c, magenta m, and yellow y. As the ink container 5, an ink cartridge, a bag-shaped ink pack formed of a flexible film, an ink tank that can be refilled with ink, and the like can be used.

[0014] The control mechanism 10 includes a processing circuit such as a CPU (Central Processing Unit) or an FPGA (Field Programmable Gate Array), and a storage circuit such as a semiconductor memory. The control mechanism 10 controls each element of the liquid ejection device 1 including the ejection mechanism 20.

[0015] The ejection mechanism 20 has print heads 21-1 to 21-7. The print heads 21-1 to 21-7 are arranged in a staggered pattern in the order of print head 21-1, print head 21-2, print head 21-3, print head 21-4, print head 21-5, print head 21-6, and print head 21-7 along a scanning direction that intersects with the transport direction in which the medium P is transported.

[0016] The ejection mechanism 20 receives the control signal Ctrl-H, drive signal COM, and reference voltage signal VBS output by the control mechanism 10. The control signal Ctrl-H, drive signal COM, and reference voltage signal VBS are input to each of the print heads 21-1 to 21-7. Ink stored in the ink container 5 is supplied to each of the print heads 21-1 to 21-7 via a tube or the like (not shown). Each of the print heads 21-1 to 21-7 ejects ink supplied from the ink container 5 based on the input control signal Ctrl-H, drive signal COM, and reference voltage signal VBS.

[0017] The transport mechanism 40 includes a transport motor 41 and a transport roller 42. The transport motor 41 is driven to rotate based on a control signal Ctrl-T input from the control mechanism 10. The transport roller 42 rotates in accordance with the rotational drive of the transport motor 41. As the transport roller 42 rotates, the medium P is transported in the transport direction.

[0018] As described above, in the liquid ejection device 1 of this embodiment, the control mechanism 10 controls the transportation of the medium P and the ejection of ink from the ejection mechanism 20. That is, the ejection mechanism 20 ejects ink at a timing linked to the transportation of the medium P by the transport mechanism 40. As a result, the ink ejected from the ejection mechanism 20 lands at a desired position on the medium P. As a result, a desired image is formed on the medium P.

[0019] 2. Functional configuration of the liquid ejection device Next, a description will be given of the functional configuration of the liquid ejection device 1. Fig. 2 is a diagram showing the functional configuration of the liquid ejection device 1. As shown in Fig. 2, the liquid ejection device 1 includes a control mechanism 10, an ejection mechanism 20, and a transport mechanism 40.

[0020] The control mechanism 10 includes drive circuits 50-1 to 50-7, a reference voltage circuit 52, and a control circuit 100.

[0021] The control circuit 100 includes a processor such as a microcontroller, and is communicatively connected to an external device such as a host computer (not shown) that is provided outside the liquid ejection device 1. An image information signal including image data to be formed on the medium P is input from the external device to the control circuit 100. The control circuit 100 performs predetermined image processing on the input image information signal to generate various data for controlling the liquid ejection device 1 and signals corresponding to the data, and outputs the data to corresponding components.

[0022] The control circuit 100 generates a control signal Ctrl-T for controlling the transport of the medium P, and outputs it to the transport mechanism 40. This causes the transport motor 41 of the transport mechanism 40 to rotate, controlling the transport along the transport direction of the medium P. Here, the control signal Ctrl-T output by the control circuit 100 may be converted into a signal by a driver circuit (not shown), and then input to the transport motor 41.

[0023] Furthermore, the control circuit 100 generates print data signals DATA1 to DATA7 as control signals Ctrl-H for controlling the emission mechanism 20 based on the input image information signal, and outputs the print data signals DATA1 to DATA7 to the emission mechanism 20.

[0024] The control circuit 100 also outputs basic drive signals dA1 to dA7, which are digital signals, to the drive circuits 50-1 to 50-7, respectively. The drive circuits 50-1 to 50-7 generate drive signals COM1 to COM7 as the drive signal COM in response to the basic drive signal dA, which is a digital signal input thereto. The drive circuits 50-1 to 50-7 then output the generated drive signals COM1 to COM7 to the emission mechanism 20. Specifically, the drive circuit 50-1 generates drive signal COM1 and outputs it to the emission mechanism 20, the drive circuit 50-7 generates drive signal COM7 and outputs it to the emission mechanism 20, and the drive circuit 50-i (i is any of 1 to 7) generates drive signal COMi and outputs it to the emission mechanism 20.

[0025] The reference voltage circuit 52 generates a reference voltage signal VBS that serves as a reference potential for driving a piezoelectric element 60 (described later) of the emission mechanism 20. Then, the reference voltage circuit 52 outputs the generated reference voltage signal VBS to the emission mechanism 20. Such a reference voltage signal VBS is a signal with a constant voltage value, and may be, for example, a signal with a ground potential value of 0V, or a DC voltage signal with a voltage value of 5.5V, 6V, or the like.

[0026] The ejection mechanism 20 has print heads 21-1 to 21-7. Each of the print heads 21-1 to 21-7 includes a drive signal selection circuit 200 and a plurality of ejection units 600. Each of the plurality of ejection units 600 has a piezoelectric element 60.

[0027] The drive signal selection circuit 200 of the print head 21-1 is configured to include one or more integrated circuit devices. A print data signal DATA1 and a drive signal COM1 are input to the drive signal selection circuit 200 of the print head 21-1. The drive signal selection circuit 200 of the print head 21-1 selects or deselects the signal waveform of the drive signal COM1 based on the input print data signal DATA1, thereby outputting a plurality of ejection portions 600. The driving voltage VOUT corresponding to each of the discharge portions 600 is generated and output to the corresponding discharge portions 600.

[0028] The drive signal selection circuit 200 of the print head 21-7 is configured to include one or more integrated circuit devices. A print data signal DATA7 and a drive signal COM7 are input to the drive signal selection circuit 200 of the print head 21-7. The drive signal selection circuit 200 of the print head 21-7 selects or deselects the signal waveform of the drive signal COM7 based on the input print data signal DATA7, thereby generating drive voltages VOUT corresponding to each of the multiple ejection units 600 and outputting them to the corresponding ejection units 600.

[0029] The drive signal selection circuit 200 of the print head 21-i is configured to include one or more integrated circuit devices. A print data signal DATAi and a drive signal COMi are input to the drive signal selection circuit 200 of the print head 21-i. The drive signal selection circuit 200 of the print head 21-i generates a drive voltage VOUT corresponding to each of the multiple ejection units 600 individually by selecting or not selecting the signal waveform of the drive signal COMi based on the input print data signal DATAi, and outputs the drive voltage VOUT to the corresponding ejection unit 600.

[0030] Here, the drive circuits 50-1 to 50-7 are all of the same configuration, and may be referred to as the drive circuit 50 when there is no need to distinguish between them. The drive circuit 50 will be described as outputting drive signals COM as drive signals COM1 to COM7 based on the basic drive signal dA as basic drive signals dA1 to dA7. The print heads 21-1 to 21-7 are all of the same configuration, and may be referred to as the print head 21 when there is no need to distinguish between them. In this case, the print head 21 will be described as receiving print data signals DATA as print data signals DATA1 to DATA7, and drive signals COM.

[0031] Next, a description will be given of the configuration of the discharge unit 600 to which the driving voltage VOUT is supplied. Fig. 3 is a diagram for explaining a schematic configuration of the discharge unit 600. In addition to the discharge unit 600, Fig. 3 also illustrates a nozzle plate 632, a reservoir 641, and a supply port 661.

[0032] As shown in FIG. 3, the ejection section 600 includes a piezoelectric element 60, a vibration plate 621, a cavity 631, and a nozzle 651. The piezoelectric element 60 includes a piezoelectric body 601 and electrodes 611 and 612. The electrodes 611 and 612 are positioned so as to sandwich the piezoelectric body 601, thereby forming the piezoelectric element 60. The piezoelectric element 60 is driven so that the central portion is displaced in the vertical direction in response to the potential difference between the voltage supplied to the electrode 611 and the voltage supplied to the electrode 612. Specifically, the electrode 611 is supplied with a drive voltage VOUT based on the drive signal COM, and the electrode 612 is supplied with a reference voltage signal VBS. When the voltage value of the drive voltage VOUT supplied to the electrode 611 changes, the potential difference between the drive voltage VOUT supplied to the electrode 611 and the reference voltage signal VBS supplied to the electrode 612 changes. As a result, the piezoelectric element 60 is driven so that the central portion is displaced in the vertical direction.

[0033] The diaphragm 621 is located below the piezoelectric element 60 in Fig. 3. In other words, the piezoelectric element 60 is formed on the upper surface of the diaphragm 621 in Fig. 3. Such a diaphragm 621 is displaced in the vertical direction as the piezoelectric element 60 is driven in the vertical direction.

[0034] A cavity 631 is located below the vibration plate 621 in FIG. 3. Ink is supplied to the cavity 631 from a reservoir 641. In addition, ink stored in the ink container 5 is introduced into the reservoir 641 via a supply port 661. In other words, the inside of the cavity 631 is filled with ink stored in the ink container 5. The internal volume of such cavity 631 expands or contracts with the vertical displacement of diaphragm 621. That is, diaphragm 621 functions as a diaphragm that changes the internal volume of cavity 631, and cavity 631 functions as a pressure chamber in which the pressure changes with the vertical displacement of diaphragm 621.

[0035] The nozzle 651 is an opening provided in the nozzle plate 632, and communicates with the cavity 631. When the internal volume of the cavity 631 changes, ink filled inside the cavity 631 is ejected from the nozzle 651 in accordance with the change in the internal volume.

[0036] In the ejection section 600 configured as above, when the piezoelectric element 60 is driven to bend upward, the vibration plate 621 is displaced upward. This causes the internal volume of the cavity 631 to expand, and as a result, the ink stored in the reservoir 641 is drawn into the cavity 631. On the other hand, when the piezoelectric element 60 is driven to bend downward, the vibration plate 621 is displaced downward. This causes the internal volume of the cavity 631 to shrink, and as a result, an amount of ink corresponding to the degree of shrinkage of the internal volume of the cavity 631 is ejected from the nozzle 651.

[0037] Note that the piezoelectric element 60 is not limited to the structure shown in FIG. 3 as long as it is driven by being supplied with a drive voltage VOUT corresponding to the drive signal COM and is capable of ejecting ink from the nozzle 651 by being driven.

[0038] 3. Functional configuration and operation of the drive circuit 3.1 Signal waveform of drive signal COM Next, the configuration and operation of the drive circuit 50 will be described. In describing the configuration and operation of the drive circuit 50, first, an example of the signal waveform of the drive signal COM output by the drive circuit 50 will be described. FIG. 4 is a diagram showing an example of the signal waveform of the drive signal COM. As shown in FIG. 4, the drive signal COM includes a trapezoidal waveform Adp for each period T. The trapezoidal waveform Adp includes a certain period at voltage vc, a certain period at voltage vb lower than voltage vc following the certain period at voltage vc, a certain period at voltage vb following the certain period at voltage vb and a certain period at voltage vt higher than voltage vc, and a certain period at voltage vt following the certain period at voltage vc.

[0039] The voltage vc corresponds to a potential that is a reference for the displacement of the piezoelectric element 60. When the voltage of the drive signal COM supplied to the piezoelectric element 60 changes from the voltage vc to the voltage vb, the piezoelectric element 60 is driven in the upward direction shown in FIG. 3. As a result, the vibration plate 621 is displaced in the upward direction shown in FIG. 3. When the vibration plate 621 is displaced in the upward direction shown in FIG. 3, the internal volume of the cavity 631 expands, and ink is drawn from the reservoir 641 into the cavity 631. After that, the voltage of the drive signal COM supplied to the piezoelectric element 60 changes from the voltage vb to the voltage vt, and the piezoelectric element 60 is driven in the downward direction shown in FIG. 3. As a result, the vibration plate 621 is displaced in the downward direction shown in FIG. 3. When the vibration plate 621 is displaced in the downward direction shown in FIG. 3, the internal volume of the cavity 631 decreases, and the ink stored in the cavity 631 is ejected from the nozzle 651.

[0040] Furthermore, the ink near the nozzle 651 and the diaphragm 621 may continue to vibrate for a certain period after the ink is ejected from the nozzle 651 by driving the piezoelectric element 60. The certain period of the voltage vc included in the drive signal COM also functions as a period for stopping such vibrations that occur in the ink and the diaphragm 621 and do not contribute to the ejection of ink.

[0041] Here, the signal waveform of the drive signal COM shown in FIG. 4 is an example, and is not limited to this. The signal waveform may vary depending on the physical properties of the ink discharged by the print head 21, the length of the period T of the drive signal COM, the medium, etc. The drive circuits 50-1 to 50-7 may output drive signals COM1 to COM7 each including a different signal waveform.

[0042] 3.2 Drive circuit configuration Next, a configuration of the drive circuit 50 will be described. Fig. 5 is a diagram showing an example of a functional configuration of the drive circuit 50. As shown in Fig. 5, the drive circuit 50 has a DA conversion circuit 510, an adder 511, a pulse modulation circuit 520, an inverter 521, an amplifier circuit 550, a demodulation circuit 560, a feedback circuit 570, a memory circuit 700, a level switching signal generation circuit 710, a level shift circuit 750, and a bootstrap circuit BS.

[0043] The DA conversion circuit 510 receives a reference drive signal dA, which is a digital signal, from the control circuit 100. The DA conversion circuit 510 performs digital-to-analog conversion on the reference drive signal dA, and then outputs the converted analog signal as the reference drive signal aA. The voltage amplitude of this reference drive signal aA is, for example, 1 to 2 V, and the drive circuit 50 outputs a signal obtained by amplifying the reference drive signal aA as the drive signal COM. In other words, the reference drive signal aA corresponds to a target signal before amplification of the drive signal COM.

[0044] The base drive signal aA is input to the positive input terminal of the adder 511. A feedback signal VFB, which is the drive signal COM fed back via a feedback circuit 570 (described later), is input to the negative input terminal of the adder 511. The adder 511 then outputs a signal obtained by subtracting the feedback signal VFB from the base drive signal aA to the pulse modulation circuit 520.

[0045] The pulse modulation circuit 520 generates a modulated signal MS by pulse-modulating the signal output by the adder 511. The modulated signal MS is a digital signal including an L-level potential and an H-level potential higher than the L-level. The pulse modulation circuit 520 outputs the generated modulated signal MS to the amplifier circuit 550. The pulse modulation circuit 520 generates a pulse density modulated signal (PDM signal) by modulating the signal output by the adder 511 by a pulse density modulation (PDM) method, and outputs the PDM signal as the modulated signal MS to the amplifier circuit 550. Specifically, the pulse modulation circuit 520 compares the voltage of the output signal of the adder 511 with a predetermined reference voltage. The pulse modulation circuit 520 generates and outputs a modulated signal MS that is H level when the voltage of the output signal of the adder 511 is higher than the reference voltage, and is L level when the voltage of the output signal of the adder 511 is lower than the reference voltage.

[0046] In this way, the circuit configured by the DA conversion circuit 510, the adder 511, and the pulse modulation circuit 520 functions as a modulation circuit 500 that modulates the basic drive signal dA that is the basis of the drive signal COM, and outputs the modulated signal MS.

[0047] The amplifier circuit 550 includes a gate drive circuit 530, a diode D1, a capacitor C1, and transistors M1 and M2. The amplifier circuit 550 generates a first amplified modulated signal AMS1 by amplifying the modulated signal MS, and outputs the first amplified modulated signal AMS1 from a first output point OP1.

[0048] The gate drive circuit 530 outputs gate signals HGD1 and LGD1 based on the modulation signal MS. Specifically, the modulation signal MS is input to a gate driver 531 included in the gate drive circuit 530. The gate driver 531 generates a gate signal HGD1 by level-shifting the input modulation signal MS and outputs it to the transistor M1. The modulation signal MS is also input to a gate driver 532 included in the gate drive circuit 530 after its logical level is inverted by an inverter 521. The gate driver 532 level-shifts the signal obtained by inverting the logical level of the input modulation signal MS, A gate signal LGD1 is generated and output to the transistor M2.

[0049] The transistors M1 and M2 are both configured as N-channel FETs. The transistor M1 operates based on a gate signal HGD1 input to the gate terminal. A voltage signal VHV1 having a voltage value of vhv1 is supplied as a power supply voltage to a drain terminal which is one end of the transistor M1. A source terminal which is the other end of the transistor M1 is electrically connected to a first output point OP1. The transistor M2 operates based on a gate signal LGD1 input to the gate terminal. A ground potential is supplied to a source terminal which is one end of the transistor M2. A drain terminal which is the other end of the transistor M2 is electrically connected to the first output point OP1. The transistors M1 and M2 configure a transistor pair Mp1. That is, the transistor pair Mp1 includes the transistor M1 and the transistor M2, and the transistors M1 and M2 are configured as FETs.

[0050] The gate drive circuit 530 includes gate drivers 531 and 532. As described above, the modulation signal MS is input to the gate driver 531, and a signal obtained by inverting the logical level of the modulation signal MS by the inverter 521 is input to the gate driver 532. That is, the signal input to the gate driver 531 and the signal input to the gate driver 532 are exclusively at H level. Here, exclusively at H level includes the case where an H level signal is not input to the gate driver 531 and the gate driver 532 at the same time. That is, it does not exclude the case where an L level signal is input to the gate driver 531 and the gate driver 532 at the same time.

[0051] The low-potential power supply terminal of the gate driver 531 is electrically connected to the first output point OP1. Therefore, the signal generated at the first output point OP1 is supplied as a voltage signal HVS1 to the low-potential power supply terminal of the gate driver 531. In addition, the high-potential power supply terminal of the gate driver 531 is electrically connected to the cathode terminal of the diode D1 and one end of the capacitor C1. The anode terminal of the diode D1 is supplied with a voltage vm, and the other end of the capacitor C1 is electrically connected to the first output point OP1. That is, the diode D1 and the capacitor C1 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 531.

[0052] Therefore, a voltage signal HVD1 having a voltage vm higher than the voltage signal HVS1 input to the low-potential power terminal of the gate driver 531 is supplied to the high-potential power terminal of the gate driver 531. When an H-level modulation signal MS is input, the gate driver 531 outputs a gate signal HGD1 having a voltage based on the voltage signal HVD1 having a voltage vm higher than the voltage of the first output point OP1, and when an L-level modulation signal MS is input, the gate driver 531 outputs a gate signal HGD1 having a voltage based on the voltage signal HVS1, which is the voltage of the first output point OP1. Here, the voltage vm is a voltage value capable of driving the transistors M1 and M2 and the transistors M3 and M4 described later, and is, for example, a DC voltage of 7.5 V.

[0053] A ground potential signal is supplied as a voltage signal LVS1 to a low potential power supply terminal of the gate driver 532. A voltage vm is supplied as a voltage signal LVD1 to a high potential power supply terminal of the gate driver 532. Thus, when an H level signal obtained by inverting the logical level of an L level modulation signal MS by the inverter 521 is input to the gate driver 532, the gate driver 532 outputs a gate signal LGD1 of a voltage based on the voltage signal LVD1 of the voltage vm, and when an L level signal obtained by inverting the logical level of an H level modulation signal MS by the inverter 521 is input to the gate driver 532, the gate driver 532 outputs a gate signal LGD1 of a voltage based on the voltage signal LVS1 of the ground potential.

[0054] Then, the transistor M1 operates based on the gate signal HGD1, and the transistor M2 operates based on the gate signal LGD1, so that a first amplified modulated signal AMS1 obtained by amplifying the modulated signal MS with the voltage vhv1 is generated at the first output point OP1. The first amplified modulated signal AMS1 generated at the first output point OP1 of this transistor pair Mp1 is output from the amplifier circuit 550.

[0055] Here, a modulation circuit 500 including a DA conversion circuit 510, an adder 511, and a pulse modulation circuit 520, and a gate drive circuit 530 including gate drivers 531 and 532 are configured as an integrated circuit Q1 which is a single semiconductor device.

[0056] The level switching signal generating circuit 710 receives a reference drive signal dA, which is a digital signal, from the control circuit 100. The level switching signal generating circuit 710 generates and outputs a level switching signal LS including an L level potential and an H level potential higher than the L level based on the reference drive signal dA. Specifically, when the value of the reference drive signal dA increases and exceeds a threshold value dvth while the level switching signal LS is at an L level, the level switching signal generating circuit 710 switches the logical level of the level switching signal LS from an L level to an H level. Also, when the value of the reference drive signal dA decreases and becomes smaller than a threshold value dvth while the level switching signal LS is at an H level, the level switching signal generating circuit 710 switches the logical level of the level switching signal LS from an H level to an L level.

[0057] The threshold value dvth is stored in the storage circuit 700. The storage circuit 700 may be, for example, a non-volatile memory. Alternatively, the storage circuit 700 may be a volatile memory, and the threshold value dvth may be set in the storage circuit 700 by external communication from the control circuit 100 or the like. In other words, the threshold value dvth may be a predetermined value, or may be rewritable from outside the drive circuit 50.

[0058] The level shift circuit 750 includes a gate drive circuit 730, diodes D11 and D12, capacitors C11 and C12, and transistors M3 and M4. The level shift circuit 750 outputs the first amplified modulated signal AMS1 output by the amplifier circuit 550, or a signal obtained by shifting the reference potential of the first amplified modulated signal AMS1 by the amplifier circuit 550, from a second output point OP2 as a second amplified modulated signal AMS2.

[0059] The gate drive circuit 730 outputs gate signals HGD2 and LGD2 based on the level switching signal LS. Specifically, the level switching signal LS is input to a gate driver 731 included in the gate drive circuit 730. The gate driver 731 generates a gate signal HGD2 by level-shifting the level switching signal LS and outputs it to the transistor M3. The level switching signal LS is also input to a gate driver 732 included in the gate drive circuit 730 after the logical level of the level switching signal LS is inverted by an inverter 721. The gate driver 732 generates a gate signal LGD2 by level-shifting a signal obtained by inverting the logical level of the input level switching signal LS and outputs it to the transistor M4.

[0060] The transistors M3 and M4 are both configured as N-channel FETs. The transistor M3 operates based on a gate signal HGD2 input to the gate terminal. A voltage signal VHV2 having a voltage value of vhv2 output by a bootstrap circuit BS (described later) is supplied as a power supply voltage to a drain terminal, which is one end of the transistor M3. The source terminal, which is the other end of the transistor M3, is electrically connected to a second output point OP2. The transistor M4 operates based on a gate signal LGD2 input to the gate terminal. A first amplified modulation signal AMS1 is supplied to a source terminal, which is one end of the transistor M4. The drain terminal, which is the other end of the transistor M4, is electrically connected to a second output point OP2. The transistor M3 and the transistor M4 constitute a transistor pair Mp2. That is, the transistor pair Mp2 includes the transistor M3 and the transistor M4, and the transistors M3 and M4 are constituted by FETs.

[0061] The gate drive circuit 730 includes gate drivers 731 and 732. As described above, the level switching signal LS is input to the gate driver 731, and a signal obtained by inverting the logical level of the level switching signal LS by the inverter 721 is input to the gate driver 732. That is, the signal input to the gate driver 731 and the signal input to the gate driver 732 are exclusively at H level. Here, exclusively at H level includes the case where an H level signal is not input to the gate driver 731 and the gate driver 732 at the same time. That is, it does not exclude the case where an L level signal is input to the gate driver 731 and the gate driver 732 at the same time.

[0062] The low-potential power supply terminal of the gate driver 731 is electrically connected to the second output point OP2. Therefore, the signal generated at the second output point OP2 is supplied as a voltage signal HVS2 to the low-potential power supply terminal of the gate driver 731. In addition, the high-potential power supply terminal of the gate driver 731 is electrically connected to the cathode terminal of the diode D11 and one end of the capacitor C11. In addition, the voltage vm is supplied to the anode terminal of the diode D11, and the other end of the capacitor C11 is electrically connected to the second output point OP2. That is, the diode D11 and the capacitor C11 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 731.

[0063] Therefore, a voltage signal HVD2 having a voltage vm higher than the voltage signal HVS2 input to a low potential power terminal of the gate driver 731 is supplied to a high potential power terminal of the gate driver 731. When an H level level switching signal LS is input to the gate driver 731, the gate driver 731 outputs a gate signal HGD2 having a voltage based on the voltage signal HVD2 having a voltage vm higher than the voltage of the second output point OP2, and when an L level switching signal LS is input, the gate driver 731 outputs a gate signal HGD2 having a voltage based on the voltage signal HVS2, which is the voltage of the second output point OP2.

[0064] The low-potential power supply terminal of the gate driver 732 is electrically connected to the first output point OP1. Therefore, the first amplified modulation signal AMS1 generated at the first output point OP1 is supplied as a voltage signal LVS2 to the low-potential power supply terminal of the gate driver 732. In addition, the high-potential power supply terminal of the gate driver 732 is electrically connected to the cathode terminal of the diode D12 and one end of the capacitor C12. In addition, the voltage vm is supplied to the anode terminal of the diode D12, and the other end of the capacitor C12 is electrically connected to the first output point OP1. That is, the diode D12 and the capacitor C12 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 732.

[0065] Therefore, a voltage signal LVD2 having a voltage vm higher than the voltage signal LVS2 input to a low potential power terminal of the gate driver 732 is supplied to a high potential power terminal of the gate driver 732. When an H level signal obtained by inverting the logical level of the L level level switching signal LS by the inverter 721 is input to the gate driver 732, the gate driver 732 outputs a gate signal LGD2 having a voltage value based on the voltage signal LVD2 having a voltage vm higher than the voltage of the first output point OP1, and when an L level signal obtained by inverting the logical level of the H level level switching signal LS by the inverter 721 is input to the gate driver 732, the gate driver 732 outputs a gate signal HGD2 having a voltage based on the voltage signal LVS2, which is the voltage of the first output point OP1.

[0066] Then, the transistor M3 operates based on the gate signal HGD2, and the transistor M4 operates based on the gate signal LGD2, so that the first amplified modulated signal AMS1 or the second amplified modulated signal AMS2 obtained by shifting the reference potential of the first amplified modulated signal AMS1 is generated as the second amplified modulated signal AMS2 at the second output point OP2 of the transistor pair Mp2. The second amplified modulated signal AMS2 generated at the second output point OP2 of the transistor pair Mp2 is output from the level shift circuit 750.

[0067] The bootstrap circuit BS includes a diode D13 and a capacitor C13. One end of the capacitor C13 is electrically connected to the first output point OP1, and the other end is electrically connected to the drain terminal of the transistor M3. A voltage signal VHV1 is supplied to the anode terminal of the diode D13 via the diodes D21, D22, and D23. A cathode terminal of the diode D13 is electrically connected to the other end of the capacitor C13 and the drain terminal of the transistor M3. Therefore, the bootstrap circuit BS outputs a voltage signal VHV2 obtained by shifting the reference potential of the first amplified modulation signal AMS1 output to the first output point OP1 by a voltage value obtained by subtracting the sum of the forward drop voltage Vf1 of the diode D13, the forward drop voltage Vf2 of the diode D21, the forward drop voltage Vf3 of the diode D22, and the forward drop voltage Vf4 of the diode D23 from the voltage vhv1, which is the voltage value of the voltage signal VHV1.

[0068] Therefore, when the level switching signal generation circuit 710 outputs an L-level level switching signal LS, the level shift circuit 750 outputs the first amplified modulated signal AMS1 output to the first output point OP1 of the amplifier circuit 550 from the second output point OP2 as the second amplified modulated signal AMS2. On the other hand, when the level switching signal generation circuit 710 outputs an H-level level switching signal LS, the level shift circuit 750 outputs a voltage signal VHV2 obtained by shifting the reference potential of the first amplified modulated signal AMS1 output to the first output point OP1 of the amplifier circuit 550 by a voltage value obtained by subtracting the sum of the forward drop voltages Vf1, Vf2, Vf3, and Vf4 from the voltage signal VHV1 as the second amplified modulated signal AMS2 from the second output point OP2.

[0069] As described above, the bootstrap circuit BS includes the capacitor C13 and the diode D13, and level-shifts the voltage value of the voltage signal VHV1, which is the power supply voltage supplied to the transistor pair Mp1 including the transistors M1 and M2 of the amplifier circuit 550, in accordance with the first amplified modulation signal AMS1 and supplies it to the transistor pair Mp2. A drain terminal which is one end of the transistor M3 is electrically connected to the bootstrap circuit BS, the first amplified modulation signal AMS1 is supplied to a source terminal which is one end of the transistor M4, and the other end of the transistor M3 and the other end of the transistor M4 are electrically connected at the second output point OP2, so that a second amplified modulation signal AMS2 is output from the second output point OP2.

[0070] In the following description, an operation mode in which the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 is referred to as a first mode MD1, and an operation mode in which a signal obtained by shifting the reference potential of the first amplified modulated signal AMS1 is output as the second amplified modulated signal AMS2 is referred to as a second mode MD2. That is, the level shift circuit 750 is in the first mode MD1 when the level switching signal LS is at an L level, and in the second mode MD2 when the level switching signal LS is at an H level.

[0071] For example, when the voltage value defined by the reference drive signal dA is smaller than the threshold value dvth, the level switching signal generation circuit 710 outputs an L-level level switching signal LS. Therefore, the level shift circuit 750 operates in the first mode MD1. After that, when the voltage value defined by the reference drive signal dA becomes larger than the threshold value dvth, the level switching signal generation circuit 710 The level switching signal LS is switched from L level to H level. This switches the operation mode of the level shift circuit 750 from the first mode MD1 to the second mode MD2. Furthermore, when the voltage value defined by the reference drive signal dA is greater than the threshold value dvth, the level switching signal generation circuit 710 outputs the level switching signal LS of H level. Therefore, the level shift circuit 750 operates in the second mode MD2. Thereafter, when the voltage value defined by the reference drive signal dA becomes smaller than the threshold value dvth, the level switching signal generation circuit 710 switches the level switching signal LS from H level to L level. This switches the operation mode of the level shift circuit 750 from the second mode MD2 to the first mode MD1.

[0072] The level switching signal generating circuit 710 of this embodiment outputs, as the level switching signal LS, a pulse signal that is at L level for a short period of time, one or more times, immediately after switching the level switching signal LS from L level to H level. Also, the level switching signal generating circuit 710 of this embodiment outputs, as the level switching signal LS, a pulse signal that is at H level for a short period of time, one or more times, immediately after switching the level switching signal LS from H level to L level. This reduces the risk of distortion occurring in the signal waveform of the drive signal COM when the operation mode of the level shift circuit 750 is switched.

[0073] In the following description, a pulse signal that becomes L level for a short period of time when the operation mode of the level shift circuit 750 is switched from the first mode MD1 to the second mode MD2, and a pulse signal that becomes H level for a short period of time when the operation mode of the level shift circuit 750 is switched from the second mode MD2 to the first mode MD1 may be referred to as a counter pulse CP. In the liquid ejection device 1 of this embodiment, the memory circuit 700, the level switching signal generation circuit 710, and the gate drive circuit 730 including the gate drivers 731 and 732 are configured as an integrated circuit Q2 that is a single semiconductor device.

[0074] The second amplified modulated signal AMS2 output by the level shift circuit 750 is input to the demodulation circuit 560. The demodulation circuit 560 smoothes and demodulates the second amplified modulated signal AMS2 output by the level shift circuit 750, and outputs the drive signal COM.

[0075] The demodulation circuit 560 includes an inductor 561 and a capacitor 562. One end of the inductor 561 is electrically connected to the second output point OP2. The other end of the inductor 561 is electrically connected to one end of the capacitor 562. The other end of the capacitor 562 is supplied with a ground potential. That is, the inductor 561 and the capacitor 562 configure a low-pass filter circuit. The second amplified modulation signal AMS2 output from the level shift circuit 750 is smoothed by this low-pass filter circuit, and is output from the drive circuit 50 as the drive signal COM.

[0076] The drive signal COM generated by the demodulation circuit 560 is input to the feedback circuit 570. The feedback circuit 570 generates a feedback signal VFB according to the input drive signal COM and outputs it to the modulation circuit 500. Specifically, the feedback circuit 570 supplies the feedback signal VFB obtained by dividing the drive signal COM to the adder 511. This causes the drive signal COM to be fed back to the pulse modulation circuit 520. As a result, the waveform accuracy of the drive signal COM output by the drive circuit 50 is improved. Here, the feedback circuit 570 may feed back, as the feedback signal VFB, a plurality of signals including a signal obtained by dividing the drive signal COM and a signal obtained by extracting high-frequency components from the drive signal COM. That is, the feedback circuit 570 may include a plurality of feedback circuits including a circuit that feeds back a signal obtained by dividing the drive signal COM and a circuit that feeds back a signal obtained by extracting high-frequency components from the drive signal COM. This makes it possible to individually feed back the high-frequency components included in the drive signal COM. As a result, the driving circuit 50 can self-oscillate based on the high-frequency component, and the frequency of the modulation signal MS can be increased to a level that ensures sufficient accuracy of the driving signal COM. It will improve further.

[0077] The frequency of the drive signal COM output by the drive circuit 50 configured as above is several tens of kHz, whereas the frequency of the gate signals HGD1, LGD1 output by the gate drive circuit 530 is several MHz from the viewpoint of generating the signal waveform of the drive signal COM with high accuracy. On the other hand, the gate signals HGD2, LGD2 output by the gate drive circuit 730 are signals whose logical level changes several times in the period T in which the drive signal COM is generated, and therefore the frequency of the gate signals HGD2, LGD2 is several times the frequency of the drive signal COM, for example, several tens of kHz to several hundreds of kHz. That is, the frequency of the gate signals HGD1, LGD1 is higher than the frequency of the gate signals HGD2, LGD2. This reduces the switching loss in the transistors M3, M4.

[0078] As described above, the drive circuit 50 of this embodiment has a gate drive circuit 530 that outputs gate signals HGD1, LGD1 in response to the basic drive signal dA, an amplifier circuit 550 including a transistor pair Mp1 that includes a transistor M1 that drives in response to the gate signal HGD1 and a transistor M2 that drives in response to the gate signal LGD1 and outputs a first amplified modulation signal AMS1 in response to the gate signals HGD1, LGD1, a gate drive circuit 730 that outputs gate signals HGD2, LGD2 in response to the basic drive signal dA, and a level shift circuit 750 that includes a transistor M3 that drives in response to the gate signal HGD2 and a transistor M4 that drives in response to the gate signal LGD2 and includes a transistor pair Mp2 that outputs a second amplified modulation signal AMS2 in response to the first amplified modulation signal AMS1, and a demodulation circuit 560 that smooths the second amplified modulation signal AMS2 to demodulate it and output it as a drive signal COM.

[0079] That is, in the driving circuit 50 of this embodiment, the modulation circuit 500 has a DA conversion circuit 510 that converts the basic drive signal dA into a basic drive signal aA that is an analog signal, and a pulse modulation circuit 520 that outputs a modulated signal MS obtained by modulating the basic drive signal aA. The modulation circuit 500 and the amplifier circuit 550 output a first amplified modulated signal AMS1 obtained by amplifying the modulated signal MS based on the basic drive signal dA, and the level shift circuit 750 outputs a second amplified modulated signal AMS2 obtained by shifting the reference potential of the first amplified modulated signal AMS1 based on the basic drive signal dA. The demodulation circuit 560 smoothes and demodulates the second amplified modulated signal AMS2 to output the driving signal COM.

[0080] In the drive circuit 50 configured as described above, the voltage value of the voltage signal VHV1, which serves as the power supply voltage supplied to the transistors M1 and M2, can be reduced. This reduces switching loss in the transistors M1 and M2. As a result, the power consumption of the drive circuit 50 can be reduced compared to when the drive circuit 50 is configured with a class AB amplifier circuit or a general class D amplifier circuit.

[0081] 3.3 Operation of the driver circuit Next, a description will be given of the operation of the drive circuit 50. Fig. 6 is a diagram for explaining the operation of the drive circuit 50. Note that Fig. 6 only illustrates the drive signal COM in an arbitrary period T among the drive signals COM output by the drive circuit 50.

[0082] As shown in Fig. 6, in the period from time t0 to time t10, a basic drive signal dA of a digital value dvc is input to the DA conversion circuit 510. At this time, the drive circuit 50 outputs a drive signal COM of a voltage vc. Since the digital value dvc is greater than the threshold value dvth, the level switching signal generation circuit 710 outputs a level switching signal LS of an H level. As a result, the operation mode of the level shift circuit 750 becomes the second mode MD2, and the level shift circuit 750 outputs a second amplified modulated signal AMS2 obtained by shifting the reference potential of the first amplified modulated signal AMS1. .

[0083] During the period from time t10 to time t20, the basic drive signal dA decreasing from a digital value dvc to a digital value dvb is input to the DA conversion circuit 510. At this time, the drive circuit 50 outputs a drive signal COM decreasing from a voltage vc to a voltage vb. Then, at time tc1 within the period from time t10 to time t20, when the value defined by the basic drive signal dA falls below a threshold value dvth, the level switching signal generation circuit 710 outputs a predetermined number of counter pulses CP, and then switches the logical level of the level switching signal LS from an H level to an L level. As a result, the operation mode of the level shift circuit 750 transitions from the second mode MD2 to the first mode MD1. Therefore, in the period from time t10 to time tc1, the level shift circuit 750 outputs the second amplified modulated signal AMS2 obtained by shifting the reference potential of the first amplified modulated signal AMS1, and in the period from time tc1 to time t20, it outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0084] In the period from time t20 to time t30, the basic drive signal dA of the digital value dvb is input to the DA conversion circuit 510. At this time, the drive circuit 50 outputs the drive signal COM of the voltage vb. Since the digital value dvb is smaller than the threshold value dvth, the level switching signal generation circuit 710 outputs the level switching signal LS of the L level. As a result, the operation mode of the level shift circuit 750 maintains the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0085] During the period from time t30 to time t40, the basic drive signal dA that increases from a digital value dvb to a digital value dvt is input to the DA conversion circuit 510. At this time, the drive circuit 50 outputs a drive signal COM that increases from a voltage vb to a voltage vt. Then, at time tc2 within the period from time t30 to time t40, when the value defined by the basic drive signal dA exceeds a threshold value dvth, the level switching signal generation circuit 710 outputs a predetermined number of counter pulses CP and then switches the logical level of the level switching signal LS from an L level to an H level. As a result, the operation mode of the level shift circuit 750 transitions from the first mode MD1 to the second mode MD2. As a result, the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 during the period from time t30 to time tc2, and outputs the second amplified modulated signal AMS2 obtained by shifting the reference potential of the first amplified modulated signal AMS1 during the period from time tc2 to time t40.

[0086] In the period from time t40 to time t50, a basic drive signal dA of a digital value dvt is input to the DA conversion circuit 510. At this time, the drive circuit 50 outputs a drive signal COM of a voltage vt. Since the digital value dvt is greater than the threshold value dvth, the level switching signal generation circuit 710 generates a level switching signal LS of an H level. As a result, the operation mode of the level shift circuit 750 maintains the second mode MD2, and the level shift circuit 750 outputs a signal obtained by shifting the reference potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0087] In the period from time t50 to time t60, the basic drive signal dA decreasing from the digital value dvt to the digital value dvc is input to the DA conversion circuit 510. At this time, the drive circuit 50 outputs a drive signal COM decreasing from the voltage vt to the voltage vc. In the period from time t50 to time t60, the digital value of the basic drive signal dA is greater than the threshold value dvth, so the level switching signal generation circuit 710 outputs an H-level level switching signal LS. Therefore, the operation mode of the level shift circuit 750 maintains the second mode MD2, and the level shift circuit 750 outputs a signal obtained by shifting the potential of the first amplified modulation signal AMS1 as the second amplified modulation signal AMS2.

[0088] During the period from time t60 to time t70, the DA conversion circuit 510 receives the digital value dvc. A basic drive signal dA is input. At this time, the drive circuit 50 outputs a drive signal COM of a voltage vc. Since the digital value dvc is greater than the threshold value dvth, the level switching signal generation circuit 710 outputs a level switching signal LS of an H level. As a result, the operation mode of the level shift circuit 750 maintains the second mode MD2, and the level shift circuit 750 outputs a signal obtained by shifting the potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0089] Here, time t70 corresponds to the above-mentioned time t0. The drive circuit 50 repeats the above-mentioned operation from time t0 to t70 every cycle T, thereby outputting the drive signal COM having the signal waveform shown in FIG.

[0090] 4. Configuration of the drive circuit board Next, a structure of the drive circuit board 300 on which various circuits including the drive circuits 50-1 to 50-7 configured as above are mounted will be described.

[0091] 7 is a diagram showing an example of the structure of the drive circuit board 300. Here, in describing the structure of the drive circuit board 300, the description will be given using an X-axis and a Y-axis which are perpendicular to each other. When defining a direction along the X-axis, the starting point side of the illustrated arrow may be referred to as the -X side, and the tip side as the +X side, and when defining a direction along the Y-axis, the starting point side of the illustrated arrow may be referred to as the -Y side, and the tip side as the +Y side.

[0092] As shown in FIG. 7, the drive circuit board 300 has a wiring board 310. The wiring board 310 may be a glass epoxy board or a glass composite board including one or more wiring layers. The wiring board 310 includes sides 311, 312, 313, and 314. The sides 311 and 312 are positioned opposite each other along the X axis such that the side 311 is on the -X side and the side 312 is on the +X side. The sides 313 and 314 are positioned opposite each other along the Y axis such that the side 313 is on the -Y side and the side 314 is on the +Y side. That is, the wiring board 310 includes the sides 311 and 312 positioned opposite each other along the X axis in a direction from the -X side to the +X side, and the sides 313 and 314 positioned opposite each other along the Y axis in a direction from the -Y side to the +Y side.

[0093] Sides 311 and 312 intersect with sides 313 and 314, respectively. That is, wiring board 310 of this embodiment has a substantially rectangular shape. Note that wiring board 310 is not limited to a rectangular shape, and may be a polygonal shape such as a pentagon or hexagon, and further, a cutout may include an arc in part.

[0094] The wiring board 310 is provided with an integrated circuit Q3, driving circuits 50-1 to 50-7, and a connector CN.

[0095] The integrated circuit Q3 is a semiconductor device including at least a part of the control circuit 100 of the control mechanism 10. Among the multiple functions of the control circuit 100, the integrated circuit Q3 has at least the function of outputting basic drive signals dA1 to dA7 to the drive circuits 50-1 to 50-7, respectively.

[0096] Drive circuit mounting areas 51-1 to 51-7 are located on the +X side of integrated circuit Q3. Drive circuit mounting area 51-1 is a substantially rectangular area with its longitudinal direction along the X-axis along side 313 of wiring board 310, and drive circuit 50-1 is mounted in drive circuit mounting area 51-1. Drive circuit mounting area 51-2 is located on the +Y side of drive circuit mounting area 51-1, and is a substantially rectangular area with its longitudinal direction along the X-axis, and drive circuit 50-2 is mounted in drive circuit mounting area 51-2. Drive circuit mounting area 51-3 is located on the +Y side of drive circuit mounting area 51-2, and is a substantially rectangular area with its longitudinal direction along the X-axis. and the driving circuit 50-3 is mounted in the driving circuit mounting area 51-3. The driving circuit mounting area 51-4 is located on the +Y side of the driving circuit mounting area 51-3, and is a substantially rectangular area whose longitudinal direction is along the X-axis, and the driving circuit 50-4 is mounted in the driving circuit mounting area 51-4. The driving circuit mounting area 51-5 is located on the +Y side of the driving circuit mounting area 51-4, and is a substantially rectangular area whose longitudinal direction is along the X-axis, and the driving circuit 50-5 is mounted in the driving circuit mounting area 51-5. The driving circuit mounting area 51-6 is located on the +Y side of the driving circuit mounting area 51-5, and is a substantially rectangular area whose longitudinal direction is along the X-axis, and the driving circuit 50-6 is mounted in the driving circuit mounting area 51-6. The drive circuit mounting area 51-7 is located on the +Y side of the drive circuit mounting area 51-6, and is a substantially rectangular area with its longitudinal direction along the X axis. The drive circuit 50-7 is mounted in this drive circuit mounting area 51-7.

[0097] That is, in the wiring board 310, the length along the X-axis of the drive circuit mounting area 51-1 in which the drive circuit 50-1 is provided is longer than the length along the Y-axis, the length along the X-axis of the drive circuit mounting area 51-2 in which the drive circuit 50-2 is provided is longer than the length along the Y-axis, the length along the X-axis of the drive circuit mounting area 51-3 in which the drive circuit 50-3 is provided is longer than the length along the Y-axis, the length along the X-axis of the drive circuit mounting area 51-4 in which the drive circuit 50-4 is provided is longer than the length along the Y-axis, the length along the X-axis of the drive circuit mounting area 51-5 in which the drive circuit 50-5 is provided is longer than the length along the Y-axis, the length along the X-axis of the drive circuit mounting area 51-6 in which the drive circuit 50-6 is provided is longer than the length along the Y-axis, and the length along the X-axis of the drive circuit mounting area 51-7 in which the drive circuit 50-7 is provided is longer than the length along the Y-axis.

[0098] Here, the length along the X-axis of each of drive circuit mounting areas 51-1 to 51-7 may be the distance along the X-axis from the electronic component located furthest on the -X side to the electronic component located furthest on the +X side among the electronic components that make up drive circuit 50, and the length along the Y-axis of each of drive circuit mounting areas 51-1 to 51-7 may be the distance along the X-axis from the electronic component located furthest on the -Y side to the electronic component located furthest on the +Y side among the electronic components that make up drive circuit 50.

[0099] As described above, drive circuits 50-1 to 50-7 are mounted on wiring board 310 on the +X side of integrated circuit Q3 along the Y axis from the -Y side to the +Y side in the order of drive circuit 50-1, drive circuit 50-2, drive circuit 50-3, drive circuit 50-4, drive circuit 50-5, drive circuit 50-6, and drive circuit 50-7. That is, drive circuits 50-1 to 50-7 are provided so as to at least partially overlap when viewed from the direction along the Y axis.

[0100] In this case, the drive circuit mounting regions 51-1 to 51-7 are positioned so as to at least partially overlap each other when viewed along the Y axis.

[0101] Specifically, the driving circuits 50-1 to 50-7 mounted in the corresponding driving circuit mounting regions 51-1 to 51-7 are arranged such that the integrated circuit Q1 of the driving circuit 50-1, the integrated circuit Q1 of the driving circuit 50-2, the integrated circuit Q1 of the driving circuit 50-3, the integrated circuit Q1 of the driving circuit 50-4, the integrated circuit Q1 of the driving circuit 50-5, the integrated circuit Q1 of the driving circuit 50-6, and the integrated circuit Q1 of the driving circuit 50-7 are arranged on the Y axis. The integrated circuit Q2 of the drive circuit 50-1, the integrated circuit Q2 of the drive circuit 50-2, the integrated circuit Q2 of the drive circuit 50-3, the integrated circuit Q2 of the drive circuit 50-4, the integrated circuit Q2 of the drive circuit 50-5, the integrated circuit Q2 of the drive circuit 50-6, and the integrated circuit Q2 of the drive circuit 50-7 are positioned so as to overlap at least partially when viewed along the Y-axis.

[0102] That is, the integrated circuits Q1 of each of the driving circuits 50-1 to 50-7 are arranged so as to at least partially overlap when viewed along the Y axis, and the integrated circuits Q2 of each of the driving circuits 50-1 to 50-7 are arranged so as to at least partially overlap when viewed along the Y axis.

[0103] Furthermore, the driving circuits 50-1 to 50-7 mounted in the corresponding driving circuit mounting regions 51-1 to 51-7 include a transistor M1 included in the driving circuit 50-1, a transistor M1 included in the driving circuit 50-2, a transistor M1 included in the driving circuit 50-3, a transistor M1 included in the driving circuit 50-4, a transistor M1 included in the driving circuit 50-5, a transistor M1 included in the driving circuit 50-6, and a transistor M1 included in the driving circuit 50-7. When viewed along the Y-axis, the transistor M2 of the drive circuit 50-1, the transistor M2 of the drive circuit 50-2, the transistor M2 of the drive circuit 50-3, the transistor M2 of the drive circuit 50-4, the transistor M2 of the drive circuit 50-5, the transistor M2 of the drive circuit 50-6, and the transistor M2 of the drive circuit 50-7 are at least partially overlapped with each other when viewed along the Y-axis. When viewed along the Y axis, the transistor M3 of the drive circuit 50-1, the transistor M3 of the drive circuit 50-2, the transistor M3 of the drive circuit 50-3, the transistor M3 of the drive circuit 50-4, the transistor M3 of the drive circuit 50-5, the transistor M3 of the drive circuit 50-6, and the transistor M3 of the drive circuit 50-7 are at least partially overlapped with each other. are positioned so as to overlap at least partially when viewed along the Y-axis, and the transistor M4 of the drive circuit 50-1, the transistor M4 of the drive circuit 50-2, the transistor M4 of the drive circuit 50-3, the transistor M4 of the drive circuit 50-4, the transistor M4 of the drive circuit 50-5, the transistor M4 of the drive circuit 50-6, and the transistor M4 of the drive circuit 50-7 are positioned so as to overlap at least partially when viewed along the Y-axis.

[0104] That is, the transistors M1 in each of the driving circuits 50-1 to 50-7 are arranged so as to overlap at least partially when viewed along the Y axis, the transistors M2 in each of the driving circuits 50-1 to 50-7 are arranged so as to overlap at least partially when viewed along the Y axis, the transistors M3 in each of the driving circuits 50-1 to 50-7 are arranged so as to overlap at least partially when viewed along the Y axis, and the transistors M4 in each of the driving circuits 50-1 to 50-7 are arranged so as to overlap at least partially when viewed along the Y axis.

[0105] Moreover, the drive circuits 50-1 to 50-7 mounted in the corresponding drive circuit mounting regions 51-1 to 51-7 are positioned such that the inductor 561 of the drive circuit 50-1, the inductor 561 of the drive circuit 50-2, the inductor 561 of the drive circuit 50-3, the inductor 561 of the drive circuit 50-4, the inductor 561 of the drive circuit 50-5, the inductor 561 of the drive circuit 50-6, and the inductor 561 of the drive circuit 50-7 at least partially overlap when viewed along the Y axis. That is, the demodulation circuits 560 of the drive circuits 50-1 to 50-7 are provided so as to at least partially overlap when viewed along the Y axis.

[0106] The connector CN is located on the +X side of the drive circuit mounting areas 51-1 to 51-7 arranged in parallel along the Y axis, and on the +X side of the drive circuits 50-1 to 50-7 arranged in parallel along the Y axis, so that multiple terminals TM are arranged in parallel along the Y axis. The connector CN has multiple terminals TM. Multiple signals including drive signals COM1 to COM7 output by each of the drive circuits 50-1 to 50-7 are input to the multiple terminals TM of the connector CN. The connector CN electrically connects the emission mechanism 20 and the drive circuit board 300. As a result, a plurality of signals including the drive signals COM1 to COM7 outputted from the drive circuits 50-1 to 50-7 are outputted to the emission mechanism 20.

[0107] At this time, the connector CN is provided so that the distance between the inductor 561 of each of the drive circuits 50-1 to 50-7 arranged in parallel along the Y axis is approximately equal. The shortest distance between the inductor 561 of the drive circuit 50-1 and the connector CN, the shortest distance between the inductor 561 of the drive circuit 50-2 and the connector CN, the shortest distance between the inductor 561 of the drive circuit 50-3 and the connector CN, the shortest distance between the inductor 561 of the drive circuit 50-4 and the connector CN, the shortest distance between the inductor 561 of the drive circuit 50-5 and the connector CN, the shortest distance between the inductor 561 of the drive circuit 50-6 and the connector CN, and the shortest distance between the inductor 561 of the drive circuit 50-7 and the connector CN are approximately equal.

[0108] Furthermore, in the connector, terminal TM to which drive signal COM1 is input, terminal TM to which drive signal COM2 is input, terminal TM to which drive signal COM3 is input, terminal TM to which drive signal COM4 is input, terminal TM to which drive signal COM5 is input, terminal TM to which drive signal COM6 is input, and terminal TM to which drive signal COM7 is input are set so that the path length of the propagation path through which drive signal COM1 is propagated, the path length of the propagation path through which drive signal COM2 is propagated, the path length of the propagation path through which drive signal COM3 is propagated, the path length of the propagation path through which drive signal COM4 is propagated, the path length of the propagation path through which drive signal COM5 is propagated, the path length of the propagation path through which drive signal COM6 is propagated, and the path length of the propagation path through which drive signal COM7 is propagated are approximately equal.

[0109] That is, the wiring length of the propagation path electrically connecting the inductor 561 and the connector CN of the drive circuit 50-1, the wiring length of the propagation path electrically connecting the inductor 561 and the connector CN of the drive circuit 50-2, the wiring length of the propagation path electrically connecting the inductor 561 and the connector CN of the drive circuit 50-3, the wiring length of the propagation path electrically connecting the inductor 561 and the connector CN of the drive circuit 50-4, the wiring length of the propagation path electrically connecting the inductor 561 and the connector CN of the drive circuit 50-5, the wiring length of the propagation path electrically connecting the inductor 561 and the connector CN of the drive circuit 50-6, and the wiring length of the propagation path electrically connecting the inductor 561 and the connector CN of the drive circuit 50-7 are approximately equal.

[0110] This reduces the risk that variations will occur in the signal waveforms of the drive signals COM1 to COM7 input to the corresponding print heads 21-1 to 21-7 due to the influence of the impedance of the propagation path of each of the drive signals COM1 to COM7.

[0111] As described above, the drive circuit board 300 which outputs drive signals COM1 to COM7 to drive the piezoelectric element 60, which is the capacitive load of this embodiment, comprises a drive circuit 50-1 which outputs a drive signal COM1 in response to a basic drive signal dA1, a drive circuit 50-2 which outputs a drive signal COM2 in response to a basic drive signal dA2, a drive circuit 50-3 which outputs a drive signal COM3 in response to a basic drive signal dA3, a drive circuit 50-4 which outputs a drive signal COM4 in response to a basic drive signal dA4, a drive circuit 50-5 which outputs a drive signal COM5 in response to a basic drive signal dA5, a drive circuit 50-6 which outputs a drive signal COM6 in response to a basic drive signal dA6, a drive circuit 50-7 which outputs a drive signal COM7 in response to a basic drive signal dA7, an integrated circuit Q3 which outputs the basic drive signals dA1 to dA7, a connector CN which outputs the drive signals COM1 to COM7, and a wiring board 310 on which the drive circuits 50-1 to 50-7, the integrated circuit Q3, and the connector CN are provided.

[0112] In addition, in the wiring board 310, the driving circuit 50-1, the integrated circuit Q3, and the connector CN is arranged along the X-axis from the -X side to the +X side in the order of integrated circuit Q3, drive circuit 50-1, and connector CN, and drive circuits 50-1 to 50-7 are arranged so that at least a portion of them overlap when viewed from the direction along the Y-axis that is perpendicular to the X-axis.

[0113] By arranging the drive circuits 50-1 to 50-7, the integrated circuit Q3, and the connector CN as described above, the risk of the wiring pattern on the drive circuit board 300 becoming complicated is reduced. In other words, an optimal wiring pattern can be formed on the wiring board 310. This reduces the risk that the wiring board 310 will become large due to the wiring pattern being laid out, making it possible to reduce the size of the drive circuit board 300, and also reduces the risk of noise being superimposed when generating the drive signals COM1 to COM7 based on the basic drive signals dA1 to dA7, improving the waveform accuracy of the signal waveforms of the drive signals COM1 to COM7.

[0114] Next, an example of the arrangement of various components in the drive circuits 50-1 to 50-7 mounted in the drive circuit mounting areas 51-1 to 51-7 will be described. Here, the mounting arrangement of components in the drive circuits 50-1 to 50-7 in the drive circuit mounting areas 51-1 to 51-7 is the same. Therefore, in the following explanation, the component arrangement of the drive circuit 50 will be described. In this case, the explanation will be made assuming that the drive circuit 50 is mounted in the drive circuit mounting area 51 of the drive circuit mounting areas 51-1 to 51-7.

[0115] Fig. 8 is a diagram showing an example of the arrangement of components of the drive circuit 50 mounted in the drive circuit mounting area 51. Fig. 8 also shows the X-axis, Y-axis, and Z-axis which indicate the same directions as those in Fig. 7 described above. Note that the configuration shown in Fig. 8 is only a part of the drive circuit 50, and various components other than those shown in Fig. 8 may be mounted on the drive circuit board 300.

[0116] As shown in FIG. 8, the integrated circuit Q1 is mounted on the −X side of the drive circuit mounting area 51, in an area of ​​the drive circuit mounting area 51 in the vicinity of the integrated circuit Q3.

[0117] A plurality of electronic components including one or more resistor elements and one or more capacitor elements that constitute a feedback circuit 570 are mounted on the -Y side of the integrated circuit Q1.

[0118] Transistors M1 and M2 are mounted on the +X side of the integrated circuit Q1. Specifically, the transistor M1 is mounted on the +X side of the integrated circuit Q1, and the transistor M2 is mounted on the +X side of the integrated circuit Q1, on the -Y side of the transistor M1. That is, a transistor pair Mp1 including the transistor M1 and the transistor M2 is mounted on the +X side of the integrated circuit Q1. At this time, the transistors M1 and M2 are mounted so as to overlap at least partially when viewed along the Y axis. This can reduce the difference between the shortest distance between the integrated circuit Q1 and the transistor M1 and the shortest distance between the integrated circuit Q1 and the transistor M2. Therefore, it is possible to reduce the difference between the propagation distance of the gate signal HGD1 input to the transistor M1 and the propagation distance of the gate signal LGD1 input to the transistor M2. In other words, it is possible to make the propagation distance of the gate signal HGD1 input to the transistor M1 and the propagation distance of the gate signal LGD1 input to the transistor M2 approximately equal. As a result, the possibility of variation in operation timing between the transistors M1 and M2 is reduced, and the driving accuracy of the transistors M1 and M2 in response to the modulation signal MS is improved, thereby improving the accuracy of the first amplified modulation signal AMS1 output by the amplifier circuit 550.

[0119] Further, a capacitor C1 and a diode D1 that constitute a bootstrap circuit of the amplifier circuit 550 are mounted between the integrated circuit Q1 and the transistor pair Mp1 along the Y-axis.

[0120] Further, a capacitor Cvh (not shown in FIG. 5) is mounted between the integrated circuit Q1 and the transistor pair Mp1 along the Y-axis. One end of the capacitor Cvh is electrically connected to the wiring pattern through which the voltage signal VHV1 propagates, and the other end is electrically connected to the ground potential. This capacitor Cvh functions as a stabilizing capacitor for reducing the possibility of fluctuations in the voltage value of the voltage signal VHV1 supplied to the amplifier circuit 550 and the bootstrap circuit BS. That is, the drive circuit 50 has a capacitor Cvh for stabilizing the voltage signal VHV1 supplied to the transistor pair Mp1 and the transistor pair Mp2. Therefore, it is preferable that the capacitor Cvh has a large capacity. Therefore, although only one capacitor Cvh is illustrated in FIG. 8, the capacitor Cvh may be configured to include a plurality of chip capacitors connected in parallel, or may be configured to include an electrolytic capacitor.

[0121] Transistors M3 and M4 are mounted on the +X side of the transistor pair Mp1.

[0122] That is, a transistor pair Mp2 including a transistor M3 and a transistor M4 is mounted on the +X side of the transistor pair Mp1. Specifically, the transistor M3 is mounted on the +X side of the transistor pair Mp1, and the transistor M4 is mounted on the +X side of the transistor pair Mp1, on the -Y side of the transistor M3. At this time, the transistors M3 and M4 are mounted so that they at least partially overlap when viewed along the Y axis.

[0123] Then, as viewed along the Y axis, capacitors C13a and C13b as the capacitor C13 and diodes D13, D21, D22, and D23 are mounted between the transistor pair Mp1 and the transistor pair Mp2. The capacitor C13a is mounted between the transistor pair Mp1 and the transistor pair Mp2. The capacitor C13b is mounted on the +Y side of the capacitor C13a between the transistor pair Mp1 and the transistor pair Mp2. That is, the capacitor C13 including the capacitors C13a and C13b is provided between the transistor pair Mp1 and the transistor pair Mp2, and between the transistors M1, M2 and the transistors M3, M4, as viewed along the Y axis. At this time, the capacitor C13a and the capacitor C13b are electrically connected in parallel. That is, the bootstrap circuit BS includes the capacitor C13b electrically connected in parallel with the capacitor C13a. The number of capacitors connected in parallel in the bootstrap circuit BS is not limited to two, the capacitor C13a and the capacitor C13b, and may be three or more.

[0124] Moreover, the diodes D13, D21, D22, and D23 are mounted on the +Y side of the capacitor C13b, lined up in the order of diode D21, diode D22, diode D23, and diode D13 along the X-axis from the -X side to the +X side. In other words, a bootstrap circuit BS is formed between the transistor pair Mp1 and the transistor pair Mp2.

[0125] An inductor 561 and a capacitor 562 are located on the +X side of the transistor pair Mp2. The inductor 561 is mounted on the +X side of the transistor pair Mp2, and the capacitor 562 is mounted on the +X side of the transistor pair Mp2, on the -Y side of the inductor 561. At this time, the capacitor 562 is located so that at least a portion of it overlaps with the inductor 561 when viewed along the Y axis. That is, a demodulation circuit 560 is mounted on the +X side of the transistor pair Mp2.

[0126] An integrated circuit Q2 is mounted on the +X side of an inductor 561 and a capacitor 562 that configure the demodulation circuit 560. Capacitors C11 and C12 and diodes D11 and D12 that constitute a bootstrap circuit of the level shift circuit 750 are located between the inductor 561 and the capacitor 562 and the integrated circuit Q2.

[0127] As described above, in the drive circuit board 300, the integrated circuit Q1 including the gate drive circuit 530, the transistor pair Mp1 including transistors M1 and M2, and the demodulation circuit 560 which the drive circuit 50 has are arranged along the X-axis from the -X side to the +X side in the order of the integrated circuit Q1, the transistor pair Mp1, and the demodulation circuit 560, the integrated circuit Q2 including the gate drive circuit 730, the transistor pair Mp2 including transistors M3 and M4, and the demodulation circuit 560 are arranged along the X-axis from the -X side to the +X side in the order of the transistor pair Mp2, the demodulation circuit 560, and the integrated circuit Q2, and the transistor pair Mp1, the transistor pair Mp2, and the demodulation circuit 560 are arranged along the X-axis from the -X side to the +X side in the order of the transistor pair Mp1, the transistor pair Mp2, and the demodulation circuit 560.

[0128] In the drive circuit board 300 configured as described above, the integrated circuit Q1 including the gate drive circuit 530, the transistor pair Mp1, and the demodulation circuit 560 are arranged from the -X side to the +X side along the X axis in the order of the integrated circuit Q1, the transistor pair Mp1, and the demodulation circuit 560. That is, the gate drive circuit 530, the transistor pair Mp1, and the demodulation circuit 560 are arranged along the generation process for generating the drive signal COM from the basic drive signal dA. This reduces the risk that the wiring pattern formed on the wiring board 310 will become complicated, and as a result, the wiring board 310 can be made smaller, and the risk of noise being superimposed on the signal propagated by the wiring board 310 is also reduced.

[0129] Furthermore, the integrated circuit Q2 including the gate drive circuit 730, the transistor pair Mp2, and the demodulation circuit 560 are arranged along the X-axis from the -X side to the +X side in the order of the transistor pair Mp2, the demodulation circuit 560, and the integrated circuit Q2, thereby making it possible to shorten the length of the wiring through which the first amplified modulated signal AMS1 and the second amplified modulated signal AMS2, which are high-frequency signals, propagate. As a result, the waveform accuracy of the second amplified modulated signal AMS2 input to the demodulation circuit 560 is improved, and the waveform accuracy of the drive signal COM corresponding to the second amplified modulated signal AMS2 is improved.

[0130] And, by arranging the transistor pair Mp1, the transistor pair Mp2, and the demodulation circuit 560 along the X-axis from the -X side to the +X side in the order of the transistor pair Mp1, the transistor pair Mp2, and the demodulation circuit 560, the transistor pair Mp1, the transistor pair Mp2, and the demodulation circuit 560 are also arranged along the generation process of generating the drive signal COM from the basic drive signal dA. Therefore, the risk of the wiring pattern formed on the wiring board 310 becoming complicated is reduced, and as a result, the wiring board 310 can be made smaller, and the risk of noise being superimposed on the signal propagated by the wiring board 310 is also reduced.

[0131] In addition, in the drive circuit board 300 of this embodiment, the transistors M1, M2, M3, and M4 and the integrated circuits Q1 and Q2 are provided on the wiring board 310 so that the shortest distance between the transistor pair Mp1 including the transistors M1 and M2 and the integrated circuit Q1 including the gate drive circuit 530 is shorter than the shortest distance between the transistor pair Mp2 including the transistors M3 and M4 and the integrated circuit Q2 including the gate drive circuit 730. This makes it possible to shorten the wiring length of the gate signals HGD1 and LGD1 output by the gate drive circuit 530 included in the integrated circuit Q1. As a result, the waveform accuracy of the gate signals HGD1 and LGD1 input to the transistors M1 and M2 is improved, and the drive accuracy of the transistors M1 and M2 is improved. Therefore, the waveform accuracy of the first amplified modulation signal AMS1 generated by driving the transistors M1 and M2 is improved.

[0132] In addition, the capacitor 562 of the demodulation circuit 560 is slightly larger than the capacitor 562 when viewed from the direction along the Y axis. At least a part of the feedback circuit 570 is located between the integrated circuit Q1 and the inductor 561. This makes it possible to shorten the wiring length of the feedback path including the feedback circuit 570 that feeds back the drive signal COM to the integrated circuit Q1. As a result, the accuracy of the feedback control in the drive circuit 50 is improved, and the waveform accuracy of the drive signal COM output by the drive circuit 50 is improved.

[0133] Furthermore, an integrated circuit Q1 including a gate drive circuit 530, a transistor pair Mp1 including transistors M1 and M2, an integrated circuit Q2 including a gate drive circuit 730, a transistor pair Mp2 including transistors M3 and M4, and a capacitor Cvh for stabilizing the voltage value of the voltage signal VHV1 are provided in the following order along the X-axis in the direction from the -X side to the +X side: integrated circuit Q1, capacitor Cvh, transistor pair Mp1, transistor pair Mp2, integrated circuit Q2. In detail, the capacitor Cvh is provided so that the shortest distance between the capacitor Cvh and the transistor pair Mp1 including transistors M1 and M2 is shorter than the shortest distance between the capacitor Cvh and the transistor pair Mp2 including transistors M3 and M4.

[0134] As described above, the frequency of the gate signals HGD1 and LGD1 output by the integrated circuit Q1 is The frequency of the gate signals HGD2 and LGD2 output from the integrated circuit Q2 is higher, and therefore the driving frequency of the transistors M1 and M2 is higher than the driving frequency of the transistors M3 and M4. By locating the capacitor Cvh, which stabilizes the voltage value of the voltage signal VHV1, in the vicinity of the transistors M1 and M2, which are driven at such a high frequency, the risk of the voltage value of the voltage signal VHV1 input to the transistors M1 and M2 fluctuating is further reduced, and the feedback path through which the high-frequency current generated by driving the transistors M1 and M2 returns to the capacitor Cvh can be shortened. This improves the accuracy of the signal waveform of the first amplified modulation signal AMS1 generated by driving the transistors M1 and M2, and improves the stability of the operation of the drive circuit 50.

[0135] In this case, by positioning the capacitor Cvh so that the distance between the capacitor Cvh and the transistors M3 and M4 is shorter than the shortest distance between the capacitor Cvh and the demodulation circuit 560, the accuracy of the voltage signal VHV2 corresponding to the voltage signal VHV1 supplied to the transistor pair Mp2 including the transistors M3 and M4 is also improved. As a result, the accuracy of the signal waveform of the second amplified modulation signal AMS2 is also improved.

[0136] Furthermore, the capacitors C13a and C13b included in the bootstrap circuit BS, which supplies a voltage signal VHV2 corresponding to the voltage signal VHV1 to the transistor pair Mp2 including the transistors M3 and M4, are arranged so that the shortest distance between the capacitors C13a and C13b and the transistor pair Mp1 is longer than the shortest distance between the capacitors C13a and C13b and the transistor pair Mp2, and is shorter than the shortest distance between the capacitors C13a and C13b and the integrated circuit Q2 including the gate drive circuit 730. In other words, the capacitors C13a and C13b included in the bootstrap circuit BS are arranged closer to the transistor pair Mp2 than to the transistor pair Mp1. In this case, the capacitors C13a, C13b are preferably arranged so that the shortest distance between the capacitors C13a, C13b and the drain terminal of the transistor M3 is shorter than the shortest distance between the capacitors C13a, C13b and the source terminal of the transistor M3.

[0137] This improves the stability of the voltage signal VHV2 of the transistor pair Mp2 that corresponds to the voltage signal VHV1 supplied to the transistor M3, thereby improving the accuracy of the signal waveform of the second amplified modulated signal AMS2 generated by the transistor pair Mp2, and improving the accuracy of the signal waveform of the drive signal COM that corresponds to the second amplified modulated signal AMS2.

[0138] Next, an example of a wiring pattern formed in the drive circuit mounting area 51 of the wiring board 310 on which the drive circuit 50 configured as above is mounted will be described. Fig. 9 is a diagram showing an example of a wiring pattern formed in the drive circuit mounting area 51. Note that in Fig. 9, a part of the drive circuit 50 mounted in the drive circuit mounting area 51 is shown by a dashed line.

[0139] As shown in FIG. 9, the integrated circuit Q1 and the transistor M1 are electrically connected by a wiring Wgh1. That is, a gate signal HGD1 output by a gate driver 531 of the integrated circuit Q1 is propagated through the wiring Wgh1 and input to the transistor M1. Also, the integrated circuit Q1 and the transistor M2 are electrically connected by a wiring Wgl1. That is, a gate signal LGD1 output by a gate driver 532 of the integrated circuit Q1 is propagated through the wiring Wgl1 and input to the transistor M2. This drives the transistors M1 and M2.

[0140] One end of the capacitor Cvh, the drain terminal of the transistor M1, and the anode terminal of the diode D21 are electrically connected to the wiring Wvh. A voltage signal VHV1 supplied via a wiring pattern (not shown) propagates through this wiring Wvh.

[0141] The wiring Ws1 is electrically connected to the source terminal of the transistor M1, the drain terminal of the transistor M2, the source terminal of the transistor M4, one end of the capacitors C13a and C13b, and the integrated circuit Q1. The first amplified modulation signal AMS1 is generated on the wiring Ws1 by driving the transistors M1 and M2. In other words, the wiring Ws1 corresponds to the first output point OP1.

[0142] The wiring Wbs is electrically connected to the other ends of the capacitors C13a and C13b, the drain terminal of the transistor M3, and the cathode terminal of the diode D13. The anode terminal of the diode D13 is electrically connected to the cathode terminal of the diode D23, the anode terminal of the diode D23 is electrically connected to the cathode terminal of the diode D22, and the anode terminal of the diode D22 is electrically connected to the cathode terminal of the diode D21. That is, the wiring Wbs is electrically connected to the wiring Wvh via the diodes D13, D21, D22, and D23.

[0143] On this wiring Wbs1, a voltage signal VHV2 is generated, which is obtained by shifting the reference potential of the first amplified modulation signal AMS1 generated on the wiring Ws1 by a voltage value obtained by subtracting the sum of the forward drop voltage Vf1 of diode D13, the forward drop voltage Vf2 of diode D21, the forward drop voltage Vf3 of diode D22, and the forward drop voltage Vf4 of diode D23 from the voltage vhv1, which is the voltage value of the voltage signal VHV1, in accordance with the charge stored in capacitors C13a and C13b.

[0144] The integrated circuit Q2 and the transistor M3 are electrically connected via a wiring Wgh2 and a via wiring (not shown). That is, a gate signal HGD2 output by the gate driver 731 of the integrated circuit Q2 is propagated through the wiring Wgh2 and input to the transistor M3. The integrated circuit Q2 and the transistor M4 are electrically connected via a wiring Wgl2 and a via wiring (not shown). That is, a gate signal LGD2 output by the gate driver 732 of the integrated circuit Q2 is propagated through the wiring Wgl2 and input to the transistor M4. This drives the transistors M3 and M4.

[0145] The wiring Ws2 is electrically connected to the source terminal of the transistor M3, the drain terminal of the transistor M4, and the inductor 561. In addition, during a period in which the drain terminal and the source terminal of the transistor M3 are controlled to be conductive, a voltage signal VHV2 propagating through the wiring Wbs is supplied to the wiring Ws2 via the transistor M3. In addition, during a period in which the drain terminal and the source terminal of the transistor M4 are controlled to be conductive, The first amplified modulated signal AMS1 propagating through the wiring Ws1 is input to s2 via the transistor M4. That is, the wiring Ws2 corresponds to the second output point OP2, and the second amplified modulated signal AMS2 is generated on this wiring Ws2.

[0146] An inductor 561 and a capacitor 562 are electrically connected to the wiring Wcm. In addition, a second amplified modulated signal AMS2 is input to the wiring Wcm via the inductor 561. As a result, a drive signal COM is generated in the wiring Wcm, in which the second amplified modulated signal AMS2 input via the inductor 561 is smoothed by the inductor 561 and the capacitor 562.

[0147] The drive circuit 50 outputs the generated drive signal COM to the wire Wcm. That is, the wire Wcm is electrically connected to the corresponding terminal TM of the connector CN.

[0148] Here, a description will be given of an example of a mounting form in which the transistors M1, M2, M3, and M4 are mounted on the wiring board 310. Fig. 10 is a diagram showing an example of a mounting form in which the transistors M1, M2, M3, and M4 are mounted on the wiring board 310, and is an enlarged view of part (A) in Fig. 9.

[0149] 10, the transistor M1 includes one gate terminal g1, three source terminals s1, and four drain terminals d1. The transistor M1 is mounted on the wiring board 310 such that the gate terminal g1 is located on the -Y side of the molded part of the transistor M1, the three source terminals s1 are located side by side along the X-axis on the -Y side of the molded part of the transistor M1 and on the +X side of the gate terminal g1 of the transistor M1, and the four drain terminals d1 are located side by side along the X-axis on the +Y side of the molded part of the transistor M1.

[0150] The transistor M2 also includes one gate terminal g2, three source terminals s2, and four drain terminals d2. The transistor M2 is mounted on the wiring board 310 such that the gate terminal g2 is located on the -X side of the molded part of the transistor M1, the three source terminals s1 are located side by side along the Y axis on the -X side of the molded part of the transistor M1 and on the -Y side of the gate terminal g1 of the transistor M1, and the four drain terminals d1 are located side by side along the Y axis on the +X side of the molded part of the transistor M1.

[0151] That is, the transistor M2 is arranged so that the shortest distance between the source terminal s2 of the transistor M2 and the side 311 is shorter than the shortest distance between the drain terminal d2 of the transistor M2 and the side 311, and the transistor M1 is arranged so that the shortest distance between the source terminal s1 of the transistor M1 and the transistor M2 is shorter than the shortest distance between the drain terminal d1 of the transistor M2 and the transistor M2. The transistors M1 and M2 are arranged so that at least a portion of them overlap when viewed from the direction along the Y axis perpendicular to the direction along the X axis. In other words, the mounting direction of the transistor M1 and the mounting direction of the transistor M2 differ by 90 degrees.

[0152] In the transistor M1 and transistor M2 implemented as described above, the gate terminal g1 of the transistor M1 electrically connected to the integrated circuit Q1 and the gate terminal g2 of the transistor M2 electrically connected to the integrated circuit Q1 are both located on the -X side where the integrated circuit Q1 is provided. In this case, the gate terminal g1 of the transistor M1 electrically connected to the integrated circuit Q1 is located near the gate terminal g2 of the transistor M2 electrically connected to the integrated circuit Q1. In other words, the transistor M1 is arranged such that the shortest distance between the gate terminal g1 of the transistor M1 and the integrated circuit Q1 including the gate drive circuit 530 is the shortest distance between the drain terminal d1 of the transistor M1 and the integrated circuit Q1 including the gate drive circuit 530. The transistor M2 is arranged so that the shortest distance between the gate terminal g2 of the transistor M2 and the integrated circuit Q1 including the gate drive circuit 530 is shorter than the shortest distance between the drain terminal d2 of the transistor M2 and the integrated circuit Q1 including the gate drive circuit 530.

[0153] This makes it possible to reduce the difference between the length of the wiring Wgh1 electrically connecting the gate terminal g1 of the transistor M1 to the integrated circuit Q1 and the length of the wiring Wgl1 electrically connecting the gate terminal g1 of the transistor M2 to the integrated circuit Q1. This reduces the risk of signal delay occurring between the gate signal HGD1 input to the gate terminal g1 of the transistor M1 and the gate signal HGD1 input to the gate terminal g2 of the transistor M2. As a result, the accuracy of the signal waveform of the first amplified modulation signal AMS1 generated by driving the transistors M1 and M2 is improved.

[0154] Furthermore, in the transistors M1 and M2 implemented as described above, The source terminal s1 of the transistor M1 electrically connected to the first output point OP1 is located near the drain terminal d2 of the transistor M2 electrically connected to the first output point OP1. This reduces the risk of the wiring Ws1 corresponding to the first output point OP1 being routed in a complicated manner. As a result, the risk of noise being superimposed on the first amplified modulated signal AMS1 generated on the wiring Ws1 corresponding to the first output point OP1 is reduced, and the accuracy of the signal waveform of the first amplified modulated signal AMS1 output from the first output point OP1 is improved.

[0155] The transistor M3 also includes one gate terminal g3, three source terminals s3, and four drain terminals d3. The transistor M3 is mounted on the wiring board 310 such that the gate terminal g3 is located on the +X side of the molded part of the transistor M3, the three source terminals s3 are located side by side along the Y axis on the +X side of the molded part of the transistor M3 and on the +Y side of the gate terminal g3 of the transistor M3, and the four drain terminals d3 are located side by side along the Y axis on the -X side of the molded part of the transistor M3.

[0156] The transistor M4 also includes one gate terminal g4, ​​three source terminals s4, and four drain terminals d4. The transistor M4 is mounted on the wiring board 310 such that the gate terminal g4 is located on the -X side of the molded part of the transistor M4, the three source terminals s4 are located side by side along the Y axis on the -X side of the molded part of the transistor M4 and on the -Y side of the gate terminal g4 of the transistor M4, and the four drain terminals d4 are located side by side along the Y axis on the +X side of the molded part of the transistor M4.

[0157] That is, the transistor M3 is arranged so that the shortest distance between the source terminal s3 of the transistor M3 and the demodulation circuit 560 is shorter than the shortest distance between the drain terminal d3 of the transistor M3 and the demodulation circuit 560, and the transistor M4 is arranged so that the shortest distance between the drain terminal d4 of the transistor M4 and the demodulation circuit 560 is shorter than the shortest distance between the source terminal s4 of the transistor M4 and the demodulation circuit 560. The transistor M3 is arranged so that the shortest distance between the drain terminal d3 of the transistor M3 and the transistor pair Mp1 is shorter than the shortest distance between the source terminal s3 of the transistor M3 and the transistor pair Mp1, and the transistor M4 is arranged so that the shortest distance between the source terminal s4 of the transistor M4 and the transistor pair Mp1 is shorter than the shortest distance between the drain terminal d4 of the transistor M4 and the transistor pair Mp1. In other words, the mounting direction of the transistor M3 and the mounting direction of the transistor M4 are 180 degrees different.

[0158] The transistors M3 and M4 implemented as above perform level shifting. When the operation mode of the level shift circuit 750 is a first mode MD1 in which the first amplified modulated signal AMS1 is output as the second amplified modulated signal AMS2, the first amplified modulated signal AMS1 generated on the wiring Ws1 is propagated to the wiring Ws2 as the second amplified modulated signal AMS2 via the transistor M3. Then, the second amplified modulated signal AMS2 propagated to the wiring Ws2 is smoothed by the inductor 561 and the capacitor 562. On the other hand, when the operation mode of the level shift circuit 750 is a second mode MD2 in which a signal obtained by shifting the reference potential of the first amplified modulated signal AMS1 is output as the second amplified modulated signal AMS2, a signal obtained by shifting the reference potential of the first amplified modulated signal AMS1 generated on the wiring Ws1 based on the charges stored in the capacitors C13a and C13b is propagated to the wiring Ws2 as the second amplified modulated signal AMS2 via the transistor M4. Then, the second amplified modulation signal AMS2 propagated to the wiring Ws2 is smoothed by the inductor 561 and the capacitor 562.

[0159] That is, in the drive circuit board 300 of this embodiment, when the second amplified modulated signal AMS2 based on the first amplified modulated signal AMS1 is generated, the signal is propagated from the -X side to the +X side via the same propagation path without crossing when the operation mode of the level shift circuit 750 is the first mode MD1 and when the operation mode of the level shift circuit 750 is the second mode MD2. This reduces the risk of noise being superimposed on the second amplified modulated signal AMS2 based on the first amplified modulated signal AMS1, and improves the signal accuracy of the second amplified modulated signal AMS2.

[0160] Here, the piezoelectric element 60 is an example of a capacitive load, and the drive signal COM is an example of a drive signal. The gate drive circuit 530 and the integrated circuit Q1 equipped with the gate drive circuit 530 are an example of a first driver circuit, the gate signals HGD1 and LGD1 output by the gate drive circuit 530 are an example of a first drive signal, the transistor pair Mp1 is an example of a first switching element pair, the transistor M1 included in the transistor pair Mp1 is an example of a second high-potential side FET, the transistor M2 included in the transistor pair Mp1 is an example of a second low-potential side FET, the first amplified modulation signal AMS1 generated by driving the transistor pair Mp1 is an example of a first switching signal, and the configuration including the modulation circuit 500 and the amplifier circuit 550 is an example of a first switching circuit. Moreover, the gate drive circuit 730 and the integrated circuit Q2 equipped with the gate drive circuit 730 are an example of a second driver circuit, the gate signals HGD2, LGD2 output by the gate drive circuit 730 are an example of a second drive signal, the transistor pair Mp2 is an example of a second switching element pair, the transistor M3 included in the transistor pair Mp2 is an example of a first high-potential side FET, the transistor M4 included in the transistor pair Mp2 is an example of a first low-potential side FET, the second amplified modulation signal AMS2 generated by driving the transistor pair Mp2 is an example of a second switching signal, and the level shift circuit 750 is an example of a second switching circuit. The demodulation circuit 560 is an example of a smoothing circuit. Furthermore, the base drive signal aA, which is an analog signal output by the DA conversion circuit 510, is an example of an analog base drive signal, at least one of the pulse modulation circuit 520 and the modulation circuit 500 including the pulse modulation circuit 520 is an example of a modulation circuit, the side 311 of the wiring board 310 is an example of a first side, and the side 312 of the wiring board 310 is an example of a second side. The direction from the -X side to the +X side along the X-axis is an example of a first direction, and the direction from the -Y side to the +Y side along the Y-axis is an example of a second direction.

[0161] 5. Effects In the drive circuit board 300 of the liquid ejection device 1 of this embodiment configured as described above, the drive circuit 50 that outputs the drive signal COM in response to the basic drive signal dA includes a gate drive circuit 530 that outputs gate signals HGD1, LGD1 in response to the basic drive signal dA, an amplifier circuit 550 including a transistor pair Mp1 including transistors M1, M2 that are driven in response to the gate signals HGD1, LGD1 and output a first amplified modulation signal AMS1, a gate drive circuit 730 that outputs gate signals HGD2, LGD2 in response to the basic drive signal dA, and a gate The level shift circuit 750 includes a transistor pair Mp2 including transistors M3 and M4 that are driven in response to the first amplified modulation signal AMS1 and output the second amplified modulation signal AMS2 in response to the first amplified modulation signal AMS1, and a demodulation circuit 560 that smoothes the second amplified modulation signal AMS2 and outputs it as the drive signal COM. This makes it possible to make the voltage value used when amplifying the basic drive signal dA to generate a drive signal smaller than the voltage value of the drive signal COM that outputs the voltage value of the voltage signal VHV1. This reduces the losses that occur in each of the transistors M1, M2, M3, and M4. As a result, the power consumption in the drive circuit 50 is reduced, and the power consumption of the liquid ejection device 1 and the drive circuit board 300 of the liquid ejection device 1 can be reduced.

[0162] In addition, in the drive circuit board 300 of the liquid ejection device 1 of this embodiment, even if the drive circuits 50-1 to 50-7 are mounted on the wiring board 310 as the multiple drive circuits 50, the drive circuit 50-1, the integrated circuit Q3, and the connector CN are arranged in the order of the integrated circuit Q3, the drive circuit 50-1, and the connector CN along the direction from the -X side to the +X side along the X axis, and the drive circuits 50-1 to 50-7 are arranged so as to overlap at least partially when viewed from the direction along the Y axis perpendicular to the X axis, thereby reducing the risk of the wiring pattern becoming complicated when the drive circuit board 300 generates the drive signals COM1 to COM7 corresponding to the basic drive signals dA1 to dA7. As a result, the size of the wiring board 310 of the drive circuit board 300 can be reduced, and the risk of noise being superimposed on various signals propagated by the drive circuit board 300 is reduced, improving the accuracy of the signal waveforms of the drive signals COM1 to COM7 output from the drive circuit board 300.

[0163] In this case, the integrated circuit Q1 including the gate drive circuit 530, the transistors M1, M2, and the demodulation circuit 560 of each of the drive circuits 50-1 to 50-7 are arranged in the order of the integrated circuit Q1, the transistors M1, M2, and the demodulation circuit 560 along the X-axis in the direction from the -X side to the +X side. Furthermore, the integrated circuit Q1 including the gate drive circuit 530 of each of the drive circuits 50-1 to 50-7 is arranged so as to overlap at least a portion of when viewed from the direction along the Y-axis, and the transistors M1, M2 of each of the drive circuits 50-1 to 50-7 are arranged so as to overlap at least a portion of when viewed from the direction along the Y-axis. This reduces the risk of the wiring pattern becoming complicated when each of the drive circuits 50-1 to 50-7 generates the drive signals COM1 to COM7 corresponding to the basic drive signals dA1 to dA7. As a result, the wiring board 310 of the drive circuit board 300 can be further miniaturized, the risk of noise being superimposed on various signals transmitted by the drive circuit board 300 is further reduced, and the accuracy of the signal waveforms of the drive signals COM1 to COM7 output from the drive circuit board 300 is further improved.

[0164] Furthermore, the integrated circuit Q2 including the gate drive circuit 730, the transistors M3 and M4, and the demodulation circuit 560 of each of the drive circuits 50-1 to 50-7 are arranged in the order of the transistors M3 and M4, the demodulation circuit 560, and the integrated circuit Q2 along the X-axis in the direction from the -X side to the +X side, and the integrated circuit Q2 including the gate drive circuit 730 of each of the drive circuits 50-1 to 50-7 is arranged so as to overlap at least a portion of when viewed from the direction along the Y-axis, and the transistors M3 and M4 of each of the drive circuits 50-1 to 50-7 are arranged so as to overlap at least a portion of when viewed from the direction along the Y-axis. This further reduces the risk of the wiring pattern becoming complicated when each of the drive circuits 50-1 to 50-7 generates the drive signals COM1 to COM7 corresponding to the basic drive signals dA1 to dA7. As a result, the wiring board 310 of the drive circuit board 300 can be further miniaturized, the risk of noise being superimposed on various signals transmitted by the drive circuit board 300 is further reduced, and the accuracy of the signal waveforms of the drive signals COM1 to COM7 output from the drive circuit board 300 is further improved.

[0165] In addition, the driving circuit board 300 of the liquid ejection device 1 of this embodiment has a capacitor Cvh that stabilizes the voltage value of the voltage signal VHV1 supplied to the transistor pair Mp1 and the transistor pair Mp2, and when the frequency of the gate signals HGD1, LGD1 input to the transistor pair Mp1 is higher than the frequency of the gate signals HGD2, LGD2 input to the transistor pair Mp2, the capacitor Cvh is arranged so that the shortest distance between the capacitor Cvh and the transistor pair Mp1 is shorter than the shortest distance between the capacitor Cvh and the transistor pair Mp2, thereby reducing the possibility that the voltage value of the voltage signal VHV1 will fluctuate due to the influence of the transistor pair Mp1 driven at a high driving frequency due to the high frequency of the gate signals HGD1, LGD1. In this case, the feedback path through which the high frequency current generated by the transistor pair Mp1 driven at a high driving frequency returns to the capacitor Cvh can also be shortened. As a result, the accuracy of the signal waveform of the first amplified modulation signal AMS1 generated by driving the transistors M1 and M2 is improved, and the stability of the operation of the drive circuit 50 is improved.

[0166] In addition, in the driving circuit board 300 of the liquid ejection device 1 of this embodiment, the driving circuit 50 has a bootstrap circuit BS that includes a capacitor C13 and a diode D13, and level-shifts the voltage value of the voltage signal VHV1 supplied to the transistor pair Mp1 in accordance with the first amplified modulation signal AMS1 and supplies the voltage signal VHV2 to the transistor pair Mp2. The capacitors C13a and C13b as the capacitor C13 of the bootstrap circuit BS are arranged so that the shortest distance between the capacitors C13a and C13b and the transistor pair Mp1 is longer than the shortest distance between the capacitors C13a and C13b and the transistor pair Mp2. In other words, the capacitors C13a and C13b as the capacitor C13 of the bootstrap circuit BS are arranged closer to the transistor pair Mp2 than to the transistor pair Mp1. This reduces the possibility that noise will be superimposed on the voltage signal VHV2 supplied to the transistor pair Mp2, thereby improving the accuracy of the voltage signal VHV2 supplied to the transistor pair Mp2. Therefore, the accuracy of the second amplified modulated signal AMS2 output from the transistor pair Mp2 in response to the voltage signal VHV2 is also improved, and as a result, the accuracy of the drive signal COM generated based on the second amplified modulated signal AMS2 is also improved.

[0167] In addition, in the driving circuit board 300 of the liquid ejection device 1 of this embodiment, the transistor M3 of the driving circuit 50 is provided so that the shortest distance between the source terminal s3 of the transistor M3 and the demodulation circuit 560 is shorter than the shortest distance between the drain terminal d3 of the transistor M3 and the demodulation circuit 560, and the transistor M4 is provided so that the shortest distance between the drain terminal d4 of the transistor M4 and the demodulation circuit 560 is shorter than the shortest distance between the source terminal s4 of the transistor M4 and the demodulation circuit 560. That is, the transistors M3 and M4 are mounted in a 180-degree inverted state. This makes it possible to provide in parallel a propagation path when a signal corresponding to the first amplified modulation signal AMS1 is output via the transistor M3 and a propagation path when a signal corresponding to the first amplified modulation signal AMS1 is output via the transistor M4 when the transistor pair Mp2 generates the second amplified modulation signal AMS2 corresponding to the first amplified modulation signal AMS1. As a result, the propagation path when a signal corresponding to the first amplified modulated signal AMS1 is output via transistor M3 and the propagation path when a signal corresponding to the first amplified modulated signal AMS1 is output via transistor M4 do not cross, and the risk of a difference in path length occurring is reduced. As a result, the risk of noise being superimposed on the second amplified modulated signal AMS2 based on the first amplified modulated signal AMS1 is reduced, and the signal accuracy of the second amplified modulated signal AMS2 is improved.

[0168] In the drive circuit board 300 of the liquid ejection device 1 of this embodiment, the distance between the integrated circuit Q1 including the gate drive circuit 530 that outputs the gate signals HGD1 and LGD1 and the transistors M1 and M2 that are driven by the gate signals HGD1 and LGD1 is set to 1 / 2. The integrated circuits Q1 and Q2 and the transistors M1, M2, M3, and M4 are provided so that the distance between the integrated circuit Q2 including the gate drive circuit 730 that outputs HGD2 and LGD2 is shorter than the distance between the integrated circuit Q2 and the transistors M3 and M4 driven by the gate signals HGD2 and LGD2. Therefore, even if the frequency of the gate signals HGD1 and LGD1 input to the transistor pair Mp1 is higher than the frequency of the gate signals HGD2 and LGD2 input to the transistor pair Mp2, the risk of noise being superimposed on the gate signals HGD1 and LGD1 is reduced, allowing the transistors M1 and M2 to be driven stably, and the risk of noise caused by conversion of the logic levels of the gate signals HGD1 and LGD1 being superimposed on the gate signals HGD2 and LGD2 is reduced, and the driving of the transistors M3 and M4 is also stabilized. As a result, the waveform accuracy of the first amplified modulated signal AMS1 generated by driving the transistors M1 and M2 is improved, and the waveform accuracy of the second amplified modulated signal AMS2 generated by driving the transistors M1 and M2 in response to the first amplified modulated signal AMS1 is also improved, and as a result, the waveform accuracy of the drive signal COM in response to the second amplified modulated signal AMS2 is also improved.

[0169] Although the embodiments and modifications have been described above, the present invention is not limited to these embodiments, and can be embodied in various forms without departing from the spirit of the present invention. For example, the above embodiments can be appropriately combined.

[0170] The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations with the same functions, methods and results, or configurations with the same purpose and effect). The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments or that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0171] The following can be derived from the above-described embodiment.

[0172] One aspect of the drive circuit board is A drive circuit board that outputs a drive signal for driving a capacitive load, A drive circuit that outputs the drive signal corresponding to a basic drive signal; a wiring board on which the drive circuit is provided; Equipped with The drive circuit includes: a first driver circuit that outputs a first drive signal corresponding to the basic drive signal, and a first switching circuit including a first switching element pair that is driven in response to the first drive signal to output a first switching signal; a second driver circuit that outputs a second drive signal corresponding to the basic drive signal, and a second switching circuit including a second switching element pair that is driven in response to the second drive signal and outputs a second switching signal corresponding to the first switching signal; a smoothing circuit that smoothes the second switching signal and outputs the smoothed signal as the drive signal; having The wiring board includes a first side and a second side facing each other along a first direction, the second switching element pair includes a first high-side FET and a first low-side FET; the shortest distance between the source terminal of the first high potential side FET and the smoothing circuit is shorter than the shortest distance between the drain terminal of the first high potential side FET and the smoothing circuit; The shortest distance between the drain terminal of the first low potential side FET and the smoothing circuit is shorter than the shortest distance between the source terminal of the first low potential side FET and the smoothing circuit.

[0173] According to this drive circuit board, the signal propagation path when the first high-potential side FET is controlled to be conductive and the signal propagation path when the first low-potential side FET is controlled to be conductive are in the same direction. By forming the wiring pattern along the wiring line, the risk of the wiring pattern on the wiring board becoming complicated is reduced, the wiring board can be made smaller, and the risk of noise being superimposed on the signal is also reduced.

[0174] In one aspect of the drive circuit board, a shortest distance between a drain terminal of the first high potential side FET and the first switching element pair is shorter than a shortest distance between a source terminal of the first high potential side FET and the first switching element pair, The shortest distance between the source terminal of the first low potential side FET and the first switching element pair may be shorter than the shortest distance between the drain terminal of the first low potential side FET and the first switching element pair.

[0175] According to this drive circuit board, the signal propagation path when the signal input from the first switching element pair is output via the first high-side FET and the signal propagation path when the signal input from the first switching element pair is output via the first low-side FET are formed along the same direction, thereby reducing the risk of the wiring pattern on the wiring board becoming complicated, enabling the wiring board to be made smaller, and also reducing the risk of noise being superimposed on the signal.

[0176] In one aspect of the drive circuit board, The first switching element pair, the second switching element pair, and the smoothing circuit may be provided in the first direction in the following order: the first switching element pair, the second switching element pair, and the smoothing circuit.

[0177] In one aspect of the drive circuit board, The frequency of the first drive signal may be higher than the frequency of the second drive signal.

[0178] In one aspect of the drive circuit board, the first switching element pair includes a second high-side FET and a second low-side FET; a shortest distance between a source terminal of the second low potential side FET and the first side is shorter than a shortest distance between a drain terminal of the second low potential side FET and the first side; the shortest distance between the source terminal of the second high potential side FET and the second low potential side FET is shorter than the shortest distance between the drain terminal of the second high potential side FET and the second low potential side FET; The second low potential side FET and the second high potential side FET may be provided so as to at least partially overlap each other when viewed from a second direction perpendicular to the first direction.

[0179] In one aspect of the drive circuit board, The first switching circuit outputs the first switching signal obtained by amplifying a modulated signal based on the basic drive signal; The second switching circuit may output the second switching signal obtained by shifting a reference potential of the first switching signal based on the base drive signal.

[0180] In one aspect of the drive circuit board, The first switching circuit may include a DA conversion circuit that converts the reference drive signal into an analog reference drive signal, and a modulation circuit that outputs the modulated signal obtained by modulating the analog reference drive signal.

[0181] One aspect of the liquid ejection device is a drive circuit board that outputs a drive signal for driving a capacitive load; a print head that ejects liquid by driving the capacitive load; Equipped with The drive circuit board includes: A drive circuit that outputs the drive signal corresponding to a basic drive signal; a wiring board on which the drive circuit is provided; Equipped with The drive circuit includes: a first driver circuit that outputs a first drive signal corresponding to the basic drive signal, and a first switching circuit including a first switching element pair that is driven in response to the first drive signal to output a first switching signal; a second driver circuit that outputs a second drive signal corresponding to the basic drive signal, and a second switching circuit including a second switching element pair that is driven in response to the second drive signal and outputs a second switching signal corresponding to the first switching signal; a smoothing circuit that smoothes the second switching signal and outputs the smoothed signal as the drive signal; having The wiring board includes a first side and a second side facing each other along a first direction, the second switching element pair includes a first high-side FET and a first low-side FET; the shortest distance between the source terminal of the first high potential side FET and the smoothing circuit is shorter than the shortest distance between the drain terminal of the first high potential side FET and the smoothing circuit; The shortest distance between the drain terminal of the first low potential side FET and the smoothing circuit is shorter than the shortest distance between the source terminal of the first low potential side FET and the smoothing circuit.

[0182] According to this liquid ejection device, the signal propagation path when the first high potential side FET is controlled to be conductive and the signal propagation path when the first low potential side FET is controlled to be conductive are formed along the same direction, thereby reducing the risk of the wiring pattern on the wiring board becoming complicated, enabling the wiring board to be made smaller, and also reducing the risk of noise being superimposed on the signal.

[0183] In one aspect of the liquid ejection device, a shortest distance between a drain terminal of the first high potential side FET and the first switching element pair is shorter than a shortest distance between a source terminal of the first high potential side FET and the first switching element pair, The shortest distance between the source terminal of the first low potential side FET and the first switching element pair may be shorter than the shortest distance between the drain terminal of the first low potential side FET and the first switching element pair.

[0184] According to this liquid ejection device, the signal propagation path when the signal input from the first switching element pair is output via the first high-side FET and the signal propagation path when the signal input from the first switching element pair is output via the first low-side FET are formed along the same direction, thereby reducing the risk of the wiring pattern on the wiring board becoming complicated, enabling the wiring board to be made smaller, and also reducing the risk of noise being superimposed on the signal.

[0185] In one aspect of the liquid ejection device, The first switching element pair, the second switching element pair, and the smoothing circuit may be provided in the first direction in the following order: the first switching element pair, the second switching element pair, and the smoothing circuit.

[0186] In one aspect of the liquid ejection device, The frequency of the first drive signal may be higher than the frequency of the second drive signal. .

[0187] In one aspect of the liquid ejection device, the first switching element pair includes a second high-side FET and a second low-side FET; a shortest distance between a source terminal of the second low potential side FET and the first side is shorter than a shortest distance between a drain terminal of the second low potential side FET and the first side; the shortest distance between the source terminal of the second high potential side FET and the second low potential side FET is shorter than the shortest distance between the drain terminal of the second high potential side FET and the second low potential side FET; The second low potential side FET and the second high potential side FET may be provided so as to at least partially overlap each other when viewed from a second direction perpendicular to the first direction.

[0188] In one aspect of the liquid ejection device, The first switching circuit outputs the first switching signal obtained by amplifying a modulated signal based on the basic drive signal; The second switching circuit may output the second switching signal obtained by shifting a reference potential of the first switching signal based on the base drive signal.

[0189] In one aspect of the liquid ejection device, The first switching circuit may include a DA conversion circuit that converts the reference drive signal into an analog reference drive signal, and a modulation circuit that outputs the modulated signal obtained by modulating the analog reference drive signal. [Explanation of symbols]

[0190] 1...liquid ejection device, 5...ink container, 10...control mechanism, 20...ejection mechanism, 21...print head, 40...transport mechanism, 41...transport motor, 42...transport roller, 50...drive circuit, 51...drive circuit mounting area, 52...reference voltage circuit, 60...piezoelectric element, 100...control circuit, 200...drive signal selection circuit, 300...drive circuit board, 310...wiring board, 311, 312, 313, 314...side, 500 ...modulation circuit, 510...DA conversion circuit, 511...adder, 520...pulse modulation circuit, 521...inverter, 530...gate drive circuit, 531, 532...gate driver, 550...amplification circuit, 560...demodulation circuit, 561...inductor, 562...capacitor, 570...feedback circuit, 600...discharge section, 601...piezoelectric body, 611, 612...electrode, 621...diaphragm, 631...cavity, 632...nozzle plate, 641...reservoir, 651...nozzle, 661...supply port, 700...memory circuit, 710...level switching signal generation circuit, 721...inverter, 730...gate drive circuit, 731, 732...gate driver, 750...level shift circuit, BS...bootstrap circuit, C1, C11, C12, C13, C13a, C13b...capacitor, CN...connector , Cvh...capacitor, D1, D11, D12, D13, D21, D22, D23...diode, M1, M2, M3, M4...transistor, Mp1, Mp2...transistor pair, OP1...first output point, OP2...second output point, P...medium, Q1, Q2, Q3...integrated circuit, TM...terminal, Wbs, Wbs1, Wcm, Wgh1, Wgh2, Wgl1, Wgl2, Ws1, Ws2, Wvh...wiring

Claims

1. A drive circuit board that outputs a drive signal for driving a capacitive load, A drive circuit that outputs the drive signal corresponding to a basic drive signal; a wiring board on which the drive circuit is provided; Equipped with The drive circuit includes: a first driver circuit that outputs a first drive signal corresponding to the basic drive signal, and a first switching circuit including a first switching element pair that is driven in response to the first drive signal to output a first switching signal; a second driver circuit that outputs a second drive signal corresponding to the basic drive signal, and a second switching circuit including a second switching element pair that is driven in response to the second drive signal and outputs a second switching signal corresponding to the first switching signal; a smoothing circuit that smoothes the second switching signal and outputs the smoothed signal as the drive signal; having The wiring board includes a first side and a second side facing each other along a first direction, the second switching element pair includes a first high-side FET and a first low-side FET; the shortest distance between the source terminal of the first high potential side FET and the smoothing circuit is shorter than the shortest distance between the drain terminal of the first high potential side FET and the smoothing circuit; the shortest distance between the drain terminal of the first low potential side FET and the smoothing circuit is shorter than the shortest distance between the source terminal of the first low potential side FET and the smoothing circuit; A drive circuit board comprising:

2. a shortest distance between a drain terminal of the first high potential side FET and the first switching element pair is shorter than a shortest distance between a source terminal of the first high potential side FET and the first switching element pair; a shortest distance between a source terminal of the first low potential side FET and the first switching element pair is shorter than a shortest distance between a drain terminal of the first low potential side FET and the first switching element pair; 2. The drive circuit board according to claim 1.

3. the first switching element pair, the second switching element pair, and the smoothing circuit are provided in the first direction in the order of the first switching element pair, the second switching element pair, and the smoothing circuit.

2. The drive circuit board according to claim 1.

4. The frequency of the first drive signal is higher than the frequency of the second drive signal.

2. The drive circuit board according to claim 1.

5. the first switching element pair includes a second high-side FET and a second low-side FET; a shortest distance between a source terminal of the second low potential side FET and the first side is shorter than a shortest distance between a drain terminal of the second low potential side FET and the first side; the shortest distance between a source terminal of the second high potential side FET and the second low potential side FET is shorter than the shortest distance between a drain terminal of the second high potential side FET and the second low potential side FET; the second low potential side FET and the second high potential side FET are provided so as to at least partially overlap each other when viewed from a second direction perpendicular to the first direction; 2. The drive circuit board according to claim 1.

6. The first switching circuit outputs the first switching signal obtained by amplifying a modulated signal based on the basic drive signal; The second switching circuit outputs the second switching signal obtained by shifting a reference potential of the first switching signal based on the basic drive signal.

6. The drive circuit board according to claim 1, wherein the first and second electrodes are electrically connected to each other.

7. The first switching circuit has a DA conversion circuit that converts the base drive signal into an analog base drive signal, and a modulation circuit that modulates the analog base drive signal and outputs the modulated signal.

7. The drive circuit board according to claim 6.

8. a drive circuit board that outputs a drive signal for driving a capacitive load; a print head that ejects liquid by driving the capacitive load; Equipped with The drive circuit board includes: A drive circuit that outputs the drive signal corresponding to a basic drive signal; a wiring board on which the drive circuit is provided; Equipped with The drive circuit includes: a first driver circuit that outputs a first drive signal corresponding to the basic drive signal, and a first switching circuit including a first switching element pair that is driven in response to the first drive signal to output a first switching signal; a second driver circuit that outputs a second drive signal corresponding to the basic drive signal, and a second switching circuit including a second switching element pair that is driven in response to the second drive signal and outputs a second switching signal corresponding to the first switching signal; a smoothing circuit that smoothes the second switching signal and outputs the smoothed signal as the drive signal; having The wiring board includes a first side and a second side facing each other along a first direction, the second switching element pair includes a first high-side FET and a first low-side FET; the shortest distance between the source terminal of the first high potential side FET and the smoothing circuit is shorter than the shortest distance between the drain terminal of the first high potential side FET and the smoothing circuit; the shortest distance between the drain terminal of the first low potential side FET and the smoothing circuit is shorter than the shortest distance between the source terminal of the first low potential side FET and the smoothing circuit; A liquid ejection device comprising:

9. a shortest distance between a drain terminal of the first high potential side FET and the first switching element pair is shorter than a shortest distance between a source terminal of the first high potential side FET and the first switching element pair; a shortest distance between a source terminal of the first low potential side FET and the first switching element pair is shorter than a shortest distance between a drain terminal of the first low potential side FET and the first switching element pair; 9. The liquid ejection device according to claim 8.

10. the first switching element pair, the second switching element pair, and the smoothing circuit are provided in the first direction in the order of the first switching element pair, the second switching element pair, and the smoothing circuit.

9. The liquid ejection device according to claim 8.

11. The frequency of the first drive signal is higher than the frequency of the second drive signal.

9. The liquid ejection device according to claim 8.

12. the first switching element pair includes a second high-side FET and a second low-side FET; a shortest distance between a source terminal of the second low potential side FET and the first side is shorter than a shortest distance between a drain terminal of the second low potential side FET and the first side; the shortest distance between a source terminal of the second high potential side FET and the second low potential side FET is shorter than the shortest distance between a drain terminal of the second high potential side FET and the second low potential side FET; the second low potential side FET and the second high potential side FET are provided so as to at least partially overlap each other when viewed from a second direction perpendicular to the first direction; 9. The liquid ejection device according to claim 8.

13. The first switching circuit outputs the first switching signal obtained by amplifying a modulated signal based on the basic drive signal; The second switching circuit outputs the second switching signal obtained by shifting a reference potential of the first switching signal based on the basic drive signal.

13. The liquid ejection device according to claim 8, wherein the liquid ejection device is a liquid ejection device.

14. The first switching circuit has a DA conversion circuit that converts the base drive signal into an analog base drive signal, and a modulation circuit that modulates the analog base drive signal and outputs the modulated signal. The liquid ejection device according to claim 13 .

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