Digital / analog conversion device, display driver and display apparatus

Abstract

PURPOSE: To provide a digital / analog conversion device capable of generating a high-quality output voltage while suppressing noise superposition, a display driver including the digital / analog conversion device, and a display apparatus.CONSTITUTION: A digital / analog conversion device comprises: a gray code conversion circuit for receiving a sequence of digital data pieces consisting of binary codes to generate each of gray code data pieces for which each of the digital data pieces is converted into a gray code; a decoder by which the gray code data pieces and a plurality of reference voltages having mutually different voltage values are received and based on the gray code data pieces, two reference voltages including an overlap are selected from among the plurality of reference voltages and outputted as a first selection voltage and a second selection voltage; and an amplifier circuit which includes first and second input terminals for receiving the first selection voltage and the second selection voltage and generates an output voltage by amplifying a voltage which is obtained by performing an interpolation with the first selection voltage and the second selection voltage in a weighting ratio allocated to the first and second input terminals.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] The present invention relates to a digital-to-analog conversion device, a display driver for driving a display panel, and a display device. [Background technology]

[0002] A known liquid crystal display device includes a display panel in which a plurality of data lines and a plurality of scanning lines are arranged at an intersection, with display cells serving as pixels being formed at each intersection, as well as a source driver and a gate driver that drive the display panel (see, for example, Patent Document 1).

[0003] The source driver includes a shift register, a level shifter, a data register latch, a DA (digital to analog) conversion section, and an output amplifier section.

[0004] The shift register generates a plurality of latch timing signals for selecting the latches in synchronization with the clock signal, and supplies them to the data register latches.

[0005] The data register latch takes in, for example, n pieces of 8-bit display data corresponding to each display cell based on the video signal, based on each latch timing signal supplied from the shift register. The level shifter performs level shift processing on each of the n pieces of display data to increase the amplitude of the signal level corresponding to each bit, and supplies each of the n pieces of display data after the level shift to the DA conversion unit.

[0006] The DA conversion unit includes a gamma circuit and n selection circuits (decoders) provided corresponding to the n pieces of display data. The gamma circuit generates, for example, 256 voltages having different voltage values ​​as reference voltages and supplies them to the n selection circuits. Each selection circuit selects a reference voltage corresponding to a value indicated by the 8-bit display data piece it has received from the 256 reference voltages. With this configuration, the DA conversion unit supplies the n reference voltages selected by the n selection circuits as n gradation voltages to the output amplifier unit. The output amplifier unit amplifies the n gradation voltages individually and supplies them as output voltages to the n data lines of the display panel. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2009-145492 A Summary of the Invention [Problem to be solved by the invention]

[0008] In recent years, with the trend toward larger screen size and higher resolution of display panels, the period (one data period) during which an output voltage (grayscale voltage) corresponding to one piece of display data is charged to a display cell of the display panel has become shorter, and a high quality waveform of the output voltage is required to obtain the desired display quality.

[0009] However, since the display data fragment uses binary code, even if the change in the luminance level of the display data fragment supplied to the DA conversion unit per horizontal scanning period is slight, the number of changes in the logical level of each bit of the display data fragment may become large.

[0010] For example, when a piece of display data changes from a state representing a brightness level of "126" to a state representing "127", the 8-bit binary code changes from [01111110] to [01111111]. That is, for every "1" change in brightness level, the number of bits changed in the binary code is "1".

[0011] However, when the display data piece changes state from representing a brightness level of "127" to "128", the 8-bit binary code changes from [01111111] to [10000000].

[0012] In this way, in binary code, the Hamming distance between adjacent codes varies between "1" and the total number of bits (e.g., 8). Therefore, in this case, even if the amount of change in the luminance level is "1", the Hamming distance between the codes, that is, the total number of inversions of the logic level for each bit digit, is "8".

[0013] As a result, a current corresponding to the number of inversions of the logic level flows suddenly in the data register latch and the DA conversion unit, generating noise. This noise may be superimposed on the output voltage and cause deterioration of image quality.

[0014] Therefore, an object of the present invention is to provide a digital-to-analog conversion device capable of generating a high-quality output voltage with reduced noise superposition, and a display driver and display device including the digital-to-analog conversion device. [Means for solving the problem]

[0015] The digital-to-analog conversion device of the present invention comprises a Gray code conversion circuit that receives a series of digital data pieces consisting of binary codes and generates Gray code data pieces by converting each of the digital data pieces into a Gray code; a decoder that receives the Gray code data pieces and a plurality of reference voltages having different voltage values, and selects two reference voltages including overlaps from the plurality of reference voltages based on the Gray code data pieces and outputs them as a first selection voltage and a second selection voltage, respectively; and an amplifier circuit that has first and second input terminals that receive the first selection voltage and the second selection voltage, respectively, and generates an output voltage by amplifying a voltage obtained by interpolating the first selection voltage and the second selection voltage using a weighting ratio assigned to the first and second input terminals.

[0016] A display driver according to the present invention includes first to n-th digital-to-analog conversion circuits that receive a sequence of pixel data pieces, each of which expresses a luminance level of each pixel based on a video signal in a binary code, and converts each of n (n is an integer of 2 or more) pixel data pieces included in the sequence of pixel data pieces into first to n-th output voltages having voltage values ​​corresponding to the luminance levels, and supplies the output voltages to first to n-th data lines of a display panel, and further includes a gray code conversion circuit that generates each of the gray code data pieces by converting each of the pixel data pieces included in the sequence of pixel data pieces into a gray code, Each of the 1st to nth digital-analog conversion circuits includes a decoder that receives the Gray code data piece and a plurality of reference voltages having different voltage values, selects two reference voltages including overlaps from the plurality of reference voltages based on the Gray code data piece, and outputs the two reference voltages as a first selected voltage and a second selected voltage, respectively, and an amplifier circuit that has first and second input terminals that receive the first selected voltage and the second selected voltage, respectively, and generates, as the output voltage, a voltage obtained by interpolating the first selected voltage and the second selected voltage using a weighting ratio assigned to the first and second input terminals.

[0017] A display device according to the present invention is a display driver including a display panel on which first to nth (n is an integer of 2 or more) data lines are arranged, each of which has a plurality of display cells formed thereon, and first to nth digital-to-analog conversion circuits that receive a series of pixel data pieces expressing a luminance level of each pixel based on a video signal in a binary code, and convert each of the n pixel data pieces included in the series of pixel data pieces into first to nth output voltages having voltage values ​​corresponding to the luminance level, and supply the output voltages to the first to nth data lines of the display panel, and each of the pixel data pieces included in the series of pixel data pieces is converted into a gray code. each of the first to nth digital-analog conversion circuits includes a decoder that receives the Gray code data piece and a plurality of reference voltages having different voltage values, selects two reference voltages including an overlap from the plurality of reference voltages based on the Gray code data piece, and outputs the two reference voltages as a first selected voltage and a second selected voltage, respectively; and an amplifier circuit that has first and second input terminals that receive the first selected voltage and the second selected voltage, respectively, and generates, as the output voltage, a voltage obtained by interpolating the first selected voltage and the second selected voltage using a weighting ratio assigned to the first and second input terminals. Effect of the Invention

[0018] In the present invention, a series of digital data pieces represented by binary code is received, each digital data piece is converted to Gray code, and each Gray code data piece converted to Gray code is digital-to-analog converted to generate an output voltage having an analog voltage value.

[0019] This makes it possible to generate a high-quality output voltage with reduced noise generated during transitions between adjacent grayscales in a digital data piece. [Brief description of the drawings]

[0020] [Figure 1] FIG. 2 is a block diagram showing a configuration of a display device 200. [Diagram 2] 2 is a block diagram showing an internal configuration of a data driver 13. FIG. [Diagram 3] FIG. 1 is a diagram illustrating an example of binary code-Gray code conversion. [Figure 4] 2 is a block diagram illustrating an example of the configuration of a DA conversion circuit DA1. FIG. [Diagram 5] 2 is a circuit diagram showing an example of the internal configuration of a first decoder DE1 and a second decoder DE2. FIG. [Figure 6A] FIG. 2 is a diagram illustrating the operation of the first decoder DE1. [Figure 6B] 11 is a diagram illustrating the operation of the selection circuit EXSEL. [Figure 6C] 4 is a diagram illustrating the operation of the selection circuit SEL. [Figure 7] FIG. 2 is a diagram illustrating the operation of the first decoder DE1 and the second decoder DE2. [Figure 8] 13 is a circuit diagram showing another example of the internal configuration of the second decoder DE2. FIG. [Figure 9] 9 is a diagram illustrating an internal operation of the second decoder DE2 illustrated in FIG. 8. [Figure 10A] 13 is a circuit diagram showing a part of another example of the internal configuration of the second decoder DE2. FIG. [Figure 10B] 13 is a circuit diagram showing a part of another example of the internal configuration of the second decoder DE2. FIG. [Figure 11A] 10C is a diagram illustrating a part of the internal operation of the second decoder DE2 illustrated in FIGS. 10A and 10B. FIG. [Figure 11B] 10C is a diagram illustrating another internal operation of the second decoder DE2 shown in FIGS. 10A and 10B. FIG. [Figure 12] FIG. 13 is a block diagram showing a modified example of the DA conversion circuit. [Figure 13] FIG. 3 is a block diagram showing a configuration of a DA conversion device 300. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS EXAMPLES

[0021] FIG. 1 is a block diagram showing a schematic configuration of a display device 200 including a display driver according to the present invention.

[0022] As shown in FIG. 1, a display device 200 includes a display panel 20, a display controller 11, a scan driver 12, and a data driver 13 serving as a display driver.

[0023] The display panel 20 is made of, for example, a liquid crystal or organic EL panel, and includes horizontal scanning lines S1 to Sm (m is an integer of 2 or more) extending in the horizontal direction of the two-dimensional screen, and data lines D1 to Dn (n is an integer of 2 or more) extending in the vertical direction of the two-dimensional screen. At each intersection of the horizontal scanning lines and the data lines, a display cell PC which serves as a pixel is formed.

[0024] The display controller 11 receives a video signal VS, and supplies to the scan driver 12 a scan timing signal indicating the timing for sequentially selecting the horizontal scanning lines S1 to Sm in response to the video signal VS.

[0025] Furthermore, the display controller 11 generates various control signals including a start pulse signal STP and a clock signal CLK, and a video data signal VD based on the video signal VS. The start pulse signal STP is a single pulse signal generated in response to a horizontal scanning synchronization signal included in the video signal VS. The video data signal VD is a signal including a series of pixel data pieces that express the luminance level of each display cell PC, which represents a pixel, in binary code. The display controller 11 supplies the video data signal VD and the control signals to the data driver 13.

[0026] The scan driver 12 applies horizontal scan pulses to each of the horizontal scan lines S1 to Sm of the display panel 20 in sequence in response to a scan timing signal supplied from the display controller 11.

[0027] The data driver 13 converts each of n pixel data pieces in the series of pixel data pieces included in the video data signal VD into an analog voltage having a magnitude corresponding to the luminance level indicated by that pixel data piece in response to various control signals (including STP and CLK) supplied from the display controller 11. Then, the data driver 13 supplies n voltages obtained by converting the n pixel data pieces into analog voltages to the data lines D1 to Dn of the display panel 20 as output voltages G1 to Gn.

[0028] FIG. 2 is a block diagram showing the internal configuration of the data driver 13. As shown in FIG.

[0029] As shown in FIG. 2, the data driver 13 includes a Gray code conversion circuit 130, a shift register 131, a data latch unit 132, and a DA (digital to analog) conversion unit 133.

[0030] The Gray code conversion circuit 130 receives the video data signal VD and converts each of the pixel data pieces included in the video data signal VD into a Gray code. For example, as shown in Fig. 3, the Gray code conversion circuit 130 converts each of the pixel data pieces, each of which is a binary code capable of expressing 16 gradations with, for example, 4 bits (d3 to d0), into a 4-bit (d3 to d0) Gray code. Then, the Gray code conversion circuit 130 supplies the data latch unit 132 with a series VDG of Gray code data pieces obtained by individually converting each pixel data piece into a Gray code.

[0031] When the shift register 131 receives a start pulse signal STP, which is a single pulse signal, it shifts the start pulse signal STP in order in synchronization with the clock signal CLK to generate n latch timing signals SR1 to SRn, each of which produces a single pulse at a different timing. The shift register 131 supplies the latch timing signals SR1 to SRn to the data latch unit 132.

[0032] The data latch unit 132 includes data latches LC1 to LCn that receive latch timing signals SR1 to SRn, respectively. Data latch LC1 latches one Gray code data piece included in the series VDG of Gray code data pieces at the timing of a single pulse included in the latch timing signal SR1. Data latch LC2 latches one Gray code data piece included in the series VDG of Gray code data pieces at the timing of a single pulse included in the latch timing signal SR2. Similarly, each of data latches LC3 to LCn latches one Gray code data piece included in the series VDG of Gray code data pieces at the timing of a single pulse included in the latch timing signal SRj (j is an integer from 3 to n) that it receives.

[0033] Then, the data latches LC1 to LCn simultaneously supply the n pieces of Gray code data (hereinafter also referred to as GR data) that they have latched as described above to the DA conversion unit 133 as GR data R1 to Rn.

[0034] The DA conversion unit 133 includes a reference voltage generation circuit RFG that generates a plurality of reference voltages V0 to Vx (x is an integer equal to or greater than 1) having mutually different voltage values, and DA conversion circuits DA1 to DAn provided corresponding to each of the GR data R1 to Rn.

[0035] The DA conversion circuits DA1 to DAn receive the corresponding GR data R1 to Rn individually, and convert the GR data R1 to Rn into output voltages G1 to Gn having analog voltage values ​​by using the above-mentioned reference voltages V0 to Vx, and output the output voltages. The DA conversion circuits DA1 to DAn have the same internal configuration.

[0036] FIG. 4 is a block diagram showing the internal configuration of the DA conversion circuit DA1 selected from the DA conversion circuits DA1 to DAn.

[0037] As shown in FIG. 4, the DA conversion circuit DA1 includes a decoder DEC and an amplifier circuit AP1.

[0038] The decoder DEC receives reference voltages V0 to Vx supplied from the reference voltage generation circuit RFG and GR data R1 consisting of a Gray code of a total of (k+1) bits, including the kth (k is an integer greater than or equal to 2) bit (most significant bit) to the 0th bit (least significant bit).

[0039] The decoder DEC includes a first decoder DE1 and a second decoder DE2.

[0040] The first decoder DE1 receives a high-order bit group MB including the most significant bit of the GR data R1, and selects two adjacent reference voltages V0 to Vx based on the high-order bit group MB. w (w is an integer equal to or greater than 1) reference voltages are selected.

[0041] The total number of reference voltages V0 to Vx is 2. (k-w+1) and the upper bit group MB is the k-th bit (the most significant bit) to the (2·w)-th bit in the GR data R1, where “w” is a value that satisfies the relationship k≧(2w−1)>0.

[0042] The first decoder DE1 selects the two w The reference voltages are selected as L1 to L2. w to the second decoder DE2.

[0043] The second decoder DE2 outputs the selection voltages L1 to L2 w At the same time, the GR data R1 receives a lower bit group LB including the least significant bit in the GR data R1. The lower bit group LB is the (2·w−1)th bit to the 0th bit (the least significant bit) in the GR data R1.

[0044] The second decoder DE2 selects the above-mentioned selection voltages L1 to L2 based on the lower bit group LB. w 2, the selection voltages T1 and T2 output from the second decoder DE2 are supplied to the amplifier circuit AP1 as the selection voltage pair J1.

[0045] Fig. 5 is a circuit diagram showing an example of the internal configuration of the first decoder DE1 and the second decoder DE2. Note that Fig. 5 shows circuits applied as the first decoder DE1 and the second decoder DE2 when "k" is 3 and "w" is 1.

[0046] That is, the GR data R1 is a 4-bit Gray code consisting of the 3rd bit d3 to the 0th bit d0 shown in Fig. 3, the upper bit group MB is the 3rd and 2nd bits (d3, d2) of the 4 bits, and the lower bit group L is the 1st and 0th bits (d1, d0).Furthermore, the reference voltage group is reference voltages V0 to V7 whose respective voltage values ​​have the following magnitude relationship.

[0047] V7>V6>V5>V4>V3>V2>V1>V0 Furthermore, in FIG. 5, Xd3 is the inversion of the logic level of the third bit d3 in the GR data R1, Xd2 is the inversion of the logic level of the second bit d2, Xd1 is the inversion of the logic level of the first bit d1, and Xd0 is the inversion of the logic level of the 0th bit d0.

[0048] As shown in FIG. 5, the first decoder DE1 includes N-channel transistors Q1 to Q12 as switching elements.

[0049] The transistors Q1 and Q5 supply a reference voltage V0 to the transistor Q9 when the third bit d3 is at logic level 1, and supply a reference voltage V7 to the transistor Q9 when the third bit d3 is at logic level 0.

[0050] The transistors Q2 and Q6 supply the reference voltage V4 to the transistor Q11 when the third bit d3 is at logic level 1, and supply the reference voltage V3 to the transistor Q11 when the third bit d3 is at logic level 0.

[0051] Transistors Q3 and Q7 supply a reference voltage V6 to transistor Q10 when the third bit d3 is at logic level 1, and supply a reference voltage V1 to transistor Q10 when the third bit d3 is at logic level 0.

[0052] Transistors Q4 and Q8 supply a reference voltage V5 to transistor Q12 when the third bit d3 is at logic level 1, and supply a reference voltage V2 to transistor Q12 when the third bit d3 is at logic level 0.

[0053] When the second bit d2 is at logic level 1, the transistors Q9 and Q11 supply the reference voltage V0 or V7 supplied via the transistor Q1 or Q5 to the second decoder DE2 as the selection voltage L1. On the other hand, when the second bit d2 is at logic level 0, the transistors Q9 and Q11 supply the reference voltage V3 or V4 supplied via the transistor Q2 or Q6 to the second decoder DE2 as the selection voltage L1.

[0054] When the second bit d2 is at logic level 1, the transistors Q10 and Q12 supply the reference voltage V2 or V5 supplied via the transistor Q4 or Q8 to the second decoder DE2 as the selection voltage L2. On the other hand, when the second bit d2 is at logic level 0, the transistors Q10 and Q12 supply the reference voltage V2 or V5 supplied via the transistor Q4 or Q8 to the second decoder DE2 as the selection voltage L2.

[0055] FIG. 6A is a diagram showing the contents of the selection voltages L1 and L2 output by the first decoder DE1 in accordance with the third bit d3 and the second bit d2, which are the upper bit group in the GR data R1, in the configuration shown in FIG.

[0056] As shown in FIG. 5, the second decoder DE2 includes a selection circuit EXSEL made up of N-channel transistors Q21 to Q26, and a selection circuit SEL made up of N-channel transistors Q31 and Q32.

[0057] In the selection circuit EXSEL, when the first bit d1 is at logic level 1, the transistors Q21 and Q24 supply the selection voltage L2 supplied from the first decoder DE1 to the transistor Q25. On the other hand, when the first bit d1 is at logic level 0, the transistors Q21 and Q24 supply the selection voltage L1 supplied from the first decoder DE1 to the transistor Q25.

[0058] When the first bit d1 is at logic level 1, the transistors Q22 and Q23 supply the selection voltage L1 supplied from the first decoder DE1 to the transistor Q26. On the other hand, when the first bit d1 is at logic level 0, the transistors Q22 and Q23 supply the selection voltage L2 supplied from the first decoder DE1 to the transistor Q26.

[0059] When the 0th bit d0 is at logic level 1, the transistors Q25 and Q26 output the selection voltage L1 or L2 supplied via the transistor Q22 or Q23 as the selection voltage T1. On the other hand, when the 0th bit d0 is at logic level 1, the transistors Q25 and Q26 output the selection voltage L1 or L2 supplied via the transistor Q21 or Q24 as the selection voltage T1.

[0060] FIG. 6B is a diagram showing the contents of the selection voltage T1 output by the selection circuit EXSEL of the second decoder DE2 in accordance with the first bit d1 and the 0th bit d0, which are the lower bit group in the GR data R1, in the configuration shown in FIG.

[0061] In the selection circuit SEL, the transistors Q31 and Q32 output the selection voltage L2 supplied from the first decoder DE1 as the selection voltage T2 when the first bit d1 is at logic level 1. On the other hand, when the first bit d1 is at logic level 0, the transistors Q31 and Q32 output the selection voltage L1 supplied from the first decoder DE1 as the selection voltage T2.

[0062] FIG. 6C is a diagram showing the contents of the selection voltage T2 that the selection circuit SEL of the second decoder DE2 outputs in response to the first bit d1, which is the lower bit in the GR data R1, in the configuration shown in FIG.

[0063] 7, the first decoder DE1 outputs selection voltages L1 and L2 indicating one of the reference voltages V0 to V7 according to the contents of the 3rd bit d3 to the 0th bit d0 in the GR data R1. Furthermore, the second decoder DE2 selects two reference voltages including an overlap from the reference voltages V0 to V7, and supplies them to the amplifier circuit AP1 as selection voltages T1 and T2, respectively.

[0064] The amplifier circuit AP1 is an operational amplifier having an interpolation function, with its output terminal connected to its inverting input terminal and two non-inverting input terminals +A1 and +A2 receiving selection voltages T1 and T2, respectively.

[0065] The amplifier circuit AP1 performs interpolation between a selection voltage T1 received at the non-inverting input terminal +A1 and a selection voltage T2 received at the non-inverting input terminal +A2 using weighting that is preset for each of the non-inverting input terminals +A1 and +A2, and generates the amplified voltage as the output voltage Vout.

[0066] For example, the weighting ratio assigned to the non-inverting input terminal +A1 and the non-inverting input terminal +A2 is as follows: +A1:+A2=1:2 In this case, the amplifier circuit AP1 Vout = (T1 + 2 T2) / 3 The output voltage Vout indicated by is output.

[0067] For example, the DA conversion circuit DA1 outputs the output voltage Vout output from its own amplifier circuit AP1 as an output voltage G1.

[0068] Therefore, according to the configuration of each of the DA conversion circuits DA1 to DAn shown in FIG. 4, by using eight reference voltages V0 to V7, it is possible to obtain output voltages Vout for 16 gradations having mutually different voltage values, as shown in FIG.

[0069] Each of the DA conversion circuits DA1 to DAn outputs the output voltage Vout output from its own amplifier circuit AP1 as an output voltage G1 to Gn.

[0070] Furthermore, in the data driver 13, each pixel data piece expressing the luminance level of each pixel based on the video signal VS in, for example, 4 bits is converted from binary code to gray code, and each GR data piece is captured by the data latch unit 132. At this time, the data latch unit 132 supplies the n GR data pieces captured therein as GR data R1 to Rn to the DA conversion unit 133. The DA conversion unit 133 converts each of the GR data R1 to Rn into an analog voltage value corresponding to the luminance level expressed by the original binary code.

[0071] In this case, in the Gray code, the Hamming distance between adjacent codes is always "1". For example, as shown in FIG. 3, the total number of inversions of the logic level between adjacent codes (d3 to d0) at the same bit digit is "1".

[0072] Therefore, in the decoder DEC of the data latch unit 132 and the DA conversion unit 133, the frequency of inversion of the logic level occurring at each bit is significantly reduced compared to when the n pixel data pieces are received in the form of binary code, and accordingly, less current flows in the data latch unit 132 and the DA conversion unit 133. This suppresses noise caused by a sudden increase in the current flowing in the data latch unit 132 and the DA conversion unit 133 accompanying the transition of the pixel data pieces. Therefore, the data driver 13 can output high-quality output voltages G1 to Gn without noise superimposed thereon. EXAMPLES

[0073] 8 is a circuit diagram showing an example of the internal configuration of the second decoder DE2 of each of the DA conversion circuits DA1 to DAn when "w" is 2, that is, when the number of bits in the lower bit group LB is 4. In this case, the second decoder DE2 receives four selection voltages L1 to L4 together with four bits consisting of the third bit d3 to the 0th bit d0 as the lower bit group LB.

[0074] The second decoder DE2 shown in FIG. 8 includes selection circuits EXS1 to EXS4 each having the same internal configuration as the selection circuit EXSEL shown in FIG. 5, and selection circuits SE1 and SE2 having the same internal configuration as the selection circuit SEL shown in FIG.

[0075] 8, the selection circuit EXS1 supplies a selection voltage L1 or L4 to the selection circuit EXS3 in response to the third bit d3 and the second bit d2. The selection circuit EXS2 supplies a selection voltage L2 or L3 to the selection circuit EXS3 in response to the third bit d3 and the second bit d2.

[0076] The selection circuit EXS3 outputs, as a selection voltage T1, the selection voltage L1 or L4 supplied from the selection circuit EXS1, or the selection voltage L2 or L3 supplied from the selection circuit EXS2, in response to the first bit d1 and the zeroth bit d0.

[0077] The selection circuit SE1 supplies the selection voltage L1 or L4 to the selection circuit EXS4 in response to the third bit d3. The selection circuit SE2 supplies the selection voltage L2 or L3 to the selection circuit EXS4 in response to the third bit d3.

[0078] The selection circuit EXS4 outputs, as a selection voltage T2, the selection voltage L1 or L4 supplied from the selection circuit SE1, or the selection voltage L2 or L3 supplied from the selection circuit SE2, in response to the second bit d2 and the first bit d1.

[0079] FIG. 9 is a diagram illustrating the internal operation of the second decoder DE2 shown in FIG.

[0080] According to the configuration shown in Fig. 8, the second decoder DE2 selects two of the reference voltages V0 to V3, including overlaps, according to four bits from the third bit d3 to the zeroth bit d0, as shown in Fig. 9, and supplies them to the amplifier circuit AP1 as selected voltages T1 and T2, respectively. At this time, the amplifier circuit AP1 generates an output voltage Vout by amplifying a voltage obtained by interpolating the selected voltage T1 and the selected voltage T2.

[0081] Therefore, according to the second decoder DE2 shown in FIG. 8, by using four reference voltages V0 to V3, it is possible to obtain output voltages Vout for 16 gradations having mutually different voltage values ​​as shown in FIG. EXAMPLES

[0082] 10A and 10B are circuit diagrams showing an example of the internal configuration of the second decoder DE2 of each of the DA conversion circuits DA1 to DAn when "w" is 3, that is, when the number of bits in the lower bit group LB is 6. In this case, the second decoder DE2 receives eight selection voltages L1 to L8 together with 6 bits consisting of the 5th bit d5 to the 0th bit d0 as the lower bit group LB.

[0083] The second decoder DE2 shown in FIGS. 10A and 10B includes selection circuits EXS1 to EXS10 each having the same internal configuration as the selection circuit EXSEL shown in FIG. 5, and selection circuits SE1 to SE4 each having the same internal configuration as the selection circuit SEL shown in FIG.

[0084] In Fig. 10A, the selection circuit EXS1 supplies a selection voltage L1 or L8 to the selection circuit EXS5 in response to the fifth bit d5 and the fourth bit d4. The selection circuit EXS2 supplies a selection voltage L4 or L5 to the selection circuit EXS5 in response to the fifth bit d5 and the fourth bit d4. The selection circuit EXS3 supplies a selection voltage L2 or L7 to the selection circuit EXS6 in response to the fifth bit d5 and the fourth bit d4. The selection circuit EXS4 supplies a selection voltage L3 or L6 to the selection circuit EXS6 in response to the fifth bit d5 and the fourth bit d4.

[0085] The selection circuit EXS5 supplies the selection voltage L1 or L8 supplied from the selection circuit EXS1, or the selection voltage L4 or L5 supplied from the selection circuit EXS2, to the selection circuit EXS7 in accordance with the third bit d3 and the second bit d2.

[0086] The selection circuit EXS6 supplies the selection voltage L2 or L7 supplied from the selection circuit EXS3, or the selection voltage L3 or L6 supplied from the selection circuit EXS4, to the selection circuit EXS7 in response to the third bit d3 and the second bit d2.

[0087] The selection circuit EXS7 outputs, in response to the first bit d1 and the zeroth bit d0, the selection voltage L1, L8, L4 or L5 supplied from the selection circuit EXS5, or the selection voltage L2, L7, L3 or L6 supplied from the selection circuit EXS6, as the selection voltage T1.

[0088] 10B, the selection circuit SE1 supplies a selection voltage L1 or L8 to the selection circuit EXS8 in response to the fifth bit d5. The selection circuit SE2 supplies a selection voltage L4 or L5 to the selection circuit EXS8 in response to the fifth bit d5. The selection circuit SE3 supplies a selection voltage L2 or L7 to the selection circuit EXS9 in response to the fifth bit d5. The selection circuit SE4 supplies a selection voltage L3 or L6 to the selection circuit EXS9 in response to the fifth bit d5.

[0089] The selection circuit EXS8 supplies the selection voltage L1 or L8 supplied from the selection circuit SE1, or the selection voltage L4 or L5 supplied from the selection circuit SE2, to the selection circuit EXS10 in response to the fourth bit d4 and the third bit d3.

[0090] The selection circuit EXS9 supplies the selection voltage L2 or L7 supplied from the selection circuit SE3, or the selection voltage L3 or L6 supplied from the selection circuit SE4, to the selection circuit EXS10 in response to the fourth bit d4 and the third bit d3.

[0091] The selection circuit EXS10 outputs, in response to the second bit d2 and the first bit d1, the selection voltage L1, L8, L4 or L5 supplied from the selection circuit EXS8, or the selection voltage L2, L7, L3 or L6 supplied from the selection circuit EXS9, as the selection voltage T2.

[0092] 11A and 11B are diagrams illustrating the internal operation of the second decoder DE2 shown in FIGS. 10A and 10B.

[0093] 10A and 10B, the second decoder DE2 selects two of the reference voltages V0 to V7, including overlaps, according to six bits from the 5th bit d5 to the 0th bit d0, as shown in Fig. 11A and 11B, and supplies them to the non-inverting input terminals +A1 and +A2 as the selected voltages T1 and T2, respectively. At this time, the amplifier circuit AP1 generates an output voltage Vout by amplifying a voltage obtained by performing an interpolation between the selected voltage T1 and the selected voltage T2 using a weighting ratio assigned to the non-inverting input terminals +A1 and +A2.

[0094] Therefore, according to the second decoder DE2 shown in Figures 10A and 10B, by using eight systems of reference voltages V0 to V7, it is possible to obtain output voltages Vout for 64 gradations having different voltage values ​​as shown in Figures 11A and 11B. EXAMPLES

[0095] FIG. 12 is a block diagram of a DA conversion circuit showing a modified example of the decoder DEC shown in FIG.

[0096] 12 includes a first decoder DE1 and a second decoder DE2, similar to the decoder DEC shown in FIG. 4. However, in the decoder DEC shown in FIG. 12, the first decoder DE1 selects two decoders having different voltage values ​​from among the reference voltages V0 to Vx in accordance with a lower bit group LB consisting of the (2w-1)-th to 0-th bits in the GR data fragment as a Gray code data fragment. (k-2w) Each reference voltage is selected as a selected voltage L1 to L2. (k-2w)The second decoder DE2 supplies the selected voltages L1 to L2 in accordance with a high-order bit group MB consisting of the k-th to (2w)-th bits in the GR data fragment. (k-2w) Two selection voltages including an overlap are selected from these and supplied as selection voltages T1 and T2 to the non-inverting input terminals +A1 and +A2 of the amplifier circuit AP1, respectively.

[0097] In the above-mentioned embodiments 1 to 4, in order to convert each of the n pixel data pieces into an analog voltage value, n DA conversion circuits (DA1 to DAn) each having the configuration shown in FIG. 4 or FIG. 12, and a Gray code conversion circuit 130 are provided in the data driver 13.

[0098] However, the use is not limited to DA conversion of pixel data pieces, and a configuration including a DA conversion circuit and a Gray code conversion circuit shown in Figure 4 or Figure 12 may be adopted as a DA conversion device that simply converts digital data into an analog output voltage.

[0099] FIG. 13 is a block diagram showing the configuration of a DA (digital to analog) conversion device 300 according to the present invention, which has been made in view of the above points.

[0100] As shown in FIG. 13, the DA conversion device 300 includes a Gray code conversion circuit 130a that is the same as the Gray code conversion circuit 130 shown in FIG. 2, and a decoder DECa and an amplifier circuit APa that have the same configurations as the decoder DEC and the amplifier circuit AP1 shown in FIG. 4 or FIG. 12, respectively.

[0101] The Gray code conversion circuit 130a receives a series DIN of digital data pieces composed of binary codes, and supplies a series IDG of Gray code data pieces obtained by converting each of the digital data pieces into a Gray code to the decoder DECa. The decoder DECa includes a first decoder DE1 and a second decoder DE2 shown in FIG. 4 or FIG. 12, and receives reference voltages V0 to Vx having different voltage values, and the series IDG of Gray code data pieces.

[0102] The decoder DECa selects two reference voltages including overlaps from among the reference voltages V0 to Vx based on each Gray code data piece in the sequence IDG of Gray code data pieces through the operation of the first decoder DE1 and the second decoder DE2 described above. Then, the decoder DECa supplies the two selected reference voltages as selection voltages T1 and T2 to the non-inverting input terminals +A1 and +A2 of the amplifier circuit APa. The amplifier circuit APa generates an output voltage Vout by amplifying a voltage obtained by performing an interpolation between the selection voltage T1 and the selection voltage T2 using a weighting ratio assigned to the non-inverting input terminals +A1 and +A2.

[0103] In short, such a single DA conversion device 300 or a DA conversion device included in the data driver 13 of the display device 200 may include the following Gray code conversion circuit, decoder, and amplifier circuit.

[0104] The Gray code conversion circuits (130, 130a) receive digital data pieces consisting of binary codes as conversion targets, and generate Gray code data pieces (VDG, IDG) by converting the digital data pieces into Gray codes.

[0105] The decoder (DEC, DECa) receives a plurality of reference voltages (V0 to Vx) having different voltage values ​​and a Gray code data piece, selects two reference voltages including an overlap from among the plurality of reference voltages based on the Gray code data piece, and outputs the two reference voltages as a first and a second selected voltage, respectively.

[0106] The amplifier circuit (AP1, APa) has first and second input terminals (+A1, +A2), receives the above-mentioned first and second selected voltages at the first and second input terminals, and generates an output voltage by amplifying the voltage obtained by interpolating the first selected voltage and the second selected voltage using the weighting ratios assigned to the first and second input terminals.

[0107] In the example shown in Fig. 13, a digital data piece consisting of a binary code to be converted is converted to a gray code by a gray code conversion circuit 130a, and the gray code data piece is converted to an analog output voltage Vout by a DA conversion circuit (DECa, APa). With this configuration, the frequency of bit inversions occurring in the gray code data piece in response to the transition of the digital data piece is less than the number of bit inversions in the digital data piece. Therefore, the amount of change in the current flowing in the decoder DECa in response to the transition of the gray code data piece is also reduced, and noise caused by the change in the current is suppressed.

[0108] Incidentally, the DA conversion circuits (DECa, APa) shown in FIG. 13 obtain an analog output voltage by interpolating two voltages selected from a plurality of reference voltages (V0 to Vx) based on a digital data piece, but the Gray code conversion circuit 130a may be added to a DA conversion circuit that employs a DA conversion method other than such a DA conversion circuit. [Explanation of symbols]

[0109] 130, 130a Gray code conversion circuit 133 DA conversion section AP1, APa amplifier circuit DA1~DAn DA conversion circuit DE1 First decoder DE2 Second decoder RFG reference voltage generation circuit

Claims

1. a Gray code conversion circuit that receives a series of digital data pieces each consisting of a binary code and converts each of the digital data pieces into a Gray code to generate Gray code data pieces; a decoder that receives the Gray code data piece and a plurality of reference voltages having different voltage values, selects two reference voltages including overlaps from the plurality of reference voltages based on the Gray code data piece, and outputs the two reference voltages as a first selection voltage and a second selection voltage, respectively; a first input terminal for receiving the first selected voltage and a second input terminal for receiving the second selected voltage, respectively; and an amplifier circuit for generating an output voltage by amplifying a voltage obtained by interpolating the first selected voltage and the second selected voltage using a weighting ratio assigned to the first input terminal and a weighting ratio assigned to the second input terminal.

2. The decoder comprises: selecting two adjacent voltage values ​​from the plurality of reference voltages based on a first group of bits in the Gray code data piece; ｗ (w is an integer of 1 or more) reference voltages are selected, and each of them is designated as the first to second ｗ a first decoder for outputting a selected voltage of based on a second group of bits in the Gray code data piece, ｗ and a second decoder that selects two reference voltages including the overlap from among the selected voltages and outputs them as the first selected voltage and the second selected voltage, respectively.

3. Each of the Gray code data pieces is composed of a total of (k+1) bits, with the most significant bit being the kth bit (k is an integer equal to or greater than 2) and the least significant bit being the 0th bit, the first bit group is a high-order bit group consisting of the kth bit to the (2·w)th bit, 3. The digital-to-analog conversion device according to claim 2, wherein the second bit group is a lower bit group consisting of the (2·w−1)th bit to the 0th bit.

4. Each of the Gray code data pieces is composed of a total of (k+1) bits, with the most significant bit being the kth bit (k is an integer equal to or greater than 2) and the least significant bit being the 0th bit, the first bit group is a lower bit group consisting of the (2 w-1)th bit to the 0th bit, 3. The digital-to-analog conversion device according to claim 2, wherein the second bit group is a most significant bit group consisting of the kth bit to the (2·w)th bit.

5. The digital-to-analog conversion device according to any one of claims 1 to 4, characterized in that the amplifier circuit is an operational amplifier having an interpolation function, in which the first and second input terminals are both non-inverting input terminals and its output terminal is connected to its inverting input terminal.

6. a display driver including first to n-th digital-to-analog conversion circuits that receive a sequence of pixel data pieces, each of which expresses a luminance level of each pixel based on a video signal in a binary code, and converts each of n (n is an integer of 2 or more) pixel data pieces included in the sequence of pixel data pieces into first to n-th output voltages having voltage values ​​corresponding to the luminance levels, and supply the output voltages to first to n-th data lines of a display panel; a Gray code conversion circuit that generates Gray code data pieces by converting each of the pixel data pieces included in the sequence of pixel data pieces into a Gray code; Each of the first to n-th digital-to-analog conversion circuits a decoder that receives the Gray code data piece and a plurality of reference voltages having different voltage values, selects two reference voltages including overlaps from the plurality of reference voltages based on the Gray code data piece, and outputs the two reference voltages as a first selection voltage and a second selection voltage, respectively; a first input terminal for receiving the first selection voltage and a second selection voltage, respectively; and an amplifier circuit for generating as the output voltage a voltage obtained by interpolating the first selection voltage and the second selection voltage using a weighting ratio assigned to the first input terminal and the second selection voltage.

7. a display panel on which first to n-th (n is an integer of 2 or more) data lines are arranged, each of which has a plurality of display cells formed thereon; a display driver including first to n-th digital-to-analog conversion circuits that receive a sequence of pixel data pieces, the pixel data pieces representing a luminance level of each pixel based on a video signal in binary code, and convert each of n pixel data pieces included in the sequence of pixel data pieces into first to n-th output voltages having voltage values ​​corresponding to the luminance levels, and supply the output voltages to first to n-th data lines of the display panel; a Gray code conversion circuit that generates Gray code data pieces by converting each of the pixel data pieces included in the sequence of pixel data pieces into a Gray code; Each of the first to n-th digital-to-analog conversion circuits a decoder that receives the Gray code data piece and a plurality of reference voltages having different voltage values, selects two reference voltages including overlaps from the plurality of reference voltages based on the Gray code data piece, and outputs the two reference voltages as a first selection voltage and a second selection voltage, respectively; a first input terminal for receiving the first selection voltage and a second selection voltage, respectively; and an amplifier circuit for generating as the output voltage a voltage obtained by interpolating the first selection voltage and the second selection voltage using a weighting ratio assigned to the first input terminal and the second selection voltage.

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