Spread spectrum clock generation circuit

Abstract

To realize a spectrum spread technology to change the frequency of a generated clock signal even when generating a clock signal using a CR oscillator circuit.SOLUTION: A flash memory 40 is a storage element that stores a trimming code for adjusting a resistance value of a trimming resistor 37 such that the oscillation frequency of an output clock signal 110 generated by a CR oscillation circuit 30 becomes a preset frequency. The CR oscillation circuit 30 generates an output clock signal 110 having a frequency based on a time constant determined by the resistance value R of the trimming resistor 37, which is a resistive element, and the capacitance value C of the capacitance elements 35 and 36. An up-down counter 50 is a counter circuit that synchronizes with the output clock signal 110 generated by the CR oscillation circuit 30, and increases or decreases the trimming code stored in the flash memory 40 to output it as a trimming code for adjusting the resistance value of the trimming resistor 37.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a spread spectrum clock generating circuit. [Background technology]

[0002] In addition to improving noise resistance (EMS: Electro Magnetic Susceptibility), MCUs (Micro Controller Units) are also required to reduce the amount of noise they generate and suppress EMI (Electro Magnetic Interference).To suppress the generation of EMI, a technology called spread spectrum is used to intentionally change the frequency of the clock signal that operates the MCU, thereby suppressing the peak amount of generated noise and preventing malfunction of peripheral devices.

[0003] As a spread spectrum clock generating circuit that changes the frequency of a clock signal generated using such a spread spectrum technique, a clock generating circuit using a PLL (Phase Locked Loop) circuit is widely used (see, for example, Patent Document 1).

[0004] In a PLL circuit, a feedback loop is formed that compares the phase and frequency of a reference clock and a feedback clock. In a PLL circuit, when the division number of the frequency divider that divides the feedback clock changes, the frequency of the output clock also changes, so the frequency of the clock can be controlled and changed by changing the division number. In addition, PLL circuits generally have a voltage controlled oscillator (VCO) that changes frequency according to a control voltage, and the output frequency can be periodically changed by dithering, which adds a triangular wave to the control voltage input to this voltage controlled oscillator. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-243911 A Summary of the Invention [Problem to be solved by the invention]

[0006] Here, MCUs often have multiple clock generation circuits, and the clock generation circuit to be used may be switched as necessary. In such a case, if a clock generation circuit other than the clock generation circuit using a PLL circuit as described above is selected, EMI countermeasures using spectrum spread will not be possible. For example, a clock generation circuit that is widely used in MCUs may be a CR oscillation circuit that generates a clock signal with a frequency based on a time constant determined by the resistance value (R) of a resistive element and the capacitance value (C) of a capacitive element.

[0007] However, the spectrum spread technology applied to PLL circuits cannot be applied to CR oscillator circuits, and it is desirable to realize a spectrum spread technology that changes the frequency of the generated clock signal even in a clock generation circuit configured to generate a clock signal using a CR oscillator circuit.

[0008] An object of the present invention is to provide a spread spectrum clock generation circuit that can realize a spread spectrum technique for changing the frequency of a generated clock signal even when a clock signal is generated using a CR oscillation circuit. [Means for solving the problem]

[0009] In order to solve the above problems, the spread spectrum clock generating circuit of the present invention comprises: a CR oscillation circuit that generates a clock signal having a frequency based on a time constant determined by a resistance value of a resistive element and a capacitance value of a capacitive element; a memory element storing a trimming code for adjusting a resistance value of the resistive element or a capacitance value of the capacitive element so that a frequency of a clock signal generated by the CR oscillation circuit becomes a preset frequency; and a counter circuit which increases or decreases the trimming code stored in the memory element in synchronization with the clock signal generated by the CR oscillation circuit, and outputs the trimming code as a trimming code for adjusting the resistance value of the resistive element or the capacitance value of the capacitive element.

[0010] In addition, in the spread spectrum clock generation circuit of the present invention, the counter circuit may be configured to increase or decrease the trimming code stored in the memory element so that the trimming code to be output is within a preset range of the trimming code stored in the memory element.

[0011] In the spread spectrum clock generating circuit of the present invention, the resistive element is a ladder-type trimming resistor whose resistance value changes based on an input trimming code, the memory element stores a trimming code for adjusting a resistance value of the resistor element so that a frequency of a clock signal generated by the CR oscillation circuit becomes a preset frequency; The counter circuit may be configured to increase or decrease the trimming code stored in the memory element in synchronization with the clock signal generated by the CR oscillation circuit, and output the trimming code as a trimming code for adjusting the resistance value of the resistance element.

[0012] Furthermore, the spread spectrum clock generating circuit of the present invention is a feedback type oscillation circuit in which the CR oscillation circuit is composed of an amplifier circuit and a feedback circuit and oscillates to generate a clock signal when an oscillation condition is satisfied, or a relaxation type oscillation circuit in which a clock signal is generated by controlling the on / off timing of a switching element. Effect of the Invention

[0013] According to the present invention, even when a clock signal is generated using a CR oscillation circuit, it is possible to provide a spread spectrum clock generation circuit that can realize a spread spectrum technique for changing the frequency of the generated clock signal. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a diagram showing a circuit configuration of a clock generation circuit using a PLL circuit as a comparative example. [Diagram 2] FIG. 1 is a diagram illustrating a circuit configuration of an example of a spread spectrum clock generating circuit using a PLL circuit. [Diagram 3] FIG. 13 is a diagram showing a clock generation circuit using a CR oscillation circuit as a comparative example. [Figure 4] 4 is a diagram showing the relationship between the trimming code and the oscillation frequency in the CR oscillation circuit 30. FIG. [Diagram 5] 1 is a diagram showing a circuit configuration of a spread spectrum clock generation circuit according to an embodiment of the present invention; [Figure 6] 6 is a diagram showing operation waveforms in the spread spectrum clock generating circuit of the present embodiment shown in FIG. 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Next, an embodiment of the present invention will be described in detail with reference to the drawings.

[0016] First, before describing the spread spectrum clock generating circuit of this embodiment, a circuit configuration of a clock generating circuit using a general PLL circuit will be described as a comparative example.

[0017] FIG. 1 is a diagram showing a circuit configuration of a clock generation circuit using a PLL circuit as a comparative example.

[0018] As shown in FIG. 1, the clock generation circuit of this comparative example is composed of a phase comparison circuit 14, a charge pump circuit 15, a loop filter (LPF) 16, a VCO (voltage controlled oscillator) 17, and a 1 / N divider 18.

[0019] The phase comparison circuit 14 detects the phase difference between the feedback clock signal 106 and the reference clock signal 101, and when the phase of the reference clock signal 101 leads the phase of the feedback clock signal 106, it outputs an up pulse signal 102 to the charge pump circuit 15. In addition, when the phase of the reference clock signal 101 lags the phase of the feedback clock signal 106, the phase comparison circuit 14 outputs a down pulse signal 103 to the charge pump circuit 15.

[0020] The charge pump circuit 15 increases or decreases the output voltage based on the up pulse signal 102 or the down pulse signal 103. Specifically, when the charge pump circuit 15 receives the up pulse signal 102, it increases the output voltage, and when the charge pump circuit 15 receives the down pulse signal 103, it decreases the output voltage.

[0021] The loop filter (LPF) 16 is a filter circuit that smoothes the output voltage from the charge pump circuit 15 and outputs the smoothed output voltage as a control voltage 104 to the VCO 17 .

[0022] Due to the circuit configuration as described above, when the phase comparison circuit 14 outputs an up pulse signal 102, the control voltage 104 rises, and when the phase comparison circuit 14 outputs a down pulse signal 103, the control voltage 104 falls.

[0023] VCO (Voltage Controlled Oscillator) 17 generates an output clock signal 105 with an oscillation frequency according to a control voltage 104 input from loop filter 16 .

[0024] The 1 / N frequency divider 18 is a frequency divider circuit that divides the frequency of the output clock signal 105 generated by the VCO 17 by a preset frequency division ratio N and outputs the result as a feedback clock signal 106 .

[0025] 1, the frequency of output clock signal 105 is controlled by setting the division ratio N for 1 / N divider 18. That is, the frequency of output clock signal 105 can be controlled by changing the division ratio N. For example, if the division ratio N set for 1 / N divider 18 is 100, the frequency of output clock signal 105 will be 100 times the frequency of reference clock signal 101.

[0026] As described above, the VCO 17 is configured to generate and output the output clock signal 105 having a frequency according to the input control voltage 104. Therefore, by changing the control voltage 104, it is possible to change the frequency of the output clock signal 105.

[0027] By utilizing these characteristics of the PLL circuit, a spread spectrum clock generation circuit can be realized. Figure 2 shows the circuit configuration of an example of a spread spectrum clock generation circuit using a PLL circuit.

[0028] The spread spectrum clock generating circuit shown in FIG. 2 has a configuration in which an adder 19 and a triangular wave generating circuit 20 are added to the circuit configuration shown in FIG.

[0029] The triangular wave generating circuit 20 generates and outputs a triangular wave. Then, the adder 19 adds the triangular wave generated by the triangular wave generating circuit 20 to the voltage smoothed by the loop filter 16 and outputs the result as a control voltage 104 to the VCO 17.

[0030] 2, the control voltage 104 input to the VCO 17 is not constant but fluctuates due to the added triangular wave. Therefore, the frequency of the output clock signal 105 generated by the VCO 17 also fluctuates, and the spectrum of the noise component due to the output clock signal 105 also spreads.

[0031] Next, FIG. 3 shows a clock generation circuit using a CR oscillation circuit as a comparative example, instead of the clock generation circuit using a PLL circuit as shown in FIG. 1 and FIG.

[0032] 3 includes a CR oscillation circuit 30 and a flash memory 40. The CR oscillation circuit 30 includes inverter circuits 31 to 34, capacitance elements 35 and 36, and a trimming resistor 37, which are connected in series.

[0033] 3 generates an output clock signal 110 with a frequency based on a time constant determined by the resistance value R of a trimming resistor 37, which is a resistive element, and the capacitance value C of the capacitive elements 35 and 36. Specifically, the CR oscillator circuit 30 generates an output clock signal 110 with an oscillation frequency proportional to the inverse of the time constant CR determined by the resistance value R of the trimming resistor 37 and the capacitance value C of the capacitive elements 35 and 36.

[0034] However, since the capacitance elements and resistance elements formed on a semiconductor wafer vary from chip to chip, there will also be variation in the oscillation frequency of the generated output clock signal 110. Therefore, in the CR oscillation circuit 30 shown in Fig. 3, a trimming resistor 37 whose resistance value can be changed is used as the resistance element to suppress the variation in the oscillation frequency from chip to chip, thereby making it possible to obtain an output clock signal 110 with a constant frequency.

[0035] Here, the trimming resistor 37 is a ladder-type trimming resistor whose resistance value changes based on an input trimming code.

[0036] The flash memory 40 is a storage element that stores a trimming code for adjusting the resistance value of the trimming resistor 37 so that the oscillation frequency of the output clock signal 110 generated by the CR oscillation circuit 30 becomes a preset frequency.

[0037] Here, the description will be made on the assumption that the frequency of the output clock signal 110 is adjusted to 1 MHz, and the relationship between the trimming code and the oscillation frequency in the CR oscillation circuit 30 is as shown in FIG.

[0038] 4, when the trimming code is n, the oscillation frequency of the output clock signal 110 of the CR oscillation circuit 30 is 1 MHz, and when the trimming code is n-1, the oscillation frequency is 0.995 MHz. In other words, when the trimming code changes by 1, the oscillation frequency changes by about 0.5%.

[0039] In the clock generation circuit shown in FIG. 3, it is assumed that a value of n is stored as the trimming code in the flash memory 40 in order to set the oscillation frequency of the output clock signal 110 to 1 MHz.

[0040] Next, FIG. 5 shows a circuit configuration of a spread spectrum clock generating circuit according to one embodiment of the present invention, in which spread spectrum technology is applied to the clock generating circuit using the CR oscillation circuit shown in FIG.

[0041] The spread spectrum clock generating circuit according to one embodiment of the present invention shown in FIG. 5 has a configuration in which an up / down counter 50 is added to the clock generating circuit shown in FIG. 3 as a comparative example.

[0042] The up-down counter 50 is a counter circuit that, in synchronization with the output clock signal 110 generated by the CR oscillation circuit 30, increases or decreases the trimming code stored in the flash memory 40 and outputs it as a trimming code for adjusting the resistance value of the trimming resistor 37. Specifically, the up-down counter 50 changes and outputs the trimming code in synchronization with the rising edge of the output clock signal 110.

[0043] The up-down counter 50 increases or decreases the trimming code n stored in the flash memory 40 so that the trimming code to be output to the trimming resistor 37 is within a preset range of the trimming code n stored in the flash memory 40. For example, in this embodiment, when the trimming code stored in the flash memory 40 is n, the up-down counter 50 operates so that the trimming code to be output to the trimming resistor 37 changes between n-4 and n. Specifically, the up-down counter 50 changes the trimming code in the following order in synchronization with the rising edge of the output clock signal 110: n → (n-1) → (n-2) → (n-3) → (n-4) → (n-3) → (n-2) → (n-1) → n → (n-1) → . . .

[0044] Next, FIG. 6 shows the operation waveforms in the spread spectrum clock generating circuit of the present embodiment shown in FIG.

[0045] Referring to FIG. 6, it can be seen that although the trimming code read from the flash memory 40 is constant at n, the trimming code output from the up / down counter 50 changes as follows: n → (n-1) → (n-2) → (n-3) → (n-4) →...

[0046] Therefore, it can be seen that the oscillation frequency of the output clock signal 110 also changes from 1.0 MHz, 0.995 MHz, 0.990 MHz, 0.985 MHz, 0.980 MHz, . . . in accordance with the change in this trimming code.

[0047] As described above, in the spread spectrum clock generating circuit of this embodiment, the up / down counter 50 that operates according to the logic change of the output clock signal 110 is inserted between the trimming code from the flash memory 40 and the trimming resistor 37, so that the trimming code output to the trimming resistor 37 changes in synchronization with the clock of the output clock signal 110. Therefore, the oscillation frequency of the output clock signal 110 changes dynamically, and the spectrum of the output clock signal 110 is spread. As a result, the spread spectrum clock generating circuit of this embodiment makes it possible to reduce the EMI (radiated noise) of the entire MCU.

[0048] In other words, according to the spread spectrum clock generation circuit of this embodiment, even when a clock signal is generated using a CR oscillation circuit, it is possible to realize a spread spectrum technique that changes the frequency of the generated clock signal.

[0049] In the above embodiment, the trimming method for trimming the oscillation frequency is described using a trimming method in which the resistance value is changed by the ladder-type trimming resistor 37, but the present invention is not limited to this case. The present invention is also applicable to a trimming method in which the capacitance value of a capacitive element is changed according to a trimming code, instead of changing the resistance value.

[0050] Furthermore, the CR oscillation circuit 30 is not limited to a feedback-type oscillation circuit that is composed of an amplifier circuit and a feedback circuit and oscillates to generate a clock signal when an oscillation condition is satisfied, but can also be applied to a relaxation-type oscillation circuit that generates a clock signal by controlling the on / off timing of a switching element as long as it is an oscillation circuit whose oscillation frequency changes by trimming. [Explanation of symbols]

[0051] 14 Phase comparison circuit 15 Charge pump circuit 16 Loop Filter 17 VCO 18 1 / N frequency divider 19 Adder 20 Triangular wave generation circuit 30 CR Oscillator Circuit 31~34 Inverter circuit 35, 36 Capacitor element 37 Trimming resistor 40 Flash Memory 50 Up / Down Counter 101 Reference Clock Signal 102 Up pulse signal 103 Down Pulse Signal 104 Control Voltage 105 Output Clock Signal 106 Feedback Clock Signal 110 Output Clock Signal

Claims

1. a CR oscillation circuit that generates a clock signal having a frequency based on a time constant determined by a resistance value of a resistive element and a capacitance value of a capacitive element; a memory element storing a trimming code for adjusting a resistance value of the resistive element or a capacitance value of the capacitive element so that a frequency of a clock signal generated by the CR oscillation circuit becomes a preset frequency; a counter circuit that increases or decreases the trimming code stored in the memory element in synchronization with a clock signal generated by the CR oscillation circuit, and outputs the trimming code as a trimming code for adjusting the resistance value of the resistive element or the capacitance value of the capacitive element; A spread spectrum clock generation circuit comprising:

2. the counter circuit increases or decreases the trimming code stored in the memory element so that the trimming code to be output is within a preset range from the trimming code stored in the memory element; 2. The spread spectrum clock generating circuit according to claim 1.

3. the resistor element is a ladder-type trimming resistor whose resistance value changes based on an input trimming code, the memory element stores a trimming code for adjusting a resistance value of the resistor element so that a frequency of a clock signal generated by the CR oscillation circuit becomes a preset frequency; the counter circuit increases or decreases the trimming code stored in the memory element in synchronization with the clock signal generated by the CR oscillation circuit, and outputs the trimming code as a trimming code for adjusting the resistance value of the resistor element.

3. The spread spectrum clock generating circuit according to claim 1 or 2.

4. The CR oscillator circuit is a feedback type oscillator circuit that is composed of an amplifier circuit and a feedback circuit and oscillates to generate a clock signal when an oscillation condition is satisfied, or a relaxation type oscillator circuit that generates a clock signal by controlling the on / off timing of a switching element.

3. The spread spectrum clock generating circuit according to claim 1 or 2.

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