External oscillator control and calibration

Abstract

To provide an apparatus and a method for external oscillator control and calibration.SOLUTION: In a particular embodiment, an electronic oscillator system includes a semiconductor die and a controllable oscillator external to the semiconductor die. The oscillation frequency of the controllable oscillator is adjusted by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor.SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] FIELD OF THEINVENTION Embodiments of the invention relate to electronic systems, and more particularly, to control and calibration of external oscillators. [Background technology]

[0002] Voltage controlled oscillators (VCOs) are widely used in electronic and communications applications such as clock generation and distribution, carrier synthesis, and data recovery. A VCO may include an oscillator core that generates an oscillating output signal, and a resonator (e.g., an inductor-capacitor tank) that exhibits a variable electrical characteristic, such as capacitance and / or inductance, in the oscillator core. The frequency of oscillation depends at least in part on the value of the variable electrical characteristic, and thus, adjusting the resonator provides a method of controlling the frequency of oscillation of the output signal.

[0003] The VCO may be included in a control loop, such as a phase-locked loop (PLL), which may use feedback to set the input control voltage of the VCO to a desired value. Summary of the Invention

[0004] Apparatus and methods are provided for control and calibration of an external oscillator. In a particular embodiment, an electronic oscillator system includes a semiconductor die and a controllable oscillator external to the semiconductor die. The oscillation frequency of the controllable oscillator is adjusted by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor.

[0005] In one aspect, an electronic oscillator system includes a semiconductor die, a controllable oscillator external to the semiconductor die, a first varactor configured to adjust an oscillation frequency of the controllable oscillator, and a second varactor configured to adjust an oscillation frequency of the controllable oscillator. The semiconductor die includes a phase-locked loop (PLL) configured to provide a fine adjustment to the controllable oscillator by controlling the first varactor, and a calibration circuit configured to provide a coarse adjustment to the controllable oscillator by controlling the second varactor.

[0006] In another aspect, a method of electronic oscillator control is provided. The method includes adjusting an oscillation frequency of a controllable oscillator using a first varactor, the controllable oscillator being external to a semiconductor die. The method further includes adjusting an oscillation frequency of the controllable oscillator using a second varactor, controlling the first varactor to provide a fine adjustment to the controllable oscillator using a phase-locked loop (PLL) on the semiconductor die, and controlling the second varactor to provide a coarse adjustment to the controllable oscillator using a calibration circuit on the semiconductor die.

[0007] In another aspect, a radio frequency communication system is provided that includes a mixer controlled by an oscillator signal, a semiconductor die, a controllable oscillator external to the semiconductor die and configured to output the oscillator signal, a first varactor configured to adjust an oscillation frequency of the controllable oscillator, and a local oscillator including a second varactor configured to adjust an oscillation frequency of the controllable oscillator. The semiconductor die includes a phase-locked loop (PLL) configured to provide a fine adjustment to the controllable oscillator by controlling the first varactor, and a calibration circuit configured to provide a coarse adjustment to the controllable oscillator by controlling the second varactor. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram of one embodiment of a radio frequency (RF) communication system. [Figure 2A] FIG. 2 is a schematic diagram of one embodiment of tuning an external voltage controllable oscillator (VCO). [Figure 2B] FIG. 13 is a schematic diagram of another embodiment of tuning an external VCO. [Figure 3A] FIG. 1 is a schematic diagram of an electronic oscillator system according to one embodiment. [Figure 3B] FIG. 2 is a schematic diagram of an electronic oscillator system according to another embodiment. [Figure 4] 1 is a schematic diagram of an outer VCO tracking loop according to one embodiment. [Figure 5A] 4 is a schematic diagram of an outer VCO tracking loop according to another embodiment. [Figure 5B] 4 is a schematic diagram of an outer VCO tracking loop according to another embodiment. [Figure 6] FIG. 2 is a schematic diagram of an electronic oscillator system according to another embodiment. [Figure 7] FIG. 2 is a schematic diagram of another embodiment of an electronic oscillator system including a semiconductor die operating in a first coarse calibration mode. [Figure 8] FIG. 1 is a schematic diagram of another embodiment of an electronic oscillator system including a semiconductor die operating in a second coarse calibration mode. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The following detailed description of the embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in many different ways. In this description, reference is made to the drawings, in which like reference numbers may indicate identical or functionally similar elements. It will be understood that the elements illustrated in the figures are not necessarily drawn to scale. It will further be understood that certain embodiments can include more elements than shown in the drawings and / or a subset of the elements shown in the drawings. Furthermore, some embodiments can incorporate any suitable combination of features from two or more drawings.

[0010] Control and calibration of an external controllable oscillator is provided herein. In a particular embodiment, an electronic oscillator system includes a semiconductor die and a controllable oscillator (e.g., a VCO) that is external to the semiconductor die. The oscillation frequency of the controllable oscillator is adjusted by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor.

[0011] Thus, the controllable oscillator can be controlled using a first loop with a low gain and a second loop with a higher gain than the second loop, which in turn achieves low noise, wide tuning range, and the ability to implement a PLL on a semiconductor die while operating within the supply voltage limitations associated with typical semiconductor die manufacturing processes.

[0012] The teachings herein are applicable to a wide range of electronic systems and applications. For example, transceivers, such as land vehicle radio transceivers, may use an external VCO as a local oscillator (LO).

[0013] Figure 1 is a schematic diagram of one embodiment of an RF communication system 30. The RF communication system 30 includes a transceiver 1, a front-end system 2, and an antenna 3. The transceiver 1 of Figure 1 may include one or more local oscillators (LOs) implemented with tuning and calibration loops in accordance with the teachings herein. However, the teachings herein are applicable to other configurations of electronic circuitry.

[0014] In the embodiment shown, transceiver 1 includes a transmitter 5 and a receiver 6. Although not shown in FIGURE 1, transceiver 1 may also include other circuitry, such as an observation receiver, control circuitry, and / or additional transmitters and / or receivers.

[0015] Although FIG. 1 illustrates the transceiver 1 as including one transmitter and one receiver, the transceiver may include additional transmitters, receivers, and / or observation receivers.

[0016] In the embodiment shown, transmitter 5 includes an I-path DAC 11a, an I-path amplifier 12a, an I-path mixer 13a, a Q-path DAC 11b, a Q-path amplifier 12b, a Q-path mixer 13b, and a transmit local oscillator (LO) 14. Although one embodiment of transmitter circuitry is shown, the transmitter may be implemented in other manners.

[0017] For signal transmission, I-path DAC 11a converts the digital I signal to an analog I signal, which is amplified by I-path amplifier 12a. Additionally, Q-path DAC 11b converts the digital Q signal to an analog Q signal, which is amplified by Q-path amplifier 12b. Transmit LO 14 provides an I-path clock signal to I-path mixer 13a, which upconverts the amplified analog I signal. Transmit LO 14 also provides a Q-path clock signal to Q-path mixer 13b, which upconverts the amplified analog Q signal. The outputs of I-path mixer 13a and Q-path mixer 13b are combined to generate an RF transmit signal TX, which is provided to front-end system 2.

[0018] 1, receiver 6 includes an I-path ADC 21a, an I-path amplifier 22a, an I-path mixer 23a, a Q-path ADC 21b, a Q-path amplifier 22b, a Q-path mixer 23b, and a receive LO 24. Although one embodiment of the receiver circuitry is shown, the receiver may be implemented in other manners.

[0019] With respect to signal reception, receiver 6 receives RF receive signal RX from front-end system 2. Receive LO 24 provides an I path clock signal to I path mixer 23a and a Q path clock signal to Q path mixer 23b. I path mixer 23a down-converts RF receive signal RX using the I path clock signal to generate an analog I signal. The analog I signal is amplified by I path amplifier 22a and digitized by I path ADC 21a to generate a digital I signal. Q path mixer 23b down-converts RF receive signal RX using the Q path clock signal to generate an analog Q signal. The analog Q signal is amplified by Q path amplifier 22b and digitized by Q path ADC 21b to generate a digital Q signal.

[0020] The transceiver 1 may be implemented according to any of the embodiments herein.

[0021] 1, the front-end system 2 includes a power amplifier 27 that amplifies an RF transmit signal TX for transmission on the antenna 3, and a low noise amplifier 28 that generates an RF receive signal RX based on amplifying the receive signal from the antenna 3. Although only the power amplifier 27 and the low noise amplifier 28 are shown, the front-end system 2 may include other components, including but not limited to filters, switches, duplexers, diplexers, couplers, and / or other components. Furthermore, the transmit and receive channels need not share an antenna, but rather may use separate antennas.

[0022] The transceiver 1 can receive not only RF signals in the 30MHz to 7GHz band, but also X-band (approximately 7GHz to 12GHz), K u band (approx. 12GHz to 18GHz), K band (approx. 18GHz to 27GHz), K aThe present invention can handle signals of various frequencies, including higher frequency signals such as those in the RF band (approximately 27 GHz to 40 GHz), V band (approximately 40 GHz to 75 GHz), and / or W band (approximately 75 GHz to 110 GHz). Thus, the teachings herein are applicable to a wide variety of RF communication systems, including microwave systems.

[0023] FIG. 2A is a schematic diagram of one embodiment of tuning an external VCO. In this embodiment, the external VCO has a frequency vs. voltage gain (K VCO ) using a 9V tuning range (0.5V to 9.5V). The external VCO has a frequency range of 100 MHz to account for the desired tuning range as well as process, voltage, and / or temperature (PVT) variations.

[0024] FIG. 2B is a schematic diagram of another embodiment of tuning an external VCO. In this embodiment, the external VCO has a K VCO1 The first loop for fine tuning has a K of 11 MHz / Volt. VCO2 The first loop operates over a relatively small voltage adjustment range of 1V, allowing the first loop to be implemented on the semiconductor die while operating within the typical supply voltage limits associated with the semiconductor die manufacturing process. The first loop also has a low gain, which is better for noise. The second loop operates over a wide voltage adjustment range of 9V (0.5V to 9.5V) and provides a wide frequency range of 100MHz to account for PVT.

[0025] K VCO Various example values, voltage ranges, and frequencies are shown in Figures 2A and 2B, although other values ​​are possible.

[0026] 3A is a schematic diagram of an electronic oscillator system 50 according to one embodiment. Electronic oscillator system 50 includes a semiconductor die 41 and a controllable oscillator 42 that is external to semiconductor die 41. Electronic oscillator system 50 further includes a first varactor 43 controlled by a fine control signal FINE from semiconductor die 41 and a second varactor 44 controlled by a coarse control signal COARSE from semiconductor die 41.

[0027] As shown in FIG. 3A, the controllable oscillator 42 outputs an oscillation signal OSC having an oscillation frequency controlled by a fine control signal FINE and by a coarse control signal COARSE.

[0028] Thus, the oscillation frequency of the controllable oscillator 42 is adjusted by the first varactor 43 and the second varactor 44 .

[0029] 3A, the semiconductor die 41 includes a phase-locked loop (PLL) 45 that provides fine adjustment to the controllable oscillator 42 by controlling a fine control signal FINE provided to the first varactor 43. In addition, the semiconductor die 41 further includes a calibration circuit 46 that provides coarse adjustment to the controllable oscillator 42 by controlling a coarse control signal COARSE provided to the second varactor 44. An oscillator signal OSC is provided to the semiconductor die 41 to provide feedback for adjusting the fine control signal FINE and the coarse control signal COARSE.

[0030] By implementing electronic oscillator system 50 in this manner, controllable oscillator 42 can be controlled using a first loop with a low gain (LOW GAIN LOOP) and a second loop with a higher gain (HIGH GAIN LOOP), which in turn achieves low noise, wide tuning range, and the ability to implement PLL 45 on semiconductor die 41 while operating within the supply voltage limitations associated with typical semiconductor die manufacturing processes.

[0031] 3B is a schematic diagram of an electronic oscillator system 130 according to another embodiment. The electronic oscillator system 130 includes a semiconductor die 101 and various components external to the semiconductor die 101 on a circuit board.

[0032] In the embodiment shown, the external components include an external VCO 102, a first varactor 103, a second varactor 104, a first amplifier 105, a second amplifier 106, a temperature sensor 107, a VCO input capacitor 108, a VCO output capacitor 109, a VCO bias inductor 110, a first varactor series capacitor 111a, a second varactor series capacitor 111b, a first varactor bias inductor 112a, a second varactor series capacitor 112b, a first varactor bias inductor 112c, a second varactor bias inductor 112d, a second varactor bias inductor 112e, a second varactor bias inductor 112f, a second varactor bias inductor 112g, a second varactor bias inductor 112h, a second varactor bias inductor 112i ... The input amplifier includes a bias inductor 112b, a coarse tuning resistor bypass switch 113a, a bias resistor bypass switch 113b, a coarse tuning resistor 114a, a bias resistor 114b, a first voltage divider resistor 115a / 115b, a second voltage divider resistor 116a / 116b, a first amplifier input resistor 117a, a second amplifier input resistor 117b, a bias capacitor 118, a fine tuning capacitor 119a, a sense capacitor 119b, and a coarse tuning capacitor 120.

[0033] 3B includes a PLL 121, a coarse adjustment and calibration circuit 122, an auxiliary analog-to-digital converter (ADC) 123, a PVT and coarse adjustment digital-to-analog converter (DAC) 124, an amplitude DAC 125, and a switchable resistor network 126. The switchable resistor network 126 includes a fixed resistor 127, a switchable resistor 128, and a resistor bypass switch 129. The semiconductor die 101 also includes a coarse adjustment pin V coarse , Fine adjustment pin V fine , range sensing pin V Z , VCO sensing pin V vco , and the VCO bias pin V bias It also includes various pins or pads, including

[0034] The external VCO 102 is tuned by both the first varactor 103 and the second varactor 104. The first varactor 103 is tuned by a fine-tune pin V that is set by a PLL 121 that can operate at low voltages (e.g., using a 1V charge pump 132). fine As shown in FIG. 3B, the PLL 121 is controlled by the voltage at the VCO sense pin V vco For example, the PLL 121 may include a phase and / or frequency detector (PFD) 133 that compares the feedback clock signal to a reference clock signal, and the output of the PFD is used to control a charge pump 132 of the PLL.

[0035] The second varactor 104 is controlled by a coarse adjustment and calibration circuit 122, which may include adjustment circuitry 131 for PVT, temperature coefficient (TC), and / or amplitude control. The coarse adjustment and calibration circuit 122 provides a digital coarse control signal to a DAC 124, which in turn provides a coarse adjustment pin V coarse Although shown as a single DAC 124 for providing the PVT and coarse adjustment, multiple DACs can be used.

[0036] A current flows from the DAC 124 through resistor 117a to generate a coarse adjustment voltage that is scaled by amplifier 105 to generate a scaled coarse adjustment voltage that adjusts the second varactor 104. While the coarse adjustment voltage is generated by a current flowing through a current DAC and through a resistor, other implementations are possible, such as a voltage DAC generating the coarse adjustment voltage. The external amplifier 105 outputs a voltage coarse to a voltage level suitable for varactor control, for example, to about 20 V. The external amplifier 105 is connected to a varactor voltage source V suitable for generating such a voltage level. VAR Noise from amplifier 105 is filtered by a low frequency RC filter that can be selectively bypassed (e.g., during calibration).

[0037] In this embodiment, the coarse adjustment and calibration circuit 122 receives temperature information from the temperature sensor 107 via the ADC 123, as well as the VCO sense pin V vco from the VCO's output clock signal, and the range sense pin V Z Receive adjustment range information from

[0038] In a particular implementation, the coarse tuning and calibration circuit 122 first adjusts the VCO bias pin V bias (and a bias supply voltage V DDB The VCO amplitude calibration is performed based on biasing the external VCO 102 (using a second amplifier 106 powered by VCO 104) as well as based on observing the VCO output clock signal from the VCO sense pin Vvco. After the initial amplitude calibration, the coarse adjustment and calibration circuit 122 can coarsely tune the external VCO 102 using the second varactor 104.

[0039] During normal operation after amplitude calibration and coarse tuning, the PLL 121 serves to provide fine tuning to the external VCO 102 by controlling the first varactor 103. In addition, the coarse tuning and calibration circuit 122 is connected to the range sense pin V Z may be used to monitor the tuned voltage of PLL 121 and perform a coarse adjustment when the tuned voltage exceeds an upper threshold or falls below a lower threshold. Thus, the coarse adjustment may serve to keep the tuned voltage within a desired tuned voltage range set by the upper and lower thresholds.

[0040] Although one embodiment has been described with VCO amplitude scaling, such amplitude scaling may be omitted, e.g., amplitude DAC 125 and second amplifier 106 need not be included to drive external VCO 102 to a desired target amplitude.

[0041] 4 is a schematic diagram of an outer VCO tracking loop 210 according to one embodiment. The outer VCO tracking loop 210 includes a coarse control resistor 201 on a substrate, and a low pass filter 202 and a control loop core 203 formed on a semiconductor die attached to the substrate.

[0042] Although certain components are shown as being on a substrate or a semiconductor die, other configurations are possible.

[0043] The control loop core 203 can be an analog loop or a digital loop. The control loop core 203 receives a range sense signal V (generated by sensing the fine tuning voltage used to control the fine tuning varactor). z , the signal V z the upper threshold (V tune_up ) and the lower threshold (V tune_dn ) by comparing it to the signal V z (hence the value of the fine-tuning voltage V in Figure 3B) fine ) is held between the two thresholds. coarse In some implementations, the outer VCO tracking loop uses the temperature information 204 (T BOARD ) can be received.

[0044] In the illustrated embodiment, the low pass filter 202 filters the signal V z , which in this embodiment includes a series resistor 207 and a shunt capacitor 208.

[0045] 5A is a schematic diagram of an outer VCO tracking loop 230 according to another embodiment. The outer VCO tracking loop 230 includes a coarse control resistor 201 on a substrate, a low pass filter 202, a first comparator 211, a second comparator 212, a comparator processing circuit 213, a summer 219, and a PVT / TC DAC 220 formed on a semiconductor die attached to the board.

[0046] In this embodiment, an analog hysteresis comparator 211 / 212 is used to calculate the sensed voltage V (after low-pass filtering by low-pass filter 202). z The upper threshold V tune_up and the lower threshold V tune_dn Additionally, the output of the comparator is processed by a comparator processing circuit 213, which includes an increment / decrement counter 215, a flip-flop 216 (controlled by a clock signal CLK), an integrator 217, and a modulator 218. The output of the comparator processing circuit 213 is added in the digital domain to a PVT code 221 set by a PVT calibration loop and then provided to a PVT / TC DAC 220.

[0047] FIG. 5B is a schematic diagram of an outer VCO tracking loop 240 according to another embodiment.

[0048] The outer VCO tracking loop 240 of Figure 5B is similar to that of the outer VCO tracking loop 230 of Figure 5A, except that separate DACs 231 are used for the PVT and TC. Thus, a TC DAC 232 is included for temperature control, a PVT DAC 233 is provided for PVT control, and the outputs of the DACs are combined. Implementing the system in this manner can reduce the DAC dynamic range specification.

[0049] 6 is a schematic diagram of an electronic oscillator system 430 according to another embodiment. The electronic oscillator system 430 includes a semiconductor die 401 and various components external to the semiconductor die 401 on a circuit board.

[0050] In the embodiment shown, the external components are CC_VCOThe VCO includes an external VCO 402 (powered by a first varactor 103, a second varactor 104, a first amplifier 105, a second amplifier 106, a temperature sensor 107, a VCO input capacitor 108, a VCO output capacitor 109, a first varactor series capacitor 111a, a second varactor series capacitor 111b, a first varactor bias inductor 112a, a second varactor bias inductor 112b, a coarse tuning resistor bypass switch 113a, a coarse tuning resistor 114a, a bias capacitor 118, a fine tuning capacitor 119a, a sense capacitor 119b, a coarse tuning capacitor 120, a VCO clock buffer 403, and a coarse tuning voltage scaling circuit 404.

[0051] 6 includes a PLL 421, a coarse frequency adjustment and temperature compensation (TC) calibration circuit 422 (also referred to as a coarse frequency adjustment and TC calibration loop), an auxiliary analog-to-digital converter (ADC) 123, a switchable resistor network 126, and an analog-to-digital interface 423. The switchable resistor network 126 includes a fixed resistor 127, a switchable resistor 128, and a resistor bypass switch 129. The semiconductor die 401 also includes a coarse adjustment pin V coarse , Fine adjustment pin V fine , range sensing pin V Z , and various pins or pads including the VCO sensing pin Vvco.

[0052] The external VCO 402 is tuned by both a first varactor 103 (fine tuning varactor) and a second varactor 104 (coarse tuning varactor). The first varactor 103 is tuned by a fine tuning pin V that is set by a PLL 421 that operates with a low voltage (in this embodiment, less than 1 V) charge pump. fine 6, PLL 421 receives the VCO's clock signal (in this embodiment, through clock driver 403) on VCO sense pin Vvco.

[0053] The second varactor 104 (coarse tuning varactor) is coupled to the coarse tuning voltage pin V coarseThe coarse adjustment voltage pin V coarse The voltage level of is stepped up by a coarse voltage scaling circuit 404 to set the bias voltage of the second varactor 104 (the coarse varactor). The coarse voltage scaling circuit 404 may include level shifters, amplifiers, charge pumps, and / or other suitable circuitry that serves to step up the bias voltage of the coarse varactor 104 from a low voltage domain associated with the semiconductor die 401 to a high voltage domain associated with the external VCO 402.

[0054] FIG. 7 is a schematic diagram of another embodiment of an electronic oscillator system 460 including a semiconductor die 431 operating in a first coarse calibration mode.

[0055] Electronic oscillator system 460 includes semiconductor die 431 and a circuit board that includes various components external to semiconductor die 431. The external components include external VCO 402 (powered by a 5V supply in this example), first varactor 103, second varactor 104, temperature sensor 107, VCO input capacitor 108, VCO output capacitor 109, first varactor series capacitor 111a, second varactor series capacitor 111b, first varactor bias inductor 112a, second varactor bias inductor 112b, fine tuning capacitor 119a, sense capacitor 119b, VCO clock buffer 403, first current mirror transistor 433, second current mirror transistor 434, current mirror load resistor 435 (coupled to a 20V supply in this example), coarse tuning bias resistor 436, first current mirror load capacitor 437, second current mirror load capacitor 438, first calibration switch S1, and second calibration switch S2. cal1 , coarse-tuning integrated capacitor C i , and the sensing resistor R z Includes.

[0056] The semiconductor die 431 of FIG. 7 includes a PLL 451, a coarse frequency adjustment / switch control calibration circuit 452, an auxiliary ADC 123, an auxiliary switch S aux , Calibration DAC453, Calibration DAC Reference Current Source Iref , (In some implementations, I ref Calibration DAC reference current switch S ref , the second calibration switch S cal2 , the third calibration switch S cal3 , Upper calibration switch S calup , Downward Calibration Switch S caldn , current up source I up , current down source I dn , the first charging switch S chg1 , the second charging switch S chg2 , the third charging switch S chg3 , (S chg1 1 when is closed . Charging resistor R (connected between the 8V power supply and ground) chg , (reference voltage V ref A first controllable transconductance circuit G m1 , and (reference voltage V ref A second controllable transconductance circuit G m2 The semiconductor die 431 also includes a coarse adjustment pin V coarse , Fine adjustment pin V fine , range sensing pin V Z , Coarse adjustment integral pin V coarse_int , VCO sensing pin V vco It also includes various pins or pads, including

[0057] The external VCO 402 is tuned by both a first varactor 103 (fine tuning varactor) and a second varactor 104 (coarse tuning varactor). The first varactor 103 is a reference clock signal CLK ref A fine adjustment pin V set by the PLL 451, which includes a PFD 455 (which receives the feedback clock signal), a charge pump 456, and a feedback divider 457. fine is controlled by the voltage.

[0058] The second varactor 104 (coarse tuning varactor) is controlled by a coarse frequency adjust / switch control calibration circuit 452 which controls the state of a calibration DAC 453 as well as the switches shown. The coarse frequency adjust / switch control calibration circuit 452 receives a temperature signal D from the auxiliary ADC 123. temp Receive the calibration DAC code D cal to the calibration DAC 453.

[0059] Semiconductor die 431 has a coarse voltage pin V coarse The DAC453 can operate in several modes to control the transconductance circuit G. m1 and G m2 The first mode (DAC / G m -C mode) and the calibrated charge pump (S calup , I up , I dn , and S caldn ) and a first transconductance circuit G m1 The second mode (Charge Pump / G m -C mode).

[0060] The electronic oscillator system can be implemented by selecting the board components desired for a particular application, and the semiconductor die 431 selects a first mode (DAC / Gate) based on the board components selected for that application. m -C mode) or the second mode (Charge Pump / G m -C mode) can be used to provide a coarse calibration. For example, the first mode (DAC / G m -C mode) can provide lower performance with lower board complexity, while the second mode (Charge Pump / G m -C mode) can offer higher performance at the expense of increased board component complexity.

[0061] The electronic oscillator system 460 of FIG. 7 is implemented using external components suitable for operation in the first mode (DAC / Gm-C mode). Table 1 below shows the external components suitable for operation in the first mode (DAC / Gm 1 shows the three-state operation of the transconductance circuit G-C mode, where ON=1 and OFF=0. The states are operated in sequence starting from the reset state, then transitioning to the calibration state and ending with the tracking state. The reset state is used to reset the voltage levels of the nodes, while the calibration state is used to calibrate the voltage levels to the desired values. Then, the transconductance circuit G m1 / G m2 is the coarse voltage pin V coarse Distance sensing pin V z In this embodiment, the integrating capacitor C i current integration is provided by, and in tracking mode, the second transconductance stage G m2 However, the coarse voltage pin V coarse In this embodiment, the coarse voltage pin V coarse controls the current mirror, which in turn controls the bias of the coarse tuning varactor 104 .

[0062] [Table 1]

[0063] Now, referring to FIG. 7, one embodiment of the first mode will be described. In this embodiment, the coarse frequency adjustment / switch control calibration circuit 452 operates as a finite state machine (FSM) that starts in a reset state. In addition, during reset, the PLL block is powered up by a separate power-up signal from a local serial peripheral interface (SPI) present in the PLL (which may be initiated by firmware). In addition, the external VCO, synth, and external circuitry are powered up and ready for calibration (which may be initiated by firmware).

[0064] Once the new frequency is written to the semiconductor die 431, the FSM transitions from the RESET state to the CALIBRATE state. In the CALIBRATE state, the PLL loop is opened and the PFD can be reset. In addition, the FSM also writes the calibration DAC code D calA search (e.g., a binary search or a linear search) can be performed. For example, a binary search can start from the height of the most significant bit (MSB), and the current from the DAC generates a coarse voltage for the external VCO using an external bipolar transistor and RC components. After each DAC bit trial, the DAC has a programmable time to settle before starting the frequency measurement. The measured frequency of the external VCO can be compared to the PLL reference frequency, or a frequency derived from the PLL reference frequency, or a predefined target value. Furthermore, once all bits of the calibration DAC 453 have been used, the FSM transitions to a tracking state.

[0065] In the tracking state, the charge pump tristate is issued (through control of the PFD) and then the transconductance circuit G m1 and G m2 and tracking is provided by locking the VCO calibration loop with an integrating capacitor Ci, and the first transconductance circuit G m1 senses the fine-tuning voltage, compares it with a reference value, and a second transconductance circuit G m2 In addition, a second transconductance compares the output to a reference value and also generates a current to drive the coarse voltage pin V coarse Drives.

[0066] FIG. 8 is a schematic diagram of another embodiment of an electronic oscillator system 470 including a semiconductor die operating in a second, coarse calibration mode.

[0067] Electronic oscillator system 470 includes semiconductor die 431 and a circuit board that includes various components external to semiconductor die 431. The external components include external VCO 402 (powered by a 5V power supply in this example), first varactor 103, second varactor 104, temperature sensor 107, VCO input capacitor 108, VCO output capacitor 109, first varactor series capacitor 111a, second varactor series capacitor 111b, first varactor bias inductor 112a, second varactor bias inductor 112b, fine tuning capacitor 119a, sense capacitor 119b, VCO clock buffer 403, amplifier 461, feedback integration capacitor 462, and sense resistor R z Includes.

[0068] The semiconductor die 431 of FIG. 8 includes a PLL 451, a coarse frequency adjustment / switch control calibration circuit 452, an auxiliary ADC 123, an auxiliary switch S aux , Calibration DAC453, Calibration DAC Reference Current Source I ref , Calibration DAC Reference Current Switch S ref , the second calibration switch S cal2 , the third calibration switch S cal3 , Upper calibration switch S calup , Downward Calibration Switch S caldn , current up source I up , current down source I dn , the first charging switch S chg1 , the second charging switch S chg2 , the third charging switch S chg3 , (S chg1 1 when is closed . Charging resistor R (connected between the 8V power supply and ground) chg , (reference voltage V ref A first controllable transconductance circuit G m1 , and (reference voltage V ref A second controllable transconductance circuit G m2 The semiconductor die 431 also includes a coarse adjustment pin V coarse , Fine adjustment pin V fine , range sensing pin V Z , Coarse adjustment integral pin Vcoarse_in, VCO sensing pin V vco It also includes various pins or pads, including

[0069] The external VCO 402 is tuned by both a first varactor 103 (fine tuning varactor) and a second varactor 104 (coarse tuning varactor). The first varactor 103 is a reference clock signal CLK ref A fine adjustment pin V set by the PLL 451, which includes a PFD 455 (which receives the feedback clock signal), a charge pump 456, and a feedback divider 457. fine is controlled by the voltage.

[0070] As previously described with reference to FIG. 7, semiconductor die 431 includes a coarse voltage pin V coarse The DAC453 and the transconductance circuit G can be operated in several modes to control the m1 and G m2 The first mode (DAC / G m -C mode) and the calibrated charge pump (S calup , I up , I dn , and S caldn ) and transconductance circuit G m1 The second mode (Charge Pump / G m -C mode).

[0071] The electronic oscillator system 470 of FIG. m The MOSFET is implemented using external components suitable for operation in the first mode (Charge Pump / G -C mode). m 1 shows three states of operation of the transconductance stage G1 in the 1-C mode, where ON=1 and OFF=0. The states are operated in sequence starting from the reset state, then transitioning to the calibration state and ending with the tracking state. The reset state is used to reset the voltage levels of the nodes, and the calibration state is used to calibrate the voltage levels to the desired values. Then, the transconductance stage G1 is m1 The distance measurement transmission pin V zBased on the coarse voltage pin V coarse A tracking state is entered which controls the bias of the coarse adjustment varactor 104. In this embodiment, the integration of the coarse adjustment voltage is provided externally by amplifier 461 and feedback integration capacitor 462. The output of amplifier 461 (in this embodiment in the 20V domain) controls the bias of the coarse adjustment varactor 104.

[0072] [Table 2]

[0073] One embodiment of the second mode will now be described with reference to Figure 8. In this embodiment, the coarse frequency adjustment / switch control calibration circuit 452 operates as an FSM that starts in a reset state. In the reset state, the PLL block is powered up by a separate power-up signal from a local SPI present in the PLL (which may be initiated by firmware). In addition, the external VCO, synth, and external circuitry are powered up and ready for calibration (which may be initiated by firmware).

[0074] Once the new frequency is written to the semiconductor die 431, the FSM transitions from the reset state to the calibration state. In the calibration state, the PLL loop is opened and the PFD can be reset. In addition, the FSM also starts the calibration charge pump (S calup and S caldn ) and set the up and down controls so that the current from the calibration charge pump is (S calup is on), or (S caldn Depending on the polarity of the current from the calibration charge pump, either a sink current (when the PLL is on) or a current source (when the PLL is on), it is integrated on an external capacitor 462. After waiting a programmable time to settle, the frequency of the external VCO 402 is measured. In addition, the measured VCO frequency relative to the PLL reference frequency is compared to a frequency derived from the PLL reference frequency or a predetermined target value.

[0075] Once the VCO frequency approaches the target frequency, the FSM transitions to a tracking state. In the tracking state, the tri-state of the charge pump is issued through the PFD, after which the tracking loop achieves lock and the first transconductance circuit G m1 senses the fine tuning voltage, compares it to a reference value, and generates a current to drive an external amplifier and an integrating capacitor.

[0076] conclusion The foregoing description may refer to elements or features as being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element / feature is directly or indirectly connected to another element / feature, but not necessarily mechanically connected. Similarly, unless expressly stated otherwise, "coupled" means that one element / feature is directly or indirectly connected to another element / feature, but not necessarily mechanically coupled. Thus, while the various schematics depicted in the figures depict example configurations of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming the functionality of the depicted circuit is not adversely affected).

[0077] Although specific embodiments have been described, these embodiments are presented as examples only and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and further, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given configuration, alternative embodiments may perform similar functionality using different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The scope of the present invention is therefore defined solely by reference to the appended claims.

[0078] The claims presented herein are in single dependent format for purposes of filing with the USPTO, but it should be understood that any claim may be dependent on any preceding claim of the same type unless clearly technically impracticable. [Explanation of symbols]

[0079] 1 Transmitter / Receiver 2 Front-end system 3 Antennas 5 Transmitter 6 Receiver 12a I-pass amplifier 12b Q-pass amplifier 13a I-path mixer 13b Q-path mixer 14 Transmit local oscillator (LO) 22a I-pass amplifier 22b Q-pass amplifier 23a I-path mixer 23b Q-path mixer 27 Power Amplifier 28 Low Noise Amplifier 30 RF Communication Systems 41 Semiconductor Die 42 Controllable Oscillator 43 First Varactor 44 Second Varactor 45 Phase Locked Loop (PLL) 46 Calibration Circuit 50 Electronic Oscillator System 101 Semiconductor Die 103 First Varactor 104 Second Varactor 104 Coarse tuning varactor 105 First Amplifier 106 Second Amplifier 107 Temperature Sensor 108 VCO input capacitor 109 VCO output capacitor 110 VCO Bias Inductor 111a First varactor series capacitor 111b Second varactor series capacitor 112a First varactor bias inductor 112b Second Varactor Bias Inductor 113a Coarse resistor bypass switch 113b Bias Resistor Bypass Switch 114a coarse adjustment resistor 114b Bias resistor 115a First voltage dividing resistor 116a Second voltage dividing resistor 117a first amplifier input resistor 117a resistor 117b Second amplifier input resistor 118 Bias Capacitor 119a Fine Tuning Capacitor 119b Sensing capacitor 120 Coarse Adjustment Capacitor 122 Calibration Circuit 123 Auxiliary Analog-to-Digital Converter (ADC) 124 Coarse Digital-to-Analog Converter (DAC) 126 Possible Resistor Network 127 Fixed resistor 128 possible resistor 129 Resistor Bypass Switch 130 Electronic Oscillator System 131 Adjustment Circuitry 132 Charging Pump 132V Charge Pump 133 Frequency Detector (PFD) 201 Coarse control resistor 202 Low-pass filter 203 Control Loop Core 204 Temperature information 207 Series Resistor 208 Shunt Capacitor 210 External VCO Tracking Loop 211 First comparator 212 Second comparator 213 Comparator Processing Circuit 215 Down Counter 216 flip-flops (controlled by the clock signal CLK) 217 Integrator 218 Modulator 219 Adder 220TC DAC 221 PVT Code 230 External VCO Tracking Loop 232TC DAC 233 PVT DAC 240 External VCO Tracking Loop 401 Semiconductor Die 403 VCO Clock Buffer 404 Coarse voltage scaling circuit 422 Calibration Circuit 423 Digital Interface 430 Electronic Oscillator System 431 Semiconductor Die 433 First Current Mirror Transistor 434 Second Current Mirror Transistor 435 Current mirror load resistor (in this example, tied to a 20V power supply) 436 Coarse bias resistor 437 First Current Mirror Load Capacitor 438 Second Current Mirror Load Capacitor 452 Switch Control Calibration Circuit 456 Charging Pump 457 Feedback Divider 460 Electronic Oscillator System 461 Amplifier 462 Feedback Integration Capacitor 470 Electronic Oscillator System

Claims

1. 1. An electronic oscillator system comprising: A semiconductor die; a controllable oscillator external to the semiconductor die; a first varactor configured to adjust the oscillation frequency of the controllable oscillator; a second varactor configured to adjust the oscillation frequency of the controllable oscillator; The semiconductor die includes a phase-locked loop (PLL) configured to provide fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit configured to provide coarse tuning to the controllable oscillator by controlling the second varactor.

2. 2. The electronic oscillator system of claim 1, wherein the semiconductor die further comprises a coarse voltage pin configured to output a coarse control voltage, the electronic oscillator system further comprising a coarse voltage scaling circuit configured to scale the coarse control voltage to generate a varactor control voltage for the second varactor.

3. 2. The electronic oscillator system of claim 1, wherein the semiconductor die comprises a coarse voltage pin configured to output a coarse control voltage for controlling the second varactor, a calibration digital-to-analog converter (DAC), and a calibration charge pump, the calibration circuitry operating in a first mode in which the calibration DAC sets a voltage level of the coarse voltage pin and a second mode in which the calibration charge pump sets the voltage level of the coarse control voltage.

4. 4. The electronic oscillator system of claim 3, wherein the semiconductor die further comprises a first transconductance stage and a second transconductance stage, wherein in the first mode, the first transconductance stage and the second transconductance stage operate in series to adjust the voltage level of the coarse voltage pin after it is set by the calibration DAC, and in the second mode, the first transconductance stage adjusts the voltage level of the coarse voltage pin after it is set by the calibration charge pump.

5. 5. The electronic oscillator system of claim 4, wherein in the first mode, the first transconductance stage generates a current based on comparing a reference signal to a sensed fine tuning voltage to control the first varactor, and the second transconductance stage receives the current and drives the coarse tuning voltage pin.

6. 2. The electronic oscillator system of claim 1, further comprising a digital-to-analog converter (DAC) having an input for receiving digital data from the calibration circuit and an output connected to the coarse voltage pin, the coarse voltage pin being for controlling the second varactor.

7. 2. The electronic oscillator system of claim 1, wherein the coarse adjustment voltage pin is for controlling the second varactor, and further comprising: a first DAC for controlling the coarse adjustment voltage pin based on a process voltage temperature (PVT) code; and a second DAC for controlling the coarse adjustment voltage pin based on an oscillator voltage range sensed by the calibration circuit.

8. 2. The electronic oscillator system of claim 1, wherein the calibration circuit is configured to calibrate an amplitude of the controllable oscillator based on controlling a bias of the controllable oscillator and observing an output oscillator signal of the controllable oscillator.

9. 2. The electronic oscillator system of claim 1, wherein the calibration circuit is configured to compare a tuning voltage set by the PLL to an upper threshold signal and a lower threshold signal.

10. 10. The electronic oscillator system of claim 9, wherein the calibration circuit further comprises: a first comparator for comparing the trim voltage with the upper threshold signal; a second comparator for comparing the trim voltage with the lower threshold signal; a counter controlled based on an output of the first comparator and an output of the second comparator; and an integrator configured to integrate an output of the comparator.

11. 10. The electronic oscillator system of claim 1 further comprising an external temperature sensor, the calibration circuitry operating based on temperature data received from the external temperature sensor.

12. 2. The electronic oscillator system of claim 1, wherein the second varactor provides a higher frequency vs. voltage gain than the first varactor.

13. 1. A method of electronic oscillator control, comprising: adjusting an oscillation frequency of a controllable oscillator using a first varactor, the controllable oscillator being external to a semiconductor die; adjusting the oscillation frequency of the controllable oscillator using a second varactor; controlling the first varactor to provide fine tuning to the controllable oscillator using a phase-locked loop (PLL) on the semiconductor die; and controlling the second varactor to provide a coarse adjustment to the controllable oscillator using a calibration circuit of the semiconductor die.

14. 14. The method of claim 13, further comprising: outputting a coarse control voltage from a coarse voltage pin of the semiconductor die; and scaling the coarse control voltage using an amplifier to generate a varactor control voltage for the second varactor.

15. 15. The method of claim 14, further comprising operating the semiconductor die in one of a first mode in which a calibration DAC sets a voltage level of the coarse voltage pin or a second mode in which a calibration charge pump sets the voltage level of the coarse control voltage.

16. 14. The method of claim 13, further comprising: receiving digital data from the calibration circuit as an input to a digital-to-analog converter (DAC); and providing a coarse control voltage from an output of the DAC to a coarse voltage pin of the semiconductor die.

17. 14. The method of claim 13, further comprising comparing the tuning voltage set by the PLL to an upper threshold signal and a lower threshold signal.

18. 1. A radio frequency communication system comprising: a mixer controlled by an oscillator signal; A local oscillator, Semiconductor die, a controllable oscillator external to the semiconductor die and configured to output the oscillator signal; a first varactor configured to adjust the oscillation frequency of the controllable oscillator; and a local oscillator comprising a second varactor configured to adjust the oscillation frequency of the controllable oscillator; 1. A radio frequency communication system, comprising: a phase-locked loop (PLL) configured to provide a fine adjustment to the controllable oscillator by controlling the first varactor; and a calibration circuit configured to provide a coarse adjustment to the controllable oscillator by controlling the second varactor.

19. 20. The radio frequency communication system of claim 18, wherein the calibration circuit is configured to compare a tuning voltage set by the PLL to an upper threshold signal and a lower threshold signal.

20. 20. The radio frequency communication system of claim 18, wherein the second varactor provides a higher voltage vs. frequency gain than the first varactor.

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