Light detection device, detection device, and detection device control method

Abstract

To provide a light detection device that may simplify a structure of a wiring for applying a bias voltage to each avalanche photodiode and a wiring for reading out signals from each cell.SOLUTION: Each of a plurality of cells includes at least one avalanche photodiode that operates in a Geiger mode. A light projection unit projects light having a cross-sectional shape where a first direction is a longer direction toward a detection target region. The light projection unit scans light along a second direction crossing the first direction so that reflected light enters for one or a plurality of cell groups among N cell groups each of which includes M cells arranged in a column direction. A control unit applies, in response to incidence of the reflected light, a bias voltage to operate the avalanche photodiode in the Geiger mode for one or the plurality of cell groups, and reads out signals from the cells included in the one or plurality of cell groups to which the bias voltage is applied.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a photodetection device, a semiconductor photodetection element, and a method for driving a semiconductor photodetection element. [Background technology]

[0002] There is known a photodetection device having a light receiving unit having a semiconductor substrate (see, for example, Patent Document 1). The semiconductor substrate includes a plurality of cells arranged two-dimensionally. This photodetection device stores a depth map of a three-dimensional image detected by using distance information obtained from the propagation time of light. Each cell includes an avalanche photodiode that operates in Geiger mode. The light receiving unit receives reflected light of light irradiated from a light source toward a monitoring area. The light receiving unit outputs a signal corresponding to the reflected light. The avalanche photodiode operates in Geiger mode by application of a bias voltage. Therefore, each cell of the light receiving unit outputs a signal by the avalanche photodiode operating in Geiger mode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-59301 A Summary of the Invention [Problem to be solved by the invention]

[0004] One aspect of the present invention aims to provide a photodetector device in which the configurations of wiring for applying a bias voltage to each avalanche photodiode and wiring for reading out a signal from each cell can be simplified.Another aspect of the present invention aims to provide a semiconductor photodetector element in which the configurations of wiring for applying a bias voltage to each avalanche photodiode and wiring for reading out a signal from each cell can be simplified.Yet another aspect of the present invention aims to provide a method for driving a semiconductor photodetector element in which the configurations of wiring for applying a bias voltage to each avalanche photodiode and wiring for reading out a signal from each cell can be simplified. [Means for solving the problem]

[0005] A light detection device according to one aspect of the present invention includes a light projecting unit that projects light having a cross-sectional shape whose longitudinal direction is a first direction toward a detection target area, a light receiving unit that receives reflected light of the light projected by the light projecting unit, and a control unit connected to the light receiving unit. The light receiving unit has a semiconductor substrate including a plurality of cells that are two-dimensionally arranged in M ​​rows and N columns (M and N are integers of 2 or more). Each of the plurality of cells includes at least one avalanche photodiode that operates in Geiger mode. For each of N first cell groups each including M cells arranged in the column direction, one of the anodes and the cathodes of the plurality of cells included in each first cell group is electrically connected to each other. For each of M second cell groups each including N cells arranged in the row direction, the other of the anodes and the cathodes of the plurality of cells included in each second cell group is electrically connected to each other. The light projecting unit scans light along a second direction intersecting with the first direction so that reflected light is incident on each of one or more first cell groups. The control unit applies a bias voltage for operating the avalanche photodiode in the Geiger mode to each of the one or more first cell groups in response to the incidence of the reflected light. The control unit reads out signals from cells included in the one or more first cell groups to which the bias voltage for operating the avalanche photodiode in the Geiger mode has been applied.

[0006] In the one aspect, the light projecting unit scans the light having a cross-sectional shape in which the first direction is the longitudinal direction in the second direction, so that the reflected light is incident on the light receiving unit for each of one or more first cell groups. The control unit applies a bias voltage to each of one or more first cell groups in response to the incidence of the reflected light. Therefore, for example, a wiring for applying a bias voltage to a cell may be provided corresponding to each first cell group, and may be electrically connected to an avalanche photodiode in each cell included in the corresponding first cell group. The control unit reads out a signal from a cell included in one or more first cell groups to which a bias voltage is applied. Therefore, for example, a wiring for reading out a signal from a cell may be provided corresponding to each M cell groups each including N cells arranged in the row direction, and may be electrically connected to an avalanche photodiode in each cell included in the corresponding cell group among the M cell groups. As a result, in the one aspect, it is possible to simplify the configuration of the wiring for applying a bias voltage to each avalanche photodiode and the wiring for reading out a signal from each cell.

[0007] In one aspect, the light projecting unit may scan light along the second direction so that reflected light is incident on each of the first cell groups. In this case, the reflected light is incident on the light receiving unit for each of the first cell groups. The control unit may apply a bias voltage for operating the avalanche photodiode in Geiger mode to each of the first cell groups in response to the incidence of the reflected light, and read out signals from M cells included in the first cell group to which the bias voltage for operating the avalanche photodiode in Geiger mode has been applied. In this configuration, as in the above configuration, for example, the wiring for applying a bias voltage to the cells may be provided for each first cell group, and may be electrically connected to the avalanche photodiode in each cell included in the corresponding first cell group. For example, the wiring for reading out a signal from the cell may be provided for each M cell groups each including N cells arranged in the row direction, and may be electrically connected to the avalanche photodiode in each cell included in the corresponding one of the M cell groups. As a result, in this configuration, the configuration of the wiring for applying a bias voltage to each avalanche photodiode and the wiring for reading out a signal from each cell can be simplified.

[0008] In one of the above aspects, the photodetector may include a plurality of first wirings and a plurality of second wirings. In this case, the plurality of first wirings are provided corresponding to each of the first cell groups. The plurality of second wirings are provided corresponding to each of the second cell groups. Each of the first wirings may be electrically connected to one of the anodes and cathodes of M cells included in the corresponding first cell group among the N first cell groups. Each of the second wirings may be electrically connected to the other of the anodes and cathodes of N cells included in the corresponding second cell group among the M second cell groups. The control unit may apply a bias voltage to the M cells included in the corresponding first cell group via each of the first wirings, and may read out a signal via each of the second wirings. In this configuration, a bias voltage is applied to the avalanche photodiode in each cell included in the corresponding first cell group among the N first cell groups through each first wiring. A signal is read out from the avalanche photodiode in each cell included in the corresponding second cell group among the M second cell groups through each second wiring. Therefore, this configuration simplifies the configuration of the first and second wirings. Avalanche photodiodes perform avalanche multiplication when a bias voltage is applied. As a result, photoelectrons generated by the incidence of light are multiplied, and the avalanche photodiode outputs a signal based on the multiplied photoelectrons. Even in avalanche photodiodes to which no bias voltage is applied, photoelectrons are generated by the incidence of light. The signal output from an avalanche photodiode to which no bias voltage is applied is extremely small compared to the signal output from an avalanche photodiode to which a bias voltage is applied. In this configuration, not only the cells to which the bias voltage is applied, but also the cells to which the bias voltage is not applied are electrically connected to the second wiring. Therefore, the control unit reads out signals from the cells to which the bias voltage is not applied. As described above, the signal output from the avalanche photodiode in the cell to which the bias voltage is not applied is extremely small, so the influence of the signal on the entire signal read out via the second wiring is extremely small. Therefore, the detection accuracy of the photodetector is ensured.

[0009] In one embodiment, each of the first wirings may include a first branch wiring and a second branch wiring. In this case, the first branch wiring is electrically connected to one of the anodes and cathodes of some of the cells included in the corresponding first cell group. The second branch wiring is electrically connected to one of the anodes and cathodes of another part of the cells included in the corresponding first cell group. For example, when all the cells in the first cell group are electrically connected to one first wiring, the difference between the wiring distance to the cell at one end in the column direction and the wiring distance to the cell at the other end in the column direction is large, and when the difference in the wiring distance to the cells is large, the difference in the timing at which the bias voltage is applied to the cells also becomes large. In this configuration, the difference in wiring distance to the cells is smaller than when all the cells in the first cell group are electrically connected to one first wiring, and therefore the difference in timing at which the bias voltage is applied to the cells is smaller.

[0010] In one embodiment, each of the second wirings may include a third branch wiring and a fourth branch wiring. In this case, the third branch wiring is electrically connected to the other of the anodes and cathodes of some of the cells included in the corresponding second cell group. The fourth branch wiring is electrically connected to the other of the anodes and cathodes of another part of the cells included in the corresponding second cell group. For example, when all the cells in the second cell group are electrically connected to one second wiring, the difference between the wiring distance from the cell located at one end in the row direction and the wiring distance from the cell located at the other end in the row direction is large. If the wiring distance from the cell is long, there is a risk that noise will be included in the signal read out through the second wiring due to the influence of parasitic capacitance generated in the second wiring. In this configuration, the wiring distance from the cell is shorter than when all the cells in the second cell group are electrically connected to one second wiring. Therefore, the signal read out through the second wiring is less likely to contain noise. As a result, the deterioration of the detection accuracy of the photodetector is suppressed.

[0011] In the above aspect, the photodetector may further include a circuit board having a control unit. Each of the plurality of cells may be electrically connected to the circuit board. The plurality of first wirings and the plurality of second wirings may be provided on the circuit board. In this configuration, a plurality of first wirings provided for each of the first cell groups and a plurality of second wirings provided for each of the second cell groups are provided on the circuit board. Therefore, in this configuration, compared to a case where the first wirings and the second wirings are arranged on a semiconductor substrate, for example, a member for protecting the first wirings and the second wirings is not required. As a result, the configuration of the photodetector can be simplified.

[0012] In the above aspect, a trench may be formed in the semiconductor substrate so as to separate adjacent first cell groups from each other. In this configuration, adjacent first cell groups are electrically isolated by the trenches. Therefore, even if a bias voltage is applied to a cell in one first cell group, the bias voltage is unlikely to be applied to cells in the first cell group adjacent to the first cell group in the row direction. As a result, the first cell groups adjacent in the row direction are unlikely to perform avalanche multiplication.

[0013] In the above aspect, the semiconductor substrate may include a first main surface and a second main surface opposed to each other. The semiconductor substrate may have trenches formed therein that open to the first main surface and the second main surface. The trenches may surround each of the plurality of cells when viewed from a direction perpendicular to the first main surface. In this configuration, each cell is electrically isolated by a trench. Therefore, electrical crosstalk between signals generated in adjacent cells among the M cells included in the first cell group to which a bias voltage is applied is suppressed. As a result, the detection accuracy of the photodetector is ensured.

[0014] A semiconductor photodetector element according to another aspect of the present invention includes a semiconductor substrate, a plurality of first wirings, and a plurality of second wirings. The semiconductor substrate includes a plurality of cells arranged two-dimensionally in M ​​rows and N columns (M and N are integers of 2 or more). The plurality of first wirings are provided corresponding to N first cell groups each including M cells arranged in the column direction. The plurality of second wirings are provided corresponding to M second cell groups each including N cells arranged in the row direction. Each of the plurality of cells includes at least one avalanche photodiode operating in Geiger mode. Each of the first wirings is electrically connected to one of the anodes and cathodes of M cells included in the corresponding first cell group among the N first cell groups. Each of the second wirings is electrically connected to the other of the anodes and cathodes of N cells included in the corresponding second cell group among the M second cell groups.

[0015] In the above-mentioned another aspect, for example, for each of the N first cell groups, a bias voltage is applied to the avalanche photodiode in each cell included in the corresponding first cell group via each first wiring. For example, for each of the M second cell groups, a signal is read out from the avalanche photodiode in each cell included in the corresponding second cell group via each second wiring. Therefore, the above-mentioned another aspect can simplify the configuration of the first and second wirings. When a signal is read out through the second wiring, as described above, not only the cell to which the bias voltage is applied, but also the cell to which the bias voltage is not applied is electrically connected to the second wiring. Therefore, a signal is read out from the cell to which the bias voltage is not applied. As described above, the signal output from the avalanche photodiode in the cell to which the bias voltage is not applied is extremely small, so that the influence of the signal on the entire signal read out through the second wiring is extremely small. Therefore, the detection accuracy of the semiconductor photodetector element is ensured.

[0016] In the above-mentioned another aspect, each of the first wirings may include a first branch wiring and a second branch wiring. In this case, the first branch wiring is electrically connected to one of the anodes and the cathodes of some of the cells included in the corresponding first cell group. The second branch wiring is electrically connected to one of the anodes and the cathodes of another part of the cells included in the corresponding first cell group. In this configuration, as described above, the difference in wiring distance to the cells is smaller than when all the cells in the first cell group are electrically connected to one first wiring, and therefore the difference in timing at which the bias voltage is applied to the cells is smaller.

[0017] In the above-mentioned another aspect, each second wiring may include a third branch wiring and a fourth branch wiring. In this case, the third branch wiring is electrically connected to the other of the anodes and cathodes of some cells included in the corresponding second cell group. The fourth branch wiring is electrically connected to the other of the anodes and cathodes of another part of cells included in the corresponding second cell group. In this configuration, as described above, the wiring distance from the cell is shorter than when all the cells in the second cell group are electrically connected to one second wiring. Therefore, the signal read out through the second wiring is less likely to contain noise. As a result, the deterioration of the detection accuracy of the photodetector is suppressed.

[0018] In the above-mentioned another aspect, a trench may be formed in the semiconductor substrate so as to separate adjacent first cell groups from each other. In this configuration, as described above, the first cell group adjacent in the row direction to the first cell group to which the bias voltage is applied is unlikely to undergo avalanche multiplication.

[0019] In the above-mentioned another aspect, the semiconductor substrate may include a first main surface and a second main surface opposed to each other. The semiconductor substrate may have a trench formed therein, the trench opening to the first main surface and the second main surface. The trench may surround each of the plurality of cells when viewed from a direction perpendicular to the first main surface. As described above, this configuration ensures the detection accuracy of the semiconductor light detecting element.

[0020] A method for driving a semiconductor photodetector element according to yet another embodiment of the present invention applies a bias voltage to each of N first cell groups at different timings via corresponding first wirings among a plurality of first wirings, and operates avalanche photodiodes included in M ​​cells of the first cell group to which the bias voltage has been applied in Geiger mode. As described above, this driving method simplifies the configuration of the first and second wirings. Effect of the Invention

[0021] One aspect of the present invention provides a photodetector device in which the configuration of wiring for applying a bias voltage to each avalanche photodiode and the configuration of wiring for reading out a signal from each cell can be simplified.Another aspect of the present invention provides a semiconductor photodetector element in which the configuration of wiring for applying a bias voltage to each avalanche photodiode and the configuration of wiring for reading out a signal from each cell can be simplified.Yet another aspect of the present invention provides a method for driving a semiconductor photodetector element in which the configuration of wiring for applying a bias voltage to each avalanche photodiode and the configuration of wiring for reading out a signal from each cell can be simplified. [Brief description of the drawings]

[0022] [Figure 1] FIG. 1 is a schematic diagram of a photodetector according to the first embodiment. [Diagram 2] FIG. 2 is a schematic diagram of a light receiving unit included in the light detection device. [Diagram 3] FIG. 3 is a schematic plan view of the semiconductor photodetector element. [Figure 4] FIG. 4 is a schematic diagram showing a cross-sectional configuration of the light receiving unit. [Diagram 5] FIG. 5 is a schematic diagram showing a cross-sectional configuration of the light receiving unit. [Figure 6] FIG. 6 is a diagram illustrating an example of a circuit of the readout unit. [Figure 7] FIG. 7 is a timing chart of various signals in the photodetector. [Figure 8] FIG. 8 is a schematic plan view of a semiconductor photodetector according to a modified example. [Figure 9] FIG. 9 is a perspective view of a light receiving unit included in a light detection device according to the second embodiment. [Figure 10] FIG. 10 is a schematic plan view of the semiconductor photodetector element. [Figure 11] FIG. 11 is a schematic diagram showing a cross-sectional configuration of the light receiving unit. [Figure 12] FIG. 12 is a schematic diagram showing a cross-sectional configuration of the light receiving unit. [Figure 13] FIG. 13 is a perspective view showing an example of a wiring configuration of a semiconductor photodetector element. [Figure 14] FIG. 14 is a diagram showing a cross-sectional structure of a semiconductor photodetector element. [Figure 15] FIG. 15 is a schematic plan view of a semiconductor photodetector according to a modified example. [Figure 16] FIG. 16 is a schematic plan view of a semiconductor photodetector element included in the photodetector according to the third embodiment. [Figure 17] FIG. 17 is a schematic diagram showing a cross-sectional configuration of the light receiving unit. [Figure 18] FIG. 18 is a schematic diagram showing a cross-sectional configuration of the light receiving unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same elements or elements having the same functions will be denoted by the same reference numerals, and duplicated description will be omitted.

[0024] First, the photodetector according to the first embodiment will be described with reference to Fig. 1. Fig. 1 is a schematic diagram of the photodetector according to the first embodiment.

[0025] As shown in FIG. 1, the light detection device 1 includes a light projection unit 2, a lens 3, and a light receiving unit 4. The light projection unit 2 is a device that projects laser light. The light projection unit 2 is disposed at a position where it can project laser light toward a detection target area S. The light receiving unit 4 is a device that receives reflected light of the laser light. The light receiving unit 4 is disposed at a position where it can receive the reflected light. For example, when an object is present in the detection target area S, the laser light projected from the light projection unit 2 is reflected by the object. The laser light reflected by the object, i.e., the reflected light, enters the light receiving unit 4. The detection target area S is arbitrarily set in advance, and is rectangular in this embodiment. The light detection device 1 constitutes, for example, a LiDAR (Light Detection and Ranging). The light projection unit 2 constitutes, for example, a light projection section.

[0026] The light projection unit 2 includes a plurality of laser light sources 5 and a mirror 6. The laser light source 5 generates laser light. The laser light source 5 emits the generated laser light toward the mirror 6. For example, each of the lights emitted from the plurality of laser light sources 5 is collimated (adjusted to travel parallel to each other) and enters the mirror 6. The mirror 6 reflects the plurality of laser lights emitted by the plurality of laser light sources 5 toward the detection target area S. The light reflected by the mirror 6 and projected toward the detection target area S has, for example, an elliptical or oval shape in a plane perpendicular to the projection direction. The light projection unit 2 projects laser light having a cross-sectional shape in which the direction D1 is the longitudinal direction and the direction D2 is the transverse direction toward the detection target area S. In other words, in the cross-sectional shape of the laser light, the direction D1 is the major axis direction of the ellipse or oval, and the direction D2 is the minor axis direction of the ellipse or oval. The cross-sectional shape of the laser light may be a linear shape along the direction D1. The mirror 6 constitutes a scanning section that scans the laser light in the light projection unit 2, and is, for example, a galvanometer mirror or a MEMS mirror. For example, the scanning section in the light projection unit 2 may be constituted by a mechanism that changes the projection direction (projection position) of the laser light, other than the mirror 6.

[0027] In this embodiment, as shown in FIG. 1, the light projection unit 2 projects laser light toward each of the light projection positions P1 to PN included in the detection target area S in order from the light projection position P1 to the light projection position PN. N is an integer of 2 or more. By projecting the laser light from the light projection position P1 to the light projection position PN in order, the light projection unit 2 scans the laser light along the direction D2. For example, the laser light projected toward one of the light projection positions P1 to PN is generated by a plurality of laser light sources 5. The laser light projected toward one of the light projection positions P1 to PN may be generated by a single laser light source 5. In this case, the laser light projected toward one of the light projection positions may be emitted at different timings in order from the end along the direction D1 at the light projection position by controlling the angle of the mirror 6. For example, when the direction D1 is a first direction, the direction D2 is a second direction.

[0028] The light-projecting unit 2 includes a control unit (not shown). The control unit of the light-projecting unit 2 controls the projection position of the laser light projected from the light-projecting unit 2, for example, by driving and controlling the mirror 6. The control unit of the light-projecting unit 2 transmits, to the control unit 13 of the light-receiving unit 4, position information indicating one of the light-projection positions P1 to PN and time information indicating the time to start projection.

[0029] The reflected light reflected in the detection target area S is incident on the lens 3. The lens 3 collects the incident reflected light so that the reflected light is incident on the light receiving unit 4. The light receiving unit 4 outputs a plurality of light receiving signals according to the reflected light incident via the lens 3. The configuration and function of the light receiving unit 4 will be described later. For example, the light detecting device 1 measures the distance from the light detecting device 1 to a portion of the object present in each of the divided areas obtained by dividing the detection target area S into a plurality of areas based on the plurality of light receiving signals. In this case, the projection positions P1 to PN of the laser light projected from the light projecting unit 2 are set according to the positions of the divided areas.

[0030] Next, the configuration of the light receiving unit 4 will be described with reference to Figs. 2 to 6. Fig. 2 is a schematic diagram of a light receiving unit provided in a light detection device. Fig. 3 is a schematic plan view of a semiconductor light detection element. Fig. 4 is a schematic diagram showing a cross-sectional configuration of the light receiving unit. Fig. 5 is a schematic diagram showing a cross-sectional configuration of the light receiving unit. Fig. 6 is a diagram showing an example of a circuit of a readout section.

[0031] As shown in FIG. 2, the light receiving unit 4 includes a semiconductor light detecting element 11, a mounting substrate 12, and a control unit 13. The control unit 13 is connected to the semiconductor light detecting element 11. The control unit 13 includes a switching unit 14 and a readout unit 15. The semiconductor light detecting element 11 includes a semiconductor substrate 20. The semiconductor substrate 20 and the mounting substrate 12 are disposed opposite to each other. In this embodiment, the semiconductor substrate 20 is provided on the mounting substrate 12. Both the semiconductor substrate 20 and the mounting substrate 12 have a rectangular shape in a plan view. The semiconductor light detecting element 11, for example, constitutes a light receiving unit. The semiconductor light detecting element 11 is, for example, a front-illuminated semiconductor light detecting element.

[0032] The semiconductor substrate 20 has mutually opposing main surfaces 20A and 20B, and a side surface 20C (see FIG. 4). The mounting substrate 12 has mutually opposing main surfaces 12A and 12B, and a side surface 12C (see FIG. 4). The main surface 20B of the semiconductor substrate 20 faces the main surface 12A of the mounting substrate 12. Here, the main surface 20B is in contact with the main surface 12A. The main surface 20A is a light incidence surface to the semiconductor light detecting element 11. In this embodiment, a plane parallel to each main surface of the semiconductor substrate 20 and the mounting substrate 12 is an XY-axis plane, and a direction perpendicular to each main surface is a Z-axis direction. For example, when the main surface 20A constitutes a first main surface, the main surface 20B constitutes a second main surface.

[0033] As shown in FIG. 3, the semiconductor substrate 20 has a plurality of cells U two-dimensionally arranged in M ​​rows and N columns in a plan view. M and N are each an integer of 2 or more. In the semiconductor substrate 20, a signal corresponding to the reflected light detected in each cell U is output from each cell U. For example, a current signal corresponding to the reflected light is output from each cell U. As an example, the number of cells U is "1024 (32 rows x 32 columns)". Each of the plurality of cells U includes one or more avalanche photodiodes APD. The avalanche photodiode APD operates in Geiger mode by applying a bias voltage. The bias voltage applied to the avalanche photodiode APD is equal to or higher than the breakdown voltage. When the reflected light is incident on the avalanche photodiode APD operating in Geiger mode, the avalanche photodiode APD generates a current signal corresponding to the reflected light. In the semiconductor substrate 20, a light receiving region A is formed, which is a region in which the plurality of cells U arranged two-dimensionally are located. In other words, the outer edge of the light-receiving region A surrounds all of the cells U when viewed from the Z-axis direction. In the light-detecting device 1, the positions of the lens 3 and the light-receiving unit 4 or the optical function of the lens 3 are adjusted so that the reflected light is incident on the light-receiving region A.

[0034] As shown in FIG. 4 and FIG. 5, a trench 21 is formed in the semiconductor substrate 20. The trench 21 opens to the main surface 20A and the main surface 20B. In other words, the trench 21 penetrates the semiconductor substrate 20 in a direction (Z-axis direction) in which the main surface 20A and the main surface 20B face each other. The Z-axis direction is also the thickness direction of the semiconductor substrate 20. The trench 21 separates adjacent cells U from among the plurality of cells U. Specifically, the trench 21 surrounds each of the plurality of cells U when viewed from a direction (Z-axis direction) perpendicular to the main surface 20A. The trench 21 physically separates adjacent cell groups from among the cell groups in the first to N columns described below, and physically separates adjacent cell groups from among the cell groups in the first to M rows described below. In other words, the trench 21 electrically separates adjacent cell groups among the cell groups in the first to N columns, and electrically separates adjacent cell groups among the cell groups in the first to M rows. The trench 21 does not need to surround the entire periphery of a cell U that is adjacent to the outer edge of the light receiving region A in the XY-axis plane among the multiple cells U. In a cell U adjacent to the outer edge of the light receiving region A, the trench 21 may be formed only between the cell U adjacent to the outer edge of the light receiving region A and another cell U located inside the cell U and adjacent to the cell U. A light shielding member that blocks light may be provided in the trench 21. The light shielding member may be covered with an insulating film. In this case, the light shielding member optically separates adjacent cells U.

[0035] The semiconductor light detecting element 11 further includes a plurality of wirings H1 to HN and a plurality of wirings R1 to RM. The plurality of wirings H1 to HN are provided corresponding to the first to N columns of cell groups included in the plurality of cells U, one for each column. The plurality of wirings R1 to RM are provided corresponding to the first to M rows of cell groups included in the plurality of cells U, one for each row. The nth column of the first to N columns of cell groups is composed of a plurality of cells U (M cells U) located in the nth column counting from the negative direction in the X-axis direction. Except when expressing the conductivity type of the semiconductor region, n represents an integer from 1 to N. The nth column of cell groups includes the first to M rows of cells U located in the nth column and aligned in the column direction. The mth row of the first to M rows of cell groups is composed of a plurality of cells U (N cells U) located in the mth row counting from the negative direction in the Y-axis direction. m is an integer from 1 to M. The cell group in the mth row includes cells U in columns 1 to N that are located in the mth row and aligned in the row direction. In this embodiment, the column direction is the X-axis direction, and the row direction is the Y-axis direction. For example, the cell group in columns 1 to N constitutes N first cell groups, and the cell group in rows 1 to M constitutes M second cell groups.

[0036] Among the multiple wirings H1 to HN, the wiring Hn located at the nth position counting from the negative direction of the X-axis direction is provided corresponding to the cell group in the nth column. The wiring Hn is electrically connected to the avalanche photodiodes APD included in the cell group in the nth column. That is, the wiring Hn is electrically connected to the cells U in the 1st to Mth rows located in the nth column. The wiring Hn is electrically connected to the semiconductor region constituting the avalanche photodiode APD. For example, the wiring Hn is electrically connected to a semiconductor region whose conductivity type is p-type. In the light receiving unit 4, a bias voltage is applied to each avalanche photodiode APD via the wiring Hn to operate each avalanche photodiode APD in Geiger mode.

[0037] The semiconductor light detecting element 11 has a plurality of pad electrodes 22 (N pad electrodes 22). The plurality of pad electrodes 22 are provided outside the light receiving region A in the XY-axis plane of the semiconductor substrate 20. The plurality of pad electrodes 22 are provided corresponding to the first to Nth columns of cell groups. Each of the wirings H1 to HN is electrically connected to the pad electrodes 22.

[0038] Among the multiple wirings R1 to RM, the wiring Rm located at the mth position counting from the negative Y-axis direction is provided corresponding to the cell group in the mth row. The wiring Rm is electrically connected to the avalanche photodiode APD included in the cell group in the mth row. The wiring Rm is electrically connected to a semiconductor region constituting the avalanche photodiode APD. For example, the wiring Rm is electrically connected to a semiconductor region whose conductivity type is n-type. In the light receiving unit 4, a signal generated in each avalanche photodiode APD is read out via the wiring Rm.

[0039] The semiconductor light detecting element 11 has a plurality of pad electrodes 23 (M pad electrodes 23). The plurality of pad electrodes 23 are provided outside the light receiving region A in the XY-axis plane of the semiconductor substrate 20. The plurality of pad electrodes 23 are provided corresponding to the 1st to Mth rows of cell groups. Each of the wirings R1 to RM is electrically connected to the pad electrodes 23.

[0040] The switching unit 14 and the readout unit 15 constitute the control unit 13 that controls the semiconductor photodetector element 11. The switching unit 14 and the readout unit 15 are provided on the mounting substrate 12. The switching unit 14 and the readout unit 15 are, for example, constituted by hardware. This hardware includes, for example, a register, a memory, a comparator, an arithmetic unit, a multiplexer, a selector, an A / D converter, and a power supply control circuit. The register is, for example, constituted by a logic circuit. The logic circuit includes, for example, an AND gate, an OR gate, a NOT gate, and an XOR gate. A part or the whole of the switching unit 14 and the readout unit 15 may be constituted by an integrated circuit. This integrated circuit includes, for example, an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array).

[0041] The wirings H1 to HN are electrically connected to the switching unit 14. Specifically, as shown in Fig. 4, the wirings Hn are electrically connected to the switching unit 14 via the pad electrodes 22, the bonding wires 24, and the wirings 25 on the mounting substrate 12. Although one bonding wire 24 and one wiring 25 are shown in Fig. 4, a plurality of bonding wires 24 and a plurality of wirings 25 are provided for electrically connecting the wirings H1 to HN to the switching unit 14, respectively. The switching unit 14 applies a bias voltage to the cell groups of the 1st to Nth columns for each column via the wirings H1 to HN.

[0042] The wirings R1 to RM are each electrically connected to the readout unit 15. Specifically, as shown in Fig. 5, the wiring Rm is electrically connected to the readout unit 15 via the pad electrode 23, the bonding wire 26, a wiring 27 in the mounting substrate 12, and a bonding wire 28. Although one bonding wire 26, 28 and one wiring 27 are shown in Fig. 5, a plurality of bonding wires 26, 28 and a plurality of wirings 27 are provided to electrically connect the wirings R1 to RM to the readout unit 15, respectively.

[0043] As shown in FIG. 6, the readout unit 15 includes a resistor 31, a readout circuit 32, and a signal processing unit 33. Each of the wirings R1 to RM includes a quenching resistor 34. One or more avalanche photodiodes APD included in each of the cells U in the first to nth columns constituting the mth row of the cell group are electrically connected to one end of the resistor 31 via the wiring Rm. The avalanche photodiode APD is electrically connected to one end of the resistor 31 via the quenching resistor 34. The other end of the resistor 31 is connected to a GND (ground) potential. And, one end of the resistor 31 is electrically connected to the readout circuit 32. As a result, the voltage drop across the resistor 31 is input to the readout circuit 32.

[0044] The readout circuit 32 includes a D / A converter (digital-analog conversion circuit) 35, a comparator 36, and a time counter 37. The comparator 36 compares a reference voltage generated by the D / A converter 35 with a voltage drop in the resistor 31. When the voltage drop in the resistor 31 exceeds the reference voltage, the comparator 36 outputs a signal to the time counter 37. For example, when reflected light is incident on one cell U of the cell group in the m-th row and an output current (pulse) flows from the cell U to the resistor 31, the resistance value of the resistor 31 is set so that the voltage drop in the resistor 31 exceeds the reference voltage. The time counter 37 calculates the projection time of the laser light based on the time when the signal from the comparator 36 is input. For example, information indicating the time when the laser light is projected is input from the control unit of the light projection unit 2 to the time counter 37.

[0045] The time measuring device 37 outputs time information indicating the calculated projection time of the laser light to the signal processing unit 33. When it is not necessary to measure the projection time of the laser light depending on the application of the light detection device 1, the readout circuit 32 may measure, for example, the amount of incident light. In this manner, the readout unit 15 of the control unit 13 reads out a signal according to the reflected light. Although a single readout circuit 32 is shown in FIG. 6, M readout circuits 32 are provided in the readout unit 15 corresponding to each of the 1st to Mth rows of the cell group. Each of the M readout circuits 32 outputs a signal to the signal processing unit 33. The signal processing unit 33 (light receiving unit 4) outputs, for example, a light receiving signal based on the signal output by the readout circuit 32.

[0046] Next, the operation of the photodetector 1 will be described with reference to FIG. 7. FIG. 7 is a timing chart of various signals in the photodetector. FIG. 7 shows the control timing by the light projecting unit 2 and the light receiving unit 4 in periods t1 to tN. The waveforms shown by "HV_1" to "HV_N" show the timing at which bias voltages are applied by the switching unit 14, and correspond to the bias voltages applied to the cell groups in the 1st to Nth columns, respectively. The waveforms shown by "OUTPUT_1" to "OUTPUT_M" show the voltage signals generated in the resistor 31, and correspond to the signals from the cell groups in the 1st to Mth rows, respectively.

[0047] In a period t1, the control unit of the light-projecting unit 2 causes the light-projecting unit 2 to project a laser beam toward the light-projecting position P1 at a predetermined timing. In FIG. 7, the pulse width of the waveform indicated by "laser beam" indicates the time during which the laser beam is projected. The switching unit 14 of the light-receiving unit 4 starts applying a bias voltage to the cell group in the first column via the wiring H1 before the start time of projection of the laser beam toward the light-projecting position P1. The switching unit 14 continues to apply the bias voltage to the cell group in the first column until a predetermined time has elapsed from the end time of projection of the laser beam toward the light-projecting position P1. While the bias voltage is being applied to the cell group in the first column, the avalanche photodiode APD included in the cell group in the first column operates in Geiger mode. In other words, when reflected light is incident on the cell group in the first column while the bias voltage is being applied to the cell group in the first column, a current signal according to the reflected light is generated in each of the avalanche photodiodes APD in the cells U in the 1st to Mth rows of the cell group in the first column.

[0048] The switching unit 14 receives information indicating the light projection position and the light projection time (light projection start time and light projection end time) from the control unit of the light projection unit 2, and applies a bias voltage to the cell group in the first column in accordance with the incidence timing of the reflected light incident on the cell group in the first column. When a current signal corresponding to the reflected light is generated in each of the cells U in the first to M rows of the cell group in the first column, the current signal flows through the above-mentioned resistor 31 via the wirings R1 to RM. Then, the current signal is converted into a voltage signal, and each voltage signal is output to the readout circuit 32. Then, the readout unit 15 of the control unit 13 reads out a signal corresponding to the reflected light incident on the cells U in the first to M rows of the cell group in the first column. Each of the waveforms indicated by "OUTPUT_1" to "OUTPUT_M" is represented by a rectangular pulse. The voltage signal generated in the resistor 31 may be a pulse that increases rapidly in the initial stage and then decreases gradually, as shown in the enlarged view included in FIG. 7.

[0049] When the detection of the reflected light of the laser light toward the light projection position P1 (signal reading) is completed, the control in the period t2 is started. In the period t2, the control unit of the light projection unit 2 causes the light projection unit 2 to project the laser light toward the light projection position P2 at a predetermined timing. The switching unit 14 starts applying a bias voltage to the cell group in the second column via the wiring H2 before the start time of projection of the laser light toward the light projection position P2. The switching unit 14 continues to apply the bias voltage to the cell group in the second column until a predetermined time has elapsed from the end time of projection of the laser light toward the light projection position P2. While the bias voltage is being applied to the cell group in the second column, the avalanche photodiode APD included in the cell group in the second column operates in the Geiger mode. In other words, when the reflected light is incident on the cell group in the second column while the bias voltage is being applied to the cell group in the second column, a current signal according to the reflected light is generated in each of the avalanche photodiodes APD in the cells U in the first to M rows of the cell group in the second column. The switching unit 14 applies a bias voltage to the cell group in the second row in accordance with the incidence timing of the reflected light that is incident on the cell group in the second row.

[0050] When a current signal corresponding to the reflected light is generated in each of the cells U in the first to M rows of the second column cell group, the current signal flows through the resistor 31 described above via the wirings R1 to RM. The current signal is then converted into a voltage signal, and the voltage signal is output to the readout circuit 32. Then, the readout section 15 of the light receiving unit 4 reads out a signal corresponding to the reflected light incident on the cells U in the first to M rows of the second column cell group. In the periods t1 and t2, different wirings H1 and H2 are used, and bias voltages are applied to the first column cell group and the second column cell group, respectively. On the other hand, in the periods t1 and t2, the wirings R1 to RM are used in common, and signals are read out from the cells U in the first to M rows included in the first column cell group and the second column cell group.

[0051] Thereafter, the control unit 14, the switching unit 14, and the readout unit 15 of the light projection unit 2 sequentially perform the same control as that in the periods t1 and t2 from period t3 to tN. The switching unit 14 applies a bias voltage to the cell groups located in different columns through any one of the wirings Hn among the wirings H1 to HN according to the projection position of the laser light. The readout unit 15 reads out signals according to the reflected light incident on the cells U in the first to M rows included in the cell group to which the bias voltage is applied through each of the wirings R1 to RM, regardless of the projection position of the laser light. In this way, in the method of driving the semiconductor light detection element 11 by the control unit 13, the bias voltage is applied to the cell groups in the first to N columns at different timings for each column. The switching unit 14 may start applying the bias voltage to the cell group in the nth column through the wiring Hn after a predetermined time has elapsed from the start time of projection of the laser light. For example, if a cover (transmission window) that is provided in the housing that houses the light detection device 1 and transmits the laser light is dirty, there is a risk that unintended reflected light from a very close distance will be incident on the light receiving unit 4. By starting the application of the bias voltage after a predetermined time has elapsed from the start of projection of the laser light, it is possible to prevent the above-mentioned unintended reflected light from being detected.

[0052] After the light-projecting unit 2 projects the laser light up to the light-projection position PN, the light-detecting device 1 may repeat scanning the laser light in the detection target area S and read out a signal corresponding to the reflected light. For example, the light-projecting unit 2 of the light-detecting device 1 may project the laser light up to the light-projection position PN, and then project the laser light again in sequence from the light-projection position P1 to the light-projection position PN, or may project the laser light in sequence from the light-projection position PN to the light-projection position P1.

[0053] As described above, in the light detection device 1, the light projection unit 2 scans the laser light having a cross-sectional shape in which the direction D1 is the longitudinal direction in the direction D2, so that the reflected light is incident on each of the cell groups in the first to N columns of the semiconductor light detection element 11. The control unit 13 applies a bias voltage to each of the cell groups in the first to N columns of the semiconductor light detection element 11 in response to the incidence of the reflected light. Therefore, the wiring for applying the bias voltage to the cell U only needs to be provided corresponding to each of the cell groups in the first to N columns of the semiconductor light detection element 11, and it only needs to be electrically connected to the avalanche photodiode APD in each of the cells U included in the corresponding cell group. The control unit 13 reads out signals from M cells U included in one of the cell groups in the first to N columns to which the bias voltage is applied. Therefore, the wiring for reading out signals from the cell U only needs to be provided corresponding to each of the M cell groups including N cells U arranged in the row direction, and it only needs to be electrically connected to the avalanche photodiode APD in each of the cells U included in the corresponding cell group among the M cell groups. As a result, in the photodetector 1 of this embodiment, the configuration of the wiring for applying a bias voltage to each avalanche photodiode APD and the wiring for reading out a signal from each cell U can be simplified.

[0054] As a configuration of a photodetector for reading out a signal from each cell of a semiconductor photodetector element, a configuration including wiring that simultaneously applies a bias voltage to all of the cells arranged on a semiconductor substrate is conceivable. In this configuration, a plurality of switches are provided on a plurality of readout wirings provided corresponding to each row of the cells. In a photodetector configured in this way, a plurality of switches are provided for each cell, and by switching the open / closed state of the switch, a specific cell and the readout wiring are made conductive, and a signal from the specific cell is read out. In contrast to a photodetector configured in this way, in the photodetector 1 of this embodiment, not only the cell U to which a bias voltage is applied, but also the cell U to which a bias voltage is not applied are electrically connected to the multiple wirings provided for readout. Therefore, the control unit 13 reads out a signal from the cell U to which a bias voltage is not applied. Since the signal output from the avalanche photodiode APD in the cell U to which a bias voltage is not applied is extremely small, the effect of the signal on the entire signal read out through the multiple wirings provided for readout is extremely small. Therefore, in order to read out a signal from a specific cell, it is not necessary to provide a switch in the wiring provided for readout. Therefore, compared to a case where a switch is provided on the readout wiring, in the photodetector 1, the influence of noise generated by the capacitance of the switch and the opening and closing operation of the switch on the signal read out from the readout wiring is reduced. The above-mentioned photodetector device, which includes wiring that simultaneously applies a bias voltage and a plurality of switches, may have the following problems. In a configuration in which a signal is read out from a specific cell by switching a switch from an open state to a closed state, if light (photons) is incident on a specific cell just before the switch is switched to a closed state, the signal read out from the specific cell may include a signal due to the light that was incident just before the switch was switched to a closed state. The signal due to the light that was incident just before the switch was switched to a closed state is an unnecessary output. In contrast, the signal due to the light that is incident after the switch is switched to a closed state is a necessary output. In the photodetector 1, even if light is incident on a cell with no bias voltage applied, the signal output from the cell is extremely small, so that unnecessary outputs are unlikely to be included in the signal read out from the cell.

[0055] In the photodetector 1, signals are output at approximately the same timing from M cells U included in the n-th column of cells to which a bias voltage is applied to operate in Geiger mode. Specifically, adjacent cells among the M cells U included in the n-th column of cells are separated by trenches 21, and signals can be read out from each of the M cells U by providing wiring corresponding to each row. Therefore, signals from each of the M cells U included in the n-th column of cells are output in parallel at approximately the same timing. As a result, signals corresponding to the reflected light incident on the light receiving section are read out at high speed. The cell group to be read is determined by applying a bias voltage in response to the incidence of the reflected light. As described above, the influence of the signal from the cell U to which no bias voltage is applied is extremely small, so even if the reflected light is incident on a cell group adjacent to the cell group to be read, the influence on the signal to be read is small. Therefore, it is not necessary to precisely match the range where the reflected light is incident to the cell group to be read, so that it is easy to adjust the cross-sectional shape of the laser light. For example, this is effective in cases where it is difficult to match the range where the reflected light is incident by optical adjustment alone.

[0056] In the photodetector 1, the control unit 13 applies a bias voltage to the avalanche photodiode APD in each cell U included in the corresponding cell group among the cell groups in the 1st to Nth columns via the wirings H1 to HN provided corresponding to each column of the cell groups in the 1st to Nth columns in response to the incidence of the reflected light. The control unit 13 reads out a signal from the avalanche photodiode APD in each cell U included in the corresponding cell group among the cell groups in the 1st to Mth rows via the wirings R1 to RM provided corresponding to each row of the cell groups in the 1st to Mth rows. Therefore, the photodetector 1 simplifies the configuration of the wirings H1 to HN and the wirings R1 to RM. Note that the above-mentioned Patent Document 1 does not disclose or suggest a specific configuration of the wirings that apply a bias voltage to each photodiode and the wirings that read out a signal. The avalanche photodiode APD performs avalanche multiplication by application of a bias voltage. Therefore, photoelectrons generated by the incidence of light are multiplied, and the avalanche photodiode APD outputs a signal (current signal) due to the multiplied photoelectrons. Even in an avalanche photodiode APD to which no bias voltage is applied, photoelectrons are generated by the incidence of light. The signal output from an avalanche photodiode APD to which no bias voltage is applied is extremely small compared to the signal output from an avalanche photodiode APD to which a bias voltage is applied. In the photodetector 1, not only the cells U to which a bias voltage is applied, but also the cells U to which no bias voltage is applied are electrically connected to the wirings R1 to RM. Therefore, the control unit 13 reads out signals from the cells U to which no bias voltage is applied. As described above, the signals output from the avalanche photodiodes APD in the cells U to which no bias voltage is applied are extremely small, so that the influence of these signals on the overall signals read out via the wirings R1 to RM is extremely small. Therefore, the detection accuracy of the photodetector 1 is ensured.

[0057] In the photodetector 1, adjacent cell groups among the cell groups in the 1st to Nth columns are electrically isolated by the trenches 21. Therefore, even if a bias voltage is applied to a cell U included in the cell group in the nth column, the bias voltage is unlikely to be applied to cells U included in the cell group in the (n-1)th column and the cell group in the (n+1)th column that are adjacent to the cell group in the nth column in the row direction. As a result, the cell group in the (n-1)th column and the cell group in the (n+1)th column that are adjacent to the cell group in the nth column in the row direction are unlikely to perform avalanche multiplication.

[0058] In the photodetector 1, each cell U is electrically isolated by a trench 21. Therefore, when a bias voltage is applied to M cells included in the nth cell group, electrical crosstalk occurring between signals generated in adjacent cells U among the M cells included in the nth cell group is suppressed. As a result, the detection accuracy of the photodetector 1 is ensured.

[0059] Next, a semiconductor photodetector 11A according to a modification of the photodetector 1 of this embodiment will be described. FIG. 8 is a schematic plan view of the semiconductor photodetector according to the modification. The semiconductor photodetector 11A shown in FIG. 8 differs from the semiconductor photodetector 11 shown in FIG. 3 in the following points. The wirings H1 to HN include a plurality of branch wirings hu1 to huN and a plurality of branch wirings hd1 to hdN. The wirings R1 to RM include a plurality of branch wirings rl1 to rlM and a plurality of branch wirings rr1 to rrM. The pad electrodes 22 are provided on both outer sides of the light receiving region A in the Y-axis direction on the XY-axis plane. The pad electrodes 23 are provided on both outer sides of the light receiving region A in the X-axis direction on the XY-axis plane.

[0060] In the semiconductor light-detecting element 11A, the n-th wiring Hn includes a branch wiring hun located at the n-th position among the branch wirings hu1 to huN, and a branch wiring hdn located at the n-th position among the branch wirings hd1 to hdN. In this embodiment, the branch wiring hun is electrically connected to the cells U in the 1st to (M / 2)th rows included in the cell group in the n-th column, and the branch wiring hdn is electrically connected to the cells U in the (M / 2+1)th to Mth rows included in the cell group in the n-th column. The number of cells U connected to the branch wiring hun and the branch wiring hdn may not be the same. The branch wiring hun may be connected to the cells U in the 1st to jth rows of the cell group in the n-th column, and the branch wiring hdn may be connected to the cells U in the (j+1)th to Mth rows of the cell group in the n-th column. j is an integer between 2 and (M-2). In this case, M may be an integer equal to or greater than 4. In the semiconductor light-detecting element 11A, a bias voltage is applied to the cell group in the n-th column via the branch wiring hun and the branch wiring hdn. For example, the branch wirings hu1 to huN form a first branch wiring, and the branch wirings hd1 to hdN form a second branch wiring.

[0061] In the semiconductor light detecting element 11A, the wiring Rm located at the mth position includes a branch wiring rlm located at the mth position among the branch wirings rl1 to rlM, and a branch wiring rrm located at the mth position among the branch wirings rr1 to rrM. In this embodiment, the branch wiring rlm is electrically connected to the cells U in the 1st to (N / 2)th columns included in the cell group in the mth row, and the branch wiring rrm is electrically connected to the cells U in the (N / 2+1)th to Nth columns. The number of cells U connected to the branch wiring rlm and the branch wiring rrm may not be the same. The branch wiring rlm may be connected to the cells U in the 1st to kth columns included in the cell group in the mth row, and the branch wiring rrm may be connected to the cells U in the (k+1)th to Nth columns included in the cell group in the mth row. k is an integer between 2 and (N-2). In this case, N may be an integer equal to or greater than 4. A current signal generated in each cell U is output to the resistor 31 via either the branch wiring rlm or the branch wiring rrm. In this case, the branch wiring rlm and the branch wiring rrm may be connected to the same readout circuit 32, or may be connected to different readout circuits 32. The branch wiring rlm and the branch wiring rrm may be connected to the same resistor 31, or may be connected to different resistors 31. For example, the branch wirings rl1 to rlM constitute a third branch wiring, and the branch wirings rr1 to rrM constitute a fourth branch wiring.

[0062] In the photodetector 1 including the semiconductor photodetector element 11A according to the modified example, similarly to the photodetector 1 including the semiconductor photodetector element 11, the configuration of the wirings H1 to HN and the wirings R1 to RM is simplified.

[0063] The branch wiring hun is electrically connected to the cells U in the 1st to (M / 2)th rows included in the corresponding cell group in the nth column. The branch wiring hdn is electrically connected to the cells in the (M / 2+1)th to Mth rows included in the corresponding cell group in the nth column. When all the cells U included in the cell group in the nth column are electrically connected to one wiring Hn as in the semiconductor light-detecting element 11, the difference between the wiring distance to the cell U in the Mth row located at one end in the column direction and the wiring distance to the cell in the 1st row located at the other end in the column direction is large. When the difference in the wiring distance to the cell U is large, the difference in the timing at which the bias voltage is applied to the cell U also becomes large. In the semiconductor light-detecting element 11A, the difference in the wiring distance to the cell U is small compared to the semiconductor light-detecting element 11 in which all the cells U included in the cell group in the nth column are electrically connected to one wiring Hn. Therefore, the difference in the timing at which the bias voltage is applied to the cell U is small.

[0064] The branch wiring rlm is electrically connected to the cells U in the 1st to (N / 2)th columns included in the corresponding cell group in the mth row. The branch wiring rrm is electrically connected to the cells U in the (N / 2+1)th to Nth columns included in the corresponding cell group in the mth row. When all the cells U included in the cell group in the mth row are electrically connected to one wiring Rm as in the semiconductor photodetector element 11, the difference between the wiring distance from the cell U in the Nth column located at one end in the row direction and the wiring distance from the cell U in the 1st column located at the other end in the row direction is large. When the wiring distance from the cell U is long, noise may be included in the signal read out via the wirings R1 to RM due to the influence of parasitic capacitance generated in the wirings R1 to RM. In the semiconductor photodetector element 11A, the wiring distance from the cell U is short compared to the case where all the cells U included in the cell group in the mth row are electrically connected to one wiring Rm. Therefore, noise is unlikely to be included in the signal read out via each of the wirings R1 to RM. As a result, the deterioration of the detection accuracy of the photodetector 1 is suppressed.

[0065] Next, a light receiving unit 40 provided in a light detecting device according to a second embodiment will be described with reference to Figs. 9 to 14. Fig. 9 is a perspective view of the light receiving unit provided in a light detecting device according to the second embodiment. Fig. 10 is a schematic plan view of a semiconductor light detecting element. Fig. 11 is a schematic view showing a cross-sectional configuration of the light receiving unit. Fig. 12 is a schematic view showing a cross-sectional configuration of the light receiving unit. Fig. 13 is a perspective view showing an example of a wiring form of the semiconductor light detecting element. Fig. 14 is a view showing a cross-sectional configuration of the semiconductor light detecting element.

[0066] 9, the light receiving unit 40 includes a semiconductor light detecting element 41 and a circuit board 42. The semiconductor light detecting element 41 includes a glass substrate 43, a semiconductor substrate 44, and a wiring layer 45. The circuit board 42, the wiring layer 45, the semiconductor substrate 44, and the glass substrate 43 are arranged in this order in the Z-axis direction. In this embodiment, the circuit board 42, the glass substrate 43, the semiconductor substrate 44, and the wiring layer 45 have a rectangular shape in a plan view.

[0067] The glass substrate 43 is made of a transparent glass material that transmits light. The glass substrate 43 has main surfaces 43A and 43B facing each other, and a side surface 43C. The main surfaces 43A and 43B are flat surfaces. The glass substrate 43 is bonded to the semiconductor substrate 44 by an optical adhesive OA. The glass substrate 43 may be formed directly on the semiconductor substrate 44. The semiconductor photodetector element 41 is, for example, a back-illuminated semiconductor photodetector element.

[0068] The semiconductor substrate 44 is made of Si (silicon) and has a p-type conductivity. The semiconductor substrate 44 has a main surface 44A and a main surface 44B that face each other, and a side surface 44C. The main surface 44A of the semiconductor substrate 44 and the main surface 43B of the glass substrate 43 face each other via an optical adhesive OA. The main surface 44A is a light incidence surface to the semiconductor substrate 44. In this embodiment, reflected light is transmitted through the glass substrate 43 and is incident on the semiconductor substrate 44. The wiring layer 45 is disposed between the semiconductor substrate 44 and the circuit substrate 42. For example, when the main surface 44A constitutes the first main surface, the main surface 44B constitutes the second main surface.

[0069] The circuit board 42 has a main surface 42A and a main surface 42B, which face each other, and a side surface 42C. The main surface 42A of the circuit board 42 and the main surface 44B of the semiconductor substrate 44 face each other via the wiring layer 45. In this embodiment, the side surface 42C of the circuit board 42, the side surface 44C of the semiconductor substrate 44, and the side surface 43C of the glass substrate 43 are flush with each other. That is, in a plan view, the outer edges of the circuit board 42, the semiconductor substrate 44, and the glass substrate 43 are aligned with each other. The outer edges of the circuit board 42, the semiconductor substrate 44, and the glass substrate 43 may not be aligned with each other. For example, in a plan view, the area of ​​the circuit board 42 may be larger than the area of ​​the semiconductor substrate 44 and the glass substrate 43. In this case, the side surface 42C of the circuit board 42 is located outside the side surface 44C of the semiconductor substrate 44 and the side surface 43C of the glass substrate 43 in the XY-axis plane.

[0070] The circuit board 42 constitutes an ASIC. The ASIC constituted by the circuit board 42 has a switching unit and a readout unit. The switching unit applies a bias voltage to the cell groups in the 1st to Nth columns for each column. The readout unit includes a readout circuit that reads out signals from the cell groups in the 1st to Mth rows for each row. For example, the switching unit and readout unit in the ASIC constitute a control unit.

[0071] As shown in FIG. 10, the semiconductor substrate 44 has a plurality of cells U that are two-dimensionally arranged in M ​​rows and N columns in a plan view. In the semiconductor substrate 44, a signal corresponding to reflected light detected in each cell U is output from each cell U. The number of cells U is, for example, "1024 (32 rows x 32 columns)". In this embodiment, each of the plurality of cells U includes one avalanche photodiode APD. Each of the plurality of cells U may include a plurality of avalanche photodiodes APD. In the semiconductor substrate 44, a light receiving region A that surrounds the plurality of cells U that are two-dimensionally arranged is formed. In FIG. 10, the illustration of the insulating layer 66 that constitutes the wiring layer 45 is omitted.

[0072] 11 and 12, a trench 21 is formed in the semiconductor substrate 44. The trench 21 opens to the main surface 44A and the main surface 44B. In other words, the trench 21 penetrates the semiconductor substrate 44 in a direction in which the main surface 44A and the main surface 44B face each other (the Z-axis direction). The trench 21 separates adjacent cells U from among the multiple cells U. Specifically, the trench 21 surrounds each of the multiple cells U when viewed from a direction perpendicular to the main surface 44A (the Z-axis direction).

[0073] The wiring layer 45 of the semiconductor photodetector element 41 has a plurality of wirings H1-HN and a plurality of wirings R1-RM, similar to the semiconductor photodetector element 11. The plurality of wirings H1-HN are provided corresponding to the first to Nth columns of cell groups included in the plurality of cells U, respectively. The plurality of wirings R1-RM are provided corresponding to the first to Mth rows of cell groups included in the plurality of cells U, respectively. The plurality of wirings H1-HN and wirings R1-RM in the semiconductor photodetector element 41 have the same configuration as the semiconductor photodetector element 11, except that they are arranged on a main surface 41B of the semiconductor photodetector element 41, i.e., a main surface close to the circuit board.

[0074] The semiconductor light detection element 41 has a plurality of bump electrodes 46 (N bump electrodes 46), a plurality of bump electrodes 47 (N bump electrodes 47), a plurality of bump electrodes 48 (M bump electrodes 48), and a plurality of bump electrodes 49 (M bump electrodes 49). A plurality of wirings H1 to HN are electrically connected to the plurality of bump electrodes 46. The plurality of bump electrodes 47 are provided at positions corresponding to the plurality of bump electrodes 46 in the X-axis direction, and no wirings are connected to the plurality of bump electrodes 47. A plurality of wirings R1 to RM are electrically connected to the plurality of bump electrodes 48. The plurality of bump electrodes 49 are provided at positions corresponding to the plurality of bump electrodes 47 in the Y-axis direction, and no wirings are connected to the plurality of bump electrodes 49. The plurality of bump electrodes 47 and the plurality of bump electrodes 49 are dummy bump electrodes, and have a role of preventing the semiconductor substrate 44 from tilting with respect to the circuit substrate 42.

[0075] Wirings H1 to HN are each electrically connected to the circuit board 42. As shown in FIG. 11, wiring Hn is disposed on the main surface 44B of the semiconductor substrate 44. Here, wiring Hn is provided on the main surface 44B. Wiring Hn is electrically connected to a switching unit in the circuit board 42. In addition, wirings R1 to RM are each electrically connected to the circuit board 42. As shown in FIG. 12, wiring Rm is disposed on the main surface 44B of the semiconductor substrate 44. Here, wiring Rm is provided on the main surface 44B. Wiring Rm is electrically connected to a read-out unit in the circuit board 42.

[0076] Next, an example of the wiring form between the wirings H1 to HN and the wirings R1 to RM will be described. FIG. 13 shows a perspective view of the semiconductor substrate 44 from which the insulating layer 66 constituting the wiring layer 45 is omitted. The avalanche photodiode APD constituting the cell U includes a semiconductor region 51 having an n-type conductivity and a semiconductor region 55 having a p-type conductivity. The semiconductor region 51 and the semiconductor region 55 form a pn junction of the avalanche photodiode APD. The avalanche photodiode APD further includes a semiconductor region 56 in order to reduce the contact resistance with the wiring connected to the avalanche photodiode APD. The impurity concentration of the semiconductor region 56 is higher than the impurity concentration of the semiconductor region 55.

[0077] The avalanche photodiodes APD adjacent to each other are separated by a trench 21. In other words, the trench 21 surrounds the semiconductor region 56 of each avalanche photodiode APD when viewed from the Z-axis direction. The trench 21 is filled with a light-shielding member 53. The light-shielding member 53 is made of a material that reflects light. The light-shielding member 53 may be made of a material that absorbs light without reflecting it. The material that constitutes the light-shielding member 53 is, for example, tungsten. A part of the light-shielding member 53 protrudes from the main surface 44A of the semiconductor substrate 44 and is located in the optical adhesive OA. The surface of the light-shielding member 53 except for the surface exposed from the main surface 44B is covered with an insulating film 54. For example, the side surface of the part of the light-shielding member 53 located in the trench 21 and the surface of the part of the light-shielding member 53 protruding from the main surface 44A are covered with the insulating film 54 that is integrally formed. The insulating film 54 is located between the light shielding member 53 and the semiconductor region 56. This ensures insulation between the semiconductor region 56 of the avalanche photodiode APD and the light shielding member 53.

[0078] The wiring Hn includes a common wiring 61 and a plurality of connection wirings 62. The common wiring 61 is arranged along the direction in which the plurality of cells U included in the n-th column of cell groups are arranged. The plurality of connection wirings 62 electrically connect the common wiring 61 to the semiconductor region 56 of each avalanche photodiode APD. When viewed from the X-axis direction, the common wiring 61 and the connection wirings 62 cross each other. The common wiring 61 and the connection wirings 62 are made of the same metal material, for example, aluminum. The common wiring 61 and the connection wirings 62 may be made of a metal material. The metal material includes, for example, Cu (copper), Ti (titanium), Ni (nickel), Au (gold), or Pt (platinum).

[0079] The wiring Rm includes a common wiring 63, a plurality of quenching resistors 64, and a plurality of connection wirings 65. The common wiring 63 is arranged along the direction in which the plurality of cells U included in the m-th row of cell groups are arranged. The plurality of quenching resistors 64 are connected to the common wiring 63. The plurality of connection wirings 65 electrically connect the plurality of quenching resistors 64 and the semiconductor region 51 to each other. When viewed from the Y-axis direction, the common wiring 63 and the connection wirings 65 cross each other. The common wiring 63 and the connection wirings 65 are made of the same metal material, for example, aluminum. The common wiring 63 and the connection wirings 65 may be made of a metal material. The metal material includes, for example, Cu (copper), Ti (titanium), Ni (nickel), Au (gold), or Pt (platinum). The quenching resistor 64 is arranged along the periphery of the semiconductor region 51 when viewed from the Z-axis direction. The quenching resistor 64 is made of, for example, silicon chromium (SiCr). The quenching resistor 64 may be made of polysilicon, nickel chromium (NiCr), or ferrochromium (FeCr).

[0080] FIG. 14 shows an example of a cross-sectional configuration of the semiconductor substrate 44 including the insulating layer 66 of the wiring layer 45. In FIG. 14, the cross-sectional configuration of the insulating layer 66 is shown, and hatching of the insulating layer 66 is omitted. The semiconductor region 55 surrounds a part (side surface and bottom surface) of the semiconductor region 51, and the semiconductor region 56 surrounds a part (outer side surface and bottom surface) of the semiconductor region 55. The common wiring 61 of the wiring Hn is electrically connected to the semiconductor region 56 via a connection wiring 62. The common wiring 63 of the wiring Rm is electrically connected to the semiconductor region 51 via a quenching resistor 64 and a connection wiring 65. For example, in an avalanche photodiode APD to which a bias voltage is applied, the semiconductor region 51 is a cathode, and the semiconductor region 56 is an anode. For example, when a depletion layer does not reach the semiconductor region 56 in the pn junction formed by the semiconductor region 51 and the semiconductor region 55 even if a bias voltage is applied, and when a bias voltage is not applied, the semiconductor region 51 is a cathode, and the semiconductor region 55 and the semiconductor region 56 are an anode. As shown in FIG. 14, the positions in the Z-axis direction of the common wiring 61 of the wiring Hn, the quenching resistor 64 of the wiring Rm, and the common wiring 63 of the wiring Rm are different from each other. In this embodiment, the common wiring 63, the quenching resistor 64, and the common wiring 61 are arranged in this order from the main surface 44B of the semiconductor substrate 44. The cross sections of the common wiring 61, the common wiring 63, and the quenching resistor 64 are rectangular. For example, when the semiconductor region 55 and the semiconductor region 56 constitute an anode, the semiconductor region 51 constitutes a cathode.

[0081] As an example, the thickness of the common wiring 61, i.e., the length of the common wiring 61 in the Z-axis direction, is about 600 nm, the thickness of the common wiring 63 is about 600 nm, and the thickness of the quenching resistor 64 is about 5 nm. As an example, the distance between the common wiring 61 and the quenching resistor 64 is about 300 nm, and the distance between the quenching resistor 64 and the common wiring 63 is about 300 nm. The distance between the common wiring 63 and the main surface 44B of the semiconductor substrate 44 is about 300 nm. The insulating layer 66 is made of SiO2 (silicon oxide). The insulating layer 66 covers the wirings H1 to HN and the wirings R1 to RM. As an example, the thickness of the insulating layer 66 is about 2.5 μm.

[0082] In the photodetector according to the second embodiment including the light receiving unit 40, similarly to the photodetector 1, a bias voltage is applied in sequence to each of the cell groups in the 1st to Nth columns via the wirings H1 to HN in synchronization with the incidence of reflected light on each of the cell groups in the 1st to Nth columns. Furthermore, while a bias voltage is being applied to any of the cell groups in the 1st to Nth columns, signals are read out via the wirings R1 to RM from the cells U in the 1st to Mth rows included in the cell group to which the bias voltage is being applied.

[0083] Next, a semiconductor photodetector 41A according to a modified example of the photodetector of this embodiment will be described. Fig. 15 is a schematic plan view of the semiconductor photodetector according to the modified example. The semiconductor photodetector 41A shown in Fig. 15 differs from the semiconductor photodetector 11A shown in Fig. 8 in the following points. The wirings H1 to HN and the wirings R1 to RM are disposed on the main surface 44B close to the circuit board 42. These wirings are electrically connected to a plurality of bump electrodes 46, a plurality of bump electrodes 47, a plurality of bump electrodes 48, and a plurality of bump electrodes 49.

[0084] In the semiconductor light-detecting element 41A, similarly to the semiconductor light-detecting element 11A, the plurality of wirings H1 to HN include a plurality of branch wirings hu1 to huN and a plurality of branch wirings hd1 to hdN, and the plurality of wirings R1 to RM include a plurality of branch wirings rl1 to rlM and a plurality of branch wirings rr1 to rrM. The plurality of branch wirings hu1 to huN are electrically connected to a plurality of bump electrodes 47, and the plurality of branch wirings hd1 to hdN are electrically connected to a plurality of bump electrodes 46. The plurality of branch wirings rl1 to rlM are electrically connected to a plurality of bump electrodes 49, and the plurality of branch wirings rr1 to rrM are electrically connected to a plurality of bump electrodes 48.

[0085] In the photodetector according to the second embodiment including the semiconductor photodetector elements 41, 41A, the configuration of the wirings H1 to HN and the wirings R1 to RM is simplified, similar to the photodetector 1 including the semiconductor photodetector elements 11, 11A.

[0086] When reflected light is incident on a cell U included in the n-th row cell group to which a bias voltage is applied, a light other than the reflected light may be emitted from the cell U during the avalanche multiplication process. In this case, another light may be incident on a cell U adjacent to the cell U emitting the other light, causing optical crosstalk. Such optical crosstalk may occur even if another light is incident on a cell U adjacent in the row direction to which no bias voltage is applied. In the semiconductor photodetector element 41, 41A, the light shielding member 53 is provided in the trench 21, so that even if another light attempts to enter the adjacent cell U, it is blocked by the light shielding member 53. As a result, optical crosstalk is suppressed, and the detection accuracy of the photodetector including the semiconductor photodetector element 41, 41A is ensured. The light shielding member 53 is covered with an insulating film 54. Even if moisture or the like adheres to the light shielding member 53, the insulating film 54 prevents the moisture from adhering to the light shielding member 53, and therefore prevents the surface of the light shielding member 53 from corroding. As a result, the durability of the light shielding member 53 is improved.

[0087] Next, a light receiving unit 70 included in a light detecting device according to a third embodiment will be described with reference to Figs. 16 to 18. Fig. 16 is a schematic plan view of a semiconductor light detecting element included in a light detecting device according to the third embodiment. Fig. 17 is a schematic view showing a cross-sectional configuration of the light receiving unit. Fig. 18 is a schematic view showing a cross-sectional configuration of the light receiving unit.

[0088] A light-receiving unit 70 shown in Figs. 16 to 18 differs from the light-receiving unit 40 shown in Fig. 10 in that each cell U is electrically connected to a circuit board 72 via a plurality of bump electrodes 71 instead of the wirings H1 to HN and wirings R1 to RM. The light-receiving unit 70 includes a semiconductor light-detecting element 73 and a circuit board 72. The semiconductor light-detecting element 73 includes a semiconductor substrate 44 and a plurality of bump electrodes 71. The plurality of bump electrodes 71 are provided corresponding to each of the plurality of cells U two-dimensionally arranged in M ​​rows and N columns. The semiconductor light-detecting element 73 is, for example, a back-illuminated semiconductor light-detecting element.

[0089] The circuit board 72 has a switching unit and a readout unit. The switching unit applies a bias voltage to the cell groups in the first to N columns for each column. The readout unit includes a readout circuit that reads out signals from the cell groups in the first to M rows for each row. For example, the switching unit and readout unit of the circuit board 72 constitute a control unit. As shown in FIG. 17, a cell U included in the cell group in the nth column is electrically connected to the switching unit in the circuit board 72 via a wiring Hpn provided in the circuit board 72. "n" in "wiring Hpn" is an integer from 1 to N. A bias voltage is applied to the cell group in the nth column via the wiring Hpn in the circuit board 72. A plurality of wirings Hp1 to HpN are provided in the circuit board 72 corresponding to the cell groups in the first to N columns for each column, and the wirings Hp1 to HpN are electrically connected to the corresponding cell groups among the cell groups in the first to N columns via bump electrodes 71.

[0090] As shown in FIG. 18, a cell U included in the m-th cell group is electrically connected to a readout unit in the circuit board 72 via a wiring Rpm provided in the circuit board 72. "m" in "wiring Rpm" is an integer from 1 to M. A signal from each cell U included in the m-th cell group is read out via the wiring Rpm. The wiring Rpm may include a quenching resistor. A plurality of wirings Rp1 to RpM are provided in the circuit board 72 corresponding to the 1st to Mth cell groups, and the wirings Rp1 to RpM are electrically connected to the corresponding cell groups among the 1st to Mth cell groups via bump electrodes 71.

[0091] Unlike the semiconductor photodetector elements 11 and 41, the semiconductor photodetector element 73 does not include wiring for applying a bias voltage to the 1st to Nth columns of cells for each column, and wiring for reading out signals from the 1st to Mth rows of cells for each row. In the light receiving unit 70, wirings Hp1 to HpN for applying a bias voltage and wirings Rp1 to RpN for reading out signals are provided in the circuit board 72. The wirings Hp1 to HpN and wirings Rp1 to RpN may be provided on the surface of the circuit board 72. For example, the wirings Hp1 to HpN constitute a plurality of first wirings, and the wirings Rp1 to RpM constitute a plurality of second wirings.

[0092] In the photodetector according to the third embodiment including the light receiving unit 70, in synchronization with the timing at which reflected light is incident on each of the cell groups in the 1st to Nth columns, a bias voltage is applied to each of the cell groups in the 1st to Nth columns in sequence via the wiring Hp1 to HpN in the circuit board 72. When a bias voltage is applied to any of the cell groups in the 1st to Nth columns, signals from the cells U in the 1st to Mth rows included in the cell group to which the bias voltage is applied are read out via the wiring Rp1 to RpM in the circuit board 42.

[0093] In the photodetector according to the third embodiment including the light receiving unit 70, similarly to the photodetector 1 including the semiconductor photodetector element 11, the configuration of the wirings Hp1 to HpN and the wirings Rp1 to RpM is simplified.

[0094] The light-receiving unit 70 includes a circuit board 72 having a switching section and a readout section. Each of the multiple cells U is electrically connected to the circuit board 72. The wirings Hp1 to HpN and wirings Rp1 to RpM are provided on the circuit board 72. Therefore, compared to the light-receiving units 4, 40 in which the wirings H1 to HN and wirings R1 to RM are arranged on the semiconductor substrates 20, 44, the light-receiving unit 70 does not require a member (e.g., insulating layer 66) for protecting the wirings that apply a bias voltage and the wirings that read out signals, and the configuration of the light-receiving unit 70 can be simplified.

[0095] The above describes the embodiments and modifications of the present invention, but the present invention is not necessarily limited to the above-described embodiments and modifications, and various modifications are possible without departing from the spirit of the present invention.

[0096] For example, in a plurality of cells U two-dimensionally arranged in M ​​rows and N columns, M and N may be different numbers. A plurality of cells U located in a part of the light receiving region A among the plurality of cells U two-dimensionally arranged in M ​​rows and N columns may be used, and a signal according to the reflected light may be read out. For example, the light projecting unit 2 may project laser light onto a plurality of cells U located in rows 1 to (M / 2) and columns 1 to (N / 2) in the row direction such that reflected light is incident on each column.

[0097] For example, the photodetector may include a semiconductor photodetector element having a plurality of cells U two-dimensionally arranged in (2×M) rows and N columns. In this photodetector, the light projecting unit 2 may scan with a laser light such that reflected light is incident on a plurality of cells U located in rows 1 to M and columns 1 to N for each column, and then scan with a laser light such that reflected light is incident on a plurality of cells U located in rows (M+1) to (2×M) and columns 1 to N for each column. For example, the light projecting unit 2 may scan with a laser light along direction D2 such that reflected light is incident on cells U in rows 1 to M, and then reflected light is incident on cells U in rows (M+1) to (2×M) in each column. In these cases, a single wiring may be provided for each column to apply a bias voltage to cells U in the 1st to (2×M)th rows, or a wiring may be provided for each column to apply a bias voltage to cells U in the 1st to Mth rows and a wiring to apply a bias voltage to cells U in the (M+1)th to (2×M)th rows.

[0098] The trench 21 formed so as to electrically separate the avalanche photodiodes APD in the adjacent cells U may be open only to one of the main surfaces 20A, 44A and the main surfaces 20B, 44B of the semiconductor substrates 20, 44. In this case, the length of the trench 21 in the Z-axis direction may be, for example, half or more of the length of the semiconductor substrates 20, 44 in the Z-axis direction. In the case where the trench 21 in the semiconductor substrate 44 is open only to one of the main surfaces 44A and 44B, the light receiving unit 40 may not include the glass substrate 43. The trench 21 may not be formed in the semiconductor substrates 20, 44 so as to surround each of the multiple cells U as viewed from the Z-axis direction. For example, the trench 21 may be formed in the semiconductor substrates 20, 44 only at positions separating adjacent cell groups from each other among the cell groups in the first to Nth rows. For example, the shape or depth of the trench separating adjacent cell groups among the cell groups in the 1st to Nth columns may be different from the shape or depth of the trench separating adjacent cell groups among the cell groups in the 1st to Mth rows.

[0099] In the above-described embodiment, the trench 21 electrically separates adjacent cell groups from the cell groups in the first to N columns, but the configuration for electrically separating adjacent cell groups from each other is not limited thereto. For example, instead of the trench 21, adjacent cells U from among the plurality of cells U may be separated from each other by a well. In other words, adjacent cell groups from among the cell groups in the first to N columns may be separated from each other by a well. The well is, for example, a semiconductor region of a conductivity type opposite to that of the semiconductor region constituting the outer edge of the avalanche photodiode APD. The well is formed by adding impurities to a silicon substrate by a diffusion method or an ion implantation method. When adjacent cells U are separated from each other by a well, it is not possible to arrange the light shielding member 53 in the well, but when the cells are separated from each other by the trench 21, it is possible to arrange the light shielding member 53 in the trench 21. Therefore, optical crosstalk can be suppressed when adjacent cells U are separated from each other by the trench 21, compared to when they are separated by a well.

[0100] In the above-described embodiment, one layer structure of the avalanche photodiode APD is shown, but the layer structure of the avalanche photodiode APD is not limited to this. For example, the conductivity type of the semiconductor region 51 may be p-type, and the conductivity type of the semiconductor region 55 and the semiconductor region 56 may be n-type. For example, the semiconductor region 51 may be composed of a plurality of semiconductor regions having different impurity concentrations. The avalanche photodiode APD may not have the semiconductor region 56. For example, in each avalanche photodiode APD, a semiconductor region of a first conductivity type may constitute one main surface of a semiconductor substrate, and a semiconductor region of a second conductivity type forming a pn junction with the semiconductor region of the first conductivity type may constitute the other main surface of the semiconductor substrate. In this case, the wirings H1 to HN and the wirings R1 to RM may be provided on different main surfaces. For example, the wirings H1 to HN for applying a bias voltage may be electrically connected to the semiconductor region 51, and the wirings R1 to RM for reading out a signal may be electrically connected to the semiconductor region 56. For example, the semiconductor regions 51, 55, and 56 may be formed by adding impurities to a silicon substrate by a diffusion method or an ion implantation method. The layer structures of the avalanche photodiode APD in the above-described embodiment and this modified example are merely examples, and the layer structure of the avalanche photodiode APD may be configured to operate in the Geiger mode when a bias voltage is applied. In the layer structure of the avalanche photodiode APD illustrated, the semiconductor region indicated as n-type may be p-type, and the semiconductor region indicated as p-type may be n-type. The semiconductor regions corresponding to the anode and the cathode differ depending on the layer structure of the avalanche photodiode APD.

[0101] The wirings H1 to HN may be electrically connected to the cells U in the 1st to Mth rows, and the wirings R1 to RM may have branch wirings rl1 to rlM and branch wirings rr1 to rrM. The wirings R1 to RM may be electrically connected to the cells U in the 1st to Nth columns, and the wirings H1 to HN may have branch wirings hu1 to huN and branch wirings hd1 to hdN. In other words, a part of the configuration of the semiconductor photodetector elements 11A and 41A may be applied to the semiconductor photodetector elements 11 and 41.

[0102] A control unit that drives the cell groups in the 1st to Nth columns of semiconductor photodetector element 11, 41 column by column and controls reading out the outputs from the cell groups in the 1st to Mth rows row by row may be provided on a substrate different from the mounting substrate or circuit substrate on which semiconductor photodetector elements 11, 41 are provided. Control unit 13 may control light projection unit 2 in addition to the above-mentioned drive and readout control.

[0103] The wiring Hn may have three or more branch wirings. In this case, the cell group in the nth column may be divided into groups with the same number as the number of branch wirings, and a bias voltage may be applied to each group via the branch wiring. The wiring Rm may have three or more branch wirings. In this case, the cell group in the mth row may be divided into groups with the same number as the number of branch wirings, and a signal may be read out for each group via the branch wiring.

[0104] The light projection unit 2 may project (scan) the laser light so that the reflected light of the laser light projected toward each of the plurality of light projection positions is incident on each of the plurality of cell groups among the cell groups in the first to N columns. In this case, the number of the plurality of cell groups is less than N. In this case, the control unit 13 may apply a bias voltage to each of the plurality of cell groups in correspondence with the incidence of the reflected light on each of the plurality of cell groups. For example, the light projection unit 2 may project the laser light so that the reflected light of the laser light projected toward each of the (N / 2) light projection positions is incident on each of the cell groups in the (2×n-1)th and (2×n)th columns among the cell groups in the first to N columns. In this case, as in the case where the laser light is projected so that the reflected light of the laser light is incident on each of the cell groups in the first to N columns, it is sufficient that the wiring for applying the bias voltage is provided for each column, and the wiring for reading out the signal is provided for each row. As a result, it is possible to simplify the configuration of the wiring for applying a bias voltage to each avalanche photodiode APD and the wiring for reading out a signal from each cell U. For example, the light-projecting unit 2 may project a laser beam so that the number of cells aligned in the column direction is greater than the number of cells aligned in the row direction in a plurality of cell groups into which reflected light of the laser beam projected toward one light-projecting position is incident. In this case, a signal corresponding to the reflected light is efficiently read out while maintaining the resolution of the detection result of the object by the light-detecting device 1.

[0105] For example, the light projecting unit 2 may scan the laser light so that the reflected light of the laser light is incident on the cell groups in the (2×n-1)th and (2×n)th columns, and then the reflected light of the laser light is incident on the cell groups in the (2×n)th and (2×n+1)th columns. When the reflected light is incident on each of the two cell groups as described above, a signal is read out, and an image is generated based on the read out signal, an image with high resolution is obtained. For example, when the laser light is scanned so that the reflected light is partially overlapped in the range where it is incident as described above, the reflected light may be incident on each of three or more cell groups. For example, the light projecting unit 2 may project the laser light so that the reflected light of the laser light is incident on each of one or more cell groups at different positions in the row direction. For example, when the reflected light of the laser light is incident on each of one or more cell groups, the mirror 6 may be set at two different angles corresponding to one or more cell groups. The mirror 6 may be set at two mutually different angles corresponding to one or more cell groups, so that the laser light is incident on two divided regions for one or more cell groups. For example, the mirror 6 may be set at three or more mutually different angles corresponding to one or more cell groups. In this case, the laser light may be incident on three or more divided regions for one or more cell groups.

[0106] In the above embodiment, the readout unit 15 of the control unit 13 reads out signals from each of the M cells U included in the cell group in the n-th column to which the bias voltage is applied, but the signal readout method is not limited to this. The control unit 13 may read out signals for each of the M cells included in the cell group in the n-th column to which the bias voltage is applied. For example, the readout unit 15 of the control unit 13 may read out signals for each of the cells U in the (2×m−1)th row and the (2×m)th row included in the cell group in the n-th column to which the bias voltage is applied. In this case, a wiring electrically connected to the cell U in the (2×m−1)th row and a wiring electrically connected to the cell U in the (2×m)th row may be connected to a single resistor 31, and a voltage drop across the resistor 31 may be input to the readout circuit 32. For example, when reflected light is incident on one or more cell groups, the multiple laser light sources 5 included in the light projection unit 2 may emit light not only simultaneously but also at different timings. In this case, the timing at which the reflected light is incident on each of the cells U included in the cell group located in one column is shifted. At this time, a bias voltage is applied to M cells U included in the cell group located in one column, but the timing at which the signals are output from each of the M cells U is different. Therefore, in the readout unit 15, it is possible to read out signals from the cells on which the reflected light is incident among the M cells U included in the cell group in order. This makes it possible to reduce the number of rows (the number of cells U) that must be read out simultaneously, and simplifies the circuit configuration located downstream of the resistor 31 or the signal processing unit 33.

[0107] When applying a bias voltage to the cell group in the n-th column, the switching unit 14 of the control unit 13 may apply a voltage smaller than the bias voltage to the cell group located in a column other than the n-th column. The voltage applied to the cell group located in a column other than the n-th column is smaller than the breakdown voltage. In other words, a voltage that does not operate the avalanche photodiode APD in the cell group located in a column other than the n-th column may be applied to the avalanche photodiode APD included in the cell group located in the column other than the n-th column. Even in this case, the signal output from the avalanche photodiode APD in the cell U to which the bias voltage is not applied is extremely small, so that the influence of the signal on the entire signal read out via the wiring R1 to RM is extremely small, and the detection accuracy of the photodetector 1 is ensured. Furthermore, when applying a bias voltage, a bias voltage that operates the avalanche photodiode APD in the Geiger mode is applied to the avalanche photodiode APD without causing a sudden voltage change.

[0108] The wirings R1 to RM may not have the quenching resistor 64. In this case, the readout unit 15 of the control unit 13 may have the quenching resistor.

[0109] The column direction in which the cells U are arranged and the direction D1 may be slightly misaligned from each other. When the column direction and the direction D1 are aligned with each other, it is easy to make the reflected light enter the necessary places among the cells U, and the electric power supplied to the laser light source 5 is suppressed by making the reflected light enter only the necessary places and their vicinity.

[0110] The wirings electrically connecting the cells U included in each of the cell groups in the first to N columns and the wirings electrically connecting the cells U included in each of the cell groups in the first to M rows are not limited to the wirings H1 to HN and wirings R1 to RM made of metal materials. For example, in each cell group in which the cells U are arranged in the column direction or in each cell group in which the cells U are arranged in the row direction, the wirings electrically connecting the cells U included in each cell group may be semiconductor regions formed on a semiconductor substrate. In this case, the semiconductor regions corresponding to the anodes or cathodes of each cell U may be electrically connected to each other by a semiconductor region (diffusion region) for connection. In contrast, when the cells U included in each cell group are electrically connected to each other by wirings made of metal materials, the voltage drop associated with the wirings is smaller than in the configuration in which the cells are electrically connected by the semiconductor region for connection, so that each cell U is connected to approximately the same potential. For example, when the above-mentioned semiconductor region for connection is provided, one electrical contact (electrode) may be provided corresponding to M cells U included in a cell group in which cells U are arranged in a column direction, and one wiring for applying a bias voltage to the cell group may be connected to the contact. [Explanation of symbols]

[0111] 2...light-projecting unit, 11, 11A, 41, 41A...semiconductor photodetector element, 13...control unit, 20, 44...semiconductor substrate, 20A, 44A...main surface, 20B, 44B...main surface, 21...trench, U...cell, APD...avalanche photodiode, H1-HN, Hn...wiring, R1-RM, Rm...wiring, hu1-huN, hd1-hdN...branch wiring, rl1-rlM, rr1-rrM...branch wiring, S...detection target area.

Claims

1. a light projecting unit that projects light having a cross-sectional shape whose longitudinal direction is the first direction toward a detection target area; a light receiving unit that has a semiconductor substrate including a plurality of cells that are two-dimensionally arranged in M ​​rows and N columns (M and N are integers of 2 or more), and that receives reflected light of the light projected by the light projecting unit; A control unit connected to the light receiving unit, each of the plurality of cells includes at least one avalanche photodiode operating in Geiger mode; The plurality of cells include N first cell groups each including M of the cells arranged in a column direction, the light projecting unit scans the light along a second direction intersecting the first direction such that the reflected light is incident on each of one or more of the first cell groups; The control unit is applying either a first voltage higher than a breakdown voltage of the avalanche photodiode or a second voltage lower than the breakdown voltage to one or more of the first cell groups; reading out signals from the cells included in one or more of the first cell groups to which the first voltage is applied in response to the incidence of the reflected light; Light detection device.

2. the light projecting unit scans the light along the second direction such that the reflected light is incident on each of the first cell groups; 2. The photodetection device of claim 1, wherein the control unit applies the first voltage to each of the first cell groups in response to the incidence of the reflected light, and reads out signals from M of the cells included in the first cell group to which the first voltage has been applied.

3. a plurality of first wirings and a plurality of second wirings provided corresponding to each of the first cell groups; The plurality of cells include M second cell groups each including N of the cells arranged in a row direction, the second wirings are provided corresponding to the second cell groups, Each of the first wirings is electrically connected to one of the anodes and the cathodes of M of the cells included in a corresponding one of the N first cell groups, Each of the second wirings is electrically connected to the other of the anode and the cathode of N cells included in a corresponding one of the M second cell groups, The control unit is applying the first voltage to M cells included in the corresponding first cell group via each of the first wirings; The photodetector according to claim 1 , wherein the signals are read out via the second wirings.

4. A circuit board having the control unit is further provided. Each of the plurality of cells is electrically connected to the circuit board; The photodetector according to claim 3 , wherein the first wirings and the second wirings are provided on the circuit board.

5. 5. The photodetector according to claim 1, wherein a trench is formed in the semiconductor substrate so as to separate adjacent first cell groups from each other.

6. the semiconductor substrate includes a first main surface and a second main surface opposed to each other; The photodetector according to claim 5 , wherein the trench is open to the first main surface and the second main surface, and surrounds each of the plurality of cells when viewed in a direction perpendicular to the first main surface.

7. a light receiving section having a semiconductor substrate including a plurality of cells arranged two-dimensionally in M ​​rows and N columns (M and N are integers of 2 or more); A control unit connected to the light receiving unit, each of the plurality of cells includes at least one avalanche photodiode operating in Geiger mode; The plurality of cells include N first cell groups each including M of the cells arranged in a column direction, The control unit is applying either a first voltage higher than a breakdown voltage of the avalanche photodiode or a second voltage lower than a breakdown voltage of the avalanche photodiode to one or more of the first cell groups; reading out signals from the cells included in the one or more first cell groups to which the first voltage is applied; Light detection device.

8. The photodetector according to claim 7 , wherein a trench is formed in the semiconductor substrate so as to separate adjacent first cell groups from each other.

9. the semiconductor substrate includes a first main surface and a second main surface opposed to each other; The photodetector according to claim 8 , wherein the trench is open to the first main surface and the second main surface, and surrounds each of the plurality of cells when viewed from a direction perpendicular to the first main surface.

10. a plurality of cells each having at least one avalanche photodiode; a control unit that controls so that either a first voltage greater than a breakdown voltage of the avalanche photodiode or a second voltage less than the breakdown voltage is supplied to each of a plurality of cell groups obtained by dividing the plurality of cells.

11. The control unit sequentially performs switching control on each of the plurality of cell groups to sequentially read out signals from the plurality of cells; The switching control includes: supplying the first voltage to a cell belonging to one of the plurality of cell groups; and supplying the second voltage to cells belonging to other of the plurality of cell groups.

12. 1. A method for controlling a detection device including a plurality of cells, each cell having at least one avalanche photodiode, comprising the steps of: A method for controlling a detection device, comprising: controlling so that either a first voltage greater than a breakdown voltage of the avalanche photodiode or a second voltage less than the breakdown voltage is supplied to each of a plurality of cell groups obtained by dividing the plurality of cells.

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