Forming method for semiconductor device

Abstract

To provide a transistor including an oxide semiconductor, in which variation in electric characteristic is suppressed and the reliability is improved.SOLUTION: A transistor includes an oxide semiconductor film on a first insulating film, a second insulating film on the oxide semiconductor film, a metal oxide film on the second insulating film, a gate electrode on the metal oxide film, and a third insulating film on the oxide semiconductor film and the gate electrode. The oxide semiconductor film includes a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The source region and the drain region include one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a noble gas.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. Regarding the device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to a product, a method, or a manufacturing method. process, machine, manufacture, or composition of matter In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, The present invention relates to a device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Semiconductor elements such as transistors, semiconductor circuits, computing devices, memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (field-effect transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology that makes up the field-effect transistor (FET) or thin-film transistor (TFT) is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices. Silicon is a semiconductor thin film that can be used in transistors. Semiconductor materials such as silicon are widely known, but oxide semiconductors are also attracting attention. It is being watched.

[0005] For example, amorphous oxides containing In, Zn, Ga, Sn, etc. are used as oxide semiconductors. A technique for fabricating a transistor using self-aligned transistors has been disclosed (see Patent Document 1). A technique for fabricating a transistor using a thin oxide film having a top gate structure has been disclosed (Patent (See Patent Document 2).

[0006] In addition, a base insulating layer of the oxide semiconductor layer in which a channel is formed is heated to release oxygen. A semiconductor device is disclosed in which an insulating layer is used to reduce oxygen vacancies in the oxide semiconductor layer. (See Patent Document 3). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2006-165529 A [Patent Document 2] JP 2009-278115 A [Patent Document 3] JP 2012-009836 A Summary of the Invention [Problem to be solved by the invention]

[0008] As a transistor having an oxide semiconductor film, for example, an inverted staggered type (bottom gate structure) The oxide semiconductor When a transistor having a thin film is applied to a display device, it is preferable to use an inverted type transistor rather than a staggered type transistor. The manufacturing process of staggered transistors is relatively simple and the manufacturing costs are reduced. However, as the screen size of display devices increases, Higher resolution image quality (for example, 4K x 2K (horizontal pixel count = 3840 pixels, vertical pixel count = 2160 pixels) or 8K x 4K (horizontal pixel count = 7680 pixels, vertical pixel count = As the development of high-resolution display devices (represented by 4320 pixels) progresses, the use of inverted staggered transistors In some cases, parasitic capacitance may occur between the gate electrode and the source and drain electrodes. Depending on the size of the parasitic capacitance, signal delays may increase, degrading the image quality of the display device. Therefore, a staggered transistor including an oxide semiconductor film has a problem that the It is desirable to develop structures that have consistent semiconductor properties and high reliability.

[0009] In addition, when a transistor is manufactured by using an oxide semiconductor film for a channel region, Oxygen vacancies formed in the channel region of the conductive film affect transistor characteristics. For example, when oxygen vacancies are formed in the channel region of the oxide semiconductor film, the oxygen Carriers are generated due to electron vacancies. Carriers are generated in the channel region of the oxide semiconductor film. When the oxide semiconductor film is generated, the electrical characteristics of a transistor having a channel region including the oxide semiconductor film change. Typically, a shift in threshold voltage occurs. In addition, the electrical characteristics of each transistor vary. Therefore, in the channel region of the oxide semiconductor film, oxygen vacancies are formed. On the other hand, in a transistor using an oxide semiconductor film for a channel region, In the present invention, the oxide semiconductor film in contact with the source electrode and the drain electrode is In order to reduce the contact resistance with the drain electrode, it is preferable that the contact has many oxygen vacancies and has low resistance.

[0010] In view of the above problems, one embodiment of the present invention is to provide a transistor including an oxide semiconductor. One of the objectives is to suppress fluctuations in thermal characteristics and improve reliability. An object of one embodiment of the present invention is to provide a staggered transistor including an oxide semiconductor. Alternatively, one embodiment of the present invention is a transistor having an oxide semiconductor and having a large on-state current. Another object of the present invention is to provide a transistor including an oxide semiconductor. Another object of the present invention is to provide a transistor having a low off-state current. An object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0011] The above description of the problem does not preclude the existence of other problems. The embodiment does not necessarily have to solve all of these problems. Problems other than those mentioned above may be solved by the specification. The above problems are obvious from the description of the specification, etc., and problems other than those mentioned above cannot be extracted from the description of the specification, etc. It is possible to issue it. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a transistor, the transistor comprising: an oxide semiconductor film on the insulating film; a second insulating film on the oxide semiconductor film; a metal oxide film, a gate electrode on the metal oxide film, an oxide semiconductor film, and a third layer on the gate electrode; the oxide semiconductor film has a channel region overlapping with the gate electrode and a third insulating film. a source region in contact with the insulating film and a drain region in contact with the third insulating film, and the drain region is doped with hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, Or it is a semiconductor device having one or more rare gases.

[0013] Another embodiment of the present invention is a semiconductor device including a transistor. The oxide semiconductor film includes a conductive film, a first insulating film on the conductive film, an oxide semiconductor film on the first insulating film, and an oxide a second insulating film on the semiconductor film; a metal oxide film on the second insulating film; and a gate on the metal oxide film. a third insulating film over the electrode, the oxide semiconductor film, and the gate electrode; The gate electrode and the source region are connected to a channel region and a third insulating film, respectively. and a drain region in contact with the insulating film, the source region and the drain region being doped with hydrogen, boron, Semiconductors containing one or more of carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, or rare gases It is a device.

[0014] Another embodiment of the present invention is a semiconductor device including a transistor. The oxide semiconductor film includes a conductive film, a first insulating film on the conductive film, an oxide semiconductor film on the first insulating film, and an oxide a second insulating film on the semiconductor film; a metal oxide film on the second insulating film; and a gate on the metal oxide film. The gate electrode includes an oxide semiconductor film and a third insulating film over the gate electrode. The oxide semiconductor film has a channel region overlapping with the gate electrode and a first electrode. a source region in contact with the third insulating film and a drain region in contact with the third insulating film, The source and drain regions are doped with hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and titanium. A semiconductor device having one or more of the following:

[0015] In the above embodiment, the transistor further includes a fourth insulating film on the third insulating film; a source insulating film connected to the source region through an opening provided in the insulating film and the fourth insulating film; The drain region is connected to the electrode through an opening provided in the third insulating film and the fourth insulating film. and a drain electrode connected thereto.

[0016] In the above embodiment, the metal oxide film is selected from the group consisting of In, Zn, Al, Ga, Y, and Sn. It is preferred to have 1 or more.

[0017] In the above embodiment, the rare gas is helium, neon, argon, krypton, xenon, or the like. It is preferred to have one or more of the following:

[0018] In the above embodiment, the third insulating film preferably contains one or more of nitrogen, hydrogen, and fluorine. I wish.

[0019] In the above embodiment, the oxide semiconductor film is a semiconductor layer including In, Zn, and M (M is Al, Ga, In the above embodiment, the oxide semiconductor film preferably has It is preferable that the crystal portion has a c-axis orientation.

[0020] Another embodiment of the present invention is a semiconductor device and a display device according to any one of the above embodiments. Another embodiment of the present invention is a display device including the display device and a touch sensor. In addition, another aspect of the present invention is a display module having any one of the above aspects. The semiconductor device according to any one of claims 1 to 5, the display device, or the display module, and an operation key or and a battery. Effect of the Invention

[0021] According to one embodiment of the present invention, a transistor including an oxide semiconductor can be prevented from fluctuating in electrical characteristics. Furthermore, according to one embodiment of the present invention, It is possible to provide a staggered transistor including an oxide semiconductor. According to one embodiment of the present invention, a transistor including an oxide semiconductor and having high on-state current can be provided. According to one embodiment of the present invention, a transistor having an oxide semiconductor and low off-state current can be provided. According to one embodiment of the present invention, a transistor having reduced power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. can be provided.

[0022] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other effects from the descriptions in the claims, etc. [Brief description of the drawings]

[0023] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Diagram 2] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Diagram 3] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 4] 1 is a cross-sectional view illustrating a semiconductor device. [Diagram 5] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 6] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 7] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 8] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 9] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 10] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 11] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 12] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 13] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 14] FIG. 2 is a diagram for explaining a band structure. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 20] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 21] FIG. 1 is a diagram illustrating a model for forming oxygen vacancies. [Figure 22] FIG. 1 is a diagram illustrating a model for forming oxygen vacancies. [Diagram 23] FIG. 1 is a diagram for explaining a model used in calculations. [Figure 24] FIG. 13 is a diagram for explaining calculation results of the density of states of the VOF model. [Diagram 25] FIG. 1 is a diagram for explaining a model used in calculations. [Figure 26] FIG. 1 is a diagram for explaining a model used in calculations. [Figure 27] 4A to 4C are diagrams for explaining calculation results of the density of states of a crystal model. [Figure 28] FIG. 13 is a diagram for explaining calculation results of the formation energies of VO and VOF. [Figure 29] FIG. 13 is a diagram for explaining calculation results of the formation energies of Fint and Oint. [Diagram 30] FIG. 1 is a diagram for explaining the calculation results of the formation energies and energy differences of reactant and product systems. [Diagram 31] FIG. 1 is a diagram for explaining a model used in calculations. [Diagram 32]A diagram explaining a model of the stable arrangement of impurities (F or H) between the lattices of an InGaZnO4 crystal model. [Diagram 33] A diagram explaining a model of the diffusion path of F in an InGaZnO4 crystal. [Diagram 34] FIG. 1 is a diagram illustrating the calculation results of the change in energy corresponding to the diffusion path of F. [Diagram 35] A diagram explaining a model of the diffusion path of H in an InGaZnO4 crystal. [Diagram 36] FIG. 1 is a diagram illustrating the calculation results of the change in energy corresponding to the diffusion path of H. [Figure 37] 1A and 1B are diagrams illustrating structural analyses of a CAAC-OS and a single crystal oxide semiconductor by XRD, and diagrams showing selected-area electron diffraction patterns of a CAAC-OS. [Figure 38] Cross-sectional TEM image and planar TEM image of CAAC-OS, and their image analysis images. [Figure 39] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Diagram 40] Cross-sectional TEM image of a-like OS. [Diagram 41] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Diagram 42] FIG. 1 is a top view illustrating one embodiment of a display device. [Diagram 43] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Diagram 44] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Diagram 45] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 46] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 47] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 48] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 49] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 50] FIG. 1 illustrates a circuit configuration of a semiconductor device. [Figure 51] 2A and 2B are a diagram for explaining the configuration of a pixel circuit and a timing chart for explaining the operation of the pixel circuit; [Figure 52] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Diagram 53] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 54] 1A and 1B are graphs and circuit diagrams illustrating one embodiment of the present invention. [Figure 55] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 56] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 57] FIG. 1 is a cross-sectional view showing an example of an input / output device. [Figure 58] FIG. 2 is a diagram illustrating a display module. [Figure 59] 1A to 1C are diagrams illustrating electronic devices. [Figure 60] FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Hereinafter, the embodiments will be described with reference to the drawings. The present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily understood by those skilled in the art that various modifications and changes may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0025] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown in the drawings. The drawings are merely schematic illustrations and are not limited to the shapes or values ​​shown in the drawings.

[0026] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the components of the It should be noted that this is added to avoid confusion and is not intended to limit the numbers.

[0027] In addition, in this specification, the words "above" and "below" indicating the position of the components are used. The positional relationship is used for convenience in describing the drawings. The relationship changes depending on the direction in which each component is depicted. The above words and phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0028] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) A current flows through the drain, the channel region, and the source. In this specification and the like, the channel region refers to a region through which a current mainly flows. The flow area.

[0029] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0030] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." In this case, "something that has some electrical effect" includes a case where the device is connected via the "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0031] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0032] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to:

[0033] In this specification and the like, unless otherwise specified, the off-state current refers to the current that occurs when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also called a cut-off state). Unless otherwise specified, for n-channel transistors, V is the voltage between the gate and source When gs is lower than the threshold voltage Vth, the gate and This refers to a state in which the voltage Vgs between the n-channel transistors is higher than the threshold voltage Vth. The off-state current of a transistor is the voltage between the gate and source, Vgs, that is, the threshold voltage, Vt This may refer to the drain current when it is lower than h.

[0034] The off-state current of a transistor may depend on Vgs. The off-state current is I or less if there exists a Vgs value at which the off-state current of the transistor is I or less. The off-state current of a transistor is the current that flows through it in the off-state at a given Vgs. , an off-state at Vgs within a given range or a sufficiently reduced off-current is obtained. In some cases, it may refer to the off-state current at Vgs.

[0035] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -1 3 A, and the drain current at Vgs -0.5 V is 1×10 -19 A and Vg The drain current at s = -0.8 V is 1 × 10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: , or 1×10 when Vgs is in the range of -0.5V to -0.8V -19 A or below Therefore, the off-state current of the transistor is 1×10 -19 There are cases where it is said to be A or lower. The drain current of the transistor is 1×10 -22 A or less Vgs exists. Therefore, the off-state current of the transistor is 1×10 -22 It may be said that it is below A.

[0036] In this specification, the off-state current of a transistor having a channel width W is expressed as It is sometimes expressed as the current value that flows per watt. Also, for a given channel width (for example, 1 μm), In the latter case, the unit of the off-state current is current / length. It may be expressed in units with an element (e.g., A / μm).

[0037] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the operating temperature is room temperature, 60°C, 85°C, 95°C, or 125°C. Or, the reliability of a semiconductor device including the transistor may be guaranteed. The temperature at which the transistor is certified, or the temperature at which a semiconductor device or the like that contains the transistor is used (e.g. For example, the off-state current at any one of temperatures from 5° C. to 35° C. The off-state current of the transistor is I or less at room temperature, 60°C, 85°C, 95°C, 125°C, The temperature at which the reliability of a semiconductor device including the transistor is guaranteed, or the temperature at which the transistor is The temperature at which the semiconductor device containing the transistor is used (for example, between 5°C and 35°C) There exists a value of Vgs at which the off-state current of the transistor at a certain temperature is equal to or less than I. It may refer to.

[0038] The off-state current of a transistor may depend on the voltage Vds between the drain and source In this specification, unless otherwise specified, the off-state current is measured when Vds is 0.1 V, 0.8 V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or In some cases, it indicates the off-state current at 20 V. In other cases, it indicates the off-state current at 20 V. Vds that guarantees the reliability of semiconductor devices, or semiconductor devices including the transistor The term may also refer to the off-state current at Vds used in the transistor off-state. The current is equal to or less than I when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, transistors included Vds that guarantees the reliability of the semiconductor device, etc., in which the transistor is included, or The off-state current of a transistor at Vds used in semiconductor devices is I or less. This may refer to the existence of a Vgs value.

[0039] In the above description of the off-state current, the drain may be read as the source. The current may also refer to the current through the source when the transistor is in the off state.

[0040] In this specification and the like, the term "leak current" may be used to mean the same thing as the "off current." In this specification, the off-state current refers to, for example, the current flowing when a transistor is in an off state. , may refer to the current flowing between the source and drain.

[0041] In this specification, impurities in a semiconductor refer to anything other than the main component that constitutes the semiconductor. For example, an element with a concentration of less than 0.1 atomic percent is an impurity. , DOS (Density of State) is formed in the semiconductor, and carrier The mobility and crystallinity may decrease. In the case of a compound semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements. , Group 2 elements, Group 14 elements, Group 15 elements, transition metals other than the main components, etc., in particular, Hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, for example, oxygen vacancies are formed due to the inclusion of impurities such as hydrogen. In addition, when a semiconductor contains silicon, there are cases where the semiconductor properties are changed. The pure substances include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 1 elements. Group 5 elements, etc.

[0042] (Embodiment 1) In this embodiment, a semiconductor device including a transistor and a manufacturing method of the semiconductor device An example of this will be described with reference to FIGS.

[0043] <1-1. Configuration example 1 of semiconductor device> 1A, 1B, and 1C show examples of a semiconductor device including a transistor. The transistors shown in 1(A), (B), and (C) are staggered type (top-gate structure).

[0044] FIG. 1A is a top view of a transistor 100, and FIG. 1B is a dot-dash diagram of FIG. FIG. 1(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 1(A). In FIG. 1(A), components such as an insulating film 110 are omitted for clarity. In the top view of the transistor, the same structure as that shown in FIG. 1( As in A), some of the components may be omitted. The two directions are called the channel length (L) direction, and the dashed line Y1-Y2 direction is called the channel width (W) direction. This may be the case.

[0045] The transistor 100 shown in FIGS. 1A, 1B, and 1C includes an insulating film 104 on a substrate 102 and , an oxide semiconductor film 108 on the insulating film 104, and an insulating film 110 on the oxide semiconductor film 108. , a metal oxide film 112 on the insulating film 110, a conductive film 114 on the metal oxide film 112, and an insulating film The insulating film 116 is disposed over the insulating film 104, the oxide semiconductor film 108, and the conductive film 114. The oxide semiconductor film 108 has a channel region 108i overlapping with the conductive film 114 and an insulating film 11 6 and a drain region 108d in contact with the insulating film 116. do.

[0046] The insulating film 116 contains one or more of nitrogen, hydrogen, and fluorine. The source region 108s and the drain region 108d are in contact with each other, so that the nitrogen in the insulating film 116, One or more of hydrogen and fluorine are added to the source region 108s and the drain region 108d. The source region 108s and the drain region 108d are formed by adding the above-mentioned elements. In particular, the source region 108s and the drain region 108d are It is preferable that the source region 108s and the drain region 108d contain fluorine. When the oxide semiconductor contains fluorine, the carrier density can be stably increased. The configuration will be described in detail in the second embodiment.

[0047] The transistor 100 also includes an insulating film 118 on the insulating film 116 and an insulating film 116 on the insulating film 117. A conductive layer electrically connected to the source region 108s through an opening 141a provided in the semiconductor substrate 108 is The drain region is connected to the insulating film 120a through an opening 141b provided in the insulating films 116 and 118. and a conductive film 120b electrically connected to the region 108d.

[0048] In this specification and the like, the insulating film 104 is referred to as a first insulating film, and the insulating film 110 is referred to as a second insulating film. The insulating film 116 is referred to as a third insulating film, and the insulating film 118 is referred to as a fourth insulating film. In addition, the conductive film 114 may function as a gate electrode. a functions as a source electrode, and the conductive film 120b functions as a drain electrode. Yes.

[0049] The metal oxide film 112 also has a function of supplying oxygen to the insulating film 110. Since the insulating film 112 has a function of supplying oxygen to the insulating film 110, excess oxygen is not generated in the insulating film 110. Since the insulating film 110 has an excess oxygen region, the oxide Excess oxygen can be supplied into the channel region 108i of the compound semiconductor film 108. Therefore, oxygen vacancies that may be formed in the channel region 108i can be compensated for by excess oxygen. Therefore, a highly reliable semiconductor device can be provided.

[0050] In order to supply excess oxygen to the oxide semiconductor film 108, Excess oxygen may be supplied to the insulating film 104 formed below the insulating film 8. The excess oxygen contained in the insulating film 104 is converted into oxygen in the source region 108s of the oxide semiconductor film 108. , and drain region 108d. When excess oxygen is supplied to the source region 108s and the drain region 108d, The resistance may be high.

[0051] On the other hand, in the structure in which the insulating film 110 formed above the oxide semiconductor film 108 contains excess oxygen, By forming the semiconductor layer 108 in this manner, it is possible to selectively supply excess oxygen only to the channel region 108i. Alternatively, the channel region 108i, the source region 108s, and the drain region 10 After supplying excess oxygen to the source region 108s and the drain region 108d, All you have to do is selectively increase the rear density.

[0052] Note that the metal oxide film 112 only needs to have a function of supplying oxygen to the insulating film 110. The metal oxide film 112 may be insulator, semiconductor, or conductor. In the case of an insulator or a semiconductor, the metal oxide film 112 functions as a gate insulating film, and the insulating film 11 0 and the metal oxide film 112 can form the gate insulating film of the transistor 100. In addition, when the metal oxide film 112 is a semiconductor or a conductor, the metal oxide film 112 serves as a gate electrode. The conductive film 114 and the metal oxide film 112 form a gate electrode of the transistor 100. It can be configured.

[0053] The metal oxide film 112 contains one or more of In, Zn, Al, Ga, Y, and Sn. For example, when the metal oxide film 112 is used as an insulator or a semiconductor, 2 may be aluminum oxide, gallium oxide, or yttrium oxide. In addition, when the metal oxide film 112 is used as a semiconductor or a conductor, the metal oxide film 112 and Examples of the material include indium oxide, tin oxide, zinc oxide, and In-Ga-Zn oxide. That's good.

[0054] The metal oxide film 112 is made of an oxide semiconductor such as In-Ga-Zn oxide. In this case, the metal oxide film 112 is formed by supplying oxygen to the insulating film 110 and then bonding with the conductive film 114. The contact increases the carrier density, or nitrogen, hydrogen, or fluorine is introduced from the insulating film 116. In other words, the oxide semiconductor has an oxide It functions as an oxide conductor (OC). The oxide film 112 can be used as a part of the gate electrode.

[0055] The source region 108s and the drain region 108d of the oxide semiconductor film 108 are Each of them preferably has an element that forms an oxygen vacancy or an element that bonds with the oxygen vacancy. Representative elements that form the oxygen vacancies or that bond with the oxygen vacancies include Hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, rare gases, etc. Representative examples of rare gases are helium, neon, argon, krypton, and xenon. When the element that forms the oxygen vacancy is contained in the insulating film 116, the insulating film The constituent elements of 116 diffuse into the source region 108s and the drain region 108d. The elements that form the oxygen vacancies are added to the source region 108s and the drain region 108s by an impurity addition process. The dopant is added to the dopant region 108d.

[0056] When an impurity element is added to an oxide semiconductor film, a bond between a metal element and oxygen in the oxide semiconductor film is formed. The bond is broken, and oxygen vacancies are formed. Alternatively, an impurity element is added to the oxide semiconductor film. Then, oxygen that has been bonded to a metal element in the oxide semiconductor film is bonded to an impurity element, and the metal element As a result, oxygen is released from the oxide semiconductor film, and oxygen vacancies are formed. The carrier density increases and the conductivity becomes higher.

[0057] In this manner, in the semiconductor device of one embodiment of the present invention, By supplying excess oxygen to the insulating film 110, the channel region of the oxide semiconductor film 108 In addition, the insulating film 116 can selectively supply excess oxygen to the insulating film 108i. By containing one or more of silicon, silicon dioxide, or fluorine, the source region 108s in contact with the insulating film 116, In addition, it is possible to selectively increase the carrier density in the drain region 108d. As a result, a semiconductor device with excellent electrical characteristics can be provided.

[0058] Next, the components of the semiconductor device shown in FIGS. 1(A), 1(B), and 1(C) will be described in detail.

[0059] [substrate] Various substrates can be used as the substrate 102 and are not limited to a specific one. Examples of the substrate include a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), a SO I substrate, glass substrate, quartz substrate, plastic substrate, metal substrate, stainless steel substrate , Substrate with Stainless Steel Foil, Tungsten Substrate, Tungsten Foil A substrate having a fibrous material, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film Examples of glass substrates include barium borosilicate glass and aluminophore. silicate glass, or soda lime glass. Flexible substrates, lamination films Examples of the materials and base films are as follows: Polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulf For example, there are plastics such as polyether ether sulphate (PES). Synthetic resins, etc. Examples include polypropylene, polyester, and polyfluorine. Examples of the polyvinyl chloride include polyvinyl chloride and polyvinyl chloride. Examples of the polyamide and polyimide are , aramid, epoxy, inorganic deposition film, paper, etc. In particular, semiconductor substrates, By manufacturing transistors using single crystal substrates or SOI substrates, etc., Small size transformers with small variations in size, shape, and current capability. When a circuit is constructed using such transistors, This makes it possible to reduce the power consumption of the circuit or to increase the degree of circuit integration.

[0060] In addition, a flexible substrate is used as the substrate 102, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the transistor. After a semiconductor device is partially or entirely completed on the substrate, the semiconductor device is separated from the substrate 102 and another In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The transfer can also be performed on a flexible substrate. The above-mentioned release layer may be, for example, a tungsten film and a silicon oxide film. A laminated structure of inorganic films with silicon films, or an organic resin film such as polyimide is formed on the substrate The above-mentioned configurations and the like can be used.

[0061] An example of a substrate on which a transistor is transferred is a substrate on which the above-mentioned transistor is formed. In addition to the substrates that can be used, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, Rubber substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, hemp), synthetic fibers (nylon) , polyurethane, polyester) or regenerated fibers (acetate, cupra, rayon, These substrates include recycled polyester, leather substrates, and rubber substrates. By using this, it is possible to form transistors with good characteristics and low power consumption. It is possible to form, manufacture devices that are less likely to break, are heat resistant, or are lighter or thinner. .

[0062] [First insulating film] The insulating film 104 can be formed by sputtering, CVD, vapor deposition, pulsed laser deposition ( The insulating film 104 can be formed by appropriately using a photolaser laser deposition (PLD) method, a printing method, a coating method, or the like. For example, a single layer or a stacked layer of an oxide insulating film or a nitride insulating film can be formed. Note that in order to improve the interface characteristics with the oxide semiconductor film 108, In this case, at least a region in contact with the oxide semiconductor film 108 is preferably formed using an oxide insulating film. It is preferable to use an oxide insulating film that releases oxygen by heating as the insulating film 104. Then, oxygen contained in the insulating film 104 is transferred to the oxide semiconductor film 108 by heat treatment. It is possible.

[0063] The thickness of the insulating film 104 is 50 nm or more, or 100 nm or more and 3000 nm or less, or The thickness of the insulating film 104 can be set to 200 nm or more and 1000 nm or less. This can increase the amount of oxygen released from the insulating film 104 and also can prevent the insulating film 104 and the oxide semiconductor from The interface state at the interface with the conductive film 108 and the channel region 1 of the oxide semiconductor film 108 It is possible to reduce the oxygen vacancies contained in 08i.

[0064] The insulating film 104 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitrogen. Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The insulating film may be a single layer or a stacked layer. The layer structure of the silicon nitride film and the silicon oxynitride film is used as the layer 104. The insulating film 104 has a laminated structure, with a silicon nitride film on the lower layer and an oxynitride film on the upper layer. By using a silicon film, oxygen can be efficiently introduced into the oxide semiconductor film 108. Cut.

[0065] [Oxide semiconductor film] The oxide semiconductor film 108 is an In-M-Zn oxide (M is Al, Ga, Y, or Sn). The oxide semiconductor film 108 is formed of a metal oxide such as In-Ga oxide, In-Zn oxide may also be used.

[0066] In addition, when the oxide semiconductor film 108 is an In-M-Zn oxide, the atomic ratio of In to M is When the sum of In and M is 100 atomic %, In is higher than 25 atomic %. , M is less than 75 atomic %, or In is higher than 34 atomic %, and M is 66a tomic% or less.

[0067] In addition, the oxide semiconductor film 108 has an energy gap of 2 eV or more, or 2.5 eV or more. It is preferably 3 eV or more.

[0068] The thickness of the oxide semiconductor film 108 is 3 nm to 200 nm, preferably 3 nm to 100 nm. 00 nm or less, and more preferably 3 nm or more and 60 nm or less.

[0069] In the case where the oxide semiconductor film 108 is an In-M-Zn oxide, the In-M-Zn oxide is formed. The atomic ratio of the metal elements in the sputtering target used for this purpose is In≧M, Zn≧M. It is preferable that the atomic ratio of the metal elements in such a sputtering target and In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn =2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2:1:3, I n:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5:1 Note that the atomic ratio of the oxide semiconductor film 108 to be formed is preferably 1:7 or the like. The atomic ratio of the metal elements contained in the sputtering target is about ±40%. For example, the atomic ratio of In:Ga is When the atomic ratio of In:Zn is 4:2:4.1, the atomic ratio of the oxide semiconductor film to be formed is In: In some cases, the Ga:Zn ratio is approximately 4:2:3. Also, as a sputtering target, When the atomic ratio of In:Ga:Zn=5:1:7 is used, the oxide semiconductor film to be formed has The atomic ratio may be approximately In:Ga:Zn=5:1:6.

[0070] In addition, the oxide semiconductor film 108 contains silicon or carbon, which is one of the Group 14 elements. When the oxide semiconductor film 108 is filled with oxygen, oxygen vacancies are increased and the oxide semiconductor film 108 may become an n-type film. In particular, in the channel region 108i, the concentration of silicon or carbon is set to 2×10 18 a toms / cm 3 or less, or 2×10 17 atoms / cm 3 It can be As a result, the transistor has electrical characteristics in which the threshold voltage is positive (normally off characteristics). The concentration of silicon or carbon mentioned above is, for example, two Secondary Ion Mass Spectroscopy (SIMS) It can be measured by fluoroscopy.

[0071] In addition, in the channel region 108i, an alkali metal ion is obtained by secondary ion mass spectrometry. The concentration of metal or alkaline earth metal is 1×10 18 atoms / cm 3 Less than or equal to 2 ×1016 atoms / cm 3 It can be: Alkali metals and alkaline earths When a metal combines with an oxide semiconductor, carriers may be generated, causing the transistor to turn off. For this reason, the current may increase. It is preferable to reduce the concentration of alkaline earth metals. The device has electrical characteristics in which the lowest voltage is positive (also called normally-off characteristics).

[0072] In addition, when nitrogen is contained in the channel region 108i, electrons that act as carriers are generated, and The carrier density increases and the semiconductor becomes n-type. As a result, the oxide semiconductor containing nitrogen A transistor using a thin film is likely to have normally-on characteristics. In the 08i, it is preferable that nitrogen is reduced as much as possible. For example, secondary ions The nitrogen concentration obtained by mass spectrometry was 5×10 18 atoms / cm 3 Let's say the following: stomach.

[0073] In addition, by reducing the impurity elements in the channel region 108i, Therefore, in the channel region 108i, the carrier density can be reduced. Carrier density is 1×10 17 / cm 3 or less, or 1×10 15 / cm 3 Less than or equal to 1 ×10 13 / cm 3 or less, or 1×10 11 / cm 3 It can be as follows:

[0074] The channel region 108i is an oxide semiconductor film having a low impurity concentration and a low density of defect states. By using such a material, a transistor having better electrical characteristics can be manufactured. Here, a high-purity pure silicon has a low impurity concentration and a low defect level density (few oxygen vacancies). Alternatively, they are called pure or substantially pure. A highly intrinsic or substantially highly purified intrinsic oxide semiconductor has a small carrier generation source; Therefore, the carrier density can be reduced in the oxide semiconductor film. The transistor in which the junction region is formed has electrical characteristics in which the threshold voltage is positive (normal Also known as off-state characteristics.) Also, high purity intrinsic or substantially high purity intrinsic Since the oxide semiconductor film has a low density of defect states, the oxide semiconductor film may also have a low density of trap states. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a significantly low off-state current. Therefore, a channel region is formed in the oxide semiconductor film. Such a transistor may have small fluctuations in electrical characteristics and become a highly reliable transistor. do.

[0075] On the other hand, the source region 108s and the drain region 108d are in contact with the insulating film 116. The source region 108s and the drain region 108d are in contact with the insulating film 116. 116 to the source region 108s and the drain region 108d, one or more of hydrogen, nitrogen, and fluorine are Since the top is doped, the carrier density is increased.

[0076] The oxide semiconductor film 108 may have a non-single crystal structure. CAAC-OS (C Axis Aligned Crystalline Ox ide Semiconductor), polycrystalline structure, microcrystalline structure (described later), or amorphous structure Among non-single crystal structures, the amorphous structure has the highest defect level density and CAAC -OS has the lowest defect state density.

[0077] Note that the oxide semiconductor film 108 may have an amorphous structure, a microcrystalline structure, or a polycrystalline structure. a monolayer film having two or more of a CAAC-OS region, a CAAC-OS region, and a single crystal structure region, or The film may have a laminated structure.

[0078] In the oxide semiconductor film 108, the channel region 108i and the source region 108s The crystallinity of the oxide semiconductor film 108c may be different from that of the drain region 108d. In the case of 108, the source region 108s and the drain region 108 are closer to each other than the channel region 108i. The source region 108s and the drain region 108d may have a lower crystallinity. When an impurity element is added to the source region 108s and the drain region 108d, This is because damage occurs and the crystallinity decreases.

[0079] [Second insulating film] The insulating film 110 functions as a gate insulating film of the transistor 100. The oxide semiconductor film 100 has a function of supplying oxygen to the oxide semiconductor film 108, particularly to the channel region 108i. For example, the insulating film 110 may be a single layer or a stack of an oxide insulating film or a nitride insulating film. In order to improve interface characteristics with the oxide semiconductor film 108, In the insulating film 110, at least a region in contact with the oxide semiconductor film 108 is made of an oxide insulating material. The insulating film 110 is preferably formed using a film such as silicon oxide or oxynitride. Silicon oxide, silicon nitride, silicon oxide nitride, silicon nitride, or the like may be used.

[0080] The thickness of the insulating film 110 is 5 nm or more and 400 nm or less, or 5 nm or more and 300 nm or less. m or less, or from 10 nm to 250 nm.

[0081] In addition, it is preferable that the insulating film 110 has few defects. (ESR: Electron Spin Resonance) observed signal For example, the above signal is observed at a g value of 2.001. The signal caused by the E' center is shown in Fig. 1. The E' center is a silicon dummy The insulating film 110 is a material that suppresses the spin of the signal caused by the E' center. The density of 17 spins / cm 3 Less than or equal to 5×10 16 spins / cm 3 A silicon oxide film or a silicon oxynitride film as described below may be used.

[0082] In addition to the above-mentioned signals, the insulating film 110 also contains signals due to nitrogen dioxide (NO2). A null may be observed. The signal is divided into three signals due to the nuclear spin of N. The g value of each is between 2.037 and 2.039 (this is the first signal). , g value is 2.001 to 2.003 (second signal), and g value is 1.96 It is observed between 4 and 1.966 (referred to as the third signal).

[0083] For example, the insulating film 110 may be a spin density film for signals caused by nitrogen dioxide (NO2). But 1×10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Less than It is preferred to use a velum.

[0084] In addition, nitrogen oxides (NO x , x is greater than 0 and less than or equal to 2, preferably or 1 to 2, typically NO or NO2) forms a level in the insulating film 110. The level is located within the energy gap of the oxide semiconductor film 108. When nitrogen oxide diffuses to the interface between the insulating film 110 and the oxide semiconductor film 108, the state Electrons may be trapped on the insulating film 110 side. As a result, the trapped electrons However, since the oxide semiconductor film 108 is not formed on the insulating film 110, the thickness of the transistor is reduced. This causes the low-value voltage to shift in the positive direction.

[0085] Therefore, a film containing a small amount of nitrogen oxide is used as the insulating film 110. Therefore, if a film that releases less nitrogen oxide is used as the insulating film 110, the threshold of the transistor Therefore, the shift in the low-value voltage can be reduced.

[0086] As an insulating film that emits a small amount of nitrogen oxide, for example, a silicon oxynitride film is used. The silicon oxynitride film was analyzed by thermal desorption spectroscopy (TDS). Desorption Spectroscopy (DAS) showed that the amount of nitrogen oxides released was This is a membrane that releases a large amount of ammonia, typically 1×10 18 pieces / cm 3 5×10 or more 19 pieces / cm 3 The amount of ammonia released is as follows: The temperature of the heat treatment in TDS is 50°C or more and 650°C or less, or 50°C or more and 550°C or less. The total amount is within the range below.

[0087] Nitrogen oxides react with ammonia and oxygen during the heat treatment, resulting in the release of ammonia. By using an insulating film with a high outflow rate, nitrogen oxides are reduced.

[0088] When the insulating film 110 was measured by SIMS, the nitrogen concentration in the film was 6×10 20 ato ms / cm 3 It is preferable that the following is true:

[0089] The insulating film 110 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate (HfAl x O y N z ), and high-k materials such as hafnium oxide are used to The gate leakage of the transistor can be reduced.

[0090] [Metal oxide film] The metal oxide film 112 includes one or more of In, Zn, Al, Ga, Y, and Sn. Specific examples of materials that can be used for the metal oxide film 112 include indium oxide and zinc oxide. , Aluminum oxide, Gallium oxide, Yttrium oxide, Tin oxide, In-Zn oxide, Examples of the oxide include In-Ga oxide, In-Sn oxide, and In-Ga-Zn oxide. In addition, when an insulator or a semiconductor is used as the metal oxide film 112, aluminum oxide In addition, when a semiconductor or a conductor is used as the metal oxide film 112, In this case, it is preferable to use In-Ga-Zn oxide.

[0091] The metal oxide film 112 may be formed by sputtering or atomic layer deposition (ALD). It is preferable to use a deposition method. After the metal oxide film 112 is formed, an oxygen addition process is performed. By the oxygen addition treatment, excess oxygen is added to the metal oxide film 112 and the insulating film 110. The oxygen addition process may be performed by ion implantation, ion doping, etc. A deposition method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

[0092] [Third insulating film] The insulating film 116 contains at least one of nitrogen, hydrogen, and fluorine. For example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride and silicon oxynitride. The insulating layer can be formed using silicon nitride fluoride, silicon nitride fluoride, or the like. The hydrogen concentration in the film 116 is 1×10 22 atoms / cm 3 It is preferable that the above is The insulating film 116 covers the source region 108s and the drain region 108s of the oxide semiconductor film 108. Therefore, the source region 108s and the drain region 108d are in contact with the insulating film 116. The impurity (nitrogen, hydrogen, or fluorine) concentration in the in-region 108d becomes high, and the source region This can increase the carrier density in the drain region 108s and the drain region 108d.

[0093] In the present embodiment, the insulating film 116 is made of a mixture of silicon tetrafluoride (SiF4) and nitrogen ( N2) is used as the source gas to form a silicon fluoride nitride film. Silicon fluoride oxide (SiF4) and dinitrogen monoxide (N2O) are used as raw material gases to produce silicon fluoride oxide. A coating film may be formed.

[0094] [Fourth insulating film] The insulating film 118 is formed as a single layer or a stack of an oxide insulating film or a nitride insulating film. The insulating film 118 can be made of, for example, silicon oxide, silicon oxynitride, or silicon nitride. Silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide or G It is sufficient to use a-Zn oxide or the like, and the film can be provided as a single layer or a multilayer.

[0095] The insulating film 118 functions as a barrier film against hydrogen, water, and the like from the outside. It is preferable that

[0096] The thickness of the insulating film 118 is 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less. m or less.

[0097] [Conductive film] The conductive films 114, 120a, and 120b can be formed by sputtering, vacuum deposition, pulse deposition, or the like. It can be formed by using a laser deposition (PLD) method, a thermal CVD method, etc. 114, 120a, and 120b are, for example, aluminum, chromium, copper, tantalum, Metal elements selected from titanium, molybdenum, nickel, iron, cobalt, and tungsten, or or an alloy containing the above-mentioned metal elements or an alloy combining the above-mentioned metal elements. It can be formed by using one or more of manganese and zirconium. A selected metal element may be used. The conductive films 114, 120a, and 120b are each a single layer. For example, a silicon-containing aluminum film may be used. Single layer structure, single layer structure of copper film containing manganese, two-layer structure with titanium film laminated on aluminum film Structure: Two-layer structure with titanium film laminated on titanium nitride film; Tungsten film on titanium nitride film A two-layer structure in which a tantalum nitride film is laminated on a tungsten nitride film or a tungsten nitride film is laminated on a tantalum nitride film or a tungsten nitride film is laminated on a tungsten film. A two-layer structure in which a copper film is laminated on a copper film containing manganese; a two-layer structure in which a copper film is laminated on a titanium film A two-layer structure is formed by laminating a titanium film and an aluminum film on the titanium film. A three-layer structure in which a titanium film is formed on top, a copper film is laminated on a copper film containing manganese, and then a copper film is laminated on top of that. There are three-layer structures in which a copper film containing manganese is formed on the aluminum. One selected from the group consisting of tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film made by combining a plurality of layers, or a nitride film may be used.

[0098] The conductive films 114, 120a, and 120b are made of indium tin oxide (InT in Oxide (ITO), indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide containing silicon, indium zinc oxide, indium tin oxide containing silicon (I By using a conductive material with light transmission such as n-Sn-Si oxide (also called ITSO), In addition, the conductive material having the light-transmitting property and the metal element may be laminated to form a laminate structure. It is also possible.

[0099] Alternatively, the conductive film 114 may be made of the above-described oxide conductor (OC). For example, The conductive film 114 may have a single-layer structure of an oxide conductor (OC), a single-layer structure of a metal film, or Examples of the structure include a laminated structure of an oxide conductor (OC) and a metal film.

[0100] Note that the conductive film 114 may have a single-layer structure of a metal film having a light-shielding property or an oxide conductor ( When a laminated structure of an OC and a metal film having a light-shielding property is used, the conductive film 114 is formed below the conductive film 114. This is preferable because it can shield the channel region 108i that is to be covered by the insulating film 104 from light.

[0101] The thickness of the conductive films 114, 120a, and 120b is 30 nm or more and 500 nm or less. Alternatively, it may be 100 nm or more and 400 nm or less.

[0102] <1-2. Configuration example 2 of semiconductor device> Next, regarding the semiconductor device having a different structure from that shown in FIG. 1(A)(B)(C), Explain using B)(C).

[0103] FIG. 2A is a top view of a transistor 100A, and FIG. 2B is a cross-sectional view of a portion of FIG. 2A. 2(C) is a cross-sectional view taken along dashed line X1-X2, and FIG. 2(C) is a cross-sectional view taken along dashed line Y1-Y2 in FIG. 2(A). FIG.

[0104] The transistor 100A shown in FIGS. 2A, 2B, and 2C includes a conductive layer formed on a substrate 102. A conductive film 106, an insulating film 104 on the conductive film 106, and an oxide semiconductor film 10 on the insulating film 104. 8, an insulating film 110 on the oxide semiconductor film 108, and a metal oxide film 112 on the insulating film 110. The conductive film 114 on the metal oxide film 112, the insulating film 104, the oxide semiconductor film 108, and the conductive film 114 are The oxide semiconductor film 108 has an insulating film 116 over the conductive film 114. 4, a source region 108s in contact with the insulating film 116, and and a drain region 108d in contact with the film 116.

[0105] The transistor 100A has the same structure as the transistor 100 described above, and further includes a conductive film 106 and , and an opening 143.

[0106] The opening 143 is provided in the insulating films 104 and 110 and the metal oxide film 112 . In addition, the conductive film 106 is electrically connected to the conductive film 114 through the opening 143 . Therefore, the conductive film 106 and the conductive film 114 are applied with the same potential. Alternatively, different potentials may be applied to the conductive film 106 and the conductive film 114 without providing the potential difference. The conductive film 106 may be used as a light-shielding film without providing the opening 143. By forming the first insulating layer 06 from a light-shielding material, the channel region 108i is protected from the light irradiated from below. Note that the conductive film 106 can be used for the conductive film 114. The same materials that can be used for the above-mentioned purposes can be used.

[0107] In the case of the transistor 100A, the conductive film 106 is a first gate electrode ( The conductive film 114 functions as a second gate electrode ( The insulating film 104 functions as a first gate electrode. The insulating film 110 functions as a first gate insulating film. do.

[0108] In this way, the transistor 100A shown in FIGS. Unlike the transistor 100, the oxide semiconductor film 108 has conductive layers functioning as gate electrodes above and below it. As shown in the transistor 100A, the semiconductor The device may be provided with multiple gate electrodes.

[0109] As shown in FIG. 2C, the oxide semiconductor film 108 functions as a first gate electrode. and a conductive film 114 functioning as a second gate electrode. The gate electrode is sandwiched between two conductive films that function as gate electrodes.

[0110] The length of the conductive film 114 in the channel width direction is longer than that of the oxide semiconductor film 108. The length of the oxide semiconductor film 108 in the channel width direction is longer than the length of the insulating film 110. The conductive film 114 is covered with the metal oxide film 112. The opening 106 is provided in the insulating film 104, the insulating film 110, and the metal oxide film 112. Since the oxide semiconductor film 108 is connected to the first insulating film 43, one of the side surfaces in the channel width direction of the oxide semiconductor film 108 is It faces the conductive film 114 via the insulating film 110 .

[0111] In other words, in the channel width direction of the transistor 100A, the conductive film 106 and the conductive The film 114 is formed by filling the opening 1 provided in the insulating film 104, the insulating film 110, and the metal oxide film 112. 43, and through the insulating film 104, the insulating film 110, and the metal oxide film 112. The oxide semiconductor film 108 is surrounded by the insulating film 104 .

[0112] With such a structure, the oxide semiconductor film 10 included in the transistor 100A 8 is a conductive film 106 functioning as a first gate electrode and a conductive film 108 functioning as a second gate electrode. The transistor 100A can be electrically surrounded by the electric field of the conductive film 114. Thus, a channel region is formed by the electric field of the first gate electrode and the second gate electrode. The device structure of the transistor that electrically surrounds the oxide semiconductor film is called Surround. This can be called an ed channel (S-channel) structure.

[0113] Since the transistor 100A has an S-channel structure, the conductive film 106 or The conductive film 114 effectively applies an electric field for inducing a channel to the oxide semiconductor film 108. This improves the current drive capability of the transistor 100A and provides a high on-state current. It is also possible to obtain high on-current characteristics. The transistor 100A can be miniaturized. The semiconductor film 108 is surrounded by the conductive film 106 and the conductive film 114. This increases the mechanical strength of the transistor 100A.

[0114] Note that an opening in the oxide semiconductor film 108 in the channel width direction of the transistor 100A An opening different from opening 143 may be formed on the side where portion 143 is not formed.

[0115] As shown in the transistor 100A, a transistor is formed with a semiconductor film sandwiched therebetween. In the case of a pair of gate electrodes, one of which is connected to a signal A and the other is connected to a signal B. A fixed potential Vb may be applied to the gate electrodes. A signal A may be applied to one gate electrode and a signal B may be applied to the other gate electrode. A signal B may be applied to one of the gate electrodes. A fixed potential V a, and the other gate electrode may be given a fixed potential Vb.

[0116] The signal A is, for example, a signal for controlling the conductive state or the non-conductive state. It is a digital signal that can take two types of potential: potential V1 or potential V2 (V1>V2). For example, the potential V1 may be a high power supply potential and the potential V2 may be a low power supply potential. Signal A may be an analog signal.

[0117] The fixed potential Vb is, for example, a potential for controlling the threshold voltage VthA of a transistor. The fixed potential Vb may be the potential V1 or the potential V2. This is preferable because it is not necessary to provide a separate potential generating circuit for generating the fixed potential Vb. The fixed potential Vb may be different from the potential V1 or the potential V2. In some cases, the threshold voltage VthA can be increased. As a result, the gate-source voltage V By reducing the drain current when gs is 0V, the leakage current of the circuit having the transistor is reduced. For example, the fixed potential Vb may be lower than the low power supply potential. In some cases, the threshold voltage VthA can be lowered by increasing the fixed potential Vb. As a result, the drain current is improved when the gate-source voltage Vgs is at a high power supply potential, and the transistor For example, the fixed potential Vb can be reduced to a low potential. It may be higher than the source potential.

[0118] The signal B is, for example, a signal for controlling the conductive state or the non-conductive state. It is a digital signal that can take two types of potential: potential V1, potential V2, or potential V3 (V3>V4). For example, the potential V3 may be a high power supply potential and the potential V4 may be a low power supply potential. Signal B may be an analog signal.

[0119] If signal A and signal B are both digital signals, signal B will have the same digital value as signal A. In this case, the on-current of the transistor is improved, and the transistor In this case, the operation speed of the circuit having the potential V1 and The potential V2 may be different from the potentials V3 and V4 in the signal B. For example, The gate insulating film corresponding to the gate to which signal B is input is the gate insulating film corresponding to the gate to which signal A is input. If the gate insulating film is thicker than the gate insulating film, the potential amplitude of signal B (V3-V4) is It may be set to be larger than (V1-V2). This will allow the transistor to be in a conducting state or The effect of signal A on the non-conducting state is set to the same degree as the effect of signal B on the non-conducting state. It may be possible to do so.

[0120] If signal A and signal B are both digital signals, signal B has a different digital value than signal A. In this case, the transistors are controlled by signals A and B separately. For example, a transistor can be In the case of the channel type, when signal A is at potential V1 and signal B is at potential V3, When only the signal A is in a conductive state, or when the signal B is at a potential V4, If only one transistor is non-conducting, a single transistor can function as a NAND circuit or a NOR circuit. In addition, the signal B is a signal for controlling the threshold voltage VthA. For example, the signal B may be a period during which a circuit having a transistor is in operation. The signal B may be a signal having a different potential during a period when the circuit is not operating. In this case, signal B may be a signal with a different potential depending on the operation mode of the circuit. In some cases, the potential may not switch as frequently as

[0121] When signal A and signal B are both analog signals, signal B is an analog signal with the same potential as signal A. analog signal obtained by multiplying the potential of signal A by a constant, or adding a constant to the potential of signal A Alternatively, it may be an analog signal obtained by subtracting the signal. In this case, the on-current of the transistor is The signal B may be increased in response to the signal P, thereby increasing the operating speed of a circuit having a transistor. A may be a different analog signal. In this case, the transistor control is signal A and signal B can be performed separately, which may result in higher functionality.

[0122] Signal A may be a digital signal and signal B may be an analog signal. Or, signal A may be It is also possible that signal A is an analog signal and signal B is a digital signal.

[0123] When a fixed potential is applied to both gate electrodes of a transistor, the transistor is For example, a transistor can function as an n-channel transistor. In the case of a transistor type, the fixed potential Va or the fixed potential Vb can be increased (or decreased). In some cases, the effective resistance of the resistor can be lowered (higher). By making both Vb high (low), a transistor with only one gate In some cases, a lower (higher) effective resistance may be obtained.

[0124] The other configurations of the transistor 100A are the same as those of the transistor 100 shown above. and has a similar effect.

[0125] <1-3. Configuration example 3 of semiconductor device> Next, regarding the semiconductor device having a different structure from that shown in FIG. 2(A), (B), and (C), the semiconductor device shown in FIG. This will be explained using:

[0126] 3A and 3B are cross-sectional views of a transistor 100B, and FIGS. 5(A)(B), 6(A)(B), and 7( 8A and 8B are cross-sectional views of a transistor 100D, and 9(A) and (B) are cross-sectional views of a transistor 100F. In addition, the transistors 100B, 100C, 100D, The top view of the transistor 100E and the transistor 100F is the same as that of the transistor 100 shown in FIG. Since this is the same as the resistor 100A, the explanation will be omitted here.

[0127] The transistor 100B shown in FIGS. 3A and 3B is similar to the transistor 100A shown above. The shapes of the conductive film 114, the metal oxide film 112, and the insulating film 110 are different. In the transistor 100A, the conductive film 114, the metal oxide film 112, and the insulating film 110 are tapered. In contrast, the transistor 100B has a conductive film 114, a metal oxide film 112, and an insulating film 113. The insulating film 110 is rectangular. In a cross section in the panel length (L) direction, the upper end of the conductive film 114 is closer to the lower end of the insulating film 110 than the In other words, the side edge of the insulating film 110 is closer to the inside than the side edge of the conductive film 114. On the other hand, the transistor 100B is located on the outside in the channel length (L) direction of the transistor. In the cross section in the axial direction, the upper end of the conductive film 114 and the lower end of the insulating film 110 are at approximately the same position. is formed.

[0128] For example, the conductive film 114, the metal oxide film 112, and the insulating film 110 are processed using the same mask. The structure of the transistor 100B is obtained by processing the same all at once using a dry etching method. It can be said that:

[0129] By adopting a structure such as that of the transistor 100A, the coverage of the insulating film 116 is improved. On the other hand, by adopting a configuration like the transistor 100B, the source region 10 Since the ends of the drain region 108s and the conductive film 114 are formed at approximately the same positions, This is preferable.

[0130] The transistor 100C shown in FIGS. 4A and 4B is similar to the transistor 100A shown above. The shapes of the conductive film 114, the metal oxide film 112, and the insulating film 110 are different. In the transistor 100C, the conductive film 114, the metal oxide film 112, and the insulating film 110 are inverted tapered. In other words, the transistor 100C has a channel length (L) direction In the cross section of FIG. 1, the upper end of the conductive film 114 is formed outside the lower end of the insulating film 110. .

[0131] For example, the conductive film 114, the metal oxide film 112, and the insulating film 110 are processed using the same mask. Then, the structure of the transistor 100C is formed by processing them all at once using a wet etching method. It can be constructed as follows.

[0132] In addition, by configuring the transistor 100C, a conductor that functions as a gate electrode A part of the source region 108s and the drain region 108d is provided inside the conductive film 114. Note that in a region where the conductive film 114 overlaps with the source region 108s and The region where the drain region 108d overlaps is called an overlap region (also called an Lov region). The Lov region overlaps with the conductive film 114 that functions as a gate electrode. The resistance of the LOV region is lower than that of the channel region 108i. By this, the channel region 108i, the source region 108s, and the drain region 108d Since no high resistance region is formed between the become.

[0133] The transistor 100D shown in FIGS. 5(A) and 5(B) is similar to the transistor 100A shown above. The shapes of the conductive film 114, the metal oxide film 112, and the insulating film 110 are different. In the cross section of the transistor 100D in the channel length (L) direction, the conductive film 114 The lower end of the conductive film 114 is located at a different position from the upper end of the metal oxide film 112. It is formed inside the upper end of metal oxide film 112 .

[0134] For example, the structure of the transistor 100D includes a conductive film 114, a metal oxide film 112, and The conductive film 1 and the insulating film 110 can be processed using the same mask. A mask is formed on the conductive film 114, and the conductive film 114 is etched by wet etching using the mask. Thereafter, the metal oxide film 112 and the insulating film 110 are processed by a dry etching method. This results in the structure of transistor 100D.

[0135] In addition, by using the structure of the transistor 100D, the region 1 Region 108f may be formed by forming channel region 108i and source region 108i. 08s and between the channel region 108i and the drain region 108d.

[0136] The region 108f functions as either a high resistance region or a low resistance region. The resistive region is a conductive region that has a resistance equivalent to that of the channel region 108i and functions as a gate electrode. This is a region where the film 114 does not overlap. When the region 108f is a high resistance region, the region 108f is This region functions as a so-called offset region. When the region 108f functions as an offset region, In order to suppress a decrease in the on-state current of the transistor 100D, the channel length (L ) direction, the region 108f may be set to 1 μm or less.

[0137] The low resistance region is a region having a lower resistance than the channel region 108i and a The region 108f is a low resistance region. In this case, the region 108f is a so-called LDD (Lightly Doped Drain) region. When the region 108f functions as an LDD region, the drain This allows the electric field in the drain region to be relaxed, which reduces the threshold voltage of the transistor caused by the electric field in the drain region. This can reduce fluctuations in the value voltage.

[0138] In addition, when the region 108f is used as an LDD region, for example, One or more of nitrogen, hydrogen, and fluorine are supplied to 8f, or the insulating film 110 and the metal oxide film By using 112 as a mask, impurity elements are added from above the metal oxide film 112, The impurity element is added to the oxide semiconductor film 108 through the metal oxide film 112 and the insulating film 110. As a result, a region 108f is formed.

[0139] The transistor 100D shown in FIGS. 6A and 6B is the same as the transistor 100 shown in FIGS. The transistor 100D shown in FIGS. In a cross section in the channel length (L) direction of the transistor, the lower end of the conductive film 114 and the metal oxide The lower end of the film 112 is located at a different position from the lower end of the insulating film 110. The upper end of the metal oxide film 112 is formed inside the upper end of the metal oxide film 112, and the lower end of the metal oxide film 112 is formed inside the upper end of the metal oxide film 112. It is formed inside the upper end of the film 110 .

[0140] The transistor 100D shown in FIGS. 7A and 7B is the same as the transistor 100 shown in FIGS. The transistor 100D shown in FIGS. In a cross section in the channel length (L) direction of the transistor, the lower end of the conductive film 114 and the metal oxide The upper end of the metal oxide film 112 is formed at approximately the same position as the upper end of the insulating film 11. It is formed inside the upper end of 0.

[0141] The transistor 100E shown in FIGS. 8A and 8B is the same as the transistor 100A shown above. The shapes of the metal oxide film 112 and the insulating film 110 are different. In the cross section in the channel length (L) direction of the transistor, the lower end of the conductive film 114 is made of gold. It is formed outside the upper end of metal oxide film 112 .

[0142] For example, the structure of the transistor 100E is a conductive film 114, a metal oxide film 112, and The insulating film 110 and the conductive film 111 can be formed by processing the conductive film 111 and the insulating film 110 using the same mask. A mask is formed on the conductive film 114, and the conductive film 114 is removed by dry etching using the mask. Then, the upper surface of the metal oxide film 112 and the insulating film 110 is etched using an etchant or the like. By performing etching and side etching, transistor 1 00E structure.

[0143] In addition, by configuring the transistor 100E, the same A Lov region can be provided.

[0144] The transistor 100F shown in FIGS. 9(A) and 9(B) has a substantially the same structure as the transistor 100A shown above. In contrast, the insulating film 122 that functions as a planarizing insulating film is provided on the insulating film 118. The rest of the configuration is the same as that of the transistor 100A shown above. , has a similar effect.

[0145] The insulating film 122 has a function of planarizing unevenness due to transistors and the like. The film 122 may be made of any insulating material, and may be made of an inorganic or organic material. The inorganic material may be a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a nitride Examples of the organic material include a silicon film, an aluminum oxide film, and an aluminum nitride film. Examples of the material include photosensitive resin materials such as acrylic resin and polyimide resin. .

[0146] In addition, in FIG. 9(A) and (B), the shape of the opening in the insulating film 122 is opening 1. However, the shape is not limited to this. For example, the opening 141 a, 141b, or may be smaller than the openings 141a, 141b. stomach.

[0147] In addition, in FIG. 9(A) and (B), conductive films 120a and 120b are provided on an insulating film 122. However, the present invention is not limited to this. For example, a conductive film 120 on an insulating film 118 Alternatively, a configuration may be adopted in which the conductive films 120a and 120b are provided, and an insulating film 122 is provided on the conductive films 120a and 120b. good.

[0148] <1-4. Configuration example 4 of semiconductor device> Next, regarding a semiconductor device having a different structure from that shown in FIG. 2(A), (B), and (C), FIG. 10 to FIG. 13 will be used to explain.

[0149] 10(A) and (B) are cross-sectional views of a transistor 100G, and FIGS. 12A and 12B are cross-sectional views of the transistor 100J. 13A and 13B are cross-sectional views of a transistor 100K. Transistor 100G, transistor 100H, transistor 100J, and transistor The top view of the transistor 100K is the same as that of the transistor 100A shown in FIG. , the explanation will be omitted here.

[0150] Transistor 100G, transistor 100H, transistor 100J, and transistor The transistor 100K has a different structure of the oxide semiconductor film 108 from the transistor 100A described above. The rest of the configuration is the same as that of the transistor 100A shown above. This has the effect of:

[0151] The oxide semiconductor film 108 included in the transistor 100G illustrated in FIGS. The oxide semiconductor film 108_1 on the insulating film 104 and the oxide semiconductor film 108_1 on the oxide semiconductor film and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. The channel region 108i, the source region 108s, and the drain region 108d are The oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film It has a three-layer laminated structure of 108_3.

[0152] The oxide semiconductor film 108 included in the transistor 100H illustrated in FIGS. The oxide semiconductor film 108_2 on the insulating film 104 and the oxide semiconductor film 108_2 on the oxide semiconductor film The semiconductor device further includes a channel region 108i, a source region 108s, and a semiconductor film 108_3. The drain region 108d is formed by the oxide semiconductor film 108_2 and the oxide semiconductor film 1 It has a two-layer laminated structure of 08_3.

[0153] The oxide semiconductor film 108 included in the transistor 100J illustrated in FIGS. The oxide semiconductor film 108_1 on the insulating film 104 and the oxide semiconductor film 108_1 on the oxide semiconductor film and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. The channel region 108i is formed by the oxide semiconductor film 108_1 and the oxide semiconductor film 108 The source region 108s and the oxide semiconductor film 108_3 are stacked in a three-layer structure. The drain region 108d is formed of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2. The transistor 100J has a two-layer laminate structure of 108_2. In the cross section in the axial direction, the oxide semiconductor film 108_3 is It covers the side surface of the semiconductor film 108_2.

[0154] The oxide semiconductor film 108 included in the transistor 100K illustrated in FIGS. The oxide semiconductor film 108_2 on the insulating film 104 and the oxide semiconductor film 108_2 on the oxide semiconductor film The channel region 108i includes an oxide semiconductor film 108_3. 2 and an oxide semiconductor film 108_3. The drain region 108d has a single-layer structure of the oxide semiconductor film 108_2. In the cross section of the transistor 100K in the channel width (W) direction, the oxide semiconductor film 108 _3 covers the side surfaces of the oxide semiconductor film 108_2.

[0155] The side surface or the vicinity of the channel region 108i in the channel width (W) direction is processed. Damage in the junctions can easily lead to the formation of defects (e.g. oxygen vacancies) or the presence of impurities. Therefore, even if the channel region 108i is substantially intrinsic, When a stress such as an electric field is applied, the channel width ( The side surface or its vicinity in the W direction is activated and tends to become a low-resistance (n-type) region. When the side surface or the vicinity of the side surface of the channel region 108i in the channel width (W) direction is an n-type region, Since the n-type region serves as a path for carriers, a parasitic channel may be formed.

[0156] Therefore, in the transistor 100J and the transistor 100K, the channel region The channel region 108i has a laminated structure, and the side surface of the channel region 108i in the channel width (W) direction is By using this structure, the side surface of the channel region 108i is covered with one layer of the structure. or suppressing defects on or near the side of the channel region 108i. This makes it possible to reduce the adhesion of impurities to the substrate.

[0157] <1-5. Band structure> Here, the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film The band structure of the insulating film 110, the insulating film 104, and the oxide semiconductor films 108_2 and 108_ The band structure of the insulating film 110 will be described with reference to FIG. , the band structure in the channel region 108i.

[0158] FIG. 14A shows the insulating film 104 and the oxide semiconductor films 108_1, 108_2, and 108_3. 1 and an insulating film 110. 4(B) shows the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and the insulating film 110. This is an example of a band structure in the thickness direction of a laminated structure having a structure having a band structure in the thickness direction. For ease of understanding, the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and The energy level (Ec) at the bottom of the conduction band of the insulating film 110 is shown.

[0159] FIG. 14A shows a case where a silicon oxide film is used as the insulating films 104 and 110, and an oxide semiconductor film is used as the insulating films 104 and 110. The conductor film 108_1 is a metal oxide film having an atomic ratio of metal elements of In:Ga:Zn=1:3:2. An oxide semiconductor film formed using an oxide semiconductor target was used as the oxide semiconductor film 108_2. A metal oxide target with an atomic ratio of metal elements of In:Ga:Zn=4:2:4.1 was used. The oxide semiconductor film 108_3 is formed by using an oxide semiconductor film formed by The oxide formed using a metal oxide target with a numerical ratio of In:Ga:Zn=1:3:2 FIG. 1 is a band diagram of a configuration using a semiconductor film.

[0160] FIG. 14B shows a case where a silicon oxide film is used as the insulating films 104 and 110, and an oxide semiconductor film is used as the insulating films 104 and 110. The conductor film 108_2 is a metal film having an atomic ratio of metal elements of In:Ga:Zn=4:2:4.1. The oxide semiconductor film 108_3 is formed by using an oxide semiconductor film formed by using an oxide target. A metal oxide target with an atomic ratio of metal elements of In:Ga:Zn=1:3:2 was used. FIG. 13 is a band diagram of a structure using an oxide semiconductor film formed in accordance with the present invention.

[0161] As shown in FIG. 14A, in the oxide semiconductor films 108_1, 108_2, and 108_3, In addition, as shown in FIG. 14(B), the energy level at the bottom of the conduction band changes gradually. As shown in FIG. 1, the energy level of the conduction band minimum in the oxide semiconductor films 108_2 and 108_3 is In other words, it can be said that the change is continuous or that the connection is continuous. In order to have such a band structure, the oxide semiconductor film 108_1 and the oxide semiconductor or between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. At the interface, impurities that form defect levels such as trap centers and recombination centers exist. Assume it does not exist.

[0162] In order to form a continuous junction in the oxide semiconductor films 108_1, 108_2, and 108_3, A multi-chamber deposition system (sputtering system) equipped with a load lock chamber was used. It is necessary to laminate each film in succession without exposing them to the atmosphere.

[0163] By using the structure shown in FIG. 14A and FIG. 14B, the oxide semiconductor film 108_2 is a well. In the transistor having the above stacked structure, the channel region is an oxide semiconductor film It can be seen that it is formed at 108_2.

[0164] Note that by providing the oxide semiconductor films 108_1 and 108_3, the trap states are It can be located away from the compound semiconductor film 108_2.

[0165] In addition, the trap states are in the conduction band of the oxide semiconductor film 108_2 functioning as a channel region. The energy level at the bottom (Ec) can be farther from the vacuum level, and the charge is transferred to the trap level. When electrons accumulate in the trap level, negative electrons are trapped. This results in a constant charge, and the threshold voltage of the transistor shifts in the positive direction. The trap level is higher than the energy level (Ec) of the conduction band minimum of the oxide semiconductor film 108_2. It is preferable to use a structure in which the trap level is as close to the vacuum level as possible. This makes it difficult for electrons to accumulate at the gate potential, which makes it possible to increase the on-state current of the transistor. Together, the field effect mobility can be increased.

[0166] In addition, the oxide semiconductor films 108_1 and 108_3 are more conductive than the oxide semiconductor film 108_2. The energy level of the conduction band minimum is close to the vacuum level. The energy levels of the conduction band minimum and the conduction band minimum of the oxide semiconductor films 108_1 and 108_3 are The difference between the energy levels is 0.15 eV or more, or 0.5 eV or more and 2 eV or less. That is, the electron affinity of the oxide semiconductor films 108_1 and 108_3 is The difference between the electron affinity of the oxide semiconductor film 108_2 and the electron affinity of the oxide semiconductor film 108_2 is 0.15 eV or more, or 0. The electron transport energy is 5 eV or more and 2 eV or less, or 1 eV or less.

[0167] With such a structure, the oxide semiconductor film 108_2 serves as a main current path. That is, the oxide semiconductor film 108_2 functions as a channel region. The films 108_1 and 108_3 function as oxide insulating films. The films 108_1 and 108_3 constitute the oxide semiconductor film 108_2 in which a channel region is to be formed. It is preferable to use an oxide semiconductor film formed of one or more metal elements that form the oxide semiconductor layer. By adopting such a structure, the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2, Alternatively, the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3 may be diffused at the interface between them. Therefore, the movement of carriers is not hindered at the interface, and therefore, The field effect mobility of the transistor is increased.

[0168] The oxide semiconductor films 108_1 and 108_3 function as part of a channel region. To prevent this, materials with sufficiently low electrical conductivity are used. The conductive films 108_1 and 108_3 are each made of oxide insulating material based on their physical properties and / or functions. Alternatively, the oxide semiconductor films 108_1 and 108_3 may be formed of a material having a high electron affinity (vacuum the energy level of the oxide semiconductor film 108_2 is smaller than that of the oxide semiconductor film 108_2, The energy level of the conduction band minimum is the same as that of the oxide semiconductor film 108_2. A material with a band offset is used. In order to suppress the occurrence of a difference in threshold voltage depending on the thickness of the oxide semiconductor film 108, The energy levels of the conduction band minimums of the oxide semiconductor films 108_1 and 108_3 are lower than the conduction band minimum of the oxide semiconductor film 108_2. It is preferable to use a material that is closer to the vacuum level than the lower energy level. For example, an oxide The energy level of the conduction band minimum of the semiconductor film 108_2 and the oxide semiconductor films 108_1 and 10 The difference between the energy level of the conduction band minimum of 8_3 is 0.2 eV or more, preferably 0.5 eV. It is preferable that the amount is equal to or more than that.

[0169] In addition, the oxide semiconductor films 108_1 and 108_3 each have a spinel crystal structure. It is preferable that the oxide semiconductor films 108_1 and 108_3 do not include a spinel type crystal. When the spinel type crystal structure is included, the conductive film 120 is In some cases, the constituent elements of the oxide semiconductor film 108_2 may diffuse into the oxide semiconductor film 108_2. When the oxide semiconductor films 108_1 and 108_3 are CAAC-OS, the conductive film 120a , 120b, for example, the blocking property of copper element is increased, which is preferable.

[0170] In this embodiment, the oxide semiconductor films 108_1 and 108_3 are made of a metal The atomic ratio of elements was In:Ga:Zn=1:3:2. However, the present invention is not limited to this structure. The compound semiconductor films 108_1 and 108_3 are made of In:Ga:Zn=1:1:1 [atomic ratio] ], In:Ga:Zn=1:1:1.2[atomic ratio], In:Ga:Zn=1:3:4[ atomic ratio], In:Ga:Zn=1:3:6[atomic ratio], or In:Ga:Zn=1 The oxide semiconductor film was formed using a metal oxide target with an atomic ratio of 10:1. Alternatively, the oxide semiconductor films 108_1 and 108_3 may include an atom of a metal element. An oxide semiconductor film formed using a metal oxide target with a numerical ratio of Ga:Zn=10:1 In this case, the oxide semiconductor film 108_2 may be formed by using a metal element having an atomic ratio of In An oxide semiconductor film formed using a metal oxide target of Ga:Zn=1:1:1 When the oxide semiconductor film 108_2 is used, the energy level of the conduction band minimum of the oxide semiconductor film 108_2 and the energy level of the oxide semiconductor film The difference between the energy levels of 108_1 and 108_3 at the bottom of the conduction band is 0.6 eV or more. This is preferable because it is possible to

[0171] Note that the oxide semiconductor films 108_1 and 108_3 are made of In:Ga:Zn=1:1:1 When a metal oxide target having an atomic ratio of 108 is used, the oxide semiconductor films 108_1 and 108 _3 is the case where In:Ga:Zn=1:β1(0<β1≦2):β2(0<β2≦2) In addition, the oxide semiconductor films 108_1 and 108_3 may be formed of In:Ga:Zn=1. When a metal oxide target having an atomic ratio of 3:4 is used, the oxide semiconductor film 108_1 , 108_3 is In:Ga:Zn=1:β3(1≦β3≦5):β4(2≦β4≦6) In addition, the oxide semiconductor films 108_1 and 108_3 may be formed of In:Ga: When a metal oxide target with an atomic ratio of Zn=1:3:6 is used, the oxide semiconductor film 1 08_1 and 108_3 are In:Ga:Zn=1:β5(1≦β5≦5):β6(4≦β 6≦8).

[0172] <1-6. Manufacturing method of semiconductor device 1> Next, an example of a method for manufacturing the transistor 100 shown in FIG. 1 will be described with reference to FIGS. 15 to 17 are used to explain a method for manufacturing the transistor 100. 1 is a cross-sectional view in the channel length (L) direction and the channel width (W) direction.

[0173] First, an insulating film 104 is formed on a substrate 102. Then, an oxide semiconductor is formed on the insulating film 104. Then, the oxide semiconductor film is processed into an island shape to form an oxide semiconductor film. 107 is formed (see FIG. 15(A)).

[0174] The insulating film 104 can be formed by sputtering, CVD, vapor deposition, pulsed laser deposition ( The film can be formed by appropriately using a PLD method, a printing method, a coating method, or the like. In this case, a silicon nitride film having a thickness of 400 nm was deposited as the insulating film 104 using a PECVD apparatus. Then, a silicon oxynitride film having a thickness of 50 nm is formed.

[0175] After the insulating film 104 is formed, oxygen may be added to the insulating film 104. The oxygen added to 4 can be oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions. The doping method includes ion doping, ion implantation, plasma treatment, etc. In addition, a film that suppresses oxygen desorption is formed on the insulating film, and then the insulating film is formed through the film. The film 104 may be doped with oxygen.

[0176] The above-mentioned oxygen desorption-suppressing film may be made of indium, zinc, gallium, tin, aluminum, or the like. Aluminum, Chromium, Tantalum, Titanium, Molybdenum, Nickel, Iron, Cobalt, or Tungsten The insulating film can be formed using a conductive film or a semiconductor film having one or more tennines.

[0177] In addition, when oxygen is added in plasma treatment, the oxygen is excited by microwaves to produce high-density oxygen. By generating atomic plasma, the amount of oxygen added to the insulating film 104 can be increased. .

[0178] The oxide semiconductor film 107 can be formed by a sputtering method, a coating method, a pulsed laser deposition method, or a method using a deposition method such as a deposition method. It can be formed by a laser ablation method, a thermal CVD method, etc. To process the conductive film 107, a mask is formed on the oxide semiconductor film by a lithography process. Then, part of the oxide semiconductor film is etched using the mask. Alternatively, the oxide semiconductor film 107 that is isolated from the other elements may be directly formed by using a printing method. stomach.

[0179] When an oxide semiconductor film is formed by a sputtering method, a power source for generating plasma The device may be an RF power supply device, an AC power supply device, a DC power supply device, or the like. In the case of forming an oxide semiconductor film, a sputtering gas is a rare gas (typically, argon). ), oxygen, rare gas, and mixed gas of oxygen are used as appropriate. Note that the mixed gas of rare gas and oxygen In this case, it is preferable to increase the gas ratio of oxygen to the rare gas.

[0180] Note that when the oxide semiconductor film is formed by, for example, a sputtering method, Temperature: 150℃ to 750℃, 150℃ to 450℃, or 200℃ By forming an oxide semiconductor film at a temperature of 350° C. or less, the crystallinity can be improved. Therefore, it is preferable.

[0181] Note that in this embodiment, the oxide semiconductor film 107 is formed by a sputtering apparatus. The sputtering target was In-Ga-Zn metal oxide (In:Ga:Zn = 4:2:4.1 [atomic ratio]) to form a 35-nm-thick oxide semiconductor film.

[0182] After the oxide semiconductor film 107 is formed, heat treatment is performed. The temperature of the heat treatment is typically 150° C. or higher. Less than the strain point, or 250°C to 450°C, or 300°C to 450°C .

[0183] Heat treatment is carried out using rare gases such as helium, neon, argon, xenon, krypton, etc., or It can be carried out in an inert gas atmosphere containing nitrogen. Alternatively, it can be heated in an inert gas atmosphere. After that, heating may be performed in an oxygen atmosphere. Note that hydrogen, water, etc. may be added to the inert atmosphere and oxygen atmosphere. It is preferable that the treatment time does not include the above-mentioned. The treatment time may be from 3 minutes to 24 hours.

[0184] The heat treatment can be performed using an electric furnace, an RTA device, or the like. Therefore, heat treatment can be performed at a temperature above the distortion point of the substrate for a short period of time. The processing time can be reduced.

[0185] The oxide semiconductor film is formed while being heated, or the oxide semiconductor film is formed and then subjected to heat treatment. By performing the process, the hydrogen concentration in the oxide semiconductor film measured by SIMS was increased to 5×10 19 atoms / cm 3 or less, or 1×10 19 atoms / cm 3 Below, 5 x 10 1 8 atoms / cm 3 or less, or 1×10 18 atoms / cm 3 or less, or 5×1 0 17 atoms / cm 3 or less, or 1×10 16 atoms / cm 3 The following shall be done: can be done.

[0186] Next, the insulating film 110_0 is formed over the insulating film 104 and the oxide semiconductor film 107 (FIG. 1 5(B)).

[0187] The insulating film 110_0 is a silicon oxide film or a silicon oxynitride film formed by PECVD. In this case, the source gas is a deposition gas containing silicon. It is preferable to use a gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silicon include Examples of oxidizing gases include silane, disilane, trisilane, and fluorinated silane. Examples of oxidizing gases include oxygen. , ozone, nitrous oxide, nitrogen dioxide, etc.

[0188] In addition, for the insulating film 110_0, the flow rate of the oxidizing gas is set to 20 times the flow rate of the deposition gas. The pressure in the treatment chamber should be 100P or more but less than 100 times, or 40 times or more but less than 80 times. By using the PECVD method with a pressure of less than a or 50 Pa or less, the amount of defects is reduced. A silicon hydride film can be formed.

[0189] In addition, the insulating film 110_0 is placed in a evacuated processing chamber of a PECVD apparatus. The substrate is maintained at a temperature of 280° C. or higher and 400° C. or lower, and a source gas is introduced into the processing chamber. The pressure in the chamber is set to 20 Pa or more and 250 Pa or less, and more preferably 100 Pa or more and 250 Pa or less. Under the conditions of supplying high frequency power to an electrode provided in the processing chamber, the insulating film 110 is 0, a dense silicon oxide film or silicon oxynitride film can be formed. .

[0190] In addition, the insulating film 110_0 may be formed by using a plasma CVD method using microwaves. Good. Microwaves refer to the frequency range from 300MHz to 300GHz. Microwaves are: The electron temperature is low and the electron energy is small. Also, the electron acceleration is The proportion of the ionized gas used for dissociation and ionization of a larger number of molecules is reduced. This allows for the excitation of high density plasma. The insulating film 110_0 is formed with less defects due to less plasma damage to the surface and deposits. It is possible.

[0191] In addition, the insulating film 110_0 can be formed by a CVD method using an organic silane gas. As an organic silane gas, ethyl silicate (TEOS: chemical formula Si(OC2H5)4 ), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetramethylsilane (TMS: chemical formula Si(CH3)4), Lasiloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), Silicon-containing compounds such as trisdimethylaminosilane (SiH(N(CH3)2)3) By using the CVD method using organic silane gas, it is possible to obtain a high coating property. An insulating film 110_0 can be formed.

[0192] In this embodiment, a PECVD apparatus is used to deposit a 100 nm thick insulating film 110_0. A silicon oxynitride film is formed.

[0193] Next, a metal oxide film 112_0 is formed on the insulating film 110_0. During the formation of the insulating film 110_0, oxygen is added from the metal oxide film 112_0 to the insulating film 110_0. (See FIG. 15(C)).

[0194] The metal oxide film 112_0 is formed by sputtering. It is preferable to form the metal oxide film in an atmosphere containing oxygen gas during the formation. By forming 112_0, oxygen can be suitably added to the insulating film 110_0. The method for forming the metal oxide film 112_0 is not limited to the sputtering method. Other methods, such as ALD, may also be used.

[0195] In FIG. 15C, oxygen added to the insulating film 110_0 is indicated by arrows. It represents.

[0196] In this embodiment, the metal oxide film 112_0 is formed by sputtering. An aluminum oxide film having a thickness of 10 nm is formed. After the formation of the metal oxide film 112_0, Oxygen addition treatment may be performed after the formation of the insulating film 104. The addition of oxygen may be carried out in the same manner as in the case of the addition of oxygen to the catalyst.

[0197] Next, a conductive film 114_0 is formed on the metal oxide film 112_0. A mask 140 is formed at a desired position on the substrate _0 by a lithography process (FIG. 15(D) reference).

[0198] In this embodiment, the conductive film 114_0 is formed by a sputtering method. A 100 nm thick tungsten film is deposited.

[0199] Next, etching is performed from above the mask 140 to remove the conductive film 114_0 and the metal oxide film 112 Then, the mask 140 is removed to form the insulating film 110_0. In the process, an island-shaped conductive film 114, an island-shaped metal oxide film 112, and an island-shaped insulating film 110 are formed (see FIG. 16(A)).

[0200] In this embodiment, the conductive film 114_0, the metal oxide film 112_0, and the insulating film 11 The processing of 0_0 is carried out using a dry etching method.

[0201] In addition, when processing the conductive film 114_0, the metal oxide film 112_0, and the insulating film 110_0, In some cases, the thickness of the oxide semiconductor film 107 in a region not overlapped with the conductive film 114 becomes thin. Alternatively, when processing the conductive film 114_0, the metal oxide film 112_0, and the insulating film 110_0, In some cases, the thickness of the insulating film 104 in a region where the oxide semiconductor film 107 does not overlap with the insulating film 104 becomes thin. In addition, when processing the conductive film 114_0, the metal oxide film 112_0, and the insulating film 110_0, An etchant or an etching gas (such as chlorine) is added to the oxide semiconductor film 107. Alternatively, the conductive film 114_0, the metal oxide film 112_0, or the insulating film 110_0 In some cases, the constituent elements of the above may be added to the oxide semiconductor film 107.

[0202] Next, an impurity element 1 was added from above the insulating film 104, the oxide semiconductor film 107, and the conductive film 114. Addition of 45 is performed (see FIG. 16(B)).

[0203] The impurity element 145 can be added by ion doping, ion implantation, plasma In the case of plasma treatment, the plasma is heated in a gas atmosphere containing the impurity element to be added. Impurity elements can be added by generating a plasma and performing a plasma treatment. The plasma generating device may be a dry etching device, an ashing device, A plasma CVD apparatus, a high density plasma CVD apparatus, or the like can be used.

[0204] The source gas for the impurity element 145 is B2H6, PH3, CH4, N2, NH3 , AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2 and one or more of the rare gases Alternatively, B2H6, PH3, N2, NH3, diluted with rare gases, One or more of AlH3, AlCl3, F2, HF, and H2 can be used. Diluted B2H6, PH3, N2, NH3, AlH3, AlCl3, F2, HF, and The impurity element 145 is added to the oxide semiconductor film 107 using one or more of H and One or more of silicon, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, and chlorine are added to the oxide semiconductor. It can be added to the film 107 .

[0205] Or after adding rare gases, B2H6, PH3, CH4, N2, NH3, AlH3, At least one of AlCl3, SiH4, Si2H6, F2, HF, and H2 is added to the oxide semiconductor film 1 07. Or B2H6, PH3, CH4, N2, NH3, AlH3, After adding one or more of AlCl3, SiH4, Si2H6, F2, HF, and H2, rare gas The oxide semiconductor film 107 may be doped with sulfur.

[0206] The addition of the impurity element 145 is controlled by appropriately setting implantation conditions such as acceleration voltage and dose amount. For example, when argon is added by ion implantation, the acceleration voltage is set to 10 kV or more. 00kV or less, dose amount is 1×10 13 ions / cm 2 More than 1×10 16 ions / c m 2 For example, 1×10 14 ions / cm 2 Also, When phosphorus ions are added by the on-implantation method, the acceleration voltage is 30 kV and the dose is 1×10 13 ions / cm 2 5×10 or more 16 ions / cm 2 For example, 1×1 0 15 ions / cm 2 This can be done as follows.

[0207] In this embodiment, the mask 140 is removed, and then the impurity element 145 is added. However, the present invention is not limited to this. For example, the mask 140 may be left in place. The impurity element 145 may be added in this state.

[0208] In this embodiment, the impurity element 145 is doped using a doping device. Argon is added to the oxide semiconductor film 107. However, this is not limiting. For example, In this case, the step of adding the impurity element 145 is not required. Since the above-mentioned process is not performed, the manufacturing process can be simplified.

[0209] Next, the insulating film 116 is formed over the insulating film 104, the oxide semiconductor film 107, and the conductive film 114. Note that by forming the insulating film 116, the oxide semiconductor film 1 07 becomes the source region 108s and the drain region 108d. In other words, the oxide semiconductor film 107 in contact with the insulating film 110 This results in the channel region 108i. The oxide semiconductor film 108 having the drain region 108d is formed (FIG. 16C). reference).

[0210] In this embodiment, the insulating film 116 is made of a material that can be used for the insulating film 116. In the present embodiment, the insulating film 116 is formed by PECVD. Using this device, a silicon fluoride nitride film with a thickness of 100 nm is formed. The silicon film is formed, for example, by using SiF4 and N2 as raw material gas. Alternatively, it can be formed using SiF4, N2, and SiH4 as source gases. do.

[0211] By using a silicon fluoride nitride film as the insulating film 116, the The source region 108s and the drain region 108d are provided with nitrogen, hydrogen, and the like in the silicon fluoride nitride film. Fluorine may be provided to one or more of the source region 108s and the drain region 108s. It is preferable that fluorine is supplied to the source region 108s and the drain region 108d. The carrier density in the rain region 108d can be stably increased.

[0212] Next, the insulating film 118 is formed over the insulating film 116 (see FIG. 16(D)).

[0213] In this embodiment, the insulating film 118 is made of a material that can be used for the insulating film 118. In the present embodiment, the insulating film 118 is formed by PECVD. Using this apparatus, a silicon oxynitride film with a thickness of 300 nm is formed.

[0214] Next, a mask is formed by lithography at a desired position on the insulating film 118, and then the insulating film By etching a part of the insulating film 118 and the insulating film 116, an opening reaching the source region 108s is formed. An opening 141a and an opening 141b reaching the drain region 108d are formed (FIG. 17). (See (A)).

[0215] The method for etching the insulating film 118 and the insulating film 116 is a wet etching method. Either one or both of the dry etching method and the dry etching method may be used. For this purpose, the insulating film 118 and the insulating film 116 are processed by dry etching.

[0216] Next, a conductive film 120 is formed on the insulating film 118 so as to cover the openings 141a and 141b. (See FIG. 17(B)).

[0217] For the conductive film 120, a material that can be used for the conductive films 120a and 120b is selected. In this embodiment, the conductive film 120 is formed by a sputtering device. Using this apparatus, a laminated film of a 50 nm thick tungsten film and a 400 nm thick copper film is formed. do.

[0218] Next, a mask is formed at a desired position on the conductive film 120 by a lithography process, and then, A part of the conductive film 120 is etched to form conductive films 120a and 120b (FIG. 17(C)).

[0219] The conductive film 120 can be processed by wet etching or dry etching. In this embodiment, the copper is removed by wet etching. After etching the film, the tungsten film is etched by a dry etching method. The conductive film 120 is processed to form conductive films 120a and 120b.

[0220] Through the above steps, the transistor 100 illustrated in FIG. 1 can be manufactured.

[0221] Note that the films constituting the transistor 100 (insulating film, metal oxide film, oxide semiconductor film, conductive film, In addition to the above-mentioned formation methods, the deposition method of the thin film, the sputtering method, the chemical vapor deposition (CVD) method, It can be formed using vacuum deposition, pulsed laser deposition (PLD), or ALD. Alternatively, it can be formed by a coating method or a printing method. Representative examples of the method include a plasma enhanced chemical vapor deposition (PECVD) method, but a thermal CVD method may also be used. An example of the thermal CVD method is MOCVD (metal organic chemical vapor deposition).

[0222] In the thermal CVD method, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the source gas and the oxidizing agent are simultaneously The reaction is carried out in the chamber near or on the substrate, where it is deposited on the substrate to form a film. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0223] Thermal CVD methods such as MOCVD can be used to form the above-mentioned conductive films, insulating films, oxide semiconductor films, and metal It is possible to form films such as oxide films. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3 )3) and dimethylzinc (Zn(CH3)2). Instead of trimethylgallium, triethylgallium (Ga(C2H5)3) is used. Alternatively, diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc. can.

[0224] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and liquids containing hafnium precursors (hafnium alkoxides and tetrakisdimethylamide Hafnium (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamine) C) Hafnium amide (e.g. hafnium) is vaporized as a raw material gas, and ozone is used as an oxidizer. Two types of gases are used:

[0225] For example, when forming an aluminum oxide film using an ALD deposition system, A liquid containing a catalyst and an aluminum precursor (trimethylaluminum (TMA, Al(CH3) 3) and other) are used as the raw material gas and as the oxidizing agent, H2O. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate) There are some.

[0226] For example, when forming a silicon oxide film using a deposition system that uses ALD, Chlorodisilane is adsorbed on the surface to be coated, and the radicals of oxidizing gases (O2, nitrous oxide) are The adsorbate is reacted with the adsorbate.

[0227] For example, when forming a tungsten film using an ALD deposition system, WF6 The initial tungsten film is formed by sequentially introducing B2H6 gas and WF6 gas. The tungsten film is formed using H2 gas. Note that SiH4 gas is used instead of B2H6 gas. A suction cup may also be used.

[0228] For example, an oxide semiconductor film, such as In-Ga-Zn- When forming an O film, an In-O layer is formed using In(CH3)3 gas and O3 gas. Then, a GaO layer is formed using Ga(CH3)3 gas and O3 gas, and then Z The ZnO layer is formed using n(CH3)2 gas and O3 gas. The order of these layers is The present invention is not limited to this example. In addition, In-Ga-O layers and In-Zn-O layers can be formed by using these gases. Alternatively, a mixed compound layer such as a Ga-Zn-O layer may be formed. H2O gas obtained by bubbling water with an inert gas such as HO may be used, but it is not recommended to use gas that does not contain H. It is preferable to use O3 gas, which is less oxidative.

[0229] <1-7. Manufacturing method of semiconductor device 2> Next, an example of a method for manufacturing the transistor 100A shown in FIG. 2 will be described with reference to FIGS. 18 to 20 are used to explain a method for manufacturing the transistor 100A. 1 is a cross-sectional view in the channel length (L) direction and the channel width (W) direction.

[0230] First, the conductive film 106 is formed on the substrate 102. Next, the substrate 102 and the conductive film 106 are An insulating film 104 is formed over the insulating film 104, and an oxide semiconductor film is formed over the insulating film 104. The oxide semiconductor film is processed into an island shape to form an oxide semiconductor film 107 (FIG. 18(A) )reference).

[0231] The conductive film 106 is formed using a material and a method similar to those of the conductive films 112a and 112b. In this embodiment, the conductive film 106 is a 100 nm thick film. A tungsten film having a thickness of 100 nm is formed by sputtering.

[0232] Next, the insulating film 110_0 is formed over the insulating film 104 and the oxide semiconductor film 107. Thereafter, a metal oxide film 112_0 is formed on the insulating film 110_0 (see FIG. 18(B)).

[0233] In addition, when the metal oxide film 112_0 is formed, oxygen is added to the insulating film 110_0. In FIG. 18(B), the oxygen is diagrammatically represented by an arrow.

[0234] Next, a mask was formed by lithography at a desired position on the metal oxide film 112_0. Thereafter, the metal oxide film 112_0, the insulating film 110_0, and a part of the insulating film 104 are etched. As a result, an opening 143 reaching the conductive film 106 is formed (see FIG. 18C).

[0235] The opening 143 can be formed by wet etching or dry etching. In this embodiment, a dry etching method is used. 2. The opening 143 is formed using the fluorine-containing ...

[0236] Next, a conductive film 114_0 is formed on the metal oxide film 112_0 so as to cover the opening 143. (See FIG. 18(D)).

[0237] In addition, the conductive film 114_0 is formed so as to cover the opening 143, so that the conductive film 106 and the conductive film 114_0 are electrically connected to each other.

[0238] Next, a mask 140 is formed at a desired position on the conductive film 114_0 by a lithography process. (See FIG. 19(A)).

[0239] Next, etching is performed from above the mask 140 to remove the conductive film 114_0 and the metal oxide film 112 The conductive film 114_0, the metal oxide film 112_0, and the insulating film 110_0 are processed. By processing the insulating film 110_0, an island-shaped conductive film 114, an island-shaped metal oxide film 112, Furthermore, island-shaped insulating films 110 are formed (see FIG. 19(B)).

[0240] In this embodiment, a dry etching method is used to remove the conductive film 114_0 and the metal oxide film 112_0 and the insulating film 110_0 are processed.

[0241] Next, after removing the mask 140, the insulating film 104, the oxide semiconductor film 107, and the conductive film An impurity element 145 is added from above 114 (see FIG. 19C).

[0242] In this embodiment, the impurity element 145 is doped using a doping device. Argon is added to the oxide semiconductor film 107.

[0243] Next, the insulating film 116 is formed over the insulating film 104, the oxide semiconductor film 107, and the conductive film 114. Note that by forming the insulating film 116, the oxide semiconductor film 1 07 becomes the source region 108s and the drain region 108d. In other words, the oxide semiconductor film 107 in contact with the insulating film 110 This results in the channel region 108i. 19D, the oxide semiconductor film 108 having the drain region 108d is formed. reference).

[0244] Next, the insulating film 118 is formed on the insulating film 116 (see FIG. 20A).

[0245] Next, a mask is formed by lithography at a desired position on the insulating film 118, and then the insulating film By etching a part of the insulating film 118 and the insulating film 116, an opening reaching the source region 108s is formed. An opening 141a and an opening 141b reaching the drain region 108d are formed (FIG. 20). (See (B)).

[0246] Next, a conductive film 120 is formed on the insulating film 118 so as to cover the openings 141a and 141b. (See Figure 20(C)).

[0247] Next, a mask is formed at a desired position on the conductive film 120 by a lithography process, and then, A part of the conductive film 120 is etched to form conductive films 120a and 120b (FIG. 20(D)).

[0248] Through the above steps, the transistor 100A shown in FIG. 2 can be manufactured.

[0249] In this embodiment, an example in which a transistor includes an oxide semiconductor film is shown. However, one embodiment of the present invention is not limited thereto. As an example, the channel region of a transistor may not have a nitride semiconductor film. In the vicinity of the gate region, the source region, or the drain region, rumanium), SiGe (silicon germanium), GaAs (gallium arsenide), etc. The insulating layer 10 may be formed of a material having such a structure.

[0250] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0251] (Embodiment 2) In this embodiment, oxygen vacancies (V O ), and the oxygen The case where an impurity (fluorine or hydrogen) enters the defect will be described in detail.

[0252] <2-1. Oxygen vacancies (V O ) Model First, oxygen vacancies (V O ) model is explained. In semiconductors, oxygen vacancies form deep levels (dDOS). This can cause deterioration of the electrical characteristics of a transistor including an oxide semiconductor. Here, we consider the clusters of oxygen vacancies (V O Also called a cluster.) is of the form We will explain the results of verifying the model created.

[0253] Figure 21(A) shows a model of an InGaZnO4 crystal in its initial state (before oxygen vacancies are created). 21(B), 21(C), 22(A), 22(B), and 22(C) are diagrams showing the same structure as those shown in FIG. C) shows the state where oxygen vacancies are formed in the InGaZnO4 crystal model in the initial state shown in FIG. 21(A), 21(B), 21(C), and 22(A) are diagrams showing the model. In Fig. 22(B) and Fig. 22(C), white circles represent metal atoms, and the element name is written in the white circle. The black circles represent oxygen atoms, and the dotted circles represent V. O Represents.

[0254] [V O Formation of First, from the initial state shown in FIG. 21(A), as shown in FIG. 21(B), V at the missing oxygen site O is formed.

[0255] [Formation of Vzn 1] Next, from the model shown in FIG. 21(B), as shown in FIG. 21(C), V O The nearby Zn This results in the formation of a Zn deficiency (Vzn).

[0256] [V O Formation of Next, from the model shown in FIG. 21C, as shown in FIG. 22A, in the vicinity of Vzn and V is added to the oxygen site with a low coordination number with Ga. O is formed.

[0257] [Formation of Vzn 2] Next, from the model shown in FIG. 22(A), as shown in FIG. 22(B), V O The nearby Zn is released and Vzn is formed.

[0258] [V O Formation of Next, from the model shown in FIG. 22(B), as shown in FIG. 22(C), V O is formed.

[0259] In this manner, one oxygen vacancy is formed in the oxide semiconductor. New oxygen vacancies are formed near the oxygen vacancies, resulting in multiple oxygen vacancies or clusters of oxygen vacancies. Body (V O Therefore, when oxygen vacancies are formed, stable bonds are formed. It is important to terminate the oxygen vacancies by

[0260] <2-2.V O 1> About the F-terminator Next, oxygen vacancies (V O ) to terminate the oxide semiconductor. First, V O F termination (hereinafter, V O Check whether F) is likely to occur. Therefore, F is V O Models that exist outside of V O Two models of the model that entered We performed calculations to determine which model is more energetically stable.

[0261] The model diagrams used in the calculations are shown in Figure 23(A)(B), and the calculation conditions are shown in Table 1. In Fig. 23(A) and (B), the large black circles represent oxygen atoms, and the white circles, small black circles, and The gray circles represent metal atoms (In, Ga, and Zn, respectively), and the dotted circles represent V. O Represents the arrow The circle indicated by represents F.

[0262] [Table 1]

[0263] The model used for the calculation was an InGaZnO4 crystal model (112 atoms). Also, in Figure 23(A), F is V O Models that exist outside of O +F int Mo In FIG. 23(B), F is V O The model that entered (hereinafter, V O F+bulk model (L).

[0264] In addition, V O and V O The F formation sites are three In atoms and one In atom bonded to Zn. The oxygen site of the O2 layer was set as F. Also, V O For models outside the lattice, F is the interstitial Exists (F int Therefore, F atoms were placed at possible interstitial sites, and The most energetically stable site was selected.

[0265] In addition, V shown in FIG. O +F int The model is V O and F int What is the impact? In this case, F is assumed to be located so far away that there is no V O The model entered in Figure 2 V shown in 3(A) O +F int To compare the energies of the models, the number of atoms must be the same. So, V O +F int The energy of the model (E tot (V O +F int ) to V O The energy of the model (E(V O )) and F int Model (E(F int Energy of - is the sum of V O F model energy (Etot (V O F)) to V O F model energy Gee(E(V O F) and the energy of the bulk model without defects (E(bulk)). It was decided.

[0266] The formula that satisfies the above relationship is shown below.

[0267]

number

[0268]

number

[0269] The relative energy calculated using the above formulas (1) and (2) is shown in Table 2. As shown in.

[0270] [Table 2]

[0271] From the results shown in Table 2, V O F is more V O +F int The relative energy is lower than This shows that V O and F int V O In the shape of F This suggests that the more stable the V O In the case where the IGZO film is Probably F. int V O Fill in the V O Form F.

[0272] <2-3.V O F-model density of states Next, V OThe density of states of the F model was calculated. O The calculation results of the density of states of the F model are shown in Fig. 2. Shown in 4.

[0273] In addition, V O To calculate the density of states of the F model, the functional GGA (Generalized Gaussian Algorithm) is used. In addition, in FIG. 24, The upper half shows an up spin, the lower half shows a down spin, and the horizontal The axis represents energy, with 0 eV on the horizontal axis corresponding to the top of the valence band.

[0274] From the results shown in Figure 24, V O When F is formed, an electron is released into the conduction band. This is suggested to be due to the difference in ionic valence between O and F. For that, V O When F enters the InGaZnO4 crystal model, electrons are released and the InGaZnO4 crystal model becomes n-type. Ugh.

[0275] <2-4.V O Regarding the O-terminator of Next, the V O To compare with the F termination of V O The calculation was performed for the O-terminus of In addition, V O The O termination of V O Restoration, V O After O-termination, there are no defects. , O is V O Models that exist outside of V O Energy ratio with the repaired (without defects) model A comparison was made.

[0276] The model diagrams used in the calculations are shown in Figure 25(A)(B). The calculation conditions are as shown above. S V O Same as F.

[0277] The model used for the calculation was an InGaZnO4 crystal model (112 atoms). Also, in Figure 25(A), O is V O Models that exist outside of O +O int Mo Figure 25(B) shows the defect-free bulk model (hereafter referred to as bulk+bulk In Figure 25(A) and (B), the large black circles represent oxygen atoms, and the white circles represent oxygen atoms. The circles, small black circles, and gray circles represent metal atoms (In, Ga, and Zn, respectively), and the dotted circles is V O The circle indicated by the arrow represents O. int Represents.

[0278] In addition, V shown in FIG. O +O int The model is V O and O int What is the impact? In this case, O shown in Figure 25(B) is V O Enter The model without defects and the V shown in Figure 25(A) O +O int Compare with the model In order to achieve this, it is necessary to align the number of atoms. O +O int Model As a rule, V O +O int The energy of the model (E tot (V O +O int )) to V O The energy of the model (E(V O )) and O int Model (E(O int Energy with -, and V shown in Figure 25(B) O The energy of the repaired (defect-free) model (E to t(cure)) is twice the energy of the defect-free bulk model (E(bulk)). It was decided.

[0279] The formula that satisfies the above relationship is shown below.

[0280]

number

[0281]

number

[0282] The relative energy calculated using the above formulas (3) and (4) is shown in Table 3. As shown in.

[0283] [Table 3]

[0284] From the results shown in Table 3, V O The repair is V O +O int The relative energy is lower than This is because V O and O int V O Repair This suggests that the structure is more stable. O was in the IGZO film. If, perhaps, O int V O Fill in the V O Repair. V O Carrier for repair There is no generation.

[0285] <2-5.V O 2> About F termination Next, V with a calculation method different from the above OThe F-terminus of the above calculation is explained. In the above, the GGA functional was used, whereas in the following, the Hybrid functional was used. The calculation conditions are shown in Table 4.

[0286] [Table 4]

[0287] In the calculation conditions shown in Table 4, the lattice constants and atomic positions of the initially defect-free crystal model are Then, we created a model for each defect and optimized only the atomic configuration.

[0288] In addition, calculations are performed for the four models shown in Figure 26(A)(B)(C)(D). went.

[0289] FIG. 26(A) shows oxygen vacancies (V O ) is a model diagram showing the V O F The structure filled with (V O F), and Fig. 26(C) shows the insertion of F between the lattices. The structure (F int ), and Fig. 26(D) shows a structure in which O is inserted between the lattices. Construction (O int ) is a model diagram showing the structure of the 3D model shown in Fig. 26(A), (B), (C), and (D). The large black circles represent oxygen atoms, and the white, small black, and gray circles represent metal atoms (I n, Ga, Zn), and the dotted circle represents V O The white circle indicated by the arrow represents F int Represents the arrow The black circle indicated by the mark is O int Represents.

[0290] Also, in FIG. 26(A), V O The formation position of the InO2 layer is O, and the adjacent The site was O. That is, V OThe formation position of is a site surrounded by three In atoms and one Zn atom. In addition, in FIG. 26(B), V O The formation position of F is O in the InO2 layer, and Zn and The adjacent site was O. That is, V O The F formation position is surrounded by three In atoms and one Zn atom. In addition, in FIG. 26(C), F int The formation position of the InO2 layer, The interstitial sites were between the (Ga,Zn)O layers. That is, F int The formation position of I The site is surrounded by n3, Ga2, and Zn1. Also, in FIG. 26(D), O int The formation position of the ZnO was set as an interstitial site between the InO2 layer and the (Ga,Zn)O layer. Nawa, O int The formation site is surrounded by three In atoms, two Ga atoms, and one Zn atom. .

[0291] In addition, for the model diagrams shown in Figures 26(A), (B), (C), and (D), the following formulas are used to calculate the missing parts. The formation energy of the dent model (E form (D) was calculated. Energy (E form (D)) The smaller the value, the easier it is for defects to form.

[0292]

number

[0293] In equation (5), E(defect,q) is the charge of a lattice with a defect D at q. is the total energy of the crystal without defects, E(bulk) is the total energy of the crystal without defects, and Δn(X) is the energy of the system μ(X) is the number of atoms X removed (added) from the system, and μ(X) is the number of atoms X removed (added) from the system. is the chemical potential with respect to the defect, q is the charge valence of the system with defects, and μ(e) is the chemical potential of the electron The potential (the Fermi level from the top of the valence band) is E VBM is the upper edge of the valence band (VBM ) and ΔV represents the correction to the electrostatic potential energy.

[0294] FIG. 27 shows the calculation results of the density of states for a defect-free crystal model (perfect crystal).

[0295] In FIG. 27, the Fermi level refers to the highest electron occupancy level. In the calculation, the calculation is performed only at the Γ point, so the levels are discrete. All the electrons are in the valence band, and there is no level in the gap. From the calculation results shown in Figure 27, The band gap was 3.10 eV.

[0296] Next, V O The calculated formation energy of is shown in Figure 28(A). O The formation energy of F The calculation results are shown in Fig. 28(B). int The calculated formation energy of is shown in Fig. 29(A). int The calculation results of the formation energies of are shown in FIG. 29(B). 29(A)(B), the vertical axis represents the formation energy calculated using formula (5). The horizontal axis indicates the energy, and the horizontal axis indicates the Fermi level. On the horizontal axis of 29(A)(B), 0.0 eV corresponds to the upper valence band (VBM), and 3. 10 eV corresponds to the conduction band edge (CBM).

[0297] In addition, in Figs. 28(A)(B) and 29(A)(B), X represents the type of defect (V O , V O F, F int, or O int ), q is the charge of the system, and Y is the unit cell equivalent The number of spins per electron is (number of up spin electrons - number of down spin electrons), and X q (Y) It is expressed in the form of

[0298] From the results shown in FIG. 28(A), V O The charge state of is 2.29 from the VBM. Up to 2.29 eV, the charge was +2, and above 2.29 eV the charge was 0 (neutral).

[0299] From the results shown in FIG. 28(B), V O The F charge state has a Fermi level of 2.9 from the VBM. Up to 4 eV, it is +1, and above 2.94 eV it is -1. The charge state changes Since the Fermi energy is 2.94 eV, close to the CBM, V O F is the donor source (n required (cause)

[0300] From the results shown in FIG. 29(A), F int The charge state of is the Fermi level 0. Up to 54 eV, the charge is +1, and from 0.54 eV to the CBM, the charge is -1. i nt Since it tends to assume a negatively charged state, it traps electrons.

[0301] From the results shown in FIG. 29(B), O int The charge state of is 1. Up to 99 eV, the charge is +1, and from 1.99 eV to 2.18 eV, the charge is 0 (neutral). and -2 from 2.18 eV to the CBM.

[0302] <2-6.V O 3> About F termination Next, <2-5.V OFor the F termination, using the formation energy of each defect described in 2> The following reaction formulas (A) and (B) were verified. Reaction formula (A): V O + F → V O F Reaction formula (B): V O F + ex.O → F(+ex.O by V O repair)

[0303] In addition, in reaction formula (A), V O F is more V O + F is more energetically stable. If there is excess oxygen, F termination is likely to occur. In reaction formula (B), ex.O represents excess oxygen. In addition, the left side of reaction formula (A) and reaction formula (B) are the reactant system, and the right side is the product system. This may be the case.

[0304] The following formula (6) was used to verify reaction formula (A), and the following formula (B) was used to verify reaction formula (A). The following formula (7) was used.

[0305]

number

[0306]

number

[0307] In formula (6), ΔE A is the generation system (V O From the formation energy of F, the reactant ( V O +F int ) is the difference in formation energy.

[0308] In addition, in formula (7), ΔE B is the generation system (F int ) from the formation energy of Ohara system (V O F+O int ) is the difference in formation energy.

[0309] In the calculation, we assumed a model in which the defects are far enough apart that they do not interact with each other. -Difference (ΔE A and ΔE B At the Fermi level where ) is positive, the reactant system is more stable and the ene Energy difference (ΔE A and ΔE B ) is negative at the Fermi level, the product system is more stable. Also, <2-5.V O As described in 2> for the F terminus of the system, the stable charge state of the system is It depends on the Fermi level. So, ΔE A and ΔE B The number of defects used to calculate The formation energy was determined as the most stable charge state at each Fermi level.

[0310] In reaction formula (A), the formation energy and the energy difference (ΔE A The calculation results of (A) are shown in FIG. 30. From the results shown in FIG. 30, is ΔE A Since is negative, V O If and F exist, then V O Fill in the blank with F to get V O It was confirmed that F is easily produced.

[0311] In addition, in reaction formula (B), the formation energy and the energy difference between the reactant and the product ( ΔE B The calculation results of ) are shown in FIG. 30(B). From the results shown in FIG. 30(B), the Fermi level When is less than 1.31 eV, O int By V O F emission from F is unlikely (i.e. The reactant is more stable), and above 1.31 eV, Oint is V O F emits F into the lattice s(F int ), V O It is more stable to repair the

[0312] Therefore, V O The membrane on which F is formed is V O With excess oxygen such that F of F is released When the electrons are released, the emitted F exists between the lattices, i.e., F int Then, the F int is an electron may be trapped in the gap.

[0313] In this way, oxygen vacancies (V O ) has F between lattices (F int ), then V O F is formed, and the V O F produces electrons. That is, V O F The oxide semiconductor that has the V O F is when there is excess oxygen (ex.O) In this case, F is released between the lattices and V O Then, the V O undergoes repair of excess oxygen. , F int It is an oxide semiconductor with F int traps electrons and creates a fixed negative charge Form.

[0314] <2-7.V O About the stability of structures containing impurities Next, V O We performed calculations to examine the stability of the structure with impurities. was set to fluorine and hydrogen. O The structure with fluorine is V O F, V O Hydrogen enters The structure is V O Let's call it H.

[0315] First, V O The stable configuration of the impurity released from V was calculated. O The explosives released from In calculating the stable configuration of the pure substance, the charge of the entire model was assumed to be neutral.

[0316] FIG. 31 shows the model used in the calculation, and Table 5 shows the calculation conditions.

[0317] [Table 5]

[0318] FIG. 31 shows a model of an InGaZnO4 crystal (112 atoms). A model was created that included impurities (F or H).

[0319] Figure 32(A)(B) shows the interstitial impurities (F or The model of the stable configuration of InGaZnO4 is shown in Figure 32(A). Fig. 32(B) shows a model of InGaZnO4 crystal. This is a model diagram of a stable arrangement of hydrogen atoms between the lattices of a quartz crystal.

[0320] In Figure 32(A), F is located at the center of an octahedron with six oxygen atoms at its vertices. In addition, in FIG. 32(B), H is an InGaZnO4 crystal. The state in which it bonds with O in the middle is energetically stable.

[0321] Here, the Pauling electronegativity relationships are shown in Table 6.

[0322] [Table 6]

[0323] As shown in Table 6, the electronegativity of H is smaller than that of O, and the difference in electronegativity is large. Therefore, the H mixed in the InGaZnO4 crystal that maintains the stoichiometric ratio is probably a mixture of O and ions. They exist in a bonded state, i.e., the O with the H bonded to it is negatively charged and the H is positively charged.

[0324] On the other hand, the electronegativity of F is greater than that of O, so it tends to be negative relative to O. However, the difference in electronegativity is smaller than that of H, so the contribution of covalent bonding is probably larger. Therefore, in the IGZO crystal, F binds to the metal in the (Ga,Zn)O layer and They tend to exist in positions (interstitial spaces) where the repulsive force of O is balanced.

[0325] Next, V O There is an impurity (F or H) in V O There are impurities (F or H) outside the In order to thermodynamically evaluate the change between the state of the reaction and the state of the reaction, we used the NEB ( Using the Nudged Elastic Band method, impurities (F or H) are O To The energy required to enter and exit and the diffusion frequency were calculated.

[0326] The NEB method was used to evaluate the diffusion barrier (Ea) required to estimate the diffusion frequency. In addition, a model was prepared that corresponds to the initial and final states of the diffusion path. (F or H) is V O The final state is when the impurity (F or H) is in V O mosquito That is, the light was emitted from the InGaZnO4 crystal (112 Using the atomic model, we created a model containing impurities (F or H) and V O Conclusion For the crystal model, impurities (F or H) are VO Models that entered (V O F and V O H) The initial state is that the impurity (F or H) is V O Models located outside of O + interstitial F, and V O + interstitial H) was taken as the final state.

[0327] In addition, the charge of the entire model is set to +1, and the calculation conditions are the same as those shown in Table 5. It was quiet.

[0328] [V O On the stability of F First, V O V, which is a structure with F in it O The calculation results of the stability of F are explained below. First, The model of the diffusion path of F in the InGaZnO4 crystal is shown in Figure 33. The calculation results of the energy change are shown in FIG. 34. The arrows in FIG. 33 indicate V O The diffusion pathway of F from F is shown.

[0329] As shown in Figures 33 and 34, there is at least one diffusion barrier in the diffusion path of F. In addition, in FIG. O The state where F is entered is V O F and F between lattices F int In addition, in FIG. 34, V O The state where F is entered is V O F and V O The state where F is emitted from F is V O +F int These are written as follows. In 34, V O From F to the right is V O corresponds to the emission of F from F, and V O +F int Left Side is VO This corresponds to the entry of F into (also called a trap).

[0330] From the results shown in Figure 34, V O Energy required for F to be released from F (diffusion barrier) is 4.59 eV, V O The energy required for F to enter the (diffusion barrier) is , 0.90 eV. Therefore, V O The energy required to release F from F is , V O Since the energy at which F enters is higher than the energy at which V O Once F gets in, it is difficult to release it. It is suggested that

[0331] [V O On the stability of H Next, V O V, which is a structure with H in O The calculation results for the stability of H are explained below. First, The model of the diffusion path of H in the InGaZnO4 crystal is shown in Figure 35. The calculation results of the energy changes are shown in FIG.

[0332] As shown in Figures 35 and 36, there is at least one diffusion barrier in the diffusion path of H. In addition, in FIG. O The state where H is entered is V O H. Also, Fig. 3 In 6, V O The state where H is entered is V O H and V O The state in which H is released from H is called V O + In FIG. 36, V O From H to the right is V O corresponds to the release of H from H, and V O +H complex to the left is V O Incorporation of H into This corresponds to a trap.

[0333] From the results shown in Figure 36, V O Energy required to release H from H (diffusion barrier) is 1.85 eV, V O The energy required for H to penetrate into the , 1.01 eV. Therefore, V O The energy required to release H from H is , V O Since the energy required for H to enter is higher than the energy required for H to enter, V O Once H gets in, it's hard to release It is suggested that

[0334] [V O F and V O Comparison of stability with H] As a result of the above calculation, V O The energy required for F to be released from F (diffusion barrier), V O When comparing the energy required to release H from H (diffusion barrier), the following I know it's going to be a relationship. F(4.59eV) > H(1.85eV)

[0335] Next, from the diffusion barrier shown above, the diffusion frequency Γ of the impurity (F or H) is calculated using the following formula ( 8) was used for the calculation.

[0336]

number

[0337] In equation (8), ν is the frequency factor, Ea is the diffusion barrier, and k B is the Boltzmann constant, T represents absolute temperature. Also, ν=1.0×10 13 S -1 It was decided.

[0338] The results of calculations using formula (8) are shown in Table 7. In Table 7, the defects at 350°C are Diffusion frequency of pure substances (F or H) and diffusion barrier of impurities (F or H) at 350℃ The impurity (F or H) pathway is V O Emissions from and V O With a trap There are two types.

[0339] [Table 7]

[0340] As described above, V O F and the oxide semiconductor RuV O When compared with H, V O F is more V O It is more stable than H. Therefore, The source and drain regions functioning as n-type regions are made of oxide semiconductors containing hydrogen. The change in resistance of the n-type region is smaller and the reliability is improved by using an oxide semiconductor containing fluorine rather than a silicon oxide. Therefore, a highly reliable semiconductor device can be obtained.

[0341] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0342] (Embodiment 3) In this embodiment, the structure of an oxide semiconductor will be described with reference to FIGS. He explains.

[0343] <3-1. Structure of oxide semiconductor> Oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned d crystalline oxide semiconductor), polycrystalline oxide Nanocrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconducting ductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- amorphous oxide semiconductors, etc. be.

[0344] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductors, and nc-OS.

[0345] Amorphous structures are generally isotropic and have no inhomogeneous structure, and are characterized by the arrangement of atoms in a metastable state. The positions are not fixed, the bond angles are flexible, and there is short-range order but no long-range order. It is said that there is no such thing.

[0346] That is, a stable oxide semiconductor is transformed into a completely amorphous In addition, the semiconductor is not isotropic (for example, A periodic oxide semiconductor cannot be called a completely amorphous oxide semiconductor. -like OS is not isotropic, but has an unstable structure with voids. In terms of instability, the a-like OS is physically an amorphous oxide semiconductor. Close to.

[0347] <3-2.CAAC-OS> First, let me explain about CAAC-OS.

[0348] CAAC-OS is an oxide that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0349] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystals was analyzed by the out-of-plane method. As shown in FIG. 37(A), a peak appears at a diffraction angle (2θ) of about 31°. The peak is attributed to the (009) plane of the InGaZnO4 crystal, so In this case, the crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be confirmed that the direction is perpendicular to the surface of the crystal, or perpendicular to the surface of the crystal. In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The nearby peak is due to a crystal structure classified into the space group Fd-3m. It is preferred that the C-OS does not exhibit such a peak.

[0350] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS in a direction parallel to the surface on which the X-ray is to be formed. When structural analysis was performed using the ane method, a peak appeared at 2θ of approximately 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. And, 2θ is fixed at around 56°. Then, the sample is rotated around the normal vector of the sample surface as an axis (φ axis) while analyzing (φ scan). Even if this is done, no clear peak appears, as shown in FIG. When 2θ is fixed at around 56° and φ is scanned for ZnO4, the results shown in Figure 37(C) As shown in the figure, six peaks attributable to crystal planes equivalent to the (110) plane are observed. XRD structural analysis revealed that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0351] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the process was parallel to the CAAC-OS surface. When an electron beam with a probe diameter of 300 nm is incident, a diffraction pattern ( This is also called a selected area electron diffraction pattern.) may appear. This diffraction pattern includes I The spots are due to the (009) plane of the nGaZnO4 crystal. Diffraction also confirmed that the pellets contained in the CAAC-OS have a c-axis orientation and that the c-axis is the unformed On the other hand, for the same sample, the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly to the ) is shown. From FIG. 37(E), a ring-shaped diffraction pattern is confirmed. Electron diffraction using an electron beam with a diameter of 300 nm also revealed that the PEG-1000 nanometers in the CAAC-OS It can be seen that the a-axis and b-axis of the slits have no orientation. The first ring is due to the (010) and (100) planes of the InGaZnO4 crystal. The second ring in FIG. 37(E) is due to the (110) plane, etc.

[0352] In addition, a transmission electron microscope (TEM) Combined analysis of bright-field images and diffraction patterns of CAAC-OS using a microscope. When observing the image (also called a high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain boundaries), are not clearly visible. (also called underly.) may not be clearly identified. It can be said that C-OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0353] Figure 38(A) shows a high-resolution cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image is shown. A spherical aberration correction (SCA) was used for high-resolution TEM imaging. The spherical aberration corrector function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. Therefore, it can be observed.

[0354] From FIG. 38(A), a pellet, which is an area where metal atoms are arranged in layers, can be confirmed. The size of each pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). CAAC-OS can also be used as a C-Axis Aligned Navigator (CANC). The pellets can also be called oxide semiconductors with no crystals. It reflects the unevenness of the surface on which the C-OS is formed or the top surface, and the unevenness of the surface on which the CAAC-OS is formed or It is parallel to the top surface.

[0355] In addition, Fig. 38(B) and Fig. 38(C) show CAA images observed from a direction approximately perpendicular to the sample surface. Cs-corrected high-resolution TEM images of the C-OS surface. 38(B) and 38(C), respectively. First, the method of processing is explained. Then, the FFT image is obtained by Fourier Transform (FFT) processing. In the acquired FFT image, the origin is used as the reference point, and the -1 From 5.0 nm -1 The range between Next, the masked FFT image is transformed by inverse fast Fourier transform (IFFT : Inverse Fast Fourier Transform) processing is used to The image obtained in this way is called an FFT filtered image. The filtered image is an image in which periodic components are extracted from a Cs-corrected high-resolution TEM image. This indicates a child array.

[0356] In FIG. 38(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area indicated by the dashed line is the connection between the pellets. The broken line shows the hexagonal shape, so we can see that the pellet is hexagonal. The shape of the let is not limited to a regular hexagon, and is often a non-regular hexagon.

[0357] In FIG. 38(E), a grid is formed between an area with a uniform lattice arrangement and an area with a different uniform lattice arrangement. The dotted lines indicate the changes in the orientation of the child array, and the dashed lines indicate the changes in the orientation of the lattice array. Even in the vicinity of the dotted line, no clear crystal grain boundaries can be confirmed. If you connect the lattice points around the center, you will get a distorted hexagon, distorted pentagon, or distorted heptagon, etc. In other words, the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because the atomic arrangement of CAAC-OS is not dense in the ab-plane direction. The substitution of metal elements causes the bond distance between atoms to change, resulting in distortion. This is believed to be because it is acceptable.

[0358] As described above, the CAAC-OS has a c-axis orientation and is Multiple pellets (nanocrystals) are connected to form a distorted crystal structure. AAC-OS, CAA crystal(c-axis-aligned abp It can also be called an oxide semiconductor having lane-anchored crystals. Cut.

[0359] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors is determined by the presence of impurities. CAAC-OS is designed to prevent impurities and defects from causing degradation. It can also be said to be an oxide semiconductor with few defects (such as oxygen vacancies).

[0360] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0361] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the ZnO traps hydrogen and becomes a carrier generation source.

[0362] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. There is. Specifically, 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than Such an oxide semiconductor can be a high-purity intrinsic or The CAAC-OS is essentially a high-purity intrinsic oxide semiconductor. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0363] <3-3.nc-OS> Next, we will explain nc-OS.

[0364] The following describes the case where nc-OS is analyzed by XRD. However, when structural analysis was performed using the out-of-plane method, no peaks indicating orientation appeared. That is, the crystals of the nc-OS do not have any orientation.

[0365] For example, an nc-OS having InGaZnO4 crystals was sliced ​​to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on the region of m, the A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in Figure 9(A) was observed. In addition, the diffraction pattern when an electron beam with a probe diameter of 1 nm is incident on the same sample ( The nanobeam electron diffraction pattern is shown in Figure 39(B). Therefore, the nc-OS has a probe diameter of 50 nm. No order was observed when an electron beam with a probe diameter of 1 nm was incident. When light is incident on it, order is confirmed.

[0366] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 39(C), an electron diffraction pattern was observed in which the spots were arranged in a substantially regular hexagonal shape. Therefore, it is considered that the nc-OS is ordered in the range of thickness less than 10 nm. It can be seen that the crystals are highly ordered. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0367] FIG. 39(D) shows the Cs-corrected height of the cross section of the nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image as the area indicated by the auxiliary lines. How to identify the crystals and the areas where no clear crystals can be identified The crystal parts in the nc-OS have a size of 1 nm to 10 nm. In particular, the size of the crystals is often between 1 nm and 3 nm. An oxide semiconductor having a size of 10 nm or more and 100 nm or less is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). o crystalline oxide semiconductor) For example, in the case of nc-OS, the grain boundaries are often not clearly visible in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, below, the crystalline part of the nc-OS may be referred to as a pellet.

[0368] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, particularly The atomic arrangement has periodicity in the region of 1 nm to 3 nm. In the case of the Cr-Al-Al-Fe-Al-Fe-O-Pb-Al-Zn ... Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. In some cases, it may be difficult to distinguish them from solid oxide semiconductors.

[0369] In addition, since the crystal orientation between the pellets (nanocrystals) is not regular, nc-OS is , oxidation with RANC (Random Aligned nanocrystals) Semiconductors or NANC (Non-Aligned nanocrystals) In other words, the oxide semiconductor has a conductivity of 1000.

[0370] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0371] <3-4.a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a semiconductor.

[0372] FIG. 40 shows a high-resolution cross-sectional TEM image of the a-like OS. is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. B) is 4.3 x 10 8 e - / nm 2 Electrons (e - ) A-like OS after irradiation These are high-resolution cross-sectional TEM images. Figures 40(A) and 40(B) show that a-like O It can be seen that striped bright regions extending in the vertical direction are observed in S from the start of electron irradiation. It can also be seen that the shape of the bright regions changes after electron irradiation. It is suspected to be a density region.

[0373] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the change in structure due to electron irradiation.

[0374] As samples, a-like OS, nc-OS and CAAC-OS are prepared. Both samples are In-Ga-Zn oxides.

[0375] First, high-resolution cross-sectional TEM images of each sample are obtained. All of the materials have crystalline parts.

[0376] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn It is known that the structure has a total of nine layers, six of which are -O layers, stacked in layers in the c-axis direction. The distance between these adjacent layers is the lattice spacing (also called the d value) of the (009) plane. The value is about the same, and is calculated to be 0.29 nm from crystal structure analysis. In the following, the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less is called InGaZ. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0377] Figure 41 shows an example of investigating the average size of the crystal parts (22 to 30 places) of each sample. The length of the lattice fringes is the size of the crystal part. e. The crystal part of the OS grows larger according to the cumulative dose of electrons used in obtaining the TEM image. From Figure 41, it can be seen that in the early stages of TEM observation, the size of the particles is about 1.2 nm. The part of the crystal that grew up (also called the initial nucleus) absorbs electrons (e - ) cumulative exposure of 4.2 × 10 8 e - / nm 2 It can be seen that the size of the crystals grows to about 1.9 nm in the n For c-OS and CAAC-OS, the cumulative electron irradiation dose was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of 100 to 150 mm. Therefore, the size of the crystalline parts of nc-OS and CAAC-OS is constant regardless of the cumulative dose of electron irradiation. , and 1.3 nm and 1.8 nm, respectively. The Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. The conditions were an acceleration voltage of 300 kV and a current density of 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter of the region was set to 230 nm.

[0378] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. That is, a-like OS is not seen in comparison with nc-OS and CAAC-OS. , it is clear that this is an unstable structure.

[0379] In addition, because of the porosity, a-like OS is more difficult to treat than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is The density of the nc-OS and the CAA The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0380] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 Less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0381] If single crystals of the same composition are not available, single crystals of different compositions may be combined in any ratio. By combining these, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density of a single crystal of a desired composition is calculated based on the ratio of the single crystals of different compositions. However, the density can be estimated by using as few types of single crystals as possible. A combined estimate is preferred.

[0382] As described above, oxide semiconductors have various structures and each structure has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the CAAC-OS and CAAC-OS.

[0383] The configuration described in this embodiment mode may be used in appropriate combination with the configurations described in other embodiments. There can be.

[0384] (Embodiment 4) In this embodiment, a display device including the transistor described in the above embodiment will be An example will be described below with reference to FIGS.

[0385] 42 is a top view showing an example of a display device. The display device 700 shown in FIG. A pixel portion 702 is provided on the first substrate 701, and a source driver is provided on the first substrate 701. A pixel portion 702, a source driver circuit portion 704, a gate driver circuit portion 706, A sealant 712 is disposed so as to surround the path portion 704 and the gate driver circuit portion 706. and a second substrate 705 disposed so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 seal the entire structure. Although not shown in FIG. 42, a display element is provided between the first substrate 701 and the second substrate 705. can be done.

[0386] The display device 700 is surrounded by a sealant 712 on the first substrate 701. A pixel section 702, a source driver circuit section 704, and a gate driver circuit section 705 are arranged in a region different from the region. and a flexible printed circuit (FPC) terminal section 708 (FPC: Flex Also, an FPC terminal portion 708 is provided. An FPC 716 is connected to the pixel section 702 and the source driver circuit. Various signals are supplied to the path section 704 and the gate driver circuit section 706. 702, a source driver circuit section 704, a gate driver circuit section 706, and an FPC terminal section Signal lines 710 are connected to the terminals 708. Various signals are supplied by the FPC 716. The signals are transmitted through a signal line 710 to a pixel section 702, a source driver circuit section 704, a gate driver A driver circuit portion 706 and an FPC terminal portion 708 are provided.

[0387] The display device 700 may include a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit is formed (for example, A driving circuit board formed of a monocrystalline semiconductor film or a polycrystalline semiconductor film is mounted on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead, we use COG (Chip On Glass) method, wire bonding method, etc. can be used.

[0388] The display device 700 also includes a pixel portion 702, a source driver circuit portion 704, and a gate The driver circuit portion 706 includes a plurality of transistors. A transistor having a specific position can be applied.

[0389] The display device 700 can also include various elements, such as: For example, electroluminescence (EL) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistor elements (light-emitting elements that emit light according to electric current) transistors, electron emission elements, liquid crystal elements, electronic ink elements, electrophoretic elements, Rowetting element, plasma display panel (PDP), MEMS (microelectromechanical systems) Electro-mechanical systems) displays (e.g., grating light bars) GLV, Digital Micromirror Device (DMD), Digital Microsha Distributed Modulation (DMS) element, Interference Modulation (IMOD) element, etc. ), piezoelectric ceramic displays, etc.

[0390] An example of a display device using an EL element is an EL display. An example of a display device using emission elements is a field emission display (FE D) or SED type flat panel display (SED: Surface-conductio n Electron-emitter Display) and others. An example of such a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). Display, reflective LCD display, direct-view LCD display, projection LCD display Examples of display devices using electronic ink elements or electrophoretic elements include: Electronic paper. Semi-transmissive LCDs and reflective LCDs are also used. In this case, a part or the whole of the pixel electrode should function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, a memory circuit such as an SRAM may be provided under the reflective electrode. This can further reduce power consumption.

[0391] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying in color are R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a pixel, and a pixel of white (W). As in the column, two colors of RGB form one color element, and different two colors are generated depending on the color element. You can also select colors to configure the color. Or, you can select one or more colors such as yellow, cyan, and magenta for RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, and may be used in monochrome display devices. The present invention can also be applied to display devices.

[0392] Also, white light is emitted from the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) In order to display full color using (W), a colored layer (also called a color filter) is The colored layer may be, for example, red (R), green (G), blue (B), or red (C). ), yellow (Y), etc. can be used in appropriate combination. In this case, the color reproducibility can be improved compared to when no color layer is used. By disposing a region having a color layer and a region not having a color layer, The white light in the region may be directly used for display. By placing the colored layer in the display, the decrease in brightness caused by the colored layer can be reduced during bright display, and power consumption can be reduced by 2. However, in some cases, the emission of light from organic EL elements and inorganic EL elements can be reduced by about 10 to 30%. When using optical elements to display full color, R, G, B, Y, and W are each emitted in different colors. By using a self-luminous element, it is possible to obtain a light emission from a colored layer. In some cases, power consumption can be reduced even further.

[0393] In addition, as a colorization method, a part of the light emitted from the above-mentioned white light is passed through a color filter. In addition to the color filter method, which converts the light into red, green, and blue by filtering the light, A method that uses two colors of light (three-color method), or a method that uses part of the light emitted from the blue light to emit red or A method for converting to green (color conversion method, quantum dot method) may be applied.

[0394] In this embodiment, a liquid crystal element and an EL element are used as display elements. 43 and 44. Note that FIG. 43 shows the area indicated by the dashed line QR in FIG. FIG. 44 is a cross-sectional view of the liquid crystal display device shown in FIG. 42, a cross-sectional view taken along dashed line QR, showing a configuration in which an EL element is used as a display element. It is.

[0395] First, the common parts shown in Figures 43 and 44 will be explained, and then the different parts will be explained. This will be explained below.

[0396] <4-1. Explanation of common parts of display device> The display device 700 shown in FIG. 43 and FIG. 44 includes a wiring portion 711 and a pixel portion 702. The display panel 700 includes a source driver circuit section 704 and an FPC terminal section 708. The line portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and The source driver circuit portion 704 includes a transistor 752. Yes.

[0397] Transistor 750 and transistor 752 are similar to transistor 100 shown above. The structures of the transistors 750 and 752 are the same as those described above. Any other transistors than those shown in the embodiment modes may be used.

[0398] The transistor used in this embodiment is made of a highly purified oxide film in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. It is possible to extend the retention time of electrical signals such as signals, and the write interval can be extended when the power is on. This allows the frequency of refresh operations to be reduced, resulting in reduced power consumption. It has the effect of suppressing power.

[0399] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed operation can be used for a liquid crystal display. By using this in a display device, the switching transistor in the pixel section and the driver circuit section In other words, the driver transistor can be formed on the same substrate as the driver circuit. Therefore, it is not necessary to use a semiconductor device formed from a silicon wafer or the like. The number of components can be reduced. By using a register, a high quality image can be provided.

[0400] The capacitor 790 is formed using the same oxide semiconductor film as that of the transistor 750. The lower electrode formed through a process of processing the semiconductor film and the source electrode of the transistor 750 The conductive film that functions as the electrode and drain electrode is formed through a process of processing the same conductive film. A transistor 750 is disposed between the lower electrode and the upper electrode. The third insulating film and the fourth insulating film are formed through a process of forming the same insulating film. That is, the capacitor 790 functions as a dielectric between the pair of electrodes. It has a laminated structure in which an insulating film is sandwiched between the insulating film.

[0401] Also, in FIG. 43 and FIG. 44, a transistor 750, a transistor 752, and a capacitor A planarization insulating film 770 is provided on the capacitor 790 .

[0402] The planarization insulating film 770 may be made of a polyimide resin, an acrylic resin, or a polyimide amide resin. Heat-resistant organic materials such as benzocyclobutene resin, polyamide resin, and epoxy resin In addition, by stacking multiple insulating films made of these materials, A planarization insulating film 770 may be formed. Alternatively, the planarization insulating film 770 may not be provided. This is also fine.

[0403] 43 and 44, the transistor 750 and the A transistor having the same structure as the transistor 752 included in the source driver circuit portion 704 is used. The configuration used is illustrated above, but is not limited to this. For example, A transistor different from that in the driver circuit section 704 may be used.

[0404] Note that different transistors are used for the pixel portion 702 and the source driver circuit portion 704. In this case, the staggered transistor and the inverted staggered transistor shown in Embodiment 1 may be used. Specifically, a staggered transistor may be used in the pixel portion 702. 703 is configured to use an inverted staggered transistor in the source driver circuit section 704, Alternatively, an inverted staggered transistor is used in the pixel portion 702, and a source driver circuit portion 704 is used. A configuration using staggered transistors is also possible. The path section 704 may be interpreted as a gate driver circuit section.

[0405] Here, a reverse switching element that can be used in the pixel portion 702 or the source driver circuit portion 704 is A hoop-type transistor is shown in FIGS.

[0406] FIG. 45(A) is a top view of a transistor 300A, and FIG. 45(B) is a 45(C) corresponds to a cross-sectional view taken along the dashed line X1-X2 shown in FIG. 5(A) along the dashed line Y1-Y2 in FIG. In (A), in order to avoid complication, some of the components of the transistor 300A are The insulating film functioning as a gate insulating film and the like are omitted in the figure. When the -X2 direction is called the channel length direction, and the dashed dotted line Y1-Y2 direction is called the channel width direction Note that the top views of the transistors in the following drawings are the same as those in FIG. Similarly, some of the components may be omitted in the drawings.

[0407] The transistor 300A includes a conductive film 304 over a substrate 302, the conductive film 304 serving as a gate electrode, and An insulating film 306 on the substrate 302 and the conductive film 304, an insulating film 307 on the insulating film 306, The oxide semiconductor film 308 on the insulating film 307 and the solder joints electrically connected to the oxide semiconductor film 308 are The conductive film 312a serving as a source electrode and the oxide semiconductor film 308 are electrically connected to each other. and a conductive film 312b functioning as a drain electrode. More specifically, an insulating film 3 is formed on the conductive films 312a and 312b and the oxide semiconductor film 308. The insulating films 314, 316, and 318 are provided. It functions as a protective insulating film for the transistor 300A.

[0408] FIG. 46(A) is a top view of a transistor 300B, and FIG. 46(B) is a top view of a transistor 300B. 46(C) corresponds to a cross-sectional view taken along the dashed line X1-X2 in FIG. 6(A) along dashed line Y1-Y2.

[0409] The transistor 300B includes a conductive film 304 over a substrate 302, the conductive film 304 serving as a gate electrode, and An insulating film 306 on the substrate 302 and the conductive film 304, an insulating film 307 on the insulating film 306, An oxide semiconductor film 308 on the insulating film 307, an insulating film 314 on the oxide semiconductor film 308, An insulating film 316 on the insulating film 314 and an opening 34 provided in the insulating film 314 and the insulating film 316 A conductive layer functioning as a source electrode is electrically connected to the oxide semiconductor film 308 through the conductive layer 1a. The oxide film 312a is oxidized through an opening 341b provided in the insulating film 314 and the insulating film 316. a conductive film 312b functioning as a drain electrode electrically connected to the semiconductor film 308; In addition, the transistor 300B, more specifically, the conductive films 312a, 312b, An insulating film 318 is provided on the insulating film 316. The insulating films 314 and 316 are The insulating film 318 functions as a protective insulating film for the oxide semiconductor film 308. It functions as a protective insulating film for the capacitor 300B.

[0410] The transistor 300A has a channel etch structure, whereas the transistor 300B has a channel etch structure. The transistor 300B shown in (A), (B), and (C) has a channel protection type structure.

[0411] FIG. 47(A) is a top view of transistor 300C, and FIG. 47(B) is a top view of transistor 300C. 47(C) corresponds to a cross-sectional view taken along the dashed line X1-X2 in FIG. 7(A) along dashed line Y1-Y2 in FIG.

[0412] The transistor 300C is insulated from the transistor 300B shown in FIGS. The insulating films 314 and 316 of the transistor 300C have different shapes. The insulating film 316 is provided in an island shape on the channel region of the oxide semiconductor film 308. The structure is similar to that of transistor 300B.

[0413] FIG. 48(A) is a top view of a transistor 300D, and FIG. 48(B) is a top view of a transistor 300C. 48(C) corresponds to a cross-sectional view taken along the dashed line X1-X2 in FIG. 8(A) along dashed line Y1-Y2.

[0414] The transistor 300D includes a conductive film 300A serving as a first gate electrode on a substrate 302. 4, an insulating film 306 on the substrate 302 and the conductive film 304, and an insulating film 307 on the insulating film 306. an oxide semiconductor film 308 on the insulating film 307; and an insulating film 314 on the oxide semiconductor film 308. The insulating film 316 on the insulating film 314 and the source electrode 316 electrically connected to the oxide semiconductor film 308 are The conductive film 312a serving as a gate electrode and the gate electrode electrically connected to the oxide semiconductor film 308 are The conductive film 312b functions as a drain electrode, and the conductive films 312a and 312b and the insulating film 31 6, and conductive films 320a and 320b on the insulating film 318.

[0415] In the transistor 300D, the insulating films 314, 316, and 318 are The second gate insulating film of the transistor 300D is also formed. In the display device, the conductive film 320a functions as a pixel electrode. The conductive film 320a is formed through an opening 342c provided in the insulating films 314, 316, and 318. In the transistor 300D, the conductive film 320b is connected to the conductive film 312b. , which functions as a second gate electrode (also called a back gate electrode).

[0416] As shown in FIG. 48C, the conductive film 320b is formed by insulating films 306, 307, 314, In the openings 342a and 342b provided in the gate electrodes 316 and 318, Therefore, the conductive film 320b and the conductive film 304 are connected to each other. The same potential is applied.

[0417] In the transistor 300D, openings 342a and 342b are provided, and the conductive film 3 Although the configuration in which 20b and the conductive film 304 are connected has been illustrated, the present invention is not limited to this. For example, , only one of the openings 342a and 342b is formed, and the conductive film 3 20b and the conductive film 304, or openings 342a and 342b are provided. In this case, the conductive film 320b and the conductive film 304 may not be connected to each other. In the case where the conductive film 320b is not connected to the conductive film 304, the conductive film 320b and the conductive film 304 are Each of the electrodes can be given a different potential.

[0418] The transistor 300D has the S-channel structure described above.

[0419] In addition, the oxide semiconductor film of the transistor 300A shown in FIGS. 308 may be a multi-layer structure. An example of such a structure is shown in FIG. 49(A)(B)(C)(D) ) as shown in

[0420] 49(A) and (B) are cross-sectional views of a transistor 300E, and FIGS. 1 and 2 are cross-sectional views of the transistor 300F. The diagram is similar to the transistor 300A shown in FIG.

[0421] The oxide semiconductor film 308 included in the transistor 300E illustrated in FIGS. A nitride semiconductor film 308_1, an oxide semiconductor film 308_2, and an oxide semiconductor film 308_3. In addition, the oxide semiconductor of the transistor 300F shown in FIG. The oxide semiconductor film 308 includes an oxide semiconductor film 308_2 and an oxide semiconductor film 308_3.

[0422] Note that the conductive film 304, the insulating film 306, the insulating film 307, the oxide semiconductor film 308, and the conductive film 3 12a, a conductive film 312b, an insulating film 314, an insulating film 316, an insulating film 318, and a conductive film 32 320a and 320b are the conductive film 114 and the insulating film 11 described in the first embodiment, respectively. 6, insulating film 110, oxide semiconductor film 108, conductive film 120a, conductive film 120b, insulating film 1 04, the insulating film 118, the insulating film 116, and the conductive film 114 are formed using the materials and the forming methods described therein. good.

[0423] In addition, the structures of the transistors 300A to 300F can be freely combined. They may be used in combination.

[0424] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed through the same process as the conductive film that functions as the transistor. A conductive film formed through a process different from that of the source electrode and drain electrode of 750 and 752, e.g. For example, an oxide semiconductor film formed through the same process as an oxide semiconductor film functioning as a gate electrode may be used. For example, when a material containing copper is used as the signal line 710, the wiring There is little signal delay caused by line resistance, making it possible to display on a large screen.

[0425] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed through the same process as the conductive film that functions as the drain electrode. , and is electrically connected to a terminal of the FPC 716 via an anisotropic conductive film 780 .

[0426] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0427] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film. A device for controlling the distance (cell gap) between the first substrate 701 and the second substrate 705 is provided. In addition, a spherical spacer may be used as the structure 778.

[0428] In addition, on the second substrate 705 side, a light-shielding film 738 functioning as a black matrix and A colored film 736 that functions as a color filter, a light-shielding film 738 that is in contact with the colored film 736, and An insulating film 734 is provided.

[0429] <4-2. Configuration examples of display devices using liquid crystal elements> The display device 700 shown in FIG. 43 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film The conductive film 774 is a second substrate 705. The display device 700 shown in FIG. The alignment state of the liquid crystal layer 776 changes depending on the voltage applied to the conductive film 772 and the conductive film 774. By controlling the light transmission or non-transmission, an image can be displayed.

[0430] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is connected to a conductive film that functions as a pixel electrode. The conductive film 772 functions as a reflective electrode, that is, one of the electrodes of the display element. The display device 700 shown in FIG. The liquid crystal display device 730 is a so-called reflective color liquid crystal display device, which reflects the light and displays it through the colored film 736.

[0431] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a reflectivity can be used. For example, a material containing one of the elements indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum In this embodiment, the conductive film 772 may be formed of A conductive film that is reflective in visible light is used.

[0432] In the display device 700 shown in FIG. The unevenness is provided in a part. For example, the flattening insulating film 770 is made of a resin film. The surface of the resin film may be provided with irregularities to form the reflecting electrode. The conductive film 772 is formed along the above-mentioned unevenness. When the light is incident on the conductive film 772, the light can be diffusely reflected on the surface of the conductive film 772. It is possible to improve the performance.

[0433] The display device 700 shown in FIG. 43 is a reflective color liquid crystal display device. However, the present invention is not limited to this. For example, the conductive film 772 may be a conductive film that transmits visible light. A transmissive color liquid crystal display device may be formed by using the above-mentioned. In this case, the unevenness provided in the planarization insulating film 770 does not necessarily have to be provided.

[0434] Although not shown in FIG. 43, the conductive films 772 and 774 on the side in contact with the liquid crystal layer 776 In addition, although not shown in FIG. Optical members (optical substrates) such as optical members, phase difference members, and anti-reflection members may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. Crites, sidelights, etc. may also be used.

[0435] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, the liquid crystal material can have a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0436] In addition, when the in-plane switching method is adopted, liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. Since the liquid crystal display has a short rotational angle and is optically isotropic, no alignment treatment is required. Since the rubbing process is unnecessary, electrostatic damage caused by the rubbing process is prevented. This can prevent the occurrence of defects or damage to the liquid crystal display device during the manufacturing process. Furthermore, liquid crystal materials exhibiting a blue phase have little viewing angle dependency.

[0437] In addition, when liquid crystal elements are used as display elements, TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero lectric Liquid Crystal) mode, AFLC (AntiFerr Electrochemical Liquid Crystal (ECC) mode can be used. .

[0438] In addition, normally black type liquid crystal display devices, for example, those using a vertical alignment (VA) mode The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode mode, ASV mode, etc. can be used.

[0439] <4-3. Display devices using light-emitting elements> The display device 700 shown in FIG. 44 includes a light-emitting element 782. The light-emitting element 782 is a conductive film The display device 700 shown in FIG. The EL layer 786 of the light element 782 emits light, thereby displaying an image. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0440] Examples of materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dots. materials, alloy type quantum dot materials, core-shell type quantum dot materials, core type quantum dot materials, In addition, the elements of the 12th and 16th families, the 13th and 15th families, or the 14th and 16th families Materials containing the element group may also be used. Cadmium (Cd), selenium (Se), Zinc (Zn), Sulfur (S), Phosphorus (P), Indium (In), Tellurium (Te), Lead (P b) Quantum with elements such as gallium (Ga), arsenic (As), aluminum (Al), etc. Dot material may also be used.

[0441] The conductive film 784 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is connected to a conductive film that functions as a pixel electrode. The conductive film 784 functions as an electrode, that is, one of the electrodes of the display element. In the above, a conductive film that transmits light or a conductive film that reflects visible light can be used. Examples of conductive films that are transparent to visible light include indium (In), zinc (Zn), and ZnO. It is recommended to use a material containing one of the following elements: Zn (Zn) or tin (Sn). The reflective conductive film may be made of a material containing aluminum or silver. stomach.

[0442] In addition, in the display device 700 shown in FIG. 44, an insulating film is provided on the planarization insulating film 770 and the conductive film 784. An insulating film 730 is provided. The insulating film 730 covers a part of the conductive film 784. 782 has a top emission structure. Therefore, the conductive film 788 has a light transmitting property, and It transmits the light emitted by the L layer 786. In this embodiment, the top emission The structure is exemplified, but is not limited to this. For example, a bottom emission structure in which light is emitted to both the conductive film 784 and the conductive film 788; It can also be applied to al-emission structures.

[0443] A colored film 736 is provided at a position overlapping the light emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided at the position where the light-shielding film 738 is to be formed, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is illustrated. For example, when the EL layer 786 is formed by coloring, The film 736 may not be provided.

[0444] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0445] (Embodiment 5) In this embodiment, the memory contents can be retained even when power is not supplied, and writing is possible. An example of a circuit configuration of a semiconductor device with no limit on the number of times of reading will be described with reference to FIG.

[0446] <5-1. Circuit configuration> FIG. 50 is a diagram illustrating a circuit configuration of a semiconductor device. In FIG. 1st Line) and the source electrode or drain electrode of p-type transistor 1280a The other side is electrically connected to the source electrode of the p-type transistor 1280a. The other of the source and drain electrodes of the n-type transistor 1280b is connected to the source or drain electrode of the n-type transistor 1280c. The source voltage of the n-type transistor 1280b is electrically connected to one of the electrodes. The other of the electrode or drain electrode of the n-type transistor 1280c is connected to the source electrode or drain electrode of the n-type transistor 1280c. The electrode is electrically connected to one of the electrodes.

[0447] In addition, the second wiring (2nd Line) and the source electrode of the transistor 1282 or The source electrode of the transistor 1282 is electrically connected to one of the drain electrodes. The other of the source electrode or drain electrode, one of the electrodes of the capacitor 1281 and the n-type transistor The gate electrode of the second transistor 1280c is electrically connected to the gate electrode of the first transistor 1280a.

[0448] In addition, a third wiring (3rd Line), a p-type transistor 1280a, and an n-type transistor The gate electrode of the transistor 1280b is electrically connected to the fourth wiring (4 th Line) and the gate electrode of the transistor 1282 are electrically connected In addition, the fifth wiring (5th Line), the other electrode of the capacitor element 1281, and the n-type transistor The other of the source electrode or the drain electrode of the transistor 1280c is electrically connected. In addition, the sixth line and the source of the p-type transistor 1280a The other of the electrode or drain electrode and the source electrode or drain electrode of the n-type transistor 1280b The electrode is electrically connected to one of the in-electrodes.

[0449] Note that the transistor 1282 is an oxide semiconductor (OS). Therefore, in FIG. The symbol “OS” is added to the transistor 1282. Note that the transistor 1282 is made of an oxide semiconductor. It may be formed from materials other than those.

[0450] In addition, in FIG. 50, the other of the source electrode or the drain electrode of the transistor 1282 One of the electrodes of the capacitor 1281 and the gate electrode of the n-type transistor 1280c The connection point is labeled as a floating node (FN). By turning off the floating node, one of the electrodes of the capacitor 1281, and the n The potential applied to the gate electrode of the second type transistor 1280c can be maintained.

[0451] In the circuit configuration shown in FIG. 50, the potential of the gate electrode of the n-type transistor 1280c can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0452] <5-2. Writing and storing information> First, writing and holding of data will be described. The transistor 1282 is turned on by applying a potential to the transistor 1282. As a result, the potential of the second wiring is applied to the gate electrode of the n-type transistor 1280c and the capacitor 12 That is, a predetermined voltage is applied to the gate electrode of the n-type transistor 1280c. Then, the potential of the fourth wiring is applied to the transistor 1282. The transistor 1282 is turned off by applying a potential to the n-type transistor 1281. The charge applied to the gate electrode of transistor 1280c is retained (retained).

[0453] Since the off-state current of the transistor 1282 is extremely small, the The charge on the gate electrode is retained for a long period of time.

[0454] <5-3. Reading information> Next, the reading of information will be described. At this time, the p-type transistor 1280a is turned on and the n-type transistor 1280b is turned off. At this time, the potential of the first wiring is applied to the sixth wiring. On the other hand, When the potential is set to a high level potential, the p-type transistor 1280a is turned off, and At this time, the floating node (FN) Depending on the amount of charge stored, the sixth wire has a different potential. By looking at the position, the stored information can be read (read).

[0455] In addition, the transistor 1282 is extremely The off-state current of the transistor 1282 using an oxide semiconductor is small. The off-state current is less than 1 / 100,000 of that of transistors made of silicon semiconductors, etc. Since the transistor 1282 is a current, the floating node (FN) It is possible to ignore the loss of the stored charge. A non-volatile memory circuit that can retain information even without power supply using the transistor 1282 It is possible to achieve the following.

[0456] In addition, a semiconductor device using such a circuit configuration may be used as a register, a cache memory, or the like. By using it in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire storage device or one or more components constituting the storage device can be In logic circuits, the power can be stopped for a short time during standby, so the power consumption is reduced. This can reduce power consumption.

[0457] The configurations, methods, etc. described in this embodiment may be different from the configurations, methods, etc. described in other embodiments. They can be used in appropriate combination.

[0458] (Embodiment 6) In this embodiment, a configuration of a pixel circuit that can be used in a semiconductor device of one embodiment of the present invention will be described. The following will explain this with reference to FIG.

[0459] <6-1. Pixel circuit configuration> FIG. 51(A) is a diagram illustrating the configuration of a pixel circuit. The circuit shown in FIG. Electrical conversion element 1360, transistor 1351, transistor 1352, transistor 13 53, and a transistor 1354.

[0460] The anode of the photoelectric conversion element 1360 is connected to the wiring 1316, and the cathode is connected to the transistor The transistor 1351 is connected to one of the source electrode and the drain electrode of the transistor 1351. The other of the source electrode and the drain electrode is connected to the charge storage section (FD), and the gate electrode is The source electrode or drain electrode of the transistor 1352 is connected to the line 1312 (TX). One of the electrodes is connected to the wiring 1314 (GND), and the other of the source electrode or drain electrode is The gate electrode is connected to one of the source electrode and the drain electrode of the transistor 1354. The source electrode or drain electrode of the transistor 1353 is connected to the charge storage portion (FD). One of the electrodes is connected to the charge storage section (FD), and the other is the source electrode or drain electrode. The gate electrode of the transistor 1 is connected to the wiring 1311 (RS). The other of the source electrode or drain electrode of 354 is connected to the wiring 1315 (OUT). The port electrode is connected to a wiring 1313 (SE). Note that all of the above connections are electrical connections. do.

[0461] The wiring 1314 may be supplied with a potential such as GND, VSS, or VDD. Here, potential and voltage are relative. Therefore, the magnitude of the GND potential is always However, it is not necessarily 0 volts.

[0462] The photoelectric conversion element 1360 is a light receiving element that generates a current according to the light incident on the pixel circuit. The transistor 1353 functions as a charge storage portion (F The transistor 1354 has a function of controlling charge accumulation in the charge accumulation unit (FD The transistor 1352 has a function of outputting a signal according to the potential of the charge storage portion ( The transistor 1352 has a function of resetting the potential of the pixel It has the function of controlling the selection of circuits.

[0463] The charge storage unit (FD) is a charge storage node, and the photoelectric conversion element 1360 receives It holds an electrical charge that changes depending on the amount of light.

[0464] The transistor 1352 and the transistor 1354 are connected to the wiring 1315 and the wiring 131 4. Therefore, the wiring 1314 and the transistor 13 52, the transistor 1354, and the wiring 1315 may be arranged in this order. Alternatively, the transistor 1354, the transistor 1352, and the wiring 1315 may be arranged in this order.

[0465] The wiring 1311 (RS) functions as a signal line for controlling the transistor 1353. The wiring 1312 (TX) serves as a signal line for controlling the transistor 1351. The wiring 1313 (SE) is a signal for controlling the transistor 1354. The wiring 1314 (GND) serves as a reference potential (for example, GND). The wiring 1315 (OUT) functions as a signal line for determining whether The wiring 1316 functions as a signal line for reading out a signal output from the As a signal line for outputting electric charge from the storage unit (FD) via the photoelectric conversion element 1360 The wiring 1317 has a charge transfer function and is a low potential line in the circuit of FIG. It has a function as a signal line for resetting the potential of the storage section (FD), and is shown in FIG. In the circuit, it is a high potential line.

[0466] Next, the configuration of each element shown in FIG. 51(A) will be described.

[0467] <6-2. Photoelectric conversion element> The photoelectric conversion element 1360 contains selenium or a compound containing selenium (hereinafter referred to as a selenium-based material). or silicon-containing devices (e.g., devices in which pin-type junctions are formed). In addition, a transistor using an oxide semiconductor and a transistor using selenium By combining it with a photoelectric conversion element using a material based on ZnO, reliability can be improved. preferable.

[0468] <6-3.Transistor> Transistor 1351, transistor 1352, transistor 1353, and transistor Zysta 1354 is a material that can be used for amorphous silicon, microcrystalline silicon, polycrystalline silicon, and single crystal silicon. Although it is possible to form the transistor using a silicon semiconductor such as oxide semiconductor, It is preferable that the transistor has a channel formation region formed of an oxide semiconductor. The transistor has the characteristic of exhibiting an extremely low off-state current. As a transistor having a channel forming region, for example, the transistor shown in the first embodiment may be used. A star can be used.

[0469] In particular, a transistor 1351 connected to the charge storage unit (FD) and a transistor If the leakage current of 1353 is large, the charge stored in the charge storage section (FD) can be held for a long time. Therefore, the distance between the two transistors is insufficient. By using a transistor that uses this technology, unnecessary charge leakage from the charge storage section (FD) is prevented. It can be stopped.

[0470] In addition, the transistor 1352 and the transistor 1354 also have a large leakage current. If the voltage is too high, unnecessary charge will be output to the wiring 1314 or wiring 1315. A transistor in which a channel formation region is formed using an oxide semiconductor is used as the transistor. It is preferable.

[0471] FIG. 51A illustrates a transistor having one gate electrode. However, the present invention is not limited to this, and may have a configuration having a plurality of gate electrodes. As a transistor having a gate electrode, for example, a semiconductor having a channel forming region is used. a first gate electrode and a second gate electrode (also called a backgate electrode) overlapping the body membrane; The back gate electrode may have a structure having, for example, a first gate electrode and The gate electrode may be given the same potential, a floating potential, or a potential different from that of the first gate electrode.

[0472] <6-4. Circuit operation timing chart> Next, an example of the circuit operation of the circuit shown in FIG. 51(A) will be described with reference to the timing shown in FIG. 51(B). This will be explained using a diagram.

[0473] In FIG. 51B, for the sake of simplicity, the potential of each wiring is given as a signal that changes into two values. However, since each potential is an analog signal, it is not limited to binary values ​​and may be various depending on the situation. Note that the signal 1401 shown in FIG. 51B is the potential of the wiring 1311 (RS). A signal 1402 is the potential of the wiring 1312 (TX), and a signal 1403 is the potential of the wiring 1313 (SE). The potential, signal 1404, is the potential of the charge storage unit (FD), and the signal 1405 is the potential of the wiring 1315 (OUT The potential of the wiring 1316 is always “Low”, and the potential of the wiring 1317 is always “Low”. is always set to “High”.

[0474] At time A, the potential of the wiring 1311 (signal 1401) is set to “High” and the potential of the wiring 1312 is set to “High”. When the potential (signal 1402) of the charge storage unit (FD) is set to "High", the potential (signal 14 04) is initialized to the potential of the wiring 1317 ("High"), and the reset operation begins. Note that the potential of the wiring 1315 (signal 1405) is precharged to "High". .

[0475] At time B, when the potential of the wiring 1311 (signal 1401) is set to “Low”, the reset The operation ends and the accumulation operation begins. Here, the photoelectric conversion element 1360 has a reverse bias. Since a reverse current flows, the potential (signal 1404) of the charge storage section (FD) When the photoelectric conversion element 1360 is irradiated with light, the reverse current increases, so The rate at which the potential (signal 1404) of the charge storage section (FD) drops varies depending on the amount of light irradiated. That is, the transistor 135 The channel resistance between the source and drain of 4 changes.

[0476] At time C, when the potential of the wiring 1312 (signal 1402) is set to “Low”, the accumulation operation Then, the potential (signal 1404) of the charge storage unit (FD) becomes constant. is determined by the amount of charge generated by the photoelectric conversion element 1360 during the accumulation operation. The output of the transistor 135 changes depending on the amount of light irradiated onto the conversion element 1360. The transistor 1353 is an off-state current transistor having a channel formation region formed of an oxide semiconductor. Since it is composed of transistors with extremely low It is possible to keep the potential of the charge storage section (FD) constant until

[0477] When the potential of the wiring 1312 (signal 1402) is set to “Low”, The potential of the charge storage unit (FD) changes due to the parasitic capacitance between the charge storage unit (FD) and the If the change in the potential is large, the photoelectric conversion element 136 may Therefore, the amount of charge generated by 0 cannot be accurately obtained. To reduce the amount of change in the potential, , the gate electrode-source electrode (or gate electrode-drain electrode) of the transistor 1351 ) capacitance, increasing the gate capacitance of the transistor 1352, and In this embodiment, it is effective to provide a storage capacitor for the The change in potential is assumed to be negligible due to the above measures.

[0478] At time D, when the potential of the wiring 1313 (signal 1403) is set to “High”, the transistor The transistor 1354 becomes conductive to start the selection operation, and the wiring 1314 and the wiring 1315 become Then, the potential of the wiring 1315 ( The signal 1405) drops. Note that the precharge of the wiring 1315 is completed before time D. The rate at which the potential of the wiring 1315 (signal 1405) decreases is It depends on the current between the source and drain electrodes of the transistor 1352. It changes depending on the amount of light irradiated onto the photoelectric conversion element 1360 during operation.

[0479] At time E, when the potential of the wiring 1313 (signal 1403) is set to “Low”, the transistor The resistor 1354 is cut off, the selection operation is terminated, and the potential of the wiring 1315 (signal 1405) Here, the constant value is determined by the amount of light irradiated onto the photoelectric conversion element 1360. Therefore, by acquiring the potential of the wiring 1315, Therefore, the amount of light irradiated onto the photoelectric conversion element 1360 can be known.

[0480] More specifically, when the light irradiating the photoelectric conversion element 1360 is strong, the charge storage portion (F D), i.e., the gate voltage of transistor 1352, drops. The current flowing between the source electrode and the drain electrode of the transistor 1352 becomes small, and the wiring 1315 Therefore, the potential of the signal 1405 is relatively low from the wiring 1315. A high potential can be read out.

[0481] Conversely, when the light irradiating the photoelectric conversion element 1360 is weak, the potential of the charge storage unit (FD) That is, the gate voltage of the transistor 1352 becomes high. The current flowing between the source electrode and the drain electrode of 352 becomes large, and the potential of the wiring 1315 ( The signal 1405) falls quickly. Therefore, a relatively low potential is read from the wiring 1315. It can be put out.

[0482] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is Noh.

[0483] (Embodiment 7) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0484] <7. Circuit configuration of display device> The display device shown in FIG. 52(A) has a region having pixels of a display element (hereinafter referred to as a pixel portion 502). ) and a circuit section ( hereinafter referred to as a drive circuit section 504) and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 50 6) and a terminal portion 507. Note that the protection circuit 506 is not provided. This is also fine.

[0485] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or the whole of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Band). It can be implemented by using the onding.

[0486] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter, referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter, a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a) to provide a signal (data signal) for driving the display element of the pixel. The pixel circuit 504 includes a driver circuit such as a circuit (hereinafter, referred to as a source driver 504b).

[0487] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is input via a terminal unit 507, and a signal is output. For example, a start pulse signal, a clock signal, etc. are input to the gate driver 504a. The gate driver 504a outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it. However, the gate driver 50 has a function of supplying 4a may also provide another signal.

[0488] The source driver 504b includes a shift register and the like. Through the terminal section 507, a signal for driving the shift register as well as a source of a data signal are input. The source driver 504b outputs a pixel circuit based on the image signal. The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated according to a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The potential of the wiring (hereinafter, referred to as data lines DL_1 to DL_Y) connected to the data line DL_Y is controlled by the Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may also supply other signals. It is possible.

[0489] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a number of analog switches, The image signal can be time-division-multiplexed and output as a data signal. Also, a shift register, etc. This may be used to configure the source driver 504b.

[0490] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is inputted through the data line DL, and a data signal is given through one of the data lines DL. A data signal is input to each of the pixel circuits 501. 504a controls writing and holding of data of the data signal. For example, The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or smaller than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via a source driver 504c (n is a natural number equal to or smaller than Y).

[0491] The protection circuit 506 shown in FIG. 52(A) is, for example, a gate driver 504a and a pixel circuit 5 01. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the driver 504b and the pixel circuit 501. The protection circuit 506 can be connected to a wiring between the gate driver 504a and the terminal unit 507. Alternatively, the protection circuit 506 may be a wiring between the source driver 504b and the terminal unit 507. The terminal unit 507 can be connected to a power supply and a power supply line from an external circuit to the display device. This refers to the part provided with terminals for inputting control signals and image signals.

[0492] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit This is a circuit that brings one wire into electrical continuity with another wire.

[0493] As shown in FIG. 52A, a protection circuit 50 is provided in each of a pixel section 502 and a driver circuit section 504. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrent caused by electrostatic discharge (ESD) and the like. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a protection circuit 506 is connected to the source driver 504b Alternatively, a protection circuit 506 may be connected to the terminal portion 507. It can also be written as:

[0494] In FIG. 52(A), the gate driver 504a and the source driver 504b Therefore, although an example in which the driver circuit portion 504 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a source driver circuit is formed separately. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is It may also be configured to be equipped with

[0495] In addition, the pixel circuits 501 shown in FIG. 52(A) may have a configuration shown in FIG. 52(B), for example. It can be said that:

[0496] The pixel circuit 501 shown in FIG. 52B includes a liquid crystal element 570, a transistor 550, and a capacitor. The transistor 550 may be any of the transistors described in the previous embodiment. can be applied.

[0497] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. A different potential may be applied to one of the electrodes.

[0498] For example, the display device including the liquid crystal element 570 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned M icro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode, etc. may also be used. In addition to the above-mentioned driving method, the display device can be driven by an ECB (Electric Carrier Bipolar Transistor) or the like. Ally Controlled Birefringence mode, PDLC(P Oligomeric Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest hole However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of different types of sensors can be used.

[0499] In the pixel circuit 501 in the mth row and the nth column, One of the electrodes is electrically connected to the data line DL_n, and the other is a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the scan lines G L_m. The transistor 550 can be turned on or off. Thus, the data write of the data signal is controlled.

[0500] One of a pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0501] For example, in a display device having the pixel circuit 501 shown in FIG. The pixel circuits 501 in each row are sequentially selected by a gate driver 504a shown in FIG. 550 is turned on to write data of the data signal.

[0502] In the pixel circuit 501 in which data has been written, the transistor 550 is turned off. By repeating this process row by row, an image can be displayed.

[0503] In addition, the pixel circuits 501 shown in FIG. 52(A) may have a configuration shown in FIG. 52(C), for example. It can be said that:

[0504] The pixel circuit 501 shown in FIG. 52C includes transistors 552 and 554 and a capacitance element. The transistor 552 and the transistor 554 The transistor described in the above embodiment can be used for either or both of the above. .

[0505] A data signal is applied to one of the source and drain electrodes of the transistor 552. The transistor 5 is electrically connected to a wiring (hereinafter, referred to as a data line DL_n). The gate electrode 52 is connected to a wiring (hereinafter, referred to as a scanning line GL_m) to which a gate signal is applied. are electrically connected.

[0506] Transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of data.

[0507] One of a pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL _a), and the other is electrically connected to the source electrode and drain electrode of the transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0508] The capacitor 562 functions as a storage capacitor for storing written data.

[0509] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. In addition, the gate electrode of the transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0510] One of the anode and the cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b. The other one is electrically connected to the other of the source electrode and drain electrode of the transistor 554. will be done.

[0511] The light-emitting element 572 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light-emitting element 572 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0512] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0513] In a display device having the pixel circuit 501 shown in FIG. 52(C), for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0514] In the pixel circuit 501 to which the data has been written, the transistor 552 is turned off. Furthermore, the transistor 554 is in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted with a brightness that corresponds to the flow rate. By performing this process row by row, an image can be displayed.

[0515] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0516] (Embodiment 8) In this embodiment, the circuit configuration to which the transistors described in the above embodiment can be applied is An example will be described with reference to FIGS.

[0517] Note that in this embodiment, the transistor having the oxide semiconductor described in the above embodiment In the following description, the above-mentioned transistor will be referred to as an OS transistor.

[0518] <8. Example of inverter circuit configuration> FIG. 53(A) shows a circuit that can be applied to a shift register, a buffer, etc. in a driver circuit. 8 shows a circuit diagram of an inverter 800 that can convert the logic of a signal provided to an input terminal IN into a The inverter 800 outputs an inverted signal of the OS transistors to the output terminal OUT. Signal S BG is a signal for varying the electrical characteristics of the OS transistor. .

[0519] 53B is a circuit diagram of an example of the inverter 800. The inverter 800 includes: The inverter 800 includes an OS transistor 810 and an OS transistor 820. In other words, the transistor can be fabricated as an n-channel transistor, and can have a so-called unipolar circuit configuration. Therefore, it can be manufactured at low cost compared to a CMOS inverter.

[0520] The OS transistors 810 and 820 each have a first gate functioning as a front gate and a back gate. The second gate acts as a gate electrode and the first gate acts as either a source or a drain. It has one terminal, a second terminal which functions as the other of the source or drain.

[0521] The first gate of the OS transistor 810 is connected to the second terminal. The second gate of 10 is the signal S BG The OS transistor 810 is connected to a wiring The first terminal of the OS transistor 810 is connected to a wiring that supplies a voltage VDD. is connected to the output terminal OUT.

[0522] A first gate of the OS transistor 820 is connected to the input terminal IN. A second gate of the OS transistor 820 is connected to the input terminal IN. The second terminal of the OS transistor 820 is connected to the output terminal OUT. The GND is connected to a wire that supplies

[0523] FIG. 53C is a timing chart for explaining the operation of the inverter 800. In the timing chart of Figure 53(C), the signal waveform of the input terminal IN and the output terminal OUT Signal waveform, signal S BG The signal waveform and the operating state of the OS transistor 810 (FET 810) are shown in FIG. 4 shows the change in threshold voltage.

[0524] signal S BG is applied to the second gate of the OS transistor 810, Threshold voltage of 810 (V TH ) can be controlled.

[0525] signal S BG V TH Voltage V for negative shift BG_A , V TH Plus Voltage to shift V BG_B The second gate has a voltage V BG_A Giving The OS transistor 810 has a threshold voltage V TH_A It is possible to shift the Also, the second gate can be connected to the voltage V BG_B By providing the above, the OS transistor 810 has Threshold voltage V TH_B can be shifted positively to

[0526] That is, the OS transistor 810 has a second gate as shown in the graph of FIG. By increasing the voltage, the curve can be shifted to the dashed line 840. By reducing the voltage of the second gate, the curve can be shifted to the solid line 841. can.

[0527] Threshold voltage V TH_B By positively shifting the voltage to As shown in FIG. 54(B), the flowing current I B Therefore, the signal applied to the input terminal IN is high. When the OS transistor 820 is in an ON state, the voltage at the output terminal OUT is Therefore, in the timing chart shown in FIG. In addition, when the voltage VDD is applied, the signal waveform 831 at the output terminal can be made to change sharply. This reduces the through current that flows between the wiring that supplies the VSS voltage and the wiring that supplies the VSS voltage. Therefore, it is possible to operate with low power consumption.

[0528] In addition, the threshold voltage V TH_A By shifting the voltage to the negative side, the OS transistor 81 0 can be made a state in which current easily flows. As shown in FIG. 54(C), The current I A At least the current I B Therefore, the input When the signal applied to the terminal IN is at a low level, the OS transistor 820 is in an off state (OFF). Therefore, the voltage at the output terminal OUT can be increased sharply. In the timing chart shown in FIG. 1, the signal waveform 832 at the output terminal can be made to change sharply. can.

[0529] In addition, signal S BG V of OS transistor 810 TH Control is OS transistor 8 It is preferable to perform this before the state of 20 is switched, that is, before time T1 or T2. For example, as shown in FIG. 53(C), when the signal applied to the input terminal IN is switched to a high level, Before the time T1, the threshold voltage V TH_AFrom the threshold voltage V TH_B To O It is preferable to switch the threshold voltage of the S transistor 810. Also, FIG. As shown in the figure, the signal applied to the input terminal IN is switched to a low level at time T2. Before, the threshold voltage V TH_B to threshold voltage V TH_A In the OS transistor 810 It is preferable to switch the threshold voltage.

[0530] In the timing chart of FIG. 53(C), the signal changes according to the signal applied to the input terminal IN. No.S BG However, other configurations may be used. For example, the threshold voltage is The control voltage is applied to the second gate of the OS transistor 810 in a floating state. An example of a circuit configuration that can realize this configuration is shown in FIG. As shown in (A).

[0531] In FIG. 55A, in addition to the circuit configuration shown in FIG. 53B, an OS transistor 850 The first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810. The second terminal of the OS transistor 850 is connected to a voltage V BG_B (or Pressure V BG_A The first gate of the OS transistor 850 is connected to a wiring that provides a signal No.S F The second gate of the OS transistor 850 is connected to a wiring that supplies a voltage V BG _B (or voltage V BG_A ) is connected to the wire that provides the

[0532] The operation of FIG. 55(A) will be described with reference to the timing chart of FIG. 55(B).

[0533] As in FIG. 53C, the voltage for controlling the threshold voltage of the OS transistor 810 is The OS transistor is turned on before the time T3 when the signal applied to the input terminal IN is switched to high level. The signal S is provided to the second gate of the transistor 810. F High-level OS transaction The transistor 850 is turned on, and the node N BG Voltage V for controlling the threshold voltage B G_B Gives.

[0534] Node N BG is the voltage V BG_B After this, the OS transistor 850 is turned off. The OS transistor 850 has an extremely small off-state current and can be kept in an off state. So, once node N BG The voltage V held at BG_B Therefore, A voltage V BG_B The number of actions required to give the Voltage V BG_B Therefore, the power consumption required for rewriting the data can be reduced.

[0535] In the circuit configurations in FIGS. 53B and 55A, the second We have shown a configuration in which the voltage applied to the gate is controlled from outside, but we will also consider other configurations. For example, a signal for controlling the threshold voltage may be applied to the input terminal IN. and provided to the second gate of the OS transistor 810. FIG. 56A shows an example of a circuit configuration that can realize the above configuration.

[0536] In FIG. 56(A), the input terminal IN and the OS transistor are connected in the circuit configuration shown in FIG. A CMOS inverter 860 is provided between the second gate of the transistor 810 and the CMOS inverter 860. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The output terminal is connected to the second gate of OS transistor 810.

[0537] The operation of FIG. 56(A) will be described with reference to the timing chart of FIG. 56(B). In the timing chart of Figure 56(B), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are 8, the output waveform IN_B of the CMOS inverter 860, and the OS transistor 810 ( 8 shows the change in threshold voltage of FET 810.

[0538] The output waveform IN_B, which is the inverted signal of the signal applied to the input terminal IN, is shown in Figure 53 ( As in C), the threshold voltage of the OS transistor 810 can be controlled. As described in FIG. 4(A) to FIG. 54(C), the threshold voltage of the OS transistor 810 is For example, at time T4 in FIG. 56(B), the voltage applied to the input terminal IN is When the signal is at a high level, the OS transistor 820 is turned on. Therefore, the OS transistor 810 is in a state where it is difficult for a current to flow. This allows the voltage at the output terminal OUT to drop sharply.

[0539] At time T5 in FIG. 56(B), the signal applied to the input terminal IN becomes low. At this time, the OS transistor 820 is turned off. Therefore, the OS transistor 810 can be in a state where a current easily flows. This allows the voltage at the output terminal OUT to rise sharply.

[0540] As described above, in the configuration of this embodiment, the inverter having the OS transistor The back gate voltage is switched according to the logic of the signal at the input terminal IN. By using this configuration, the threshold voltage of the OS transistor can be controlled. The threshold voltage of the OS transistor is controlled by the signal applied to IN. This makes it possible to make the OUT voltage change steeper. In addition, This allows the current to be reduced, thereby enabling low power consumption.

[0541] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0542] (Embodiment 9) In this embodiment, an input / output device of one embodiment of the present invention will be described with reference to FIG.

[0543] <9. Example of I / O device configuration> The input / output device of one embodiment of the present invention has a function of displaying an image and a function as a touch sensor. , and is an in-cell type touch panel having the above structure.

[0544] There is no limitation on the display element included in the input / output device of one embodiment of the present invention. Optical elements using ICRO Electro Mechanical System , organic EL (Electro Luminescence) elements and light-emitting diodes (LE D: Light Emitting Diode) and other light emitting elements, electrophoretic elements, etc. Various elements can be applied as display elements.

[0545] In this embodiment, a transmissive liquid crystal display device using a lateral electric field type liquid crystal element is taken as an example. explain.

[0546] There is no limitation on a detection element (also referred to as a sensor element) included in the input / output device of one embodiment of the present invention. Various sensors that can detect the proximity or contact of a sensing object such as a finger or stylus, It can be used as a sensing element.

[0547] For example, the sensor types include capacitance type, resistive film type, surface acoustic wave type, infrared type, etc. Various methods can be used, such as a pressure-sensitive method, an optical method, or a pressure-sensitive method.

[0548] In this embodiment, an input / output device having a capacitance type sensing element will be described as an example. .

[0549] The capacitance type includes the surface capacitance type and the projected capacitance type. The shadow type capacitance method includes the self-capacitance method and the mutual capacitance method. This is preferable because it enables simultaneous multi-point detection.

[0550] Representative in-cell touch panels are the hybrid in-cell type and the full in-cell type. The hybrid in-cell type has both a substrate that supports the display element and an opposing substrate. Alternatively, it refers to a configuration in which electrodes constituting a sensing element are provided only on the opposing substrate. The cancel-cell type has a structure in which electrodes constituting the sensing element are provided only on the substrate that supports the display element. The input / output device of one embodiment of the present invention is a full-in-cell touch panel. A cell-type touch panel is preferable because it allows the configuration of the opposing substrate to be simplified.

[0551] In the input / output device of one embodiment of the present invention, an electrode that constitutes a display element constitutes a sensor element. Since the electrode also functions as a conductive layer, the manufacturing process can be simplified and the manufacturing cost can be reduced, which is preferable.

[0552] In addition, by applying one embodiment of the present invention, a display panel and a detector element that are separately manufactured can be used. Compared to a structure in which the detector element is fabricated on the opposing substrate, the input / output device is thinner. It is possible to reduce the size and weight of the input / output device, or to reduce the number of parts in the input / output device. Cut.

[0553] In addition, the input / output device according to one embodiment of the present invention includes an FPC that supplies a signal for driving a pixel, and a detection The FPC that supplies the signals to drive the elements is placed on one of the boards. It is easy to incorporate into electronic devices and it is possible to reduce the number of parts. The FPC may provide signals to drive the pixels and signals to drive the detector elements.

[0554] The configuration of the input / output device of one embodiment of the present invention is described below.

[0555] [Example 1 of cross-sectional configuration of input / output device] FIG. 57(A) shows a cross-sectional view of two adjacent subpixels of an input / output device. The two sub-pixels shown belong to different pixels.

[0556] As shown in FIG. 57A, the input / output device includes a transistor 201, a transistor The transistor 203 and the liquid crystal element 207a are provided on the substrate 211. 12, insulating films such as an insulating film 213, an insulating film 215, and an insulating film 219 are provided.

[0557] For example, a red subpixel, a green subpixel, and a blue subpixel may be used. The configuration of one pixel makes it possible to display full color on the display unit. However, the colors of the sub-pixels are not limited to red, green, and blue. For example, the pixels may be white, yellow, magenta, or the like. Alternatively, sub-pixels exhibiting colors such as black, red, or cyan may be used.

[0558] The transistors 201 and 203 included in the subpixel may be the transistors exemplified in the above embodiment. A stamp can be applied.

[0559] The liquid crystal element 207a is in FFS (Fringe Field Switching) mode. The liquid crystal element 207a is a liquid crystal element to which a conductive film 251, a conductive film 252, and The liquid crystal 249 is formed by an electric field generated between the conductive film 251 and the conductive film 252. The conductive film 251 can function as a pixel electrode. The conductive film 252 can function as a common electrode.

[0560] By using a conductive material that transmits visible light for the conductive film 251 and the conductive film 252, The input device can function as a transmissive liquid crystal display device. A conductive material that reflects visible light is used for the conductive film 251, and a conductive material that transmits visible light is used for the conductive film 252. This allows the input / output device to function as a reflective liquid crystal display device.

[0561] Examples of conductive materials that transmit visible light include indium (In), zinc (Zn), It is advisable to use a material containing one selected from tin (Sn). Indium tin oxide (ITO), indium zinc Lead oxide, indium oxide with tungsten oxide, indium oxide with tungsten oxide Indium zinc oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide Indium tin oxide doped with silicon oxide, zinc oxide, zinc oxide doped with gallium A film containing graphene may also be used. The film can be formed, for example, by reducing a film containing graphene oxide formed in a film shape. .

[0562] It is preferable to use an oxide conductive film for the conductive film 251. The oxide conductive film is preferably a metal oxide semiconductor film. For example, the conductive film 251 may contain indium. is preferable, and In-M-Zn oxide (M is Al, Ga, Y, or Sn) is more preferable. Similarly, the conductive film 252 preferably contains indium, and is preferably In-M- Zn oxide is more preferred.

[0563] At least one of the conductive films 251 and 252 is formed using an oxide semiconductor. As described above, an oxide semiconductor having the same metal element may be used to construct an input / output device. By using this material in two or more layers of the layers, the manufacturing equipment (e.g., film formation equipment, processing equipment, etc.) can be It can be used in two or more processes, which reduces manufacturing costs. .

[0564] For example, the insulating film 253 is a silicon nitride film containing hydrogen, and the conductive film 251 is an oxide semiconductor. When the insulating film 253 is used, the conductivity of the oxide semiconductor is increased by hydrogen supplied from the insulating film 253. It is possible.

[0565] Examples of conductive materials that reflect visible light include aluminum, silver, and metals thereof. Examples of suitable materials include alloys containing such materials.

[0566] The conductive film 251 functioning as a pixel electrode is connected to the source or drain of the transistor 203. are electrically connected.

[0567] The conductive film 252 has a comb-like top surface shape (also referred to as a planar shape) or a slit-like An insulating film 253 is provided between the conductive film 251 and the conductive film 252. The conductive film 251 overlaps with the conductive film 252 with the insulating film 253 interposed therebetween. In the region where the conductive film 251 and the colored film 241 overlap, the conductive film 252 is formed on the conductive film 251. It has a portion that is not placed.

[0568] A conductive film 255 is provided over the insulating film 253. and can function as an auxiliary wiring for the conductive film 252. By providing auxiliary wiring that electrically connects to the electrode, the voltage drop caused by the resistance of the common electrode is reduced. In addition, the conductive film containing the metal oxide and the conductive film containing the metal can be suppressed. In the case of forming a laminated structure, it is formed by a patterning technique using a halftone mask. This is preferable because it simplifies the process.

[0569] The conductive film 255 may be a film having a lower resistance than the conductive film 252. For example, molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, silver A single layer is formed using metal materials such as neodymium, scandium, etc., or alloy materials containing these elements. The film may be formed by laminating or stacking.

[0570] The conductive film 255 overlaps with the light-shielding film 243 etc. so as not to be visible to the user of the input / output device. It is preferable that the sensor is provided at a position.

[0571] The colored film 241 has a portion overlapping with the liquid crystal element 207a. The stalk 201 and the stalk 203 overlap at least partially.

[0572] The insulating film 245 prevents impurities contained in the colored film 241, the light-shielding film 243, etc. from diffusing into the liquid crystal 249. It is preferable that the insulating film 245 has a function as an overcoat to prevent the above-mentioned problems. If not required, it need not be provided.

[0573] In addition, an alignment film is provided on either or both of the upper and lower surfaces of the liquid crystal 249. The alignment film can control the alignment of the liquid crystal 249. For example, ), an alignment film may be formed to cover the conductive film 252. An alignment film may be provided between the insulating film 245 and the liquid crystal 249. The layer may have both a function as an alignment film and a function as an overcoat.

[0574] The input / output device also includes a spacer 247. The spacer 247 is disposed between the substrate 211 and the substrate It has the function of preventing the distance between it and 261 from becoming closer than a certain amount.

[0575] In FIG. 57(A), the spacer 247 is provided on the insulating film 253 and the conductive film 252. However, the embodiment of the present invention is not limited to this example. For example, the insulating film 2 may be provided on the insulating film 2 side, or on the substrate 261 side. A spacer 247 may be formed on the substrate 45. Also, in FIG. 57(A), the spacer 247 253 and the insulating film 245. It is not necessary for the structure to be in contact with either of them.

[0576] Granular spacers may be used as the spacers 247. Materials such as rubber or plastic can be used, but materials with elasticity such as resin and rubber should be used. At this time, the granular spacers may be crushed in the vertical direction.

[0577] The substrate 211 and the substrate 261 are bonded together by an adhesive layer (not shown). A liquid crystal 249 is sealed in the area surrounded by the substrate 261 and the adhesive layer.

[0578] In addition, when the input / output device is made to function as a transmission type liquid crystal display device, the polarizing plate is The light from the backlight placed on the outside of the polarizing plate is polarized. At this time, the voltage applied between the conductive film 251 and the conductive film 252 The alignment of the liquid crystal 249 can be controlled by the polarizer, and the optical modulation of light can be controlled. The intensity of the light emitted through the colored film 241 can be controlled. Since light outside a specific wavelength range is absorbed, the emitted light is, for example, red, blue, or The light has a green color.

[0579] In addition to the polarizing plate, for example, a circular polarizing plate can be used. For example, a laminate of a linear polarizing plate and a quarter-wave retardation plate can be used. This makes it possible to reduce the viewing angle dependency of the display of the input / output device.

[0580] In this example, an element to which the FFS mode is applied is used as the liquid crystal element 207a. Liquid crystal elements using various modes can be used. For example, VA( Vertical Alignment mode, TN (Twisted Neutral c) mode, IPS (In-Plane-Switching) mode, ASM (Axi ally Symmetric aligned Micro-cell) mode, OC B (Optically Compensated Birefringence) mode mode, FLC (Ferroelectric Liquid Crystal) mode, A FLC (AntiFerroelectric Liquid Crystal) mode A liquid crystal element to which the above is applied can be used.

[0581] In addition, the input / output device may be a normally black type liquid crystal display device, such as a vertical alignment (VA) model. A transmissive liquid crystal display device using a vertical alignment mode may be used. A (Multi-Domain Vertical Alignment) mode, PV A (Patterned Vertical Alignment) mode, ASV mode etc. can be used.

[0582] The liquid crystal element is an element that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. The optical modulation of liquid crystals is caused by the electric field applied to the liquid crystal (horizontal electric field, vertical electric field The liquid crystal used in the liquid crystal element is , Thermotropic Liquid Crystal, Low Molecular Weight Liquid Crystal, Polymer Liquid Crystal, Polymer Dispersed Liquid Crystal (PDLC:Po lymer Dispersed Liquid Crystal), Ferroelectric Liquid Crystal, Antiferroelectric Liquid Crystal Ferroelectric liquid crystals can be used. These liquid crystal materials can be cholesteric or These phases include nematic phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, etc.

[0583] As the liquid crystal material, either positive type liquid crystal or negative type liquid crystal may be used as appropriate. The optimum liquid crystal material may be selected according to the mode and design to be used.

[0584] In addition, when the in-plane switching method is adopted, liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing 5% by weight or more of chiral agent was used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used as the liquid crystal 249. The response speed is short and the liquid crystal is optically isotropic. The crystal composition does not require alignment treatment and has little viewing angle dependency. Since the rubbing process is unnecessary, electrostatic damage caused by the rubbing process is eliminated. This can prevent defects and damage to the liquid crystal display device during the manufacturing process. .

[0585] Here, above the substrate 261, there is a substrate that is directly touched by a detection object such as a finger or a stylus. In this case, a polarizing plate or a circular polarizing plate may be provided between the substrate 261 and the substrate. In that case, it is preferable to provide a protective layer (ceramic coat, etc.) on the substrate. The protective layer is preferably made of, for example, silicon oxide, aluminum oxide, yttrium oxide, Inorganic insulating materials such as yttria-stabilized zirconia (YSZ) can be used. The substrate may be made of tempered glass. The tempered glass may be tempered by an ion exchange method, an air-cooling tempering method, or the like. The material is subjected to physical or chemical treatment and has its surface subjected to compressive stress. can be done.

[0586] In FIG. 57A, the conductive film 252 of the left subpixel and the conductive film 253 of the right subpixel are By utilizing the capacitance formed between the sensor 52 and the sensor, the proximity or contact of the object to be detected can be detected. That is, in the input / output device of one embodiment of the present invention, the conductive film 252 is a common film for the liquid crystal element. The electrode serves as both an electrode of the detection element and an electrode of the detection element.

[0587] In this manner, in the input / output device of one embodiment of the present invention, the electrode constituting the liquid crystal element is a detection element. Since the electrode also serves as a component of the electrode, the manufacturing process can be simplified and the manufacturing cost can be reduced. In addition, the input / output device can be made thinner and lighter.

[0588] The conductive film 252 is electrically connected to a conductive film 255 that functions as an auxiliary wiring. By providing the conductive film 255, the resistance of the electrodes of the sensing element can be reduced. By reducing the resistance of the electrodes, the time constant of the electrodes of the detection element can be reduced. The smaller the time constant of the electrodes of the sensing element, the higher the detection sensitivity and the higher the detection accuracy. The degree can be increased.

[0589] In addition, if the capacitance between the electrode of the detection element and the signal line is too large, the time constant of the electrode of the detection element Therefore, a flattening mechanism is installed between the transistor and the electrode of the detector element. It is preferable to provide an insulating film having a function to reduce the capacitance between the electrode of the detection element and the signal line. For example, in FIG. 57(A), an insulating film 219 is provided as an insulating film having a planarizing function. By providing the insulating film 219, the capacitance between the conductive film 252 and the signal line can be reduced. This makes it possible to reduce the time constant of the electrodes of the detection element. The smaller the time constant of the element electrodes, the higher the detection sensitivity and the higher the detection accuracy. can be increased.

[0590] For example, the time constant of the electrodes of the sensing element is greater than 0 seconds and is 1×10 -4 seconds or less, preferably 0 seconds or more 5×10 -5 seconds or less, more preferably greater than 0 seconds and 5×10 -6 seconds or less , more preferably greater than 0 seconds and 5×10 -7 seconds or less, more preferably greater than 0 seconds and ×10 -7 It is preferable that the time constant is less than 1×10 -6 By setting the delay time to less than 2 seconds, noise It is possible to achieve high detection sensitivity while suppressing the influence of noise.

[0591] [Example of cross-sectional configuration of input / output device 2] FIG. 57(B) shows a cross-sectional view of two adjacent pixels, which is different from FIG. 57(A). The two sub-pixels shown in FIG. 7(B) belong to different pixels.

[0592] The second configuration example shown in FIG. 57B includes a conductive film 251, a conductive film 252, an insulating film 253, and a conductive The stacking order of the conductive film 255 is different from that of the configuration example 1 shown in FIG. For parts similar to those in configuration example 1, please refer to the above.

[0593] Specifically, in the configuration example 2, a conductive film 255 is provided on the insulating film 219. A conductive film 252 is provided, an insulating film 253 is provided on the conductive film 252, and a conductive film 25 1.

[0594] As shown in FIG. 57B, a liquid crystal element 207b is provided in the upper layer, and a comb-shaped or slit-shaped A conductive film 251 having a shaped upper surface is used as a pixel electrode, and a conductive film 252 provided in a lower layer is used as a pixel electrode. In that case, the conductive film 251 is also used as a conductive electrode of the transistor 203. It is sufficient that the source or drain is electrically connected.

[0595] In FIG. 57B, the conductive film 252 of the left subpixel and the conductive film 253 of the right subpixel are By utilizing the capacitance formed between the sensor 52 and the sensor, the proximity or contact of the object to be detected can be detected. That is, in the input / output device of one embodiment of the present invention, the conductive film 252 is a common film for the liquid crystal element. The electrode serves as both an electrode of the detection element and an electrode of the detection element.

[0596] In the configuration example 1 (FIG. 57(A)), the conductive film 25 serving as both the electrode of the detection element and the common electrode is 2 is located on the display surface side (closer to the object to be detected) than the conductive film 251 that functions as a pixel electrode. As a result, the conductive film 251 is positioned closer to the display surface than the conductive film 252 in the configuration example 2. However, in configuration example 1, the detection sensitivity may be improved.

[0597] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0598] (Embodiment 10) In this embodiment, a display module and an electronic device each including a semiconductor device according to one embodiment of the present invention will be described. This will be explained with reference to Figures 58 to 60.

[0599] <10-1. Display module> The display module 8000 shown in FIG. 58 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003, A display panel 8006, a backlight 8007, a frame 8009, and a printed circuit board 801 0, has battery 8011.

[0600] The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0601] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel The shape and dimensions can be changed as appropriate to match the size of 8006.

[0602] The touch panel 8004 is a resistive or capacitive touch panel. The display panel 8006 can be used by overlapping it with the opposing substrate (sealing substrate). It is also possible to provide the display panel 8 with a touch panel function. It is also possible to provide an optical sensor in each pixel of the display panel 006 to make it into an optical touch panel.

[0603] The backlight 8007 has a light source 8008. In FIG. In the above embodiment, the light source 8008 is disposed on the light source 8007, but the present invention is not limited to this. For example, a light source 8008 is arranged at the end of a backlight 8007, and a light diffusion plate is further used. In addition, when a self-luminous light-emitting element such as an organic EL element is used, or when a reflective In the case of a flat panel or the like, the backlight 8007 need not be provided.

[0604] The frame 8009 protects the display panel 8006 and also supports the movement of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the frame. The frame 8009 may also function as a heat sink.

[0605] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. , this can be omitted when using a commercial power source.

[0606] In addition, the display module 8000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0607] <10-2.Electronic equipment> 59(A) to 59(G) are diagrams showing electronic devices. These electronic devices are A body 9000, a display unit 9001, a speaker 9003, and operation keys 9005 (power switch, etc.) includes an operation switch), a connection terminal 9006, a sensor 9007 (force, displacement, position, speed, Acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electricity Measures field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays The device may have a built-in microphone 9008, etc.

[0608] The electronic devices shown in Figures 59(A) to 59(G) can have various functions. For example, the function to display various information (still images, videos, text images, etc.) on the display, Panel function, calendar, date or time display function, various software ( A function to control processing by a program, wireless communication function, and various functions using wireless communication function Functions for connecting to computer networks, transmitting various data using wireless communication functions, or receiving the program or data recorded on the recording medium, and displaying the program or data. The function of displaying the information on the display unit can be provided. The functions that the electronic device shown in the figure can have are not limited to these, and may have a variety of functions. Although not shown in Fig. 59(A) to Fig. 59(G), the electronic device may include The electronic device may have a plurality of display units. The function to take pictures, record videos, and store the images on a recording medium (external or built-in to the camera) ) and a function for displaying the captured image on a display unit.

[0609] The electronic devices shown in FIGS. 59(A) to 59(G) will be described in detail below.

[0610] FIG. 59(A) is a perspective view showing a television device 9100. 100 is a display unit 9001 having a large screen, for example, 50 inches or more, or 100 inches or more It is possible to incorporate a display unit 9001 such as the above.

[0611] FIG. 59(B) is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 is For example, the device has one or more functions selected from a telephone, a notebook, an information viewing device, etc. Specifically, the mobile information terminal 9101 can be used as a smartphone. A speaker, a connection terminal, a sensor, and the like may be provided. Image information can be displayed on multiple sides of the screen. For example, three operation buttons 9050 ( Operation icons or simply icons) can be displayed on one side of the display unit 9001. Also, information 9051 shown in a dashed rectangle can be displayed on the other side of the display unit 9001. Examples of information 9051 include e-mail and social networking sites (SNS). Display to notify of incoming calls, e-mails, SNS, etc. Subject, sender name of email or SNS, date and time, time, remaining battery level, antenna reception Or, instead of information 9051, Alternatively, operation buttons 9050 and the like may be displayed.

[0612] FIG. 59C is a perspective view showing a portable information terminal 9102. , and has a function of displaying information on three or more faces of the display unit 9001. An example is shown in which information 9053 and information 9054 are displayed on different sides. The user of the portable information terminal 9102 holds the portable information terminal 9102 in the breast pocket of the clothes. In this state, the display (information 9053 in this case) can be confirmed. The telephone number or name of the caller is displayed on the mobile information terminal 9102 so that it can be observed from above. The user can read the display without taking the mobile information terminal 9102 out of his pocket. You can check the number and decide whether to answer the call or not.

[0613] Fig. 59(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The 9200 is used for mobile phone calls, e-mail, document browsing and writing, music playback, and Internet communications. It is possible to execute various applications such as computer games. The display unit 9001 has a curved display surface, and displays information along the curved display surface. In addition, the portable information terminal 9200 can perform short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, The mobile information terminal 9200 also has a connection terminal 9006. It has a connector and can directly exchange data with other information terminals. Charging can also be performed via the connection terminal 9006. Power may also be supplied wirelessly without going through 6.

[0614] 59(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 59(E) is a perspective view of the portable information terminal 9201 in an unfolded state. (F) shows the mobile information terminal 9201 being changed from the unfolded state to the folded state. FIG. 59(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 is highly portable when folded and is unfolded. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 9001 is made up of three housings 9000 connected by hinges 9055. The two housings 9000 are supported by the hinge 9055. The portable information terminal 9201 can be reversibly transformed from an unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0615] 60(A) and 60(B) are perspective views of a display device having a plurality of display panels. FIG. 60(A) is a perspective view of a state in which a plurality of display panels are rolled up, and FIG. ) is a perspective view of a state in which a plurality of display panels are unfolded.

[0616] The display device 9500 shown in FIG. 60(A) and (B) includes a plurality of display panels 9501 and a shaft portion 9 511 and a bearing portion 9512. The display panels 9501 have a display area 9502 and a light-transmitting region 9503.

[0617] In addition, the display panels 9501 are flexible. The filters 9501 are arranged so that they partially overlap each other. For example, A light-transmitting region 9503 of the display panel 9501 can be overlapped. By using the display panel 9501, a large-screen display device can be provided. The display panel 9501 can be rolled up depending on the situation, making it a versatile display. The display device may be a display device.

[0618] In addition, in FIG. 60(A) and (B), the display area 9502 is adjacent to the display panel 950 1 shows a state in which the display panels are spaced apart from each other, but this is not limited thereto. For example, the display panels 9 By overlapping the display areas 9502 of 501 without any gaps, a continuous display area 9502 is created. You may do so.

[0619] The electronic device described in this embodiment has a display unit for displaying some information. However, the semiconductor device of one embodiment of the present invention is an electronic device that does not have a display portion. This can also be applied to vessels.

[0620] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done. [Explanation of symbols]

[0621] 100 transistors 100A Transistor 100B Transistor 100C transistor 100D Transistor 100E Transistor 100F transistor 100G Transistor 100H Transistor 100J Transistor 100K transistors 102 Substrate 104 Insulating film 106 Conductive Film 107 Oxide Semiconductor Film 108 Oxide semiconductor film 108_1 Oxide semiconductor film 108_2 Oxide semiconductor film 108_3 Oxide semiconductor film 108d Drain region 108f area 108i Channel Area 108s Source Area 110 Insulating film 110_0 Insulating film 112 Metal oxide film 112_0 Metal oxide film 112a Conductive film 112b Conductive film 114 Conductive Film 114_0 Conductive film 116 Insulating film 118 Insulating film 120 Conductive film 120a Conductive film 120b Conductive film 122 Insulating film 140 Mask 141a opening 141b opening 143 Opening 145 Impurity elements 201 Transistor 203 Transistor 207a Liquid crystal element 207b Liquid crystal element 211 Substrate 212 Insulating film 213 Insulating film 215 Insulating film 219 Insulating Film 223 Oxide Semiconductor Film 241 Colored film 243 Light-shielding film 245 Insulating Film 247 Spacer 249 Liquid Crystal 251 Conductive Film 252 Conductive Film 253 Insulating Film 255 Conductive Film 261 Substrate 300A Transistor 300B Transistor 300C transistor 300D Transistor 300E Transistor 300F transistor 302 Substrate 304 Conductive film 306 Insulating film 307 Insulating Film 308 Oxide Semiconductor Film 308_1 Oxide semiconductor film 308_2 Oxide semiconductor film 308_3 Oxide semiconductor film 312a Conductive film 312b Conductive film 314 Insulating film 316 Insulating Film 318 Insulating Film 320a Conductive film 320b Conductive film 341a opening 341b opening 342a opening 342b opening 342c opening 501 Pixel circuit 502 Pixel section 504 Drive circuit section 504a Gate Driver 504b source driver 506 Protection circuit 507 Terminal section 550 Transistor 552 Transistor 554 Transistor 560 Capacitive element 562 Capacitive element 570 Liquid crystal element 572 Light emitting element 700 Display device 701 Substrate 702 Pixel section 704 Source driver circuit section 705 Substrate 706 Gate driver circuit section 708 FPC terminal section 710 Signal Line 711 Wiring section 712 Sealing material 716 FPC 730 Insulating film 732 Sealing film 734 Insulating film 736 Colored film 738 Light-shielding film 750 Transistors 752 Transistor 760 Connection electrode 770 Planarizing Insulating Film 772 Conductive Film 774 Conductive Film 775 Liquid crystal elements 776 Liquid crystal layer 778 Structure 780 Anisotropic Conductive Film 782 Light emitting element 784 Conductive Film 786 EL layer 788 Conductive Film 790 Capacitive element 800 Inverter 810 OS Transistor 820 OS Transistor 831 Signal Waveform 832 Signal Waveform 840 dashed line 841 Solid Line 850 OS Transistor 860 CMOS Inverter 1280a p-type transistor 1280b n-type transistor 1280c n-type transistor 1281 Capacitive element 1282 Transistor 1311 Wiring 1312 Wiring 1313 Wiring 1314 Wiring 1315 Wiring 1316 Wiring 1317 Wiring 1351 Transistor 1352 Transistor 1353 Transistor 1354 Transistor 1360 Photoelectric conversion element 1401 Signal 1402 Signal 1403 Signal 1404 Signal 1405 Signal 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery 9000 Chassis 9001 Display section 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Television equipment 9101 Portable information terminal 9102 Portable information terminal 9200 Mobile Information Terminal 9201 Portable information terminals 9500 display device 9501 Display Panel 9502 Display area 9503 area 9511 Shaft 9512 Bearing section

Claims

[Claim 1] A semiconductor device having a transistor, an oxide semiconductor film over a first insulating film; a second insulating film on the oxide semiconductor film; a metal oxide film on the second insulating film; a gate electrode on the metal oxide film; a third insulating film on the oxide semiconductor film and the gate electrode, The oxide semiconductor film is a channel region overlapping the gate electrode; a source region in contact with the third insulating film; a drain region in contact with the third insulating film, The semiconductor device, wherein the source region and the drain region comprise one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, or a rare gas.

Images