Overcurrent protection circuit, semiconductor device, electronic device, and vehicle

Abstract

To provide an overcurrent protection circuit capable of detecting an overcurrent with high accuracy, and capable of fixing a detection value of the overcurrent even when a through rate of an output transistor passing a current to be monitored is variable.SOLUTION: An overcurrent protection circuit (OCP1) includes: first and second transistors (M1, M2) forming an amplifier input stage that accepts an input of a detection signal in accordance with a current to be monitored; a third transistor (M3) forming an amplifier output stage that generates a current output signal in accordance with a difference between the detection signal and a reference signal, and negative feedback inputting the current output signal to the amplifier input stage; current mirror circuits (M6, M7) generating a current limiting signal by duplicating the signal based on the current output signal; and a first current source (CS1) connected to an output terminal configured to output the current limiting signal of the current mirror circuit. The first current source is configured to switch the current output from the first current source between a fixed value and a variable value.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The invention disclosed in this specification relates to an overcurrent protection circuit, a semiconductor device, an electronic device, and a vehicle. [Background technology]

[0002] The applicant of the present application has proposed many new technologies relating to semiconductor devices such as vehicle-mounted IPDs (intelligent power devices) (see, for example, Patent Document 1).

[0003] Moreover, as a related technique for an overcurrent protection circuit incorporated in a semiconductor device, for example, Patent Document 2 can be mentioned. The overcurrent protection circuit proposed in Patent Document 2 can detect an overcurrent with high accuracy. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2017 / 187785 [Patent Document 2] JP 2023-50714 A

[0005] [overview] However, in the overcurrent protection circuit proposed in Patent Document 2, if the slew rate of the output transistor through which the monitored current flows is variable, the detected value of the overcurrent also becomes variable and is no longer a constant value.

[0006] The overcurrent protection circuit disclosed in this specification is configured to limit a monitored current based on a current limit signal, and includes a first transistor and a second transistor configured to form an amplifier input stage that receives an input of a detection signal corresponding to the monitored current, a third transistor configured to form an amplifier output stage that generates a current output signal corresponding to a difference between the detection signal and a reference signal and negatively feeds the current output signal back to the amplifier input stage, a current mirror circuit configured to generate the current limit signal by replicating a signal based on the current output signal, and a first current source connected to an output end of the current mirror circuit that is configured to output the current limit signal, the first current source configured to switch a current output from the first current source between a fixed value and a variable value.

[0007] The semiconductor device disclosed in this specification includes an output transistor, and the overcurrent protection circuit having the above-described configuration, configured so that an output current flowing through the output transistor is the current to be monitored.

[0008] The electronic device disclosed in this specification includes the semiconductor device having the above-described configuration.

[0009] The vehicle disclosed in this specification is equipped with an electronic device having the above-described configuration. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing the configuration of an electronic device according to the first embodiment. [Diagram 2] FIG. 2 is a waveform diagram of the output current and the like of the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a waveform diagram of an output current of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing the configuration of an electronic device according to the second embodiment. [Diagram 5] FIG. 5 is a waveform diagram for explaining the operation of the second current mirror circuit. [Figure 6] FIG. 6 is a waveform diagram of the output current of the semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is a waveform diagram of an output current of the semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is an external view of the vehicle.

[0011] [Detailed Description] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a transistor whose gate structure is composed of at least three layers: "a layer made of a conductor or a semiconductor such as polysilicon having a low resistance value," "an insulating layer," and "a P-type, N-type, or intrinsic semiconductor layer." In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0012] First Embodiment Fig. 1 is a diagram showing the configuration of an electronic device according to embodiment 1. An electronic device 10A shown in Fig. 1 includes a semiconductor device 1A, a load LD1, and DC power supplies VS1 and VS2.

[0013] The semiconductor device 1A is a low-side switch IC (a type of IPD) that establishes / cuts conduction between a load LD1 and a ground potential.

[0014] The semiconductor device 1A includes terminals T1 to T5 as means for establishing electrical connection with the outside of the device.

[0015] The terminal T1 is connected to a first end of a load LD1. The second end of the load LD1 is connected to a positive terminal of a DC power supply VS1. The terminal T2 is connected to a ground potential. The terminal T3 receives an input signal IN.

[0016] The terminal T4 receives an enable signal EN. When the enable signal EN is at a high level, a control circuit 2 (described later) is turned on (operating). When the enable signal EN is at a low level, the control circuit 2 (described later) is turned off (not operating). When the enable signal EN switches from a low level to a high level, the control circuit 2 (described later) is reset to its initial state and starts operating.

[0017] The terminal T5 is connected to the positive electrode of the DC power supply VS2. The negative electrodes of the DC power supplies VS1 and VS2 are connected to the ground potential. The DC power supply VS1 outputs a voltage VCC. The DC power supply VS2 outputs a voltage VDD. The voltages VCC and VDD may be the same voltage or different voltages.

[0018] The semiconductor device 1A includes an overcurrent protection circuit OCP1, a control circuit 2, and a MOS field effect transistor M15 which is an output transistor.

[0019] The control circuit 2 is connected to the terminals T3 and T4. The control circuit 2 turns the MOS field effect transistor M15 off when the input signal IN is at a LOW level, and turns the MOS field effect transistor M15 on when the input signal IN is at a HIGH level.

[0020] The control circuit 2 has an overheat protection function, and when the temperature in the vicinity of the MOS field effect transistor M15 exceeds a predetermined value, it turns off the MOS field effect transistor M15 regardless of the level of the input signal IN.

[0021] The MOS field effect transistor M15 is an N-channel MOS field effect transistor. The drain of the MOS field effect transistor M15 is connected to the terminal T1. The source and back gate of the MOS field effect transistor M15 are connected to the terminal T2. The MOS field effect transistor M15 is connected in series to the load LD1 via the terminal T1.

[0022] The overcurrent protection circuit OCP1 monitors the output current Ip (the source current of the MOS field effect transistor M15) and protects the MOS field effect transistor M15.

[0023] The overcurrent protection circuit OCP1 includes MOS field effect transistors M1 to M7, M11 to M14, and resistors R1 to R3.

[0024] The MOS field effect transistors M11 and M12 are P-channel MOS field effect transistors. The sources and back gates of the MOS field effect transistors M11 and M12 are connected to the terminal T5.

[0025] The control circuit 2 supplies a bias voltage Bias1 to each gate of the MOS field effect transistors M11 and M12. When the input signal IN is at a high level and overheat protection is not performed, the control circuit 2 sets the bias voltage Bias1 to a low level. At this time, the MOS field effect transistors M11 and M12 each operate as a current source that outputs a reference current.

[0026] On the other hand, when at least one of the first condition that the input signal IN is at a low level and the second condition that overheat protection is being performed is satisfied, the control circuit 2 sets the bias voltage Bias1 to a high level. At this time, the drain currents of the MOS field effect transistors M11 and M12 become zero.

[0027] The MOS field effect transistors M1 to M3 are N-channel MOS field effect transistors.

[0028] The drain of the MOS field effect transistor M11 is connected to the drain and gate of the MOS field effect transistor M2 and to the gate of the MOS field effect transistor M1.

[0029] The drain of the MOS field effect transistor M12 is connected to the drain of the MOS field effect transistor M1 and to the gate of the MOS field effect transistor M3.

[0030] The source and back gate of the MOS field effect transistor M1 are connected to a first terminal of the resistor R1 and to a source and back gate of the MOS field effect transistor M14, which is an N-channel MOS field effect transistor. The second terminal of the resistor R1 is connected to the ground potential via the terminal T2.

[0031] The source and back gate of the MOS field effect transistor M2 are connected to a first end of the resistor R2 and to the source and back gate of the MOS field effect transistor M3. The second end of the resistor R2 is connected to the ground potential via the terminal T2.

[0032] The drain current of the MOS field effect transistor M3 is replicated by a first current mirror circuit composed of P-channel MOS field effect transistors M4 and M5, and a second current mirror circuit composed of N-channel MOS field effect transistors M6 and M7. Therefore, the drain current of the P-channel MOS field effect transistor M7 is a current obtained by replicating the drain current of the MOS field effect transistor M3. The drain current of the MOS field effect transistor M7 serves as a current limiting signal for limiting the output current Ip.

[0033] The sources and back gates of the MOS field effect transistors M4, M5, and M13 are connected to the terminal T5. The drain and gate of the MOS field effect transistor M4 and the gate of the MOS field effect transistor M5 are connected to the drain of the MOS field effect transistor M3. The drain current of the MOS field effect transistor M13 is a charge current Icrg that charges the gates of the MOS field effect transistors M14 and M15.

[0034] The drain of the MOS field effect transistor M5 is connected to the drain of the MOS field effect transistor M6 and to the gates of the MOS field effect transistors M6 and M7. The sources and back gates of the MOS field effect transistors M6 and M7 are connected to the ground potential via the terminal T2.

[0035] The drain of the MOS field effect transistor M7 is connected to the drain of the MOS field effect transistor M13 and to a first end of the resistor R3.

[0036] The second end of the resistor R3 is connected to the gates of MOS field effect transistors M14 and M15.

[0037] The MOS field effect transistor M14 outputs a sense current Is corresponding to the output current Ip. The resistor R1 converts the sense current Is into a detection signal (detection voltage) S1 corresponding to the output current Ip.

[0038] The MOS field effect transistors M1 and M2 form an amplifier input stage that receives an input of a detection signal (detection voltage) S1 corresponding to the output current Ip. The MOS field effect transistor M1 receives an input of a detection signal (detection voltage) S1 corresponding to the output current Ip. The MOS field effect transistor M2 receives an input of a reference signal (reference voltage) S2.

[0039] The MOS field effect transistor M3 forms an amplifier output stage that generates a current output signal (the source current and the drain current of the MOS field effect transistor M3) S3 according to the difference between the detection signal (detection voltage) S1 and the reference signal (reference voltage) S2, and inputs the current output signal (the source current of the MOS field effect transistor M3) S3 as a negative feedback to the above-mentioned amplifier input stage. This makes it possible to apply a highly accurate output current limit.

[0040] The overcurrent protection circuit OCP1 operates when the output current Ip reaches the limit value I OCP_LIM When the limit value Ip is reached, the output current Ip is limited. OCP_LIM is expressed by the following formula, where the resistance value RM14 is the resistance value between the source and drain of the MOS field effect transistor M14. M15 is the resistance value of the source-drain resistor of the MOS field effect transistor M15. Resistance value R2 is the resistance value of resistor R2. Resistance value R1 is the resistance value of resistor R1. Current value I REF is the value of the drain current of the MOS field effect transistor M11. The gain K is the product of the mirror ratio of the first current mirror circuit and the mirror ratio of the second current mirror circuit. The current value I CHG is the value of the charging current Icrg. I OCP_LIM ={(R M14 +R1) / R M15}×(R2 / R1)×{I REF +(1 / K)×I CHG}

[0041] The overcurrent protection circuit OCP1 further includes MOS field effect transistors M21-M23, inverters IV1 and IV2, analog switches A1 and A2, a variable current source CS11, and a constant current source CS12. The first current source CS1 includes a MOS field effect transistor M23, which is a P-channel MOS field effect transistor, a MOS field effect transistor M13, the analog switches A1 and A2, the variable current source CS11, and the constant current source CS12.

[0042] The first current source CS1, more specifically, the drain of the MOS field effect transistor M13 is connected to an output terminal (the drain of the MOS field effect transistor M7) configured to output a current limiting signal of the second current mirror circuit.

[0043] The source and back gate of the MOS field effect transistor M21, which is a P-channel MOS field effect transistor, are connected to the sources and back gates of the MOS field effect transistors M11 and M12 and to the terminal T5. The gate of the MOS field effect transistor M21 is connected to the gates of the MOS field effect transistors M11 and M12. When the bias voltage Bias1 is at a low level, the MOS field effect transistor M21 operates as a current source that outputs a reference current, similar to the MOS field effect transistors M11 and M12.

[0044] The drain of the MOS field effect transistor M21 is connected to the drain of the MOS field effect transistor M22, which is an N-channel MOS field effect transistor, and the input terminal of the inverter IV1. The gate of the MOS field effect transistor M22 is connected to the gate of the MOS field effect transistor M3 and the drains of the MOS field effect transistors M12 and M1. The source and back gate of the MOS field effect transistor M22 are connected to the ground potential via the terminal T2.

[0045] The output terminal of the inverter IV1 is connected to the input terminal of the inverter IV2 and the control terminal of the analog switch A2. The output terminal of the inverter IV2 is connected to the control terminal of the analog switch A1.

[0046] The source and back gate of the MOS field effect transistor M23, which is a P-channel MOS field effect transistor, are connected to the source and back gate of the MOS field effect transistor M13 and to the terminal T5. The gate and drain of the MOS field effect transistor M23 and the gate of the MOS field effect transistor M13 are connected to first ends of the analog switches A1 and A2. The analog switch A1 is connected to a terminal T2 (not shown in the drawing) via a variable current source CS11, and is connected to a ground potential via the terminal T2. The analog switch A2 is connected to a terminal T2 (not shown in the drawing) via a constant current source CS12, and is connected to a ground potential via the terminal T2. The value of the variable current output from the variable current source CS11 is adjusted by, for example, providing a variable current value adjustment terminal in the semiconductor device 1A and adjusting the resistance value of a variable current value adjustment resistor externally connected to the variable current value adjustment terminal.

[0047] The first current source CS1 is configured to switch the current (charge current Icrg) output from the first current source CS1 between a fixed value and a variable value. More specifically, the first current source CS1 is configured to switch the current (charge current Icrg) output from the first current source CS1 between a fixed value and a variable value in response to a current limit signal (source current and drain current of the MOS field effect transistor M3) S3 by switching the current (charge current Icrg) output from the first current source CS1 between a fixed value and a variable value in response to an on state and an off state of a transistor M22, the gate of which is commonly connected to the transistor M3.

[0048] The threshold voltage Vth1 of the transistor M22 is sufficiently smaller than the threshold voltage Vth2 of the transistor M3. Therefore, the transistor M22 turns on before the transistor M3 turns on, and as shown in FIG. 2, the current (charge current Icrg) output from the first current source CS1 switches from a variable value to a fixed value before the output current Ip is limited. This allows the overcurrent protection circuit OCP1 to fix the detection value of the overcurrent even if the slew rate of the MOS field effect transistor M15, which is the output transistor, is variable. Note that in FIG. 2, the variable value of the charge current Icrg is adjusted to a certain value, and the variable value of the charge current Icrg can take various values ​​as shown in FIG. 3.

[0049] <Second embodiment> Fig. 4 is a diagram showing the configuration of an electronic device according to embodiment 2. An electronic device 10B shown in Fig. 4 includes a semiconductor device 1B, a load LD1, and DC power supplies VS1 and VS2.

[0050] The semiconductor device 1B has a configuration in which the overcurrent protection circuit OCP1 in the semiconductor device 1A is replaced with an overcurrent protection circuit OCP2.

[0051] The overcurrent protection circuit OCP2 differs from the overcurrent protection circuit OCP1 in the configuration of the second current mirror circuit.

[0052] In the overcurrent protection circuit OCP2, the second current mirror circuit includes, in addition to MOS field effect transistors M6 and M7, MOS field effect transistors M31 to M33 which are N-channel MOS field effect transistors, and a current source CS2.

[0053] The source and back gate of the MOS field effect transistor M31 are connected to the terminal T5. The gate of the MOS field effect transistor M21 is connected to the drain of the MOS field effect transistor M5 and the drain of the MOS field effect transistor M6. The source and back gate of the MOS field effect transistor M31 are connected to the gates of the MOS field effect transistors M6 and M7 and the drain of the MOS field effect transistor M32. A voltage VDD is applied to a first end of the current source CS2. A second end of the current source CS2 is connected to the gate of the MOS field effect transistor M32 and the gate and drain of the MOS field effect transistor M33. The sources and back gates of the MOS field effect transistors M32 and M33 are connected to the ground potential via the terminal T2.

[0054] To achieve a high-speed response of the overcurrent protection circuit, it is necessary to shorten the startup time of the high-current gain current mirror circuit provided in the overcurrent protection circuit. Note that when the gain of the current mirror circuit is reduced, the reference current needs to be increased, which increases the current consumption of the overcurrent protection circuit and narrows the operating range of the amplifier provided in the front stage of the current mirror circuit.

[0055] Therefore, the overcurrent protection circuit OCP2 realizes a high-speed response by setting the total gain of the first current mirror circuit and the second current mirror circuit to a high current gain, setting the first current mirror circuit to a lower gain than the second current mirror circuit (for example, a current amplification factor of 1, i.e. a mirror ratio of 1:1), and configuring the second current mirror circuit to be capable of a high-speed response.

[0056] The second current mirror circuit can supply a charging current to the gates of the MOS field effect transistors M6 and M7 by the MOS field effect transistor M31, which is a source follower circuit, and therefore can reduce the start-up time.

[0057] In the second current mirror circuit, the value of the discharge current that discharges each gate of the MOS field effect transistors M6 and M7 is controlled by a current source constituted by the current source CS2 and the MOS field effect transistors M32 and M33, so that the behavior (waveform) of the output current Ip when the output current Ip is limited can be controlled to a desired behavior (waveform).

[0058] Fig. 5 is a waveform diagram for explaining the operation of the second current mirror circuit. In Fig. 5, from the top, a waveform diagram of the gate voltage V1 of the MOS field effect transistor M31, a waveform diagram of the drain current Ids_M31 of the MOS field effect transistor M31, a waveform diagram of the gate voltage V2 of the MOS field effect transistors M6 and M7, a waveform diagram of the drain current Ids_M32 of the MOS field effect transistor M32, and a waveform diagram of the drain current Ids_M6 of the MOS field effect transistor M6 are depicted.

[0059] When the reference current (the drain current of the MOS field effect transistor M5) Iref increases due to the activation of the overcurrent protection circuit OCP2, the gate voltage V1 of the MOS field effect transistor M31 also increases.

[0060] Following the rise in the gate voltage V1 of the MOS field effect transistor M31, the drain current Ids_M31 of the MOS field effect transistor M31 starts to flow, which causes the MOS field effect transistor M31 to start charging the gates of the MOS field effect transistors M6 and M7, causing the gate voltage V2 of the MOS field effect transistors M6 and M7 to rise.

[0061] When the gate voltage V2 of the MOS field effect transistors M6 and M7 rises and the gate-source voltage of the MOS field effect transistor M6 exceeds the threshold voltage, the drain current Ids_M6 of the MOS field effect transistor M6 starts to flow.

[0062] Thereafter, when the gate voltage V2 of the MOS field effect transistors M6 and M7 further increases and exceeds the operating point, the MOS field effect transistor M6 lowers the gate voltage V1 of the MOS field effect transistor M31 in order to keep the drain current Ids_M6 of the MOS field effect transistor M6 at the steady value of the reference current Iref.

[0063] When the gate voltage V1 of the MOS field effect transistor M31 decreases, the charging current through the MOS field effect transistor M31 decreases, and the current Ibias (the drain current Ids_M32 of the MOS field effect transistor M32) corresponding to the discharging current becomes dominant over the charging current, so that the gate voltage V2 of the MOS field effect transistors M6 and M7 also decreases.

[0064] Thereafter, when the gate voltage V2 of the MOS field effect transistors M6 and M7 further drops below the operating point, the MOS field effect transistor M6 increases the gate voltage V1 of the MOS field effect transistor M31 in order to keep the drain current Ids_M6 of the MOS field effect transistor M6 at the steady value of the reference current Iref.

[0065] When the gate voltage V1 of the MOS field effect transistor M31 increases, the charging current through the MOS field effect transistor M31 increases and becomes dominant over the current Ibias (the drain current Ids_M32 of the MOS field effect transistor M32) which corresponds to the discharging current, so that the gate voltage V2 of the MOS field effect transistors M6 and M7 also increases.

[0066] Thereafter, the gate voltage V1 of the MOS field effect transistor M31 and the gate voltage V2 of the MOS field effect transistors M6 and M7 repeatedly rise and fall, and converge to an operating point.

[0067] The rate at which the gate voltage V2 of the MOS field effect transistors M6 and M7 drops depends on the control value of the drain current Ids_M32 of the MOS field effect transistor M32, which is determined by the setting value of the output current of the current source CS2.

[0068] When the control value of the drain current Ids_M32 of the MOS field effect transistor M32 is large, the time it takes for the gate voltage V2 to transition from rising to falling becomes shorter and the rate of change of the gate voltage V2 when it falls becomes larger, resulting in a smaller overshoot of the gate voltage V2 of the MOS field effect transistors M6 and M7. On the other hand, when the control value of the drain current Ids_M32 of the MOS field effect transistor M32 is small, the time it takes for the gate voltage V2 to transition from rising to falling becomes longer and the rate of change of the gate voltage V2 when it falls becomes smaller, resulting in a larger overshoot of the gate voltage V2 of the MOS field effect transistors M6 and M7.

[0069] After the output current Ip reaches a start value, the overcurrent protection circuit OCP2 limits the output current Ip so that it converges to a limit value smaller than the start value.

[0070] Therefore, for example, when the difference between the start value and the limit value is large as shown in Fig. 6, it is desirable to set the control value of the drain current Ids_M32 of the MOS field effect transistor M32 small so as to prioritize reducing the output current Ip to the limit value as soon as possible in order to suppress heat generation in the MOS field effect transistor M15, which is the output transistor. With such a setting, the discharge current that discharges the gate of the MOS field effect transistor M15 becomes large, so that the ringing of the output current Ip becomes large, but the time required to reduce the output current Ip from the start value to the limit value can be shortened. On the other hand, when the control value of the drain current Ids_M32 of the MOS field effect transistor M32 is set large, the ringing of the output current Ip becomes small, but the time required to reduce the output current Ip from the start value to the limit value becomes long.

[0071] In Fig. 6, the waveform of the output current Ip when the control value of the drain current Ids_M32 of the MOS field effect transistor M32 is set small is depicted by a thick solid line, and in Fig. 6, the waveform of the output current Ip when the control value of the drain current Ids_M32 of the MOS field effect transistor M32 is set large is depicted by a thin solid line.

[0072] For example, as shown in Fig. 7, when the difference between the start value and the limit value is small, it is desirable to set the control value of the drain current Ids_M32 of the MOS field effect transistor M32 large so as to prioritize the convergence of the output current Ip to the limit value quickly. With such a setting, the discharge current that discharges the gate of the MOS field effect transistor M15 becomes small, so that the time required to reduce the output current Ip from the start value to the limit value becomes long, but the ringing of the output current Ip becomes small. On the other hand, when the control value of the drain current Ids_M32 of the MOS field effect transistor M32 is set small, the time required to reduce the output current Ip from the start value to the limit value can be shortened, but the ringing of the output current Ip becomes large.

[0073] In Fig. 7, the waveform of the output current Ip when the control value of the drain current Ids_M32 of the MOS field effect transistor M32 is set small is depicted by a thick solid line, as in Fig. 6. Also, in Fig. 7, the waveform of the output current Ip when the control value of the drain current Ids_M32 of the MOS field effect transistor M32 is set large is depicted by a thin solid line, as in Fig. 6.

[0074] <Application to vehicles> 8 is an external view showing one configuration example of a vehicle. The vehicle X of this configuration example is equipped with various load driving devices that operate by receiving power supply from a battery.

[0075] The vehicle X includes not only engine vehicles but also electric vehicles (xEVs such as BEVs (battery electric vehicles), HEVs (hybrid electric vehicles), PHEVs / PHVs (plug-in hybrid electric vehicles / plug-in hybrid vehicles), or FCEVs / FCVs (fuel cell electric vehicles / fuel cell vehicles)).

[0076] It should be noted that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for the sake of convenience.

[0077] The electronic device X11 is an electronic control unit that performs engine-related control (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto-cruise control) or motor-related control (such as torque control and power regeneration control).

[0078] The electronic device X12 is a lamp control unit that controls the turning on and off of HID (high intensity discharged lamps) and DRL (daytime running lamps).

[0079] The electronic device X13 is a transmission control unit that performs control related to the transmission.

[0080] The electronic device X14 is a braking unit that performs control related to the motion of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

[0081] The electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, and the like.

[0082] The electronic device X16 is an electronic device that is installed in the vehicle X at the factory as a standard equipment or a manufacturer's option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat.

[0083] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0084] The electronic device X18 is an electronic device equipped with a high-voltage resistant motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.

[0085] The electronic device 10A described above can be understood as any of the electronic devices X11 to X18. That is, the semiconductor device 1A described above can be incorporated into any of the electronic devices X11 to X18. The electronic device 10B described above can be understood as any of the electronic devices X11 to X18 that has a capacitive load. That is, the semiconductor device 1B described above can be incorporated into any of the electronic devices X11 to X18 that has a capacitive load.

[0086] <Other> The embodiments of the present disclosure may be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The various embodiments described above may be combined as appropriate within a range that does not cause inconsistency. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments.

[0087] For example, in the above embodiment, an example of application to a low-side switch IC has been given, but the same circuit configuration as in the above embodiment can also be applied to a high-side switch IC.

[0088] <Additional Notes> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0089] The overcurrent protection circuit (OCP1, OCP2) of the present disclosure is an overcurrent protection circuit configured to limit a monitored current based on a current limit signal, The amplifier circuit includes a first transistor (M1) and a second transistor (M2) configured to form an amplifier input stage that receives an input of a detection signal corresponding to the monitored current, a third transistor (M3) configured to form an amplifier output stage that generates a current output signal corresponding to the difference between the detection signal and a reference signal and negatively feeds back the current output signal to the amplifier input stage, a current mirror circuit (M6, M7) configured to generate the current limit signal by replicating a signal based on the current output signal, and a first current source (CS1) connected to an output terminal of the current mirror circuit configured to output the current limit signal, wherein the first current source is configured to switch the current output from the first current source between a fixed value and a variable value (first configuration).

[0090] According to the overcurrent protection circuit of the first configuration, it is possible to detect an overcurrent with high accuracy, and to fix the detection value of the overcurrent even if the slew rate of the output transistor through which the monitored current flows is variable.

[0091] In the overcurrent protection circuit of the above first configuration, the first current source may be configured to switch the current output from the first current source between the fixed value and the variable value in response to the current output signal (second configuration).

[0092] In the overcurrent protection circuit of the second configuration, a current switching control transistor is provided, and the first current source is configured to switch the current output from the first current source between the fixed value and the variable value depending on the on state and off state of the current switching control transistor, and a control terminal of the current switching control transistor and a control terminal of the third transistor are commonly connected, and a threshold voltage of the current switching control transistor is smaller than a threshold voltage of the third transistor (third configuration).

[0093] In the overcurrent protection circuit of any of the first to third configurations, the current mirror circuit may be configured (fourth configuration) to include a fourth transistor (M6), a fifth transistor (M7), a source follower circuit (M31), and a second current source (M32, M33, CS2), the gate of the source follower circuit is connected to the input terminal of the current mirror circuit, the source of the source follower circuit is connected to the gate of the fourth transistor and the gate of the fifth transistor, and the second current source is configured to control the value of a discharge current that discharges the gate of the fourth transistor and the gate of the fifth transistor.

[0094] The semiconductor device (1A, 1B) of the present disclosure has a configuration (fifth configuration) including an output transistor (M15) and an overcurrent protection circuit of any of the first to fourth configurations, configured so that the output current flowing through the output transistor is the current to be monitored.

[0095] In the semiconductor device of the above-mentioned fifth configuration, the overcurrent protection circuit may be configured to limit the output current by controlling a drive signal of the output transistor based on the current output signal (sixth configuration).

[0096] The electronic device (10A, 10B) of the present disclosure has a configuration (seventh configuration) including the semiconductor device of the fifth or sixth configuration.

[0097] The vehicle (X) of the present disclosure has a configuration (eighth configuration) including the electronic device of the seventh configuration. [Explanation of symbols]

[0098] 1A, 1B Semiconductor device 2. Control circuit 10A, 10B electronic equipment A1, A2 Analog Switch CS1 1st current source CS2 current source CS11 Variable Current Source CS12 constant current source IV1, IV2 inverter LD1 load M1~M7, M11~M15, M21~23, M31~M33 MOS field effect transistors OCP1, OCP2 Overcurrent protection circuit R1~R3 ​​resistance T1~T5 terminals VS1, VS2 DC power supply X Vehicle X11~X18 Electronic equipment

Claims

1. 1. An overcurrent protection circuit configured to limit a monitored current based on a current limit signal, comprising: a first transistor and a second transistor configured to form an amplifier input stage that receives an input of a detection signal corresponding to the monitored current; a third transistor configured to form an amplifier output stage that generates a current output signal corresponding to a difference between the detection signal and a reference signal and negatively feeds the current output signal back to the amplifier input stage; a current mirror circuit configured to generate the current limit signal by replicating a signal based on the current output signal; a first current source coupled to an output of the current mirror circuit configured to output the current limit signal; Equipped with An overcurrent protection circuit, wherein the first current source is configured to switch a current output from the first current source between a fixed value and a variable value.

2. 2. The overcurrent protection circuit of claim 1, wherein the first current source is configured to switch the current output from the first current source between the fixed value and the variable value in response to the current output signal.

3. A current switching control transistor is provided, the first current source is configured to switch a current output from the first current source between the fixed value and the variable value in response to an on state and an off state of the current switching control transistor; a control terminal of the current switching control transistor and a control terminal of the third transistor are commonly connected; 3. The overcurrent protection circuit according to claim 2, wherein a threshold voltage of said current switching control transistor is smaller than a threshold voltage of said third transistor.

4. the current mirror circuit includes a fourth transistor, a fifth transistor, a source follower circuit, and a second current source; a gate of the source follower circuit is connected to an input terminal of the current mirror circuit, and a source of the source follower circuit is connected to a gate of the fourth transistor and a gate of the fifth transistor; 2. The overcurrent protection circuit of claim 1, wherein the second current source is configured to control a value of a discharge current that discharges the gate of the fourth transistor and the gate of the fifth transistor.

5. An output transistor; The overcurrent protection circuit according to any one of claims 1 to 4, configured to set an output current flowing through the output transistor as the current to be monitored; A semiconductor device comprising:

6. 6. The semiconductor device according to claim 5, wherein said overcurrent protection circuit is configured to limit said output current by controlling a drive signal of said output transistor based on said current output signal.

7. An electronic device comprising the semiconductor device according to claim 5 .

8. A vehicle comprising the electronic device according to claim 7.

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