Circuit board and electronic element package

Abstract

To provide a circuit board capable of preventing resin application defects and an electronic element package in which electronic elements are mounted on the circuit board.SOLUTION: A circuit board 101 includes a substrate 110 including a first insulating layer 111 having a first surface 111a and a cavity 119 penetrating in the direction perpendicular to the first surface 111a, a first wiring layer 120 embedded in the first insulating layer 111 and exposed from the first insulating layer on at least one surface, and a buffer portion 117 disposed adjacent to the edge of cavity 119 in the first insulating layer 111 and having a housing surface that is set back from one exposed surface of the first wiring layer 120. A electronic element package includes an electronic element 70 housed in the cavity 119 of circuit board 101, an insulating material 90 disposed on the buffer portion 117 to fill and insulate the space between the electronic element 70 and the first wiring layer 120, and a rewiring layer 150 disposed on the side of the first surface 111a of the first insulating layer 111 and to which the electronic element 70 is connected.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to circuit boards and electronic device packages. [Background technology]

[0002] Recently, semiconductor packaging technology has been evolving with the continuous trend of miniaturization and multi-functionality of electronic products. This evolution is mainly related to the emergence of new technology platforms such as FOPLP (Fan-Out Panel Level Package), FOWLP (Fan-Out Wafer Level Package), and Side By Side packaging. These new packaging technologies include improved heat dissipation characteristics due to the increase in chip thickness and size.

[0003] However, as FOPLP packaging progresses, the distance between the chip mounting area and the copper (Cu) pattern inside the printed circuit board (PCB) becomes narrower due to the expansion of chip size. This can cause resin bleeding to occur on the copper side when applying resin after mounting the chip during the package on package (PLP) process. If resin bleeding prevents electrical conduction between layers, it can affect the performance and stability of the product. Therefore, technology is needed to ensure the quality of the cavity area of ​​the printed circuit board, which is the chip mounting area. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-80030 A Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention aims to provide a circuit board capable of preventing resin application defects during a Panel Level Package (PLP) process by improving the design of a cavity area, and an electronic device package in which an electronic device is mounted on the circuit board.

[0006] However, the problems to be solved by the embodiments of the present invention are not limited to the above problems, and may be variously expanded within the scope of the technical ideas included in the present invention. [Means for solving the problem]

[0007] In order to achieve the above-mentioned object, a circuit board according to one embodiment of the present invention includes a substrate including a first insulating layer having a first surface and having a cavity penetrating in a direction perpendicular to the first surface, a first wiring layer embedded in the first insulating layer and having at least one surface exposed from the first insulating layer, and a buffer portion arranged in the first insulating layer adjacent to an edge of the cavity and having a housing surface recessed from the exposed surface of the first wiring layer.

[0008] The first wiring layer may include a plurality of wiring patterns, and the accommodating surface of the buffer portion may be positioned recessed from a surface exposed from the first insulating layer of an innermost wiring pattern among the plurality of wiring patterns that is closest to the cavity. One side of the innermost wiring pattern may be covered by the first insulating layer, and the other side of the innermost wiring pattern may have a portion exposed from the first insulating layer. The innermost wiring pattern may have a portion whose side surface is exposed toward the cavity.

[0009] A surface of the first wiring layer exposed from the first insulating layer may be recessed from the first surface of the first insulating layer. The accommodation surface of the buffer portion is configured to face in the same direction as the first surface of the first insulating layer.

[0010] In order to achieve the above-mentioned object, an electronic element package according to one embodiment of the present invention includes a substrate including a first insulating layer having a first surface and having a cavity penetrating in a direction perpendicular to the first surface, a first wiring layer embedded in the first insulating layer and having at least one surface exposed from the first insulating layer, a buffer portion arranged adjacent to an edge of the cavity in the first insulating layer and having a housing surface recessed from the exposed surface of the first wiring layer, an electronic element to be housed in the cavity, an insulating material arranged on the buffer portion and filling the space between the electronic element and the first wiring layer to provide insulation, and a rewiring layer arranged on the first surface side of the first insulating layer and to which the electronic element is connected.

[0011] The electronic device package may further include an insulating protection layer disposed between the first surface of the first insulating layer and the redistribution layer so as to cover the first wiring layer. The first wiring layer may include a plurality of wiring patterns, and the accommodating surface of the buffer portion may be positioned recessed from a surface exposed from the first insulating layer of an innermost wiring pattern among the plurality of wiring patterns that is closest to the cavity. One side of the innermost wiring pattern may be covered by the first insulating layer, and another side of the innermost wiring pattern may have an exposed portion. The insulating material is disposed on the buffer portion so as to contact one side of the innermost wiring pattern. The insulating material may have a surface located on the receiving surface of the buffer portion, the surface being recessed from a surface of the innermost wiring pattern exposed from the first insulating layer.

[0012] The exposed surface of the first wiring layer may be recessed from the first surface of the first insulating layer. The accommodation surface of the buffer portion is configured to face in the same direction as the first surface of the first insulating layer. The insulating material may include a silicon dioxide (SiO2) filler. The insulating material may include Ajinomoto Build-up Film (ABF). Effect of the Invention

[0013] According to the circuit board and electronic device package using the same according to the present invention, the design of the cavity area where the chip is mounted can be improved to prevent resin bleeding, which occurs when resin flows into the copper (Cu) pattern area of ​​the circuit board during application of ABF and resin in the PLP process.

[0014] By preventing resin bleeding around the chip mounting area, poor contact between layers inside the package can be improved and packaging yield can be ensured. [Brief description of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view showing a circuit board according to an embodiment; [Diagram 2] 2 is a cross-sectional view showing an electronic element package in which an electronic element is mounted on the circuit board shown in FIG. [Diagram 3] 5A to 5C are cross-sectional views illustrating a process for manufacturing an electronic device package by manufacturing a circuit board and mounting an electronic device thereon according to an embodiment. [Figure 4] 5A to 5C are cross-sectional views illustrating a process for manufacturing an electronic device package by manufacturing a circuit board and mounting an electronic device thereon according to an embodiment. [Diagram 5] 5A to 5C are cross-sectional views illustrating a process for manufacturing an electronic device package by manufacturing a circuit board and mounting an electronic device thereon according to an embodiment. [Figure 6] 5A to 5C are cross-sectional views illustrating a process for manufacturing an electronic device package by manufacturing a circuit board and mounting an electronic device thereon according to an embodiment. [Figure 7] 5A to 5C are cross-sectional views illustrating a process for manufacturing an electronic device package by manufacturing a circuit board and mounting an electronic device thereon according to an embodiment. [Figure 8]5A to 5C are cross-sectional views illustrating a process for manufacturing an electronic device package by manufacturing a circuit board and mounting an electronic device thereon according to an embodiment. [Figure 9] 5A to 5C are cross-sectional views illustrating a process for manufacturing an electronic device package by manufacturing a circuit board and mounting an electronic device thereon according to an embodiment. [Figure 10] 5A to 5C are cross-sectional views illustrating a process for manufacturing an electronic device package by manufacturing a circuit board and mounting an electronic device thereon according to an embodiment. [Figure 11] 5A to 5C are cross-sectional views illustrating a process for manufacturing an electronic device package by manufacturing a circuit board and mounting an electronic device thereon according to an embodiment. [Figure 12] 5A to 5C are cross-sectional views illustrating a process for manufacturing an electronic device package by manufacturing a circuit board and mounting an electronic device thereon according to an embodiment. [Figure 13] 5A to 5C are cross-sectional views illustrating a process for manufacturing an electronic device package by manufacturing a circuit board and mounting an electronic device thereon according to an embodiment. [Figure 14] 5A to 5C are cross-sectional views illustrating a process for manufacturing an electronic device package by manufacturing a circuit board and mounting an electronic device thereon according to an embodiment. [Figure 15] 5A to 5C are cross-sectional views illustrating a process for manufacturing an electronic device package by manufacturing a circuit board and mounting an electronic device thereon according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, with reference to the drawings, the embodiments of the present invention will be described in detail so that those skilled in the art can easily carry out the present invention. In order to clearly explain the present invention in the drawings, parts unnecessary for the explanation are omitted, and the same or similar components are given the same reference numerals throughout the specification. In addition, in the drawings, some components are exaggerated, omitted, or illustrated in a schematic manner, and the size of each component does not completely reflect the actual size.

[0017] The drawings are intended to facilitate understanding of the embodiments disclosed in this specification, and are not intended to limit the technical ideas disclosed in this specification. It should be understood that the drawings include all modifications, equivalents, and alternatives included in the idea and technical scope of the present invention.

[0018] Terms including ordinal numbers such as first, second, etc. are used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0019] Furthermore, when a part such as a layer, film, region, or plate is "on" or "above" another part, it includes not only when it is "directly on" the other part, but also when there is another part in between. Conversely, when a part is "directly on" another part, it means that there is no other part in between. Furthermore, when a part is "on" or "above" a reference part, it means that it is located above or below the reference part, and does not necessarily mean that it is located "on" or "above" the opposite direction of gravity.

[0020] Throughout the specification, the terms "comprise" or "have" and the like are intended to specify the presence of the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Thus, when a part is said to "comprise" a certain element, this does not mean to exclude other elements, but rather to further include other elements, unless specifically stated to the contrary.

[0021] Also, throughout the specification, the term "on a plane" means when the part is viewed from above, and the term "on a cross section" means when the part is cut vertically and viewed from the side.

[0022] In addition, throughout the specification, when the term "connected" is used, this does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected via other components, or that they are not only physically connected, but also electrically connected, or that they are referred to by different names depending on their location or function but are integrated.

[0023] FIG. 1 is a cross-sectional view showing a circuit board according to an embodiment, and FIG. 2 is a cross-sectional view showing an electronic element package in which an electronic element is mounted on the circuit board shown in FIG.

[0024] 1, the circuit board 101 according to the present embodiment includes a substrate 110 having a first insulating layer 111 and a cavity 119 formed therethrough, and a first wiring layer 120 embedded in the first insulating layer 111. The first insulating layer 111 and the first wiring layer 120 may have an ETS (Embedded Trace Substrate) structure. The circuit board 101 can be used as a printed circuit board for semiconductor packaging.

[0025] The first insulating layer 111 has a first surface 111a and a second surface 111b facing each other. The first insulating layer 111 includes a resin insulating layer. The first insulating layer 111 may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a resin impregnated with a reinforcing agent such as glass fiber or an inorganic filler, for example, a prepreg. The first insulating layer 111 may include, but is not limited to, a thermosetting resin and / or a photocurable resin.

[0026] At least one surface of the first wiring layer 120 is exposed from the first insulating layer 111. The first wiring layer 120 has an upper surface that is lower than the upper surface of the first insulating layer 111, and the upper surface of the first wiring layer 120 is exposed. That is, the exposed surface of the first wiring layer 120 is located recessed from the first surface 111a of the first insulating layer 111. The first wiring layer 120 contains copper (Cu), is exposed from the first insulating layer 111, and is connected to a terminal of an external circuit component.

[0027] The cavity 119 is formed penetrating the substrate 110 in a direction perpendicular to the first surface 111a. An electronic element 70 (see FIG. 2) is mounted in the cavity 119. The electronic element 70 includes various elements such as an active element, a passive element, and an integrated circuit (IC) chip, and may be, for example, a semiconductor chip.

[0028] The buffer portion 117 is disposed adjacent to the edge of the cavity 119 in the first insulating layer 111. The buffer portion 117 has a shape in which a part of the upper end of the first insulating layer 111 is removed, and has a storage surface that is recessed from the exposed one surface of the first wiring layer 120. That is, in terms of a height measured in a direction perpendicular to the first surface 111a of the first insulating layer 111, the storage surface of the buffer portion 117 is formed lower than the exposed one surface of the first wiring layer 120. The storage surface of the buffer portion 117 is configured to face the same direction as the first surface 111a of the first insulating layer 111. Such a buffer portion 117 is formed continuously or intermittently along the edge of the cavity 119.

[0029] The first wiring layer 120 includes a plurality of wiring patterns 121, 123, and among the plurality of wiring patterns 121, 123, the innermost wiring pattern 121 closest to the cavity 119 is adjacent to the buffer portion 117. At this time, the accommodation surface of the buffer portion 117 is located lower and recessed than one surface of the innermost wiring pattern 121 exposed from the first insulating layer 111. Therefore, one side of the innermost wiring pattern 121 is covered by the first insulating layer 111, and at least a portion of the other side is exposed from the first insulating layer 111. The exposed side of the innermost wiring pattern 121 faces the cavity 119. The first surface of the first insulating layer 111 covering one side of the innermost wiring pattern 121 is higher than the exposed surface of the innermost wiring pattern 121. That is, the exposed surface of the innermost wiring pattern 121 is located recessed from the first surface of the first insulating layer 111.

[0030] The substrate 110 includes a build-up structure 130 disposed on the second surface 111b of the first insulating layer 111. The build-up structure 130 includes a build-up insulating layer, a build-up wiring layer, and a via layer 135. The build-up insulating layer includes a plurality of insulating layers, and the build-up wiring layer includes a plurality of wiring layers embedded in each of the plurality of insulating layers, and the layers are electrically connected to each other through the plurality of via layers 135. The cavity 119 is formed penetrating the build-up insulating layer. An outermost wiring layer 133 is disposed on an outermost insulating layer 131 of the build-up structure 130 located on the second surface 111b side of the first insulating layer 111.

[0031] 2, an electronic device package 100 according to this embodiment includes a circuit board 101 and an electronic device 70 accommodated in a cavity 119 of the circuit board 101. The electronic device 70 may be an integrated circuit (IC) chip or a semiconductor chip.

[0032] Insulating material 90 is disposed around electronic element 70 to fix electronic element 70 accommodated in cavity 119 and prevent unnecessary electrical current flow between electronic element 70 and wiring of circuit board 101. Insulating material 90 is disposed within cavity 119, filling the space between electronic element 70 and first wiring layer 120 of circuit board 101. In addition, insulating material 90 is disposed on outermost insulating layer 131 so as to cover outermost wiring layer 133, and is disposed so as to fill the space between outermost wiring layer 133 and electronic element 70.

[0033] The buffer portion 117 disposed adjacent to the edge of the cavity 119 in the first insulating layer 111 of the circuit board 101 has a housing surface lower than one surface of the first wiring layer 120 exposed from the first insulating layer 111. More specifically, among the multiple wiring patterns 121, 123 constituting the first wiring layer 120, the innermost wiring pattern 121 closest to the cavity 119 is adjacent to the buffer portion 117, and the housing surface of the buffer portion 117 is located lower and recessed than the exposed one surface of the innermost wiring pattern 121. Therefore, between the electronic element 70 and the innermost wiring pattern 121, the insulating material 90 is disposed on the housing surface of the buffer portion 117. Also, the insulating material 90 is disposed so as to contact one side of the innermost wiring pattern 121 on the housing surface of the buffer portion 117, and has one surface located recessed from one surface of the innermost wiring pattern 121 exposed from the first insulating layer 111.

[0034] The insulating material 90 may be made of a polymer insulating material having fluidity and adhesiveness, and may contain a component different from that of the first insulating layer 111. The insulating material 90 may contain a silicon dioxide (SiO2) filler that enhances adhesiveness and insulating properties, and may be an Ajinomoto Build-up Film (ABF).

[0035] The electronic element package 100 may be a fan-out semiconductor package, and is arranged in a cavity 119 of a circuit board 101 such that a connection end 71 of an electronic element 70 is located on a first surface 111a side of a first insulating layer 111 constituting the board 110. On the first surface 111a side, one surface of a rewiring layer 150 is arranged, and the electronic element 70 is connected, and the first wiring layer 120 of the circuit board 101 is also connected to the rewiring layer 150. On the other surface of the rewiring layer 150, a connection pad 151 is arranged, and this connection pad 151 is partially exposed while being covered with a solder resist layer 152. A connection terminal 154 is connected to the exposed portion of the connection pad 151.

[0036] At least a portion of the electronic element 70 and the outermost insulating layer 131 of the substrate 110 are covered with an insulating material 90. The insulating material 90 covers an outermost wiring layer 133 disposed on the outermost insulating layer 131 of the substrate 110. A portion of the outermost wiring layer 133 disposed on the outermost insulating layer 131 is exposed from the insulating material 90 and functions as a connection pad.

[0037] An insulating protective layer 141 is disposed between the first surface 111a of the first insulating layer 111 and the rewiring layer 150. The insulating protective layer 141 is an underfill resin that is filled between the electronic element 70 and the rewiring layer 150 to protect the connection portion. The insulating protective layer 141 is configured by disposing a photosensitive insulating (Photo Imageable Dielectric, PID) resin between the substrate 110 and the rewiring layer 150.

[0038] 3 to 15 are cross-sectional views illustrating the steps of a method for manufacturing an electronic element package by manufacturing a circuit board according to one embodiment and mounting an electronic element thereon.

[0039] 3 to 6, a carrier substrate 60 having a first seed layer 81 disposed on at least one surface is prepared, and a first wiring pattern layer 124A is formed on the first seed layer 81 through a circuit formation process. The carrier substrate 60 is a substrate having copper foil layers 62 laminated on both surfaces of an insulating substrate 61, and the first seed layer 81 and the copper foil layer 62 can be separated from each other (see FIG. 3). A plating resist pattern 83 is formed on the carrier substrate 60, in which only the portion where the first wiring pattern layer 124A is to be formed is removed by exposure and development (see FIG. 4). The first wiring pattern layer 124A is formed by plating a conductive metal on the portion of the first seed layer 81 exposed through the opening of the patterned plating resist pattern 83 (see FIG. 5). After the first wiring pattern layer 124A is formed, the plating resist pattern is removed (see FIG. 6).

[0040] The first seed layer 81 can be applied without any restrictions as long as it is used as a conductive metal for circuits in the field of circuit boards, and copper (Cu) is generally used. The first wiring pattern layer 124A is connected to the first seed layer 81 of the carrier substrate 60 and contains the same type of metal as the first seed layer 81. For example, the first seed layer 81 and the first wiring pattern layer 124A contain copper (Cu).

[0041] In this embodiment, the first wiring pattern layer 124A is formed on both sides of the carrier substrate 60, but it is also possible to form the first wiring pattern layer 124A only on one side of the carrier substrate 60, which also falls within the scope of the present invention.

[0042] 7, an insulating layer 112 is laminated so that the first wiring pattern layer 124A is embedded, and a second seed layer 85 is formed on the upper surface of the insulating layer 112. The second seed layer 85 is formed to form a second wiring pattern layer 134, and although any conductive metal can be used without limitation, copper is generally used.

[0043] The insulating layer 112 includes a resin insulating layer. The insulating layer 112 may be made of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a resin impregnated with a reinforcing agent such as glass fiber or an inorganic filler, for example, a prepreg, and may include, but is not limited to, a thermosetting resin and / or a photocurable resin.

[0044] 8 and 9, a second wiring pattern layer 134A is formed on the insulating layer 112 through a circuit formation process. The second wiring pattern layer 134A is formed in a similar manner to the method of forming the first wiring pattern layer 124A, and the second wiring pattern layer 134A includes the same material as the first wiring pattern layer 124A. At this time, in order to form a via 136 connecting the first wiring pattern layer 124A and the second wiring pattern layer 134A to each other, the insulating layer 112 is partially etched to expose a part of the first wiring pattern layer 124A (see FIG. 8), and a plating process is performed on the part of the first wiring pattern layer 124A thus exposed (see FIG. 9). As a result, an embedded pattern substrate part is completed on both sides of the carrier substrate 60.

[0045] According to the illustrated embodiment, each embedded pattern substrate portion is shown to include one insulating layer 112 and two metal layers, a first wiring pattern layer 124A and a second wiring pattern layer 134A, but is not limited to this and may include more build-up insulating layers and more build-up wiring pattern layers, which also falls within the scope of the present invention.

[0046] 10, a buried pattern substrate is prepared by separating the first seed layer 81 from the carrier substrate 60. The first seed layer 81 formed on both sides of the carrier substrate 60 can be separated from the copper foil layer 62 to obtain a pair of buried pattern substrates, and a process is applied to each of the pair of buried pattern substrates individually.

[0047] 11, the buried pattern substrate obtained in FIG. 10 is soft-etched to remove the first seed layer 81 and the second seed layer 85. After removing the first seed layer 81 and the second seed layer 85, the first wiring pattern layer 124A buried in the insulating layer 112 forms the first wiring layer 124 including a plurality of wiring patterns, and the second wiring pattern layer 134A disposed on one surface of the insulating layer 112 forms the outermost wiring layer 134. In the process of removing the first seed layer 81, the surface of the first wiring pattern layer 124A exposed from the insulating layer 112 is also partially etched, and the first wiring layer 120 is formed to be recessed from the surface of the insulating layer 112.

[0048] 12, the center of the buried pattern substrate obtained in FIG. 11 is etched to form a cavity 119. The cavity processing can be performed using a variety of known processes, such as laser drilling, mechanical drilling, a router process, and etching.

[0049] 13, the insulating layer 112 is partially etched along the edge of the cavity 119 of the circuit board obtained from FIG. 12 to process the buffer portion 117. The buffer portion 117 is processed to have an upper surface lower than an upper surface of the innermost wiring pattern of the first wiring layer 124 that is closest to the cavity 119. The buffer portion 117 is also processed to expose one side of the innermost wiring pattern of the first wiring layer 124 toward the cavity 119. The processing of the buffer portion 117 can be performed using a CO2 laser.

[0050] 14 and 15, an electronic element 70 is accommodated in a cavity 119 of a circuit board, and an insulating material 90 is arranged around and fixed to the electronic element 70. The insulating material 90 is arranged in the cavity 119 to fill the space between the electronic element 70 and the first wiring layer 124 of the circuit board. The insulating material 90 is also arranged on the insulating layer 112 so as to cover the outermost wiring layer 134, and is arranged to fill the space between the outermost wiring layer 134 and the electronic element 70. The insulating material 90 fixes the electronic element 70 accommodated in the cavity 119 to the circuit board, and prevents unnecessary electrical current from flowing between the electronic element 70 and the wiring of the circuit board.

[0051] The insulating material 90 is disposed on the buffer portion 117 between the electronic element 70 and the innermost wiring pattern of the first wiring layer 124. The insulating material 90 is disposed on the buffer portion 117 so as to contact one side of the innermost wiring pattern, and is formed lower than the upper surface of the innermost wiring pattern.

[0052] The insulating material 90 is made of a polymer insulating material having fluidity and adhesiveness, and contains a component different from that of the first insulating layer 112. The insulating material 90 contains a silicon dioxide (SiO2) filler that enhances adhesiveness and insulating properties, and may be an Ajinomoto Build-up Film (ABF).

[0053] Although the preferred embodiment of the present invention has been described above, the present invention is not limited thereto, and various modifications can be made within the scope of the detailed description and drawings of the invention, which of course also fall within the scope of the present invention. [Explanation of symbols]

[0054] 100 Electronic device package 101 Circuit Board 110 Substrate 111 First insulating layer 117 Buffer section 119 Cavity 120 1st wiring layer 130 Build-up structure 131 Outermost insulating layer 133 Outermost wiring layer 135 Via Layer 141 Insulating protective layer 150 redistribution layer 151 Connection Pad 152 Solder resist layer 154 Connection terminal 70 Electronic Elements 90 Insulation

Claims

1. a substrate including a first insulating layer having a first surface and a cavity extending therethrough in a direction perpendicular to the first surface; a first wiring layer embedded in the first insulating layer and having at least one surface exposed from the first insulating layer; a buffer portion disposed adjacent to an edge of the cavity in the first insulating layer and having a receiving surface recessed from the exposed surface of the first wiring layer; A circuit board comprising:

2. the first wiring layer includes a plurality of wiring patterns; 2. The circuit board according to claim 1, wherein the accommodation surface of the buffer portion is located recessed from a surface exposed from the first insulating layer of an innermost wiring pattern among the plurality of wiring patterns that is closest to the cavity.

3. 3. The circuit board according to claim 2, wherein one side of the innermost wiring pattern is covered by the first insulating layer, and another side of the innermost wiring pattern has a portion exposed from the first insulating layer.

4. 3. The circuit board according to claim 2, wherein the innermost wiring pattern has a side surface exposed toward the cavity.

5. The circuit board according to claim 1 , wherein a surface of the first wiring layer exposed from the first insulating layer is positioned recessed from the first surface of the first insulating layer.

6. The circuit board according to claim 1 , wherein the housing surface of the buffer portion is configured to face the same direction as the first surface of the first insulating layer.

7. a substrate including a first insulating layer having a first surface and a cavity extending therethrough in a direction perpendicular to the first surface; a first wiring layer embedded in the first insulating layer and having at least one surface exposed from the first insulating layer; a buffer portion disposed adjacent to an edge of the cavity in the first insulating layer and having a receiving surface recessed from the exposed surface of the first wiring layer; an electronic element housed within the cavity; an insulating material disposed on the buffer portion, the insulating material filling a gap between the electronic element and the first wiring layer to provide insulation therebetween; a redistribution layer disposed on the first surface side of the first insulating layer and connected to the electronic element; 13. An electronic device package comprising:

8. The electronic device package according to claim 7 , further comprising an insulating protection layer disposed between the first surface of the first insulating layer and the redistribution layer so as to cover the first wiring layer.

9. the first wiring layer includes a plurality of wiring patterns; 8. The electronic element package according to claim 7, wherein the receiving surface of the buffer portion is located recessed from a surface exposed from the first insulating layer of an innermost wiring pattern among the plurality of wiring patterns that is closest to the cavity.

10. 10. The electronic device package of claim 9, wherein one side of the innermost wiring pattern is covered by the first insulating layer, and another side of the innermost wiring pattern has an exposed portion.

11. The electronic device package of claim 9 , wherein the insulating material is disposed on the buffer portion so as to contact one side of the innermost wiring pattern.

12. 10. The electronic element package according to claim 9, wherein the insulating material has a surface that is recessed from a surface of the innermost wiring pattern that is exposed from the first insulating layer on the receiving surface of the buffer portion.

13. The electronic device package according to claim 7 , wherein the exposed surface of the first wiring layer is recessed from the first surface of the first insulating layer.

14. The electronic element package according to claim 7 , wherein the receiving surface of the buffer portion is configured to face the same direction as the first surface of the first insulating layer.

15. The insulating material is silicon dioxide (SiO ２ 8. The electronic device package of claim 7, further comprising a filler.

16. 8. The electronic device package of claim 7, wherein the insulating material comprises Ajinomoto Build-up Film (ABF).

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