Semiconductor device

Abstract

To provide a display device which performs a stable operation by using a transistor having stable electrical characteristics.SOLUTION: In manufacturing of a display device by applying a transistor using an oxide semiconductor layer as a channel formation region, an additional gate electrode is arranged at least on a transistor applied to a drive circuit. In manufacturing of the transistor using the oxide semiconductor layer as the channel formation region, a heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor layer, an impurity such as moisture existing in an interface among a gate insulation layer and a protective insulation layer, and the oxide semiconductor layer is reduced.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a display device having a circuit formed of transistors. [Background technology]

[0002] Metal oxides exist in a wide variety of forms and are used for a variety of purposes. Indium is a well-known material that has the translucency required for liquid crystal displays and the like. It is used as a conductive material.

[0003] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include: For example, there are tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Transistors that use metal oxides that exhibit semiconducting properties as their channel formation region are already known. (See, for example, Patent Documents 1 to 4 and Non-Patent Document 1).

[0004] By the way, metal oxides are not only single-component oxides, but also multi-component oxides. For example, , InGaO3(ZnO) with homologous phase m (m: natural number) is In, Ga and It is known as a multi-element oxide semiconductor containing Zn (see Non-Patent Documents 2 to 4). reference).

[0005] Then, the oxide semiconductor layer made of the above-mentioned In-Ga-Zn-based oxide is It has been confirmed that this material can be used as a channel layer for transistors (Patent Document 5, Non-Patent Document 6). (See references 5 and 6). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Special Publication No. 60-198861 [Patent Document 2] Special Publication No. 8-264794 [Patent Document 3] Special Publication No. 11-505377 [Patent Document 4] Special Publication No. 2000-150900 [Patent Document 5] Japanese Patent Publication No. 2004-103957

Non-licensed documents

[0007]

Non-patent document 1

Non-patent document 2

Non-patent document 3

[0008] One embodiment of the present invention is a transistor having favorable electrical characteristics and high reliability, and a method for manufacturing the same. A method for producing a display device having a high display quality and high reliability is provided by applying the method. The objective of the project is to [Means for solving the problem]

[0009] One embodiment of the present invention is a display device provided with a transistor including an oxide semiconductor layer. The active matrix substrate of the display device has a pixel section and a driving circuit section, and at least In the driving circuit section, a further gate electrode is provided at a position overlapping with the back channel section. In manufacturing the transistor, the oxide semiconductor layer is subjected to heat treatment. The present invention is characterized in that the oxide is dehydrated or dehydrogenated by the heat treatment. A protective insulating layer is formed by covering the oxide semiconductor layer and using an insulating inorganic material containing oxygen. The carrier concentration also changes due to the phenomenon. Effect of the Invention

[0010] To manufacture a transistor with good electrical characteristics, and in particular, to have a low threshold voltage even when used for a long period of time. It is possible to fabricate transistors that are less susceptible to voltage shifts and are highly reliable. By applying the transistor to at least the driving circuit section, the reliability of the display device can be improved. This can be done. [Brief description of the drawings]

[0011] [Figure 1] 1A to 1C are diagrams illustrating a transistor according to one embodiment of the present invention. [Diagram 2] 1A to 1C are diagrams illustrating a transistor according to one embodiment of the present invention. [Diagram 3] FIG. 2 is a diagram illustrating an electric furnace that can be used in the present invention. [Figure 4] 1A to 1C are diagrams illustrating a transistor according to one embodiment of the present invention. [Diagram 5]1A to 1C are diagrams illustrating a transistor according to one embodiment of the present invention. [Figure 6] 1A to 1C are diagrams illustrating a transistor according to one embodiment of the present invention. [Figure 7] 1A to 1C are diagrams illustrating a transistor according to one embodiment of the present invention. [Figure 8] 1A to 1C are diagrams illustrating a transistor according to one embodiment of the present invention. [Figure 9] 1A to 1C are diagrams illustrating a transistor according to one embodiment of the present invention. [Figure 10] 1A to 1C are diagrams illustrating a transistor according to one embodiment of the present invention. [Figure 11] 1A to 1C are diagrams illustrating a display device which is one embodiment of the present invention. [Figure 12] 1A to 1C are diagrams illustrating a display device which is one embodiment of the present invention. [Figure 13] 1A to 1C are diagrams illustrating a display device which is one embodiment of the present invention. [Figure 14] 1A to 1C are diagrams illustrating a display device which is one embodiment of the present invention. [Figure 15] 1A to 1C are diagrams illustrating a display device which is one embodiment of the present invention. [Figure 16] 1A to 1C are diagrams illustrating a display device which is one embodiment of the present invention. [Figure 17] 1A to 1C are diagrams illustrating a display device which is one embodiment of the present invention. [Figure 18] 1A to 1C are diagrams illustrating a display device which is one embodiment of the present invention. [Figure 19] 1A to 1C are diagrams illustrating a display device which is one embodiment of the present invention. [Figure 20] 1A to 1C are diagrams illustrating a display device which is one embodiment of the present invention. [Figure 21] 1A to 1C are diagrams illustrating a display device which is one embodiment of the present invention. [Figure 22] 1A to 1C are diagrams illustrating a display device which is one embodiment of the present invention. [Diagram 23] 1A to 1C are diagrams illustrating a display device which is one embodiment of the present invention. [Figure 24] 1A to 1C are diagrams illustrating a display device which is one embodiment of the present invention. [Diagram 25] 1A to 1C are diagrams illustrating a display device which is one embodiment of the present invention. [Figure 26]1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 27] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 28] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 29] FIG. 1 is a diagram for explaining the first embodiment. [Diagram 30] FIG. 1 is a diagram for explaining the first embodiment. [Diagram 31] FIG. 1 is a diagram for explaining the first embodiment. [Diagram 32] FIG. 1 is a diagram for explaining the first embodiment. [Diagram 33] FIG. 11 is a diagram for explaining the second embodiment. [Diagram 34] FIG. 11 is a diagram for explaining a second embodiment. [Diagram 35] FIG. 11 is a diagram for explaining the second embodiment. [Diagram 36] FIG. 11 is a diagram for explaining the second embodiment. [Figure 37] FIG. 11 is a diagram for explaining a second embodiment. [Figure 38] FIG. 11 is a diagram for explaining a second embodiment. [Figure 39] FIG. 11 is a diagram for explaining a second embodiment. [Diagram 40] FIG. 11 is a diagram for explaining the second embodiment. [Diagram 41] FIG. 11 is a diagram for explaining a second embodiment. [Diagram 42] FIG. 11 is a diagram for explaining Example 3. [Diagram 43] FIG. 11 is a diagram for explaining Example 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various modifications and variations in form and detail may be made without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention may be modified in various ways. The present invention is not limited to the description of the embodiment. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. and the repeated explanation will be omitted.

[0013] The following first to fourth embodiments are directed to at least one embodiment of a display device according to the present invention. First, a transistor provided in at least the driver circuit portion will be described.

[0014] (Embodiment 1) This embodiment will describe a transistor and a transistor which can be applied to a display device according to one embodiment of the present invention. In the display device according to one embodiment of the present invention, at least a driving circuit The transistor of the present embodiment is applied to the path portion.

[0015] 1A to 1C are cross-sectional views of a transistor that can be used in one embodiment of the present invention. vinegar.

[0016] The transistor 471 is a bottom-gate transistor provided on the substrate 400. A first gate electrode layer 401, a gate insulating layer 402, and an oxide semiconductor layer 403 are formed on the first gate electrode layer 401. , and a source electrode and a drain electrode layer 405. Further, the oxide semiconductor layer 403 A first protective insulating layer 407 is provided on the first protective insulating layer 407. A second gate electrode layer 409 overlapping with the oxide semiconductor layer 403 is provided. Note that the first protective insulating layer 407 can also be called a second gate insulating layer.

[0017] The oxide semiconductor layer 403 including the channel formation region can be made of an oxide semiconductor material having semiconductor characteristics. For example, InMO3(ZnO) m Structure represented as (m>0) In particular, an In-Ga-Zn-O-based oxide semiconductor can be used. It is preferable that M is one metal selected from Ga, Fe, Ni, Mn and Co. For example, if M is Ga, it can be Ga and Ni or G. The above-mentioned metal elements other than Ga, such as a and Fe, may be contained.

[0018] In addition to the metal element M contained in the above oxide semiconductor, Fe, Ni, etc. Other transition metal elements or oxides of the transition metals may be included.

[0019] Among oxide semiconductors with a structure represented by InMO3(ZnO)m (m>0), M As an oxide semiconductor having a structure containing at least Ga, an In-Ga-Zn-O oxide semiconductor is used. and the thin film is also called an In-Ga-Zn-O based non-single crystal film.

[0020] In addition to the above, the oxide semiconductor layer 403 can be formed using In-S n-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn -O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn- O-based, In-O-based, Sn-O-based, and Zn-O-based oxide semiconductors can be used.

[0021] Note that the oxide semiconductor may contain silicon oxide.

[0022] In the formation of the oxide semiconductor layer 403, at least an oxide semiconductor film is formed, and then an impurity Heat treatment to reduce moisture (H2O) and other substances (heat treatment for dehydration or dehydrogenation) ) to lower the resistance (increase the carrier concentration, preferably 1×10 18 / cm 3 More than ), and a first protective insulating film is formed in contact with the oxide semiconductor film (or the processed oxide semiconductor layer). By forming the layer 407, the resistance is increased (the carrier concentration is decreased, preferably to 1×10 18 / cm 3 less than 1×10 14 / cm 3 (below) and the channel formation region It is possible to form an oxide semiconductor layer which can be used as the insulating region.

[0023] In addition, impurities such as moisture are removed by heat treatment for dehydration or dehydrogenation. After this process, it is preferable to slowly cool the mixture in an inert atmosphere. After performing a heat treatment for dehydrogenation or dehydration and gradually cooling, an insulating oxide film is formed in contact with the oxide semiconductor layer. The carrier concentration of the oxide semiconductor layer is reduced by forming an oxide film or the like, thereby This can improve the reliability of the sensor 471.

[0024] Furthermore, not only in the oxide semiconductor layer 403 but also in the gate insulating layer 402 and in contacts therebetween, Specifically, the interface between the gate insulating layer 402 and the oxide semiconductor layer 403 the interface between the first protective insulating layer 407 and the oxide semiconductor layer 403; Reduces impurities such as moisture present in the

[0025] The oxide semiconductor layer 403 is made of a high resistance oxide semiconductor at least in a region in contact with the inorganic insulating film. The high-resistance oxide semiconductor region can be used as a channel formation region. .

[0026] Note that the In-Ga-Zn-O-based non-single crystal film used for the oxide semiconductor layer 403 is amorphous. It may be either crystallite or microcrystalline, or it may be polycrystalline. However, the present invention is not limited to this and may be a single crystal.

[0027] By using a high-resistance oxide semiconductor region as a channel formation region, The electrical characteristics of the capacitor are stable, and an increase in off-state current, etc. can be prevented.

[0028] Then, a source electrode layer and a drain electrode layer 405 in contact with the oxide semiconductor layer 403 are formed. The material to be used is preferably a material containing a metal with high oxygen affinity. Materials contained include titanium, aluminum, manganese, magnesium, and zirconium. It is preferable to use a material selected from one or more of the following: It is nice.

[0029] When the oxide semiconductor layer 403 is brought into contact with a metal layer having high oxygen affinity and heat treatment is performed, the oxide semiconductor layer 403 is heated to 1000° C. Oxygen atoms move from the oxide semiconductor layer 403 to the metal layer, and the carrier density in the vicinity of the interface decreases. The low resistance region may be in the form of a film having an interface. .

[0030] In this way, the contact resistance of the transistor can be reduced and the on-current can be increased. Cut.

[0031] 2A to 2D show cross-sectional views of a manufacturing process of the transistor 471.

[0032] First, a first gate electrode layer 401 is formed on a substrate 400 having an insulating surface. The substrate 400 having a surface is made of aluminosilicate glass, aluminoborosilicate glass, burr Glass substrates used in the electronics industry, such as borosilicate glass ("non-alkali glass substrates"). The substrate is a heat-resistant plastic substrate that can withstand the processing temperatures of this manufacturing process. In the case where the substrate 400 having an insulating surface is a mother glass, 1st generation (320mm x 400mm), 2nd generation (400mm x 500mm), 3rd generation (550mm x 650mm), 4th generation (680mm x 880mm, or 730mm x 920mm), 5th generation (1000mm x 1200mm or 1100mm x 1250m m), 6th generation (1500mm x 1800mm), 7th generation (1900mm x 2200m m), 8th generation (2160mm x 2460mm), 9th generation (2400mm x 2800m m, 2450mm x 3050mm), 10th generation (2950mm x 3400mm), etc. Any size can be used.

[0033] Alternatively, similarly to FIG. 1C to be referred to later, the base insulating layer is connected to the substrate 400 and the first gate electrode. The base insulating layer may be formed between the electrode layers 401. The base insulating layer is formed by removing impurity elements (sodium) from the substrate 400. The insulating film may be formed of an insulating material capable of preventing the diffusion of metals such as silicon nitride. one selected from silicon oxide, silicon nitride oxide, and silicon oxynitride; It can be formed by laminating a plurality of films.

[0034] The first gate electrode layer 401 may be made of molybdenum, titanium, chromium, tantalum, or tungsten. Metallic materials such as aluminum, copper, neodymium, or scandium, or materials mainly composed of these The insulating film 10 can be formed as a single layer or a multilayer using an alloy material serving as a component.

[0035] For example, when the first gate electrode layer 401 has a two-layer laminate structure, an aluminum layer Two-layer structure with a molybdenum layer laminated on top, or a molybdenum layer laminated on a copper layer A two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a copper layer, or a titanium nitride It is preferable to use a two-layer structure in which a silicon layer and a molybdenum layer are laminated. In this case, a tungsten layer or a tungsten nitride layer and an alloy of aluminum and silicon are used. A layer or an alloy layer of aluminum and titanium and a titanium nitride layer or a titanium layer are laminated. It is preferable that the insulating layer has a three-layer structure.

[0036] The first gate electrode layer 401 is formed by forming a conductive film on the entire surface of the substrate 400 and then photolithographically A resist mask is formed on the conductive film by a roughening process, and unnecessary parts are etched away. The first gate electrode layer 401 is formed by removing the wiring and the electrode (first gate The gate electrode layer 401 constitutes a gate wiring, a capacitance wiring, a terminal electrode, and the like.

[0037] Next, a gate insulating layer 402 is formed over the first gate electrode layer 401 .

[0038] The gate insulating layer 402 is formed by oxidizing the gate insulating layer 402 using a plasma CVD method or a sputtering method. Silicon, silicon nitride, silicon oxynitride or silicon oxynitride can be used as a single layer or as a multilayer. For example, the source gas is SiH4, oxygen, and nitrogen. A silicon oxynitride layer is formed by plasma CVD using either one or both of the above. Alternatively, dinitrogen monoxide or the like may be used in place of oxygen and nitrogen.

[0039] Next, an oxide semiconductor film is formed over the gate insulating layer 402.

[0040] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced. The plasma is generated to perform reverse sputtering, and the gold adhering to the surface of the gate insulating layer 402 is removed. It is preferable to remove the ions, etc. Reverse sputtering is a method of applying an RF power source to a substrate in an argon atmosphere. A voltage is applied using the plasma generator to generate plasma, and the workpiece (e.g., a substrate) is immersed in the plasma. In addition, nitrogen or helium atmosphere can be used instead of argon atmosphere. Alternatively, oxygen or nitrous oxide may be added to the argon atmosphere. Alternatively, chlorine or tetrafluoromethane may be added to an argon atmosphere. It may be carried out in a comfortable atmosphere.

[0041] The oxide semiconductor film was formed by spat deposition using an In-Ga-Zn-O metal oxide as a target. The oxide semiconductor film is formed by a rare gas (e.g., argon) atmosphere. Sputtering in an oxygen atmosphere or in an atmosphere of rare gas (e.g. argon) and oxygen The film can be formed by a coating method.

[0042] Note that the gate insulating layer 402 and the oxide semiconductor film are successively formed without exposure to air. The gate insulating layer 402 and the oxide semiconductor film may be successively formed without being exposed to air. By forming the oxide semiconductor film, the interface between the gate insulating layer 402 and the oxide semiconductor film is protected from air components and airborne particles. Since it is formed without being contaminated by floating impurities (such as water or hydrocarbons), This makes it possible to reduce the variation in the characteristics of the transistors.

[0043] Next, the oxide semiconductor film is processed by a photolithography process to form an island-shaped first oxide A semiconductor layer 430 is formed (see FIG. 2(A)).

[0044] The first oxide semiconductor layer 430 is heated with an inert gas (nitrogen, helium, neon, After heat treatment under an atmosphere of rare gas such as argon or reduced pressure, The resulting mixture is slowly cooled in air to form a second oxide semiconductor layer 431 (see FIG. 2B). The oxide semiconductor layer 430 is subjected to heat treatment in the above atmosphere to form a first oxide semiconductor layer. Impurities such as hydrogen and water contained in the oxide semiconductor layer 430 are removed, and a second oxide semiconductor layer 431 is formed.

[0045] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain impurities such as water or hydrogen. The purity of nitrogen or rare gases such as helium, neon, and argon is 6N (99.99%). 99%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration It is preferable to set the concentration to 1 ppm or less, and more preferably 0.1 ppm or less.

[0046] The heat treatment can be performed using an electric furnace or a GRTA (Ga Rapid Thermal Anneal (LRTA) method or lamp light Instantaneous heating methods such as the Lamp Rapid Thermal Anneal method etc. can be used.

[0047] Here, in the case where an electric furnace is used for the heat treatment of the first oxide semiconductor layer 430, This will be explained using:

[0048] FIG. 3 is a schematic diagram of an electric furnace 601. The electric furnace 601 has a chamber 602. A heater 603 for heating the chamber 602 is provided on the outside of the chamber 602. A susceptor 605 for mounting a substrate 604 is provided in the chamber 602. A substrate 604 is loaded into or unloaded from a chamber 602. The chamber 602 is supplied with gas. The gas supply means 606 is connected to the exhaust means 607. Gas is introduced into the bar 602. Then, the inside of the chamber 602 is evacuated by the exhaust means 607. The electric furnace 601 is evacuated or the pressure in the chamber 602 is reduced. The temperature can be increased at a rate of 20°C / min or less and decreased at a rate of 0.1°C / min to 15°C / min. It is preferred.

[0049] The gas supply means 606 includes a gas supply source 611, a pressure adjusting valve 612, and a mass flow controller. The roller 614 and the stop valve 615 are provided. In this embodiment, the In order to achieve this, it is preferable to provide a purifier 613 between the gas source 611 and the chamber 602. By providing a purifier 613, the gas introduced from the gas supply source 611 into the chamber 602 is It is possible to remove impurities such as water or hydrogen contained in the gas to be fed into the chamber. This can prevent water or hydrogen from entering the inside of the housing 602.

[0050] In this embodiment, nitrogen or a rare gas is introduced into the chamber 602 from a gas supply source 611. The inside of the chamber 602 is filled with nitrogen or a rare gas atmosphere, and the temperature is set to 200° C. or higher and 600° C. or lower. In a chamber 602 that is preferably heated to 400° C. or higher and 600° C. or lower, a substrate 60 The first oxide semiconductor layer 430 formed on the substrate 4 (the substrate 400 in FIG. 1) is heated. In this manner, the first oxide semiconductor layer 430 can be dehydrated or dehydrogenated.

[0051] Alternatively, the temperature is increased by the exhaust means 607 under reduced pressure at 200° C. to 600° C., preferably 40° C. In a chamber 602 heated to 0° C. or higher and 600° C. or lower, a substrate 604 ( The first oxide semiconductor layer 430 formed over the substrate 400 is heated to form a first oxide The nitride semiconductor layer 430 can be dehydrated or dehydrogenated.

[0052] Next, the heater 603 is turned off and the chamber 602 is gradually cooled. The oxide semiconductor layer 430 is formed by heat treatment in an inert gas atmosphere or under reduced pressure and then slowly cooled. Therefore, the resistance is reduced (the carrier concentration is increased, preferably 1×10 18 / cm 3 (above) The second oxide semiconductor layer 431 can be used.

[0053] By carrying out the heat treatment as described above, the reliability of the transistor to be formed later can be improved. can be done.

[0054] When the heat treatment is performed under reduced pressure, an inert gas is introduced into the chamber 602 after the heating. and then cooled to atmospheric pressure.

[0055] After the substrate 604 in the chamber 602 of the heating device is cooled to about 300° C., The plate 604 may be moved to a room temperature atmosphere, thereby shortening the cooling time of the substrate 604. It is possible.

[0056] If the heating device is a multi-chamber device, the heating process and the cooling process are performed in different chambers. For example, nitrogen or a rare gas is filled and the temperature is 200°C to 600°C. In a first chamber heated to a temperature of 400° C. or higher and 600° C. or lower, The first oxide semiconductor layer 430 on the substrate 400 in FIG. 1 is heated. The nitrogen or rare gas is introduced into the transfer chamber, which is filled with nitrogen or rare gas and is then cooled to 100°C. transferring the heat-treated substrate to a second chamber at a temperature below 100° C., preferably at room temperature; By performing the heating and cooling processes in different chambers, throughput is improved. It is possible to do so.

[0057] Note that the first oxide semiconductor layer 430 was heated under an inert gas atmosphere or reduced pressure. The heat treatment is performed on the oxide semiconductor film before it is processed into the island-shaped first oxide semiconductor layer 430. In that case, the oxide semiconductor film may be heated under an inert gas atmosphere or reduced pressure. After the heat treatment, the substrate 604 (see FIG. 1) is gradually cooled to a temperature above room temperature and below 100° C. The substrate 400 is then taken out and a photolithography process is carried out.

[0058] Note that the first oxide semiconductor layer 430 after the heat treatment in an inert gas atmosphere or under reduced pressure The state is preferably amorphous, but may be partially crystallized.

[0059] Next, a conductive film is formed over the gate insulating layer 402 and the second oxide semiconductor layer 431.

[0060] The conductive film material is aluminum, chromium, tantalum, titanium, molybdenum, titanium. Elements selected from the group consisting of tin, tin, tin alloys, and tin alloys. Examples include alloys that combine elements.

[0061] In addition, when a heat treatment is performed after the conductive film is formed, the conductive film must be able to withstand the heat treatment. For example, the conductive film is made of only aluminum. However, it has problems such as poor heat resistance and susceptibility to corrosion, so it is recommended to combine it with a heat-resistant conductive material. The heat-resistant conductive material to be combined with aluminum is titanium, An element selected from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium or an alloy mainly composed of the above-mentioned metal elements, an alloy combining the above-mentioned elements, or or nitrides containing the above-mentioned elements as main components.

[0062] The second oxide semiconductor layer 431 and the conductive film are etched to form a third oxide semiconductor layer 432. , the source electrode and drain electrode layer 405 (the source electrode 405a and the drain electrode 40 5b) is formed (see FIG. 2C). Note that the third oxide semiconductor layer 432 is partially (but not completely) The metal plate has a groove (a recess) formed in the metal plate.

[0063] Next, the first protective insulating layer 407 is formed in contact with the third oxide semiconductor layer 432. The protective insulating layer 407 is resistant to moisture, hydrogen ions, and OH - etc. are reduced (i.e., this These external intrusions are not included, or even if they are included, they are rarely included. The insulating layer is formed by blocking the insulating layer and using an insulating inorganic material containing oxygen. Preferably, silicon oxynitride or silicon nitride oxide is used.

[0064] In this embodiment, the first protective insulating layer 407 is formed to a thickness of 30 A silicon oxide film of 0 nm is formed. The substrate temperature during the formation of the silicon oxide film is set to 300°C above room temperature. The temperature should be 100° C. or lower, and here it is 100° C. Silicon oxide film sputtering method The formation by is carried out under a rare gas (e.g., argon) atmosphere, an oxygen atmosphere, or a rare gas (e.g., The target and the mixture gas of oxygen and argon are used. A silicon oxide target or a silicon target may be used. By using a silicon target and performing sputtering in an oxygen-containing atmosphere, A silicon film can be formed.

[0065] A thin film is formed in contact with the third oxide semiconductor layer 432 by a sputtering method, a plasma CVD method, or the like. When a silicon oxide film is formed as the first protective insulating layer 407, the resistance of the third insulating film 407 is reduced. At least a region of the oxide semiconductor layer 432 in contact with the first protective insulating layer 407 is made of a high resistance material. Antibody (carrier concentration is reduced, preferably 1×10 18 / cm 3 (less than 10 ... A semiconductor region can be formed.

[0066] During the transistor manufacturing process, heating and slow cooling are performed in an inert gas atmosphere (or under reduced pressure). In addition, the carrier concentration of the third oxide semiconductor layer 432 is increased by forming an insulating oxide or the like. It is important to reduce the resistance of the third oxide semiconductor layer 432. The oxide semiconductor layer 403 has the above structure (see FIG. 2D).

[0067] Next, a conductive film is formed on the first protective insulating layer 407, and then a photolithography process is performed. Then, a resist mask is formed on the conductive film, and unnecessary portions are removed by etching. A second gate electrode layer 409 (including wiring formed from the same layer) is formed. When the gate electrode layer 409 is selectively etched to have a desired top surface shape, The protective insulating layer 407 functions as an etching stopper.

[0068] When the second gate electrode layer 409 is connected to the first gate electrode layer 401, Before forming a conductive film that will become the second gate electrode layer 409, a predetermined thickness of the first protective insulating layer 407 is An opening is formed in the region so as to expose the first gate electrode layer 401 .

[0069] The conductive film formed on the first protective insulating layer 407 is made of a metal material (aluminum, copper, Choose from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. One or more of the metal elements mentioned above, or an alloy mainly composed of the metal elements mentioned above When a film using these materials is formed to a sufficient thickness, it has a light-shielding effect. The oxide semiconductor layer 403 can be shielded from light.

[0070] In FIG. 1A, the width of the second gate electrode layer 409 is equal to that of the first gate electrode layer 401. The width of the second insulating layer 402 is larger than that of the oxide semiconductor layer 403. The width of the gate electrode layer 409 is set to be wider than that of the oxide semiconductor layer 403. The oxide semiconductor layer 403 is covered with the insulating film 409. The thin regions of the oxide semiconductor layer 403 are used as the source and drain electrodes. Since the transistor 471 is not covered with the electrode layer 405, the transistor 471 is turned on by light irradiation. For example, In-Ga formed by sputtering -Zn-O based non-single crystal film is sensitive to light with a wavelength of 450 nm or less, so the oxide semiconductor layer When using an In-Ga-Zn-O non-single crystal film for 403, the wavelength is particularly 450 nm or less. A second gate electrode layer 409 may be provided so as to block light.

[0071] In addition, here, the transistor 47 is The heat treatment may be performed on the substrate 1. The heat treatment is preferably performed at a temperature of 300° C. or less. It may be any time after forming the insulating film that will become the first protective insulating layer 407. For example, The heat treatment performed here is a heat treatment at 350° C. for 1 hour in a nitrogen atmosphere. By performing this process, the variation in the electrical characteristics of the transistor 471 can be reduced.

[0072] Through the above steps, the transistor 471 shown in FIG. can.

[0073] Note that the transistor used in this embodiment is not limited to the type shown in FIG. As shown in FIG. 1B, a planarization layer (e.g., a resin layer) is formed under the second gate electrode layer 409B. FIG. 1B shows a first gate electrode layer 401, a gate insulating layer 402, and a A first protective film covering the oxide semiconductor layer 403 and the source and drain electrode layers 405 is formed. 4 shows a configuration in which a resin layer 408 is formed between the protective insulating layer 407 and the second gate electrode layer 409B. If a resin layer is provided under the second gate electrode layer 409B, the structure below the resin layer can prevent the generation of the electric field. This can reduce the unevenness caused by the above-mentioned process, and flatten the surface on which the second gate electrode layer 409B is to be formed. In addition, the method is not limited to the resin layer, and other methods that can flatten the top surface (such as spin coating or lift coating) may be used. Alternatively, a method such as the Row method may be used.

[0074] In FIG. 1B, the same reference numerals are used for the parts other than those in FIG. 1A. .

[0075] The resin layer 408 is connected to the source electrode and drain electrode layers via the first protective insulating layer 407. The resin layer 408 covers the oxide semiconductor layer 405 and the oxide semiconductor layer 403 having a thin region. For example, a photosensitive or non-photosensitive organic material having a thickness of 0.5 μm to 3 μm may be used. Photosensitive or non-photosensitive organic materials that can be used for the resin layer 408 include is polyimide, acrylic, polyamide, polyimide amide, resist or benzosilane. Examples of the material include clobutene, and a laminate of these. The resin layer 408 is formed by applying photosensitive polyimide. After coating, exposure, development and baking are performed to obtain a 1.5μm thick polysilicon film with a flat surface. A resin layer 408 made of imide is formed.

[0076] By providing the resin layer 408, the unevenness caused by the structure of the transistor 471B is reduced. , can be made flat.

[0077] FIG. 1C shows a substrate 400 on which a transistor is provided and a first gate electrode layer 401C. A base insulating layer 410 is provided between the first gate electrode layer 401C and the second gate electrode The relationship between the widths of layers 409C shows a different configuration than in FIG.

[0078] In FIG. 1C, the same reference numerals are used for the parts other than those in FIG. 1A. .

[0079] The insulating base layer 410 is a silicon oxynitride or silicon oxynitride layer having a thickness of 50 nm to 200 nm. The substrate 400 can be made of silicon or silicon nitride. When the impurity elements (such as sodium) from the glass substrate are In particular, the impurity element is prevented from entering the oxide semiconductor layer 403. Furthermore, the formation of the first gate electrode layer 401C is prevented by the insulating base layer 410. In this way, the substrate 400 can be prevented from being etched during the etching process.

[0080] In addition, the transistor 471C is In all the gate electrodes, the width of the first gate electrode layer 401C and the width of the second gate electrode layer 409C are different. The channel length of the first gate electrode layer 401C of the transistor 471C shown in FIG. The length in the channel length direction is longer than the length of the oxide semiconductor layer 403 in the channel length direction. The length of the second gate electrode layer 409C of the transistor 471C in the channel length direction is As shown in FIG. 1(C), at least The length of the second gate electrode layer 409C in the channel length direction is equal to or smaller than the thickness of the thin region of the oxide semiconductor layer 403. The length of the second protective insulating layer 407 is longer than the length of the first protective insulating layer 408. It is possible to reduce the parasitic capacitance by reducing the length of the second gate electrode layer 409C. can.

[0081] Note that in FIGS. 1A to 1C, before the first protective insulating layer 407 is formed, The exposed thin region of the oxide semiconductor layer 403 may be subjected to oxygen radical treatment. By performing oxygen radical treatment, the exposed surface and its vicinity of the oxide semiconductor layer 403 are modified. Since it can be made into an oxygen excess region, it can be made into a high resistance region. Oxygen radicals The oxygen-containing gas may be supplied by a plasma generator, or an ozone generator may be used. The oxygen radicals or oxygen may be supplied by a generating device. As a result, the surface of the oxide semiconductor layer 403 (the surface of the back channel portion) can be modified. The method is not limited to oxygen radical treatment, and radical treatment using argon and oxygen may also be used. The argon and oxygen radical treatment is a plasma treatment using argon gas and oxygen gas. The purpose of this method is to generate a thin film and modify the surface.

[0082] In addition, in FIG. 1A to FIG. 1C, the second gate electrode layer is a light-transmitting conductive film. Conductive materials, such as indium oxide, including tungsten oxide Indium zinc oxide, indium oxide with titanium oxide, indium Indium tin oxide, indium tin oxide (ITO), indium zinc oxide, silicon oxide Alternatively, a light-transmitting conductive material such as indium tin oxide doped with ruthenium may be used.

[0083] Alternatively, in FIG. 1A to FIG. 1C, the second gate electrode layer may be formed of a light-transmitting conductive material. When a conductive material is used, the second gate electrode layer and the pixel electrode are made of the same material. The second gate electrode layer and the pixel electrode can be formed using the same photomask. By using the same material, the number of steps can be reduced. When the gate electrode layer is formed of a thin oxide semiconductor layer, a light shielding layer is used to shield the oxide semiconductor layer from light. It is preferable to provide a light-shielding layer at a position where the light-shielding layer overlaps the thin region of the oxide semiconductor layer. , at least in the wavelength range of 400 to 450 nm, light transmittance of less than about 50%, preferably 20% The light-shielding layer is formed of a material and with a thickness that provides a light transmittance of less than 100 nm. For example, the light-shielding layer is made of chromium. (Chromium oxide or chromium nitride may be used), metal such as titanium nitride, or black resin may be used. When using black resin to block light, the irradiated light is strong and Therefore, if the light-shielding layer needs to be thin, It is preferable to use a metal that has high mechanical properties and can be precisely etched and thinned.

[0084] In the above description, an example is given in which a two-tone photomask is used in a photolithography process. However, in the case where a multi-tone mask is used to form a plurality of (for example, a two-tone photomask is used, When a resist mask having regions of different thicknesses (two types in the case of This allows the number of steps to be reduced, simplifying the process and reducing costs. In this regard, for convenience, gray-tone exposure masks and half-tone exposure masks are collectively referred to as It is called a multi-tone mask. Note that the multi-tone mask is not limited to three-tone masks, and may be four-tone masks. Furthermore, the number of gradations may be increased.

[0085] Note that in the case where a multi-tone mask is used, an oxide semiconductor film and a conductive film are stacked. Then, a resist mask having a plurality of regions with different thicknesses is formed on the conductive film. The oxide semiconductor layer having a thin region and the source and drain electrodes are formed by using a mask. In this case, the ends of the source and drain electrode layers and the oxide semiconductor The ends of the first protective insulating layer 4 are approximately aligned, and the side surfaces of the oxide semiconductor layer are exposed. When forming the oxide semiconductor layer 07, the oxide semiconductor layer does not overlap with the source electrode and the drain electrode layer. Both the thin region and the side surface are in contact with the first protective insulating layer 407.

[0086] The semiconductor layer of the channel formation region of the transistor in this embodiment is a high resistance region. Since the temperature is within the range, the electrical characteristics of the transistor are stable and an increase in the off-current is prevented. Therefore, a display having transistors with good electrical characteristics and high reliability can be obtained. The display device may be a display device.

[0087] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0088] (Embodiment 2) This embodiment will describe a transistor that can be applied to a display device according to one embodiment of the present invention. A transistor different from that of the first embodiment and a method for manufacturing the same will be described. In such a display device, the transistor of the present embodiment is applied to at least a driving circuit portion. Use.

[0089] 4A and 4B each illustrate a cross-sectional view of a transistor according to one embodiment of the present invention. The transistor 472 is a bottom-gate transistor provided on the substrate 400. a first gate electrode layer 401, a gate insulating layer 402, and an oxide semiconductor layer 403, The semiconductor device further includes an n-type oxide semiconductor layer 404 and a source electrode and drain electrode layer 405. The first protective insulating layer 407 is in contact with and covers part of the oxide semiconductor layer 403. a second gate electrode provided over the first protective insulating layer 407 and overlapping with the oxide semiconductor layer 403; The first protective insulating layer 407 is called a second gate insulating layer. You can also do this.

[0090] Between the oxide semiconductor layer 403 and the source and drain electrode layers 405, a low-resistance n By providing the oxide semiconductor layer 404, the transistor 472 can operate more stably. This can be done.

[0091] First, a method for manufacturing the transistor 472 shown in FIG. 4A will be described with reference to FIGS. An example of the method is shown below.

[0092] A first gate electrode layer 401 is formed on a substrate 400 having an insulating surface. A process of forming a gate insulating layer 402 covering the gate electrode layer 401 and forming an oxide semiconductor film. Since the embodiment is the same as the first embodiment, detailed description is omitted here, and the same points as in FIG. The same reference numerals will be used in the following description.

[0093] A first oxide semiconductor film 433 is formed over the gate insulating layer 402 in a manner similar to that of Embodiment 1. do.

[0094] Next, a semiconductor layer functioning as a source region or a drain region was formed over the first oxide semiconductor film 433. A first n-type oxide semiconductor film 440 is formed (see FIG. 5A). The oxide semiconductor film 440 is an oxide semiconductor having a lower resistance than the first oxide semiconductor film 433. A membrane is used.

[0095] The first n-type oxide semiconductor film 440 is formed by, for example, sputtering in an atmosphere containing nitrogen gas. Metal oxides containing In (indium), Ga (gallium), and Zn (zinc) were prepared by the annealing method. Indium and gallium obtained using the compound (In2O3:Ga2O3:ZnO=1:1:1) , and zinc-containing oxide-nitride films, Al-Zn-O non-single crystal films, and nitrogen-containing A l-Zn-O type non-single crystal film, i.e., Al-Zn-ON type non-single crystal film (AZON film and (also called

[0096] In addition, the In-Ga-Zn-O based non-single crystal film used in this embodiment is amorphous. The crystal structure may be microcrystalline or polycrystalline, or may be single crystal. By changing the formation conditions and the composition ratio of the target, the first oxide semiconductor film 433 and the first n The crystal state of the type oxide semiconductor film 440 can be changed.

[0097] Therefore, depending on the formation conditions of the oxide semiconductor film and the composition ratio of the target, the source region and An n-type oxide semiconductor layer that will be the drain region and an oxide semiconductor layer 40 that will form the channel region The crystal state of 3 may be different. For example, n-type The oxide semiconductor layer may include microcrystals, and the oxide semiconductor layer 403 may be amorphous. The n-type oxide semiconductor layer serving as the drain region is amorphous, and the oxide semiconductor layer 4 03 may contain microcrystals.

[0098] Note that the first oxide semiconductor film 433 and the first n-type oxide semiconductor film 440 are exposed to the air. It may be formed continuously without contacting the air. This allows the interface to be exposed to atmospheric components and impurities suspended in the air, such as water and hydrocarbons. Since each layer interface can be formed without contamination, the variation in transistor characteristics is reduced. In addition, the thickness of the first n-type oxide semiconductor film 402 is 100 nm. Up to 40 may be formed consecutively.

[0099] Next, the first oxide semiconductor film 433 is subjected to heat treatment in a manner similar to that of Embodiment 1. The oxide semiconductor film 433 is subjected to heat treatment and gradual growth under an inert gas atmosphere or under reduced pressure. Cooling reduces the resistance (increases the carrier concentration, preferably 1×10 18 / cm 3 (End) Thus, the resistance of the oxide semiconductor film (second n-type oxide semiconductor film) can be reduced. .

[0100] The heat treatment of the first oxide semiconductor film 433 is performed in an inert gas atmosphere (nitrogen or helium The first oxide semiconductor film 433 is heated to 3000° C. for 10 minutes at 3 ... under a rare gas atmosphere (e.g., neon, argon, or the like) or under reduced pressure. By performing heat treatment under the above atmosphere, This can remove impurities such as hydrogen and water that are present in the gas.

[0101] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain impurities such as water and hydrogen. The purity of nitrogen or rare gases such as helium, neon, and argon is 6N (99.9999 %) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration of 1p pm or less, preferably 0.1 ppm or less).

[0102] In this embodiment, the electric furnace is configured to be capable of increasing the temperature at a rate of 0.1° C. / min to 20° C. / min. The inside of the chamber is filled with nitrogen or a rare gas atmosphere, and the temperature is 200°C to 600°C, preferably The first oxide semiconductor film 433 and the second oxide semiconductor film 434 formed over the substrate are heated at 400° C. or higher and 600° C. or lower. The first n-type oxide semiconductor film 440 is heated. The temperature is set to 00° C. or higher and 600° C. or lower, preferably 400° C. or higher and 600° C. or lower. The first oxide semiconductor film 433 and the first n-type oxide semiconductor film 440 are heated to form a second A first oxide semiconductor film and a second n-type oxide semiconductor film are formed.

[0103] After the heat treatment, the heater of the electric furnace is turned off and the chamber is cooled gradually. The electric furnace is preferably configured so that the temperature can be decreased at a rate of 0.1° C. / min to 15° C. / min. .

[0104] By carrying out the heat treatment as described above, the reliability of the transistor to be formed later can be improved. can be done.

[0105] Next, a resist mask (FIG. (not shown) is formed by a photolithography process, and an island-shaped second The n-type oxide semiconductor layer 431 and the second n-type oxide semiconductor layer 434 are then processed (FIG. 5B). (see ).

[0106] Note that, here, the oxide semiconductor film was processed after the heat treatment. After the film is processed, a heat treatment may be carried out.

[0107] Next, after removing the resist mask, a conductive film is formed on the second n-type oxide semiconductor layer 434. A film is formed.

[0108] The conductive film material is aluminum, chromium, tantalum, titanium, molybdenum, titanium. Elements selected from the group consisting of tin, tin, tin alloys, and tin alloys. Examples include alloys that combine elements.

[0109] In addition, when a heat treatment is performed after the conductive film is formed, the conductive film must be able to withstand the heat treatment. A conductive film having about the same degree of heat resistance is used.

[0110] Next, a photolithography process is performed to form a resist mask on the conductive film. The film is etched to form the source and drain electrode layers 405. A source electrode formed by the source electrode and drain electrode layer 405 using a mask. and the drain electrode (back channel portion), 34 is etched to form a second n-type oxide semiconductor layer which will become a source region and a drain region. Note that only a part of the second oxide semiconductor layer 431 is formed (see FIG. 5C). The third oxide semiconductor layer 432 is etched to have a groove (depression).

[0111] Next, silicon oxide or silicon nitride oxide is formed in contact with the third oxide semiconductor layer 432. The first protective insulating layer 407 is formed using an inorganic insulating film containing oxygen such as . As in the first embodiment, a first protective insulating layer 407 is formed to a thickness of 300 mm by sputtering. A silicon oxide film of nm is formed.

[0112] The first oxide semiconductor layer 432 having a low resistance is contacted with the first oxide semiconductor layer 432 by a sputtering method or a plasma C When the first protective insulating layer 407 is formed of silicon oxide by the VD method or the like, the resistance is reduced. In the third oxide semiconductor layer 432, at least a region in contact with the first protective insulating layer 407 High resistance (low carrier concentration, preferably 1×10 18 / cm 3 Less than 1000mV) and high resistance A compound oxide semiconductor region can be formed.

[0113] During the transistor manufacturing process, heating and slow cooling are performed in an inert gas atmosphere (or under reduced pressure). In addition, the carrier concentration of the third oxide semiconductor layer 432 is increased by forming an insulating oxide or the like. It is important to reduce the resistance of the third oxide semiconductor layer 432. The oxide semiconductor layer 403 has the above structure (see FIG. 5D).

[0114] The steps after the formation of the first protective insulating layer 407 are the same as those in the first embodiment. That is, a second gate electrode layer 409 is formed on a first protective insulating layer 407 .

[0115] Note that a resin layer may be provided on the second gate electrode layer 409. By providing a resin layer on the transistor 472, the unevenness caused by the structure of the transistor 472 can be reduced and made flat. Cut.

[0116] Then, the transistor 472 is subjected to a nitrogen atmosphere or an air atmosphere (in the air). Heat treatment may be performed. The heat treatment is preferably performed at a temperature of 300° C. or less. This can be done at any time after forming the insulating film that will become the protective insulating layer 407. For example, The heat treatment is performed at 350° C. for 1 hour. The variation in characteristics can be reduced.

[0117] Through the above steps, a transistor 472 shown in FIG. 4A can be obtained. Note that in the transistor 472, the first protective insulating layer 407 serves as a second gate insulating layer. It works like this.

[0118] FIG. 4B shows a first gate electrode layer 401, a gate insulating layer 402, and an oxide semiconductor layer 403, an n-type oxide semiconductor layer 404, and a source electrode and drain electrode layer 405. A resin layer 408 is formed between the covering first protective insulating layer 407 and the second gate electrode layer 409. Show the form.

[0119] The transistor 472B shown in FIG. 4B is only partially different from that shown in FIG. ), the same reference numerals will be used for the parts that are different from those in FIG. 4(A).

[0120] The resin layer 408 is connected to the source electrode and drain electrode layers via the first protective insulating layer 407. The resin layer 408 covers the oxide semiconductor layer 405 and the oxide semiconductor layer 403 having a thin region. For example, it is made of a photosensitive or non-photosensitive organic material having a thickness of 0.5 μm to 3 μm. Photosensitive or non-photosensitive organic materials include polyimide, acrylic, polyimide, and polyimide. Polyamide, polyimide amide, resist or benzocyclobutene, or a combination of these Here, the resin layer 408 is formed by layering a photosensitive After the polyimide is applied to the entire surface, it is exposed to light, developed, and Then, the resin layer 408 made of polyimide having a flat surface and a thickness of 1.5 μm is formed. Form.

[0121] By providing the resin layer 408, the unevenness caused by the structure of the transistor 472B is reduced. , can be made flat.

[0122] As shown in FIG. 4A, the width of the second gate electrode layer 409 is set to be equal to that of the first gate electrode layer The width of the second gate electrode layer 401 is made wider than the width of the oxide semiconductor layer 403. The oxide semiconductor layer 403 can be shielded from light by the gate electrode layer 409. A gate voltage can be applied to the entire oxide semiconductor layer 403 from the gate electrode 9 .

[0123] In addition, even in the structure shown in FIG. 4(A) or the structure shown in FIG. 4(B), the first protective insulating layer When the laminated portion of the second gate electrode layer 409 and the resin layer 408 is thin, Parasitic capacitance between the source electrode and the drain electrode layer 405 can be a problem. If this is a problem, the width of the second gate electrode layer 409 is narrowed to reduce the width of the second gate electrode layer 409. It is preferable to reduce the area where the source and drain electrode layers 405 overlap with the first electrode layer 409. By reducing the overlapping area, the parasitic capacitance can be reduced.

[0124] In addition, the laminated portion of the resin layer 408 and the first protective insulating layer 407 is sufficiently thick, and the parasitic capacitance If this is not a problem, the second gate electrode may be a common gate electrode that covers multiple transistors of the driving circuit. The area of ​​the second gate electrode is set to be approximately the same as that of the driving circuit or It may be more than that.

[0125] In the above description, an example is shown in which a two-tone photomask is used in the photolithography process. However, when a multi-tone mask is used, a multi-tone photomask (for example, a two-tone photomask) is used, When a resist mask having regions of different thicknesses (two types in the case of This allows the number of parts to be reduced, simplifying the process and reducing costs.

[0126] When a multi-tone mask is used, a two-layered oxide semiconductor film and a conductive film are stacked. After the conductive film is formed, a resist mask having a plurality of regions with different thicknesses is formed on the conductive film. The resist mask is used to form an oxide semiconductor layer having a thin region, a source electrode, and In this case, the ends of the source electrode layer and the drain electrode layer are bonded to the oxide. The ends of the first protective layer are aligned, and the side surfaces of the oxide semiconductor layer are exposed. When the protective insulating layer 407 is formed, the oxide semiconductor layer is used as the source electrode layer and the drain electrode layer. The region (thin region) that does not overlap with the first protective insulating layer 407 and the side surfaces are both in contact with the first protective insulating layer 407. do.

[0127] The semiconductor layer in the channel formation region of the transistor of this embodiment is a high resistance region. Therefore, the electrical characteristics of the transistor are stabilized, and an increase in off-state current can be prevented. Therefore, a semiconductor device (display) having a transistor with good electrical characteristics and high reliability can be manufactured. It is possible to make it into a device.

[0128] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0129] (Embodiment 3) This embodiment will describe a transistor that can be applied to a display device according to one embodiment of the present invention. A transistor different from that of the first embodiment and the second embodiment and a manufacturing method thereof will be described. In the display device according to one embodiment of the present invention, at least the driver circuit portion includes The transistor is applied.

[0130] 6A and 6B are cross-sectional views of a transistor according to one embodiment of the present invention. The transistor 473 is a bottom-gate transistor provided over the substrate 400. a first gate electrode layer 401, a gate insulating layer 402, and an oxide semiconductor layer 403, The source and drain electrode layers 405 (source electrode 405a and drain electrode 405 b) and a channel protection layer 406. The first gate electrode layer 401, the gate insulating layer 402, the oxide semiconductor layer 403, and the source electrode a first protective insulating layer 407 covering the first and drain electrode layers 405; A second gate electrode layer 409 overlapping with the oxide semiconductor layer 403 is provided over the gate electrode layer 407. That is, the transistor 473 described in this embodiment is a channel-stop type. do.

[0131] First, the fabrication of the transistor 473 shown in FIG. 6A will be described with reference to FIGS. 7A to 7D. An example of the manufacturing method is shown below.

[0132] A first gate electrode layer 401 is formed on a substrate 400 having an insulating surface. A process of forming a gate insulating layer 402 covering the gate electrode layer 401 and forming an oxide semiconductor film Since the embodiment is the same as the first embodiment, detailed description is omitted here. In the following description, the same reference numerals will be used to refer to the same parts.

[0133] A first oxide semiconductor film is formed over the gate insulating layer 402 in a manner similar to that in Embodiment 1.

[0134] Next, a photolithography process is performed, and a resist mask is formed over the first oxide semiconductor film. The first oxide semiconductor film is then etched to form an island-shaped first oxide semiconductor layer 430. The etching method is not limited to wet etching, but may be dry etching. A spooling may be used (see FIG. 7(A)).

[0135] Next, the first oxide semiconductor layer 430 is subjected to heat treatment in a manner similar to that of Embodiment 1. The oxide semiconductor layer 430 is subjected to heat treatment in an inert gas atmosphere or under reduced pressure and then gradually cooled. This reduces the resistance (increases the carrier concentration, preferably to 1×10 18 / cm 3 That's all) As a result, the second oxide semiconductor layer 431 can have low resistance.

[0136] The heat treatment of the first oxide semiconductor layer 430 is performed in an inert gas atmosphere (nitrogen or helium The first oxide semiconductor layer 430 is heated to 1000° C. for 1 hour and then cooled to 100° C. for 1 hour. By performing heat treatment under the above atmosphere, This can remove impurities such as hydrogen and water that are present in the gas.

[0137] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain impurities such as water and hydrogen. The purity of nitrogen or rare gases such as helium, neon, and argon is 6N (99.9999 %) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration of 1pp m or less, preferably 0.1 ppm or less).

[0138] In this embodiment, the electric furnace is configured to be capable of increasing the temperature at a rate of 0.1° C. / min to 20° C. / min. The inside of the chamber is filled with nitrogen or a rare gas atmosphere, and the temperature is 200°C to 600°C, preferably The film was formed on the substrate in a heated chamber at 400°C to 600°C. The first oxide semiconductor layer 430 is heated to 200° C. under reduced pressure by exhaust means. The temperature is set to 400° C. or higher and 600° C. or lower, preferably 400° C. or higher and 600° C. or lower. The first oxide semiconductor layer 430 is heated to form the second oxide semiconductor layer 431.

[0139] After the heat treatment, turn off the heater of the electric furnace and allow the chamber to cool gradually. The electric furnace is preferably configured to be capable of lowering the temperature at a rate of 0.1° C. / min to 15° C. / min. I wish.

[0140] By carrying out the heat treatment as described above, the reliability of the transistor to be formed later can be improved. can be done.

[0141] Next, an insulating film to be a channel protective layer is formed in contact with the second oxide semiconductor layer 431. The insulating film to be a channel protective layer formed in contact with the second oxide semiconductor layer is resistant to moisture, hydrogen, and the like. ions, and OH - The above are reduced, blocking the intrusion of these substances from the outside, and the oxygen-containing Specifically, the insulating layer is formed using an insulating inorganic material such as silicon oxide, silicon oxynitride, or The insulating film that serves as the channel protection layer is formed of silicon oxynitride. The first protective insulating layer 407 may be formed in a similar manner to the first protective insulating layer 407 described in the first embodiment.

[0142] In this embodiment, the insulating film that becomes the channel protection layer is formed by sputtering to a thickness of A silicon oxide film of 300 nm is formed. The substrate temperature during the formation is set to be above room temperature and below 300°C. The temperature is set to 100° C. in this example. The silicon oxide film is formed by sputtering. , in a rare gas (e.g., argon) atmosphere, in an oxygen atmosphere, or in a rare gas (e.g., argon) atmosphere The target is silicon oxide and oxygen. A cone target or a silicon target may be used. For example, a silicon target A silicon oxide film is formed by sputtering in an atmosphere containing oxygen using a silicon oxide film. This can be done.

[0143] A thin film is formed on the second oxide semiconductor layer 431 by a sputtering method, a plasma CVD method, or the like. When the insulating film that serves as the channel protection layer is formed with silicon oxide, the resistance of the second oxide film is reduced. At least the region of the compound semiconductor layer 431 that contacts the insulating film that serves as the channel protection layer is made to have a high resistance. Antigen (lower carrier concentration, preferably 1×10 18 / cm 3 (less than 100%) and high resistance oxidation A semiconductor region can be formed.

[0144] During the transistor manufacturing process, heating and slow cooling are performed in an inert gas atmosphere (or under reduced pressure). and increasing or decreasing the carrier concentration of the oxide semiconductor layer by forming an insulating oxide or the like. The second oxide semiconductor layer 431 is an oxide semiconductor layer having a high resistance oxide semiconductor region. This forms the organic semiconductor layer 403 .

[0145] Next, a photolithography process is performed to form a resist film on the insulating film that will become the channel protection layer. A mask is formed, and unnecessary portions are removed by etching to form a channel protection layer 406. The first gate electrode layer 401 is formed to have a width (length in the channel length direction) of the channel protection layer 406. It is preferable that the width of the gap is larger than the width of the gap (see FIG. 7(B)).

[0146] Next, the resist mask is removed, and then the second oxide semiconductor layer 431 and the channel protection layer are A conductive film is formed on the protective layer 406 .

[0147] The conductive film material is aluminum, chromium, tantalum, titanium, molybdenum, titanium. Elements selected from the group consisting of tin, tin, tin alloys, and tin alloys. Examples include alloys that combine elements.

[0148] In addition, when a heat treatment is performed after the conductive film is formed, the conductive film must be able to withstand the heat treatment. A conductive film having about the same degree of heat resistance is used.

[0149] Next, a photolithography process is performed to form a resist mask on the conductive film. The film is etched to form the source and drain electrode layers 405 (source electrodes 405a and In this etching, the channel protection layer 406 is Since it functions as an etching stopper for the oxide semiconductor layer 403, 3 is not etched.

[0150] A channel protection layer 406 is provided in contact with a channel formation region of the oxide semiconductor layer 403. Since the oxide semiconductor layer 403 has such a structure, the channel formation region of the oxide semiconductor layer 403 is not damaged during the process. This prevents damage (film loss and oxidation caused by plasma and etching agents during etching, etc.) Therefore, the reliability of the transistor 473 can be improved.

[0151] Next, on the source electrode and drain electrode layer 405 and the channel protection layer 406, A first protective insulating layer 407 is formed. The first protective insulating layer 407 is resistant to moisture, hydrogen ions, and Yobi OH -The intrusion of these substances from the outside is reduced, and insulating non- The insulating layer is formed using a material such as silicon oxide, silicon nitride, or silicon oxynitride. , silicon oxide nitride, aluminum oxide, aluminum nitride, magnesium oxide, iridium oxide Examples of these include tritium oxide, hafnium oxide, and tantalum oxide (see Figure 7(D)). .

[0152] The steps after the formation of the first protective insulating layer 407 are the same as those in the first embodiment. That is, a second gate electrode layer 409 is formed on a first protective insulating layer 407 .

[0153] Note that a resin layer may be provided over the second gate electrode layer 409. By providing a resin layer on the transistor 473, the unevenness caused by the structure of the transistor 473 can be reduced and the transistor 473 can be made flat. Cut.

[0154] Note that the transistor 473 is applied in a nitrogen atmosphere or in an air atmosphere (in air). Heat treatment may be performed. The heat treatment is preferably performed at a temperature of 300° C. or less to maintain the channel. For example, the heating may be performed at 350° C. for 1 hour in a nitrogen atmosphere. When the heat treatment is performed, the variation in the electrical characteristics of the transistor 473 is reduced. can be alleviated.

[0155] Through the above steps, a transistor 473 shown in FIG. 6A can be obtained. Note that in the transistor 473, the channel protection layer 406 and the first protective insulating layer 407 are The laminated portion functions as a second gate insulating layer.

[0156] The transistor 473B shown in FIG. 6B is only partially different from that shown in FIG. 6(A) will be described using the same reference numerals as in FIG. 6(A).

[0157] FIG. 6B shows a first gate electrode layer 401, a gate insulating layer 402, and an oxide semiconductor layer 403, a first protective insulating layer 407 covering the source and drain electrode layers 405, In this embodiment, a resin layer 408 is formed between second gate electrode layers 409 .

[0158] The resin layer 408 is connected to the source electrode and drain electrode layers via the first protective insulating layer 407. The resin layer 408 covers the insulating layer 405 and the channel protection layer 406. The resin layer 408 has a thickness of, for example, 0.5 μm. It can be made of photosensitive or non-photosensitive organic materials with a thickness of 1.5 μm to 3 μm. Non-photosensitive organic materials include polyimide, acrylic, polyamide, polyimide amide, Examples of the resist include resist, benzocyclobutene, and a laminate of these. Here, the resin layer 408 is formed by applying photosensitive polyimide. After coating the entire surface with polyimide, it is exposed to light, developed, and baked to make the surface flat. Then, a resin layer 408 made of polyimide having a thickness of 1.5 μm is formed.

[0159] By providing the resin layer 408, the unevenness caused by the structure of the transistor 473B is reduced. , can be made flat.

[0160] As shown in FIG. 6A, the width of the second gate electrode layer 409 is set to be equal to that of the first gate electrode layer The width of the second gate electrode layer 401 is made wider than the width of the oxide semiconductor layer 403. A gate voltage can be applied from 409 to the entire oxide semiconductor layer 403 .

[0161] In addition, even in the structure shown in FIG. 6(A) or the structure shown in FIG. 6(B), the channel protection layer 4 06, when the portion where the first protective insulating layer 407 and the resin layer 408 are laminated is thin, The parasitic capacitance between the gate electrode layer 409 and the source and drain electrode layers 405 is a problem. If parasitic capacitance becomes a problem, the width of the second gate electrode layer 409 may be set to be smaller than that of the first gate electrode layer 409. The width of the second gate electrode layer 409 and the source electrode and It is preferable to reduce the overlapping area between the drain electrode layer 405 and the gate insulating layer 406. In addition, the width of the first gate electrode layer 401 is set to a value smaller than that of the channel protection layer 402. The width of the second gate electrode layer 409 is set to be narrower than the width of the channel protection layer 406. By making the width narrower than that of the source and drain electrode layers 405, The parasitic capacitance may be further reduced by using the above-mentioned configuration.

[0162] In addition, the laminated portion of the resin layer 408 and the first protective insulating layer 407 is sufficiently thick, and the parasitic capacitance If this is not a problem, the second gate electrode may be a common gate electrode that covers multiple transistors of the driving circuit. The area of ​​the second gate electrode is set to be approximately the same as that of the driving circuit or It may be more than that.

[0163] The semiconductor layer in the channel formation region of the transistor of this embodiment is a high resistance region. Therefore, the electrical characteristics of the transistor are stabilized, and an increase in off-state current can be prevented. Therefore, a semiconductor device (display) having a transistor with good electrical characteristics and high reliability can be manufactured. It is possible to make it into a device.

[0164] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0165] (Embodiment 4) This embodiment will describe a transistor that can be applied to a display device according to one embodiment of the present invention. A transistor different from that of the first to third embodiments and a manufacturing method thereof will be described. In the display device according to one embodiment of the present invention, at least the driver circuit portion includes the Apply a transistor.

[0166] 8A and 8B are cross-sectional views of a transistor according to one embodiment of the present invention. The transistor 474 is a bottom-gate transistor provided on the substrate 400. a first gate electrode layer 401, a gate insulating layer 402, and an oxide semiconductor layer 403, The n-type oxide semiconductor layer 404a, the n-type oxide semiconductor layer 404b, and the source electrode and the drain electrode A channel electrode layer 405 (a source electrode 405a and a drain electrode 405b) and a channel protection layer 406. Furthermore, a first protective insulating layer is provided in contact with and covers the channel protective layer 406. A second gate insulating layer 407 is formed on the first protective insulating layer 407 so as to overlap the oxide semiconductor layer 403. That is, the second electrode layer 409 is provided on the second transistor 4 described in this embodiment. 74 is a channel stop type.

[0167] First, the fabrication of the transistor 474 shown in FIG. An example of the manufacturing method is shown below.

[0168] A first gate electrode layer 401 is formed on a substrate 400 having an insulating surface. A process of forming a gate insulating layer 402 covering the gate electrode layer 401 and forming an oxide semiconductor film Since the embodiment is the same as the third embodiment, detailed description is omitted here. In the following description, the same reference numerals will be used to refer to the same parts.

[0169] A first oxide semiconductor film 433 is formed over the gate insulating layer 402 in a manner similar to that of Embodiment 1. do.

[0170] Next, the first oxide semiconductor film 433 is subjected to heat treatment in a manner similar to that of Embodiment 1. The oxide semiconductor film 433 is subjected to heat treatment in an inert gas atmosphere or under reduced pressure and then gradually cooled. This reduces the resistance (increases the carrier concentration, preferably to 1×10 18 / cm 3 That's all) As a result, the second oxide semiconductor film can have low resistance.

[0171] The heat treatment of the first oxide semiconductor film 433 is performed in an inert gas atmosphere (nitrogen or helium The first oxide semiconductor film 433 is heated to 3000° C. for 10 minutes at 3 ... under a rare gas atmosphere (e.g., neon, argon, or the like) or under reduced pressure. By performing heat treatment under the above atmosphere, This can remove impurities such as hydrogen and water that are present in the gas.

[0172] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain impurities such as water and hydrogen. The purity of nitrogen or rare gases such as helium, neon, and argon is 6N (99.9999 %) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration of 1pp m or less, preferably 0.1 ppm or less).

[0173] In this embodiment, the electric furnace is configured to be capable of increasing the temperature at a rate of 0.1° C. / min to 20° C. / min. The inside of the chamber is filled with nitrogen or a rare gas atmosphere, and the temperature is 200°C to 600°C, preferably The film was formed on the substrate in a heated chamber at 400°C to 600°C. The first oxide semiconductor film 433 is heated.

[0174] After the heat treatment, turn off the heater of the electric furnace and allow the chamber to cool gradually. The electric furnace is preferably configured to be capable of lowering the temperature at a rate of 0.1° C. / min to 15° C. / min. I wish.

[0175] By carrying out the heat treatment as described above, the reliability of the transistor to be formed later can be improved. can be done.

[0176] Next, an insulating film to be a channel protective layer is formed in contact with the second oxide semiconductor film. The insulating film that becomes the channel protection layer formed in contact with the oxide semiconductor film of 2 is resistant to moisture, hydrogen ions, , and O.H. - The intrusion of oxygen and other foreign matter is reduced, and the insulation The insulating film is formed using a conductive inorganic material. Specifically, the insulating film is a silicon oxide film or a silicon nitride oxide film. is used.

[0177] In this embodiment, the insulating film that becomes the channel protection layer is formed by sputtering to a thickness of A silicon oxide film of 300 nm is formed. The substrate temperature during the formation is set to be above room temperature and below 300°C. The temperature is set to 100° C. in this example. The silicon oxide film is formed by sputtering. , in a rare gas (e.g., argon) atmosphere, in an oxygen atmosphere, or in a rare gas (e.g., argon) atmosphere The target is silicon oxide and oxygen. A cone target or a silicon target may be used. For example, a silicon target A silicon oxide film is formed by sputtering in an atmosphere containing oxygen using a silicon oxide film. This can be done.

[0178] An oxide semiconductor film is formed on the second oxide semiconductor film by sputtering or plasma CVD. When an insulating film that serves as a channel protection layer is formed using silicon oxide, the second oxide semiconductor with low resistance is formed. In the conductive film, at least the region in contact with the insulating film that becomes the channel protection layer is made highly resistive (carry The concentration of a is reduced, preferably to 1×10 18 / cm 3 (less than 1000 nm) and the high resistance oxide semiconductor region can be formed.

[0179] During the transistor manufacturing process, heating and slow cooling are performed in an inert gas atmosphere (or under reduced pressure). and increasing or decreasing the carrier concentration of the oxide semiconductor layer by forming an insulating oxide or the like. The second oxide semiconductor film is a third oxide semiconductor film having a high resistance oxide semiconductor region. This results in a semiconductor film.

[0180] Next, a photolithography process is performed to form a resist film on the insulating film that will become the channel protection layer. A mask is formed, and unnecessary portions are removed by etching to form a channel protection layer 406. The first gate electrode layer 401 is formed to have a width (length in the channel length direction) of the channel protection layer 406. It is preferable that the width is wider than the width (width).

[0181] Next, a source region or a drain region is formed on the third oxide semiconductor film and the channel protection layer 406. An n-type oxide semiconductor film is formed to function as a drain region. In addition, a film having a lower resistance than the third oxide semiconductor film can be used.

[0182] The n-type oxide semiconductor film is formed by sputtering in an atmosphere containing nitrogen gas. Metal oxides containing indium, gallium, and zinc (InO 3: Indium, gallium, and zinc obtained using Ga2O3:ZnO=1:1:1) Nitrogen-containing oxynitride films, Al-Zn-O-based non-single crystal films, and nitrogen-containing Al-Zn-O-based Using a non-single crystal film, i.e., an Al-Zn-ON type non-single crystal film (also called an AZON film), Good too.

[0183] In addition, the In-Ga-Zn-O based non-single crystal film used in this embodiment is amorphous. The crystal structure may be, but is not limited to, microcrystalline or polycrystalline. Alternatively, the crystal structure may be, but is not limited to, single crystal. By changing the formation conditions and the composition ratio of the target, the third oxide semiconductor The crystal state of the film and the n-type oxide semiconductor film changes.

[0184] Therefore, depending on the formation conditions of the oxide semiconductor film and the composition ratio of the target, the source region and An n-type oxide semiconductor film that serves as a drain region and a third oxide semiconductor that serves as a channel region. The crystalline state of the film may be different. For example, n-type The oxide semiconductor film may include microcrystals, and the third oxide semiconductor film may be amorphous. The n-type oxide semiconductor film serving as the gate region and the drain region is amorphous, and the third oxide semiconductor The body membrane may contain microcrystals.

[0185] Next, a photolithography process is performed to form a resist mask on the n-type oxide semiconductor film. Then, unnecessary portions of the n-type oxide semiconductor film and the third oxide semiconductor film are removed by etching. Then, an oxide semiconductor layer 403 is formed (see FIG. 9B).

[0186] The present invention is not limited to the above description, and may be modified by forming a resist mask on the insulating film that serves as the channel protection layer. Then, the insulating film that becomes the channel protection layer and the unnecessary portion of the third oxide semiconductor film are removed by etching. The resist mask is then reduced in size, and an insulating film that becomes a channel protection layer is formed by etching. The unnecessary portion of the channel may be further removed to form a channel protection layer 406. The resist mask that is first formed on the insulating film that will become the channel protection layer is a multi-tone mask. Preferably, the resist mask has a plurality of regions of different thickness formed thereon.

[0187] Next, after the resist mask is removed, a conductive film is formed over the n-type oxide semiconductor film.

[0188] The conductive film material is aluminum, chromium, tantalum, titanium, molybdenum, titanium. Elements selected from the group consisting of tin, tin, tin alloys, and tin alloys. Examples include alloys that combine elements.

[0189] In addition, when a heat treatment is performed after the conductive film is formed, the conductive film must be able to withstand the heat treatment. A conductive film having about the same degree of heat resistance is used.

[0190] Next, a photolithography process is performed to form a resist mask on the conductive film. The film is etched to form the source and drain electrode layers 405 .

[0191] Then, the source and drain electrodes of the n-type oxide semiconductor film are formed using the same resist mask. The area sandwiched between the source and drain electrodes formed by the electrode layer 405 is etched. The n-type oxide semiconductor layer 404 that becomes the source region and the drain region is formed by removing the n-type oxide semiconductor layer 404 by etching. Complete.

[0192] A low-resistance n-type oxide is provided between the oxide semiconductor layer 403 and the source and drain electrode layers 405. By providing the nitride semiconductor layer 404, the transistor 474 can be operated stably.

[0193] In this etching, the channel protection layer 406 is etched by etching the oxide semiconductor layer 403. Since the oxide semiconductor layer 403 functions as an etching stopper, the oxide semiconductor layer 403 is not etched. The channel protection layer 406 is formed during a process for forming a channel in the oxide semiconductor layer 403. Prevents damage caused by plasma and etching agents during etching (film reduction, oxidation, etc.) Therefore, the reliability of the transistor 474 can be improved (see FIG. 9). See (C).

[0194] Next, on the source electrode and drain electrode layer 405 and the channel protection layer 406, A first protective insulating layer 407 is formed (see FIG. 9(D)). The first protective insulating layer 407 is Water, hydrogen ions, and OH - These external intrusions are blocked. The insulating layer is formed using an insulating inorganic material containing oxygen. Specifically, silicon oxide, silicon nitride, Silicon oxide nitride, silicon oxide nitride, aluminum oxide, aluminum nitride, oxide Examples include magnesium oxide, yttrium oxide, hafnium oxide, and tantalum oxide. .

[0195] The steps after the formation of the first protective insulating layer 407 are the same as those in the first embodiment. That is, a second gate electrode layer 409 is formed on a first protective insulating layer 407 .

[0196] Note that a resin layer may be provided on the second gate electrode layer 409. By providing a resin layer on the transistor 474, the unevenness caused by the structure of the transistor 474 can be reduced and the transistor 474 can be made flat. Cut.

[0197] Note that the transistor 474 is applied in a nitrogen atmosphere or in an air atmosphere (in the air). Heat treatment may be performed. The heat treatment is preferably performed at a temperature of 300° C. or less to maintain the channel. For example, the heating may be performed at 350° C. for 1 hour in a nitrogen atmosphere. The heat treatment is performed between the first and second electrodes. The heat treatment reduces the variation in the electrical characteristics of the transistor 474. It can be reduced.

[0198] Through the above steps, a transistor 474 shown in FIG. 8A can be obtained. In the transistor 474, the channel protection layer 406 and the first protective insulating layer 407 are The laminated portion functions as a second gate insulating layer.

[0199] Note that the transistor 474B in FIG. 8B is only partially different from that in FIG. In FIG. 8(B), the same reference numerals are used for the parts that are different from those in FIG. 8(A).

[0200] FIG. 8B shows a first gate electrode layer 401, a gate insulating layer 402, and an oxide semiconductor layer 403, an n-type oxide semiconductor layer 404, and a source electrode and drain electrode layer 405. A resin layer 408 is formed between the covering first protective insulating layer 407 and the second gate electrode layer 409. Show the form.

[0201] The resin layer 408 is connected to the source electrode and drain electrode layers via the first protective insulating layer 407. The resin layer 408 covers the insulating layer 405 and the channel protection layer 406. The resin layer 408 has a thickness of, for example, 0.5 μm. It can be made of photosensitive or non-photosensitive organic materials with a thickness of 1.5 μm to 3 μm. Non-photosensitive organic materials include polyimide, acrylic, polyamide, polyimide amide, Examples include resist, benzocyclobutene, and a laminate of these. Here, the resin layer 408 is formed by coating photosensitive polyimide. After coating the entire surface with polyimide, it is exposed to light, developed and baked to make the surface flat. A resin layer 408 made of polyimide is formed to a thickness of 1.5 μm.

[0202] By providing the resin layer 408, the unevenness caused by the structure of the transistor 474B is reduced. , can be made flat.

[0203] As shown in FIG. 8A, the width of the second gate electrode layer 409 is set to be equal to that of the first gate electrode layer The width of the second gate electrode layer 401 is made wider than the width of the oxide semiconductor layer 403. A gate voltage can be applied from 409 to the entire oxide semiconductor layer 403 .

[0204] In addition, even in the structure shown in FIG. 8(A) or the structure shown in FIG. 8(B), the channel protection layer 4 06, when the portion where the first protective insulating layer 407 and the resin layer 408 are laminated is thin, The parasitic capacitance between the gate electrode layer 409 and the source and drain electrode layers 405 is a problem. If parasitic capacitance becomes a problem, the width of the second gate electrode layer 409 may be set to be smaller than that of the first gate electrode layer 409. The width of the gate electrode layer 401 is narrower than that of the source electrode and drain electrode layer 405. It is preferable to reduce the overlapping area. By reducing the overlapping area, the parasitic capacitance can be reduced. Furthermore, the width of the first gate electrode layer 401 can be made narrower than the width of the channel protection layer 406. By making the width of the second gate electrode layer 409 narrower than the width of the channel protection layer 406, The parasitic capacitance is further reduced by not overlapping the source electrode layer or the drain electrode layer. You may do so.

[0205] In addition, the laminated portion of the resin layer 408 and the first protective insulating layer 407 is sufficiently thick, and the parasitic capacitance If this is not a problem, the second gate electrode may be a common gate electrode that covers multiple transistors of the driving circuit. The area of ​​the second gate electrode is set to be approximately the same as that of the driving circuit or It may be more than that.

[0206] The semiconductor layer in the channel formation region of the transistor of this embodiment is a high resistance region. Therefore, the electrical characteristics of the transistor are stabilized, and an increase in off-state current can be prevented. Therefore, a semiconductor device (display) having a transistor with good electrical characteristics and high reliability can be manufactured. It is possible to make it into a device.

[0207] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0208] (Embodiment 5) In this embodiment, an inverter circuit of a driving circuit using two n-channel transistors is An example of the structure of the transistor in FIG. 10A is the same as that in FIG. 1A of Embodiment 1. ) and the like, the same parts are denoted by the same reference numerals. The n-type oxide semiconductor layer 14a and the n-type oxide semiconductor layer 14b are the same as those in the embodiment. The resin layer 17 is the same as the n-type oxide semiconductor layer 404 of the first embodiment. 8, and the first protective insulating layer 18 is the same as the first protective insulating layer 407 in the first embodiment. The second gate electrode layer 470 has the same structure as the second gate electrode layer 409 in the first embodiment. It seems that.

[0209] The driver circuit for driving the pixel section is composed of an inverter circuit, a capacitor, a resistor, etc. When two n-channel transistors are combined to form an inverter circuit, A combination of enhancement and depletion type transistors In the case of EDMOS circuits, the other is formed by enhancement type transistors. In some cases, the EEMOS circuit is used (hereinafter referred to as EEMOS circuit).

[0210] FIG. 10(A) shows a cross-sectional structure of an inverter circuit of a driving circuit. The first transistor 20 and the second transistor 43 are inverse staggered channel etch type transistors. A wiring is provided on the oxide semiconductor layer through a source region or a drain region. This is an example of a transistor that is being used.

[0211] In FIG. 10A, a first gate electrode 11 and a third gate electrode 4 are formed on a substrate 10. The material of the first gate electrode 11 and the third gate electrode 42 is molybdenum. Butan, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium or The material is a single layer made of metals such as scandium or alloys that contain these as the main components. Alternatively, the film may be formed by laminating.

[0212] On the first gate insulating layer 13 covering the first gate electrode 11 and the third gate electrode 42 First, an oxide semiconductor layer 16 and a second oxide semiconductor layer 47 are provided.

[0213] On the oxide semiconductor layer 16, an electrode layer (source electrode layer 15a) which becomes a first terminal and a second terminal An electrode layer (drain electrode layer 15b) serving as a second terminal is provided, and an electrode layer serving as a first terminal is provided. The third gate electrode 42 is directly connected to the gate insulating layer 13 through a contact hole 44 formed in the gate insulating layer 13. An electrode layer which serves as a third terminal 411 is provided on the second oxide semiconductor layer 47.

[0214] The transistor 20 includes a first gate electrode 11 and a first A gate insulating layer 13 and an oxide film overlapping the first gate electrode 11 via the first gate insulating layer 13. The first terminal (the source electrode layer 15a) has a negative potential. This power line is the power line (negative power line) to which the voltage VDL is applied. However, in the inverter circuit, the electrode layer ( Depending on the potential of the wiring connected to the drain electrode layer 15b), the electrode layer serving as the first terminal may be In some cases, the electrode layer that is to be the first terminal may be the drain electrode layer, and the electrode layer that is to be the second terminal may be the source electrode layer.

[0215] The second transistor 43 is connected to a third gate electrode 42 via a first gate insulating layer 13. and a second oxide semiconductor layer 47 overlapping the third gate electrode 42. is the power supply line (positive power supply line) to which a positive voltage VDH is applied. In this case, the potential of the wiring connected to the electrode layer (drain electrode layer 15b) serving as the second terminal is In this case, the electrode layer that becomes the second terminal becomes the source electrode layer, and the electrode layer that becomes the third terminal 411 becomes the drain electrode layer. In some cases, the insulating layer may be an insulating electrode layer.

[0216] Here, the buffer layer 4 is provided between the second oxide semiconductor layer 47 and the drain electrode layer 15b. 08a (also referred to as a source region or a drain region), and the second oxide semiconductor layer 47 Between the third terminal 411, a buffer layer 408b (also called a drain region or a source region) is provided. ) shall be established.

[0217] A top view of the inverter circuit of the driver circuit is shown in FIG. The cross section taken along line Z1-Z2 corresponds to FIG.

[0218] In order to make the transistor 20 an enhancement type n-channel transistor, In this embodiment, a second gate insulating layer is formed on the oxide semiconductor layer 16, and A second gate electrode 19 is provided on the second gate electrode 19, and a transistor is formed by applying a voltage to the second gate electrode 19. The threshold voltage of the transistor 20 is adjusted.

[0219] In addition, in FIG. 10(A) and FIG. 10(B), the electrode layer that becomes the second terminal (the drain electrode layer 15b) is connected to the third gate electrode through a contact hole 44 formed in the first gate insulating layer 13. Although an example in which the gate electrode 42 is directly connected to the first electrode 41 has been shown, this is not particularly limited, and a connecting electrode may be provided separately to connect the first electrode 41 to the second electrode 42. The electrode layer (drain electrode layer 15b) serving as the second terminal and the third gate electrode 42 are connected via a connection electrode. Alternatively, the connection may be made as above.

[0220] This embodiment mode can be freely combined with any of the first to fourth embodiment modes.

[0221] (Embodiment 6) This embodiment will describe a display device according to one embodiment of the present invention, including a block diagram, a circuit diagram, and signal The description will be given with reference to waveform diagrams showing potential changes in signals, top views (layout diagrams), and the like.

[0222] FIG. 11A shows an example of a block diagram of an active matrix type liquid crystal display device. The liquid crystal display device shown in FIG. 11(A) has a plurality of pixels each having a display element on a substrate 800. A scanning line driving circuit that controls the potential of the scanning line connected to the gate electrode of each pixel. 802, and a signal line driver circuit 803 for controlling the input of a video signal to a selected pixel. Each pixel is provided with a transistor 804 shown in FIG. The resistor 804 is connected between the In terminal and the Out terminal by the first control signal G1 and the second control signal G2. The transistor 804 shown in FIG. The symbol indicates a transistor described in any one of the first to fourth embodiments. is equivalent to.

[0223] In this embodiment, a scanning line driver circuit 802 and a signal line driver circuit 803 are formed on a substrate 800. However, a part of the scanning line driver circuit 802 may be formed on a separate substrate such as an IC. A part of the signal line driver circuit 803 may be implemented by an IC formed on another substrate. A plurality of scanning line driver circuits 802 may be provided over the substrate 800.

[0224] FIG. 12 shows a display device including a signal input terminal, a scanning line, a signal line, and a nonlinear element. A diagram illustrating the positional relationship between a protection circuit and a pixel portion. In the example shown in FIG. 1, scanning lines 823A, control lines 823B, and signal lines 824 are arranged to cross each other, and a pixel section 827 is formed. The pixel section 827 corresponds to the pixel section 801 shown in FIG. The control line 823B may be arranged in parallel with the signal line 824.

[0225] The pixel section 827 is configured with a plurality of pixels 828 arranged in a matrix. 28 is a pixel transistor connected to a scanning line 823A, a control line 823B, and a signal line 824. It is composed of a capacitor 829 , a storage capacitor 830 , and a pixel electrode 831 .

[0226] In the pixel configuration shown here, one electrode of the storage capacitor 830 is connected to the pixel transistor 82 9, and the other electrode of the storage capacitor 830 is connected to a capacitor line 832. The pole 831 drives display elements (liquid crystal elements, light-emitting elements, contrast media (electronic ink), etc.) The other electrode (also called the counter electrode) of each of these display elements is It is connected to a common terminal 833. A common potential (also called a common potential) is supplied from the common terminal. is supplied to the counter electrode of the display element.

[0227] The protection circuit 835 is disposed between the wiring extending from the pixel section 827 and the signal line input terminal 822. The protection circuit 835 is disposed between the scanning line driver circuit 802 and the pixel portion 827. In this embodiment, a protection circuit 835 consisting of a plurality of protection circuits is provided. Then, static electricity or the like is generated in the scanning line 823A, the control line 823B, the signal line 824, and the capacitance line 832. In order to prevent damage to pixel transistor 829 etc. when a surge voltage due to Therefore, when a surge voltage is applied to the protection circuit 835, The capacitor is configured so that electric charges can escape to the capacitor wiring.

[0228] In this embodiment, one protection circuit is provided for one wiring near the signal line input terminal 822. However, the position of the protection circuit 835 and the protection circuit 835 may be changed. The number of protection circuits is not limited to this.

[0229] The transistor shown in any one of the first to fourth embodiments is used as a pixel transistor. By applying the same to the pixel transistor 829, the threshold voltage of the pixel transistor 829 can be adjusted and the transistor It is therefore possible to realize either or both of an increase in the on-state current and an increase in the on-state current.

[0230] FIG. 13A shows a waveform diagram illustrating an outline of the potential change of a signal supplied to the pixel 828. In FIG. Here, the operation of the pixel 828 will be described. The potentials of the scanning line 823A, the control line 823B, the signal line 824, and the capacitance line 832 FIG. 13A shows a waveform G that shows an outline of the potential change of the scanning line 823A. 1, a waveform G2 showing an outline of the potential change of the control line 823B, and a waveform G3 showing an outline of the potential change of the signal line 824. The horizontal axis represents time, and the vertical axis represents a waveform D representing a potential change of the capacitance line 832. The time change of these voltages is shown. Note that the high power supply voltage of the waveform G1 is V1 The low power supply potential of the waveform G1 is represented as V2, and the potential of the waveform G2 is V C The high of waveform D is The power supply potential is V D1 The low power supply potential of waveform D is V D2 and the potential of the waveform COM is V C OM As shown in FIG. 13, from the moment when the waveform G1 changes from V2 to V1, The period from V1 to V2 and back to V1 is one frame period. As shown in the figure, from the moment when the waveform G1 changes from V2 to V1, until V1 becomes V2 again, The period at is one gate selection period.

[0231] In FIG. 13A, during one gate selection period of one frame period, that is, when the scanning line 823A is at V1, At one point, V D1 From V D2 The potential of the signal line 824 in the range In FIG. 13A, the period other than one gate selection period of one frame period is held in the memory 830. When the scan line 823A is V2, V D1 From V D2 Signal lines in the range of 8 Regardless of the potential of the gate electrode 24, the storage capacitor 830 in the pixel 828 receives the input during one gate selection period. The waveform G2 showing the outline of the potential change of the control line 823B is The control of the pixel transistor 829 being turned on or off by the pixel transistor 829 by the pixel transistor 829A is fixed within a range where no malfunction occurs. It is preferable that the potential of the control line 823B is set to a fixed potential. c V D2 The following is preferably is V2 to V D2 By setting the range to the range of the pixel transistor 829 by the scanning line 823A, This can prevent malfunction of the control of conduction or non-conduction.

[0232] FIG. 13B shows an example in which the potential of the signal line 824 is set to V D1 When fixed at 13B is a waveform diagram showing an outline of the potential change of the signal A point specifically showing waveform D showing the potential change of line 824 (V D1 From V D 2), which is held in the storage capacitor 830 in the pixel 828. Potential change waveform C pix In FIG. 13(B), before the waveform G1 is changed to V1, Waveform D to V D2 From V D1 Then, the waveform G1 is changed to V1, and the storage capacitance The potential held at section 830, i.e., waveform C pix The potential of the (See the first gate selection period shown in Figure 13(B). In Figure 13(B), before waveform G1 is set to V1, Shape D to V D1 From V D2 Then, the waveform G1 is changed to V1, and the storage capacitor 8 in the pixel 828 Potential of 30, i.e. waveform C pix The potential of the second 1 shown in FIG. 13(B) is lowered. (See Gate Selection Period.) Before waveform G1 is set to V1, waveform D is set to V D2 From V D1 ,or V D1 From V D2 By setting this to "ON", you can reduce malfunctions caused by signal delays, etc. In addition, in Fig. 13(B), waveforms D and C pix There are periods when the potential is the same, but The figures are shifted to show the actual positions.

[0233] As shown in FIG. 13(A) and FIG. 13(B), by providing a control line 823B, Therefore, the same effects as those of the transistor described in any one of the first to fourth embodiments can be obtained. In addition to obtaining a threshold voltage of the pixel transistor 829, the threshold voltage of the pixel transistor 829 can be controlled. In particular, by setting the waveform G2 of the control line 823B to a fixed potential, the threshold voltage is stabilized. This is preferable because it is possible to obtain a transistor with a good uniformity.

[0234] The outline of the potential change of the signal supplied to the pixel 828 shown in FIGS. The waveform diagram is an example, and other driving methods may be used in combination. For example, the common potential (common potential) of the common electrode is changed every certain period, every frame, or every pixel. A driving method in which the polarity of the voltage applied to the pixel electrode is inverted relative to the By using the inversion drive, flicker of the image can be prevented. It is possible to suppress display unevenness and deterioration of display elements (for example, liquid crystal elements) such as the above. Examples of inversion driving include frame inversion driving, source line inversion driving, gate line inversion driving, etc. Examples of display methods include progressive inversion driving and dot inversion driving. A pixel may have multiple sub-pixels (sub-pixels). A structure in which a pixel (also referred to as a pixel) is provided may be used.

[0235] FIG. 14 shows an example of a layout of the pixel 828 shown in FIG. The transistor is of a channel etch type, similar to that shown in the first embodiment. The cross section taken along line -B corresponds to the cross section of FIG. 1(C). The diagram corresponds to three colors, RGB (R is red, G is green, and B is blue), in the direction in which the scanning line 823A extends. In this example, the pixels corresponding to the respective pixels are arranged in a so-called stripe arrangement. However, the present invention is not limited to this, and may be a layout having a delta arrangement or a Bayer arrangement. , RGB, and may be more than three colors, for example, RGBW (W is white), or You can also use RGB with one or more colors such as yellow, cyan, or magenta added. The size of the display area may differ for each pixel of each RGB color element.

[0236] The circuit of the pixel in FIG. 14 includes a wiring that becomes a scanning line 823A and one electrode of a capacitance line 832. A first conductive layer 1101 that functions as a wiring, a channel region of a pixel transistor 829 the other of the wiring to be the signal line 824 and the capacitor line 832 The second conductive layer 1103 functions as a wiring that becomes the electrode of the pixel electrode 831. layer 1104, a third conductive layer 1105 functioning as wiring to become the control line 823B, and An opening 1106 (contact) for making contact between the conductive layer 1103 of the second electrode and the pixel electrode 831 In FIG. 14, the first conductive layer 1101 and the The third conductive layer 1105 extends over the oxide semiconductor layer 1102. 15, the first conductive layer 1101 and the oxide semiconductor layer 11 The structure shown in FIG. 15 may be a light-shielding structure. When the third conductive layer 1105 is formed of a conductive material, the third conductive layer 1105 is smaller than the layout diagram of FIG. This can further improve the light blocking property of the conductive layer 1105.

[0237] In the layout diagram shown in FIG. 14, the source and drain regions of the transistors The opposing portions of the gate region may be U-shaped or C-shaped. The first conductive layer 1101 functioning as a back electrode may be U-shaped or C-shaped. The width of the first conductive layer 1101 functioning as the first gate electrode in the channel length direction is The width of the second gate electrode is preferably larger than that of the oxide semiconductor layer 1102. The width (width in the channel length direction) of the functioning third conductive layer 1105 is 1 / 100th of that of the first conductive layer 1101. The width of the oxide semiconductor layer 1102 is narrower than that of the oxide semiconductor layer 1102 .

[0238] Note that FIG. 16 shows an example in which the pixel transistors and the scanning lines are connected in a different manner from that shown in FIG. 6 is a scanning transistor using any one of the transistors shown in the first to fourth embodiments. A first gate electrode connected to the line and a second gate electrode connected to the control line are connected to In FIG. 16, the same parts as those in FIG. 12 are repeated. The explanation of the repetition will be omitted.

[0239] FIG. 16 shows a display device including a signal input terminal, a scanning line, a signal line, and a nonlinear element. FIG. 16 is a diagram for explaining the positional relationship between the protection circuit and the pixel unit. 12. At the point where there is no scan line 823B and there is a scan line 823 corresponding to the scan line 823A in FIG. As shown in FIG. 16, a second gate electrode is connected to the scanning line 823 to form a pixel transistor. By controlling the control line, the control line can be omitted, and the number of wiring and the signal line input terminal 8 The number of 22 can be reduced.

[0240] FIG. 17 is a waveform diagram showing an outline of a change in potential of a signal supplied to the pixel 828 shown in FIG. The operation of the pixel 828 in FIG. 16 will be described. FIG. 17 shows the operation of the pixel 828 connected to an arbitrary pixel. The waveforms of the potentials of the scanning line 823, the signal line 824, and the capacitance line 832 are shown in FIG. In FIG. 17, in order to clarify the difference from FIG. 13(A), the scanning line 823 is connected to the The potential of the first gate electrode and the potential of the second gate electrode are equalized by shifting them slightly. FIG. 17 shows a waveform G1 showing an outline of the potential change of the first gate electrode, a waveform G2 showing an outline of the potential change of the second gate electrode, and a waveform G3 showing an outline of the potential change of the first gate electrode. A waveform G2 showing an outline of the potential change of the electrode, a waveform D showing an outline of the potential change of the signal line 824, and The waveform COM representing the potential change of the capacitance line 832 is plotted on the horizontal axis as time and on the vertical axis as potential. The high power supply potential of waveforms G1 and G2 is represented as V1. The low power supply potential of waveforms G1 and G2 is represented as V2, and the high power supply potential of waveform D is V D1 and The low power supply potential of waveform D is V D2 and the potential of the waveform COM is V COM In addition, Fig. 17 As shown in the figure, the moment the waveform G1 changes from V2 to V1, V1 becomes V2 again, The period until V1 is reached again is one frame period. As shown in FIG. The period from the moment 1 becomes V2 to V1 until V1 becomes V2 again is one gate selection. It is a period.

[0241] In FIG. 17, when one gate selection period of one frame period, that is, when the scanning line 823 is V1, , V D1 From V D2 The potential of the signal line 824 in the range In addition, in the period other than the gate selection period of one frame period in FIG. When the scan line 823 is V2, V D1 From V D2 Regarding the potential of the signal line 824 in the range The storage capacitor 830 in the pixel 828 stores the potential input during one gate selection period. .

[0242] As shown in FIG. 17, the waveforms G1 and G2 are set to the same potential, The area serving as the channel of the pixel transistor 829 can be increased, and the current flowing through the pixel transistor 829 can be increased. This allows the amount of current to be increased, making it possible to operate the display element at high speed. Another configuration for driving the G2 transistors at the same potential is shown in FIG. A configuration in which a scanning line driver circuit 802A and a second scanning line driver circuit 802B are provided may be used. As shown in FIG. 18, the first scanning line driving circuit 802A and the second scanning line driving circuit 80 2B supplies scanning signals via a first scanning line 823C and a second scanning line 823D. The transistor may be controlled.

[0243] The waveform diagram showing the outline of the potential change shown in FIG. 17 is an example similar to FIG. 13. The above driving methods may be combined. For each frame or for each pixel, the pixel electrode is The polarity of the voltage applied to the By using the inversion driving, the same effect as above can be obtained.

[0244] FIG. 19 shows an example of a layout diagram of the pixel 828 shown in FIG. The transistor is a channel etch type similar to that shown in the first embodiment. The pixel layout diagram shown in FIG. 8 is a diagram in which RGB (R is red, G is green, B is blue, Here is an example of a so-called stripe arrangement in which pixels corresponding to three colors (black, red, blue) are arranged side by side. The layout shown is not limited to a delta layout or a Bayer layout. It should be noted that the color is not limited to the three colors of RGB, and may be, for example, RGBW (W is white) or R One or more colors such as yellow, cyan, magenta, etc. may be added to GB. The size of the display area may differ for each pixel of each RGB color element.

[0245] The pixel circuit in FIG. 19 includes a wiring that becomes a scanning line 823 and one electrode of a capacitance line 832. A first conductive layer 1101 which functions as a wiring for forming a channel region of the pixel transistor 829 The oxide semiconductor layer 1102 to be formed, the wiring to be the signal line 824, and the other of the capacitor line 832 A second conductive layer 1103 functioning as a wiring that becomes an electrode, and a pixel electrode layer that becomes a pixel electrode 831 1104, a third conductive layer 1105 connected to the first conductive layer 1101, and a second conductive layer To contact the layer 1103 with the pixel electrode 831 or to contact the first conductive layer 1101 with An opening 1106 (also called a contact hole) for making contact with the third conductive layer 1105. In FIG. 19, the third conductive layer 1105 is formed on the oxide semiconductor layer 1. 102, a configuration in which the pixel transistor 829 is provided for each pixel transistor 829 is shown. In this case, the insulating film 1101 is provided so as to cover the first conductive layer 1101 and the oxide semiconductor layer 1102. As shown in FIG. 20, the third conductive layer 110 may be made of a conductive material having a light blocking property. 19. When the third conductive layer 1105 is formed, the light shielding property of the third conductive layer 1105 is further improved compared to the layout diagram of FIG. can be increased to.

[0246] In the layout diagram shown in FIG. 19, the source and drain regions of the transistors The opposing portions of the gate electrode may be U-shaped or C-shaped. Alternatively, the first conductive layer 1101 functioning as the first conductive layer may be U-shaped or C-shaped. The width of the first conductive layer 1101 functioning as the first gate electrode in the channel length direction is The width of the second gate electrode 1102 is preferably larger than that of the oxide semiconductor layer 1102. The width (width in the channel length direction) of the third conductive layer 1105 that can be used is 1 / 100th of the width of the first conductive layer 1101. 1102. The width of the oxide semiconductor layer 1102 is larger than that of the oxide semiconductor layer 1102.

[0247] As described above, the transistor having the configuration of any one of the first to fourth embodiments By using the capacitor, in addition to the effects described in the above embodiment, the threshold voltage can be appropriately controlled. It can be said that.

[0248] In this embodiment, the contents described in each figure may be the same as those described in another embodiment. can be freely combined or substituted as appropriate.

[0249] (Embodiment 7) In this embodiment, the oxide semiconductor layer described in any one of Embodiments 1 to 4 is A light-emitting display device using a transistor having the above structure will be described. As the display element, a light-emitting element that uses electroluminescence is shown as an example. Light-emitting elements that utilize electroluminescence are made of organic or inorganic light-emitting materials. They are classified according to whether they are organic compounds or inorganic compounds. The former are called organic EL elements, and the latter are called inorganic EL elements. is.

[0250] In an organic EL element, electrons and positive electrodes are released from a pair of electrodes by applying a voltage to the light-emitting element. The holes are then injected into a layer containing a light-emitting organic compound, and a current is passed through them. The recombination of carriers (electrons and holes) causes light-emitting organic compounds to enter an excited state. When the excited state returns to the ground state, light is emitted. is called a current-excited light-emitting element.

[0251] Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor-based ion exchange reaction that utilizes the donor and acceptor levels. This is an acceptor recombination type emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism is the inner shell electron transition of metal ions. It is a localized emission that is utilized.

[0252] In this embodiment, an organic EL element is used as the light emitting element.

[0253] FIG. 21 is a circuit diagram showing a configuration of a semiconductor device including a transistor according to any one of the first to fourth embodiments. 1 shows an example of a pixel of a light-emitting display device.

[0254] The structure and operation of a pixel included in a light-emitting display device will be described. n-channel type using (e.g. In-Ga-Zn-O non-single crystal film) in the channel formation region 1 shows an example in which one pixel has two transistors.

[0255] The pixel 6400 includes a switching transistor 6401 (first transistor), a driving A transistor 6402 (second transistor), a capacitor element 6403, and a light-emitting element 64 In the switching transistor 6401, the first gate electrode is connected to the scanning line 6 406A, the second gate electrode is connected to the control line 6406B, and the first electrode (so The second electrode (one of the source electrode and the drain electrode) is connected to a signal line 6405, The other of the drain electrode and the drain electrode is connected to the gate of the driving transistor 6402. In the driving transistor 6402, a first gate electrode is connected to a capacitor element 6403. The first gate electrode is connected to the power supply line 6407, the second gate electrode is connected to the control line 6406B, and the first electrode The first electrode is connected to a power line 6407, and the second electrode is connected to a first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The electrode 6408 is electrically connected to a common potential line formed on the same substrate, and the connection portion may be used as the common connection portion.

[0256] It is to be noted that the second electrode (common electrode 6408) of the light-emitting element 6404 is set to a low power supply potential. The low power supply potential is a low power supply potential based on the high power supply potential set to the power supply line 6407. A potential that satisfies the power supply potential < high power supply potential. Examples of low power supply potential include GND and 0V. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404, In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and a low power supply potential are The potential difference between the source potential and the light emitting element 6404 is equal to or greater than the forward threshold voltage of the light emitting element 6404. Set the potential.

[0257] The capacitor 6403 is omitted because it is replaced by the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 is, for example, It is sufficient that the insulating film is formed between the region and the gate electrode.

[0258] When analog gradation driving is performed, a light emitting diode is applied to the first gate of the driving transistor 6402. A voltage equal to or higher than the forward voltage of the element 6404 plus the threshold voltage of the driving transistor 6402 is applied. The forward voltage of the light emitting element 6404 refers to a voltage for achieving a desired luminance. , including at least a forward threshold voltage. When a video signal that operates in this manner is input, a current can be passed through the light emitting element 6404. The potential of the power supply line 6407 is set to 0 V in order to operate the driving transistor 6402 in a saturation region. The potential of the first gate of the driving transistor 6402 is made higher than that of the first gate of the driving transistor 6402. By setting the value of the analog gray scale, a current corresponding to a video signal is applied to the light emitting element 6404, and an analog gray scale drive is performed. The movement can be carried out.

[0259] As shown in FIG. 21, by providing a control line 6406B, A switching transistor 640 similar to any of the transistors shown in the fourth embodiment In particular, the threshold voltage of the driving transistor 6402 can be controlled. The video signal is input to the transistor 6402 so that it operates in the saturation region. Therefore, by controlling the threshold voltage by the potential of the control line 6406B, The difference between the input video signal and the brightness of the light-emitting element caused by the shift in threshold voltage As a result, the display quality of the display device can be improved. .

[0260] The switching transistor 6401 is a transistor that operates as a switch. Therefore, it is not necessary to control the potential of the second gate by the control line 6406B. That is, the control line 6406B is connected only to the second gate of the driving transistor 6402. It may be possible.

[0261] Note that the pixel configuration shown in FIG. 21 is not limited to this. For example, In addition, switches, resistors, capacitors, transistors, logic circuits, etc. may be added. .

[0262] In addition, when performing digital gradation driving, the gate of the driving transistor 6402 is connected to The driving transistor 6402 is either fully on or fully off. In other words, the driving transistor 6402 is in the linear region. The driving transistor 6402 is operated in the linear region. The first gate of the transistor 6402 is set to a potential higher than the potential of the power supply line 6407. A voltage of (power supply line voltage + Vth of the driving transistor 6402) or more is applied to the signal line 6405. The same pixel configuration as in FIG. 21 can be used.

[0263] Next, the configuration of the light-emitting element will be described with reference to FIG. The cross-sectional structure of a pixel will be described using an n-channel transistor as an example. 22(A), (B), and (C) are transistors 7001 and 7002 which are driving transistors. The transistor 7011 and the transistor 7021 are the same as the transistor 4 shown in Embodiment 1. The transistor can be fabricated in the same manner as in Example 71, etc., in which an oxide semiconductor layer is used for the channel formation region. It is a ninja.

[0264] A light-emitting device requires that at least one of the anode and cathode is transparent in order to extract light. Then, a transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite the substrate. The top emission structure extracts the light from the top surface (top emission), and the bottom emission structure extracts the light from the substrate side. Bottom emission structure, light is emitted from both the substrate side and the opposite side of the substrate. There are light-emitting elements with a dual emission structure, as shown in Figure 22. In this embodiment, either of these can be applied.

[0265] A light emitting element having a top emission structure will be described with reference to FIG.

[0266] FIG. 22A shows a driving transistor in which the transistor 7001 described in Embodiment 1 is arranged in a pixel. A light emitting element 7002 electrically connected to the transistor 7001 emits light. 7 shows a cross-sectional view of a pixel in which light emitted from the transistor 700 is emitted to the anode 7005 side. 1 is covered with a protective layer 7007 and a resin layer 7017, and silicon nitride is further formed on the resin layer 7017. The second protective insulating layer 7018 is formed by a GaN film. is formed of an In-Zn-O based oxide semiconductor.

[0267] In FIG. 22A, a cathode 7003 of a light emitting element 7002 and a transistor which is a driving transistor are A light-emitting layer 7004 is formed on a cathode 7003, and an anode 7004 is formed on the cathode 7003. The cathode 7003 has a small work function and reflects light. Any conductive material that reflects light can be used. For example, Ca, Al , MgAg, AlLi, etc. are preferred.

[0268] In FIG. 22A, the second gate electrode is formed of the same material as the cathode 7003. The oxide semiconductor layer is covered with a second gate electrode 7009. The second gate electrode 7009 controls the threshold voltage of the transistor 7001. The cathode 7003 and the second gate electrode 7009 are formed in the same layer using the same material. This makes it possible to reduce the number of steps.

[0269] In order to prevent a short circuit between the second gate electrode 7009 and the cathode 7003, an insulating material A partition wall 7006 made of a cathode 70 is provided. A light-emitting layer 7004 is provided so as to overlap both a part of the insulating film 7003 and the partition wall 7006 .

[0270] The light-emitting layer 7004 may be formed of a single layer or a plurality of layers may be laminated. In the case where a plurality of layers are laminated, the cathode 7003 may be formed on the cathode 7003. An electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are laminated in this order. It is not necessary to provide all of these layers. The insulating layer is formed of a conductive material having a high insulating property, for example, indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), A transparent material such as indium zinc oxide or indium tin oxide doped with silicon oxide. Alternatively, a conductive material may be used.

[0271] A light-emitting element is formed by a cathode 7003, an anode 7005, and a light-emitting layer 7004 sandwiched between them. In the case of the pixel shown in FIG. The emitted light is emitted toward the anode 7005 as indicated by the arrow.

[0272] Next, a light emitting element having a bottom emission structure will be described with reference to FIG.

[0273] FIG. 22B shows a driving transistor in which the transistor 7011 described in Embodiment 1 is arranged in a pixel. A light emitting element 7012 electrically connected to the transistor 7011 emits light. 7 shows a cross-sectional view of a pixel in which light emitted from the transistor 70 is emitted toward the cathode 7013 side. 11 is covered with a protective layer 7007 and a resin layer 7017, and further, a silicon nitride layer is formed on the resin layer 7017. The second protective insulating layer 7018 is formed by a capacitor. The glass is made of an In-Ga-Zn-O oxide semiconductor.

[0274] In FIG. 22B, the transistor 7011 which is a driving transistor is electrically connected to A cathode 7013 of a light-emitting element 7012 is formed on the light-transmitting conductive film 7010. A light-emitting layer 7014 and an anode 7015 are laminated in this order on a cathode 7013. In addition, when the anode 7015 has a light-transmitting property, a light-reflecting or light-transmitting layer is provided so as to cover the anode 7015. A shielding film 7016 for shielding the cathode 7013 may be formed. As in the case of the first embodiment, various conductive materials having a small work function can be used. However, the thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm can be used as the cathode 7013 .

[0275] The light-emitting layer 7014 may be formed of a single layer as in FIG. Alternatively, a plurality of layers may be laminated. The anode 7015 does not need to transmit light. As in FIG. 22A, the light-transmitting conductive material can be used. The shielding film 7016 may be, for example, a metal film that reflects light. However, the present invention is not limited to this. For example, a resin to which a black pigment is added may be used.

[0276] In FIG. 22B, the conductive film 7010 is formed from the same conductive material as the light-transmitting conductive film 7010. A second gate electrode 7019 formed on the oxide semiconductor layer covers the oxide semiconductor layer. In the example, the second gate electrode 7019 is made of indium tin oxide containing silicon oxide. The second gate electrode 7019 controls the threshold voltage of the transistor 7011. The light-transmitting conductive film 7010 and the second gate electrode 7019 are formed of the same material. By forming the oxide layer of the transistor 7011, the number of steps can be reduced. The semiconductor layer is shielded from light by a shielding film 7016 above the second gate electrode 7019. .

[0277] A light-emitting element is formed by a cathode 7013, an anode 7015, and a light-emitting layer 7014 sandwiched between them. In the case of the pixel shown in FIG. 22B, the light-emitting element 7012 The emitted light is emitted towards the cathode 7013 as indicated by the arrow.

[0278] Next, a light emitting element having a dual emission structure will be described with reference to FIG.

[0279] FIG. 22C shows a driving transistor in which the transistor 7021 described in Embodiment 1 is arranged in a pixel. A light emitting element 7022 electrically connected to the transistor 7021 emits light. 7 shows a cross-sectional view of a pixel in which incident light exits through both the anode 7025 side and the cathode 7023 side. The transistor 7021 is covered with a protective layer 7007 and a resin layer 7017. 17, a second protective insulating layer 7018 formed of silicon nitride, The channel of 7021 is formed of a Zn-O based oxide semiconductor.

[0280] A light-transmitting transistor 7021 is electrically connected to the connection electrode 7028. A cathode 7023 of the light-emitting element 7022 is formed on the conductive film 7027. A light-emitting layer 7024 and an anode 7025 are laminated in this order on the cathode 7023. As in the case of FIG. 22(A), various conductive materials with small work functions can be used. However, the thickness must be such that light can pass through (preferably 5 nm to 30 nm). For example, an aluminum film with a thickness of 20 nm is used as the cathode 7023. can be done.

[0281] The light-emitting layer 7024 may be formed of a single layer as in FIG. Alternatively, a plurality of layers may be laminated. The anode 7025 may be formed by laminating a plurality of layers, as in FIG. The insulating film 11 can be formed using a light-transmitting conductive material.

[0282] A light-emitting element is formed by a cathode 7023, an anode 7025, and a light-emitting layer 7024 sandwiched between them. In the case of the pixel shown in FIG. 22C, the light-emitting element 7022 The emitted light is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0283] Note that in FIG. 22C, a second gate electrode 7029 covers the oxide semiconductor layer. Therefore, the material of the second gate electrode 7029 is a conductive material having a light blocking property (e.g. , Ti, titanium nitride, Al, W, etc.) is used. The material is titanium. The second gate electrode 7029 of the transistor 702 The oxide semiconductor layer of the transistor 7021 is connected to the second gate The light is blocked by an electrode 7029. A connection electrode 702 connected to a transistor 7021 8 is formed as the same layer by the same material (i.e., titanium) as the second gate electrode 7029. and form.

[0284] Here, the case where an organic EL element is used as the light emitting element has been described. The element may be an inorganic EL element.

[0285] In this embodiment, a transistor (a driving transistor) that controls driving of a light-emitting element is used. In the above example, the driving transistor and the light emitting element are connected. A current control transistor may be connected.

[0286] Next, the appearance of a light-emitting display panel (also called a light-emitting panel) which is one embodiment of a semiconductor device will be described. The cross section will be described with reference to FIG. 23. FIG. 23(A) shows a cross section of a transistor formed on a first substrate. A light-emitting display panel in which a transistor and a light-emitting element are sealed between a second substrate by a sealant. 23(B) is a top view of the semiconductor device, and FIG. 23(B) corresponds to a cross-sectional view taken along line HI in FIG. 23(A).

[0287] A pixel portion 4502, a signal line driver circuit 4503a, a signal The scanning line driver circuit 4503b, the scanning line driver circuit 4504a, and the scanning line driver circuit 4504b are surrounded by the A sealant 4505 is provided. a, a signal line driver circuit 4503b, a scanning line driver circuit 4504a, and a scanning line driver circuit 45 A second substrate 4506 is provided on the pixel portion 4502 and the signal line driver 4504. A signal line driver circuit 4503a, a signal line driver circuit 4503b, a scanning line driver circuit 4504a, and a scanning line The driver circuit 4504b includes a first substrate 4500, a sealant 4505, and a second substrate 4506. The filling material 4503 is sealed together with the filling material 4503 by the sealing material 4503. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0288] A pixel portion 4502, a signal line driver circuit 4503a, a signal The scanning line driver circuit 4503b, the scanning line driver circuit 4504a, and the scanning line driver circuit 4504b are In FIG. 23B, the transistor included in the pixel portion 4502 is 4510 and a transistor 4509 included in a signal line driver circuit 4503a. is doing.

[0289] Here, the transistor 4509 and the transistor 4510 are made of a Zn-O-based oxide semiconductor. In this embodiment, the transistors 4509 and 4510 are n-channel transistors. The transistor 4509 and the transistor 4510 are first channel transistors. A resin layer 4508 on the protective layer 4507, and a second protective insulating layer 4514 on the resin layer 4508. , the second protective insulating layer 4514 formed of silicon nitride is It is formed to cover the upper surface and side surfaces of the resin layer 4508. A second gate electrode 4522 is provided above the transistor 4510. The first gate electrode 4521 and the second gate electrode 4522 is formed from the same layer and controls the threshold voltage of the transistor. The insulating layer also functions as a protective layer for the oxide semiconductor layer.

[0290] The width of the second gate electrode 4522 is wider than the width of the gate electrode of the transistor 4509. In this case, it is preferable that a gate voltage be applied to the entire oxide semiconductor layer. When the gate electrode 4522 is formed of a light-shielding conductive material, the oxide The second gate electrode 4522 can be made of a light-shielding conductive material. When a transistor is formed using a photosensitive material, the electrical characteristics of the transistor change due to the photosensitivity of the oxide semiconductor. This prevents this and ensures stable operation.

[0291] The width of the second gate electrode 4521 is different from the width of the second gate electrode 4522. The width of the second gate electrode 452 may be narrower than that of the first gate electrode of the transistor 4510. 1 is narrower than the width of the first gate electrode of the transistor 4510. The area overlapping with the source or drain electrode of the ST4510 is reduced to reduce the parasitic capacitance. The width of the second gate electrode 4521 can be set to be equal to the width of the oxide semiconductor layer of the transistor 4510. It is narrower than the width of the conductor layer and only partially blocks light, but there is a second electrode layer 451 above it. 3 is provided, and the second electrode layer 4513 is formed of a light-shielding conductive material. In this case, the entire oxide semiconductor layer can be shielded from light.

[0292] The first electrode layer 4517, which is a pixel electrode of the light-emitting element 4511, is a transistor 45 The light-emitting element 4511 is connected to a source electrode or a drain electrode of the first light-emitting element 4510. A first electrode layer 4517, an electroluminescent layer 4512, and a second electrode layer 4513 are laminated. The structure is not limited to this. In addition, the configuration of the light-emitting element 4511 can be changed as appropriate.

[0293] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, an opening is formed on the first electrode layer 4517 using a photosensitive material, and the side of the opening is It is preferable that the wall is formed to have an inclined surface having a continuous curvature.

[0294] The electroluminescent layer 4512 may be formed of a single layer or a laminate of multiple layers. It may be formed.

[0295] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 4511, A protective film may be formed to cover the electrode layer 4513 and the partition wall 4520. Examples of the film include a silicon nitride film, a silicon oxide nitride film, and a DLC film.

[0296] A signal line driver circuit 4503a, a signal line driver circuit 4503b, a scanning line driver circuit 4504a, Various signals and potentials given to the scanning line driver circuit 4504b or the pixel portion 4502 are Powered by FPC4518a and FPC4518b.

[0297] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 451 of the light emitting element 4511. 7, and is formed as the same layer with the same material. The source and drain electrodes of the transistor 4510 are made of the same material and have the same layer. Note that the transistor 4509 and the transistor A gate insulating layer 4501 of a transistor 4510 is provided.

[0298] The connection terminal electrode 4515 is a terminal of the FPC 4518a and an anisotropic conductive film 4519. The two are electrically connected via a

[0299] The second substrate 4506 located in the direction in which light is extracted from the light emitting element 4511 is transparent. In that case, glass plates, plastic plates, polyester films, etc. Alternatively, a light-transmitting substrate such as an acrylic film is used.

[0300] In addition, the filler 4503 can be an inert gas such as nitrogen or argon, or an ultraviolet ray hardening agent. The resin can be a fluororesin or a thermosetting resin. Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Here, nitrogen is used as the filler. Use element.

[0301] If necessary, a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), or a positioning plate may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (lambda / 4 plates, lambda / 2 plates) or color filters can be used. Alternatively, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0302] A signal line driver circuit 4503a, a signal line driver circuit 4503b, a scanning line driver circuit 4504a, The scanning line driver circuit 4504b is formed of a single crystal semiconductor film or a polycrystalline semiconductor film on another substrate. In addition, only the signal line driver circuit, or a part of the scanning line driver circuit, or All may be formed on a separate substrate.

[0303] Through the above steps, a highly reliable light-emitting display device (display panel) is manufactured as a semiconductor device. It is possible.

[0304] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is Noh.

[0305] (Embodiment 8) In this embodiment, the oxide semiconductor layer described in any one of Embodiments 1 to 4 is A liquid crystal display device using a transistor using the above-mentioned embodiment will be described. A transistor including an oxide semiconductor layer according to any one of the above aspects 4 is used for a driver circuit and a pixel. By using the transistor as a part, a liquid crystal display device having a display function can be manufactured. By using a photodiode, a part or the whole of the driver circuit is formed on the same substrate as the pixel section, and a system-on A panel can be made.

[0306] A liquid crystal display device includes a liquid crystal element (liquid crystal display element) as a display element.

[0307] The liquid crystal display device is made up of a panel in which a display element is sealed, and a control panel connected to the panel. and a module in which an IC including a liquid crystal display is mounted. In the process of manufacturing a device, the element substrate corresponds to one form before the display element is completed. Each pixel is provided with a means for supplying a current to the display element. The substrate may be in a state where only the pixel electrode is formed, or in a state where a conductive film that will become the pixel electrode is formed. It may be in a state before etching is performed to form pixel electrodes after the etching, or in any other form. It fits.

[0308] In this specification, the liquid crystal display device is an image display device, a display device, or Refers to the light source (including lighting equipment). Connectors, such as FPC (Flexible Printed Circuit) rinted circuit) or TAB (Tape Automated Board Tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or display element by using the COG (Chip On Glass) method. The liquid crystal display device also includes all modules on which a display device (such as a display circuit) is directly mounted.

[0309] FIG. 24 shows the appearance and cross section of a liquid crystal display panel, which is one form of liquid crystal display device. 24(A1) and (A2) show a liquid crystal element 4013 mounted on a first substrate 40. 4006 and a second substrate 4006. A sealing material 4005 is disposed between the first substrate 4001 and the second substrate 4006 to seal the panel. FIG. 24(B) corresponds to a cross-sectional view taken along line MN in FIG. 24(A1) and (A2). do.

[0310] In FIG. 24, a pixel portion 4002 and a scanning line driver circuit 4003 are provided on a first substrate 4001. A sealant 4005 is provided to surround the pixel portion 4002. A second substrate 4006 is provided on the scanning line driver circuit 4004. The scanning line driver circuit 4004 includes a first substrate 4001, a sealant 4005, and a second substrate 4002. The liquid crystal layer 4008 is sealed by the substrate 4006. The liquid crystal layer 4008 is not particularly limited, but a liquid crystal material exhibiting a blue phase is used. The liquid crystal material exhibiting this has a response speed of 1 ms from no voltage applied to a voltage applied state. The blue phase is a short wavelength and a high-speed response is possible. The chiral agent is used to orient the liquid crystal in a helical structure and to express a blue phase. For example, a liquid crystal material containing 5% by weight or more of a chiral agent may be used for the liquid crystal layer. Liquid crystals include thermotropic liquid crystals, low molecular weight liquid crystals, polymeric liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. Crystals, etc. are used.

[0311] FIG. 24(A1) shows an area surrounded by a sealant 4005 on a first substrate 4001. A single crystal semiconductor film or a polycrystalline semiconductor film is formed on a separately prepared substrate in a region different from the region. A signal line driver circuit 4003 formed by the above-mentioned is mounted on the substrate.

[0312] FIG. 24(A2) shows an example in which a part of a signal line driver circuit is formed over a first substrate 4001. A signal line driver circuit 4003b is formed on a first substrate 4001, and a signal line driver circuit 4003b is formed on a separately prepared substrate. A signal line driver circuit 4003a formed of a single crystal semiconductor film or a polycrystalline semiconductor film is implemented on the substrate. It is equipped with

[0313] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method. For example, a wire bonding method or a TAB method can be used. 24(A2) is an example of mounting a signal line driver circuit by the COG method, and FIG. This is an example of mounting a driver circuit using the TAB method.

[0314] The pixel portion 4002 and the scanning line driver circuit 4004 provided on the first substrate 4001 are In FIG. 24B, the transistor included in the pixel portion 4002 is 4004 and a transistor 4011 included in the scanning line driver circuit 4004. A first protective insulating layer 4 is formed on the transistor 4010 and the transistor 4011. 020, a resin layer 4021 which is a second protective insulating layer and a third protective insulating layer 4022 are provided. The transistor 4010 and the transistor 4011 are the same as those in the first embodiment to the present embodiment. Any one of the transistors described in Embodiment 4 can be used. In the transistor 4010 and the transistor 4011, an oxide semiconductor layer is This is an n-channel transistor used in the filter formation region.

[0315] The transistor 4010 and the transistor 4011 are formed by a first protective insulating layer 4020 and It is covered with a resin layer 4021 which is a second protective insulating layer and a third protective insulating layer 4022. The first protective insulating layer 4020 is a layer that covers the transistor 4010 and the transistor 401. The first oxide semiconductor layer and the gate insulating layer 4019 are provided over and in contact with each other.

[0316] The resin layer 4021, which is the second protective insulating layer used as a planarizing insulating film, is made of polyimide. Heat-resistant organic compounds such as acrylate, benzocyclobutene, polyamide, and epoxy. In addition to these organic materials, low dielectric constant materials (lo wk materials), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass) ) can be used. In addition, multiple insulating films made of these materials can be stacked. In addition, the resin layer 4021 is a light-transmitting resin layer. In this embodiment, a photosensitive polyimide resin is used.

[0317] The method for forming the insulating layer is not particularly limited, and may be a sputtering method, a SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, An IF coater or the like can be used.

[0318] Note that the third protective insulating layer 4022 is formed to prevent organic matter, metal matter, water vapor, and the like suspended in the air. The purpose is to prevent the intrusion of impurity elements (such as sodium) that contaminate the oxide semiconductor layer. A dense film is preferable. The protective film is formed by depositing silicon oxide using the PCVD method or the sputtering method. silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film , an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film in a single layer. Alternatively, the electrodes may be formed by laminating.

[0319] The third protective insulating layer 4022 is a nitride silicon layer obtained under low power conditions by the plasma CVD method. The base insulating layer 4007 and the third protective layer 4008 are made of silicon nitride. The protective insulating layer 4022 is structured to contact the outside of the pixel portion, and is a second protective insulating layer. The sides of the resin layer 4021 are also sealed, and the transistor 4010 and the transistor 4021 are sealed with a silicon nitride film. The transistor 4010 and the transistor 4011 are surrounded by a This is what they are doing.

[0320] A semiconductor layer 4011 is formed on the first protective insulating layer 4020 and overlaps with the oxide semiconductor layer of the transistor 4011. A second gate electrode 4028 is formed on the third protective insulating layer 4022. A second gate electrode 4029 is provided at a position overlapping with the oxide semiconductor layer of the transistor 4010. is formed.

[0321] A pixel electrode layer 4030 and a common electrode layer 4031 are provided on a first substrate 4001. The electrode layer 4030 is electrically connected to the transistor 4010. The second gate electrode 4028 and the second gate electrode 4029 are set to a common potential with the common electrode layer 4031. The second gate electrode 4028 and the second gate electrode 4029 are formed on a common electrode layer. 4031. The second gate electrode 4028 and the second gate electrode 4029 If the transistor 4011 and the transistor 401 are formed using a light-shielding material, The insulating layer 10 can also function as a light-shielding layer that shields the oxide semiconductor layer 10 from light.

[0322] The second gate electrode 4028 and the second gate electrode 4029 are connected to a common electrode layer 4031. The second gate electrode 4028 and the second gate A control line is provided which is electrically connected to the gate electrode 4029, and a transistor is formed by controlling the potential of the control line. The threshold voltage of the transistor 4010 and the transistor 4011 is controlled.

[0323] The second gate electrode 4028 and the second gate electrode 4029 may be formed by the above-mentioned method. 029 may be connected to the first gate electrode or may be floating.

[0324] The liquid crystal element 4013 includes a pixel electrode layer 4030, a common electrode layer 4031, and a liquid crystal layer 4008. In this embodiment, an electric field is generated that is approximately parallel (i.e., horizontal) to the substrate, The liquid crystal molecules are moved in a plane parallel to the substrate to control the gradation. As an example, the electrode configuration used in IPS (In Plane Switching) mode, The electrode configuration used in FFS (Fringe Field Switching) mode is suitable. The first substrate 4001 and the second substrate 4006 are provided on the outside with polarizing A plate 4032 and a polarizer 4033 are provided.

[0325] The first substrate 4001 and the second substrate 4006 are made of a light-transmitting glass. A substrate or a plastic substrate can be used. For the plastic substrate, F RP (Fiberglass-Reinforced Plastics) plate, PVF ( Polyvinyl fluoride film, polyester film or acrylic resin film Alternatively, aluminum foil can be covered with a PVF film or polyester film. A sheet having a structure sandwiched between films can also be used.

[0326] The post spacers 4035 are obtained by selectively etching the insulating film. This is provided to adjust the thickness (cell gap) of the liquid crystal layer 4008. However, the present invention is not limited to this, and a spherical spacer may be used. , and is disposed at a position overlapping with the second gate electrode 4029 .

[0327] In the liquid crystal display device of FIG. 24, a polarizing plate is provided on the outer side (viewing side) of the substrate. Alternatively, the polarizing plate may be provided on the inner side of the substrate.

[0328] In addition, a light-shielding layer that functions as a black matrix may be provided at a necessary position. In the example shown in FIG. 24, a transistor 4010 and a transistor 4011 are covered with a A light-shielding layer 4034 is provided on the second substrate 4006 side. This further improves the contrast and enables the transistor to operate stably.

[0329] The light-shielding layer 4034 attenuates the intensity of light incident on the oxide semiconductor layer of the transistor. Therefore, a change in the electrical characteristics of a transistor due to the photosensitivity of an oxide semiconductor layer can be prevented. and stable operation can be achieved.

[0330] A pixel electrode layer 4030, a common electrode layer 4031, a second gate electrode 4028, and a second The gate electrode 4029 is made of indium oxide containing tungsten oxide. Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide The conductive material used is a light-transmitting material such as indium tin oxide doped with silicon oxide. It can be achieved.

[0331] Alternatively, the pixel electrode layer 4030, the common electrode layer 4031, the second gate electrode 4028, and The second gate electrode 4029 is made of a conductive material containing a conductive polymer. The composition can be used.

[0332] By the way, the signal line driver circuit 4003 and the scanning line driver circuit 4004 or Various signals and potentials applied to the pixel portion 4002 are supplied from an FPC 4018 .

[0333] Since transistors are easily damaged by static electricity, etc., It is preferable to provide a protection circuit for protecting the driving circuit on the same substrate. It is preferable that the nonlinear element is made of a semiconductor material.

[0334] In FIG. 24, the connection terminal electrode 4015 is formed in the same layer as the pixel electrode layer 4030. A terminal electrode 4016 is connected to the source electrodes of the transistors 4010 and 4011. The drain electrode layer is formed from the same layer as the drain electrode layer.

[0335] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4017. The electrodes are electrically connected to each other.

[0336] In FIG. 24, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. However, the present invention is not limited to this. A scanning line driving circuit may be formed separately and mounted. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed and mounted. Good too.

[0337] FIG. 25 shows an example of a cross-sectional structure of a liquid crystal display device, in which an element substrate 2600 and an opposing substrate 260 1 is fixed by a sealing material 2602, and an element layer 26 including transistors and the like is disposed between them. 03 and a liquid crystal layer 2604 are provided.

[0338] In the case of color display, for example, a light emitting device that emits a plurality of kinds of light colors in the backlight section is used. In the case of the RGB method, the display area of ​​the LCD device is divided into multiple The divided areas are divided into red light emitting diode 2610R and green light emitting diode 2610G. and blue light emitting diodes 2610B are disposed on the right side of the periphery of the light emitting diode 2610A.

[0339] A polarizing plate 2606 is provided on the outer side of the counter substrate 2601, and A polarizing plate 2607 and an optical sheet 2613 are provided. LED 2610R, green LED 2610G and blue LED 2610B A LED control circuit 2614 is formed by a reflector 2611 and provided on a circuit board 2612. is connected to the wiring circuit section 2608 of the element substrate 2600 by a flexible wiring substrate 2609. In addition, external circuits such as a control circuit and a power supply circuit are incorporated.

[0340] In this embodiment, the LEDs can be individually illuminated by the LED control circuit 2614. Although an example of a field sequential liquid crystal display device has been shown, the present invention is not limited to this. The backlight source is a cold cathode fluorescent lamp or a white LED, and no color filters are used. It may be provided.

[0341] In this embodiment, an example of an electrode configuration used in the IPS mode is shown, but the present invention is not limited to this. TN (Twisted Nematic) mode, MVA (Multi-domain Vertical Alignment) mode, PVA(Patterned Ver. tical Alignment) mode, ASM (Axially Symmetry c aligned Micro-cell mode, OCB (Optical Com Pensated Birefringence mode, FLC (Ferroelec tric Liquid Crystal) mode, AFLC (AntiFerroel) mode You can use the (optical Liquid Crystal) mode.

[0342] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is Noh.

[0343] (Embodiment 9) In this embodiment, a semiconductor device including a plurality of transistors each having an oxide semiconductor layer is An example of electronic paper will be described.

[0344] FIG. 26(A) shows a cross-sectional view of an active matrix type electronic paper. The transistor 581 disposed in the display portion used in the embodiment 1 to The transistor according to any one of the fourth aspects is used.

[0345] The electronic paper in FIG. 26(A) is an example of a display device using a twisting ball display method. The twist ball display method uses black and white spherical particles as display elements. The spherical particles are disposed between a first electrode layer and a second electrode layer, and the first electrode layer and the second electrode layer This is a method of displaying information by controlling the orientation of spherical particles by creating a potential difference between them. .

[0346] The transistor 581 is a bottom-gate transistor, and the first electrode layer 587 The first protective insulating layer 584, the resin layer 585 which is the second protective insulating layer, and the third protective insulating layer 586 are The source electrode or the drain electrode is electrically connected through an opening formed in the edge layer 586. The first protective insulating layer 584 covers the transistor 581. A second gate electrode 582 is provided on the upper resin layer 585. A third protective insulating layer 586 is provided to cover the oxide semiconductor layer 581. The conductor layer is a first protective insulating layer 584, a resin layer 585 which is a second protective insulating layer, and a second It is configured to be protected by the gate electrode 582 and the third protective insulating layer 586 .

[0347] Between the first electrode layer 587 and the second electrode layer 588, spherical particles 589 are provided. Particle 589 has a cavity 594, black regions 590a and white regions 590b, and is a sphere. The surroundings of the shaped particle 589 are filled with a filler 595 such as a resin (see FIG. 26(A)). The first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is a common potential line and a potential line provided on the same substrate as the transistor 581. In the common connection portion, conductive particles are disposed between the pair of substrates to form a second The electrode layer 588 can be electrically connected to a common potential line.

[0348] Alternatively, an electrophoretic element can be used instead of the twist ball. A liquid containing positively charged white particles and negatively charged black particles, with a diameter of 10 μm or more. Microcapsules of about 200 μm are used. When a potential difference is applied between the first and second electrode layers, the microcapsules emit a white light. The particles and black particles move in opposite directions, allowing the display to be white or black. A display element that uses this technique is called an electrophoretic display element, and is called electronic paper. The display element has a higher reflectivity than the LCD element, so no auxiliary light is required and power consumption is low. The display is small, so it is possible to see the display even in dimly lit places. It is possible to hold an image once displayed without supplying a new one. In the case where the radio wave source is configured to supply signals and power wirelessly, Even if the semiconductor device with a display function is moved away from the It is possible.

[0349] The transistor described in any one of the first to fourth embodiments is used as a switching element. By using this as a semiconductor device, it is possible to manufacture electronic paper with reduced manufacturing costs. Electronic paper can be used in all kinds of electronic devices that display information. For example, electronic books, postal mail, etc. can be displayed on electronic paper. In-vehicle advertisements on trains and other vehicles, and on various cards such as credit cards An example of an electronic device is shown in FIG.

[0350] FIG. 26B shows an example of an electronic book 2700. The electronic book 2700 is a first housing 2 The device is made up of two housings, a first housing 2701 and a second housing 2703. The housing 2703 is connected by a shaft portion 2711, and is opened and closed around the shaft portion 2711. This configuration allows the device to operate in the same way as a paper book. It becomes.

[0351] The first housing 2701 includes a first display unit 2705, and the second housing 2703 includes a The second display unit 2707 is incorporated. 7 may be configured to display a continuous screen or may be configured to display different screens. By configuring the display to display different screens, for example, the right display unit (the first screen in FIG. 26(B) The display unit 2705) displays text, and the left display unit (the second display unit 270 in FIG. 26(B) 7) can display images.

[0352] In addition, the electronic book 2700 shown in FIG. 26(B) is provided with an operation unit and the like in the first housing 2701. For example, in the first housing 2701, a power supply 2721, an operation key 2723, a switch It is equipped with a speaker 2725. The operation key 2723 can be used to turn pages. Even if the display unit and keyboard, pointing device, etc. are on the same surface as the case, It is good to have external connection terminals (earphone terminal, USB terminal, or AC adapter) on the back or side of the case. Terminals for connecting various cables such as adapters and USB cables, and a recording medium insertion port Furthermore, the electronic book 2700 may have a function as an electronic dictionary. It is okay to do so.

[0353] The electronic book 2700 may be configured to transmit and receive information via wireless communication. The system allows users to purchase and download the desired book data from the e-book server by sending a message to the server. It may also be composed of.

[0354] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is Noh.

[0355] (Embodiment 10) A semiconductor device including a transistor manufactured according to any one of Embodiments 1 to 4. The semiconductor device can be applied to various electronic devices (including gaming machines). Examples of such devices include television devices (televisions or television receivers), computers, etc. Monitors, digital cameras, digital video cameras, digital photo frames, etc. mobile phones (also called mobile phones or mobile phone devices), portable game machines, and portable information terminals , audio playback devices, and large game machines such as pachinko machines.

[0356] The television device shown in FIG. 27A has a display portion 9603 incorporated in a housing 9601. The display unit 9603 can display an image. 9601 is fixed to the rear of the housing 9601.

[0357] The television device shown in FIG. 27A is operated using an operation switch or the like provided in the housing 9601. This can be done by a remote control operation device 9610. The operation keys 9609 allow the user to operate the channel and volume. The image displayed on the remote control unit 9610 can be operated. A display portion 9607 for displaying information output from 9610 may be provided.

[0358] The television device shown in FIG. 27(A) is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts and can also receive TV signals via a modem. By connecting the device to a wired or wireless communication network, It communicates information in a two-way (between sender and receiver, or between receivers) or two-way (between sender and receiver, etc.) manner. It is also possible.

[0359] The portable gaming machine shown in FIG. 27(B) is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to the connecting portion 9893 in an openable and closable manner. A display unit 9882 is incorporated in the housing 9891 , and a display unit 9883 is incorporated in the housing 9891 . The portable gaming machine shown in FIG. 27(B) also includes a speaker unit 9884 and a recording medium insertion unit 98 86, LED lamp 9890, input means (operation keys 9885, connection terminal 9887, sensor 9888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature , chemicals, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, (including functions for measuring vibration, odor, or infrared rays), microphone 9889) etc. Of course, the configuration of the portable gaming machine is not limited to this, and may include at least a semiconductor It is sufficient that the device is included, and other auxiliary equipment may be appropriately provided. The portable gaming machine shown in 27(B) uses a program or data recorded on a recording medium. It has the function of reading the information and displaying it on the display unit, and sharing information with other portable gaming machines through wireless communication. The functions of the portable gaming machine shown in FIG. 27(B) are not limited to these. The present invention may have various other functions.

[0360] FIG. 28A shows an example of a mobile phone 1000. The mobile phone 1000 is a case. In addition to the display unit 1002 incorporated in the body 1001, the device also includes an operation button 1003 and an external connection port 1 004, a speaker 1005, a microphone 1006, etc.

[0361] In the mobile phone 1000 shown in FIG. 28(A), when the display unit 1002 is touched with a finger or the like, You can input information. Operations such as making a phone call or writing an email can be done from the This can be done by touching the display unit 1002 with a finger or the like.

[0362] The display unit 1002 has three main screen modes. The first mode is for displaying images. The first mode is a display mode, and the second mode is an input mode, which is mainly for inputting information such as characters. The third mode is a combination of the display mode and the input mode. It is a mode.

[0363] For example, when making a call or composing an e-mail, the display unit 1002 is used for inputting characters. The main input mode is the character input mode, and the input operation of the characters displayed on the screen can be performed. In this case, most of the screen of the display unit 1002 is used to display a keyboard or number buttons. is preferred.

[0364] The mobile phone 1000 includes a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined, The screen display on the display unit 1002 can be automatically switched.

[0365] The screen mode can be changed by touching the display unit 1002 or by pressing the operation button on the housing 1001. The button 1003 is operated to perform the operation. Alternatively, the image displayed on the display unit 1002 is For example, the display unit 1002 may be configured to switch the display depending on the type of the If the image signal is video data, it switches to display mode, if it is text data, it switches to input mode. It is possible to adopt a configuration in which the above-mentioned

[0366] In the input mode, a signal detected by the optical sensor of the display unit 1002 is detected, and the display If no input is made by touching the display unit 1002 for a certain period of time, the screen mode is changed. The force mode may be switched to the display mode.

[0367] The display unit 1002 can also function as an image sensor. When the palm or finger is touched to 002, the palm print, fingerprint, etc. are captured to authenticate the user. In addition, if the display unit 1002 is provided with a backlight that emits near-infrared light or a By using a light-emitting sensing light source, it is also possible to capture images of finger veins, palm veins, etc.

[0368] The mobile phone shown in FIG. 28B includes a housing 9411, a display portion 9412, operation buttons, and a A display device 9410 including 9413, an operation button 9402 on a housing 9401, and an external input terminal 9403, a microphone 9404, a speaker 9405, and a light emitting unit 9406 that emits light when a call is received. The display device 9410 having a display function is a telephone. The communication device 9400 has all the functions and is detachable as shown by the arrow, and the display device 941 The display device 9410 and the communication device 9400 can be attached to each other on their short axes. The long axes of 00 can also be attached together. If you only need the display function, The display device 9410 can be removed from the device 9400 and used alone. The communication device 9400 and the display device 9410 may be connected to each other by wireless communication or wired communication. Images and input information can be sent and received via communication, and each device has a rechargeable battery. It is good to have.

[0369] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is Noh. EXAMPLES

[0370] One method for checking the reliability of transistors is the bias-thermal stress test (hereafter The BT test is a type of accelerated test, and is used to measure the effects of long-term use. The resulting changes in transistor characteristics can be evaluated in a short time. The amount of change in the threshold voltage of a transistor during operation is an important index for investigating reliability. The smaller the change in threshold voltage before and after the BT test, the higher the reliability.

[0371] Specifically, the temperature of the substrate on which the transistor is formed (substrate temperature) is kept constant, The source and drain of the transistor are at the same potential, and the gate is connected to the source and drain. Different potentials are applied for a certain period of time. The substrate temperature can be set appropriately depending on the purpose of the test. When the potential applied to the gate is higher than the potentials of the source and drain, this is called a +BT test. When the potential applied to the gate is lower than the potentials of the source and drain, this is called a -BT test. .

[0372] The test strength of the BT test is determined by the substrate temperature, the electric field strength applied to the gate insulating film, and the electric field application time. The electric field strength in the gate insulating film can be determined by the gate, source and drain. It is determined by dividing the potential difference between the gate electrodes by the thickness of the gate insulating film. If you want to set the electric field strength in the gate insulating film to 2MV / cm, you should set the potential difference to 20V. stomach.

[0373] In this embodiment, a heat treatment is performed before the formation of a source and a drain in the manufacture of a transistor. The treatment was carried out in a nitrogen atmosphere at 250℃, 350℃, and 450℃. The results of the BT test will be explained.

[0374] Voltage refers to the potential difference between two points, and potential refers to the static It refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in an electric field. In an electronic circuit, the difference between the potential at a certain point and a reference potential (for example, ground potential) Since the potential difference is often expressed as the potential at a certain point, in the following explanation, The difference between the potential at a certain point and a reference potential (for example, ground potential) is called the potential at the certain point. When a potential is shown, the potential at a certain point is used as the potential unless otherwise specified. Also called pressure.

[0375] The BT test was performed at a substrate temperature of 150°C, an electric field strength in the gate insulating film of 2MV / cm, and The test was performed for 1 hour for both +BT and -BT tests.

[0376] First, the +BT test will be explained. The initial characteristics of the transistor to be tested for the BT test are For the measurement, the substrate temperature was set to 40°C, and the source-drain voltage (hereafter referred to as drain voltage) The source-gate voltage (hereafter referred to as the gate voltage) is set to -20V to + Change in source-drain current (hereafter referred to as drain current) when the voltage is changed up to 20V The characteristics, i.e., the Vg-Id characteristics, were measured. Here, the substrate temperature was adjusted to prevent moisture absorption on the sample surface. The recommended temperature is 40°C, but if there are no particular problems, measurements can be taken at room temperature (25°C). do not have.

[0377] Next, the substrate temperature was raised to 150°C, and then the source and drain of the transistor were The potential was set to 0 V. Next, the gate insulating film was heated so that the electric field strength in the gate insulating film was 2 MV / cm. A voltage was applied to the gate of the transistor. Therefore, +20V was applied to the gate and held for 1 hour. However, the time may be changed appropriately depending on the purpose.

[0378] Next, while applying voltage to the source, drain, and gate, the substrate temperature was lowered to 40°C. If the voltage application is stopped before the substrate temperature drops completely, the residual heat can cause The damage to the transistor is repaired by this, so the voltage remains applied and the base The substrate temperature must be lowered. After the substrate temperature reached 40°C, the voltage application was stopped.

[0379] Next, the Vg-Id characteristics were measured under the same conditions as those for measuring the initial characteristics, and the Vg-Id characteristics after the +BT test were d characteristics were obtained.

[0380] Next, we will explain about the -BT test. The -BT test is conducted in the same manner as the +BT test. The difference is that the voltage applied to the gate is set to -20 V after the substrate temperature is raised to 150°C. become.

[0381] In addition, when conducting the BT test, transistors that have never been subjected to the BT test are used. It is important to perform testing. For example, using a transistor that has already undergone +BT testing, When the BT test is performed, the -BT test results are not correctly evaluated due to the influence of the +BT test performed earlier. It is not possible to perform a +BT test again using a transistor that has already been subjected to a +BT test. However, taking these effects into account, we decided to repeat the BT test. This does not apply if:

[0382] 29(A) to 29(C) show the Vg-Id of a transistor before and after a +BT test. FIG. 29(A) shows the characteristics of the heat treatment performed before the formation of the source and drain in a nitrogen atmosphere. The results of the +BT test of a transistor fabricated at 250°C in the same room are shown in Fig. 29(B). FIG. 29(C) shows the +BT test results at 50°C, and FIG. 29(D) shows the +BT test results at 450°C.

[0383] 30(A) to 30(C) show the Vg-Id of a transistor before and after the -BT test. FIG. 30(A) shows the characteristics of the heat treatment performed before the formation of the source and drain in a nitrogen atmosphere. The results of the -BT test of the transistor fabricated at 250°C in the same room are shown in Fig. 30(B). FIG. 30(C) shows the results of the -BT test at 50°C, and FIG. 30(D) shows the results of the -BT test at 450°C.

[0384] In the above-mentioned FIGS. 29 and 30, the second gate electrode is a titanium layer (50 nm). A three-layer laminate structure was created by laminating an aluminum layer (100 nm) and a titanium layer (5 nm). The second gate electrode was configured to be routed independently for each pixel. The results of the +BT test in the case where the second gate electrode was not provided are shown in FIG. The results are shown in Figure 32. Figure 31(A) shows the results at 250°C, Figure 31(B) shows the results at 350°C, and Figure 31(C) shows the results at 350°C. C) shows the +BT test results at 450°C. FIG. 32(B) shows the results of the -BT test at 350°C, and FIG. 32(C) shows the results of the -BT test at 450°C.

[0385] In each figure, the horizontal axis represents the gate voltage (Vg) and the vertical axis represents the drain current (Id) on a logarithmic scale. The solid line indicates the initial characteristics, and the dashed line indicates the characteristics after the stress is applied.

[0386] 29 and 31, the heat treatment temperature is increased to 250° C., 350° C., and 450° C. It can be seen that the change in threshold voltage after the +BT test becomes smaller accordingly. 30 and 32, it is clear that the threshold after the -BT test is improved by providing the second gate electrode. It can be seen that the amount of change in the low voltage becomes smaller.

[0387] 29 and 31, the temperature of the heat treatment performed before the source and drain formation is about 400° C. In the above case, the reliability of at least the +BT test can be improved. 30 and 32, the reliability of the -BT test is improved by providing a second gate electrode. Therefore, the temperature of the heat treatment performed before the source and drain formation can be set to about 4000 . By setting the temperature at 00°C or higher and providing a second gate electrode, the signal quality in the +BT test and -BT test is improved. The reliability can be improved.

[0388] As described above in this embodiment, one aspect of the present invention improves the reliability in the +BT test and the -BT test. Both can improve reliability in BT testing.

[0389] In addition, transistors with high reliability in the -BT test are used in the drive circuitry of display devices. It is particularly effective to apply this to the driver circuit of the above. EXAMPLES

[0390] In this example, the heating temperature conditions were varied, and several samples were subjected to heat treatment under a nitrogen atmosphere. Thermal Desorption Spectroscopy. The results of the TDS measurements are shown in Figures 34, 35, and 36. Please refer to the following for explanation.

[0391] TDS is a method for detecting gas components that are desorbed and generated from a sample while the sample is heated in a high vacuum. It is an analytical device that detects and identifies gases and gases desorbed from the surface and inside of a sample using a mass spectrometer. Molecules can be observed. The measurement conditions were a temperature rise of about 10°C / min and a rate of 1×10 -8 Start measuring at (Pa), During measurement, the -7 (Pa) is the degree of vacuum.

[0392] Figure 34 shows a comparison sample with only a glass substrate and a sample with a thickness of 50 nm ( In reality, the film is an In-Ga-Zn-O non-single crystal film with a thickness of about 30 nm (since it is actually etched). FIG. 34 is a graph showing the TDS measurement results in comparison with a sample (sample 1) on which a film was formed. The figure shows the results of TDS measurement for H2O, and a peak is observed around 300°C. As a result, impurities such as moisture (H2O) are released from the In-Ga-Zn-O non-single crystal film. It can be confirmed that this is the case.

[0393] FIG. 35 shows a non-single crystal film of In-Ga-Zn-O system formed on a glass substrate with a set thickness of 50 nm. The sample with the In-Ga-Zn-O film (sample 1) and the In-Ga-Zn-O film with a thickness of 50 nm on a glass substrate After the formation of the non-single crystal film, it is heated at 350°C for 1 hour in air. The sample (sample 2) was heated at 350°C for 1 hour in a nitrogen atmosphere. This is a comparison of the treated sample (sample 3) and the TDS measurement of H2O. The results of Fig. 35 show that in sample 3, the peak temperature in the vicinity of 300°C The moisture content of the sample is reduced compared to sample 2, so the moisture content (H2 It can be seen that impurities such as oxygen (O) are eliminated. Heat treatment in a nitrogen atmosphere reduces the amount of moisture (H2O) in the film. It can be seen that the impurities are reduced.

[0394] FIG. 36 shows a non-single crystal film of In-Ga-Zn-O system formed on a glass substrate with a set thickness of 50 nm. The coated sample (sample 1) was heated at 250°C for 1 hour in a nitrogen atmosphere. The treated sample (sample 4) was heated at 350°C for 1 hour in a nitrogen atmosphere. The sample (sample 3) was heated at 450°C in a nitrogen atmosphere. A sample that was heated for 1 hour (sample 5) and a sample that was heated at 350°C in a nitrogen atmosphere The results are compared with those of the sample (Sample 6) that was heated for 10 hours. The results of TDS measurements at various temperatures are shown in Figure 36. In the case of the In-Ga-Zn-O system non-single crystal film, the higher the heating temperature in the nitrogen atmosphere, the more the amount of It can be seen that impurities such as moisture (H2O) that desorb from the catalyst are reduced.

[0395] The graphs in Figures 35 and 36 show that moisture (HO) can be confirmed at temperatures between 200 and 250°C. The first peak indicates the desorption of impurities such as water (H2O) at around 300°C. A second peak can be seen which indicates which impurity has been desorbed.

[0396] The sample that was heat-treated at 450°C in a nitrogen atmosphere was then placed in air at room temperature for 1 Even after leaving it for about a week, no moisture was observed to desorb at temperatures above 200°C. It has been found that Ga-Zn-O based non-single crystal films are stable.

[0397] Here, the heating temperature conditions under a nitrogen atmosphere were 150°C, 175°C, 200°C, 225°C, 250℃, 275℃, 300℃, 325℃, 350℃, 375℃, 400℃, 425℃, The carrier concentration was measured at 450° C. and the results are shown in FIG. When an oxide insulating film is formed on a Ga-Zn-O based non-single crystal film, the capacitance shown by the dotted line in FIG. Rear concentration (1×10 14 / cm 3 )The result is as follows.

[0398] Next, the measurement of carrier concentration and Hall mobility will be explained. 7(A) shows the physical properties (carrier concentration) of an oxide semiconductor film (In-Ga-Zn-O-based non-single crystal film). The figure shows a stereoscopic view of a physical property evaluation sample 510 for evaluating the surface roughness (absolute surface roughness and Hall mobility). A physical property evaluation sample 510 was prepared and the Hall effect was measured at room temperature. The carrier concentration and Hall mobility were evaluated. The physical property evaluation sample 510 was a SiO2 film on a substrate 500. An insulating film 501 made of silicon nitride is formed, and a 10 mm×10 An oxide semiconductor film 502 having a diameter of 1 mm is formed on the oxide semiconductor film 502, and an electrode 503 having a diameter of 1 mm and an electrode 504, electrodes 505 and 506 were formed. FIG. 37(C) shows the results of measuring the mobility and the conductivity. The carrier concentration of the oxide semiconductor film obtained by the measurement is shown in FIG.

[0399] From the results in Figs. 33, 34, 35, and 36, it is clear that at temperatures above 250°C, In-Ga-Z The desorption of impurities such as water (H2O) from the nO-based non-single crystal film and the carrier concentration In other words, the In-Ga-Zn-O system non-single crystal film The increase in carrier concentration occurs when impurities such as moisture (HO) are removed from the You can understand.

[0400] In addition to H2O, TDS measurements revealed H, O, OH, H2, O2, N, N2, and When measurements were performed for each of the Ar species, H, O, and OH had clear peaks. However, no peaks were observed for H2, O2, N, N2, or Ar. is a non-single crystal In-Ga-Zn-O film with a thickness of 50 nm formed on a glass substrate. The heating conditions were 250°C for 1 hour in a nitrogen atmosphere and 350°C for 1 hour in a nitrogen atmosphere. 10 hours at 350°C in a nitrogen atmosphere, and 1 hour at 450°C in a nitrogen atmosphere as a comparative example. The measurements were taken of an untreated In-Ga-Zn-O non-single crystal film and a glass substrate alone. FIG. 38 shows the TDS results for H, FIG. 39 shows the TDS results for O, and FIG. 40 shows the TDS results for OH. Figure 41 shows the TDS result of H2. The oxygen density of the atmosphere is less than 20 ppm. EXAMPLES

[0401] In this embodiment, a method for manufacturing an oxide semiconductor layer having a high oxygen density region and a low oxygen density region is described. The results of the calculation of the oxygen diffusion phenomenon accompanying the heat treatment are shown in Figures 42 and 43. The calculation software used here is Mat Serials Explorer 5.0 was used.

[0402] FIG. 42 shows a model of the oxide semiconductor layer used in the calculation. Here, the oxide semiconductor layer 7 01 had a structure in which a layer with high oxygen density 705 was laminated on a layer with low oxygen density 703.

[0403] Here, the low oxygen density layer 703 is composed of 15 In atoms, 15 Ga atoms, and 15 The amorphous structure was composed of 100 Zn atoms and 54 O atoms.

[0404] The oxygen-rich layer 705 is composed of 15 In atoms, 15 Ga atoms, and 15 The amorphous structure was composed of a Zn atom and 66 O atoms.

[0405] The density of the oxide semiconductor layer 701 is 5.9 g / cm 3 It was decided.

[0406] Next, the oxide semiconductor layer 701 was subjected to the following treatment under the conditions of an NVT ensemble and a temperature of 250° C. Classical MD (molecular dynamics) calculations were performed. The time step size was 0.2 fs, and the total calculation time was 20 The potential was set to 0 ps. The Born potential was applied to the metal-oxygen bond and the oxygen-oxygen bond. In addition, the upper and lower ends of the oxide semiconductor layer 701 are The movement of the edge atoms is fixed.

[0407] Figure 43 shows the calculation results. The area from 0 nm to 1.15 nm on the z-axis coordinate has low oxygen density. The oxygen-rich layer 703 is located between 1.15 nm and 2.3 nm on the z-axis. The oxygen density distribution before the MD calculation is shown by the solid line 707, and the oxygen density distribution after the MD calculation is shown by the solid line 708. is indicated by dashed line 709.

[0408] In the solid line 707, the oxygen density is higher than the interface between the low oxygen density layer 703 and the high oxygen density layer 705. Therefore, the oxygen density is high in the layer 705 with high oxygen density. The oxygen density is uniform in the low oxygen density layer 703 and the high oxygen density layer 705. It can be seen that...

[0409] From the above, it appears that the layer 703 with low oxygen density and the layer 705 with high oxygen density are laminated. In addition, if there is a bias in the distribution of oxygen density, the oxygen concentration will spread from high to low density areas by heat treatment. It can be seen that the oxygen disperses and the oxygen density becomes uniform.

[0410] That is, as shown in Embodiment 1, a semiconductor layer 403 is formed on the oxide semiconductor layer 403 by using an insulating oxide. By forming the first protective insulating layer 407, the oxide semiconductor layer 403 and the insulating oxide Therefore, the oxygen density increases at the interface of the first protective insulating layer 407, and the oxygen is converted into an oxide semiconductor. The oxygen diffuses toward the area of ​​the conductor layer 403 where the oxygen density is low, and the resistance of the oxide semiconductor layer 431 increases. Therefore, the reliability of the transistor included in the display device according to one embodiment of the present invention can be improved. It is possible. [Explanation of symbols]

[0411] 10 Substrate 11 Gate electrode 13 Gate insulating layer 14a n-type oxide semiconductor layer 14b n-type oxide semiconductor layer 15a Source electrode layer 15b Drain electrode layer 16 Oxide semiconductor layer 17 Resin layer 18 Protective insulation layer 19 Gate electrode 20 Transistor 42 Gate electrode 43 Transistor 44 Contact Hole 47 Oxide semiconductor layer 400 Substrates 401 Gate electrode layer 401C Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor layer 404 n-type oxide semiconductor layer 404a n-type oxide semiconductor layer 404b n-type oxide semiconductor layer 405 Source and drain electrode layers 405a Source electrode 405b Drain electrode 406 Channel Protection Layer 407 Protective Insulation Layer 408 Resin layer 408a Buffer layer 408b Buffer layer 409 Gate electrode layer 409B Gate electrode layer 409C Gate electrode layer 410 Undercoat insulation layer 411 Terminal 430 Oxide semiconductor layer 431 Oxide Semiconductor Layer 432 Oxide semiconductor layer 433 Oxide Semiconductor Film 434 n-type oxide semiconductor layer 437 n-type oxide semiconductor layer 440 n-type oxide semiconductor film 470 Gate electrode layer 471 Transistor 471B Transistor 471C Transistor 472 Transistors 472B Transistor 473 Transistor 473B Transistor 474 Transistor 474B Transistor 500 boards 501 Insulating film 502 Oxide semiconductor film 503 Electrode 504 Electrode 505 Electrode 506 Electrode 510 Physical property evaluation samples 581 Transistor 582 Gate electrode 584 Protective Insulation Layer 585 Resin layer 586 Protective Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 601 Electric furnace 602 Chamber 603 Heater 604 Substrate 605 Susceptor 606 Gas Supply Means 607 Exhaust means 611 Gas supply source 612 Pressure Regulating Valve 613 Purifier 614 Mass Flow Controller 615 Stop valve 701 Oxide semiconductor layer 703 Low oxygen density layer 705 Oxygen-dense layer 707 Solid Line 709 Dashed Line 800 boards 801 Pixel section 802 Scanning line driver circuit 802A Scanning line driver circuit 802B Scanning line driver circuit 803 Signal line driver circuit 804 Transistor 820 Substrate 822 Signal line input terminal 823 scan lines 823A Scan Line 823B Control Line 823C Scan Line 823D Scan Line 824 Signal Line 827 Pixel section 828 pixels 829 Pixel Transistor 830 Holding capacity section 831 Pixel electrode 832 Capacitive Line 833 Common Terminal 835 Protection circuit 1000 Mobile Phones 1001 Case 1002 Display section 1003 Operation button 1004 External connection port 1005 Speaker 1006 Mike 1101 Conductive layer 1102 Oxide semiconductor layer 1103 Conductive layer 1104 Pixel electrode layer 1105 Conductive layer 1106 Opening 2600 Element Substrate 2601 Opposing substrate 2602 Sealing material 2603 Element Layer 2604 Liquid crystal layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610B Light Emitting Diode 2610G Light Emitting Diode 2610R Light Emitting Diode 2611 Reflector 2612 Circuit Board 2613 Optical Sheet 2614 LED control circuit 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4003a Signal line driver circuit 4003b Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4007 Undercoat insulation layer 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4017 Anisotropic conductive film 4018 FPC 4019 Gate insulation layer 4020 Protective insulation layer 4021 Resin layer 4022 Protective insulation layer 4028 Gate electrode 4029 Gate electrode 4030 Pixel electrode layer 4031 Common electrode layer 4032 Polarizing plate 4033 Polarizing plate 4034 Light blocking layer 4035 Post Spacer 4500 Board 4501 Gate insulation layer 4502 Pixel section 4503 Filling material 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scanning line driver circuit 4504b Scanning line driver circuit 4505 Sealing material 4506 Board 4507 Protective layer 4508 Resin layer 4509 Transistor 4510 Transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4514 Protective insulation layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4518b FPC 4519 Anisotropic conductive film 4520 Bulkhead 4521 Gate electrode 4522 Gate electrode 6400 pixels 6401 Switching transistor 6402 Driving transistor 6403 Capacitor 6404 Light emitting element 6405 Signal Line 6406A Scan Line 6406B Control Line 6407 Power line 6408 Common electrode 7001 Transistor 7002 Light emitting element 7003 Cathode 7004 Light-emitting layer 7005 Anode 7006 Bulkhead 7007 Protective layer 7009 Gate electrode 7010 Conductive film 7011 Transistor 7012 Light emitting element 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding membrane 7017 Resin layer 7018 Protective insulation layer 7019 Gate electrode 7021 Transistor 7022 Light emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive film 7028 Connection electrode 7029 Gate electrode 9400 Communication Equipment 9401 Case 9402 Operation button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light emitting part 9410 Display device 9411 Housing 9412 Display section 9413 Operation button 9600 Wall 9601 Case 9603 Display section 9607 Display section 9609 Operation key 9610 Remote control device 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section

Claims

[Claim 1] A method for manufacturing a display device having a pixel portion including a transistor and a driver circuit portion, comprising the steps of: forming a gate electrode layer on a substrate having an insulating surface; forming a gate insulating layer covering the gate electrode layer; forming an oxide semiconductor layer on the gate insulating layer; dehydrating or dehydrogenating the oxide semiconductor layer; forming a source electrode and a drain electrode layer on the dehydrated or dehydrogenated oxide semiconductor layer; forming a protective layer on the gate insulating layer, the dehydrated or dehydrogenated oxide semiconductor layer, the source electrode, and the drain electrode layer, the protective layer being made of an insulating oxide film in contact with a part of the oxide semiconductor layer; The method for manufacturing a display device further comprises forming a gate electrode layer on the protective layer to manufacture at least a transistor in the driver circuit portion.

Images