Driver device, control method, and inverter device

Abstract

To provide a driver device, etc. capable of suppressing waste of electric charge of a bootstrap capacitor.SOLUTION: A driver device comprises: a high potential side transistor 134H and a low potential side transistor 134L which are connected in series; a high potential side driver 135H which generates a high potential side control signal whose pulse width is controlled by a duty ratio for a switching operation of the high potential side transistor 134H; a low potential side driver 135L which generates a low potential side control signal complementary to the high potential side control signal for a switching operation of the low potential side transistor 134L; a driver power supply 5 which supplies power to the low potential side driver 135L; a bootstrap circuit 6 which supplies power to the high potential side driver 135H; and a duty ratio limiting unit 42 which allows a duty ratio of "zero" and limits a duty ratio from "zero" to a predetermined limit value for the low potential side control signal.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a driver device and the like. [Background technology]

[0002] As disclosed in Patent Document 1, a power supply method that uses a so-called bootstrap circuit is known as a power supply method for supplying power to a driver pair that complementarily drives a high-side and low-side transistor pair. The bootstrap circuit includes a driver power supply that directly supplies power to the low-side driver, and a bootstrap diode and a bootstrap capacitor that are connected in series between the connection point (output point) of the high-side transistor and the low-side transistor. When the low-side transistor is in the on-state, the bootstrap capacitor is charged by the current that flows through the bootstrap diode from the driver power supply. The high-side driver drives the high-side transistor using the bootstrap capacitor charged in this way as a power supply. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2003-133924 A Summary of the Invention [Problem to be solved by the invention]

[0004] As described above, the bootstrap capacitor is charged when the low-side transistor is in the on-state, but generally, a transistor requires a transition time (hereinafter also referred to as dead time) to transition from an off-state to an on-state. Therefore, if the width of the pulse applied to the control terminal of the low-side transistor is equal to or shorter than the dead time, the low-side transistor cannot transition from an off-state to an on-state, and the bootstrap capacitor is not charged. On the other hand, the high-side transistor transitions from an on-state to an off-state, and returns to an on-state again after a short time (and the dead time) corresponding to the small pulse width. In this way, when the high-side transistor returns to an on-state from a short off-state, the charge of the bootstrap capacitor is consumed. Therefore, if the width of the pulse applied to the control terminal of the low-side transistor is equal to or shorter than the dead time, the bootstrap capacitor is not charged by the low-side transistor, and the stored charge is instead consumed by the high-side transistor. As a result of the charge of the bootstrap capacitor decreasing in this way, there is a risk of causing a problem in driving the high-side transistor.

[0005] The present disclosure has been made in consideration of these circumstances, and has an object to provide a driver device and the like that can suppress waste of charge in a bootstrap capacitor. [Means for solving the problem]

[0006] In order to solve the above problems, a driver device according to an embodiment of the present disclosure includes two switching elements connected in series, a high-side switching element on a high-side side and a low-side switching element on a low-side side, a high-side driver that generates a high-side control signal whose pulse width is controlled by a duty ratio for the switching operation of the high-side switching element, a low-side driver that generates a low-side control signal complementary to the high-side control signal for the switching operation of the low-side switching element, a driver power supply that supplies power to the low-side driver, a bootstrap circuit including a bootstrap diode and a bootstrap capacitor connected in series between the driver power supply and a connection point of the high-side switching element and the low-side switching element, and a duty ratio limiting unit that allows a duty ratio of "0" for the low-side control signal and limits the duty ratio from "0" to a predetermined limit value.

[0007] In this embodiment, a duty ratio of "0" is permitted for the low-potential side control signal, and the duty ratio is limited to a range from "0" to a predetermined limit value. At a duty ratio below the limit value, the pulse width does not exceed the dead time, and as described above, there is a risk that the bootstrap capacitor will not be charged and the charge will be wasted, but the use of such a low duty ratio is restricted in this embodiment. However, at a duty ratio of "0", the bootstrap capacitor is not charged by the low-potential side switching element, but the high-potential side switching element is maintained in the on state by a duty ratio of "1", so the charge of the bootstrap capacitor is not consumed. In this way, a duty ratio of "0" is exceptionally permitted because it does not result in the waste of the charge of the bootstrap capacitor.

[0008] Another aspect of the present disclosure is a control method, which is a driver device including two switching elements connected in series, the high-side switching element on a high potential side and the low-side switching element on a low potential side, a high-side driver generating a high-side control signal whose pulse width is controlled by a duty ratio for the switching operation of the high-side switching element, a low-side driver generating a low-side control signal complementary to the high-side control signal for the switching operation of the low-side switching element, a driver power supply supplying power to the low-side driver, and a bootstrap circuit including a bootstrap diode and a bootstrap capacitor connected in series between the driver power supply and the connection point of the high-side switching element and the low-side switching element, and which executes the following: permitting a duty ratio of "0" for the low-side control signal, and limiting the duty ratio from "0" to a predetermined limit value.

[0009] Yet another aspect of the present disclosure is an inverter device comprising: a high-potential side switching element on a high potential side and a low-potential side switching element on a low potential side, which are two switching elements connected in series between a high potential line and a low potential line, and which output AC from a connection point between the high potential side switching element and the low potential side switching element; a high potential side driver generating a high potential side control signal whose pulse width is controlled by a duty ratio for a switching operation of the high potential side switching element; a low potential side driver generating a low potential side control signal complementary to the high potential side control signal for a switching operation of the low potential side switching element; a driver power supply supplying power to the low potential side driver; a bootstrap circuit including a bootstrap diode and a bootstrap capacitor connected in series between the driver power supply and the connection point between the high potential side switching element and the low potential side switching element; and a duty ratio limiting unit allowing a duty ratio of "0" for the low potential side control signal and limiting the duty ratio from "0" to a predetermined limit value.

[0010] Any combination of the above components, or any conversion of these components into a method, device, system, recording medium, computer program, or the like, is also encompassed by the present disclosure. Effect of the Invention

[0011] According to the present disclosure, waste of charge in the bootstrap capacitor can be suppressed. [Brief description of the drawings]

[0012] [Figure 1] 1 shows a schematic diagram of an inverter device. [Diagram 2] The output voltage waveforms at the output terminals of each phase, UVW, when the inverter is outputting three-phase AC are shown diagrammatically. [Diagram 3] 1 illustrates a schematic diagram of a driver device. [Figure 4] 1 shows a schematic example of charging and discharging a bootstrap capacitor. [Diagram 5] 13 shows a schematic example of a case where the command value of the duty ratio of the low potential side control signal is close to the minimum value "0". [Figure 6] An example is shown in which a duty ratio limiting unit is applied to a command value of the same duty ratio as in FIG. [Figure 7] A modification of FIG. 3 is shown. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] In the following, the form for carrying out the present disclosure (hereinafter, also referred to as an embodiment) will be described in detail with reference to the drawings. In the description and / or drawings, the same or equivalent components, members, processes, etc. will be given the same reference numerals, and duplicated descriptions will be omitted. The scale and shape of each part shown in the drawings are set for convenience in order to simplify the description, and are not to be interpreted as being limiting unless otherwise specified. The embodiment is an example, and does not limit the scope of the present disclosure in any way. All features and their combinations presented in the embodiment are not necessarily essential to the present disclosure. The embodiment is presented by decomposing it into components for each function and / or each functional group that realizes it for convenience. However, one component in the embodiment may be realized by a combination of multiple components that are actually separate, or multiple components in the embodiment may be realized by one component that is actually integrated. In addition, multiple embodiments and variations may be disclosed in parallel, but any components of each embodiment and / or each variation may be combined in any manner as long as they do not inhibit each other's functions.

[0014] 1 is a schematic diagram showing an inverter device 10 according to the present embodiment, which supplies single-phase or multi-phase AC to a motor 20. The inverter device 10 includes a converter 11 that rectifies three-phase AC, i.e., R-phase, S-phase, and T-phase, supplied from a commercial power source or the like, and converts it into DC (pulsating current), a smoothing capacitor 12 that smoothes the DC converted by the converter 11 to shape the waveform, and an inverter 13 that converts the DC smoothed by the smoothing capacitor 12 into AC.

[0015] The converter 11 includes diodes 111 to 116 that rectify three-phase (R, S, T) AC current supplied from a commercial power source or the like in a fixed direction (from bottom to top in the figure). The diode 111 passes a current when the R-phase AC voltage is positive, the diode 112 passes a current when the R-phase AC voltage is negative, the diode 113 passes a current when the S-phase AC voltage is positive, the diode 114 passes a current when the S-phase AC voltage is negative, the diode 115 passes a current when the T-phase AC voltage is positive, and the diode 116 passes a current when the T-phase AC voltage is negative. The diodes 111 to 116 connected in a bridge shape in this way cause a pulsating current with a fixed direction and varying magnitude to appear between the output terminals of the converter 11. The smoothing capacitor 12 supplies a direct current that has been smoothed from the pulsating current obtained by the converter 11 to the inverter 13.

[0016] In the following, a DC voltage input between a high potential input terminal 131 and a low potential input terminal 132 of an inverter 13 via a converter 11 and a smoothing capacitor 12 is referred to as V DC The potential of the high potential line to which the high potential input terminal 131 is connected is represented as V dd , the potential of the low potential line to which the low potential input terminal 132 is connected is V ss Then, V DC =V dd -V ss It is.

[0017] The inverter 13 outputs a high-voltage DC dd The high-potential line that supplies the DC ss In other words, the inverter 13 outputs a three-phase AC voltage V input between a high potential input terminal 131 and a low potential input terminal 132 by switching operations of three-phase transistor pairs of U-phase, V-phase, and W-phase that are connected in parallel between the low potential lines that supply the DC voltage V DC Specifically, a three-phase AC voltage is generated based on the DC voltage V DC and a U-phase inverter 13U that generates a U-phase AC voltage based on DC A V-phase inverter 13V generates a V-phase AC current based on DCA W-phase inverter 13W that generates a W-phase AC based on the above is provided in parallel. Since the inverters 13U, 13V, and 13W of each phase have a common configuration, they will be collectively referred to as inverter 13 as appropriate and described below.

[0018] The inverter 13 is connected to a high DC power supply potential V dd A high-potential input terminal 131 to which a low DC power supply potential V ss A low potential input terminal 132 to which V is input is provided between the high potential input terminal 131 and the low potential input terminal 132. dd and V ss and an AC output terminal 133 that outputs an AC voltage that fluctuates between a high potential line and the AC output terminal 133. A high potential side transistor 134H is connected between the high potential line and the AC output terminal 133 as a high potential side switching element, and a low potential side transistor 134L is connected between the low potential line and the AC output terminal 133 as a low potential side switching element.

[0019] The high-side transistor 134H performs a switching operation to switch the conductive state of the current path in response to a pulse (high-side control signal) supplied from a high-side driver 135H connected to its control terminal as a driver. The low-side transistor 134L performs a switching operation to switch the conductive state of the current path in response to a pulse (low-side control signal) supplied from a low-side driver 135L connected to its control terminal as a driver. In the following, the high-side transistor 134H and the low-side transistor 134L are collectively referred to as transistor 134 or transistor pair 134 as appropriate, and the high-side driver 135H and the low-side driver 135L are collectively referred to as driver 135 or driver pair 135 as appropriate. In the following description, "H" meaning "high side" and "L" meaning "low side" are omitted as appropriate, but "H" and "L" are added to the end of the symbols as necessary in the drawings.

[0020] In the illustrated example, the transistor 134 is an insulated gate bipolar transistor (IGBT) having a gate 31 as a control terminal, a collector 32 as a high potential side terminal connected to the high potential line side, and an emitter 33 as a low potential side terminal connected to the low potential line side. However, the transistor 134 or the switching element may be a field effect transistor (FET) having a gate as a control terminal, a drain as a high potential side terminal, and a source as a low potential side terminal, or may be a bipolar transistor having a base as a control terminal, a collector as a high potential side terminal, and an emitter as a low potential side terminal.

[0021] In the high-side transistor 134H, the gate 31H is connected to the high-side driver 135H, the collector 32H is connected to the high-side input terminal 131 or the high-side line, and the emitter 33H is connected to the AC output terminal 133 and the collector 32L of the low-side transistor 134L. In the low-side transistor 134L, the gate 31L is connected to the low-side driver 135L, the collector 32L is connected to the AC output terminal 133 and the emitter 33H of the high-side transistor 134H, and the emitter 33L is connected to the low-side input terminal 132 or the low-side line. In the above configuration, the connection point of the emitter 33H of the high-side transistor 134H and the collector 32L of the low-side transistor 134L forms the AC output terminal 133.

[0022] In each transistor 134, the current path or channel between the collector 32 and the emitter 33 switches its conductive state in response to a pulse (control signal) applied from each driver 135 to the gate 31. A protection diode 34 may be provided in parallel with this current path or channel as a protection diode element. The protection diode 34 may be a discrete element separate from the transistor 134, or may be formed integrally or monolithically with the transistor 134 in the semiconductor manufacturing process for manufacturing the transistor 134. The protection diode 34 is provided so as to pass a current only in the direction from the low potential line side to the high potential line side.

[0023] The driver 135, which may be configured as an integrated circuit (IC), supplies a switching pulse as a control signal for a switching operation to the gate 31 of the transistor 134. For example, the driver 135 applies a pulse whose duty ratio or pulse width is controlled by PWM (Pulse Width Modulation) to the gate 31 of the transistor 134. The transistor 134 performs a switching operation in which it switches between an on state and an off state depending on the presence or absence of a pulse. Specifically, while a pulse is applied to the gate 31, the transistor 134 is in an on state, and a channel between the collector 32 and the emitter 33 is in a conductive state. Meanwhile, while a pulse is not applied to the gate 31, the transistor 134 is in an off state, and a channel between the collector 32 and the emitter 33 is in a non-conductive state.

[0024] The driver 135 of each phase converts DC to AC of each phase by performing switching control to complementarily switch the conductive state of the transistor pair composed of the high potential side transistor 134H and the low potential side transistor 134L under the control of a control unit (not shown). Here, "complementarily switching" means controlling so that the transistor pairs of each phase are not simultaneously turned on. In other words, when one transistor in each phase is turned on, the other transistor in the phase is controlled to be turned off. However, it is permitted that the transistor pairs of each phase are simultaneously turned off. In addition, the high potential side control signal for the high potential side transistor 134H and the low potential side control signal for the low potential side transistor 134L, which are in the above-mentioned relationship, are expressed as being "complementary" to each other.

[0025] Specifically, for the U phase, when the high potential side transistor 134H is in the ON state, the low potential side transistor 134L is controlled to be in the OFF state, and when the low potential side transistor 134L is in the ON state, the high potential side transistor 134H is controlled to be in the OFF state. Therefore, when the high potential side transistor 134H is in the ON state, a high potential V dd appears, and when the low-potential side transistor 134L is in the ON state, a low potential V ss By periodically repeating such switching control, a high potential V appears at the U-phase AC output terminal 133U. dd and low potential V ss A U-phase alternating current is generated in which

[0026] The three-phase AC generated by the inverter 13 as described above is supplied to the motor 20 that generates rotational power. The motor 20 is, for example, a three-phase brushless motor equipped with three-phase coils 20U, 20V, and 20W of U-phase, V-phase, and W-phase. A U-phase current flows from an AC output terminal 133U of the U-phase inverter 13U to the U-phase coil 20U, a V-phase current flows from an AC output terminal 133V of the V-phase inverter 13V to the V-phase coil 20V, and a W-phase current flows from an AC output terminal 133W of the W-phase inverter 13W to the W-phase coil 20W. The inverters 13U, 13V, and 13W of each phase apply three-phase ACs of different phases to the coils 20U, 20V, and 20W of each phase based on the rotational position of the rotor (not shown) detected by the hall elements H1, H2, and H3 of the motor 20 to generate a rotating magnetic field. A desired rotational power is obtained from the rotor that rotates by this rotating magnetic field. Note that motor 20 may be another type of motor driven by AC. The number of phases of motor 20 is not limited to three and may be any natural number. Similarly, the number of phases of the AC input to converter 11 is not limited to three and may be any natural number.

[0027] FIG. 2 shows the output voltage waveforms V at the output terminals 133U, 133V, and 133W of each phase UVW when the inverter 13 is outputting three-phase AC. U , V V , V W 1 is a schematic diagram showing the high-side and low-side control signals (pulses) applied to the gates 31 of the transistor pairs 134 by the high-side driver 135H and the low-side driver 135L of each of the UVW phases. dd and low potential V ss A sinusoidal AC voltage V fluctuating between U , V V , V W In three-phase AC, the AC voltage waveform of each phase is V U , V V , V W The phases of the high potential V dd and low potential V ss For convenience, the average value of is set to "0".

[0028] During the period when each of the output terminals 133U, 133V, and 133W outputs a positive voltage, the high-side driver 135H applies a pulse (high-side control signal) whose duty ratio changes stepwise between "0" and "1" to the gate 31H of the high-side transistor 134H, while the low-side driver 135L does not apply a pulse (low-side control signal) to the gate 31L of the low-side transistor 134L (i.e., the duty ratio or pulse width is "0"). In particular, when the high-side driver 135H applies a pulse with a duty ratio of "1" to the gate 31H of the high-side transistor 134H, the channel of the high-side transistor 134H is almost completely conductive with the high-side line, so that the output terminal 133 is supplied with V dd A high voltage approximately equal to

[0029] During the period when each of the output terminals 133U, 133V, and 133W outputs a negative voltage, the low-side driver 135L applies a pulse (low-side control signal) whose duty ratio changes stepwise between "0" and "1" to the gate 31L of the low-side transistor 134L, while the high-side driver 135H does not apply a pulse (high-side control signal) to the gate 31H of the high-side transistor 134H (i.e., the duty ratio or pulse width is "0"). In particular, when the low-side driver 135L applies a pulse with a duty ratio of "1" to the gate 31L of the low-side transistor 134L, the channel of the low-side transistor 134L is almost completely conductive with the low-side line, so that the output terminal 133 is supplied with V ss A low voltage approximately equal to

[0030] As described above, during normal operation when the inverter 13 is outputting three-phase AC, in the inverters 13U, 13V, and 13W of each of the UVW phases, a pulse whose duty ratio changes in stages is applied to only one of the high-side transistor 134H and the low-side transistor 134L, and no pulse is applied to the other of the high-side transistor 134H and the low-side transistor 134L (the duty ratio is "0").

[0031] Also, AC voltage V U , V V, V W V dd and V ss In order to change the output voltage in a smooth sine wave shape with a maximum amplitude between "0" and "1", it is preferable that the duty ratio of the pulse (control signal) applied to the gate 31 of each transistor 134 is controlled substantially continuously within the maximum range between the minimum value "0" and the maximum value "1". Specifically, during the period in which each transistor 134 outputs a positive or negative voltage, the duty ratio of the pulse (control signal) applied to the gate 31 of each transistor 134 increases continuously or stepwise from the minimum value "0" to the maximum value "1" (as described above, when the duty ratio is "1", the output voltage reaches the maximum value V dd or the minimum value V ss ), and then preferably decreases again continuously or stepwise to the minimum value of "0."

[0032] Fig. 3 shows a schematic diagram of a driver device according to this embodiment which may be configured integrally with an inverter 13. The same components as those in Fig. 1 are given the same reference numerals and redundant explanations will be omitted.

[0033] The high-side driver 135H and the low-side driver 135L operate based on power supplied from a driver power supply 5. Specifically, the driver power supply 5 supplies power directly to the low-side driver 135L, and indirectly to the high-side driver 135H via a bootstrap circuit 6, which will be described later.

[0034] The high potential side terminal 136L of the low potential side driver 135L is directly connected to the driver power supply 5, and the low potential side terminal 137L of the low potential side driver 135L is directly connected to the low potential input terminal 132. In this manner, the low potential side driver 135L is connected to the high potential of the driver power supply 5 and the low potential V ss The low-side driver 135L operates based on the voltage between the output terminal 138L and the gate 31L of the low-side transistor 134L. The output terminal 138L of the low-side driver 135L generates a low-side control signal whose pulse width is controlled by the duty ratio as described above. A gate resistor 139L may be provided between the output terminal 138L and the gate 31L of the low-side transistor 134L.

[0035] The bootstrap circuit 6 for supplying power to the high-side driver 135H includes a bootstrap diode 61 and a bootstrap capacitor 62. The bootstrap diode 61 and the bootstrap capacitor 62 are connected in series between the driver power supply 5 and the AC output terminal 133 which is the connection point of the high-side transistor 134H and the low-side transistor 134L.

[0036] The bootstrap diode 61, which is directly connected to the driver power supply 5, is provided so as to pass a current only in a direction from the driver power supply 5 to the bootstrap capacitor 62. The connection point between the bootstrap diode 61 and the bootstrap capacitor 62 is connected to a high potential side terminal 136H of the high potential side driver 135H. A low potential side terminal 137H of the high potential side driver 135H is connected to the low potential side electrode of the bootstrap capacitor 62 and the AC output terminal 133.

[0037] The high-side driver 135H operates using the charge stored in the bootstrap capacitor 62 as a power source. The output terminal 138H of the high-side driver 135H generates a high-side control signal whose pulse width is controlled by the duty ratio as described above. A gate resistor 139H may be provided between the output terminal 138H and the gate 31H of the high-side transistor 134H.

[0038] The bootstrap capacitor 62, which functions as the power supply for the high-side driver 135H, is charged when the low-side transistor 134L is in the on state, as shown by the arrow in Fig. 3. At this time, the high-side transistor 134H, which is controlled complementarily to the low-side transistor 134L, is in the off state. The current that charges the bootstrap capacitor 62 flows from the driver power supply 5 through the bootstrap diode 61, the bootstrap capacitor 62, and the low-side transistor 134L to the low-side input terminal 132.

[0039] The high-side driver 135H consumes the charge thus stored in the bootstrap capacitor 62 to control the switching of the high-side transistor 134H. Specifically, the charge of the bootstrap capacitor 62 is consumed when the high-side transistor 134H is changed from an OFF state to an ON state. To allow the high-side driver 135H to operate stably, it is necessary to charge the bootstrap capacitor 62 by switching the low-side transistor 134L to the ON state (i.e., switching the high-side transistor 134H to the OFF state) before the charge of the bootstrap capacitor 62 is excessively reduced.

[0040] 4 shows a schematic example of charging and discharging the bootstrap capacitor 62. In this example, unlike the example in FIG. 2, a pulse of a high-side control signal by the high-side driver 135H and a pulse of a low-side control signal by the low-side driver 135L appear alternately. As described above, the charge of the bootstrap capacitor 62 is consumed (discharged) at the rise of the high-side control signal for transitioning the high-side transistor 134H from an OFF state to an ON state. Subsequently, the bootstrap capacitor 62 is charged while the pulse of the low-side control signal is applied to the low-side transistor 134L by the low-side driver 135L.

[0041] As described above, the bootstrap capacitor 62 is charged when the low potential side transistor 134L is in the ON state, but a transistor generally requires a transition time or dead time to transition from an OFF state to an ON state, as shown in Fig. 4. During this dead time, the low potential side transistor 134L is in the ON state according to the duty ratio command, but in reality, the low potential side transistor 134L remains substantially in the OFF state, so that the bootstrap capacitor 62 cannot be charged.

[0042] This can be a problem when the command value for the duty ratio of the low-side control signal is close to the minimum value of "0", as shown in Fig. 5. In the example shown in the figure, a command value for a duty ratio close to "0" (e.g., "0.03") that is less than or equal to the dead time of the low-side transistor 134L is continuously given to the low-side control signal. Meanwhile, a command value for a duty ratio close to the maximum value of "1" (e.g., "0.95") is continuously given to the high-side control signal for the high-side transistor 134H.

[0043] In this way, when the width of the pulse (low-side control signal) applied to the gate 31L of the low-side transistor 134L is equal to or shorter than the dead time, the low-side transistor 134L cannot transition from the off state to the on state, and remains substantially in the off state. As a result, the bootstrap capacitor 62 is not charged. On the other hand, the high-side transistor 134H transitions from the on state to the off state based on the high-side control signal with a high duty ratio, and returns to the on state again after a short time corresponding to the small pulse width (and the dead time of the high-side transistor 134H). In this way, when the high-side transistor 134H returns to the on state from the off state for a short time, the charge of the bootstrap capacitor 62 is consumed (discharged).

[0044] Therefore, when the width of the pulse (low-side control signal) applied to the gate 31L of the low-side transistor 134L is equal to or shorter than the dead time, the bootstrap capacitor 62 is not charged by the low-side transistor 134L, and the stored charge is instead consumed by the high-side transistor 134H. As a result, as shown in FIG. 5, as the charge of the bootstrap capacitor 62 decreases, the magnitude or voltage of the high-side control signal that the high-side driver 135H can output gradually decreases, which may cause problems in the driving or switching operation of the high-side transistor 134H.

[0045] The driver device according to this embodiment, which is shown in FIG. 3, aims to suppress the waste of charge in the bootstrap capacitor 62 caused by the low-potential side control signal with a low duty ratio as described above.

[0046] For this purpose, the driver device according to this embodiment includes a duty ratio command unit 41, a duty ratio limiting unit 42, a frequency monitoring unit 43, and a charge monitoring unit 44. As long as the driver device can achieve at least some of the actions and / or effects described below, some of these functional blocks may be omitted. These functional blocks may be realized by the cooperation of hardware resources such as a central processing unit of a computer, a memory, an input device, an output device, and peripheral devices connected to the computer, and software executed using these. Regardless of the type of computer or the location where the computer is installed, each of the above functional blocks may be realized by the hardware resources of a single computer, or by combining hardware resources distributed among multiple computers.

[0047] The duty ratio command unit 41 generates duty ratio command values ​​for the high potential side control signal and the low potential side control signal. As in the example of FIG. 4 or FIG. 5, the duty ratio command unit 41 may generate duty ratio command values ​​that are completely complementary to each other for the high potential side control signal and the low potential side control signal. Specifically, when the duty ratio command value for the low potential side control signal is "x" (where "x" is any number between "0" and "1"), the duty ratio command value for the completely complementary high potential side control signal is "1-x". For example, when the duty ratio command value for the low potential side control signal is "0.04", the duty ratio command value for the completely complementary high potential side control signal is "0.96".

[0048] Alternatively, as in the example of FIG. 2, the duty ratio command unit 41 may generate a command value for a duty ratio that changes stepwise between "0" and "1" for one of the high potential side control signal and the low potential side control signal, while generating a command value for a constant duty ratio of "0" for the other duty ratio.

[0049] The duty ratio limiting unit 42 allows a duty ratio of "0" for the low potential side control signal, and limits the duty ratio from "0" to a predetermined limit value. Here, the limit value is preferably equal to or greater than the transition time or dead time for the low potential side transistor 134L to transition from an off state to an on state. For example, if the dead time of the low potential side transistor 134L is "0.03" in terms of duty ratio, the limit value is set to "0.04". In this way, it is preferable that the limit value is set to an arbitrary value that is equal to or greater than the dead time of the low potential side transistor 134L and as small as possible, but in a typical use case, a limit value greater than "0" and less than "0.05" is considered appropriate.

[0050] In the following example, the limit value is assumed to be "0.04". In this case, the duty ratio limiting unit 42 allows a duty ratio of "0" for the low potential side control signal, and limits the duty ratio from "0" to "0.04". In other words, the duty ratio limiting unit 42 allows a duty ratio of "0" and "0.04" to "1" for the low potential side control signal.

[0051] On the other hand, the duty ratio limiting unit 42 allows a duty ratio of "1" for a high potential side control signal that is completely complementary to the low potential side control signal, and limits the duty ratio from a value obtained by subtracting the limit value from "1" to "1". In the example of this embodiment in which the limit value is "0.04", the duty ratio limiting unit 42 allows a duty ratio of "1" for the high potential side control signal, and limits the duty ratio from "0.96" to "1". In other words, the duty ratio limiting unit 42 allows duty ratios of "1" and "0" to "0.96" for the high potential side control signal.

[0052] The duty ratio limiting unit 42 may update the command value for the low potential side control signal generated by the duty ratio command unit 41 to "0" when the command value is between "0" and "0.04" (limit value). At this time, the duty ratio limiting unit 42 may update the command value of the duty ratio for the high potential side control signal to "1". Alternatively, the duty ratio limiting unit 42 may update the command value for the high potential side control signal generated by the duty ratio command unit 41 to "1" when the command value is between "0.96" (a value obtained by subtracting the limit value from "1") and "1".

[0053] The problem shown in Fig. 5 is solved by limiting and / or forcibly overwriting the duty ratio in such a specific small range. Fig. 6 shows an example in which the duty ratio limiting unit 42 is applied to the same duty ratio command value as in Fig. 5. In this example, since the command value of the duty ratio for the low-potential side control signal generated by the duty ratio commanding unit 41 is "0.03" (schematically shown by a dotted line) which is less than the limit value "0.04", the command value is overwritten to "0" by the duty ratio limiting unit 42. Also, since the command value of the duty ratio for the high-potential side control signal generated by the duty ratio commanding unit 41 is "0.97", which is greater than or equal to "0.96" obtained by subtracting the limit value "0.04" from "1", the command value is overwritten to "1" by the duty ratio limiting unit 42.

[0054] As a result, in this example, the command value of the duty ratio for the low potential side control signal is maintained at "0", and the command value of the duty ratio for the high potential side control signal is maintained at "1". Based on the duty ratio command value of "0" for the low potential side control signal, the low potential side transistor 134L is maintained in the OFF state. Therefore, the bootstrap capacitor 62 is not charged, as in FIG. 5. However, in FIG. 6, based on the duty ratio command value of "1" for the high potential side control signal, the high potential side transistor 134H is maintained in the ON state. Therefore, the ON / OFF state of the high potential side transistor 134H is not switched in a short time as in FIG. 5, and the charge of the bootstrap capacitor 62 is not wasted.

[0055] The frequency monitoring unit 43 may monitor the frequency at which the command value of the duty ratio for the low potential side control signal generated by the duty ratio command unit 41 is between "0" and the limit value "0.04" and / or the frequency at which the command value of the duty ratio for the high potential side control signal generated by the duty ratio command unit 41 is between "0.96", a value obtained by subtracting the limit value "0.04" from "1", and "1". When the frequency monitored by the frequency monitoring unit 43 is below a predetermined upper limit frequency, the duty ratio limiting unit 42 may allow a duty ratio between "0" and the limit value "0.04" for the low potential side control signal, or may allow a duty ratio between "0.96", a value obtained by subtracting the limit value "0.04" from "1", and "1" for the high potential side control signal.

[0056] When the frequency monitored by the frequency monitoring unit 43 is below the upper limit frequency, it is considered that the bootstrap capacitor 62 has sufficient charge stored therein so as not to impede the operation of the high-side driver 135H, and therefore a low duty ratio for the low-side control signal and / or a high duty ratio for the high-side control signal that consumes the charge of the bootstrap capacitor 62 is permitted. For example, when the frequency monitored by the frequency monitoring unit 43 is 10 times or less in succession, a low duty ratio for the low-side control signal and / or a high duty ratio for the high-side control signal is permitted. When the frequency monitored by the frequency monitoring unit 43 exceeds the upper limit frequency of 10 times in succession, a low duty ratio for the low-side control signal and / or a high duty ratio for the high-side control signal is not permitted, and is updated by the duty ratio limiting unit 42 to "0" and / or "1", respectively.

[0057] In addition to or instead of the frequency monitoring unit 43, the charge monitoring unit 44 may directly monitor the charge stored in the bootstrap capacitor 62. When the charge of the bootstrap capacitor 62 monitored by the charge monitoring unit 44 exceeds a predetermined limit release threshold, the duty ratio limiting unit 42 may release the limit on the duty ratio of the low potential side control signal from "0" to a limit value of "0.04", or may release the limit on the duty ratio of the high potential side control signal from "0.96", a value obtained by subtracting the limit value of "0.04" from "1", to "1".

[0058] When the charge of the bootstrap capacitor 62 monitored by the charge monitor 44 exceeds the limit release threshold, the charge allows the high-side driver 135H to operate normally, and therefore allows a low duty ratio for the low-side control signal and / or a high duty ratio for the high-side control signal that involves consumption of the charge of the bootstrap capacitor 62. When the charge of the bootstrap capacitor 62 monitored by the charge monitor 44 falls below the limit release threshold, the duty ratio limiter 42 applies a duty ratio limit from "0" to the limit value "0.04" for the low-side control signal, and applies a duty ratio limit from "0.96", which is a value obtained by subtracting the limit value "0.04" from "1", to "1" for the high-side control signal.

[0059] The frequency monitoring unit 43 and the charge monitoring unit 44 described above can reduce the frequency with which the duty ratio limiting unit 42 applies a duty ratio limit from "0" to the limit value "0.04" to the low potential side control signal, and the frequency with which the duty ratio limiting unit 42 applies a duty ratio limit from "0.96" (a value obtained by subtracting the limit value "0.04" from "1") to "1" to the high potential side control signal. The duty ratio limiting unit 42 applies a duty ratio limit or a forced overwrite, for example, to the AC voltage V U , V V , V W2, in a use case in which the low-side transistor 134L is periodically turned on, the bootstrap capacitor 62 is periodically charged, and therefore it is considered that the charge in the bootstrap capacitor 62 is rarely depleted to the extent that the duty ratio limiting unit 42 needs to be applied.

[0060] The present disclosure has been described above based on the embodiments. Various modifications are possible to the combinations of the components and processes in the exemplary embodiments, and it will be obvious to those skilled in the art that such modifications are included within the scope of the present disclosure.

[0061] FIG. 7 shows a modified example of FIG. 3. The same components as those in FIG. 3 are denoted by the same reference numerals, and duplicated explanations are omitted. In the example of FIG. 7, the duty ratio limiting unit 42 in FIG. 3 is realized integrally with the duty ratio command unit 41. Specifically, the duty ratio limiting unit 42 is the duty ratio command unit 41 that generates a command value of the duty ratio for the low potential side control signal, and when limiting a command value between "0" and the limit value "0.04", it does not generate a command value in that range. That is, the duty ratio command value that this duty ratio command unit 41 (duty ratio limiting unit 42) can generate for the low potential side control signal when limiting the duty ratio is "0" and "0.04" to "1". Similarly, the duty ratio limiting unit 42 is the duty ratio command unit 41 that generates a command value of the duty ratio for the high potential side control signal, and when limiting a command value between "0.96" obtained by subtracting the limit value "0.04" from "1" and "1", it does not generate a command value in that range. That is, the duty ratio command value that the duty ratio command unit 41 (duty ratio limiting unit 42) can generate for the high potential side control signal during duty ratio limiting is "1" and "0" to "0.96".

[0062] The configuration, action, and function of each device and method described in the embodiments can be realized by hardware resources or software resources, or by the cooperation of hardware resources and software resources. For example, a processor, ROM, RAM, and various integrated circuits can be used as hardware resources. For example, programs such as an operating system and applications can be used as software resources. [Explanation of symbols]

[0063] 5 driver power supply, 6 bootstrap circuit, 10 inverter device, 13 inverter, 41 duty ratio command section, 42 duty ratio limiting section, 43 frequency monitoring section, 44 charge monitoring section, 61 bootstrap diode, 62 bootstrap capacitor, 134H high potential side transistor, 134L low potential side transistor, 135H high potential side driver, 135L low potential side driver.

Claims

1. Two switching elements connected in series, a high potential side switching element on a high potential side and a low potential side switching element on a low potential side; a high-side driver that generates a high-side control signal, the pulse width of which is controlled by a duty ratio, for a switching operation of the high-side switching element; a low side driver generating a low side control signal complementary to the high side control signal for switching operation of the low side switching element; a driver power supply for supplying power to the low-side driver; a bootstrap circuit including a bootstrap diode and a bootstrap capacitor connected in series between the driver power supply and a connection point of the high potential side switching element and the low potential side switching element; a duty ratio limiting unit that allows a duty ratio of "0" for the low potential side control signal and limits the duty ratio from "0" to a predetermined limit value; A driver device comprising:

2. 2. The driver device according to claim 1, wherein the limit value is equal to or greater than a transition time required for the low potential side switching element to transition from an off state to an on state.

3. The driver device according to claim 2 , wherein the limit value is greater than "0" and less than "0.05".

4. 4. The driver device according to claim 1, wherein the duty ratio limiting unit allows a duty ratio of "1" for the high potential side control signal and limits the duty ratio to "1" from a value obtained by subtracting the limiting value from "1."

5. a duty ratio command unit that generates a command value of a duty ratio for the low potential side control signal; the duty ratio limiting unit updates the command value generated by the duty ratio command unit to "0" when the command value is between "0" and the limiting value; 4. A driver device according to claim 1.

6. 6. The driver device according to claim 5, wherein the duty cycle limiting unit allows a duty cycle between "0" and the limit value when a frequency at which the command value generated by the duty cycle command unit is between "0" and the limit value is below a predetermined upper frequency, and updates the command value to "0" when a frequency at which the command value generated by the duty cycle command unit is between "0" and the limit value exceeds the upper frequency.

7. 6. The driver device according to claim 5, wherein the duty ratio limiting unit updates the duty ratio command value for the high potential side control signal to "1" when the command value generated by the duty ratio command unit is between "0" and the limit value.

8. 4. The driver device according to claim 1, wherein the duty ratio limiting unit is a duty ratio command unit that generates a command value of a duty ratio for the low potential side control signal, and does not generate a command value between "0" and the limiting value.

9. a charge monitoring unit that monitors the charge stored in the bootstrap capacitor; the duty ratio limiting unit, when the charge exceeds a predetermined limit lifting threshold, lifts the limit of the duty ratio of the low potential side control signal from "0" to the limiting value; 4. A driver device according to claim 1.

10. a high-side driver that generates a high-side control signal whose pulse width is controlled by a duty ratio for a switching operation of the high-side switching element; a low-side driver that generates a low-side control signal complementary to the high-side control signal for a switching operation of the low-side switching element; a driver power supply that supplies power to the low-side driver; and a bootstrap circuit that includes a bootstrap diode and a bootstrap capacitor that are connected in series between the driver power supply and a connection point of the high-side switching element and the low-side switching element, A control method in which a duty ratio of "0" is permitted for the low potential side control signal, and the duty ratio is limited to a range from "0" to a predetermined limit value.

11. Two switching elements connected in series between a high potential line and a low potential line, the high potential side switching element being on the high potential side and the low potential side switching element being on the low potential side, which output AC from a connection point between the high potential line and the low potential line; a high-side driver that generates a high-side control signal, the pulse width of which is controlled by a duty ratio, for a switching operation of the high-side switching element; a low side driver generating a low side control signal complementary to the high side control signal for switching operation of the low side switching element; a driver power supply for supplying power to the low-side driver; a bootstrap circuit including a bootstrap diode and a bootstrap capacitor connected in series between the driver power supply and a connection point of the high potential side switching element and the low potential side switching element; a duty ratio limiting unit that allows a duty ratio of "0" for the low potential side control signal and limits the duty ratio from "0" to a predetermined limit value; An inverter device comprising:

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