Semiconductor device

Abstract

To provide a semiconductor device capable of stable operation even if power supply to its basic block is cut off during operation due to rewrite of its configuration.SOLUTION: An embodiment includes a plurality of basic blocks mutually connected, and a plurality of output control parts connected among the plurality of basic blocks. A basic block includes a power supply switch part and a basic logic circuit part. The power supply switch part supplies power supply to the basic logic circuit part and cuts off the power supply. The output control part is connected between output of one basic block and input of the other basic block. In the one basic block, the output control part outputs either a first logical value or a second logical value to the other basic block if the power supply to the basic logic circuit is cut off.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The embodiments relate to a programmable semiconductor device. [Background technology]

[0002] Field-programmable gate arrays (FPGAs) are known as application-specific semiconductor devices. FPGAs can easily accommodate circuits designed for specific systems. In recent years, it has become possible to apply IP blocks that use power management to FPGAs, making it easy to build energy-saving systems.

[0003] Not only when performing power management, but also in systems using FPGAs, there are cases where the FPGA configuration is dynamically rewritten while the system is running. For example, some basic blocks in an FPGA may only operate under specific circumstances, such as when the system is booting up, and there is a demand to cut off the power supply to these blocks after the system is booted up to reduce power consumption.

[0004] There is known a technique for switching between supplying and cutting off power to basic blocks depending on the configuration of an FPGA (for example, see Patent Document 1, etc.). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2001-142796 A Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the embodiment of the present invention is to provide a semiconductor device that can operate stably even if the power supply to a basic block is cut off during operation by rewriting the configuration. [Means for solving the problem]

[0007] A semiconductor device according to an embodiment includes a plurality of basic blocks connected to each other and a plurality of output control units connected between the plurality of basic blocks. Each of the plurality of basic blocks includes a logic operation circuit unit connected between a first power supply and a second power supply having a voltage value higher than a voltage value of the first power supply, and configured to be rewritable by a program with a preset logic operation, and a power switch unit connected between the second power supply and the logic operation circuit unit, and configured to control whether or not a power supply voltage, which is a difference between a voltage value of the second power supply and a voltage value of the first power supply, is supplied to the logic operation circuit. Each of the plurality of output control units is connected between an output of a logic operation circuit of one of the plurality of basic blocks connected to each other and an input of a logic operation circuit of the other basic block, and is configured to output a first logic value or a second logic value to an input of the logic operation circuit of the other basic block continuously during a cut-off period when the power switch unit cuts off the supply of the power supply voltage to the logic operation circuit of the one basic block. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic block diagram illustrating a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic block diagram illustrating a portion of the semiconductor device according to the first embodiment. [Diagram 3] 3A and 3B are schematic block diagrams illustrating a part of the semiconductor device according to the first embodiment. [Figure 4] 3A to 3C are schematic views for explaining the operation of the semiconductor device according to the first embodiment. [Diagram 5] 10A and 10B are schematic diagrams for explaining the operation of a semiconductor device of a comparative example; [Figure 6] FIG. 11 is a schematic block diagram illustrating a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are given the same reference numerals and detailed description thereof will be omitted as appropriate.

[0010] (First embodiment) FIG. 1 is a schematic block diagram illustrating the semiconductor device according to the first embodiment. 1, the semiconductor device 100 according to the embodiment includes a plurality of basic blocks 10 and a plurality of output control units 20. In this specific example, nine basic blocks are shown among the plurality of basic blocks. The plurality of basic blocks 10-1 to 10-9 are connected to each other.

[0011] The configuration of each basic block is the same unless otherwise specified. In the following, when multiple basic blocks are not distinguished, they are written as "basic block 10", and when multiple basic blocks need to be distinguished, they may be written with a different reference numeral, such as "basic blocks 10-1 to 10-9". Similarly, when the output control unit 20 does not need to be distinguished, it may be written as "output control unit 20", and when it needs to be distinguished, it may be written as "output control units 20-1 to 20-24". Similarly, when the power supply control signal DEN does not need to be distinguished, it may be written as "power supply control signal DEN", ​​and when it needs to be distinguished, it may be written with a different reference numeral, such as "power supply control signal DEN1 to DEN9".

[0012] A plurality of basic blocks 10 are connected to each other via a plurality of output control units 20. In the example of FIG. 1, the basic block 10-1 is connected to the basic block 10-2 via the output control units 20-1 and 20-2, and is connected to the basic block 10-4 via the output control units 20-5 and 20-6. The basic block 10-2 is connected to the basic block 10-3 via the output control units 20-3 and 20-4, and is connected to the basic block 10-5 via the output control units 20-7 and 20-8. The basic block 10-3 is connected to the basic block 10-6 via the output control units 20-9 and 20-10. The basic block 10-4 is connected to the basic block 10-5 via the output control units 20-11 and 20-12, and is connected to the basic block 10-7 via the output control units 20-15 and 20-16. The basic block 10-5 is connected to the basic block 10-6 via the output control units 20-13 and 20-14, and is connected to the basic block 10-6 via the output control units 20-17 and 20-18. The basic block 10-6 is connected to the basic block 10-9 via the output control units 20-19 and 20-20. The basic block 10-7 is connected to the basic block 10-8 via the output control units 20-21 and 20-22. The basic block 10-8 is connected to the basic block 10-9 via the output control units 20-23 and 20-24.

[0013] A plurality of power control signals DEN1 to DEN9 are input to the plurality of basic blocks 10-1 to 10-9, respectively. The power control signal DEN1 is input to the output control units 20-1 and 20-5, respectively. The power control signal DEN2 is input to the output control units 20-2, 20-3, and 20-7, respectively. The power control signal DEN3 is input to the output control units 20-4 and 20-9, respectively. The power control signal DEN4 is input to the output control units 20-6, 20-11, and 20-15, respectively. The power control signal DEN5 is input to the output control units 20-8, 20-12, 20-13, and 20-17, respectively. The power control signal DEN6 is input to the output control units 20-10, 20-14, and 20-19, respectively. The power control signal DEN7 is input to the output control units 20-16 and 20-21, respectively. The power supply control signal DEN8 is input to each of the output control units 20-18, 20-22, and 20-23. The power supply control signal DEN9 is input to each of the output control units 20-20 and 20-24.

[0014] FIG. 2 is a schematic block diagram illustrating a part of the semiconductor device according to the first embodiment. FIG. 2 shows a specific example of the configuration of the basic block 10 that constitutes the semiconductor device 100. As shown in FIG. 2, the basic block 10 has a power switch section 12 and a basic logic operation circuit section 14. The basic block 10 has power input sections V0 and V1. The power switch section 12 and the basic logic operation circuit section 14 are connected between the power input sections V0 and V1. The power switch section 12 is connected between the power input section V1 and the basic logic operation circuit section 14. A voltage higher than the voltage applied to the power input section V0 is applied to the power input section V1. For example, the power input section V0 is connected to a ground line GND, and the power input section V1 is connected to a power line VDD. As a result, the power supply voltage supplied to the power line VDD is applied to the power switch section 12 and the basic logic operation circuit section 14, enabling them to operate.

[0015] The basic block 10 has a plurality of input units I1 to I4 and a plurality of output units O1 to O4. The plurality of input units I1 to I4 and the plurality of output units O1 to O4 are connected to a basic logic operation circuit unit 14. Input signals DI1 to DI4 can be input to the input units I1 to I4, respectively. The output units O1 to O4 can output output signals DO1 to DO4, respectively. For example, a signal output by another basic block 10 is input to at least one of the input units I1 to I4. The basic logic operation circuit unit 14 executes a logic operation according to a set logic operation circuit, generates at least one output signal, and outputs the output signal from at least one of the plurality of output units O1 to O4.

[0016] The basic logic operation circuit section 14 has, for example, an LUT (Look Up Table), and sets a logic operation circuit by referring to the LUT configured according to a preset program, and executes a logic operation.

[0017] The basic block 10 has a power control input section EN. A power control signal DEN is input to the power control input section EN. The power switch section 12 controls the supply of power to the basic logic arithmetic circuit section 14 according to the logical value of the power control signal DEN. For example, when the power control signal DEN is at the “H” level, the power switch section 12 connects the basic logic arithmetic circuit section 14 to a power line VDD and supplies power to the basic logic arithmetic circuit section 14. When the power control signal DEN is at the “L” level, the power switch section 12 cuts off the connection between the basic logic arithmetic circuit section 14 and the power line VDD and stops the supply of power to the basic logic arithmetic circuit section 14. The logic of the power control signal DEN may be the reverse of the above. That is, when the power control signal DEN is at the “L” level, the power switch section 12 may supply power to the basic logic arithmetic circuit section 14, and when the power control signal DEN is at the “H” level, the power switch section 12 may cut off the supply of power to the basic logic arithmetic circuit section 14.

[0018] The basic logic operation circuit section 14 operates when power is supplied from the power switch section 12. The basic logic operation circuit section 14 executes a logical operation to generate an output signal in response to an input signal input to at least one input terminal, and outputs the output signal from at least one output section. As shown in Fig. 1, the power control signal DEN can take on logical values ​​that may differ for each basic block 10, and these logical values ​​are set according to a configuration that is set according to a preset program.

[0019] The preset program is, for example, a program for power management of the system in which the semiconductor device 100 is mounted, and different configurations are set for the semiconductor device 100 according to the operation state of the power management. For example, in FIG. 1, in an operation state in which the system operates at maximum performance, all the power control signals DEN1 to DEN9 are set to the “H” level and supplied to each of the basic blocks 10-1 to 10-9. For example, in an operation state in which the system operates in power saving mode, the power control signals DEN1 to DEN6 are set to the “L” level, and the power control signals DEN7 to DEN9 are set to the “H” level and supplied to each of the basic blocks 10-1 to 10-9. As a result, the basic blocks 10-1 to 10-6 stop operating, and the power consumption that may be consumed by these blocks is reduced. Note that the preset program is not limited to a program for power management, and may be a program for rewriting the configuration of the basic logic operation circuit unit 14.

[0020] The basic blocks 10 and the output control units 20 are connected to each other in advance. The relationship between the logic of the input signal and the logic of the output signal in the basic logic operation circuit unit 14 in the basic block 10 can be switched by a program. In other words, the semiconductor device 100 according to this embodiment is an FPGA that realizes different configurations by rewriting the LUT referred to in the basic logic operation circuit unit 14 in the basic block 10.

[0021] 3A and 3B are schematic block diagrams illustrating a part of the semiconductor device according to the first embodiment. FIG. 3(a) shows an example of the configuration of the output control unit 20, and FIG. 3(b) shows a specific example in the form of a logical operation circuit. As shown in FIG. 3(a), the output control unit 20 has an input unit CI, a control signal input unit CEN, and an output unit CO. The input unit CI is connected to one of the output units of the basic block 10, and an output signal is input thereto. In this example, the output signal DO1 is input thereto. The control signal input unit CEN receives a power supply control signal DEN, which is input to the basic block 10 to which the input unit CI is connected. The output unit CO is connected to the input unit of another basic block 10.

[0022] The output control section 20 can be, for example, an AND circuit as shown in Fig. 3(b). In the AND circuit as the output control section 20, one input corresponds to a control signal input section CEN, and a power supply control signal DEN is input. The other input corresponds to an input section CI, and is connected to the output section of the basic block 10, and an output signal DO1 is input. The output of the AND circuit corresponds to an output section CO.

[0023] The output control section 20 configured as described above outputs the output signal output from the output section of the basic logic operation circuit section 14 as is when the power supply control signal DEN is at the “H” level. For example, when the output signal DO1 is at the “L” level, the output control section 20 outputs the “L” level, and when the output signal DO1 is at the “H” level, the output control section 20 outputs the “H” level. When the power supply control signal DEN is at the “L” level, the output control section 20 outputs the “L” level regardless of the state of the output section O1 of the basic logic operation circuit section 14. The output control section 20 indicates that the output can change depending on the logical value of the power supply control signal DEN as shown by “DO1 / 0”. “DO1” indicates that the input output signal DO1 is output as is when the power supply control signal DEN is at the “H” level, and “0” indicates that the “L” level is output regardless of the state of the input signal.

[0024] That is, the output control unit 20 can switch between an enabled state and a disabled state of the output by the power supply control signal DEN. When the output is disabled, in the above-mentioned specific example, the output of the output control unit 20 is fixed to the “L” level.

[0025] The operation of the semiconductor device 100 according to this embodiment will be described. FIG. 4 is a schematic diagram for explaining the operation of the semiconductor device according to the first embodiment. FIG. 5 is a schematic diagram for explaining the operation of the semiconductor device of the comparative example. Fig. 4 shows an example in which two basic blocks 10-1 and 10-2 are connected via an output control unit 20-1. In Fig. 4 and Fig. 5, when the logical value of a logical signal is "L", it is expressed as "DEN1(L)" or "DO1(L)", and when the logical value is "H", it is expressed as "DEN(H)" or "DO1(H)". In Fig. 5, when the logical value is undefined, it is expressed as "DO1(X)".

[0026] 4, an output control unit 20-1 is connected between the output unit of basic block 10-1 and the input unit of basic block 10-2. In this state, a power supply control signal DEN1(L) of "L" level is input to basic block 10-1, and a power supply control signal DEN2(H) of "H" level is input to basic block 10-2. The power supply control signal DEN1(L) of "L" level is input to the control signal input unit of output control unit 20-1.

[0027] With the above settings, power supply to the basic logic circuit section of the basic block 10-1 is cut off. On the other hand, power is supplied to the basic logic circuit section of the basic block 10-2. Here, since the power control signal DEN1(L) is input to the output control section 20-1, the output control section 20-1 outputs DO1(L) regardless of the potential of the output section of the basic block 10-1. Therefore, the potential of the input section I1 of the basic block 10-2 is fixed to 0 with respect to the ground potential.

[0028] 5 shows an example in which the output parts of two basic blocks 10-1 and the input part of a basic block 10-2 are directly connected. In this state, a power supply control signal DEN1(L) of the “L” level is input to the basic block 10-1, and a power supply control signal DEN2(H) of the “H” level is input to the basic block 10-2.

[0029] With the above settings, the output signal DO1(X) output from the output unit of the basic block 10-1 becomes indefinite. That is, depending on the leakage current of the circuit elements constituting the basic block 10-1, the signal may become an intermediate potential state that is neither "H" level nor "L" level, at least transiently. Therefore, a signal of an indefinite level is input to the next-stage basic block 10-2, which may cause the basic block 10-2 to malfunction.

[0030] 1 to 4, the output control section 20 outputs an "L" level when disabled, but this is not limiting, and the output control section 20 may output an "H" level when disabled. The output level when disabled may be the same for all of the multiple output control sections 20, or may be different for each of the multiple output control sections 20.

[0031] The effects of the semiconductor device 100 according to this embodiment will be described. The semiconductor device 100 according to this embodiment includes a plurality of basic blocks 10 and a plurality of output control units 20. The output control unit 20 is connected between the output unit of the basic block 10 and the input unit of the connected basic block 10. When the power supply to the basic block 10 is cut off, the output control unit 20 fixes the input to the next basic block to the "L" level or "H" level. Therefore, regardless of the level of the output of the basic block to which the power supply is cut off, it is possible to prevent the next basic block 10 from malfunctioning.

[0032] When an FPGA is installed in a system that applies power management, it is possible to effectively reduce power consumption by controlling the supply and cutoff of power to each basic block of the FPGA in the power management. When an FPGA is applied to an industrial system, the FPGA configuration may be dynamically changed depending on the system operation sequence. For example, some blocks of the FPGA may be used only in specific states such as when the system is started up, during a specified protection operation, or in an inspection mode for inspection. It is possible to reduce power consumption in the FPGA by cutting off the power supply when some of these blocks are not operating.

[0033] The semiconductor device 100 according to this embodiment has a power switch unit 12 for each basic block 10, and is therefore capable of controlling the supply and cut-off of power to the basic block 10. Such an FPGA is known, for example, from Patent Document 1, but after the power is cut off, the signal level output by the basic block to which the power has been cut off becomes indefinite, and this may affect the operation of the basic block at the next stage.

[0034] The semiconductor device 100 according to this embodiment includes an output control unit 20 between the basic blocks 10 that are connected to each other. When the power supply to a basic block 10 is cut off, the output control unit 20 fixes the signal level that the basic block outputs to the next basic block 10 at the "L" level or "H" level. Therefore, even if the semiconductor device 100 is applied to a system to which power management is applied or a system in which a block that does not operate due to an operation mode or the like exists, the system can continue to operate stably without being affected by the output signal of the basic block 10 whose power supply has been cut off.

[0035] Second embodiment FIG. 6 is a schematic block diagram illustrating the semiconductor device according to the second embodiment. As shown in FIG. 6, the semiconductor device 200 according to the present embodiment includes a plurality of basic blocks 210. The basic block 210-1 is connected to the basic blocks 210-2 and 210-4. The basic block 210-2 is connected to the basic blocks 210-3 and 210-5. The basic block 210-3 is connected to the basic block 210-6. The basic block 210-4 is connected to the basic blocks 210-5 and 210-7. The basic block 210-5 is connected to the basic blocks 210-6 and 210-8. The basic block 210-6 is connected to the basic block 210-9. The basic block 210-7 is connected to the basic block 210-8. The basic block 210-8 is connected to the basic block 210-9.

[0036] In the semiconductor device 200 according to this embodiment, each basic block 210 includes a power switch section 12, a basic logic operation circuit section 14, and an output control section 20. The output control section 20 is provided for each output section of the basic logic operation circuit section 14, and is connected to the input section of the basic logic operation circuit section 14 of the basic block 210 at the next stage.

[0037] The power supply control signals DEN1 to DEN9 are input to the basic blocks 210-1 to 210-9, respectively, in the same manner as in the semiconductor device 100 according to the first embodiment shown in Fig. 1. The power supply control signal DEN input to each basic block 210 is also supplied within the basic block 210 to the output control unit 20 within that basic block 210.

[0038] The semiconductor device 200 according to this embodiment can operate in the same manner as the semiconductor device 100 according to the first embodiment, and therefore can provide the same effects as the semiconductor device 100 according to the first embodiment.

[0039] In this manner, a semiconductor device can be realized that can operate stably even if the power supply to the basic block is cut off during operation by rewriting the configuration.

[0040] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0041] 10, 10-1 to 10-9...basic block, 12...power switch section, 14...basic logic circuit section, 20, 20-1 to 20-24, 210, 210-1 to 210-9...output control section, 100, 200...semiconductor device

Claims

1. A plurality of interconnected basic blocks; A plurality of output control units connected between the plurality of basic blocks; Equipped with Each of the plurality of basic blocks comprises: a logic operation circuit section connected between a first power source and a second power source having a voltage value higher than a voltage value of the first power source, the logic operation circuit section being configured so that a preset logic operation can be rewritten by a program; a power supply switch section connected between the second power supply and the logic operation circuit section and configured to control whether or not a power supply voltage, which is a difference between a voltage value of the second power supply and a voltage value of the first power supply, is supplied to the logic operation circuit; Including, each of the plurality of output control units is connected between an output of a logic operation circuit of one of the plurality of basic blocks that are mutually connected and an input of a logic operation circuit of the other basic block; a first logic value or a second logic value being output to an input of a logic operation circuit of the other basic block during a period when the power supply switch section cuts off the supply of power supply voltage to the logic operation circuit of the other basic block.

2. 2. The semiconductor device according to claim 1, wherein in each of said plurality of basic blocks, said power switch is dynamically opened and closed during a period in which said plurality of basic blocks are operating.

3. 2 . The semiconductor device according to claim 1 , wherein the plurality of output control sections are configured to output either the first logic value or the second logic value for each of the plurality of basic blocks.

4. A plurality of interconnected basic blocks; Each of the plurality of basic blocks comprises: a logic operation circuit section connected between a first power source and a second power source having a voltage value higher than a voltage value of the first power source, the logic operation circuit section being configured so that a preset logic operation can be rewritten by a program; a power supply switch section connected between the second power supply and the logic operation circuit section and configured to control whether or not a power supply voltage, which is a difference between a voltage value of the second power supply and a voltage value of the first power supply, is supplied to the logic operation circuit; an output control unit connected to an output of the logical operation circuit unit; Including, the output control unit is connected between an output of a logic operation circuit of one of the plurality of basic blocks that are mutually connected and an input of a logic operation circuit of the other basic block; a first logic value or a second logic value being output to an input of a logic operation circuit of the other basic block during a period when the power supply switch section cuts off the supply of power supply voltage to the logic operation circuit of the other basic block.

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