Photonic package manufacturing method and photonic package

Abstract

To provide a photonic interposer that enables low-power and high-bandwidth inter-chip and intra-chip communication.SOLUTION: Some embodiments provide a photonic interposer that uses photonic tiles, each of which contains programmable photonic circuitry that can be programmed based on needs of a particular computer architecture. Some tiles are instantiated common template tiles that are stitched together in 1D or 2D arrangements. A programmable physical network is constituted designed to connect pairs of tiles with each other using photonic links.SELECTED DRAWING: Figure 1-1

Description

[Background technology]

[0001] A computer system includes a random access memory (RAM) for storing data and machine code. RAM is typically a volatile memory, such that the stored information is lost when power is removed. In modern implementations, the memory takes the form of integrated circuits. Each integrated circuit includes a number of memory cells. To allow access to the stored data and machine code, the memory is placed in electrical communication with the processor. Typically, these electrical communications are implemented as metal traces formed on a substrate on which the memory and processor reside. Summary of the Invention

[0002] Some embodiments relate to a photonic interposer comprising a plurality of photonic tiles instantiated from a template photonic tile, each of the plurality of photonic tiles including a transceiver comprising a transmitter and a receiver, an electrical connection coupled to the transceiver and configured to enable electrical communication between the transceiver and an electronic chip when the electronic chip is attached to the photonic interposer in correspondence with the photonic tile, and an optical distribution network comprising a first set of bus waveguides optically coupled to the transceiver, a second set of bus waveguides, and a plurality of programmable interconnects, each programmable interconnect configured to selectively place bus waveguides of the first set of bus waveguides in optical communication with bus waveguides of the second set of bus waveguides, each programmable interconnect comprising a waveguide crossing and an active coupler.

[0003] In some embodiments, the transceiver comprises a plurality of modulators coupled to a first bus waveguide of the first set of bus waveguides and tuned at different wavelengths relative to each other, and a plurality of drop filters coupled to a second bus waveguide of the first set of bus waveguides and tuned at different wavelengths relative to each other.

[0004] In some embodiments, the plurality of modulators are resonant modulators and the plurality of drop filters are resonant drop filters. In some embodiments, the transmitter is configured to transmit data in either a first direction or a second direction along a first bus waveguide of the first set of bus waveguides.

[0005] In some embodiments, each of the plurality of photonic tiles further comprises a 2×2 coupler that couples the transceiver to a first bus waveguide of the first set of bus waveguides. In some embodiments, the 2×2 coupler comprises first, second, third and fourth terminals, the first terminal coupled to an output of the transmitter, the second terminal coupled to an input of the receiver, and the third and fourth terminals coupled to a first bus waveguide of the first set of bus waveguides.

[0006] In some embodiments, each of the plurality of photonic tiles further comprises an interferometer having an input and first and second outputs, and a resonant filter; The transmitter is coupled to an input of the interferometer, the first and second outputs of the interferometer are coupled to a resonant filter, and the resonant filter is coupled to a first bus waveguide of the first set of bus waveguides.

[0007] In some embodiments, each of the plurality of photonic tiles further comprises an interferometer having an output and first and second inputs, and a resonant filter, the resonant filter coupled to a first bus waveguide of the first set of bus waveguides, the first and second inputs of the interferometer coupled to the resonant filter, and a receiver coupled to the output of the interferometer.

[0008] In some embodiments, the waveguide intersection comprises a first waveguide patterned on a first waveguide layer, a second waveguide patterned on a second waveguide layer, and a third waveguide layer patterned on a third waveguide layer, the second waveguide layer being between the first and third waveguide layers, the first waveguide being evanescently coupled to the second waveguide, and the second waveguide being evanescently coupled to the third waveguide.

[0009] In some embodiments, the first waveguide layer is formed of silicon and both the second and third waveguide layers are formed of silicon nitride. In some embodiments, the active coupler comprises a first terminal coupled to the first additional active coupler, a second terminal coupled to the first additional active coupler, and a third terminal coupled to the waveguide intersection.

[0010] In some embodiments, the active coupler comprises first and second Mach Zehnder interferometers (MZIs), the first terminal corresponding to a first output of the first MZI, the second terminal corresponding to a second output of the first MZI, and the third terminal corresponding to an output of the second MZI.

[0011] In some embodiments, the bus waveguides of the second set of bus waveguides traverse multiple photonic tiles. Some embodiments relate to a photonic interposer including a plurality of photonic tiles instantiated from a template photonic tile, the plurality of photonic tiles including a first, a second, a third, and a fourth photonic tile, each of the plurality of photonic tiles comprising a first transceiver and an electrical connection coupled to the first transceiver configured to enable electrical communication between the first transceiver and an electronic chip when the electronic chip is attached to the photonic interposer in correspondence with the photonic tile. a first transceiver of the first photonic tile with a first transceiver of the fourth photonic tile, and a second fiber, the first fiber, the first bus waveguide, and the fourth bus waveguide placing a first transceiver of the first photonic tile in optical communication with a first transceiver of the fourth photonic tile, and a second fiber, the second bus waveguide, and the third bus waveguide placing the first transceiver of the second photonic tile in optical communication with a first transceiver of the third photonic tile.

[0012] In some embodiments, each of the plurality of photonic tiles further comprises a second transceiver, the second transceiver of the first photonic tile in optical communication with the second transceiver of the second photonic tile.

[0013] In some embodiments, the second transceiver of the third photonic tile is in optical communication with a second transceiver of a fourth photonic tile. In some embodiments, the photonic interposer further comprises a third fiber, wherein the third fiber, the first bus waveguide, and the fourth bus waveguide further place the first transceiver of the first photonic tile in optical communication with the first transceiver of the fourth photonic tile.

[0014] In some embodiments, the first fiber, the third fiber, the first bus waveguide, the fourth bus waveguide, the first transceiver of the first photonic tile, and the first transceiver of the fourth photonic tile form a closed loop.

[0015] In some embodiments, the photonic interposer further comprises a fourth fiber, wherein the fourth fiber, the second bus waveguide, and the third bus waveguide further place the first transceiver of the second photonic tile in optical communication with the first transceiver of the third photonic tile.

[0016] In some embodiments, the second fiber, the fourth fiber, the second bus waveguide, the third bus waveguide, the first transceiver of the second photonic tile, and the first transceiver of the third photonic tile form a closed loop.

[0017] Some embodiments relate to a computing system, the computing system including a photonic interposer comprising a plurality of photonic tiles instantiated from a template photonic tile, and first and second application-specific integrated circuits implemented on the photonic interposer. a first ASIC coupled to a first photonic tile of the plurality of photonic tiles and a second ASIC coupled to a second photonic tile of the plurality of photonic tiles; and a data path for communicating the first ASIC with the second ASIC, the data path comprising: a first die-to-die (D2D) interface integrated in the first ASIC and comprising a plurality of wires; a first plurality of SerDes coupled to the plurality of wires; a plurality of optical modulators coupled to the plurality of SerDes and formed in the first photonic tile; a plurality of photodetectors coupled to the plurality of optical modulators and formed in the second photonic tile; a second plurality of SerDes coupled to the plurality of photodetectors; and a second D2D interface integrated in the second ASIC.

[0018] In some embodiments, the multiple photodetectors are coupled to the multiple optical modulators via waveguides formed on the photonic interposer. In some embodiments, multiple optical detectors are coupled to multiple optical modulators via fibers.

[0019] In some embodiments, the first and second D2D interfaces comprise Advanced Interface Bus (AIB) interfaces.

[0020] In some embodiments, the first and second D2D interfaces comprise Universal Chiplet Interconnect Express (UCIe) interfaces.

[0021] In some embodiments, the data path spans a length of more than 2.5 cm from the first D2D interface to the second D2D interface. Some embodiments relate to a method for manufacturing a photonic package, the method including obtaining a photonic interposer having a lattice coupler formed on a first surface of the photonic interposer, attaching an electronic chip to the first surface of the photonic interposer, encapsulating the electronic chip with an encapsulation material, disposing a protective material on the first surface of the photonic interposer to cover the lattice coupler, forming electronic connections on a second surface of the photonic interposer opposite the first surface following disposing the protective material, and removing the protective material from the first surface of the photonic interposer to expose the lattice coupler to air following forming the electronic connections.

[0022] In some embodiments, the method further includes cleaning the first surface of the photonic interposer subsequent to removing the protective material from the first surface of the photonic interposer.

[0023] In some embodiments, the method further includes, following removing the protective material, attaching a fiber to the first surface of the photonic interposer, such that the fiber, when attached, is optically coupled to the grating coupler.

[0024] In some embodiments, when the fiber is optically coupled to the grating coupler, the fiber is at a non-zero angle relative to the first surface of the photonic interposer. In some embodiments, attaching the electronic chip to the first surface of the photonic interposer occurs subsequent to disposing a protective material on the first surface of the photonic interposer.

[0025] In some embodiments, the protective material comprises a photoimageable dielectric. In some embodiments, disposing the protective material on the first surface of the photonic interposer is performed subsequent to attaching the electronic chip to the first surface of the photonic interposer.

[0026] In some embodiments, disposing the protective material on the first surface of the photonic interposer is performed subsequent to encapsulating the electronic chip with an encapsulation material. In some embodiments, the protective material comprises a glass lid having a releasable adhesive.

[0027] Some embodiments relate to a method for manufacturing a photonic package, the method including obtaining a photonic interposer having a lattice coupler formed on a first surface of the photonic interposer, attaching an electronic chip to the first surface of the photonic interposer, encapsulating the electronic chip with an encapsulation material such that the encapsulation material leaves the lattice coupler exposed to air, placing the photonic interposer on a carrier mount to cover the lattice coupler, forming electronic connections on a second surface of the photonic interposer opposite the first surface following placing the photonic interposer on the carrier mount, and removing the carrier mount following forming the electronic connections.

[0028] In some embodiments, encapsulating the electronic chip is performed subsequent to attaching the electronic chip to the first surface of the photonic interposer. In some embodiments, the method further includes separating the photonic interposer into multiple systems, each system comprising an electronic chip and a lattice coupler, subsequent to removing the carrier mount.

[0029] In some embodiments, the method further includes, following removing the protective material, attaching a fiber to the first surface of the photonic interposer, such that the fiber, when attached, is optically coupled to the grating coupler.

[0030] In some embodiments, when the fiber is optically coupled to the grating coupler, the fiber is at a non-zero angle relative to the first surface of the photonic interposer. Some embodiments relate to a photonic package comprising: a photonic interposer; a first electronic chip disposed on the photonic interposer; a circuit board having a first surface and a second surface opposite the first surface, the photonic interposer being coupled to the first surface of the circuit board; a voltage regulator module (VRM) coupled to the second surface of the circuit board; and a connection configured to provide an output voltage of the VRM to the first electronic chip, the connection traversing the circuit board and the photonic interposer.

[0031] In some embodiments, the photonic package further comprises a substrate and a socket, the photonic interposer being disposed on the substrate and the substrate being disposed on the socket. In some embodiments, the connection further traverses the substrate and the socket.

[0032] In some embodiments, the photonic package further comprises a power bus configured to provide an input voltage to the voltage regulator module. In some embodiments, the voltage regulator module receives an input voltage from a power bus and regulates an output voltage to the first electronic chip.

[0033] In some embodiments, the first electronic chip is in contact with the photonic interposer. In some embodiments, the photonic package further comprises a lid covering the photonic interposer and a cold plate covering the lid, the lid in thermal contact with the first electronic chip.

[0034] Some embodiments relate to a photonic device comprising: a photonic circuit; a plurality of optical channels having a plurality of chip-to-fiber couplers and a plurality of waveguides coupled to each chip-to-fiber coupler; an optical switch coupled between the plurality of optical channels and the optical circuit; and a controller configured to determine information indicative of a performance associated with each of the plurality of optical channels, identify a subset of the plurality of optical channels using the information indicative of the performance associated with each of the plurality of optical channels, and control the optical switch to selectively couple the subset of the plurality of optical channels to the photonic circuit.

[0035] In some embodiments, the multiple optical channels further comprise multiple optical detectors coupled to the respective waveguides, and determining the information indicative of the performance associated with each of the multiple optical channels includes determining an output of each of the multiple optical detectors.

[0036] In some embodiments, multiple photodetectors are coupled to respective waveguides via tap couplers. In some embodiments, determining the information indicative of performance associated with each of the plurality of optical channels includes determining a bit error rate (BER) associated with each of the plurality of optical channels.

[0037] In some embodiments, the photonic circuit comprises a plurality of tiles patterned according to a template tile, each tile comprising a transmitter, a receiver, a network of programmable optical connections, and electrical connections configured for vertical die-to-die connection with an electronic chip, the electrical connections being coupled to the transmitter, the receiver, and the network of programmable optical connections.

[0038] In some embodiments, using the information to identify the subset of the plurality of optical channels includes identifying a subset of the plurality of optical channels that exhibits best performance among the optical channels.

[0039] In some embodiments, the tip-fiber coupler comprises an edge coupler or a grating coupler. In some embodiments, the controller is further configured to control the photonic circuit to transmit data external to the photonic device using a subset of the plurality of optical channels selected by the optical switch.

[0040] Some embodiments relate to a method for transmitting data using a photonic device comprising an optical switch and a plurality of optical channels having a plurality of chip-fiber couplers and a plurality of waveguides coupled to each chip-fiber coupler, the method including determining information indicative of performance associated with each of the plurality of optical channels, identifying a subset of the plurality of optical channels using the information indicative of performance associated with each of the plurality of optical channels, controlling the optical switch to select the subset of the plurality of optical channels, and transmitting data external to the photonic device using the subset of the plurality of optical channels selected by the optical switch.

[0041] In some embodiments, the multiple optical channels further comprise multiple optical detectors coupled to the respective waveguides, and determining the information indicative of the performance associated with each of the multiple optical channels includes determining an output of each of the multiple optical detectors.

[0042] In some embodiments, determining the information indicative of performance associated with each of the plurality of optical channels includes determining a bit error rate (BER) associated with each of the plurality of optical channels.

[0043] In some embodiments, using the information to identify the subset of the plurality of optical channels includes identifying a subset of the plurality of optical channels that exhibits best performance among the optical channels.

[0044] Some embodiments relate to a photonic interposer comprising a plurality of photonic tiles including a redundant tile, each photonic tile comprising a transmitter, a receiver, a network of programmable optical connections, electrical connections configured for vertical die-to-die connection with an electronic chip, the electrical connections coupled to the transmitter, the receiver, and the network of programmable optical connections, and a monitoring optical detector; and a controller configured to use an output of each monitoring optical detector to determine information indicative of a performance of each of the plurality of photonic tiles, to use the information indicative of the performance of each of the plurality of photonic tiles to identify a defective tile from among the plurality of tiles, and to functionally swap the defective tile with a redundant tile.

[0045] In some embodiments, functionally swapping the defective tile with a redundant tile includes redirecting data intended for the defective tile to the redundant tile. In some embodiments, redirecting the data includes programming a network of programmable photonic connections.

[0046] Some embodiments relate to a photonic interposer comprising: a bus waveguide; a plurality of photonic transmitters coupled to the bus waveguide; a plurality of photonic receivers coupled to the bus waveguide; and a controller configured to lock a first photonic transmitter of the plurality of photonic transmitters to a first photonic receiver of the plurality of photonic receivers by dithering a photonic component of the first photonic transmitter at a first frequency and by dithering a photonic component of the first photonic receiver at the first frequency.

[0047] In some embodiments, each of the plurality of photonic transmitters comprises a resonant modulator and each of the plurality of photonic receivers comprises a resonant drop filter coupled to the bus waveguide, and dithering the photonic component of the first photonic transmitter comprises dithering a resonant modulator of the first photonic transmitter and dithering the photonic component of the first photonic receiver comprises dithering a resonant drop filter of the first photonic receiver.

[0048] In some embodiments, each of the plurality of photonic transmitters comprises a resonant add filter coupled to the bus waveguide and each of the plurality of photonic receivers comprises a resonant drop filter coupled to the bus waveguide, and dithering the photonic component of the first photonic transmitter comprises dithering a resonant add filter of the first photonic transmitter and dithering the photonic component of the first photonic receiver comprises dithering a resonant drop filter of the first photonic receiver.

[0049] In some embodiments, the first frequency is between 1 KHz and 1000 KHz. In some embodiments, the photonic interposer further comprises a plurality of photonic tiles instantiated from the template photonic tile, each of the plurality of photonic tiles comprising a photonic transmitter of the plurality of photonic transmitters and a photonic receiver of the plurality of photonic receivers, and the bus waveguide traverses two or more photonic tiles.

[0050] Some embodiments relate to a photonic transmitter comprising: a resonant modulator configured to modulate light received from a laser using input data; a Mach-Zehnder Interferometer (MZI) coupled to the resonant modulator, the MZI having a first output and a second output; a resonant additional filter coupled to a bus waveguide; and a controller configured to transmit the modulated light along the bus waveguide in either a first direction or a second direction by selectively coupling either the first output or the second output of the MZI to the resonant additional filter.

[0051] In some embodiments, the photonic transmitter further comprises a heater thermally coupled to the resonant modulator and a first monitoring detector coupled to a first output of the MZI, and the controller is further configured to lock the resonant modulator to the laser by applying a first ramp signal to the heater and maximizing the output generated by the first monitoring detector.

[0052] In some embodiments, selectively coupling either the first output or the second output of the MZI to the resonant additive filter includes applying a second ramp signal to the MZI and minimizing an output generated by the first monitoring detector.

[0053] In some embodiments, selectively coupling either the first output or the second output of the MZI to the resonant additional filter further includes applying a third ramp signal to the resonant additional filter and minimizing an output generated by a second monitoring detector coupled to the second output of the MZI.

[0054] In some embodiments, the resonant additional filter comprises a second order filter. Some embodiments relate to a photonic interposer comprising first and second photonic tiles instantiating a template photonic tile, each of the first and second photonic tiles comprising a transceiver and a receiver; an optical channel coupling a transmitter of the first photonic tile to a receiver of the second photonic tile; an encoder coupled to the transmitter of the first photonic tile and configured to perform an Xb / Yb encoding scheme; a decoder coupled to the receiver of the second photonic tile and configured to perform an Xb / Yb decoding scheme; and a clock recovery circuit configured to time the receiver of the second photonic tile using an output of the decoder.

[0055] In some embodiments, the photonic interposer further comprises a first local oscillator coupled to the encoder and a second local oscillator coupled to the decoder. In some embodiments, the photonic interposer further comprises an equalizer coupled to the receiver of the second photonic tile, the equalizer configured to perform a linear combination of the outputs of the receiver of the second photonic tile.

[0056] In some embodiments, the equalizer is further configured to determine characteristics of the optical channel during runtime and to adjust a number of taps associated with the equalizer based on the characteristics of the optical channel determined by the equalizer.

[0057] In some embodiments, the equalizer is further configured to determine characteristics of the optical channel during runtime and to adjust coefficients associated with the equalizer based on the characteristics of the optical channel determined by the equalizer.

[0058] Various aspects and embodiments of the present application are described with reference to the following drawings. It should be appreciated that the drawings are not necessarily drawn to scale. Items that appear in more than one drawing are designated with the same reference numerals in the drawings in which they appear. [Brief description of the drawings]

[0059] [Figure 1-1] 1 illustrates a computing system based on a photonic interposer, according to some embodiments. [Figure 1-2A] 1 illustrates a semiconductor wafer, according to some embodiments. [Figure 1-2B] 1 illustrates a set of photomasks, according to some embodiments. [Figure 1-2C] 1 illustrates an example of a photomask for forming an optical waveguide, according to some embodiments. [Figure 1-2D] 1-2A being patterned according to the photomask set of FIG. 1-2B, according to some embodiments. [Figure 1-2E] 1-2D, according to some embodiments. FIG. [Figure 1-3A] 1-2E illustrates an example of a tile of the patterned wafer of FIGS. 1-2E, according to some embodiments. [Figure 1-3B] 1A-3C illustrate a collection of tiles of the type illustrated in FIGS. 1-3A, according to some embodiments. [Figure 1-4A] 1 illustrates a group of tiles sharing the same pattern of metal traces according to some embodiments. [Figure 1-4B] 1 illustrates a group of tiles that share the same pattern of metal traces and form a moisture barrier according to some embodiments. [Figure 2-1A] 1 illustrates an architecture in which tiles of a photonic interposer are interconnected using static connections, according to some embodiments. [Figure 2-1B]1 illustrates another architecture in which tiles of a photonic interposer are interconnected using static connections, according to some embodiments. [Figure 2-1C] 1 illustrates yet another architecture in which tiles of a photonic interposer are interconnected using static connections, according to some embodiments. [Figure 2-1D] 1 illustrates an architecture in which tiles of a photonic interposer are interconnected using static connections and fibers, according to some embodiments. [Figure 2-1E] 1 illustrates an architecture in which tiles of a photonic interposer are interconnected using static connections and two fibers, according to some embodiments. [Figure 2-1F] 1 illustrates an architecture in which tiles of a photonic interposer are interconnected using static connections and three fibers, according to some embodiments. [Figure 2-1G] 1 illustrates another architecture in which tiles of a photonic interposer are interconnected using static connections and two fibers, according to some embodiments. [Figure 2-1H] 1 illustrates another architecture in which tiles of a photonic interposer are interconnected using static connections and four fibers, according to some embodiments. [Figure 2-1I] 13 illustrates yet another architecture in which tiles of a photonic interposer are interconnected using static connections and four fibers, according to some embodiments. [Figure 2-2A] 1 illustrates an architecture in which tiles of a photonic interposer are interconnected using programmable connections, according to some embodiments. [Figure 2-2B] 1 illustrates another architecture in which tiles of a photonic interposer are interconnected using programmable connections, according to some embodiments. [Figure 2-2C] 1 illustrates yet another architecture in which tiles of an optical interposer are interconnected using programmable connections according to some embodiments. [Figure 2-2D] 2C illustrates in further detail the tiles of the photonic interposer shown in FIGS. 2-2C, according to some embodiments. [Figure 2-2E] 1 illustrates an example of a programmable photonic interconnect in accordance with some embodiments. [Figure 2-2F] 1 illustrates an example of an active coupler, according to some embodiments. [Figure 2-3A] 1 illustrates an architecture having a bidirectional bus according to some embodiments. [Figure 2-3B] 1 illustrates another architecture having a bidirectional bus according to some embodiments. [Figure 2-4A] 1 illustrates a photonic circuit for coupling a transmitter to a bidirectional bus according to some embodiments. [Figure 2-4B] 1 illustrates a photonic circuit for coupling a receiver to a bidirectional bus according to some embodiments. [Figure 2-5] 1 illustrates an example of a waveguide intersection, according to some embodiments. [Figure 2-6A] 1 illustrates yet another architecture in which tiles of a photonic interposer are interconnected using programmable connections, according to some embodiments. [Figure 2-6B] 2-6B shows an example of a coupler used in the examples of FIGS. 2-6A, according to some embodiments. [Figure 2-6C] 1 illustrates an architecture in which tiles of a photonic interposer are interconnected using programmable connections, according to some embodiments. [Figure 2-6D] 1 illustrates another architecture in which tiles of a photonic interposer are interconnected using programmable connections and fibers, according to some embodiments. [Figure 2-7A] 1 illustrates an architecture that uses wavelength-based tile identification, according to some embodiments. [Figure 2-7B] 1 illustrates another architecture that uses wavelength-based tile identification, according to some embodiments. [Figure 2-7B-1]1 illustrates another architecture that uses wavelength-based tile identification, according to some embodiments. [Figure 2-7C] 1 illustrates yet another architecture using wavelength-based tile identification in accordance with some embodiments. [Figure 2-7D] 2-7C illustrate an example of a programmable optical loopback used in the examples of FIGS. 2-7C, according to some embodiments. [Figure 2-8A] 1 illustrates an ASIC with an Advanced Interface Bus (AIB) interface according to some embodiments. [Figure 2-8B] 1 illustrates an ASIC-ASIC connection using an AIB interface and optical links according to some embodiments. [Figure 2-8C] 1 illustrates a photonic interposer hosting multiple ASICs that communicate with each other via an AIB interface according to some embodiments. [Figure 2-9A] FIG. 2 is a block diagram illustrating a pair of ASICs interconnected using a wire-bundle (WoR) interface in accordance with some embodiments. [Figure 2-9B] FIG. 2 is a block diagram illustrating another pair of ASICs interconnected using a wire-bundle (WoR) interface in accordance with some embodiments. [Figure 2-10A] FIG. 1 is a schematic diagram illustrating a computing network architecture using a photonic interposer, according to some embodiments. [Figure 2-10B] FIG. 1 is a schematic diagram illustrating another computing network architecture using a photonic interposer, according to some embodiments. [Figure 2-10C] FIG. 1 is a schematic diagram illustrating yet another computing network architecture using a photonic interposer in accordance with some embodiments. [Figure 2-10D] FIG. 1 is a schematic diagram illustrating yet another computing network architecture using a photonic interposer in accordance with some embodiments. [Figure 3-1] FIG. 2 is a block diagram illustrating a plesiochronous clock distribution scheme according to some embodiments. [Figure 3-2] FIG. 2 is a block diagram illustrating a mesochronous clock distribution scheme according to some embodiments. [Figure 3-3A] 1 is a block diagram illustrating a portion of a photonic interposer configured to perform equalization, according to some embodiments. [Figure 3-3B] 1 is a block diagram illustrating an example of an adaptive equalizer, according to some embodiments. [Figure 3-4A] 4 illustrates a sequence for tuning a transmitter according to some embodiments. [Figure 3-4B] 4 illustrates a sequence for tuning a transmitter according to some embodiments. [Figure 3-4C] 4 illustrates a sequence for tuning a transmitter according to some embodiments. [Figure 3-5A] 4 illustrates a sequence for tuning a receiver according to some embodiments. [Figure 3-5B] 4 illustrates a sequence for tuning a receiver according to some embodiments. [Figure 3-6A] 1 illustrates a technique for locking a receiver to a particular transmitter using dithering, according to some embodiments. [Figure 3-6B] 1 illustrates an optical channel supporting communication between multiple transmitter-receiver pairs according to some embodiments. [Figure 4-1A] 1 illustrates a photonic integrated circuit (PIC) having a photonic circuit and multiple fiber attachments according to some embodiments. [Figure 4-1B] FIG. 2 is a block diagram illustrating a pair of PICs connected to each other using k fibers, some of which are provided for redundancy only, according to some embodiments. [Figure 4-1C]1 shows the overall system yield (%) for a system with 16 fiber attachment sites as a function of the number of attachments at each site, according to some embodiments. [Figure 4-2] 1 illustrates a photonic interposer having multiple tiles, one of which is provided for redundancy, according to some embodiments. [Figure 4-3] 1 is a schematic diagram illustrating a power monitoring grid embedded in a photonic interposer according to some embodiments. [Figure 5-1] 1 is a schematic diagram illustrating a fiber coupled to a grating coupler according to some embodiments. [Figure 5-2A] FIG. 1 is a schematic diagram illustrating a wafer patterned with multiple photonic circuits according to some embodiments. [Figure 5-2B] FIG. 5-2B is a cross-sectional view of the wafer of FIG. 5-2A according to some embodiments. [Figure 5-3A] FIG. 2 illustrates a side view of a photonic interposer, according to some embodiments. [Figure 5-3B] FIG. 2 illustrates a side view of a packaged photonic interposer according to some embodiments. [Figure 5-4] 1 is a flowchart illustrating a process for manufacturing a packaged photonic interposer according to some embodiments. [Figure 5-5] 10 is a flowchart illustrating another process for manufacturing a packaged photonic interposer in accordance with some embodiments. [Figure 5-6] 13 is a flowchart illustrating yet another process for manufacturing a packaged photonic interposer, according to some embodiments. [Figure 5-7] FIG. 1 is a schematic diagram illustrating a packaged photonic interposer including a voltage regulator module (VRM) according to some embodiments. [Figure 5-8A] FIG. 2 is a block diagram illustrating a VRM, according to some embodiments. [Figure 5-8B]FIG. 2 is a schematic diagram illustrating a package in which power delivery to an electronic chip is performed using a VRM, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0060] I. Overview The inventors recognize and understand several challenges that limit the scalability of modern digital computing. First, current designs are power limited. Modern computing trends lead to ever-increasing power consumption, which limits its scalability. In addition, the highly power-hungry nature of modern chips results in high temperature hot spots, often exceeding 1000° C. High temperatures effectively limit computer performance. Second, modern computing architectures are bandwidth limited. These architectures rely on multiple memory chips to provide the hundreds of gigabytes or terabytes of capacity required by modern applications. Unfortunately, providing connectivity between several memory chips is challenging. The physical space available on a board or rack to accommodate interconnects is limited, thus limiting overall bandwidth. In addition, maintaining coherence and consistency across several memory chips (e.g., memory-to-memory and processor-to-memory) is difficult to achieve. Some architectures rely on Peripheral Component Interconnect (PCI), Compute Express Link (CXL), or Ethernet for chip-to-chip communication. However, these interfaces involve board-level or rack-level communication, which increases power usage and reduces bandwidth. Wafer-scale electrical communication has also been considered, but this approach suffers from reliability issues and power inefficiencies.

[0061] The inventors have developed photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and / or rack-level) and intra-chip communication. Described herein are techniques, architectures, and processes that improve the performance of conventional multi-chip computers. Some embodiments provide photonic interposers that use "photonic modules" (also referred to herein as "photonic tiles" or simply "tiles"). Each tile contains programmable photonic circuitry that can be programmed based on the needs of a particular computer architecture. Some photonic interposers are arranged according to a one-dimensional scheme, such as a block of 3x1 tiles, a block of 5x1 tiles, a block of 10x1 modules, a block of 20x1, etc. Some photonic interposers are arranged according to a two-dimensional scheme, such as a block of 3x3 tiles, a block of 5x3 tiles, a block of 5x5 tiles, a block of 10x10 tiles, etc. More generally, photonic interposers allow for any block of NxM tiles, where N>=1 and M>=1, and any topology, such as T-topology, L-topology, X-topology, etc. Each tile can function as a node of a computing system, which may include one or more digital processor chips, one or more analog accelerators, one or more photonic accelerators, one or more memory chips, one or more networking chips, or other devices.

[0062] The photonic interposers described herein are engineered to limit manufacturing costs. These platforms may rely on the use of a common photomask set (or at least one common photomask) to fabricate multiple tiles. This approach reduces costs in two ways. First, it reduces the additional costs that would have been incurred in procuring multiple different photomask sets. Second, it allows the tiles to be manufactured using standard semiconductor foundries that require the same photomask set (or at least one photomask) to be used across the entire wafer. Designing tiles to share at least one photomask allows many tiles to be manufactured on the same semiconductor wafer while leveraging standard low-cost step-and-repeat manufacturing processes. Thus, in some embodiments, the tiles are instantiations (copies) of a common template tile that are stitched together in a 1D or 2D arrangement. Some embodiments include two template tiles such that each tile of the interposer is formed as either an instantiation of the first template tile or an instantiation of the second template tile. The tiles of the different templates may alternate, for example in a checkerboard pattern, with each tile of the first type adjacent to a tile of the second type. Other arrangements are also possible.

[0063] In one example, the photonic interposer includes a 6x8 array of tiles, where each tile is an instantiation of a reticle shot in a step-and-repeat manufacturing process. Each tile is 24.8mm x 32mm in size and can support heterogeneous technologies (e.g., general-purpose processors, GPUs, DRAM / HBM stacks, or custom accelerators). With a 3μm waveguide pitch, the photonic interposer can support well over 10,000 optical links emanating from each tile.

[0064] Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together using photonic links. The communicating tiles need not be adjacent. For example, the physical network can be programmed such that a tile located in the upper left corner can directly communicate with a tile in the lower right corner without retransmissions in the middle tiles. The network configuration time can be less than 10 μs, and communication between any two tiles, whether adjacent to each other or not, can have a transition latency of less than 5 ns. The photonic interposer described herein provides the flexibility to form various logical network topologies (e.g., from a low-radix large-diameter mesh topology to a high-radix small-diameter bus topology). For example, a 4×4 photonic interposer can map an all-to-all logical network with a dedicated channel between each pair of tiles, which can provide up to 14.4 Tbps of bandwidth per channel (between any two tiles) with a total bisection bandwidth of up to 1851 Tbps. As another example, the photonic interposer can provide up to 231 Tbps of bandwidth per channel for a 2-ary, 4-fly butterfly network.

[0065] The photonic interposer described herein enables an efficient heterogeneous architecture solution, whereby chips designed from different technology nodes and performing different functions can be housed together on a single wafer, while providing high bandwidth and low latency between the chips via photonic links. Additionally, the photonic interposer described herein can address thermal constraints associated with high power consumption chips, as it allows for slicing large chips into multiple smaller chiplets. The photonic interposer can host these smaller chiplets and provide energy-efficient communication (similar to on-chip communication) between these smaller chiplets.

[0066] In a multi-chip system, each chip is typically connected to a dedicated main memory. Typically, data is shared between multiple chips (e.g., via a Last Level Cache (LLC) or L2) using Remote Direct Memory Access (RDMA). The photonic interposer described herein can aggregate the main memory of all chips to form a shared global main memory. This global shared main memory is accessible to all chips via a photonic link. For example, LLCs can be sliced ​​from each chip, and the LLCs can be moved next to a common global shared main memory, allowing low latency and high bandwidth communication between each chip's L2 and LLC pairs. Keeping all LLCs together allows for coherency management across LLCs with low overhead. In some embodiments, the photonic interposers described herein can reduce the overhead of using standard cache coherence protocols (e.g., IV, MESI, and MOESI) across chips, for example, by enabling efficient design of cache coherent non-uniform memory access (NUMA) architectures.

[0067] In traditional architectures, processor chips communicate with memory chips (e.g., DRAM and HBM) using high-speed electrical links. However, the capacitance associated with the electrical links limits the available bandwidth and leads to power consumption. Recently, Co-Packaged Optics (CPO) has emerged as a potential alternative to electrical links. CPO provides communication between processors and memories using optical fiber-based communication links. Unfortunately, CPO is not a scalable solution in that it remains difficult to use fiber links to support communication between one processor chip and multiple memory chips and vice versa. In contrast, photonic interposers described herein can host processor chips and memory chips on the same substrate, enabling high-bandwidth density communication. Taking advantage of their wafer-scale nature, photonic interposers can spread processors across multiple tiles such that there is enough area for processor components and many memory controllers. This enables architectures that require multiple memory controllers on each processor chip, such as from one processor chip to multiple memory chips and from one memory chip to multiple processor chips.

[0068] The photonic interposers described herein can be used in a wide variety of applications, including machine learning, privacy protection, and graph applications. The photonic interposers can be used to support communication between analog computing chips (e.g., photonic, memristor) and memory chips, communication between digital computing chips (e.g., processors FPGAs GPUs) and memory chips, networking chips, digital switch chips, and communication between digital and analog computing chips.

[0069] Current machine learning models involve large amounts of data (e.g., often hundreds of GB to tens of TB). Thus, large amounts of memory are required to store the models and data. Current technology does not provide sufficient memory within a single chip. The photonic interposer described herein provides a solution for integrating multiple memory chips onto a single substrate while providing high bandwidth, low latency communication between the memory chips and the computing chips. This results in faster execution times during both training and inference operations.

[0070] As data privacy becomes a primary concern in designing systems, various privacy-preserving computing techniques have been proposed. One of these techniques is homomorphic encryption (HE). Memory bandwidth and latency are the main bottlenecks in HE-based applications. The photonic interposer described herein can alleviate this problem by providing access to memory with high bandwidth and low latency.

[0071] Graph applications involve irregular access to memory. Furthermore, graph applications involve small data granularity since they typically do not use all the data present in a cache line. The photonic interposer described herein can overcome this bottleneck by enabling efficient access to memory through a high-bandwidth, low-latency photonic link.

[0072] SUMMARY Described herein are architectures, systems, and processes that include tile-based photonic interposers. II. Tiled Photonic Interposer FIG. 1-1 illustrates an example of a computing system based on a photonic interposer with nine tiles arranged in a 3x3 topology, according to one example. The computing system 10 includes a photonic interposer 20 patterned with nine tiles 22. The photonic interposer supports one processor die (30) positioned in the center of the photonic interposer 20 and eight memory nodes surrounding the processor die. Some of the memory nodes include a single memory chip (see, e.g., memory die 32). Other memory nodes include stacked memories that include multiple vertically stacked memory dies (see, e.g., stacked memory 34). The dies are stacked on a wafer that defines tiles. The dies can communicate electronically (e.g., using through-silicon vias, copper pillars, microbumps, ball grid arrays, or other electrical interconnects) and / or optically (e.g., using grating couplers, prisms, lenses, or other optical couplers) with the tiles disposed below.

[0073] As will be described in more detail below, tiles may be patterned with optical waveguides and optical distribution networks. The optical distribution networks of tiles may selectively place the die of that particular node in optical communication with any other die of the computing system. For example, the optical distribution networks of tiles positioned under the processor die 30 may be reconfigured depending on the needs of the processor. At the start of a routine, the processor may need to access data stored in a first memory node. This read operation involves configuring the respective optical distribution network to place the processor in optical communication with the first memory node. Later in the routine, the processor may need to write data to a second memory node. This write operation involves reconfiguring the optical distribution network to place the processor in optical communication with the second memory node.

[0074] Fabricating tiles at scale can be costly. The photonic interposers described herein are engineered to limit manufacturing costs. These platforms rely on the use of a common set (subset) of photomasks to fabricate multiple tiles. This approach reduces costs in two ways. First, it eliminates the additional costs incurred in sourcing multiple different photomask sets. Second, it allows tiles to be fabricated using standard semiconductor contract foundries, some of which require the same photomask set (or at least one photomask) to be used across an entire wafer. Designing tiles that share at least one photomask allows multiple tiles to be fabricated on the same semiconductor wafer while leveraging standard, low-cost step-and-repeat manufacturing processes.

[0075] The tiles described herein may be fabricated using microfabrication techniques, including, for example, complementary metal oxide semiconductor (CMOS) microfabrication techniques. Accordingly, some embodiments relate to silicon photonic-based photonic interposers. Some specific microfabrication techniques include a step-and-repeat approach, whereby a stepper machine is used to pattern a semiconductor wafer with multiple copies of a template layout (e.g., a reticle). Each tile resulting from the step-and-repeat approach may correspond to a reticle. Figures 1-2A through 1-2E illustrate microfabrication techniques for fabricating tiles. Figures 1-3A through 1-3B show examples of tiles patterned using these microfabrication techniques.

[0076] Referring first to FIG. 1-2A, this figure illustrates a semiconductor wafer 11. Wafer 11 may be made of any material. For example, wafer 11 may be made of (or otherwise include) silicon. In one example, wafer 11 is a silicon-on-insulator (SOI) wafer. In another example, wafer 11 is a bulk silicon wafer. Wafer 11 may have any size. For example, the diameter of wafer 11 may be 150 mm, 300 mm, or 450 mm, among others, although other values ​​are possible. However, not all wafers need to have a circular shape.

[0077] 1-2B illustrate a set of photomasks that may be used to pattern a wafer 11 using photolithography techniques. Photomask set 200 includes three photomasks (201, 202, and 203), although other sets may include more or fewer photomasks. Each photomask has a particular pattern consisting of opaque and transparent areas. When the photomasks are exposed to light, the opaque areas block the light, thereby preventing it from illuminating the wafer, and the transparent areas allow the light to pass through. As a result, the pattern of the photomask is transferred to the wafer.

[0078] Each photomask may define a particular layer of tiles. One photomask may be used to define the optical waveguides. When the wafer goes through an etching process, only the exposed areas (or only the unexposed areas) are etched away, while other areas remain unetched. This photomask may be patterned to form a network of optical waveguides when the wafer is exposed through this photomask. Figures 1-2C illustrate a portion of a photomask that may be used to form the waveguides on the wafer 11. The lines of the photomask 201 represent the opaque areas. The background of the photomask 201 is transparent. When the photomask 201 is exposed so that an image of the photomask is projected onto the wafer 11, it is possible to pattern the waveguides in the shape of the opaque areas. In this particular example, the pattern of lines on the photomask becomes a grid of waveguides.

[0079] Some tiles involve the use of different levels of optical waveguides. In some such embodiments, photomask set 200 may include a dedicated photomask for each waveguide level. A separate photomask may be used to define n-doped regions. When the wafer goes through an ion implantation or dopant diffusion process, only exposed regions (or only unexposed regions) receive doping, while other regions remain undoped. A separate photomask may be used to define p-doped regions using a similar process. Some tiles involve the use of different doping concentrations. In some such embodiments, photomask set 200 may include a dedicated photomask for each doping concentration. In other embodiments, photomask set 200 may include photomasks used to define the deposition of semiconductor materials other than silicon, such as germanium, and / or other materials of the periodic table, such as Group III or Group V. A separate photomask may be used to define metal contacts. A separate photomask may be used to define metal traces. Some tiles involve the use of different levels of metal traces. In some such embodiments, photomask set 200 may include a dedicated photomask for each metal trace level.

[0080] In some embodiments, the wafer 11 is patterned in a step-and-repeat fashion. As the wafer 11 is processed in a stepper machine, the pattern of a photomask is repeatedly exposed in a grid across the surface of the wafer. This process involves stepping the wafer back and forth and side to side under the stepper's lens, exposing the photomask at each step. As a result, the wafer 11 is patterned with multiple copies of the pattern defined by the photomask. This operation may be repeated for each photomask (or for at least some of the photomasks) of the set. Thus, in some embodiments, the tiles are copies of a common template tile that are stitched together in a 1D or 2D arrangement. Other embodiments include two template tiles such that each tile of the interposer is formed as either an instantiation of a first template tile or an instantiation of a second template tile. The tiles of the different templates may be alternated, for example, in a checkerboard manner, such that each tile of the first type is adjacent only to tiles of the second type. Other arrangements are also possible.

[0081] In the example of Figures 1-2D, wafer 11 is patterned with a grid of tiles 22. The tiles may share one or more photomask patterns of set 200. For example, the tiles may share the same waveguide photomask and / or the same metal trace photomask pattern. In other embodiments, the tiles share all of the photomask patterns of set 200. For example, the tiles may share the same optical waveguide pattern, the same n-doped pattern, the same p-doped pattern, the same contact pattern, the same metal trace pattern, etc.

[0082] In some embodiments, the entire surface of wafer 11 is patterned using photomask set 200. However, not all embodiments are limited in this respect as one portion of wafer 11 may be patterned using a first photomask set and another portion of wafer 11 may be patterned using a second photomask set. The first photomask set may correspond to a first reticle and the second photomask set may correspond to a second reticle. The first and second types of reticles may be arranged in an alternating checkerboard fashion.

[0083] Once patterned, the wafer 11 may include multiple photonic circuits. In one example, the wafer of FIG. 1-2E is marked to obtain six photonic circuits from the wafer 11. The photonic circuits are monolithically integrated with the wafer. The figure identifies a 1×1 photonic circuit having only one tile 22, a 2×2 photonic circuit having four tiles 22, a 2×3 photonic circuit having six tiles 22, and three 3×3 photonic circuits each having nine tiles 22. Separating the photonic circuits from the wafer involves dicing the wafer along the perimeter of the desired photonic circuit. In this regard, the photonic circuits described herein may be considered wafer-level architectures. Once diced, each optical photonic circuit forms an independent photonic interposer. One of the 3×3 photonic circuits of the wafer 11 may be used as a photonic interposer for the example computing system of FIG. 1-1. (See photonic interposer 20.) 1-3A show an exemplary tile 22. In this example, the tile 22 is shaped as a rectangle (although other shapes such as a square or other polygons are also possible). As such, the tile 22 is bounded by four boundaries (boundaries 1, 2, 3, and 4). Boundary 1 faces boundary 2, and boundary 3 faces boundary 4. Boundary 1 is adjacent to boundary 3 and boundary 4, and boundary 2 is also adjacent to boundary 3 and boundary 4. The tile 22 includes an optical distribution network 104 coupled to waveguides 111, 112, 113, and 114. The waveguide 111 optically couples the optical distribution network 104 to boundary 1. As such, an optical signal coupled from the optical distribution network 104 to the waveguide 111 can be transferred outside the tile by crossing the boundary 111. Similarly, waveguide 112 optically couples optical distribution network 104 to boundary line 2, waveguide 113 optically couples optical distribution network 104 to boundary line 3, and waveguide 114 optically couples optical distribution network 104 to boundary line 4. In some embodiments, the boundary lines of the tiles are defined based on a photolithography shot (e.g., the boundary lines are defined by the boundary lines of a photomask used to fabricate the tiles). However, in other embodiments, a single photolithography shot may define more than one tile. For example, a photomask may be patterned with multiple adjacent instances of a template tile. In some such embodiments, the boundary lines of the tiles are defined where adjacent instances of the template tile meet.

[0084] Although the examples of Figures 1-3A illustrate waveguides coupling the optical distribution network to each of the boundaries, not all embodiments are arranged in this manner. In other embodiments, the tile 22 may include two of these four waveguides, e.g., waveguides 111 and 112, or waveguides 111 and 113. In yet other embodiments, the tile 22 may include three of these four waveguides, e.g., waveguides 111, 112, and 113. The optical distribution network 104 includes photonic components (e.g., photonic switches) for routing optical signals in and out of the tile 22. Additionally, the optical distribution network 104 may include transmitters (providing an electrical-optical interface with electronic chips implemented on the tile) and receivers (providing an optical-electrical interface with electronic chips implemented on the tile). Examples of optical distribution networks are described in detail in the next section.

[0085] In some embodiments, the tiles may include multi-layer photonic waveguides. In the same way that multi-layer conductive traces enhance the electrical signal routing capabilities of electronic circuits, multi-layer waveguides enhance the optical signal routing capabilities of the tiles. In one example, one layer includes silicon waveguides and one or additional layers include silicon nitride waveguides. The choice of material for each waveguide layer may be determined by the wavelength of light to be routed by the waveguide. For example, silicon and silicon nitride layers may be used to route infrared light in the telecommunications band around 1.3 μm or 1.5 μm wavelengths. In some examples, multi-layer waveguides may also include aluminum nitride waveguides that can be used to route visible light up to UV wavelengths, or aluminum oxide waveguides that can be used to route UV light. Each layer may be arranged in a configuration with an optical distribution network that routes signals between the waveguides of the layers, similar to the configuration illustrated in Figures 1-3A.

[0086] The tile 22 may further include one or more out-of-plane couplers (not shown in FIGS. 1-3A ). The out-of-plane couplers may be configured to emit light outside of the xy plane, e.g., in a direction parallel to the Z axis or at an angle to the Z axis. The out-of-plane couplers may be further configured to capture light incident from outside of the xy plane. In some embodiments, the out-of-plane couplers enable optical communication between the tile 22 and a die disposed above the tile and / or below the tile. The out-of-plane couplers may be implemented using any suitable optical components, including, for example, optical gratings, lenses, and prisms. In some embodiments, the optical distribution network may be configured such that the same out-of-plane couplers enable optical communication both from the optical distribution network 104 to the die and from the die to the optical distribution network 104. In some embodiments, the out-of-plane couplers enable optical communication between the tile 22 and a fiber.

[0087] The optical distribution network 104 may selectively couple any component of the tile 22 to any other component of the tile 22, as described in more detail in the next section. For example, the optical distribution network 104 may allow the passage of light between waveguide 111 and waveguide 112, and / or between waveguide 111 and waveguide 113, and / or between waveguide 113 and waveguide 114, etc. This can be accomplished by equipping the optical distribution network with controllable optical switches.

[0088] The tiles 22 may further include electrical connections 117 that may be positioned to provide electrical access to the tiles from electronic chips mounted on the tiles. For example, the electrical connections 117 may be in the form of bonds, bumps, vias, or contact pads that provide a landing surface for other types of vertical chip-to-chip interconnects. The electrical connections 117 may be coupled to transmitters, receivers, and switches of an optical distribution network, thus providing the electronic chips with electrical access to their photonic components.

[0089] A photonic circuit may include multiple tiles connected together to collectively form an optical network. FIG. 1-3B illustrates an example of a 2×3 photonic circuit including six tiles 22. The photonic circuit is obtained by dicing a group of 2×3 tiles out of a wafer 11 (see FIG. 1-2E). The tiles 22 are arranged such that the waveguide 111 of an optical module is aligned with the waveguide 112 of the optical module to the left of the optical module, the waveguide 112 of an optical module is aligned with the waveguide 111 of the optical module to the right of the optical module, the waveguide 113 of an optical module is aligned with the waveguide 114 of the optical module above the optical module, and the waveguide 114 of an optical module is aligned with the waveguide 113 of the optical module below the optical module. As a result, the optical modules form an optical network. The optical distribution network 104 may route optical signals anywhere in or out of the network. For example, assume that a processor is implemented in a tile positioned at the northwest corner of the photonic circuit and a memory is implemented in a tile positioned at the southeast corner of the photonic circuit. A read operation may involve reconfiguring the optical distribution network (e.g., by controlling an optical switch) to place the processor in optical communication with the memory. For example, an optical communication path may be formed to 1) couple the processor to an out-of-plane coupler of the tile in which it is implemented, 2) couple the out-of-plane coupler of that tile to a waveguide 112 of the same tile, 3) couple the waveguide 112 of that tile to a waveguide 111 of an adjacent tile (the central top tile), 4) couple the waveguide 112 of the central top tile to a waveguide 111 of the next adjacent tile (the northeast corner of the circuit), 5) couple the waveguide 114 of the tile positioned at the northeast corner to a waveguide 113 of the tile in which the memory is implemented, and 6) couple the waveguide 113 of the tile in which the memory is implemented to an out-of-plane coupler of the same photonic module.

[0090] As mentioned above, the waveguides of adjacent tiles are optically coupled to each other to allow the passage of light from one tile to the next photonic module. In some embodiments, the ends of the waveguides may be physically connected (although not all embodiments are limited to this particular embodiment, as will be described in more detail below). In other embodiments, there may be gaps between the waveguides. In this example, each waveguide has an end located at a distance from the boundary line. Thus, gaps are formed in the boundary region. Despite the gaps, the waveguides of adjacent tiles are still optically coupled to each other. In this case, in fact, light emitted at the end of one waveguide reaches the end of the other waveguide by free space propagation.

[0091] In some embodiments, the tiles 22 may be patterned according to a common metal trace photomask. As a result, the tiles share the same pattern of metal traces. In some embodiments, the tiles 22 are patterned according to multiple common photomasks. As a result, multiple levels of metal traces share the same pattern across different tiles. Some of the metal traces may be used to deliver power across the photonic circuit. For example, some of the metal traces may be arranged to form a power grid, as described in more detail below. Figures 1-4A illustrate a 2x3 photonic circuit, with each tile 22 sharing the same pattern of metal traces. For purposes of illustration, only metal traces are shown in this figure, but each tile further includes a waveguide, one or more out-of-plane couplers, and an optical distribution network. In this example, there are two levels of metal traces. The metal traces on each level are fabricated using the same photomask across different tiles. The metal traces on metal trace level 1 run horizontally, thereby electrically coupling horizontally adjacent tiles to each other. The metal traces on metal trace level 2 run vertically, electrically coupling tiles that are vertically adjacent to each other. Of course, other arrangements are possible. For example, in other embodiments, metal traces on the same level may electrically couple a tile to all of its neighbors.

[0092] The metal traces are arranged to carry electricity (e.g., signals and / or power) across the boundaries of the tiles. This may be achieved by patterning the metal traces to be continuous across the boundaries of the tiles. In this example, the metal traces on level 1 are continuous across the vertical boundaries and the metal traces on level 2 are continuous across the horizontal boundaries. Metal traces on different levels may be connected to each other using vias. In some embodiments, the tiles may share the same pattern of vias. In other words, the same via photomask may be used for each tile. In some embodiments, the tiles may have a larger number of metal traces (tens to hundreds). Some of these metal traces may be arranged to be continuous across the tiles, but in some embodiments, most of the metal traces do not need to be patterned to be continuous across the module. In one example, some metal traces may be patterned such that they do not reach the ends of the group of tiles, as shown in Figures 1-4B. This creates a moisture barrier between the die lanes and the metal. Additionally, these metal traces for transmitting signals and / or power may be connected to through-silicon vias (TSVs) that connect to other chips located on the substrate and / or tile, and in some embodiments, the metal traces may be connected to transistor elements that can act as electronic switches, amplifiers, or TX / RX components.

[0093] III. Optical Distribution Network This section describes an architecture for interconnecting tiles of a photonic interposer to each other in a manner that enables high bandwidth, low latency, and high resource utilization. The interconnects can be static or programmable.

[0094] A. Static Connection FIG. 2-1A shows an example where tiles of a photonic interposer are interconnected using static connections. This example shows an interposer with four tiles arranged in one dimension. Each tile has a transmitter (TX) and a receiver (RX). The transmitter may include (or be coupled to) a light source and an optical modulator. The optical modulator may be configured to encode light with information provided by the electronic chip to which the tile is connected. Each receiver may include a photodetector that converts the signal provided by the transmitter into electricity. In this arrangement, a waveguide couples the TX of a tile to the RX of an adjacent tile. This arrangement is referred to as "one hop right" in that each waveguide reaches the RX immediately to the right of the TX.

[0095] Figure 2-1B shows another example where tiles of a photonic interposer are interconnected using static connections. In this example, a waveguide couples the TX of a tile to the RX of a second adjacent tile. This arrangement is called "two hops right" in that each waveguide reaches the RX two steps to the right of the TX.

[0096] FIG. 2-1C shows yet another example where tiles of a photonic interposer are interconnected using static connections. In this example, a waveguide couples the TX of a tile to the RX of a third adjacent tile. This arrangement is called "3 hops right" in that each waveguide reaches an RX three steps to the right of the TX.

[0097] The arrangements in Figures 2-1D, 2-1E, and 2-1F are similar to those in Figures 2-1A, 2-1B, and 2-1C, respectively, but with the addition of optical fibers to close the loop. The use of fibers increases flexibility in that information can flow in a closed-loop fashion. In Figure 2-1D, the fibers loop around the photonic interposer by coupling the TX of Tile 4 with the RX of Tile 1. In Figure 2-1E, a first fiber couples the TX of Tile 4 with the RX of Tile 2, and a second fiber couples the TX of Tile 3 with the RX of Tile 1. In Figure 2-1F, a first fiber couples the TX of Tile 4 with the RX of Tile 3, a second fiber couples the TX of Tile 3 with the RX of Tile 2, and a third fiber combines the TX of Tile 2 with the RX of Tile 1.

[0098] The arrangements of Fig. 2-1D, Fig. 2-1E, and Fig. 2-1F have one drawback: TX can only transmit data in one direction (right in these examples), and RX can only receive from the opposite direction (left in these examples). Thus, such networks cannot maintain bidirectional links between two pairs of TX and RX modules. To implement bidirectional links, a complementary network with cascaded waveguides in opposite directions can be included. Examples are shown in Fig. 2-1G and 2-1H (implementing one-hop and two-hop schemes, respectively). In each arrangement, links are provided in both directions. TX1, TX2, TX3, and TX4 transmit data in one direction, and TX5, TX6, TX7, and TX8 transmit data in the opposite direction. Similarly, RX1, RX2, RX3, and RX4 receive data from one direction, and RX5, RX6, RX7, and RX8 receive data from the opposite direction. Tile 1 includes TX1, RX1, TX5, and RX5. Tile 2 includes TX2, RX2, TX6, and RX6. Tile 3 includes TX3, RX3, TX7, and RX7. Tile 4 includes TX4, RX4, TX8, and RX8.

[0099] However, such an arrangement does not provide a bidirectional link between two adjacent pairs of TX and RX. In practice, it is desirable for the first tile to transmit to the second tile and for the second tile to reply to the first tile. To implement a bidirectional link between two pairs of TX and RX modules, it is proposed to implement a "swap" between the TX modules. This is shown in Figure 2-1I. The swap allows the TX module to transmit to the RX connected to the complementary loop. This example shows a two-hop double-loop architecture with swapped TX modules. As a result, TX1 can transmit to RX7 and TX7 can reply to RX1, closing the bidirectional link.

[0100] B. Programmable Connections The static connections described above do not allow for reconfiguration based on the needs of the network, and the network topology is fixed. However, allowing the network to dynamically reconfigure itself according to the needs of the users can be useful in certain applications. Thus, some embodiments relate to programmable connections between tiles of a photonic interposer. The arrangement of FIG. 2-2A is similar to the arrangement of FIG. 2-1F in that both arrangements implement a three-hop architecture. However, instead of having static connections, the arrangement of FIG. 2-2A includes waveguide buses (four in this example, equal to the number of tiles). Each bus can couple any TX to any RX. Each transmitter and each receiver can be selectively connected to the bus through a switch. The connection points are identified as "nodes" in FIG. 2-2A. When a transmitter activates a switch, the transmitter can transmit data using the bus waveguide. Similarly, when a receiver activates a switch, the receiver can listen for data from the bus waveguide. Three fibers are used to close the loop. In this example, a first bus connects TX1 to RX4, a second bus (with a first fiber) connects TX2 to RX1, a third bus (with a second fiber) connects TX3 to RX2, and a fourth bus (with a third fiber) connects TX4 to RX3. The network can be reconfigured using switches to change the number of hops from 3 to 1 or 2.

[0101] To implement a bidirectional link, a dual loop architecture with swapped TX (similar to the architecture of FIG. 2-1I) can be used. This is shown in FIG. 2-2B. However, unlike the architecture of FIG. 2-1I, this architecture includes a bus and nodes, allowing for dynamic reconfiguration of the network.

[0102] FIG. 2-2C illustrates another photonic interposer with programmable connections, according to some embodiments. This example includes four tiles, but any number of tiles are possible, arranged in 1D or 2D. Each tile includes a transceiver 100 and a programmable photonic interconnect 120. Each transceiver includes one or more instances of a transceiver cell 110. The transceiver cell shown in FIG. 2-2C includes a laser 101, which may be mounted on the same package as the photonic interposer or may be outside the package. The laser 101 emits light at eight separate wavelengths in this example, but a different number of wavelengths is possible. Thus, the architecture of FIG. 2-2C can use wavelength division multiplexing (WDM) to increase data throughput. A TX bus 102 receives light from the lasers and is optically coupled to multiple modulators 104. Each modulator is coupled to a respective TX module, which may include a digital-to-analog converter and a modulator driver. The PLL time the operation of the TX module. The TX module may then be coupled to an electronic chip implemented on the photonic interposer corresponding to a tile. Each modulator 104, implemented in this example as a ring (or disk) resonator, is tuned to a different emission wavelength (λ0...λ7) of the laser 101. Thus, each modulator is configured to provide data on a different WDM channel. On the receiver side, the RX module is coupled to a drop filter 108, implemented in this example as a ring (or disk) resonator. Each drop filter is tuned to a different emission wavelength (λ0...λ7) of the laser 101. As a result, each drop filter captures data from the RX bus 106 on a specific WDM channel. The RX module may also be coupled to an electronic chip and may include a photodetector, a transimpedance amplifier, and an analog-to-digital converter.

[0103] The programmable photonic interconnects allow communication between tiles (and consequently between electronic chips mounted on the photonic interposer) in a programmable manner. The programmable interconnects form a grid of switchable intersections connected to each other by waveguides, which are arranged to form row and column buses, as shown in FIG. 2-2D. The tiles may further include electrical connections 117, which may be arranged to provide electrical access to the tiles from the electronic chips mounted on the tiles. For example, the electrical connections 117 may be in the form of bonds, bumps, vias, or contact pads that provide a landing surface for other types of vertical inter-chip interconnects. The electrical connections 117 may be coupled to the transceiver 100.

[0104] In the example of Figure 2-2C, the programmable interconnects are programmed to enable communication between each tile and every other tile. In this figure, a first optical path is formed between tiles 1 and 4, a second optical path is formed between tiles 1 and 3, and a third optical path is formed between tiles 1 and 2. Each optical path can support multiple wavelengths.

[0105] FIG. 2-2E illustrates an exemplary implementation of the programmable photonic interconnect 120 according to some embodiments. The programmable photonic interconnect includes active couplers 126 coupled to each other via waveguides. As further illustrated in FIG. 2-2F (which shows an example of an active coupler), each active coupler may provide a one-to-many waveguide coupling configuration. The active couplers can operate in both directions. When light propagates from a single waveguide, the active coupler may select one of the multiple waveguides for the propagation of the light, thereby performing a switching operation. A possible implementation of the active coupler 126 includes cascaded Mach-Zehnder interferometers (MZIs), as further illustrated in FIG. 2-2F (see MZI 127 and MZI 128).

[0106] 2-2E, the central waveguides of the active couplers are coupled to each other to form a waveguide intersection 127. The waveguide intersection 127 presents challenges from a systems perspective in that it introduces insertion loss and crosstalk. Below are examples of waveguide intersections developed by the inventors that provide low insertion loss and low crosstalk.

[0107] The waveguide bus shown in FIG. 2-2D may be bidirectional in some embodiments. In some such embodiments, instead of having a transmit-only bus and a receive-only bus, the tile may transmit and receive using the same bus waveguide. Additionally or alternatively, the transmitter may decide which direction of the bus to transmit data in, and the receiver may decide which direction of the bus to receive data from. An example of such an implementation, according to some embodiments, is shown in FIG. 2-3A. On the TX side, the tile includes couplers 131 arranged to form a light tree. The couplers may be controllable (similar to the active couplers in FIG. 2-2F). Each output branch of the tree is coupled to a bus via couplers 133, 134, and 135. Coupler 133 selects one input and one output. Selecting a waveguide provided by the TX as an input allows coupler 133 to place the tile in a transmit mode. By selecting one of the outputs, the TX can communicate along the bus from right to left or left to right, thus enabling two-way communication. Couplers 134 and 135 determine whether the bus is in add / drop mode (add for transmit, drop for receive) or through mode (bypass tile 1).

[0108] On the RX side, the tile includes couplers 132, also arranged to form an optical tree. Each output branch of the tree is coupled to a bus via couplers 133, 134, and 135, allowing the selection of a right-to-left or left-to-right direction during transmission. In this example, couplers 134 and 135 are implemented as 1×2 couplers and coupler 133 is implemented as a 2×2 coupler, although other configurations are possible. The architecture of FIG. 2-3B is similar to that of FIG. 2-3A in that both architectures use coupler 133. However, the architecture of FIG. 2-3B replaces couplers 133 and 135 with a 2×2 coupler (137).

[0109] Figures 2-4A and 2-4B show additional schemes that allow bidirectional propagation along the bus. On the TX side (Figure 2-4A), the TX is coupled to an MZI, which in turn is coupled to a resonant add filter. Depending on which output of the MZI is selected, either the clockwise or counterclockwise mode of the resonant filter is excited. As a result, transmission on the bus is from left to right or from right to left. On the RX side (Figure 2-4B), the RX is coupled to an MZI, which in turn is coupled to a resonant drop filter. Depending on which input of the MZI is selected, either the clockwise or counterclockwise mode of the resonant filter is selected. As a result, the RX selects the left to right or right to left bus mode.

[0110] FIG. 2-5 shows an example of a waveguide crossover that may be used in some embodiments (e.g., FIG. 2-2E). This implementation includes three waveguide layers (140, 141, and 142). The waveguide layers may be made of, for example, silicon or silicon nitride. In one example, the waveguide layer 140 is made of silicon, and the waveguide layers 141 and 142 are made of silicon nitride. The waveguide crossover is designed to couple mode A from layer 140 to layer 141, then to layer 142, then back from layer 142 to layer 141, and back again to layer 140. A taper can be used to vertically expand and contract mode A. By pushing mode A out of the plane of layer 140, the overlap between modes A and B is limited, thus reducing crosstalk. The inventors have realized that having a three layer scheme as shown herein is advantageous over a two layer scheme in that it can provide the same low insertion loss performance but allows for negligible crosstalk between layers 140 and 142.

[0111] Accordingly, some embodiments are directed to a photonic interposer comprising a plurality of photonic tiles (e.g., tiles 1-4 in FIG. 2-2C) that are instantiations of a template photonic tile. Each of the plurality of photonic tiles comprises a transceiver (100) comprising a transmitter and a receiver. Electrical connections (117) coupled to the transceiver are configured to enable electrical communication between the transceiver and an electronic chip when the electronic chip is attached to the photonic interposer in correspondence with the photonic tile (e.g., as shown in FIG. 1-1). The optical distribution network comprises a first set of bus waveguides (e.g., row buses in FIG. 2-2D) optically coupled to the transceivers, a second set of bus waveguides (e.g., column buses in FIG. 2-2D), and a plurality of programmable interconnects (120). Each programmable interconnect is configured to selectively place one bus waveguide of the first set of bus waveguides in optical communication with one bus waveguide of the second set of bus waveguides. Each programmable interconnect comprises a waveguide intersection (127) and an active coupler (126).

[0112] In some embodiments, the transceiver comprises a plurality of modulators (104) coupled to a first bus waveguide of the first set of bus waveguides and tuned at different wavelengths relative to each other, as shown, for example, in FIG. 2-2C. Additionally, a plurality of drop filters (108) coupled to a second bus waveguide of the first set of bus waveguides are tuned at different wavelengths relative to each other. In some embodiments, the plurality of modulators are resonant modulators and the plurality of drop filters are resonant drop filters.

[0113] In some embodiments, the transmitter is configured to transmit data in either a first direction or a second direction along a first bus waveguide of a first set of bus waveguides, for example, as shown in Figures 2-3A, 2-3B, and 2-4A.

[0114] In some embodiments, each of the plurality of photonic tiles further comprises a 2×2 coupler (133) coupling the transceiver to a first bus waveguide of the first set of bus waveguides. The 2×2 coupler may comprise first, second, third and fourth terminals. The first terminal is coupled to an output of the transmitter. The second terminal is coupled to an input of the receiver. The third and fourth terminals are coupled to the first bus waveguide of the first set of bus waveguides.

[0115] In some embodiments, each of the plurality of photonic tiles further comprises an interferometer (e.g., MZI in FIG. 2-4A) having an input and first and second outputs, and a resonant filter. The transmitter is coupled to the input of the interferometer, and the first and second outputs of the interferometer are coupled to the resonant filter. The resonant filter is coupled to a first bus waveguide of the first set of bus waveguides. Additionally, in some embodiments, each of the plurality of photonic tiles further comprises an interferometer (e.g., MZI in FIG. 2-4B) having an output and first and second inputs, and a resonant filter. The resonant filter is coupled to a first bus waveguide of the first set of bus waveguides. The first and second inputs of the interferometer are coupled to the resonant filter. The receiver is coupled to the output of the interferometer.

[0116] In some embodiments, the waveguide intersection comprises a first waveguide patterned on a first waveguide layer (140), a second waveguide patterned on a second waveguide layer (141), and a third waveguide layer patterned on a third waveguide layer (142). The second waveguide layer is between the first and third waveguide layers, and the first waveguide is evanescently coupled to the second waveguide and the second waveguide is evanescently coupled to the third waveguide. In some embodiments, the first waveguide layer is made of silicon and both the second and third waveguide layers are made of silicon nitride.

[0117] In some embodiments, the active coupler comprises a first terminal coupled to the first additional active coupler, a second terminal coupled to the first additional active coupler, and a third terminal coupled to the waveguide intersection, for example as shown in FIG. 2-2E.

[0118] In some embodiments, the active coupler comprises first and second Mach-Zehnder interferometers (MZIs), for example as shown in Figures 2-2F, where the first terminal corresponds to a first output of the first MZI (128), the second terminal corresponds to a second output of the first MZI, and the third terminal corresponds to an output of the second MZI (127).

[0119] In some embodiments, the bus waveguides of the second set of bus waveguides traverse multiple photonic tiles (eg, tiles 1-4 in FIG. 2-2C). FIG. 2-6A shows another interconnect architecture. The advantage of this architecture over the architecture of FIG. 2-2C is that the waveguide crossing is eliminated. The disadvantage is poor utilization of the transceivers. In this architecture, each tile includes multiple transceivers 100. Each transceiver is coupled to one of the buses (151, 152, 153, 154, and 155). These buses cross the boundaries between tiles and do not cross each other. In this figure, bus 151 allows communication between tiles 1 and 2 and between tiles 3 and 4. bus 152 allows communication between tiles 1 and 3. bus 153 allows communication between tiles 2 and 4. bus 154 allows communication between tiles 1 and 4. bus 155 allows communication between tiles 2 and 3. The transceiver-bus connections can be programmed according to the needs of the network. The coupler 156 is used to selectively couple or isolate the transceiver to the bus. An exemplary implementation of the coupler 156 shown in Figures 2-6B includes an MZI arranged in a closed loop configuration. The MZI allows communication in two directions, whether transmitting or receiving.

[0120] Utilization in the architecture of FIG. 2-6A can be increased by including additional buses. For each row of transceivers across tiles 1-4, there are two buses (e.g., 151A and 151B) to which the transceivers are switchably coupled. One bus can support left-to-right communication and the other bus can support right-to-left communication, thereby closing the loop. However, in some embodiments, both buses may support communication in the same direction. In this figure, bus 151A allows tile 1 to communicate with tile 4, and bus 151B allows tile 1 to communicate with tile 2, tile 2 to communicate with tile 3, and tile 3 to communicate with tile 4. Coupler 156 may be implemented, for example, as shown in FIG. 2-6B. One disadvantage of this configuration is that the links between tiles at opposite ends of the column (e.g., tiles 1 and 4) are longer than the other links, resulting in higher optical loss.

[0121] The architecture of FIG. 2-6D addresses this problem by connecting remote tiles using optical fibers. In this architecture, the tiles are arranged in two blocks of 1×2 tiles. The first block includes tiles 1 and 2, and the second block includes tiles 3 and 4. Each tile includes multiple transceivers 100. Tiles 1 and 2 communicate with each other using buses 161A and 161B. Having two buses allows for bidirectional communication. For example, TX of tile 1 can send data to RX of tile 2 using bus 161A, and TX of tile 2 can send data to RX of tile 1 using bus 161B. Similarly, tiles 3 and 4 communicate with each other using buses 164A and 164B. In one example, TX of tile 3 can send data to RX of tile 4 using bus 164A, and TX of tile 4 can send data to RX of tile 3 using bus 164B. Thus, buses 161A, 161B, 164A, and 164B can be considered intra-block buses. Alternatively, buses 162A, 162B, 163A, and 164B may be considered inter-block buses. Bus 162A connects to bus 163B via fibers 166A and 168A. Similarly, bus 162B connects to bus 163A via fibers 166B and 168B.

[0122] Compared with the architecture of FIG. 2-6C, the architecture of FIG. 2-6D shortens the on-chip path connecting tile 1 and tile 4. Part of the on-chip path connecting tile 1 and tile 4 is replaced with fiber. The loss introduced by the fiber can be lower than the loss introduced by the integrated waveguide, so the overall loss is reduced.

[0123] Accordingly, some embodiments are directed to a photonic interposer comprising a plurality of photonic tiles (e.g., tiles 1-4 in FIG. 2-6D) that are instantiations of a template photonic tile. Each of the plurality of photonic tiles comprises a first transceiver (100). An electrical connection (not shown in FIG. 2-6D) coupled to the first transceiver is configured to enable electrical communication between the first transceiver and an electronic chip when the electronic chip is attached to the photonic interposer in correspondence with the photonic tile, e.g., as shown in FIG. 1-1. First and second bus waveguides (162A and 162B) traverse the first and second photonic tiles, respectively, and third and fourth bus waveguides (163A and 163B) traverse the third and fourth photonic tiles, respectively. The first fiber (166A), the first bus waveguide (162A), and the fourth bus waveguide (163B) place the first transceiver of the first photonic tile in optical communication with the first transceiver of the fourth photonic tile, and the second fiber (166B), the second bus waveguide (162B), and the third bus waveguide (163A) place the first transceiver of the second photonic tile in optical communication with the first transceiver of the third photonic tile.

[0124] In some embodiments, each of the plurality of photonic tiles further comprises a second transceiver. The second transceiver of the first photonic tile is in optical communication with the second transceiver of the second photonic tile (e.g., via buses 161A and / or 161B). Similarly, the second transceiver of the third photonic tile can be in optical communication with the second transceiver of the fourth photonic tile (e.g., via buses 164A and / or 164B).

[0125] In some embodiments, the interposer further comprises a third fiber (168A). The third fiber (168A), the first bus waveguide (162A), and the fourth bus waveguide (163B) further place the first transceiver of the first photonic tile in optical communication with the first transceiver of the fourth photonic tile. The first fiber, the third fiber, the first bus waveguide, the fourth bus waveguide, the first transceiver of the first photonic tile, and the first transceiver of the fourth photonic tile can form a closed loop. The interposer may further comprise a fourth fiber (168B). The fourth fiber (168B), the second bus waveguide (162B), and the third bus waveguide (163A) further place the first transceiver of the second photonic tile in optical communication with the first transceiver of the third photonic tile. The second fiber, the fourth fiber, the second bus waveguide, the third bus waveguide, the first transceiver of the second photonic tile, and the first transceiver of the third photonic tile may also form a closed loop.

[0126] C. Wavelength-Based Tile Identification The architecture described in connection with Figures 2-1A through 2-6D leverages WDM to increase the aggregate bandwidth of each tile-to-tile optical link. In other embodiments, wavelengths can be used to uniquely identify each tile. In a four-tile architecture, for example, wavelength λ0 can uniquely identify tile 1, wavelength λ1 can uniquely identify tile 2, wavelength λ2 can uniquely identify tile 3, and wavelength λ3 can uniquely identify tile 4. Thus, a receiver can identify the origin of data collected from a bus simply by determining the wavelength that supports the data. An example is shown in Figure 2-7A. The architecture includes four tiles. A first set of transceivers 100 are connected by bus 171, a second set of transceivers 100 are connected by bus 172, and a third set of transceivers 100 are connected by bus 173. Each transceiver is labeled with a pair of numbers (x and y). The first number (x) identifies the transmission wavelength of the transceiver's transmitter. The second digit (2) identifies the wavelength that the transceiver's receiver is configured to read. Note that the x digit is the same for all transceivers in a particular tile. This allows the system to uniquely identify a transmitter by its wavelength.

[0127] In the example of FIG. 2-7B, each tile in a row has a unique transmission wavelength. However, wavelengths are reused across different rows. The first row includes rows 1-4, and the second row includes tiles 5-8. In this example, wavelength λ0 can uniquely identify tiles 1 and 5, wavelength λ1 can uniquely identify tiles 2 and 6, wavelength λ2 can uniquely identify tiles 3 and 7, and wavelength λ3 can uniquely identify tiles 4 and 8. Bus set 181 (including three buses) enables communication between the tiles in the first row (tiles 1-4). Bus set 183 (including three buses) enables communication between the tiles in the second row (tiles 5-8). Bus set 182 (including eight buses) enables communication between each tile in the first row and each tile in the second row. Each tile includes a transmitter and a receiver, represented herein in the form of a resonant modulator (TX) and a resonant drop filter (RX). The wavelengths in brackets indicate the transmission wavelength (for TX) and the drop wavelength of the resonant drop filter (for RX).

[0128] The architecture of Figure 2-7C is similar to that of Figure 2-7A, but further includes a programmable optical loopback 190 that allows for a unidirectional traffic lane. The exemplary programmable optical loopback shown in Figure 2-7D is implemented using an MZI.

[0129] IV. Die-to-Die (D2D) Interface The photonic interposers described herein may be used to interconnect application specific integrated circuits (ASICs) in ways that would be impractical (e.g., too costly or energy inefficient) with traditional interfaces. Recently, new die-to-die (D2D) interface standards have emerged that allow chiplets from different sources to communicate with each other. D2D interfaces utilize very short channels to connect two dies in a common package to achieve power efficiency and very high bandwidth efficiency beyond what traditional chip-to-chip interfaces can achieve. D2D interfaces can be viewed as being divided into a Physical Layer (PHY), a Link Layer, and a Transaction Layer. The PHY layer may be implemented using a high-speed SerDes architecture for parallel-to-serial and serial-to-parallel data conversion. The primary role of the SerDes is to minimize the number of I / O interconnects.

[0130] There is currently a great focus in the industry on advanced packaging as electronic interposers and silicon bridges enter mainstream products. Examples of D2D interfaces include Advanced Interface Bus (AIB), Universal Chiplet Interconnect Express (UCIe), and Low-voltage-In-Package-INterCONnect (LIPINCON), among others. Bunch of Wires (BoW) is a relatively new D2D interface designed to standardize some of the interconnects that are expected to become more important in future generations of chips. These interfaces are designed for high-bandwidth communication between electronic ASICs located relatively close together, e.g., a few millimeters apart.

[0131] The inventors recognize and understand that the relatively close proximity set by D2D interfaces imposes practical limitations on the types of computing architectures achievable using these interfaces. The maximum die-to-die distance set by these interfaces (at most a few millimeters) guarantees high bandwidth and reliability, given the constraints of electrical interconnects. The photonic interposer described herein can extend the applicability of conventional D2D interfaces to greater inter-ASIC distances than are possible with conventional electronic interposers. In one example, the use of a photonic interposer can enable AIB-based communication between a pair of ASICs separated by, for example, more than 1 cm, more than 1.5 cm, more than 2.5 cm, more than 3 cm, more than 5 cm, more than 10 cm. Similarly, the use of a photonic interposer can enable UCIe-based communication between a pair of ASICs separated by, for example, more than 1 cm, more than 1.5 cm, more than 2.5 cm, more than 3 cm, more than 5 cm, more than 10 cm. A SerDes interface connected to the photonic interposer can utilize a single photonic channel, whether it be a spatial channel (waveguide or fiber), wavelength channel, or polarization channel, to multiplex wires into a single photonic link. In some embodiments, the photonic channel can support from 56 Gbps using non-return to zero (NRZ) to 112 Gbps using PAM4 modulation.

[0132] FIG. 2-8A illustrates an ASIC with an AIB interface. More specifically, the ASIC includes a "Northwest" AIB unit, a "Southwest" AIB unit, a "Southeast" AIB unit, and a "Northeast" AIB unit. Each AIB includes 24 channels (although other numbers of channels are possible). FIG. 2-8B illustrates how the AIB interface can enable a connection between two ASICs (ASIC0 and ASIC1) using a photonic interposer of the type described herein. The transmitter port in ASIC0 supports 128 wires, with each wire supporting 1.5 Gbps to 2.5 Gbps (e.g., 2 Gbps). An 8:1 SerDes can multiplex signals from 8 wires to generate 12 Gbps to 20 Gbps (e.g., 16 Gbps). The SerDes may be formed directly on the photonic interposer in some embodiments (e.g., using transistors in the SOI wafer hosting the photonic interposer). A modulator formed in the photonic interposer converts the data obtained from the SerDes into an optical signal that is transmitted using a waveguide formed on the interposer or a fiber. On the receiver side, a photodetector receives the signal, the SerDes performs demultiplexing, and the wire provides the data to ASIC1 via the AIB receive port.

[0133] FIG. 2-8C shows a photonic interposer 20 hosting 16 ASICs with AIB interfaces. Each ASIC may be mounted on a respective tile of the photonic interposer, for example, in an arrangement similar to that shown in FIG. 1-1. An external laser module couples light into the interposer using a grating coupler, although edge coupling is also possible. Waveguides formed in the interposer and / or fibers support communication between the ASICs via the AIB interface. Any of the static or programmable photonic interconnects described herein may be used to support communication between the ASICs. It should be noted that the AIB interface described in connection with FIG. 2-8A through FIG. 2-8C may be replaced with other D2D interfaces, including, for example, UCIe.

[0134] FIG. 2-9A shows a pair of ASICs (ASIC0 and ASIC1) communicating with each respective tile (Tile0 and Tile1) of the interposer. In this example, a BoW interface is used. Communication is via waveguides formed in the photonic interposer, although in other embodiments, fiber may be used. In some embodiments, to reduce the number of waveguides crossing tile boundaries, signals may be multiplexed within a single waveguide or fiber using WDM and / or polarization diversity. In the example of FIG. 2-9B, one polarization is used for one transmission direction and the other polarization is used in the opposite direction.

[0135] The photonic interposers described herein enable several types of computer architectures, including those shown in Figures 2-10A, 2-10B, 2-10C, and 2-10D. In the example of Figure 2-10A, the photonic interposer 20 hosts 16 ASICs. Of these, only one (ASIC0) interfaces with components external to the interposer 20 using optical fiber. The ASICs communicate with each other using any one of the interconnects described herein. In the example of Figure 2-10B, fibers are used to close the loop. As a result, a ring network architecture can be formed. This architecture is particularly suitable for applications involving pipeline operations using multiple ASICs. In the example of Figure 2-10C, each ASIC communicates with its neighbors, and further links are formed to enable communication between ASICs located at opposite ends of a column or row. This enables a 2D hypertoroid architecture. Finally, in the example of Figure 2-10D, every ASIC communicates with every other ASIC to form an all-to-all architecture. This architecture is particularly well suited for smaller tier sizes, parallel batch processing, sequential graph processing, and HPC / AI clusters where multi-tenancy is desired.

[0136] The inventors understand that a larger number of hops (in terms of photonic tiles) requires a longer photonic path and / or more photonic switches / intersections. This can lead to more optical loss and crosstalk. The topology of FIG. 2-10A, i.e., the all-to-all topology, represents the baseline topology. The topologies of FIG. 2-10B to FIG. 2-10D are achieved by reducing the number of hops that a particular optical link takes relative to the topology of FIG. 2-10A. Thus, the optical loss of the links in the topologies of FIG. 2-10B to FIG. 2-10D is lower than the optical loss of the links shown in FIG. 2-10A. For efficiency reasons, the laser power / current can be lowered to reduce the amount of redundant light used for each optical link.

[0137] Additional topologies are also possible where the hop count of a particular TX / RX link is higher in the reconfigured topology than in the baseline topology. In this case, that particular optical link may require higher laser power (to compensate for higher losses or crosstalk) to achieve the same performance (e.g., baud and BER). By routing additional power to that link, for example from an optical link with a reduced hop count, the higher laser power can be achieved without increasing the laser power of the entire system. Otherwise, additional laser modules or increased laser module output may be required. Another solution is to use a different communication protocol that is slower, has smaller bits (e.g., going from PAM-4 to NRZ, or from QAM-16 to QAM-4), or accepts a higher bit / symbol error rate, which can be improved by the use of error correction codes.

[0138] VI. Clock Distribution The inventors recognize and understand that it would be impractical to use a single global clock to synchronize an entire photonic interposer and the electronic chips connected to it, in part because a global clock distribution scheme would be complex and require significant power to operate.

[0139] In some embodiments, clock and data recovery (CDR) may be performed by generating a local clock within each tile. CDR recovery may be implemented for each TX / RX pair where the optical communication channel crosses the boundary between the tile and another tile. CDR may be performed in some embodiments using a plesiochronous scheme. Alternatively, CDR may be performed using a mesochronous scheme in some embodiments. Both schemes are described below.

[0140] A. Plesiochronous method In a plesiochronous manner, the clock may be transmitted in the same optical channel in which the data is transmitted. Thus, the same TX and RX circuits are used to transmit / receive the data and the clock. This may be done by operating at a slightly higher bandwidth than would have been required to transmit only the data, to account for CDR overhead. Several protocols may be used, including 8b / 10b, 64b / 66b, 128b / 130b, or 256b / 257b protocols. In general, Xb / Yb protocols convert X bits of data into a string of Y bits to achieve DC balance and provide sufficient state changes for clock recovery and data alignment. An example of a DC-balanced data string is one in which the difference between the count of 1s and the count of 0s in a string of at least 20 bits should not exceed 2, and / or the number of consecutive 1s or 0s (in a row) should not exceed 5. DC balancing may be implemented using linear feedback shift registers in some embodiments. Clock recovery implemented according to these schemes relies on data transitions (eg, rising and / or falling edges).

[0141] The plesiochronous scheme described herein relies on separate local oscillators (LOs), one LO at the transmit side of the channel and one LO at the receive side of the channel. Having separate LOs can result in clock drift. In some embodiments, clock drift may be compensated for using an elastic first-input first-output (FIFO) scheme, where the FIFO depth is established by the length of the packet in parts per million (PPM).

[0142] FIG. 3-1 is a block diagram illustrating a plesiochronous clock distribution scheme according to some embodiments. In this example, the data path includes a communication by a photonic transmitter (TX) 301 located in tile 1 to a photonic receiver (RX) 203 located in tile 2. Routing between tiles can be performed using any of the architectures described above. The optical communication channel 303 (whether implemented as a bus waveguide of the photonic interposer or as a fiber) supports data using an Xb / Yb protocol. The system includes a local oscillator (LO) 310 on the RX side and an LO 316 on the RX side. Each LO may include a dedicated crystal, or alternatively, the LOs may be fed by a common crystal. Optionally, a PLL can be used to multiply the frequency of the LO 310 by a predetermined coefficient, thereby achieving a higher clock frequency. The system further includes an Xb / Yb encoder 312 on the transmit side and a corresponding Xb / Yb decoder 314 on the receive side.

[0143] B. Mesochronous method In a mesochronous approach, the clock is transmitted using a separate optical channel to the data, which may involve separate propagation media (e.g., separate waveguides or fibers), or the same propagation medium but separate wavelengths or polarizations.

[0144] FIG. 3-2 is a block diagram illustrating a mesochronous clock distribution scheme according to some embodiments. As in the previous example, the data path includes communication by a photonic transmitter (TX) 301 located in tile 1 to a photonic receiver (RX) 203 located in tile 2. However, the clock is transmitted using channel 352 and the data is transmitted using channel 350. The channels can represent separate wavelengths or separate polarizations in a physical propagation medium or a common medium. In this scheme, the transmitter includes a LO 310, but the receiver lacks a separate LO. Instead, a PLL 354 recovers the clock based on the signal transmitted via the clock channel 352. Optionally, a PLL 311 can be used to multiply the frequency of the LO 310 by a predetermined coefficient, thereby achieving a higher clock frequency.

[0145] VII. Equalization The inventors have developed techniques for improving data throughput of photonic interposers with analog and / or digital equalization. Equalization improves data throughput by reducing inter-symbol interference (ISI) and, therefore, bit error rate (BER). Equalization may be performed at the transmitter side of the channel, at the receiver side of the channel (or both). Equalization may amplify high frequency components and enable lower BER operation. Several types of equalization techniques may be used, including pre-emphasis feed-forward equalization (FFE), continuous time linear equalization (CTLE), and discrete feedback equalization (DFE). Photonic interposers utilizing the equalization techniques described herein may be fast enough to support clock frequencies in excess of 10 GHz, 15 GHz, or even 25 GHz, which represents a substantial improvement over conventional processors.

[0146] FIG. 3-3A is a block diagram illustrating a portion of a photonic interposer configured to perform equalization. On the transmit side, FFE unit 360 performs pre-emphasis and / or de-emphasis. On the receive side, unit 362 performs DFE and / or CTLE. In some embodiments, the system can determine whether to perform equalization (FFE, DFE, or CTLE) depending on whether the communication between Tile 1 and Tile 2 occurs within a common photonic interposer or spans two separate photonic interposers. Alternatively, the system may determine whether to perform equalization depending on whether the communication between Tile 1 and Tile 2 is performed using a bus waveguide or using a fiber.

[0147] In addition to determining whether to apply equalization, in some embodiments, the characteristics of the equalizer may be adaptively changed depending on the nature of the channel. For example, the system may determine the S 11 and / or S. 21 A parameter can be determined and based on that information, the number of taps of the DFE / CTLE unit 362 can be adjusted. FIG. 3-3B is a block diagram illustrating an example of an adaptive equalizer. An ADC 370 located at the end of the channel digitizes the output of the channel by generating state samples y[n], y[n-1], y[n-2], etc. The DFE / CTLE unit 362 generates an output w[n] by computing a linear combination of the state samples y[n], y[n-1], y[n-2], etc. The linear combination can be expressed as:

[0148]

number

[0149] where c iis a coefficient (real or complex) that represents the channel response. Here, M determines how many previous state samples y[n] are used to perform equalization. M is the number of taps of the equalizer. If M is a finite number, the digital equalizer 400 implements a finite impulse response (FIR) filter. However, in other embodiments, the digital equalizer 400 may implement an infinite impulse response (IIR) filter. Each state sample y[ni] corresponds to a digitization of the amplitude of a past (if i>0) or current (if i=0) analog signal, and w[n] corresponds to a calculated steady-state output value for a current set of digital inputs. In the example of FIG. 3-3B, the DFE / CTLE unit 362 includes a number of registers 372, a number of digital multipliers 374, and a digital adder 376. Each register 372 records a state sample (y) at a different time. For example, one register may record y[n-1], another register may record y[n-2], and so on. The registers allow the equalizer to store historical state samples. Digital multipliers 374 multiply the state samples by corresponding coefficients. One of the digital multipliers may, for example, multiply the state sample y[n-1] by a coefficient c1. Digital adder 376 adds the results of the digital multiplications together. As a result, the output w[n] represents a linear combination of the historical state samples.

[0150] The number M, which represents the number of taps, can be dynamically adjusted during run-time. This means that instead of transmitting a known signal and analyzing the characteristics of the channel, the system adjusts the number of taps depending on the payload itself (the data transmitted from TX to RX that carries the actual information). Adjusting the number of taps involves changing the number of registers and digital multipliers involved in the equalization. Furthermore, the coefficient c i The value of may be determined based on the characteristics of the channel.

[0151] VIII. Channel Tuning Some embodiments relate to optical interconnects that rely on resonant devices such as ring or disk modulators and ring or disk filters. The high index contrast of silicon to silicon oxide provides very high mode confinement, allowing the use of resonant devices with very small footprints while keeping optical losses low. In one example, a ring modulator can be used with a 10 5 They can have diameters less than 5 μm with quality factors (Q) greater than 1000 nm. Because resonant devices can be made small without sacrificing optical loss, these devices are preferred over other types of modulators and filters when device density is paramount (as is the case for the photonic interposers described herein).

[0152] However, the use of resonant devices poses challenges. A prerequisite for resonance-based operation is that the relationship between the output wavelength of the laser and the resonator's resonant wavelength remains constant over time. Unfortunately, both the laser's output wavelength and the resonator's resonant wavelength are subject to thermal drift, a phenomenon in which the wavelength can change due to unpredictable changes in local temperature. Furthermore, the resonator's resonant wavelength can also be subject to nonlinear effects such as two-photon absorption in silicon, especially when the resonator confines light and increases the luminous flux density. When the laser's output wavelength and the resonator's resonant wavelength drift relative to each other, the operation of the photonic interposer can be significantly degraded.

[0153] The inventors have developed a technique for locking a resonant device despite the presence of thermal drift. Figures 3-4A-3-4C show a sequence for locking the wavelength of a transmitter. As shown in Figures 3-4A, the transmitter in this example can transmit data in either one direction or the opposite direction along a bus waveguide 410. The transmitter includes a resonant modulator 400, a modulator driver 402, a heater 404, an MZI 406, monitoring detectors 411, 412, 413 and 414, and a resonant additional filter 408 coupled to the bus waveguide 410. The modulator driver 402 drives the modulator 400 with data. As a result, the light provided by the laser is modulated with the data. Depending on which output of the MZI is selected, the modulated light is coupled to the bus waveguide in either one direction (e.g., from right to left) or the opposite direction (e.g., from left to right). The additional filter ensures that the data added to the bus waveguide is at the desired wavelength, thus enabling bus waveguide 410 to support WDM. In this example, the additional filter is a second order filter designed to flatten the frequency response over the passband of interest.

[0154] The first tuning step is shown in FIG. 3-4A. Here, a signal in the form of a linear ramp controls the heater 404, thereby causing a shift in the resonant frequency of the modulator 400. As the modulator is ramped, a controller (not shown in FIG. 3-4A) monitors the output (e.g., the sum of the outputs) of the detectors 414 and 412. By determining the point at which the detector output is maximized, it can be determined which value of the ramp will lock the modulator to the laser. Sweeping the modulator in this manner ensures that the resonant wavelength of the modulator is tuned (or slightly detuned) to the wavelength of the laser. In the following steps, the heater is driven at a value that maximizes the output of the detectors 414 and 412.

[0155] The steps shown in Figures 3-4B include tuning the MZI 406. This step ensures that 100% (or nearly 100%) of the modulator's output optical power is transmitted either in one direction or the other of the bus waveguide. This is to avoid transmitting data in the wrong direction of the bus waveguide. In this step, a signal in the form of a linear ramp controls the MZI 406, thereby causing a shift in the percentage of power appearing from the output of the MZI. As the MZI is ramped, the controller monitors the output of detector 414 or detector 412, depending on the desired direction of transmission. For example, if the desired direction is from right to left, the controller monitors the output of detector 414. By determining the point at which the output of detector 414 is minimized, it can be inferred that all the power is transmitted in the desired direction. In contrast, if the desired direction is from left to right, the controller monitors the output of detector 412.

[0156] The step shown in FIG. 3-4C includes tuning the additional filter 408. As for the modulator 400, a heater (not shown in FIG. 3-4C) can be placed near the additional filter to cause a wavelength change when a signal is applied. Tuning the filter ensures that the desired wavelength is transmitted on the bus waveguide. In this step, a signal in the form of a linear ramp controls a heater near the additional filter 408, thereby causing a shift in the resonant frequency of the filter. As the filter is ramped, the controller monitors the output of detector 413 or detector 411, depending on the desired direction of transmission. For example, if the desired direction is from right to left, the controller monitors the output of detector 411. By determining the point at which the output of detector 411 is minimal, it can be inferred that all power is transmitted in the bus waveguide at the desired wavelength. In contrast, if the desired direction is from left to right, the controller monitors the output of detector 413. If, after the steps of FIG. 3-4C, it is determined that the MZI 406 is no longer properly tuned, the controller may repeat the steps of FIG. 3-4C and / or the steps of FIG. 3-4B.

[0157] 3-5A and 3-5B show a sequence for tuning a receiver. As shown in FIG. 3-5A, the receiver in this example can receive data transmitted from either one direction or the other along the bus waveguide 410. The resonant drop filter 420 is the counterpart of the resonant add filter 408 in that it selects which wavelengths are transmitted to the receiver, thus allowing the bus waveguide to support WDM. In this example, the drop filter is a second order filter designed to flatten the frequency response over the passband of interest. Supervisory detectors 424 and 425 monitor the status of the drop filter. The MZI 426 determines the direction from which data is received, whether from the left or the right. Supervisory detectors 434 and 435 monitor the status of the MZI. The receiver 440 includes a photodetector and electronic receiver circuitry (e.g., a transimpedance amplifier and an ADC).

[0158] The step shown in FIG. 3-5A includes tuning the drop filter 420. As for the modulator 400, a heater (not shown in FIG. 3-5A) can be placed near the drop filter to cause a wavelength change when a signal is applied. Tuning the filter ensures that the desired wavelength is received from the bus waveguide. In this step, a signal in the form of a linear ramp controls a heater near the drop filter 420, thereby causing a shift in the resonant frequency of the filter. As the filter is ramped, the controller monitors the output of detector 413 or detector 411, depending on the desired direction of transmission. For example, if the desired direction is left to right, the controller monitors the output of detector 425 and / or the output of detector 424. By determining the point where the output of detector 425 is maximized and / or the output of detector 424 is minimized, it can be inferred that all the power received from the bus waveguide is at the desired wavelength. In contrast, if the desired direction is right to left, the controller monitors that the output of detector 424 is maximized and / or the output of detector 425 is minimized.

[0159] The steps shown in Figures 3-5B include tuning the MZI 426. This step ensures that 100% (or nearly 100%) of the optical power provided to the receiver is received from one direction or the other. This is to avoid receiving data from the wrong direction of the bus waveguide. In this step, a signal in the form of a linear ramp controls the MZI 426, thereby causing a shift in the percentage of power accepted from the input of the MZI that is ultimately forwarded to the RX 440. As the MZI is ramped, the controller monitors the output of detector 434 or detector 435. By determining the point where the output of detector 435 is maximized and / or the output of detector 434 is minimized, it can be inferred that all power is received from the desired direction.

[0160] Taking advantage of the resonant properties of wavelength division multiplexing transmission described above, the inventors have further developed a technique involving dithering that allows a receiver to uniquely identify a particular transmitter. Dithering involves modulating a resonant component at a relatively slow frequency (e.g., 1 kHz to 1000 kHz) to uniquely identify the signal propagated through that component. The slow frequency should be supported by a modulation element such as a thermo-optical heater in some embodiments. In essence, the component marks the signal with a signature in the form of a specific dithering frequency. Each component can be dithered at a slightly different frequency. Component identification becomes especially important in architectures having several components in series. In some embodiments, a detector can identify which transmitter transmitted a particular data depending on the dithering frequency. In one example, the dithered signal is used to lock a drop filter of a receiver to a particular modulator. It is important to note that the dithering signal can be applied to a non-resonant element (e.g., an MZI as in component 406) associated with a particular wavelength transmission.

[0161] FIG. 3-6A illustrates a technique for locking a receiver to a specific transmitter using dithering, according to some embodiments. In this example, multiple transmitters and multiple receivers are coupled in series along the length of a bus waveguide 410. The transmitters are coupled to the bus waveguide via an add filter 408, and the receivers are coupled to the bus waveguide via a drop filter 420. The architecture of the transmitters is similar to that shown in FIG. 3-4A, and the architecture of the receivers is similar to that shown in FIG. 3-5A. In this case, the signal that is maximized / minimized by the detectors (424 and 425) in the RX device is dithered. An analog circuit can be built to capture the signal at a specific dither frequency, for example using a homodyne or heterodyne circuit, and a local oscillator can be generated locally by the RX device. Other TX-RX transmit pairs in series use different dither frequencies. Care must be taken that different dither frequencies are not rational numbers of each other, e.g., f1 / f2 is not a rational number a / b (a and b are integers). Thus, by using a signal at a specific dither frequency associated with a particular TX-RX transmission pair, components within and between the TX-RX transmission pair can be locked to the correct pair (and not be confused by signals from other TX-RX pairs). In some embodiments, a receiver drop filter can be locked to a particular transmitter's modulator by dithering the modulator at a certain frequency and then having a (main and tap) detector in the RX device to maximize / minimize the signal at that particular frequency. Furthermore, in some embodiments, multiple components within the same TX-RX transmission link can be dithered using the same dither frequency such that all detectors in the TX-RX transmission link only need to generate a single dither frequency to lock. In other embodiments, different components within the same TX-RX transmission link can be dithered at different frequencies such that detectors in the TX-RX link can distinguish between error signals of different components along the link.The dither frequency may be slower than the frequency of the crystal oscillator (in the MHz regime) typically used to build a PLL.

[0162] In some embodiments, a FIR digital bandpass filter (not shown in FIGS. 3-6A) may be coupled to the detector that is programmed to identify a particular dithering frequency. In these embodiments, locking between the transmitter and receiver may involve programming the FIR digital bandpass filter to only accept signals that are dithered at a particular frequency.

[0163] FIG. 3-6B shows an optical channel that supports communication between multiple transmitter-receiver pairs. Transmitter TX1 and receiver RX1 form a pair, and data transmitted by TX1 is directed to RX1. Transmitter TX2 and receiver RX2 form another pair, and data transmitted by TX2 is directed to RX2. Transmitter TX3 and receiver RX3 form another pair, and data transmitted by TX3 is directed to RX3. Transmitter TX4 and receiver RX4 form another pair, and data transmitted by TX4 is directed to RX4. Each TX-RX pair uses a unique dither frequency (f1 for TX1-RX1, f2 for TX2-RX2, f3 for TX3-RX3, and f4 for TX4-RX4). Each pair can use a unique wavelength λ1, λ2, λ3, and λ4 in the optical channel.

[0164] IX. Redundancy The present inventors have recognized and understood that the finite yield associated with a microscale manufacturing process can adversely affect the scalability of the photonic interposer. The yield associated with a manufacturing process represents the percentage of defect-free components divided by the total number of components manufactured. The yield of a manufacturing process is generally less than 100% and is due to a variety of factors including, for example, device performance, system complexity, and manufacturer capabilities.

[0165] Some types of defects can impair the function of photonic circuits. When light encounters one of these defects, partial or complete loss of optical power can occur. Other types of defects can impair the function of electronic circuits and / or wiring that are part of the tile (e.g., modulator drivers or transimpedance amplifiers). When an electrical signal encounters one of these defects, attenuation or complete loss of the signal can occur.

[0166] A. Fiber attachment redundancy The impact of limited yields on fiber attaches can be particularly severe. Fiber attaches allow photonic integrated circuits (of which photonic interposers are an example) to communicate with the outside world using optical fibers. Fiber attach can be done using passive or active processes. In passive processes, the fiber is attached to the chip without feedback on whether and how much light is coupled. In active processes, the chip provides feedback that can be used to improve optical alignment before the fiber is fixed to the chip. Active processes offer higher coupling efficiency than passive processes, but are more expensive. Unfortunately, both types of processes have finite yields. Furthermore, chip manufacturers cannot determine whether a fiber attach is good or bad until the package is fully (or nearly fully) assembled. This is because fiber attach is among the last process steps in packaging a photonic integrated circuit.

[0167] When installing multiple (16 or 32) fibers at once, whether through edge coupling, vertical coupling, or the use of V-grooves, the yield in an industrial environment is still around 95%. The type of fiber installation described herein refers to installing either a single fiber (e.g., single mode fiber, polarization maintaining fiber, or multicore fiber) or an array of fibers (e.g., V-groove fiber arrays or ribbons of fibers). Applications requiring many fibers, such as optically interconnected servers, require higher fiber installation yields. If a particular system requires N sites to be good, the system yield rate is (p) N where p is the probability that the attachment site is good. Even when p is about 90%, the yield rate drops rapidly to about 20% for N=16. To increase the system yield rate, a more fault-tolerant attachment strategy is needed. The current focus is on increasing the yield of the fiber attachment itself by introducing new packaging processes such as better index-matching epoxies / glues or better active alignment during the attachment process. However, these methods are often insufficient.

[0168] The inventors have developed a method to increase the yield of fiber attachments with fiber redundancy. This can be achieved by having more fiber attachments than are needed to operate the photonic integrated circuit. A controller identifies, among all fiber attachments, which fiber attachments or which subset of fiber attachments provides better performance. These fibers are utilized during the operation of the chip, while other fibers remain unused. This process can be performed in real time, thus enabling the controller to continue to monitor the quality of the fiber attachments during operation.

[0169] FIG. 4-1A illustrates a photonic integrated circuit (PIC) 900 having a photonic circuit 902 and multiple fiber attachments. The PIC 900 may represent, for example, any one of the photonic interposers described herein. In these embodiments, the photonic circuit 902 may include tiles, transceivers, and photonic interconnects as described above. However, fiber redundancy may be used in connection with any type of PIC. At each attachment site, a fiber 908 couples to a waveguide 907 of the PIC via an optical chip-fiber coupler 906 (e.g., edge coupler, v-groove, grating). As shown, instead of having only a single fiber attachment, an additional k-1 fiber attachments (for a total of k fiber attachments) are provided. An optical switch 904 on the PIC selects which of the k fiber attachments should be used for operation of the PIC. A controller 903 monitors the performance of each fiber attachment and controls the operation of the optical switch 904.

[0170] Different schemes may be used to monitor the performance of the fiber attachments. In one example, a photodetector 909 coupled to the waveguides 907 using a tap coupler monitors the optical power present in the waveguides (only one photodetector 909 is shown in FIG. 4-1A). The photodetector 909 provides information to the controller 909 indicative of the optical power present in the various waveguides 907. Based on this information, the controller 909 may determine which subset of the k fiber attachments (which may be one or more fiber attachments) provides the best performance. The controller 909 may then control the optical switch 904 to select the waveguide(s) corresponding to the best performing fiber attachment subset. In another example, the photonic integrated circuit 902 may include a system for monitoring the quality of the channels corresponding to the various fiber attachments. For example, the photonic integrated circuit 902 may monitor the bit error rate (BER), eye diagram quality factor, power and / or signal-to-noise ratio (SNR) associated with each channel. In this example, the controller 909 can control the optical switch 904 to select one waveguide after another in a sequential manner, thus allowing the photonic circuit 902 to monitor the quality of each channel individually. The photonic circuit 902 provides information to the controller 909 indicative of the quality of the various channels. Based on this information, the controller 909 can determine which subset of the k fiber attachments (which may be one or more fiber attachments) provides the best performance. The controller 909 can then control the optical switch 904 to select the waveguide(s) corresponding to the best performing fiber attachment subset. In some embodiments where fiber attachment performance can be measured before final system assembly, it is not necessary to connect the worse performing fiber attachment subset to other optical devices or connectors. In other embodiments, where fiber attachment performance cannot be measured before final assembly, all fiber attachments can be performed, and then subset selection can be performed.

[0171] The redundancy scheme described in connection with FIG. 4-1A may be used regardless of whether the PIC 900 is used as a transmitter or a receiver. FIG. 4-1B is a block diagram showing a pair of PICs 900 connected to each other using k fibers, some of which are provided simply for redundancy. One PIC operates as a transmitter, in which the photonic circuit 902 operates as a TX photonic circuit. The other PIC operates as a receiver, in which the photonic circuit 902 operates as a RX photonic circuit. Each controller 909 monitors the quality of the fiber attachments and controls each optical switch 904 to select the waveguide(s) corresponding to the best performing subset of fiber attachments.

[0172] If the probability that an individual fiber attachment will operate properly is p, then the overall probability that at least one of the k fiber attachments will operate properly using fiber redundancy is 1-(1-p) k Since this quantity is always larger than p, the yield increases. For example, consider a system that requires 16 functional fiber attachment sites to be good. By using redundant fiber attachments at each attachment site, the system yield can be increased to nearly 100%, even when the probability of successful fiber attachment is low. The results are shown in Figure 4-1C. Figure 4-1C shows the overall system yield (in %) for a system with 16 fiber attachment sites as a function of the number of attachments on each site. Having a single attachment (one on the x-axis) means that no redundant fiber attachments are employed. Having N attachments (N on the x-axis) means that N-1 redundant fiber attachments are used. As can be seen from this figure, regardless of the initial probability that a fiber attachment will work properly, as the number of attachments increases, the overall system yield approaches 100%.

[0173] B. Tile Redundancy The inventors further realize that not all tiles of a photonic interposer are good. Some of the tiles may have, for example, defective transmitters, receivers, interconnects, and / or switches. This may adversely affect the performance of the network in that electronic chips mounted on the defective tiles may become unusable. In addition, not all electronic chips mounted on the photonic interposer are good. To avoid these problems, the inventors have developed a scheme involving tile redundancy.

[0174] FIG. 4-2 shows a photonic interposer having multiple tiles, one of which is provided for redundancy. Electronic chips 911, 912, 913, 914, 915, and 916 are mounted on the photonic interposer 20 corresponding to the respective tiles. Optionally, a further electronic chip 917 may be placed on the redundant tile. The chip 917 may also be provided for redundancy in case one of the other electronic chips does not operate properly. For example, the chip 917 may be a copy of one of the other chips. In this example, the tile corresponding to the chip 914 is defective. In response, the photonic interposer may be reconfigured to functionally swap the defective tile with the redundant tile. The programmable interconnects described above may be utilized to redirect optical signals directed to the defective tile to the redundant tile. Optionally, the redundant chip 917 may be used in place of the chip 914.

[0175] In some embodiments, wafer-level testing can be used to determine whether tiles of a photonic wafer are good or bad. This approach allows manufacturers to determine the quality of a wafer without having to test separate portions of the wafer individually. A drawback of this approach is that once a particular portion of a wafer is designed for a particular application, the tiles of that wafer portion will eventually be packaged as part of a photonic interposer, regardless of whether they are good or bad.

[0176] In some embodiments, the performance of the tiles can be monitored in real-time during operation. This can be accomplished using a power monitoring grid, an example of which is shown in FIG. 4-3. The power monitoring grid includes multiple photodetectors (e.g., photodetector 909 in FIG. 4-1A) located at various locations on the photonic interposer. The photodetectors can be coupled to various photonic components via tap couplers. The power monitoring grid can be leveraged to determine, for example, that a particular tile is not operating as expected. Using that information, the system can decide to reconfigure itself to functionally swap that tile with one of the redundant tiles. This operation can be performed during operation of the photonic interposer.

[0177] X. Fabrication of Lattice-Based Packages The photonic interposers described herein require light to operate, whether the light is provided by a laser or other type of light source. Unfortunately, monolithically integrating a laser with a photonic interposer is difficult due to the low light emission rate of silicon. Instead, it is often more practical to use an external laser (located on the same package or on the same substrate as the interposer) and direct the light emitted by the external laser into the chip. This can be done via edge coupling or surface coupling. Edge coupling involves coupling an optical mode from a fiber to a waveguide through one of the sides of the chip. In contrast, surface coupling involves coupling an optical mode from a fiber to a waveguide through the top surface of the chip. Lattice couplers are often used to direct light coming from outside the plane of the top surface into a waveguide that extends parallel to the top surface of the chip. Lattice couplers are planar structures formed on or just below the top surface of the photonic chip.

[0178] The inventors recognize and understand that the presence of particles or other types of debris on the top surface of the chip can adversely affect fiber grating coupling efficiency because the particles can cause scattering. Unfortunately, particle-free operation is difficult to achieve due to various manufacturing steps that occur after the formation of the grating but before the fiber is attached to the top surface of the chip.

[0179] The inventors have developed a manufacturing process that limits the accumulation of particles or other debris on the top surface of the photonic chip, thereby resulting in improved fiber grating efficiency. In some embodiments, this can be achieved by forming a temporary protective layer that is positioned so that the grating is protected during process steps that are more likely to generate undesired particles. Once these process steps are completed, the temporary protective layer can be removed, exposing the grating to air for subsequent fiber attachment. The temporary protective layer may be formed before or after the electronic chip (e.g., ASIC) is bonded to the photonic interposer. Examples of protective layers include photoimageable dielectrics (e.g., polyimide or resist) and glass (e.g., with a UV-peelable adhesive). Other materials are possible. Additionally, in some embodiments, particle-free processing can be achieved by using a custom molding process designed to encapsulate the electronic chip without ever coming into contact with the grating coupler.

[0180] FIG. 5-1 is a schematic diagram showing a fiber coupled to a grating coupler formed on a photonic interposer, according to some embodiments. A fiber 1120 is positioned above a grating coupler 1110 formed on the top surface of a photonic interposer 1130. The fiber 1120 is at a non-zero angle to the surface of the photonic interposer 1130. In this example, the fiber is also at a non-zero angle to an axis normal to the top surface of the interposer, although in some embodiments the fiber may be parallel to the normal axis. Light emerging from a fiber core 1122 of the fiber 1120 is coupled to the grating coupler 1110. The grating then transmits the light to a waveguide 1121.

[0181] FIG. 5-2A is a top view of a wafer 1130 that has been patterned to form photonic circuits that, when diced from the wafer, can be used as photonic interposers. Electronic chips 1210 are mounted on the photonic interposer(s). The electronic chips are encapsulated by an encapsulation material 1220, which may be formed using a mold compound. Regions 1230 include grating couplers formed on the top surface of the wafer. To allow for subsequent fiber attachment, these regions are not covered by the encapsulation material.

[0182] FIG. 5-2B is a cross-sectional side view of a portion of the wafer of FIG. 5-2A, viewed from the y-axis in the xz plane. This view shows multiple electronic chips mounted on the top surface of a photonic interposer. The electronic chips are encapsulated by encapsulation material 1220. Region 1230 is exposed to air.

[0183] FIG. 5-3A shows the photonic interposer of FIG. 5-2B after it has been diced. Region 1230 remains exposed to air so that fiber can be attached in a subsequent step. Connections 1310 formed on the bottom surface of the photonic interposer allow connection of the photonic interposer to a circuit board 1340. Examples of connections 1310 include ball grid arrays (BGA), copper pillars, C4 bumps, pins, etc.

[0184] FIG. 5-3B is a cross-sectional side view of the package after the fiber 1120 has been attached to the top surface of the interposer 1130. Once the fiber is attached, the fiber core is optically coupled to the grating coupler. In this view, the interposer 1130 is mounted on a printed circuit board (PCB) 1340 via a connection 1310 that passes through the underfill 1330. A cap 1320, such as a heat spreader, is placed on top of the electronic chip. The fiber 1120 is coupled to a grating coupler on one side of the package via a steering optical component 1350 that steers the light propagating in the fiber in a direction that is at a non-zero angle relative to the top surface of the photonic interposer, thereby allowing the fiber modes to couple to the grating.

[0185] Figures 5-4, 5-5, and 5-6 are flow charts illustrating various processes for fabricating packaged photonic interposers. These fabrication processes are designed to prevent (or at least limit) the accumulation of particles or debris associated with the fiber gratings, thereby enabling low-loss, high-efficiency fiber grating coupling. As described in more detail below, the processes of Figures 5-4 and 5-5 include a temporary protective layer. The process of Figure 5-6 includes a custom molding process.

[0186] Referring first to FIG. 5-4, the manufacturing process begins with step 4A in a packaging facility, which includes obtaining a photonic interposer 1130 (e.g., the photonic interposer of FIG. 1-3B or any of the photonic interposers described herein) patterned with one or more lattice couplers, and covering the area 1230 (where the lattice is patterned) with a protective material 1438, thereby covering the lattice couplers. The photonic interposer may be received at the packaging facility from a semiconductor foundry, where the wafer is patterned with photonic and electronic circuits, including the lattice couplers. Examples of materials that may be used for the protective material 1438 include photo-imageable film (PIF) (e.g., polyimide or photoresist). In step 4B, an electronic chip 1210 (e.g., ASIC, processor, memory, etc.) is placed on the photonic interposer. In step 4C, the electronic chip 1210 is encapsulated with an encapsulation material 1220 by a process such as mass reflow and wafer level mold underfill (WL MUF). It is noted that the protective film applied in step 4A does not allow the coating of the mold compound on the lattice coupler in step 4C, and also keeps the lattice coupler clean from any contaminants and particles released during the subsequent backgrinding and CMP process step 4D. The encapsulation provides protection for the chip and allows the formation of the subsequent TSV exposure process step. In step 4D, the encapsulation material is removed from the top of the electronic chip via planarization (e.g., CMP) or backgrinding to allow the attachment of the carrier mount 1638, which is performed in step 4E (after the flip step). In step 4F, after the TSV exposure process, the connections 1310 (e.g., BGA) are attached to the bottom side of the photonic interposer. It is noted that the attachment of the connections 1310 to the interposer may generate particles or other debris. However, this attachment step is performed while the grating coupler is covered by the protective material 1438.As a result, particles or debris generated during the deposition step do not affect the cleanliness of the top surface on which the lattice couplers are patterned. In step 4G, the carrier mount 1638 is removed from the top of the electronic chip. In step 4H, a UV peelable adhesive tape 1330 (e.g., dicing tape) is applied. In step 4I, the protective material 1438 is removed from the top surface of the photonic interposer, leaving the lattice couplers exposed to air. Optionally, a cleaning step can be performed using a plasma process to ensure surface cleanliness for fiber attachment and optical coupling. In step 4J, the photonic interposer is separated into multiple systems, each comprising one or more electronic chips and one or more lattice couplers, for example by stealth dicing or mechanical sawing. In step 4K, the photonic interposer is attached to a circuit board 1340 by a process such as mass reflow, capillary underfill (CUF), and Urea-formaldehyde (UF) resin curing. Furthermore, a cap 1320 is attached to the electronic chip, which can act as a heat spreader. Furthermore, an open / short (O / S) test is performed to ensure good electrical connection between the photonic interposer and the circuit board. Finally, a fiber 1120 is attached to the top surface of the interposer. As a result, the fiber is optically coupled to the grating coupler.

[0187] FIG. 5-5 is a flow chart illustrating an alternative method for manufacturing a photonic package, according to some embodiments. The method of FIG. 5-5 is similar in some respects to the method of FIG. 5-4. The main difference is that a protective material 1538 is formed after attaching the chip to the photonic interposer and after the encapsulation step. Step 5A includes obtaining a photonic interposer 1130 patterned with one or more lattice couplers and placing the chip 1210 on the interposer. In step 5B, the electronic chip 1210 is encapsulated with an encapsulation material 1220 via a process such as mass reflow and wafer level mold underfill (WL MUF). As mentioned above, the encapsulation provides protection for the chip and allows for the formation of the subsequent TSV exposure process step. In step 5C, a protective material 1538 (e.g., a glass lid with a UV peelable adhesive) is placed on the area of ​​the interposer where the lattice couplers are to be formed. The attachment of the protective glass keeps the lattice couplers clean from any contaminants and particulates that are released during the subsequent backgrinding and CMP process step 5D. In step 5D, the top surface is planarized or back-ground. In step 5E, after the TSV exposure process, the interposer is flipped and the connections 1310 (e.g., BGA) are attached to the bottom surface of the photonic interposer. As mentioned above, the attachment of the connections 1310 to the interposer may generate particles or other debris. However, this attachment step is performed when the lattice coupler is covered by the protective material 1538, thereby preserving the cleanliness of the top surface on which the lattice coupler is patterned. In step 5F, the protective material 1538 is removed, thus exposing the lattice coupler to air. Optionally, a plasma clean is performed on the top surface of the photonic interposer. Subsequent steps are similar to those shown in FIG. 5-4, including fiber attachment.

[0188] Figure 5-6 is a flow chart showing another alternative method for manufacturing a photonic package according to some embodiments. The method of Figure 5-6 differs from the methods of Figures 5-4 and 5-5 in that no protective material is used to cover the lattice coupler. Instead, a custom-designed molding process is performed to encapsulate the electronic chip, while avoiding covering and contaminating the lattice coupler with debris caused by the encapsulation step. The subsequent steps are similar to those described in Figure 5-4.

[0189] In step 6A, the chip 1210 is mounted on the interposer 1130. In step 6B, the encapsulation material 1120 is formed using a custom molding process in a way that avoids covering the area 1230. As a result, contamination generated by the molding step that would have affected the cleanliness of the lattice coupler is prevented (or at least limited). Thus, this process avoids leaving impurities on the top of the lattice coupler. In step 6C, the top surface of the package is planarized or background. In step 6D, the package is mounted on a carrier mount 1638. In step 6E, the device is flipped and the connection 1310 is attached to the bottom surface of the interposer after the TSV exposure process. In step 6F, the carrier mount 1638 is removed. In step 6G, the interposer is diced. In step 6H, a fiber is attached to the top surface of the interposer to couple to the lattice coupler.

[0190] XI.Power distribution FIG. 5-7 is a cross-sectional side view of a photonic package mounted on a circuit board including a power supply system, according to some embodiments. The package of FIG. 5-7 includes a circuit board 1740, a socket 1730, a substrate 1720, a photonic interposer 1714, an electronic chip 1712, a lid 1732, a cold plate 1734, a voltage regulator module (VRM) 1750, connections 1752, and a power bus 1754. The photonic interposer 1714 and the electronic chip 1712 mounted on the photonic interposer have similar properties to the interposer and chip described in detail above. The lid 1732 covers the electronic chip and is placed in thermal contact with the electronic chip. The lid 1732 and the cold plate 1734 placed on top of the lid transfer heat generated by the electronic chip to the outside of the package. 5-7, photonic interposer 1714 is disposed on a substrate 1720 (e.g., an organic substrate), which is disposed on a socket 1730. Socket 1730 is further disposed on an upper surface of a circuit board 1740.

[0191] The packages of Figures 5-7 rely on power bus 1754, VRM 1750, and connections 1752 to transfer power to the photonic interposer and electronic chips. The VRM receives power from the power bus and provides a regulated power output to the electronic components to avoid unacceptable voltage fluctuations caused by the loads resulting from the electronic chips, as shown in Figures 5-8A. The inventors have realized that by mounting the VRM 1750 and power bus 1754 on the bottom side of the circuit board 1740 (the opposite side of the circuit board from the interposer), the lateral extent of the circuit board 1740 can be reduced, thereby reducing power losses that would otherwise result from a longer lateral path for power delivery, as compared to an implementation in which the VRM and power bus are located on the circuit board near the interposer. As a result, the design is more compact and easier to integrate with other electronic systems. In this configuration, connections 1752 interconnect the VRM and corresponding electronic chip together by traversing multiple layers: interposer 1714, substrate 1720, socket 1730, and circuit board 1740. Connections 1752 include a series of different types of vias, the nature of which depends on the substrate being traversed.

[0192] 5-8B are side cross-sectional views showing how power can be delivered from a VRM to an electronic chip. In some embodiments, a VRM transfers power to one electronic chip. In other embodiments, a VRM transfers power to multiple electronic chips. In FIGS. 5-8B, one VRM is shown transferring power to four electronic chips via connections 1752.

[0193] XII. Additional Comments Having thus described several aspects and embodiments of the technology of the present application, it should be recognized that various changes, modifications, and improvements will readily occur to those skilled in the art. Such changes, modifications, and improvements are intended to be within the spirit and scope of the technology described in this application. Accordingly, it should be understood that the foregoing embodiments are presented by way of example only, and that, within the scope of the appended claims and their equivalents, the embodiments of the present invention may be practiced otherwise than as specifically described. In addition, any combination of two or more features, systems, articles, materials, and / or methods described herein is included within the scope of the present disclosure, provided that such features, systems, articles, materials, and / or methods are not mutually inconsistent.

[0194] Similarly, as described, some aspects may be embodied as one or more methods. The acts performed as part of a method may be ordered in any suitable manner. Thus, even if shown as sequential acts in an exemplary embodiment, embodiments may be constructed in which the acts are performed in a different order than described, which may include performing some acts simultaneously.

[0195] It should be understood that all definitions defined and used herein are subject to dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms. As used in the specification and claims herein, the indefinite articles "a" and "an" should be understood to mean "at least one," unless expressly indicated otherwise.

[0196] As used in the specification and claims herein, the term "and / or" should be understood to mean "either or both" of the conjoint elements, i.e., elements that may be present conjunctively or disjunctively.

[0197] As used herein in the specification and claims, the phrase "at least one" in connection with a list of one or more elements should be understood to mean at least one element selected from any one or more of the listed elements, and does not necessarily include at least one of every element specifically listed in the list of elements, nor does it exclude any combination of elements in the list of elements. This definition also allows for the optional presence of elements other than those specifically identified in the list of elements to which the phrase "at least one" refers, whether or not related to the specifically identified elements.

[0198] The terms "approximately" and "about" may be used to mean, in some embodiments, within ±20% of a target value, in some embodiments, within ±10% of a target value, in some embodiments, within ±5% of a target value, and even in some embodiments, within ±2% of a target value. The terms "approximately" and "about" may include the target value.

Claims

1. 1. A photonic interposer, comprising: a plurality of photonic tiles instantiated from a template photonic tile; Each of the plurality of photonic tiles comprises: a transceiver including a transmitter and a receiver; an electrical connection coupled to the transceiver, the electrical connection configured to enable electrical communication between the transceiver and the electronic chip when the electronic chip is attached to the photonic interposer in correspondence with the photonic tile; an optical distribution network comprising a first set of bus waveguides optically coupled to the transceivers, a second set of bus waveguides, and a plurality of programmable interconnects, each programmable interconnect configured to selectively place one bus waveguide of the first set of bus waveguides in optical communication with one bus waveguide of the second set of bus waveguides, each programmable interconnect comprising a waveguide intersection and an active coupler; A photonic interposer comprising:

2. 2. The photonic interposer of claim 1, The transceiver includes: a plurality of modulators coupled to a first bus waveguide of the first set of bus waveguides and tuned at different wavelengths relative to one another; a plurality of drop filters coupled to a second bus waveguide of the first set of bus waveguides, the drop filters being tuned at different wavelengths relative to one another; A photonic interposer comprising:

3. The photonic interposer of claim 2 , wherein the plurality of modulators are resonant modulators and the plurality of drop filters are resonant drop filters.

4. 10. The photonic interposer of claim 1, wherein the transmitter is configured to transmit data in either a first direction or a second direction along a first bus waveguide of the first set of bus waveguides.

5. The photonic interposer of claim 4 , wherein each of the plurality of photonic tiles further comprises a 2×2 coupler coupling the transceiver to the first bus waveguide of the first set of bus waveguides.

6. 6. The photonic interposer of claim 5, wherein the 2×2 coupler comprises first, second, third and fourth terminals; the first terminal is coupled to an output of the transmitter; the second terminal is coupled to an input of a receiver; The photonic interposer, wherein the third and fourth terminals are coupled to the first bus waveguide of the first set of bus waveguides.

7. 5. The photonic interposer of claim 4, wherein each of the plurality of photonic tiles further comprises an interferometer having an input and first and second outputs, and a resonant filter; the transmitter is coupled to the input of the interferometer; the first and second outputs of the interferometer are coupled to the resonant filter; The photonic interposer, wherein the resonant filter is coupled to the first bus waveguide of the first set of bus waveguides.

8. 5. The photonic interposer of claim 4, wherein each of the plurality of photonic tiles further comprises an interferometer having an output and first and second inputs, and a resonant filter; the resonant filter is coupled to the first bus waveguide of the first set of bus waveguides; the first and second inputs of the interferometer are coupled to the resonant filter; The receiver is coupled to an output of the interferometer.

9. 2. The photonic interposer of claim 1, wherein the waveguide intersection comprises a first waveguide patterned in a first waveguide layer, a second waveguide patterned in a second waveguide layer, and a third waveguide patterned in a third waveguide layer; the second waveguide layer is between the first waveguide layer and the third waveguide layer; The first waveguide is evanescently coupled to the second waveguide, and the second waveguide is evanescently coupled to the third waveguide.

10. 10. The photonic interposer of claim 9, wherein the first waveguide layer is formed of silicon and both the second and third waveguide layers are formed of silicon nitride.

11. 2. The photonic interposer of claim 1 , wherein the active coupler comprises a first terminal coupled to a first additional active coupler, a second terminal coupled to the first additional active coupler, and a third terminal coupled to the waveguide intersection.

12. 2. The photonic interposer of claim 1, wherein the active coupler comprises first and second Mach-Zehnder interferometers, the first terminal corresponding to a first output of the first MZI, the second terminal corresponding to a second output of the first MZI, and the third terminal corresponding to an output of the second MZI.

13. The photonic interposer of claim 1 , wherein the bus waveguides of the second set of bus waveguides traverse multiple photonic tiles.

14. 1. A photonic interposer, comprising: a plurality of photonic tiles instantiated from a template photonic tile, the plurality of photonic tiles including a first photonic tile, a second photonic tile, a third photonic tile, and a fourth photonic tile, each of the plurality of photonic tiles comprising: A first transceiver; an electrical connection coupled to the first transceiver, the electrical connection configured to enable electrical communication between the first transceiver and the electronic chip when the electronic chip is attached to the photonic interposer in correspondence with the photonic tile; a plurality of photonic tiles comprising: first and second bus waveguides traversing the first and second photonic tiles, respectively; third and fourth bus waveguides traversing the third and fourth photonic tiles, respectively; First and second fibers; Equipped with the first fiber, the first bus waveguide, and the fourth bus waveguide place the first transceiver of the first photonic tile in optical communication with the first transceiver of the fourth photonic tile; the second fiber, the second bus waveguide, and the third bus waveguide place the first transceiver of the second photonic tile in optical communication with the first transceiver of the third photonic tile;

15. 15. The photonic interposer of claim 14, wherein each of the plurality of photonic tiles further comprises a second transceiver, the second transceiver of the first photonic tile in optical communication with the second transceiver of the second photonic tile.

16. The photonic interposer of claim 15 , wherein the second transceiver of the third photonic tile is in optical communication with the second transceiver of the fourth photonic tile.

17. 15. The photonic interposer of claim 14, further comprising a third fiber, wherein the third fiber, the first bus waveguide, and the fourth bus waveguide further place the first transceiver of the first photonic tile in optical communication with the first transceiver of the fourth photonic tile.

18. 20. The photonic interposer of claim 17, wherein the first fiber, the third fiber, the first bus waveguide, the fourth bus waveguide, the first transceiver of the first photonic tile, and the first transceiver of the fourth photonic tile form a closed loop.

19. 20. The photonic interposer of claim 17, further comprising a fourth fiber, wherein the fourth fiber, the second bus waveguide, and the third bus waveguide further place the first transceiver of the second photonic tile in optical communication with the first transceiver of the third photonic tile.

20. 20. The photonic interposer of claim 19, wherein the second fiber, the fourth fiber, the second bus waveguide, the third bus waveguide, the first transceiver of the second photonic tile, and the first transceiver of the third photonic tile form a closed loop.

21. 1. A computing system comprising: a photonic interposer comprising a plurality of photonic tiles instantiated from a template photonic tile; first and second application specific integrated circuits (ASICs) mounted on the photonic interposer, the first ASIC coupled to a first photonic tile of the plurality of photonic tiles and the second ASIC coupled to a second photonic tile of the plurality of photonic tiles; a data path for communicating the first ASIC with the second ASIC, a first die-to-die (D2D) interface integrated in the first ASIC and comprising a plurality of wires; a first plurality of SerDes coupled to the plurality of wires; a plurality of optical modulators coupled to the plurality of SerDes and formed within the first photonic tile; a plurality of photodetectors coupled to the plurality of optical modulators and formed within the second photonic tile; a second plurality of SerDes coupled to the plurality of photodetectors; and a second D2D interface integrated in the second ASIC; and A data path including A computing system comprising:

22. 22. The computing system of claim 21, wherein the plurality of optical detectors are coupled to the plurality of optical modulators via waveguides formed on the photonic interposer.

23. 22. The computing system of claim 21, wherein the plurality of optical detectors are coupled to the plurality of optical modulators via fibers.

24. 22. The computing system of claim 21, wherein the first and second D2D interfaces comprise an Advanced Interface Bus interface (AIB).

25. 22. The computing system of claim 21, wherein the first and second D2D interfaces comprise Universal Chiplet Interconnect Express (UCIe) interfaces.

26. 22. The computing system of claim 21, wherein the data path spans a length of more than 2.5 cm from the first D2D interface to the second D2D interface.

27. 1. A method for manufacturing a photonic package, comprising: Obtaining a photonic interposer having a lattice coupler formed on a first surface of the photonic interposer; Attaching an electronic chip to a first surface of the photonic interposer; encapsulating the electronic chip with an encapsulation material; disposing a protective material on the first surface of the photonic interposer so as to cover the grating coupler; subsequent to disposing the protective material, forming electronic connections on a second surface of the photonic interposer opposite the first surface; following forming the electrical connections, removing protective material from the first surface of the photonic interposer to expose the grating coupler to air; The method includes:

28. 30. The method of claim 27, further comprising cleaning the first surface of the photonic interposer subsequent to removing the protective material from the first surface of the photonic interposer.

29. 28. The method of claim 27, further comprising, subsequent to removing the protective material, attaching a fiber to the first surface of the photonic interposer, the fiber when attached being optically coupled to the grating coupler.

30. 30. The method of claim 29, wherein the fiber is at a non-zero angle with respect to the first surface of the photonic interposer when the fiber is optically coupled to the grating coupler.

31. 30. The method of claim 27, wherein attaching the electronic chip to the first surface of the photonic interposer occurs subsequent to disposing the protective material on the first surface of the photonic interposer.

32. The method of claim 31 , wherein the protective material comprises a photoimageable dielectric.

33. 30. The method of claim 27, wherein disposing the protective material on the first surface of the photonic interposer is performed subsequent to attaching the electronic chip to the first surface of the photonic interposer.

34. 34. The method of claim 33, wherein disposing the protective material on the first surface of the photonic interposer is performed subsequent to encapsulating the electronic chip with an encapsulation material.

35. 35. The method of claim 34, wherein the protective material comprises a glass lid having a releasable adhesive.

36. 1. A method for manufacturing a photonic package, comprising: Obtaining a photonic interposer having a lattice coupler formed on a first surface of the photonic interposer; Attaching an electronic chip to a first surface of the photonic interposer; encapsulating the electronic chip with an encapsulation material such that the encapsulation material leaves the grating coupler exposed to air; placing the photonic interposer on a carrier mount over the grating coupler; subsequent to placing the photonic interposer on the carrier mount, forming electrical connections on a second surface of the photonic interposer opposite the first surface; subsequent to forming the electrical connections, removing the carrier mount. The method includes:

37. 37. The method of claim 36, wherein encapsulating the electronic chip is performed subsequent to attaching the electronic chip to the first surface of the photonic interposer.

38. 37. The method of claim 36, further comprising, subsequent to removing the carrier mount, separating the photonic interposer into a plurality of systems, each system comprising the electronic chip and the lattice coupler.

39. 37. The method of claim 36, further comprising, subsequent to removing the protective material, attaching a fiber to the first surface of the photonic interposer, the fiber when attached being optically coupled to the grating coupler.

40. 40. The method of claim 39, wherein the fiber is at a non-zero angle with respect to the first surface of the photonic interposer when the fiber is optically coupled to the grating coupler.

41. 1. A photonic package comprising: A photonic interposer, a first electronic chip disposed on the photonic interposer; a circuit board having a first surface and a second surface opposite the first surface, the photonic interposer being coupled to the first surface of the circuit board; a voltage regulator module (VRM) coupled to the second surface of the circuit board; a connection configured to provide an output voltage of the VRM to the first electronic chip, the connection traversing the circuit board and the photonic interposer; A photonic package comprising:

42. 42. The photonic package of claim 41 further comprising a substrate and a socket, said photonic interposer disposed on said substrate and said substrate disposed on said socket.

43. 43. The photonic package of claim 42, wherein said connection further traverses said substrate and said socket.

44. 42. The photonic package of claim 41, further comprising a power bus configured to provide an input voltage to the voltage regulator module.

45. 45. The photonic package of claim 44, wherein the voltage regulator module receives the input voltage from the power bus and regulates an output voltage to the first electronic chip.

46. 42. The photonic package of claim 41, wherein the first electronic chip is in contact with the photonic interposer.

47. 42. The photonic package of claim 41 further comprising a lid covering the photonic interposer and a cold plate covering the lid, the lid in thermal contact with the first electronic chip.

48. 1. A photonic device comprising: A photonic circuit. a plurality of optical channels having a plurality of chip-to-fiber couplers and a plurality of waveguides coupled to each of the chip-to-fiber couplers; an optical switch coupled between the plurality of optical channels and the optical circuit; A controller, determining performance indicative information associated with each of the plurality of optical channels; identifying a subset of the plurality of optical channels using the information indicative of a performance associated with each of the plurality of optical channels; a controller configured to control an optical switch to selectively couple a subset of the plurality of optical channels to the photonic circuit; A photonic device comprising:

49. 49. The photonic device of claim 48, wherein the plurality of optical channels further comprises a plurality of photodetectors coupled to respective waveguides, and wherein determining the information indicative of a performance associated with each of the plurality of optical channels comprises determining an output of each of the plurality of photodetectors.

50. 50. The photonic device of claim 49, wherein the plurality of photodetectors are coupled to respective waveguides via tap couplers.

51. 49. The photonic device of claim 48, wherein determining the information indicative of a performance associated with each of the plurality of optical channels comprises determining a bit error rate associated with each of the plurality of optical channels.

52. 49. The photonic device of claim 48, wherein the photonic circuit comprises a plurality of tiles patterned according to a template tile, each tile comprising: A transmitter; A receiver; a network of programmable optical connections; an electrical connection configured for vertical die-to-die connection with an electronic chip, the electrical connection being coupled to the transmitter, the receiver, and the network of programmable optical connections; A photonic device comprising:

53. 49. The photonic device of claim 48, wherein using the information to identify a subset of the plurality of optical channels comprises identifying a subset of the plurality of optical channels that exhibits best performance among the optical channels.

54. 49. The photonic device of claim 48, wherein the chip-to-fiber coupler comprises an edge coupler or a grating coupler.

55. 49. The photonic device of claim 48, wherein the controller is further configured to control a photonic circuit to transmit data external to the photonic device using a subset of the plurality of optical channels selected by the optical switch.

56. 1. A method for transmitting data using a photonic device comprising an optical switch and a plurality of optical channels having a plurality of chip-to-fiber couplers and a plurality of waveguides coupled to each chip-to-fiber coupler, the method comprising: determining information indicative of performance associated with each of the plurality of optical channels; identifying a subset of the plurality of optical channels using the information indicative of a performance associated with each of the plurality of optical channels; controlling an optical switch to select a subset of the plurality of optical channels; transmitting the data external to the photonic device using the subset of the plurality of optical channels selected by the optical switch; The method includes:

57. 57. The method of claim 56, wherein the plurality of optical channels further comprises a plurality of optical detectors coupled to respective waveguides, and wherein determining the information indicative of a performance associated with each of the plurality of optical channels comprises determining an output of each of the plurality of optical detectors.

58. 57. The method of claim 56, wherein determining the information indicative of a performance associated with each of the plurality of optical channels comprises determining a bit error rate (BER) associated with each of the plurality of optical channels.

59. 57. The method of claim 56, wherein using the information to identify the subset of the plurality of optical channels comprises identifying the subset of the plurality of optical channels that exhibits best performance among the optical channels.

60. 1. A photonic interposer, comprising: A plurality of photonic tiles including a redundant tile, each photonic tile comprising: A transmitter; A receiver; a network of programmable optical connections; an electrical connection configured for vertical die-to-die connection with an electronic chip, the electrical connection coupled to the transmitter, the receiver, and the network of programmable optical connections; Monitoring photodetector and a plurality of photonic tiles including A controller, using an output of each of the monitor photodetectors to determine information indicative of a performance of each of the plurality of photonic tiles; using the information indicative of a performance of each of the plurality of photonic tiles to identify defective tiles from among the plurality of tiles; a controller configured to functionally swap the defective tile with a redundant tile; A photonic interposer comprising:

61. 61. The photonic interposer of claim 60, wherein functionally swapping the defective tile with the redundant tile comprises redirecting data intended for the defective tile to the redundant tile.

62. 62. The photonic interposer of claim 61 , wherein redirecting the data comprises programming the network of programmable photonic connections.

63. 1. A photonic interposer, comprising: A bus waveguide; a plurality of photonic transmitters coupled to the bus waveguide; a plurality of photonic receivers coupled to the bus waveguide; A controller, dithering a photonic component of a first photonic transmitter at a first frequency; a controller configured to lock a first photonic transmitter of the plurality of photonic transmitters to a first photonic receiver of the plurality of photonic receivers by dithering the photonic component of a first photonic receiver at the first frequency; A photonic interposer comprising:

64. 64. The photonic interposer of claim 63, wherein each of the plurality of photonic transmitters comprises a resonant modulator and each of the plurality of photonic receivers comprises a resonant drop filter coupled to the bus waveguide; dithering the photonic component of the first photonic transmitter comprises dithering the resonant modulator of the first photonic transmitter; A photonic interposer, wherein dithering the photonic component of the first photonic receiver includes dithering the resonant drop filter of the first photonic receiver.

65. 64. The photonic interposer of claim 63, wherein each of the plurality of photonic transmitters comprises a resonant add filter coupled to the bus waveguide, and each of the plurality of photonic receivers comprises a resonant drop filter coupled to the bus waveguide; dithering the photonic component of the first photonic transmitter comprises dithering a resonant additive filter of the first photonic transmitter; A photonic interposer, wherein dithering the photonic component of the first photonic receiver includes dithering the resonant drop filter of the first photonic receiver.

66. 64. The photonic interposer of claim 63, wherein the first frequency is between 1 KHz and 1000 KHz.

67. 64. The photonic interposer of claim 63, wherein the photonic interposer further comprises a plurality of photonic tiles instantiated from a template photonic tile, each of the plurality of photonic tiles comprising a photonic transmitter of the plurality of photonic transmitters and a photonic receiver of the plurality of photonic receivers, and wherein the bus waveguide traverses two or more photonic tiles.

68. 1. A photonic transmitter comprising: a resonant modulator configured to modulate light received from the laser using input data; a Mach-Zehnder Interferometer (MZI) coupled to the resonant modulator, the MZI having a first output and a second output; a resonant additional filter coupled to the bus waveguide; a controller configured to selectively couple either the first output or the second output of the MZI to the resonant additive filter to transmit modulated light along the bus waveguide in either a first direction or a second direction; A photonic transmitter comprising:

69. 69. The photonic transmitter of claim 68 further comprising a heater thermally coupled to the resonant modulator and a first monitoring detector coupled to the first output of the MZI; The controller: applying a first ramp signal to the heater; maximizing the output generated by the first monitoring detector; and the photonic transmitter further configured to lock the resonant modulator to a laser by

70. 70. The photonic transmitter of claim 69, wherein selectively coupling either the first output or the second output of the MZI to the resonant additional filter comprises: applying a second ramp signal to the MZI; Minimizing the output generated by the first monitoring detector; A photonic transmitter comprising:

71. 71. The photonic transmitter of claim 70, wherein selectively coupling either the first output or the second output of the MZI to the resonant additional filter comprises: applying a third ramp signal to the resonant additive filter; minimizing an output generated by a second monitor detector coupled to the second output of the MZI; and The photonic transmitter further comprises:

72. 69. The photonic transmitter of claim 68, wherein the resonant additional filter comprises a second order filter.

73. 1. A photonic interposer, comprising: first and second photonic tiles instantiating a template photonic tile, each of the first and second photonic tiles comprising a transceiver and a receiver; an optical channel coupling the transmitter of the first photonic tile to the receiver of the second photonic tile; an encoder coupled to the transmitter of the first photonic tile and configured to perform an Xb / Yb encoding scheme; a decoder coupled to the receiver of the second photonic tile and configured to perform an Xb / Yb decoding scheme; a clock recovery circuit configured to use an output of the decoder to time the receiver of the second photonic tile; A photonic interposer comprising:

74. 74. The photonic interposer of claim 73, further comprising a first local oscillator coupled to the encoder and a second local oscillator coupled to the decoder.

75. 74. The photonic interposer of claim 73, further comprising an equalizer coupled to a receiver of the second photonic tile, the equalizer configured to perform a linear combination of outputs of the receivers of the second photonic tile.

76. 76. The photonic interposer of claim 75, wherein the equalizer is further configured to determine characteristics of the optical channel during runtime and to adjust a number of taps associated with the equalizer based on the characteristics of the optical channel determined by the equalizer.

77. 76. The photonic interposer of claim 75, wherein the equalizer is further configured to determine characteristics of the optical channel during runtime and to adjust coefficients associated with the equalizer based on the characteristics of the optical channel determined by the equalizer.

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