Operating method for arithmetic processing device

Abstract

To provide a computer system with a small circuit area and lower power consumption.SOLUTION: A computer system includes a computer node having a processor and a NAND-type memory device with a three-dimensional structure. The NAND-type memory device with a three-dimensional structure has a first string and a second string, which belong to different blocks, respectively. The first string has a first memory cell, and the second string has a second memory cell. A controller writes first data to the first memory cell by receiving the first data and a signal including an instruction to write the first data. Subsequently, the controller reads the first data from the first memory cell and writes the first data to the second memory cell. This enables the computer node to be configured without providing a main memory such as DRAM.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to a computer system and a method for operating an information processing device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operation method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, examples of the technical field of one embodiment of the present invention disclosed in this specification more specifically include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, a sensor, a processor, an electronic device, an information processing device, a system, an operation method thereof, a manufacturing method thereof, or an inspection method thereof. [Background technology]

[0003] There is a lot of emphasis on reducing the power consumption of information processing devices. Therefore, reducing the power consumption of integrated circuits (ICs) such as CPUs and memory devices is a major issue in circuit design. The power consumption of ICs can be roughly divided into two categories: the power consumed when in operation (dynamic power) and the power consumed when not in operation (standby) (static power). Increasing the operating frequency to improve performance increases dynamic power. Most static power is consumed by leakage currents of transistors. Leakage currents include subthreshold leakage currents, gate tunnel leakage currents, gate-induced drain leakage (GIDL) currents, and junction tunnel leakage currents. These leakage currents increase with the miniaturization of transistors, so the increase in power consumption is a major barrier to improving the performance and high integration of ICs.

[0004] In order to reduce the power consumption of semiconductor devices such as integrated circuits and memory devices, or information processing devices including such semiconductor devices, circuits that do not need to be operated are stopped by power gating, clock gating, etc. Power gating has the effect of eliminating standby power by stopping the power supply. To enable power gating in a CPU, it is necessary to back up the contents of registers, caches, etc. in a non-volatile memory.

[0005] A memory circuit capable of retaining data even in a power-off state has been proposed, utilizing the extremely small off-state current of a transistor that includes an oxide semiconductor (also referred to simply as OS) in a channel formation region (hereinafter may be referred to as an "oxide semiconductor transistor" or an "OS transistor"). For example, Non-Patent Document 1 discloses an OS-SRAM (static random access memory) equipped with a backup circuit using an OS transistor. Non-Patent Document 1 discloses that a microprocessor equipped with an OS-SRAM is capable of power gating with a short break-even time (BET) without affecting normal operation. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] T. Ishizu et al., Int. Memory Workshop, 2014, pp.106-103. [Non-Patent Document 2] S. Bartling et al., ISSCC Dig.Tech.Papers, pp.432-434, 2013. [Non-Patent Document 3] N. Sakimura et al., ISSCC Dig.Tech.Papers, pp.184-185, 2014. [Non-Patent Document 4] VK.Singhal et al., ISSCC Dig.Tech.Papers, pp.148-149, 2015. Summary of the Invention [Problem to be solved by the invention]

[0007] As an example, consider a NAND type storage device having a storage unit and a cache memory. In a NAND type storage device, the input speed of data to be written (amount of information input per unit time) is slower than the write speed of data to the storage unit. Therefore, by using the cache memory included in the storage device to temporarily hold the data to be written input to the storage device, data can be written to the storage unit without lowering the input speed of data to be written to the storage device. In addition, the read speed of data from the storage unit is slower than the output speed of read data from the storage device (amount of information output per unit time). Therefore, by using the cache memory included in the storage device to temporarily hold the data read from the storage device, data can be read from the storage unit without lowering the read speed of data read from the storage device.

[0008] As another example, the cache memory has a function of temporarily storing data when rearranging data stored in the storage unit, saving data that is not related to erasure, and the like.

[0009] For example, a dynamic random access memory (DRAM) is used as the cache memory. Therefore, the cache memory and the NAND type storage device are created in different processes and are created as separate chips. For this reason, it is necessary to provide a bus wiring between the cache memory and the NAND type storage device, which may increase the circuit area of ​​the storage device. Also, depending on the length of the bus wiring, the power consumption of the signals flowing through the bus wiring may increase.

[0010] An object of one embodiment of the present invention is to provide a computer system with a reduced circuit area or a computer system with low power consumption.

[0011] Another object of one embodiment of the present invention is to provide a novel computer system or a novel method for operating a novel information processing device.

[0012] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and other problems. One embodiment of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0013] (1) One aspect of the present invention is a computer system including a processor and a memory. The processor includes a storage unit, and the storage unit includes a transistor having a metal oxide in a channel formation region. The processor and the memory are positioned so as to overlap with each other.

[0014] (2) Alternatively, according to one embodiment of the present invention, in the above-mentioned (1), a DRAM may not be connected between the processor and the memory.

[0015] (3) Alternatively, one aspect of the present invention is a computer system having a computer node including a processor. The processor has a memory unit, and the memory unit has a first transistor, a second transistor, and a capacitor. Each of the first transistor and the second transistor has a metal oxide in a channel formation region. A first terminal of the first transistor is electrically connected to a gate of the second transistor, and the gate of the second transistor is electrically connected to a first terminal of the capacitor.

[0016] (4) Alternatively, according to one aspect of the present invention, in the above configuration (3), the processor may have an SRAM and may not have a flip-flop.

[0017] (5) Another embodiment of the present invention is a computer system including a computer node, the computer node including a processor and a three-dimensional NAND memory device. The three-dimensional NAND memory device includes a transistor including a channel formation region containing a metal oxide. The computer node may not include a DRAM.

[0018] (6) Alternatively, one embodiment of the present invention is a method for operating an information processing device having a calculation processing device, a memory device, and multiple wirings, where the memory device has multiple strings, one of the multiple strings being electrically connected to the calculation processing device via one of the multiple wirings, the method converting first data input by serial transmission into multiple second data, distributing the multiple second data for each of the multiple wirings, and simultaneously supplying the multiple second data to the multiple strings in response to a trigger signal.

[0019] (7) Alternatively, in one embodiment of the present invention, in the above-described structure (6), the string may include a plurality of memory cells, and the memory cells may include an oxide semiconductor.

[0020] (8) Alternatively, in one embodiment of the present invention, in the above configuration (6) or (7), the storage device may be a NAND storage device.

[0021] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having the same circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of a semiconductor device. Also, a memory device, a display device, a light-emitting device, a lighting device, an electronic device, an information processing device, etc. are themselves semiconductor devices and may have a semiconductor device.

[0022] In addition, when it is stated in this specification that X and Y are connected, the following cases are also disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is also disclosed in a figure or text other than the connection relationship shown in the figure or text. X and Y are objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0023] As an example of a case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state) and controls whether or not a current flows.

[0024] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0025] In addition, when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without having another element or circuit between them).

[0026] Also, for example, it can be expressed as "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limited to these expressions. Here, X and Y are objects (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0027] In addition, even when components that are independent on a circuit diagram are shown as being electrically connected to each other, one component may have the functions of multiple components. For example, when a part of a wiring also functions as an electrode, one conductive film has both the functions of a wiring and an electrode. Therefore, the term "electrical connection" in this specification also includes such a case where one conductive film has the functions of multiple components.

[0028] In addition, in this specification, the term "resistance element" may be, for example, a circuit element or wiring having a resistance value higher than 0Ω. Therefore, in this specification, the term "resistance element" includes wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be rephrased as "resistance", "load", "region having a resistance value", and the like, and conversely, the terms "resistance", "load", and "region having a resistance value" can be rephrased as "resistance element". The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0029] In addition, in this specification, the term "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of a wiring having a capacitance value, a parasitic capacitance, a gate capacitance of a transistor, and the like. Therefore, in this specification, the term "capacitive element" refers not only to a circuit element including a pair of electrodes and a dielectric contained between the electrodes, but also to a parasitic capacitance appearing between wirings, a gate capacitance appearing between one of the source or drain of a transistor and the gate, and the like. In addition, the terms "capacitive element", "parasitic capacitance", "gate capacitance", and the like can be rephrased as "capacitance", and conversely, the term "capacitance" can be rephrased as "capacitive element", "parasitic capacitance", "gate capacitance", and the like. In addition, the term "pair of electrodes" in "capacitance" can be rephrased as "pair of conductors", "pair of conductive regions", "pair of regions", and the like. The value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. In addition, it may be, for example, 1 pF or more and 10 μF or less.

[0030] In addition, in this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the conductivity type (n-channel type, p-channel type) of the transistor and the level of the potential applied to the three terminals of the transistor. For this reason, in this specification, the terms source and drain can be used interchangeably. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or the first electrode or the first terminal) and "the other of the source or drain" (or the second electrode or the second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the above-mentioned three terminals. In this case, in this specification, one of the gate or the backgate of the transistor may be referred to as the first gate, and the other of the gate or the backgate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, the respective gates may be referred to as a first gate, a second gate, a third gate, and so on.

[0031] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0032] In addition, in this specification and the like, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to a potential difference from a reference potential, and if the reference potential is the ground potential (earth potential), for example, "voltage" can be interchanged as "potential." Note that ground potential does not necessarily mean 0V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also change.

[0033] In addition, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0034] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, vacuum, etc.). In addition, the "direction of current" in wiring, etc. is the direction in which positively charged carriers move, and is described as a positive current amount. In other words, the direction in which negatively charged carriers move is the opposite direction to the direction of current, and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive and negative (or current direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A" etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0035] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Also, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0036] In addition, in this specification, the terms indicating the arrangement, such as "above" and "below", may be used for convenience in order to explain the positional relationship between the components with reference to the drawings. Furthermore, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0037] In addition, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0038] In addition, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, depending on the situation, it is possible to replace the terms "film" and "layer" with other terms without using them. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulating body".

[0039] In addition, the terms "electrode", "wiring", "terminal" and the like in this specification do not limit the functions of these components. For example, "electrode" may be used as a part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where a plurality of "electrodes", "wirings", and the like are integrally formed. Furthermore, for example, "terminal" may be used as a part of "wiring", "electrode", and the like, and vice versa. Furthermore, the term "terminal" includes cases where a plurality of "electrodes", "wirings", "terminals", and the like are integrally formed. Therefore, for example, an "electrode" can be a part of a "wiring" or a "terminal", and for example, a "terminal" can be a part of a "wiring" or an "electrode". Furthermore, the terms "electrode", "wiring", "terminal" and the like may be replaced with terms such as "region" depending on the circumstances.

[0040] In addition, in this specification and the like, terms such as "wiring", "signal line", and "power line" can be interchanged with each other depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line". For example, the term "wiring" may be changed to the term "power line". The opposite is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring". The term "power line" may be changed to the term "signal line". The opposite is also true, and terms such as "signal line" may be changed to the term "power line". The term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances. The opposite is also true, and terms such as "signal" may be changed to the term "potential".

[0041] In this specification and the like, the impurity of a semiconductor refers to, for example, other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. When an impurity is included, for example, the defect level density in the semiconductor may increase, the carrier mobility may decrease, and the crystallinity may decrease. When the semiconductor is an oxide semiconductor, the impurity that changes the characteristics of the semiconductor may be, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, a transition metal other than the main component, and in particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. Specifically, when the semiconductor is silicon, the impurity that changes the characteristics of the semiconductor may be, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 15 element (however, oxygen and hydrogen are not included), and the like.

[0042] In this specification and the like, a switch refers to a device that has a function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has a function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0043] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. Also, the "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically cut off. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0044] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical system) technology. The switch has an electrode that can be moved mechanically, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0045] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes the case of -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case of 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. Effect of the Invention

[0046] According to one embodiment of the present invention, a computer system with a reduced circuit area or a computer system with low power consumption can be provided.

[0047] According to one embodiment of the present invention, a novel computer system can be provided. Another object of one embodiment of the present invention is to provide a novel method for operating a novel information processing device.

[0048] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief description of the drawings]

[0049] [Figure 1] FIG. 1 is a block diagram illustrating an example of the configuration of an information processing device. [Diagram 2] FIG. 2 is a flowchart showing an example of a method of operating the information processing device. [Diagram 3] 3A to 3C are schematic diagrams showing an example of an operation method of the information processing device. [Figure 4] 4A to 4C are circuit diagrams showing configuration examples of a storage unit included in an information processing device. [Diagram 5] 5A to 5C are circuit diagrams showing configuration examples of a storage unit included in an information processing device. [Figure 6] FIG. 6 is a circuit diagram showing a configuration example of a storage unit included in the information processing device. [Figure 7] FIG. 7 is a circuit diagram showing a configuration example of a storage unit included in the information processing device. [Figure 8] 8A and 8B are timing charts showing an example of a method of operating a storage unit included in an information processing device. [Figure 9]FIG. 9 is a circuit diagram showing a configuration example of a storage unit included in the information processing device. [Figure 10] FIG. 10 is a circuit diagram showing a configuration example of a storage unit included in the information processing device. [Figure 11] FIG. 11 is a schematic cross-sectional view illustrating an example of the configuration of an information processing device. [Figure 12] FIG. 12 is a schematic cross-sectional view illustrating a configuration example of a transistor. [Figure 13] FIG. 13 is a schematic cross-sectional view illustrating a configuration example of an information processing device. [Figure 14] FIG. 14A is a perspective view for explaining an example of the configuration of a computer, and FIG. 14B is a perspective view for explaining a monolithic IC. [Figure 15] FIG. 15 is a schematic diagram showing a configuration example of a monolithic IC. [Figure 16] 16A and 16B are diagrams illustrating the memory hierarchy of a computer, a monolithic IC, respectively. [Figure 17] 17A and 17B are block diagrams illustrating the configuration of an information processing device and its operation method. [Figure 18] FIG. 18A is a diagram for explaining the classification of IGZO crystal structures, FIG. 18B is a diagram for explaining the XRD spectrum of crystalline IGZO, and FIG. 18C is a diagram for explaining the ultrafine electron beam diffraction pattern of crystalline IGZO. [Figure 19] FIG. 19A is a perspective view showing an example of a semiconductor wafer, FIG. 19B is a perspective view showing an example of a chip, and FIGS. 19C and 19D are perspective views showing an example of an electronic component. [Figure 20] 20A to 20J are perspective views or schematic diagrams for explaining an example of a product. [Figure 21] 21A to 21C are perspective views for explaining an example of a computer. [Figure 22] FIG. 22 is a diagram illustrating an example of a computer. [Figure 23] FIG. 23 is a diagram illustrating an example of a computer system. [Figure 24]24A and 24B are diagrams illustrating an example of a computer system. [Diagram 25] 25A to 25D are circuit diagrams showing an example of a memory cell, and FIG. 25E is a block diagram showing an example of a memory cell array and peripheral circuits. [Figure 26] FIG. 26 is a diagram illustrating an example of a computer system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0050] In this specification and the like, metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors, and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be called an oxide semiconductor. In other words, when a channel formation region of a transistor having at least one of an amplifying action, a rectifying action, and a switching action can be formed of a metal oxide, the metal oxide may be called a metal oxide semiconductor.

[0051] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0052] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0053] In addition, the content (or a part of the content) described in one embodiment may be applied, combined, or replaced with at least one of another content (or a part of the content) described in that embodiment and the content (or a part of the content) described in one or more other embodiments.

[0054] In addition, the contents described in the embodiments refer to the contents described in each embodiment (or example) using various figures, or the contents described using text in the specification.

[0055] Furthermore, a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or a part thereof) described in that embodiment, and / or with at least one figure (or a part thereof) described in one or more other embodiments to form even more figures.

[0056] The embodiments described in this specification will be described with reference to the drawings. However, it is possible to implement the embodiments in many different ways, and it is easily understood by those skilled in the art that the form and details can be changed in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, in perspective views and the like, the description of some components may be omitted in order to ensure the clarity of the drawings.

[0057] In this specification, when the same symbol is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, "[n]”, "[m,n]”, etc. may be added to the symbol.

[0058] In addition, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0059] (Embodiment 1) In this embodiment, a data processing device according to one embodiment of the present invention having a function as a storage device will be described.

[0060] <Configuration example> 1 is a block diagram showing an example of the configuration of an information processing device 50. The information processing device 50 includes, for example, a storage unit 1196, a controller 1197, and a bus interface 1198.

[0061] For example, the information processing device 50 has a function of obtaining a signal including command information from the outside and writing data to the storage unit 1196 in response to the command. Note that the storage unit 1196 has a memory cell, for example, and the data is written to the memory cell. Also, the storage unit 1196 may have a transistor for selecting the memory cell.

[0062] Specifically, for example, a signal ISG including command information input to the information processing device 50 is input to the controller 1197 via the bus interface 1198.

[0063] The controller 1197 has a function of decoding the signal ISG, for example. The controller 1197 also has a function of performing various controls based on an instruction included in the decoded signal. Specifically, the controller 1197 generates an address of a memory cell included in the storage unit 1196, and reads or writes data from or to the storage unit 1196 depending on the state of the information processing device. When writing data to the storage unit 1196, the data to be written can be data DT input to the information processing device via the bus interface 1198, or the like. The data DT is transmitted to the controller 1197 via the bus interface 1198.

[0064] Therefore, as an example, the controller 1197 may have a circuit for decoding the signal ISG, a circuit for generating an address of a memory cell included in the memory unit 1196, and a circuit for outputting a signal for switching between the on and off states of a transistor included in the memory unit 1196.

[0065] The controller 1197 may also have a function of generating a signal for controlling the timing of operations. For example, the controller 1197 may be configured to include an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and to supply the internal clock signal to the various circuits described above.

[0066] The controller 1197 may also have a function of performing an error check on memory cells of a string included in the storage unit 1196. By having this function, the controller 1197 can perform an error check on memory cells of a string included in the storage unit 1196, for example, before the controller 1197 writes data to the storage unit 1196. At this time, if a defective cell is found in the string to which data is to be written, the controller 1197 can change the data write destination from the defective cell to another cell and perform a data write operation. The controller 1197 may also have a function of performing an error check on memory cells of a string included in the storage unit 1196 at regular intervals, and correcting the data when a defective cell is found in the string.

[0067] Moreover, the information processing device 50 has a function of, for example, acquiring a signal including command information from the outside and reading data from the storage unit 1196 in response to the command. Moreover, the information processing device 50 has a function of outputting the read data as a signal OSG to the outside of the information processing device 50 by the controller 1197.

[0068] In the data processing device of one embodiment of the present invention, for example, a memory circuit having a NAND string can be applied as the memory unit 1196. In particular, it is preferable to apply a NAND memory circuit having a three-dimensional structure using OS transistors as the NAND memory circuit. Note that memory cell configurations include a configuration in which NAND strings using OS transistors are horizontally stacked one layer at a time, and a configuration in which NAND strings using OS transistors are vertically formed at once by etching or the like. In this specification and the like, a structure in which NAND strings using OS transistors are vertically formed may be referred to as a 3D OS NAND (registered trademark) memory circuit. In the 3D OS NAND memory circuit, a large number of memory cells can be formed at the same time, so that the packaging density can be increased with fewer manufacturing steps. That is, the cost per bit can be reduced, and a memory circuit with high packaging density can be realized at low cost. For this reason, the memory unit 1196 has a plurality of NAND strings. Note that FIG. 1 illustrates an example in which the memory unit 1196 has strings ST1 to ST3. Moreover, in the storage unit 1196 of FIG. 1, strings other than string ST1 to string ST3 are omitted.

[0069] As an example, string ST1 has memory cells L[1] to L[n] (n is an integer of 1 or more), string ST2 has memory cells M[1] to M[n], and string ST3 has memory cells N[1] to N[n]. Note that in FIG. 1, memory cells L[1], L[2], and L[n] are selectively illustrated in string ST1, memory cells M[1], M[2], and M[n] are selectively illustrated in string ST2, and memory cells N[1], N[2], and N[n] are selectively illustrated in string ST3.

[0070] In the string ST1, the memory cells L[1] to L[n] are electrically connected in series between the wirings SL1 and BL1. Similarly, in the string ST2, the memory cells M[1] to M[n] are electrically connected in series between the wirings SL2 and BL2, and in the string ST3, the memory cells N[1] to N[n] are electrically connected in series between the wirings SL3 and BL3.

[0071] The wirings SL1 to SL3 function as wirings that apply a predetermined potential to the strings ST1 to ST3, and the wirings BL1 to BL3 function as wirings for writing data to memory cells included in the strings ST1 to ST3 and / or wirings for reading data from the memory cells.

[0072] Note that strings not shown in the figure have the same connection configuration as strings ST1 to ST3.

[0073] <Example of operation method> Here, an example of an operation method for treating some memory cells included in the string of the storage unit 1196 as a cache memory in the information processing device 50 of FIG. 1 will be described.

[0074] Fig. 2 is a flowchart showing an example of an operation method of the information processing device 50 in Fig. 1. The operation method includes steps STP1 to STP8. In addition to the flowchart, the movement of data in the string ST1 and the string ST2 is shown in Figs. 3A to 3C.

[0075] As an example of this operation method, assume that data is stored in each of the memory cells L[1] to L[n] of the string ST1, and that data in the memory cell L[6] is rewritten. Also assume that no data is stored in at least the strings ST2 and ST3.

[0076] When the information processing device 50 in FIG. 1 starts its operation, step STP1 is first performed.

[0077] Step STP1 includes a step of writing data for rewriting the memory cell L[6] to, for example, the memory cell N[1] of the string ST3. Specifically, for example, the information processing device 50 in Fig. 1 acquires the data for rewriting DT and a signal ISG including a command for rewriting the data, and a write signal is transmitted from the controller 1197 to the storage unit 1196, and the data for writing DT is stored in the memory cell N[1].

[0078] After step STP1 is completed, step STP2 is performed. Step STP2 includes a step of reading data stored in each of the memory cells L[1] to L[n] other than the memory cell to be rewritten in the string ST1. Here, for example, data stored in each of the memory cells L[1] to L[5] is read (see FIG. 3A).

[0079] Step STP3 includes a step of sequentially writing the data of the memory cells L[1] to L[5] read in step STP2 to the memory cells M[1] to M[5] of the string ST2 (see FIG. 3A). That is, by the operations from step STP2 to step STP3, the data of the memory cells L[1] to L[5] of the string ST1 are copied to the memory cells M[1] to M[5] of the string ST2.

[0080] 2, step STP3 is performed after step STP2, but the operation method of the data processing device according to one embodiment of the present invention is not limited thereto. For example, in step STP2, data stored in each of the memory cells L[1] to L[5] of the string ST1 may be sequentially read, and the read data may be sequentially written to the memory cells M[1] to M[5] of the string ST2. In other words, step STP2 and step STP3 may be combined into the same step.

[0081] After step STP3 is completed, step STP4 is performed, which includes a step of erasing data held in the memory cells L[1] to L[5] of the string ST1.

[0082] When the memory unit 1196 is a NAND type memory circuit, the data erase operation is performed on a string basis. Therefore, when erasing the data stored in the memory cells L[1] to L[5] of the string ST1, all the data in the memory cells L[1] to L[n] is erased. Therefore, in steps STP2 and STP3, it is necessary to write not only the data in the memory cells L[1] to L[5], but also the data in the memory cells L[7] to L[n] to the string ST2.

[0083] For this reason, the memory unit 1196 is preferably an OS NAND type memory circuit having the circuit configurations shown in FIGS. 4A to 4C, 6, and 7, which will be described later. Alternatively, depending on the situation, the circuit configuration of the memory unit 1196 may be any one of the configurations shown in FIGS. 5A to 5C, with a transistor including silicon in the channel formation region (hereinafter referred to as a Si transistor). Although the details will be described later, by using the memory device, data from the memory cell L[1] to an arbitrary memory cell of the string ST1 can be erased. For this reason, in this operation example, in order to rewrite the data of the memory cell L[6], only the data of the memory cells L[1] to L[6] of the string ST1 is erased (see FIG. 3B).

[0084] Step STP5 includes a step of reading rewrite data DT from the memory cell N[1] of the string ST3.

[0085] Step STP6 includes a step of writing the rewrite data DT of the memory cell N[1] read in step STP5 to the memory cell L[6] of the string ST1 (see FIG. 3B).

[0086] Step STP7 includes a step of reading data stored in each of the memory cells M[1] to M[5] of the string ST2. The data corresponds to the data written in step STP3 (see FIG. 3C).

[0087] Step STP8 includes a step of sequentially writing the data of the memory cells M[1] to M[5] read in step STP5 to the memory cells L[1] to L[5] of the string ST1 (see FIG. 3C). That is, by the operations from step STP7 to step STP8, the data of the memory cells M[1] to M[5] of the string ST1 are copied to the memory cells L[1] to L[5] of the string ST2.

[0088] 2, step STP8 is performed after step STP7, but the operation method of the data processing device according to one embodiment of the present invention is not limited thereto. For example, in step STP7, data stored in each of the memory cells M[1] to M[5] of the string ST2 may be sequentially read, and the read data may be sequentially written to the memory cells L[1] to L[5] of the string ST1. In other words, step STP7 and step STP8 may be combined into the same step.

[0089] As described above in steps STP1 to STP8, when writing data to a string in memory unit 1196, when rewriting data held in a string, etc., memory cells in another string in memory unit 1196 can be treated as cache memory.

[0090] In the information processing device 50 shown in FIG. 1, it is preferable to use, for example, a semiconductor substrate (for example, a single crystal substrate or a silicon substrate) as a substrate for forming a circuit. Examples of the substrate include an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates, laminated films, base films, and the like include the following. For example, there are plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, there is, for example, a synthetic resin such as acrylic. Examples of the material include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, or an SOI substrate, a transistor with small variations in characteristics, size, or shape, high current capacity, and small size can be manufactured. When a circuit is configured using such transistors, it is possible to reduce the power consumption of the circuit or to increase the integration of the circuit.

[0091] Alternatively, a flexible substrate may be used as the substrate, and the transistors may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate and the transistors. The peeling layer can be used to separate the information processing device from the substrate after a part or whole of the information processing device is completed thereon, and to transfer the device to another substrate. In this case, the transistors can be transferred to a substrate having poor heat resistance, a flexible substrate, or the like. Note that the above-mentioned peeling layer may be, for example, a laminated structure of inorganic films of a tungsten film and a silicon oxide film, or a structure in which an organic resin film such as polyimide is formed on a substrate.

[0092] That is, a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed on the other substrate. Examples of substrates onto which transistors are transferred include, in addition to the substrates on which the above-mentioned transistors can be formed, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester), or regenerated fibers (acetate, cupra, rayon, regenerated polyester), etc.), leather substrates, or rubber substrates. By using these substrates, it is possible to form transistors with good characteristics, form transistors with low power consumption, manufacture devices that are not easily broken, impart heat resistance, and reduce weight or thickness.

[0093] It is possible to form all of the circuits required to realize a given function on the same substrate (e.g., a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate, etc.). This makes it possible to reduce costs by reducing the number of components, or to improve reliability by reducing the number of connections to the circuit components.

[0094] It is possible that all of the circuits required to realize the predetermined function are not formed on the same substrate. That is, a part of the circuit required to realize the predetermined function is formed on one substrate, and another part of the circuit required to realize the predetermined function is formed on another substrate. For example, a part of the circuit required to realize the predetermined function is formed on a glass substrate, and another part of the circuit required to realize the predetermined function is formed on a single crystal substrate (or an SOI substrate). Then, the single crystal substrate (also called an IC chip) on which another part of the circuit required to realize the predetermined function is formed can be connected to the glass substrate by COG (Chip On Glass), and the IC chip can be arranged on the glass substrate. Alternatively, the IC chip can be connected to the glass substrate by TAB (Tape Automated Bonding), COF (Chip On Film), SMT (Surface Mount Technology), a printed circuit board, or the like. In this way, by forming a part of the circuit on the same substrate as the pixel portion, it is possible to reduce the cost by reducing the number of components, or to improve the reliability by reducing the number of connections with the circuit components. In particular, circuits with high drive voltages or high drive frequencies often consume a lot of power. Therefore, such circuits are formed on a substrate (such as a single crystal substrate) separate from the pixel section to form an IC chip. By using this IC chip, it is possible to prevent an increase in power consumption.

[0095] Note that one embodiment of the present invention is not limited to the configuration of the information processing device 50 illustrated in Fig. 1. In one embodiment of the present invention, the configuration of the information processing device 50 illustrated in Fig. 1 may be changed depending on the situation. For example, the configuration of the string of the storage unit 1196 included in the information processing device 50 illustrated in Fig. 1 may be changed to the configuration of the string described in the second embodiment.

[0096] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0097] (Embodiment 2) In this embodiment, a configuration example of a storage unit (NAND type storage circuit) that can be applied to the storage unit 1196 in the first embodiment will be described.

[0098] <Example of the configuration of the memory unit (memory circuit)> An example of a storage unit will be described with reference to Fig. 4A. Fig. 4A shows a circuit diagram of n memory cells (n is an integer equal to or greater than 1). That is, the circuit shown in Fig. 4A has memory cells MC[1] to MC[n], and wirings WWL[1] to WWL[n], RWL[1] to RWL[n], WBL, and RBL for controlling the memory cells. Note that the wiring WWL functions as a write word line, the wiring RWL functions as a read word line, the wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line.

[0099] Each memory cell MC includes a transistor WTr and a transistor RTr, which are OS transistors, and a capacitance CS. The transistor RTr illustrated in FIG. 4A has a back gate, and the threshold voltage of the transistor RTr can be changed by applying a potential to the back gate. Note that the wiring BGL illustrated in FIG. 4A is electrically connected to the back gates of the transistors RTr included in the memory cells MC[1] to MC[n]. The semiconductor device illustrated in FIG. 4A may have a configuration in which the wiring BGL is not electrically connected to each of the back gates of the transistors RTr included in the memory cells MC[1] to MC[n], but may be electrically connected independently to the back gates and different potentials are applied to each of the back gates.

[0100] Since the transistor WTr is an OS transistor, the channel formation region of the transistor WTr can be, for example, a metal oxide described in embodiment 6. In particular, in the case of a metal oxide including one or more elements selected from indium, an element M (examples of the element M include aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc, the metal oxide functions as a wide-gap semiconductor, and therefore a transistor including the metal oxide in its channel formation region has a characteristic of having a very low off-state current.

[0101] Note that the transistor WTr may be a transistor other than an OS transistor depending on the situation. For example, the transistor WTr may be a Si transistor.

[0102] In addition, the transistor RTr may be a transistor other than an OS transistor depending on the situation. For example, the transistor RTr may be a Si transistor. Since the Si transistor has a large field effect mobility, the drain current of the Si transistor can be increased. Therefore, by applying a Si transistor to the memory unit, the operation of the memory unit can be accelerated.

[0103] The transistor WTr functions as a write transistor, and the transistor RTr functions as a read transistor. The transistor WTr is switched between on and off by a potential applied to the wiring WWL. The potential of one electrode of the capacitance CS is controlled by the wiring RWL. The other electrode of the capacitance CS is electrically connected to the gate of the transistor RTr. The other electrode of the capacitance CS can be called a memory node. The memory node of each memory cell MC is electrically connected to the first terminal of the transistor WTr of that memory cell MC.

[0104] Also, the second terminal of the transistor WTr is electrically connected in series with the first terminal of the transistor WTr of the adjacent memory cell MC. Similarly, the first terminal of the transistor RTr is electrically connected in series with the second terminal of the transistor RTr of the adjacent memory cell. Then, the second terminal of the transistor WTr of the memory cell MC[n] is electrically connected to the wiring WBL, and the second terminal of the transistor RTr of the memory cell MC[n] is electrically connected to the wiring RBL. In this embodiment, the connection point between the second terminal of the transistor RTr of the memory cell MC[n] and the wiring RBL is called a node N1, and the first terminal of the transistor RTr of the memory cell MC[1] is called a node N2. In addition, in order to control the conduction state between the node N1 and the wiring RBL, a selection transistor may be connected in series with the transistor RTr of the memory cell MC[n]. Similarly, in order to control the conduction state between the wiring connected to the node N2 and the node N2, a selection transistor may be connected in series with the transistor RTr of the memory cell MC[1].

[0105] Note that one embodiment of the present invention is not limited to the semiconductor device illustrated in FIG. 4A. One embodiment of the present invention may have a circuit configuration obtained by appropriately modifying the semiconductor device illustrated in FIG. 4A. For example, one embodiment of the present invention may be a semiconductor device in which a backgate is also provided in the transistor WTr as illustrated in FIG. 4B. Note that the semiconductor device illustrated in FIG. 4B has a configuration in which, in addition to the configuration of the semiconductor device illustrated in FIG. 4A, backgates are provided in the transistors WTr included in the memory cells MC[1] to MC[n], and the backgates are each electrically connected to a wiring BGL. For example, one embodiment of the present invention may be a semiconductor device in which the transistors RTr and WTr do not have backgates as illustrated in FIG. 4C.

[0106] Alternatively, one embodiment of the present invention may be a semiconductor device in which the transistor WTr is an OS transistor and the transistor RTr is a Si transistor in the configuration of FIG. 4A as shown in FIG. 5A. Alternatively, one embodiment of the present invention may be a semiconductor device in which the transistor WTr is a Si transistor and the transistor RTr is an OS transistor in the configuration of FIG. 4A as shown in FIG. 5B. Alternatively, one embodiment of the present invention may be a semiconductor device in which the transistor WTr is a Si transistor and the transistor RTr is a Si transistor in the configuration of FIG. 4A as shown in FIG. 5C. In this manner, one embodiment of the present invention may be a semiconductor device in which an OS transistor or a Si transistor is selected as a transistor to be used for the transistor WTr included in the semiconductor device depending on a purpose or application, and similarly, an OS transistor or a Si transistor is selected as a transistor to be used for the transistor WTr included in the semiconductor device.

[0107] Incidentally, when it is desired to further increase the storage capacity of the semiconductor device shown in Figures 4A to 4C and Figures 5A to 5C, the semiconductor devices shown in Figures 4A to 4C and Figures 5A to 5C, etc. may be arranged in a matrix. For example, when the semiconductor devices shown in Figure 4B are arranged in a matrix, the circuit configuration becomes the configuration shown in Figure 6.

[0108] The semiconductor device shown in FIG. 6 is configured by arranging m columns (m is an integer of 1 or more) of the semiconductor device shown in FIG. 4B as one column, and electrically connecting the wirings RWL and WWL to memory cells MC in the same row so as to share them. In other words, the semiconductor device shown in FIG. 6 is a matrix-shaped semiconductor device with n rows and m columns, and has memory cells MC[1,1] to MC[n,m]. Therefore, the semiconductor device shown in FIG. 6 is electrically connected by wirings RWL[1] to RWL[n], wirings WWL[1] to WWL[n], wirings RBL[1] to RBL[m], wirings WBL[1] to WBL[m], and wirings BGL[1] to BGL[m]. Specifically, one electrode of the capacitance CS of the memory cell MC[j,i] (j is an integer between 1 and n, and i is an integer between 1 and m) is electrically connected to the wiring RWL[j], and the gate of the transistor WTr of the memory cell MC[j,i] is electrically connected to the wiring WWL[j]. The wiring WBL[i] is electrically connected to the second terminal of the transistor WTr of the memory cell MC[n,i], and the wiring RBL[i] is electrically connected to the second terminal of the transistor RTr of the memory cell MC[n,i].

[0109] In addition, FIG. 6 illustrates only memory cell MC[1,1], memory cell MC[1,i], memory cell MC[1,m], memory cell MC[j,1], memory cell MC[j,i], memory cell MC[j,m], memory cell MC[n,1], memory cell MC[n,i], memory cell MC[n,m], wiring RWL[1], wiring RWL[j], wiring RWL[n], wiring WWL[1], wiring WWL[j], wiring WWL[n], wiring RBL[1], wiring RBL[i], wiring RBL[m], wiring WBL[1], wiring WBL[i], wiring WBL[m], wiring BGL[1], wiring BGL[i], wiring BGL[m], capacitance CS, transistor WTr, transistor RTr, node N1, and node N2, and omits other wirings, elements, symbols, and signs.

[0110] In this specification and the like, for example, memory cells MC[1,i] to MC[n,i] electrically connected between the node N1 and the node N2 in the i-th column may be referred to as the i-th column string. Also, for example, memory cells MC[j,1] to MC[j,m] electrically connected to the wiring RWL[j] and the wiring WWL[j] in the j-th row may be referred to as the j-th page. Also, for example, memory cells MC[1,1] to MC[n,m] arranged in a matrix of n rows and m columns as shown in FIG. 6 may be collectively referred to as a block.

[0111] FIG. 7 shows m columns (m is an integer equal to or greater than 1) of semiconductor devices each having the semiconductor device shown in FIG. 4C arranged in one column. Note that the semiconductor device shown in FIG. 7 is configured such that no back gate is provided for each transistor of all memory cells MC, and therefore the semiconductor device shown in FIG. 7 does not have a wiring BGL. Note that for the semiconductor device shown in FIG. 7, the description of the semiconductor device shown in FIG. 6 should be referred to.

[0112] <<Example of how it works>> Next, an example of an operation method of the semiconductor device shown in Figures 4A to 4C and Figures 5A to 5C will be described. Note that the low-level potential and high-level potential used in the following description do not mean specific potentials, and the specific potentials may be different depending on the wiring. For example, the low-level potential and high-level potential applied to the wiring WWL may be different from the low-level potential and high-level potential applied to the wiring RWL.

[0113] In this example of the operation method, a potential within a range in which the transistors RTr and WTr operate normally is applied to the wiring BGL shown in Figures 4A and 4B in advance. Therefore, the operations of the semiconductor devices shown in Figures 4A to 4C can be considered to be the same as each other.

[0114] Fig. 8A is a timing chart showing an example of an operation of writing data to a semiconductor device, and Fig. 8B is a timing chart showing an example of an operation of reading data from the semiconductor device. The timing charts in Fig. 8A and Fig. 8B each show changes in the potentials of the wiring WWL[1], the wiring WWL[2], the wiring WWL[n], the wiring RWL[1], the wiring RWL[2], the wiring RWL[n], the node N1, and the node N2. The wiring WBL shows data supplied to the wiring WBL.

[0115] FIG. 8A shows an example in which data D[1] to data D[n] are written to memory cells MC[1] to MC[n]. Each of the data D[1] to D[n] can be binary, multi-valued, analog, or the like. The multi-valued data can be, for example, 4 bits, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, 256 bits, or the like. The data D[1] to D[n] are supplied from the wiring WBL. That is, in the circuit configuration of the semiconductor device shown in FIG. 4A to FIG. 4C, data is written sequentially from the memory cell MC[1] to the memory cell MC[n]. For example, when high-speed writing is required, binary data can be used, and when high-speed writing is not required, multi-valued data can be used.

[0116] Furthermore, for example, if an attempt is made to write data to memory cell MC[1] after writing data to memory cell MC[2], the data stored in memory cell MC[2] will be lost when the data is written to memory cell MC[1] unless the data written in memory cell MC[2] is first read and saved in another location.

[0117] 4A to 4C, when data is written to the memory cell MC[i] (where i is an integer between 2 and n), in order to prevent the data stored in the memory cells MC[1] to MC[i-1] from being rewritten, a low-level potential is supplied to the wirings WWL[1] to WWL[i-1] to turn off the transistors WTr included in the memory cells MC[1] to MC[i-1]. This makes it possible to protect the data stored in the memory cells MC[1] to MC[i-1].

[0118] When data is written to the memory cell MC[i], the data is supplied from the wiring WBL, so that a high-level potential is supplied to the wirings WWL[i] to WWL[n] to turn on the transistors WTr in the memory cells MC[i] to MC[n] sufficiently, thereby allowing the data to be held in the memory node of the memory cell MC[i].

[0119] 4A to 4C, the wiring RBL does not need to be set to a specific potential because it can be controlled independently of other wirings, but can be set to, for example, a low-level potential. That is, the potential of the node N1 can be set to a low-level potential. In addition, the potential of the node N2 can also be set to a low-level potential.

[0120] In light of the above, an operation example shown in the timing chart of Fig. 8A will be described. At time T10, the potentials of the wirings WWL[1] to WWL[n], the wirings RWL[1] to RWL[n], the wiring WBL, the node N1, and the node N2 are all low-level potentials.

[0121] At time T11, application of a high-level potential to the wirings WWL[1] to WWL[n] is started. As a result, between time T11 and time T12, the transistors WTr of the memory cells MC[1] to MC[n] are fully on. Then, data D[1] is supplied to the wiring WBL. Since the transistors WTr of the memory cells MC[1] to MC[n] are fully on, the data D[1] reaches the memory node of the memory cell MC[1] and is written therein.

[0122] At time T12, application of a low-level potential to the wiring WWL[1] is started, and a high-level potential is continuously applied to the wirings WWL[2] to WWL[n]. As a result, between time T12 and time T13, the transistor WTr of the memory cell MC[1] is turned off, and each of the transistors WTr of the memory cells MC[2] to MC[n] is fully turned on. Then, data D[2] is supplied to the wiring WBL. Since each of the transistors WTr of the memory cells MC[2] to MC[n] is fully turned on, the data D[2] reaches the memory node of the memory cell MC[2] and is written therein. In addition, since the transistor WTr of the memory cell MC[1] is turned off, the data D[1] held in the memory cell MC[1] is not lost by the write operation from time T12 to time T13.

[0123] Between time T13 and time T14, data D[3] to data D[n-1] are sequentially written to memory cells MC[3] to MC[n-1], respectively, in the same manner as the write operation of data D[1] to memory cell MC[1] between time T11 and time T12 and the write operation of data D[2] to memory cell MC[2] between time T12 and time T13. Specifically, the transistors WTr included in memory cells MC[1] to MC[j-1] (where j is an integer between 3 and n-1) to which data has already been written are turned off, and the transistors WTr included in memory cells MC[j] to MC[n] to which data has not been written are turned on sufficiently, and data D[j] is supplied from the wiring WBL to be written to the memory node of memory cell MC[j]. When writing of data D[j] to memory cell MC[j] is completed, the transistor WTr in memory cell MC[j] is turned off, and data D[j+1] is supplied from the wiring WBL to be written to the memory node of memory cell MC[j+1]. In particular, the write operation when j is n-1 refers to the operation from time T14 to time T15 described below.

[0124] At time T14, a low-level potential is applied to the wirings WWL[1] to WWL[n-1], and a high-level potential is continuously applied to the wiring WWL[n]. As a result, from time T14 to time T15, the transistors WTr in the memory cells MC[1] to MC[n-1] are turned off, and the transistors WTr in the memory cells MC[n] are fully turned on. Then, data D[n] is supplied to the wiring WBL. Since the transistors WTr in the memory cells MC[n] are fully turned on, the data D[n] reaches the memory node of the memory cell MC[n] and is written therein. In addition, since the transistors WTr in the memory cells MC[1] to MC[n-1] are turned off, the data D[1] to D[n-1] held in the memory cells MC[1] to MC[n-1] are not lost by the write operation from time T14 to time T15.

[0125] By the above-mentioned operation, in any one of the semiconductor devices shown in FIGS. 4A to 4C, data can be written to the memory cells MC of that semiconductor device.

[0126] 8B shows an example of a timing chart for reading data D[1] to D[n] from memory cells MC[1] to MC[n], respectively. Note that at this time, in order to maintain the data stored in each memory cell MC, the transistor WTr is required to be in an off state. Therefore, during the operation of reading data from the memory cells MC[1] to MC[n], the potentials of the wirings WWL[1] to WWL[n] are set to low level potentials.

[0127] 4A to 4C, when reading data from a specific memory cell MC, the transistors RTr of the other memory cells MC are turned on sufficiently, and the transistor RTr of the specific memory cell MC is operated in a saturated region. In other words, the current flowing between the source and drain of the transistor RTr of the specific memory cell MC is determined according to the source-drain voltage and the data stored in the specific memory cell MC.

[0128] For example, consider the case where data stored in a memory cell MC[k] (where k is an integer between 1 and n) is read out. In this case, a high-level potential is supplied to the wirings RWL[1] to RWL[n] excluding the wiring RWL[k] in order to turn on each of the transistors RTr in the memory cells MC[1] to MC[n] excluding the memory cell MC[k] sufficiently.

[0129] On the other hand, in order to turn on the transistor RTr in the memory cell MC[k] according to the stored data, the wiring RWL[k] needs to be at the same potential as the wiring RWL[k] when the data is written to the memory cell MC[k]. Note that the potential of the wiring RWL[k] during the write operation and the read operation is considered to be a low-level potential here.

[0130] For example, a potential of +3 V is applied to node N1, and a potential of 0 V is applied to node N2. Then, node N2 is made floating, and the potential of node N2 is measured after that. When the potentials of wirings RWL[1] to RWL[n] excluding wiring RWL[k] are set to a high level potential, the transistors RTr of memory cells MC[1] to MC[n] excluding memory cell MC[k] are fully turned on. On the other hand, the voltage between the first terminal and the second terminal of the transistor RTr of memory cell MC[k] is determined by the gate potential of the transistor RTr and the potential of node N1, and therefore the potential of node N2 is determined according to the data held in the memory node of memory cell MC[k].

[0131] In this manner, the data stored in the memory cell MC[k] can be read.

[0132] Based on the above, an operation example shown in the timing chart of Fig. 8B will be described. At time T20, the potentials of the wirings WWL[1] to WWL[n], the wirings RWL[1] to RWL[n], the wiring WBL, the node N1, and the node N2 are all low-level potentials. In particular, the node N2 is in a floating state. Data D[1] to D[n] are stored in the memory nodes of the memory cells MC[1] to MC[n], respectively.

[0133] Between time T21 and time T22, application of a low-level potential to the wiring RWL[1] is started, and application of a high-level potential to the wirings RWL[2] to RWL[n] is started. As a result, between time T21 and time T22, the transistors RTr of the memory cells MC[2] to MC[n] are fully turned on. The transistor RTr of the memory cell MC[1] is turned on in accordance with the data D[1] stored in the memory node of the memory cell MC[1]. In addition, a potential V R This causes the potential of node N1 to rise to V R The potential of the node N2 is V R and the data held in the memory node of the memory cell MC[1]. Here, the potential of the node N2 is V D[1] Then, the potential V of the node N2 D[1] By measuring this, the data D[1] stored in the memory node of the memory cell MC[1] can be read.

[0134] Between time T22 and time T23, application of a low-level potential to the wirings RWL[1] to RWL[n] begins. A low-level potential is supplied to the node N2, and then the node N2 is in a floating state. In other words, between time T22 and time T23, the potentials of the wirings RWL[1] to RWL[n] and the node N2 are the same as those between time T20 and time T21. The potential V R In this operation example, the wiring RBL is supplied with a potential V R will continue to be supplied.

[0135] Between time T23 and time T24, a low-level potential is applied to the wiring RWL[2], and application of a high-level potential is started to the wirings RWL[1], RWL[3] to RWL[n]. As a result, between time T23 and time T24, the transistors RTr of the memory cell MC[1], MC[3] to MC[n] are fully turned on. The transistor RTr of the memory cell MC[2] is turned on according to the data D[2] stored in the memory node of the memory cell MC[2]. A potential V R As a result, the potential of the node N2 is equal to the potential V of the node N1. R and the data held in the memory node of the memory cell MC[2]. Here, the potential of the node N2 is V D[2] Then, the potential V of the node N2 D[2] By measuring this, the data D[2] stored in the memory node of the memory cell MC[2] can be read.

[0136] Between time T24 and time T25, data D[3] to data D[n-1] are sequentially read from each of memory cells MC[3] to MC[n-1], similar to the read operation of data D[1] from memory cell MC[1] between time T20 and time T22 and the read operation of data D[2] from memory cell MC[2] between time T22 and time T24. Specifically, when data D[j] is read from memory cell MC[j] (where j is an integer between 3 and n-1), the potential of node N2 is set to a low level potential and node N2 is set to a floating state, and then high level potential is supplied to wirings RWL[1] to RWL[n] excluding wiring RWL[j], so that transistors RTr included in memory cells MC[1] to MC[n] excluding memory cell MC[j] are fully turned on, and the transistor RTr included in memory cell MC[j] is turned on according to data D[j]. Next, the potential of node N1 is V R By setting the potential of the node N2 to the value corresponding to the data D[j], the data D[j] can be read by measuring this potential. After the data D[j] stored in the memory cell MC[j] has been read, application of low-level potentials to the wirings RWL[1] to RWL[n] is started in preparation for the next read operation, the potential of the node N2 is set to a low-level potential, and then the node N2 is set to a floating state. In particular, when j is n-1, this preparation refers to the operation from time T25 to time T26.

[0137] Between time T25 and time T26, application of a low-level potential starts to the wirings RWL[1] to RWL[n]. After application of a low-level potential starts to the node N2 and the potential of the node N2 becomes a low-level potential, the node N2 is in a floating state. In other words, between time T25 and time T26, the potentials of the wirings RWL[1] to RWL[n] and the node N2 are the same as those between time T20 and time T21. Note that the potential V RIn this operation example, at time T21, a potential V R After time T22, the potential V R shall continue to be applied.

[0138] At time T26, a low-level potential is applied to the wiring RWL[n], and a high-level potential is supplied to the wirings RWL[1] to RWL[n-1]. As a result, between time T26 and time T27, the transistors RTr of the memory cells MC[1] to MC[n-1] are fully turned on. The transistor RTr of the memory cell MC[n] is turned on in accordance with the data D[n] stored in the memory node of the memory cell MC[n]. A potential V R As a result, the potential of the node N2 is equal to the potential V of the node N1. R and the data held in the memory node of the memory cell MC[n]. Here, the potential of the node N2 is V D[n] Then, the potential V of the node N2 D[n] By measuring the potential difference, the data D[n] stored in the memory node of the memory cell MC[n] can be read.

[0139] By the above operation, data can be read from each of the memory cells MC of the semiconductor device shown in FIGS. 4A to 4C.

[0140] Note that the operation of the data processing device of one embodiment of the present invention is not limited to the above-described operation example. The operation of the data processing device of one embodiment of the present invention may be modified as appropriate from the above-described operation example depending on the situation. For example, in the above-described read operation, when a potential V R By supplying a potential V according to the data held in the memory node of the MC of the desired memory cell from the node N2, D Read out.

[0141] Next, an example of a method of treating the NAND type memory circuit shown in FIG. 6 or FIG. 7 as a cache memory in order to apply it to the memory unit 1196 in FIG. 1 will be described.

[0142] FIG. 9 is a configuration example of a storage unit having blocks BLK_1 to BLK_k (k is an integer equal to or greater than 1). Each of blocks BLK_1 to BLK_k has memory cells MC[1,1] to MC[n,m] in a matrix of n rows and m columns, as shown in FIG. 6 or FIG. 7. Note that blocks BLK_1 to BLK_k shown in FIG. 9 only show memory cells MC in a certain column. Therefore, in FIG. 9, the address of the row of the matrix-shaped memory cells MC included in block BLK is written as "[ ]", and the address of block BLK is written as "_", and the address of the column is omitted from the code. In addition, when the configuration of the storage unit shown in FIG. 6 is applied to the storage unit shown in FIG. 9, the back gates of the transistors shown in FIG. 9 are omitted.

[0143] The storage unit illustrated in FIG. 9 has a configuration in which transistors BTr_1 to BTr_k and transistors STr_1 to STr_k are added to the storage unit illustrated in FIG. 6 or FIG.

[0144] Specifically, in the storage unit of FIG. 9, the wiring RBL_1 is electrically connected to the first terminal of the transistor BTr_1 and the first terminal of the transistor STr_1. The second terminal of the transistor STr_1 is electrically connected to the wiring WBL_1 and the first terminal of the switch SW_1. The wiring RBL_h (h is an integer not less than 1 and not more than k) is electrically connected to the first terminal of the transistor BTr_h and the first terminal of the transistor STr_h. The second terminal of the transistor STr_h is electrically connected to the wiring WBL_h and the first terminal of the switch SW_h. The wiring RBL_k is electrically connected to the first terminal of the transistor BTr_k and the first terminal of the transistor STr_k. The second terminal of the transistor STr_k is electrically connected to the wiring WBL_k and the first terminal of the switch SW_k.

[0145] Second terminals of the switches SW_1 to SW_k are electrically connected to a wiring LN1, and third terminals of the switches SW_1 to SW_k are electrically connected to a wiring LN2.

[0146] Each of the switches SW_1 to SW_k has a function of establishing electrical continuity between the first terminal and either the second terminal or the third terminal. That is, each of the switches SW_1 to SW_k can select whether each of the blocks BLK_1 to BLK_k is to be established in electrical continuity with the wiring LN1 or the wiring LN2.

[0147] The wiring LN1 functions as, for example, a wiring that transmits data to be written to memory cells of strings in each of the blocks BLK_1 to BLK_k. The wiring LN2 functions as, for example, a wiring that transmits data read from memory cells of strings in each of the blocks BLK_1 to BLK_k. Note that the data processing device of one embodiment of the present invention is not limited to this configuration. For example, the number of wirings LN1 and LN2 does not have to be two, and may be one (in this case, the switches SW_1 to SW_k do not have to be provided), or three or more wirings (in this case, each of the switches SW_1 to SW_k may be replaced with a selector circuit or the like according to the number of wirings).

[0148] Each of the transistors BTr_1 to BTr_k functions as a transistor for adjusting the potential of the node N1 of each of the wirings RBL_1 to RBL_k. For this reason, a predetermined potential is input to the second terminal and the gate of each of the transistors BTr_1 to BTr_k. Specifically, for example, when a potential is read from any one of the memory cells MC[1]_h to MC[n]_h of the block BLK_h (h is an integer of 1 to k), the transistor BTr[i] has a function of changing the potential of the node N1 of the wiring RBL_h to a write potential. For this reason, the transistors BTr_1 to BTr_k may be replaced with an amplifier circuit such as a sense amplifier.

[0149] Each of the transistors STr_1 to STr_k functions as a switching element, and therefore, a gate of each of the transistors STr_1 to STr_k is electrically connected to a wiring that transmits a signal for switching each of the transistors STr_1 to STr_k to an on state or an off state.

[0150] Next, a method of operation of the storage unit when a part of the storage unit in Fig. 9 functions as a cache memory will be described. The method of operation will be described using the storage unit shown in Fig. 10.

[0151] The storage unit in Fig. 10 is a simplified representation of the storage unit in Fig. 9. Specifically, the storage unit in Fig. 10 has a configuration in which m is 3 and k is 3 in the storage unit in Fig. 9.

[0152] 10 includes blocks BLK_1 to BLK_3, each of which includes one or more strings. Specifically, the block BLK_1 includes memory cells MC[1]_1 to MC[3]_1 as one string, the block BLK_2 includes memory cells MC[1]_2 to MC[3]_2 as one string, and the block BLK_3 includes memory cells MC[1]_3 to MC[3]_3 as one string.

[0153] It is assumed that data is held in the memory nodes of the memory cells MC[1]_2 to MC[3]_2 included in the string of the block BLK_2. Specifically, for example, it is assumed that potentials V[1]_2, V[2]_2, and V[3]_2 are held in the memory nodes of the memory cells MC[1]_2 to MC[3]_2, respectively.

[0154] In addition, it is assumed that no data is held in the memory nodes of memory cells MC[1]_1 to MC[3]_1 included in the string of block BLK_1, and memory cells MC[1]_3 to MC[3]_3 included in the string of block BLK_3.

[0155] Here, consider the case where V[1]_2 held in the memory node of memory cell MC[1]_2 is rewritten.

[0156] When rewriting the potential of the memory node of memory cell MC[1]_2, rewrite data is sent to memory cell MC[1]_2 from wiring WBL_2 via the respective transistors WTr of memory cell MC[2]_2 and memory cell MC[3]_2, so it is necessary to temporarily store V[2]_2 and V[3]_2 that are pre-stored in the respective memory nodes of memory cell MC[2]_2 and memory cell MC[3]_2.

[0157] First, the potential V REW is written to the memory node of the memory cell MC[3]_1 included in the string of the block BLK_1, for example. Specifically, the first terminal and the second terminal of the switch SW_1 are brought into a conductive state, a high-level potential is input to the wiring WWL[3]_1 to turn on the transistor WTr of the memory cell MC[3]_1, and a V REW At this time, a low-level potential is input to the wiring WWL[3]_2 of the block BLK_2 and the wiring WWL[3]_3 of the block BLK_3, the transistors WTr of the memory cells MC[3]_2 and MC[3]_3 are turned off, and V REW Alternatively, in each of the switches SW_2 and SW_3, the first terminal and the third terminal may be brought into a conductive state, that is, the first terminal and the second terminal may be brought into a non-conductive state.

[0158] At this time, the memory cell MC[3]_1 can be regarded as a cache memory.

[0159] Next, V[3]_2 held in the memory node of the memory cell MC[3]_2 of the block BLK_2 is temporarily saved. In this operation example, V[3]_2 of the memory node of the memory cell MC[3]_2 is saved in the memory node of the memory cell MC[2]_3 of the block BLK_3. Specifically, the first terminal and the second terminal of each of the switches SW_2 and SW_3 are brought into a conductive state, and a high-level potential is input to the wiring RWL[1]_2 and the wiring RWL[2]_2, so that the transistors RTr of the memory cells MC[1]_2 and the memory cells MC[2]_2 are sufficiently turned on, and the potentials of the memory nodes of the memory cells MC[1]_2 and the memory cells MC[2]_2 are raised. In addition, a high-level potential is input to the gate of the transistor STr_2 to turn on the transistor STr_2. In addition, a low-level potential is input to the gate of the transistor STr_3 to turn off the transistor STr_3, and a high-level potential is input to the wiring WWL[2]_3 and the wiring WWL[3]_3 of the block BLK_3 to turn on the transistors WTr of the memory cell MC[2]_3 and the memory cell MC[3]_3.

[0160] Here, V is applied to node N2 of block BLK_2. R By supplying V[3]_2 to the memory node of the memory cell MC[3]_2 in the block BLK_2, the potential of the node N1 in the block BLK_2 can be set to a potential corresponding to V[3]_2 held in the memory node of the memory cell MC[3]_2 in the block BLK_2. In addition, the potential of the node N1 can be changed to V[3]_2 by the transistor BTr_2.

[0161] At this time, since the node N1 of the block BLK_2 and the memory node of the memory cell MC[2]_3 of the block BLK_3 are electrically connected, the potential of the memory node of the memory cell MC[2]_3 of the block BLK_3 becomes V[3]_2. Then, a low-level potential is input to the wiring WWL[2]_3 to turn off the transistor WTr of the memory cell MC[2]_3, thereby holding the potential of V[3]_2 at the memory node of the memory cell MC[2]_3.

[0162] Next, V[2]_2 held in the memory node of the memory cell MC[2]_2 of the block BLK_2 is temporarily saved. In this operation example, V[2]_2 of the memory node of the memory cell MC[2]_2 is saved in the memory node of the memory cell MC[3]_3 of the block BLK_3. Specifically, the first terminal and the second terminal of each of the switches SW_2 and SW_3 are brought into a conductive state, and a high-level potential is input to the wiring RWL[1]_2 and the wiring RWL[3]_2, so that the transistors RTr of the memory cells MC[1]_2 and the memory cells MC[3]_2 are sufficiently turned on, and the potentials of the memory nodes of the memory cells MC[1]_2 and the memory cells MC[3]_2 are raised. In addition, a high-level potential is input to the gate of the transistor STr_2 to turn on the transistor STr_2. In addition, a low-level potential is input to the gate of the transistor STr_3 to turn off the transistor STr_3, and a high-level potential is input to the wiring WWL[3]_3 of the block BLK_3 to turn on each transistor WTr of the memory cell MC[3]_3.

[0163] Here, V is applied to node N2 of block BLK_2. R By supplying V[2]_2 to the memory node of the memory cell MC[2]_2 in the block BLK_2, the potential of the node N1 in the block BLK_2 can be set to a potential corresponding to V[2]_2 held in the memory node of the memory cell MC[2]_2 in the block BLK_2. In addition, the potential of the node N1 can be changed to V[2]_2 by the transistor BTr_2.

[0164] At this time, since the node N1 of the block BLK_2 and the memory node of the memory cell MC[3]_3 of the block BLK_3 are electrically connected, the potential of the memory node of the memory cell MC[3]_3 of the block BLK_3 becomes V[2]_2. Then, a low-level potential is input to the wiring WWL[3]_3 to turn off the transistor WTr of the memory cell MC[3]_3, thereby holding the potential of V[2]_2 at the memory node of the memory cell MC[3]_3.

[0165] Next, the data held in each memory node of the memory cells MC[1]_2 to MC[3]_2 in the block BLK_2 is erased.

[0166] Specifically, first, the first terminal and the second terminal of the switch SW_2 are brought into a conductive state, and a low-level potential is input to each of the gates of the transistors STr_1 to STr_3 to turn off each of the transistors STr_1 to STr_3. A low-level potential is input to the wiring WWL[3]_1 of the block BLK_1 and the wiring WWL[3]_3 of the block BLK_3 to turn off each of the transistors WTr of the memory cell MC[3]_1 of the block BLK_1 and the memory cell MC[3]_3 of the block BLK_3. Alternatively, the first terminal and the third terminal of each of the switches SW_1 and SW_3 may be brought into a conductive state, that is, the first terminal and the second terminal may be brought into a non-conductive state.

[0167] After that, a high-level potential is input to each of the wirings WWL[1]_2 to WWL[3]_2 of the block BLK_2 to turn on the transistors WTr of the memory cells MC[1]_2 to MC[3]_2 of the block BLK_2. At this time, a potential for data initialization (e.g., a low-level potential, a ground potential, etc.) is applied from the wiring LN1 to each of the memory nodes of the memory cells MC[1]_2 to MC[3]_2 to rewrite the potentials held in the memory nodes of the memory cells MC[1]_2 to MC[3]_2 to the potentials for initialization. After that, a low-level potential is input to each of the wirings WWL[1]_2 to WWL[3]_2 of the block BLK_2 to turn off the transistors WTr of the memory cells MC[1]_2 to MC[3]_2 of the block BLK_2 to complete erasing of data from the memory cells MC[1]_2 to MC[3]_2 of the block BLK_2. Note that at the timing of writing data described below, the data is rewritten by turning on the transistors WTr of the memory cells MC[1]_2 to MC[3]_2. Therefore, the erase operation described above does not need to be performed.

[0168] Next, V held in the memory node of the memory cell MC[3]_1 of the block BLK_1 REWis written to the memory cell MC[2]_2 of the block BLK_2. Specifically, the first terminal and the second terminal of each of the switches SW_1 and SW_2 are brought into a conductive state, and a high-level potential is input to the wirings RWL[1]_1 and RWL[2]_1, so that the transistors RTr of each of the memory cells MC[1]_1 and MC[2]_1 are sufficiently turned on, and the potentials of the memory nodes of the memory cells MC[1]_1 and MC[2]_1 are raised. A high-level potential is input to the gate of the transistor STr_1 to turn on the transistor STr_1. A low-level potential is input to the gate of the transistor STr_2 to turn off the transistor STr_2, and a high-level potential is input to the wirings WWL[1]_3 to WWL[3]_3 of the block BLK_2 to turn on the transistors WTr of each of the memory cells MC[1]_3 to MC[3]_3.

[0169] At this time, a low-level potential is input to the wiring WWL[3]_3 of the block BLK_3 to turn off the transistor WTr of the memory cell MC[3]_3, and a low-level potential is input to the gate of the transistor STr_3 to turn off the transistor STr_3, thereby discharging V from the block BLK_1 to the memory cell MC[3]_3 of the block BLK_3. REW Alternatively, the first terminal and the third terminal of the switch SW_3 may be brought into a conductive state, that is, the first terminal and the second terminal may be brought into a non-conductive state.

[0170] Here, V is applied to node N2 of block BLK_1. R , the potential of the node N1 of the block BLK_1 is changed to V held in the memory node of the memory cell MC[3]_1 of the block BLK_1. REW The potential of the node N1 can be set to a potential according to V REW can be varied to

[0171] At this time, the node N1 of the block BLK_1 and the memory node of the memory cell MC[1]_2 of the block BLK_2 are electrically connected to each other, so that the potential of the memory node of the memory cell MC[1]_2 of the block BLK_2 becomes V REW After that, a low-level potential is input to the wiring WWL[1]_2 to turn off the transistor WTr of the memory cell MC[1]_2, thereby applying V REW The potential can be maintained at .

[0172] Next, V[2]_2 held in the memory node of the memory cell MC[3]_3 in the block BLK_3 is written back to the memory cell MC[2]_2 in the block BLK_2. Specifically, the first terminal and the second terminal of each of the switches SW_2 and SW_3 are brought into a conductive state, and a high-level potential is input to the wirings RWL[1]_3 and RWL[2]_3, so that the transistors RTr of the memory cells MC[1]_3 and MC[2]_3 are sufficiently turned on, thereby increasing the potentials of the memory nodes of the memory cells MC[1]_3 and MC[2]_3. In addition, a high-level potential is input to the gate of the transistor STr_3 to turn on the transistor STr_3. In addition, a low-level potential is input to the gate of the transistor STr_2 to turn off the transistor STr_2, and a high-level potential is input to the wiring WWL[2]_2 and the wiring WWL[3]_2 of the block BLK_2 to turn on the transistors WTr of the memory cells MC[2]_2 and MC[3]_2.

[0173] At this time, it is necessary to prevent writing of V[2]_2 from the block BLK_3 to the memory cell MC[3]_1 of the block BLK_1 by inputting a low-level potential to the wiring WWL[3]_1 of the block BLK_1 to turn off the transistor WTr of the memory cell MC[3]_1, and by inputting a low-level potential to the gate of the transistor STr_1 to turn off the transistor STr_1. Alternatively, the first and third terminals of the switch SW_1 may be brought into a conductive state, that is, the first and second terminals may be brought into a non-conductive state.

[0174] Here, V is applied to node N2 of block BLK_3. R By supplying V[2]_2 to the memory node of the memory cell MC[3]_3 in the block BLK_3, the potential of the node N1 in the block BLK_3 can be set to a potential corresponding to V[2]_2 held in the memory node of the memory cell MC[3]_3 in the block BLK_3. In addition, the potential of the node N1 can be changed to V[2]_2 by the transistor BTr_3.

[0175] At this time, since the node N1 of the block BLK_3 and the memory node of the memory cell MC[2]_2 of the block BLK_2 are electrically connected, the potential of the memory node of the memory cell MC[2]_2 of the block BLK_2 becomes V[2]_2. Then, a low-level potential is input to the wiring WWL[2]_2 to turn off the transistor WTr of the memory cell MC[2]_2, thereby completing the writing back of the potential of V[2]_2 to the memory node of the memory cell MC[2]_2.

[0176] Next, V[3]_2 held in the memory node of the memory cell MC[2]_3 of the block BLK_3 is written back to the memory cell MC[3]_2 of the block BLK_2. Specifically, the first terminal and the second terminal of each of the switches SW_2 and SW_3 are brought into a conductive state, and a high-level potential is input to the wiring RWL[1]_3 and the wiring RWL[3]_3, so that the transistors RTr of the memory cells MC[1]_3 and the memory cells MC[3]_3 are sufficiently turned on, and the potentials of the memory nodes of the memory cells MC[1]_3 and the memory cells MC[3]_3 are raised. A high-level potential is input to the gate of the transistor STr_3 to turn the transistor STr_3 on. A low-level potential is input to the gate of the transistor STr_2 to turn the transistor STr_2 off, and a high-level potential is input to the wiring WWL[3]_2 of the block BLK_2 to turn the transistors WTr of the memory cells MC[3]_2 on.

[0177] At this time, it is necessary to prevent writing of V[3]_2 from the block BLK_3 to the memory cell MC[3]_1 of the block BLK_1 by inputting a low-level potential to the wiring WWL[3]_1 of the block BLK_1 to turn off the transistor WTr of the memory cell MC[3]_1, and by inputting a low-level potential to the gate of the transistor STr_1 to turn off the transistor STr_1. Alternatively, the first terminal and the third terminal of the switch SW_1 may be brought into a conductive state, that is, the first terminal and the second terminal may be brought into a non-conductive state.

[0178] Here, V is applied to node N2 of block BLK_3. R By supplying V[3]_2 to the memory node of the memory cell MC[2]_3 of the block BLK_3, the potential of the node N1 of the block BLK_3 can be set to a potential corresponding to V[3]_2 held in the memory node of the memory cell MC[2]_3 of the block BLK_3. In addition, the potential of the node N1 can be changed to V[3]_2 by the transistor BTr_3.

[0179] At this time, since the node N1 of the block BLK_3 and the memory node of the memory cell MC[3]_2 of the block BLK_2 are electrically connected, the potential of the memory node of the memory cell MC[3]_2 of the block BLK_2 becomes V[3]_2. Then, a low-level potential is input to the wiring WWL[3]_2 to turn off the transistor WTr of the memory cell MC[3]_2, thereby completing the writing back of the potential of V[3]_2 to the memory node of the memory cell MC[3]_2.

[0180] By performing the above-described operations, the memory unit shown in FIG. 9 or FIG. 10 can treat a portion of the memory unit as a cache memory when writing data to the memory unit, rewriting data stored in the memory unit, etc.

[0181] However, due to the environment (temperature, humidity, etc.) of the information processing device, soft errors caused by natural radiation, etc., at least one of the transistor characteristics of the transistors WTr, RTr, BTr, and STr included in each memory cell of the string of the storage unit shown in FIG. 9 or FIG. 10 may deteriorate (for example, the source-drain current of the transistor in the off state increases). In this case, by having the controller 1197 of the information processing device 50 of FIG. 1 have a function of performing an error check on the string (memory cell) included in the storage unit, it is possible to perform an error check on the string of the storage unit shown in FIG. 9 or FIG. 10. In addition, the controller 1197 may have a function of stopping access to the string including the memory cell when an error is found in the memory cell that has been subjected to the error check, and accessing another string.

[0182] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0183] (Embodiment 3) In this embodiment, a configuration example of the data processing device described in Embodiment 1 and a configuration example of a transistor that can be applied to the data processing device will be described.

[0184] <Configuration example 1 of information processing device> The information processing device shown in Fig. 11 includes a storage unit 100 and a control unit 200. Fig. 11 is a cross-sectional view of a transistor 300 in a channel length direction, and Fig. 12 is a cross-sectional view of the transistor 300 in a channel width direction.

[0185] 11, a control unit 200 corresponds to a circuit including the controller 1197 in FIG. 1, and a storage unit 100 corresponds to the storage unit 1196 in FIG.

[0186] First, the transistor 300 included in the control unit 200 and the insulators, conductors, etc. formed around it will be described.

[0187] As an example, the transistor 300 is provided on a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b that function as a source region or a drain region. Note that the transistor 300 can be applied to a transistor included in the controller 1197, for example.

[0188] Moreover, as the substrate 311, it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate).

[0189] 12, the upper surface and the side surface in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this manner, the effective channel width is increased, thereby improving the on-characteristics of the transistor 300. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-characteristics of the transistor 300.

[0190] The transistor 300 may be either a p-channel type or an n-channel type.

[0191] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low resistance region 314a which becomes the source region or the drain region, and the low resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single crystal silicon. Alternatively, they may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0192] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0193] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, such as silicon, containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, a metal material, an alloy material, or a metal oxide material.

[0194] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use metal materials such as tungsten and aluminum as the conductor in a laminated state, and in particular, it is preferable to use tungsten in terms of heat resistance.

[0195] 11 and 12 is merely an example, and the present invention is not limited to this structure, and an appropriate transistor may be used depending on the circuit configuration, driving method, etc. For example, the control unit 200 of the information processing device may be a unipolar circuit including only OS transistors.

[0196] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 300.

[0197] As the insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used.

[0198] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen, silicon nitride oxide refers to a material having a higher nitrogen content than oxygen, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen.

[0199] The insulator 322 may function as a planarizing film that planarizes steps caused by the transistor 300 provided thereunder. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0200] Furthermore, it is preferable to use a film having barrier properties for the insulator 324 to prevent impurities such as hydrogen from diffusing from the substrate 311 or the transistor 300 to the memory unit 100 including the transistor 700, the multiple transistors 800, and the transistor 900.

[0201] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when the transistor 700, the plurality of transistors 800, and the transistor 900 are OS transistors, hydrogen may diffuse into the semiconductor elements including an oxide semiconductor of the transistor 700, the plurality of transistors 800, and the transistor 900, and the characteristics of the semiconductor elements may be degraded. Therefore, a film that suppresses hydrogen diffusion is preferably used between the transistor 700, the plurality of transistors 800, and the transistor 900 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0202] The amount of desorption of hydrogen can be analyzed, for example, by using thermal desorption spectrometry (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in the TDS analysis. 15 atoms / cm 2 Less than or equal to 5×10 15 atoms / cm 2 The following is acceptable.

[0203] The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0204] Moreover, for example, conductors 328 and 330 are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wiring. In addition, for conductors that function as plugs or wiring, the same reference numerals may be given to a plurality of structures. In addition, in this specification, the wiring and the plug that connects to the wiring may be integral. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0205] As the material for each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a laminated layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form the wiring from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, it is possible to reduce the wiring resistance.

[0206] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 11 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring connected to the transistor 300. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0207] Note that, for example, the insulator 350 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the memory unit 100 including the transistor 700, the plurality of transistors 800, and the transistor 900 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the memory unit 100 can be suppressed.

[0208] Note that, for example, tantalum nitride or the like may be used as the conductor having a barrier property against hydrogen. By stacking tantalum nitride and tungsten having high conductivity, it is possible to suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0209] It is preferable to use an insulator having a barrier property against hydrogen over the insulator 354 and the conductor 356. For example, in FIG. 11, an insulator 360 is provided over the insulator 354 and the conductor 356. Note that an opening may be provided in the insulator 360 and a conductor may be formed so as to be electrically connected to the conductor 356. In this case, the conductor functions as a plug or a wiring. The conductor can be provided using a material similar to that of the conductor 328 and the conductor 330. In particular, it is preferable that the conductor includes a conductor having a barrier property against hydrogen.

[0210] Furthermore, by using an insulator having a hydrogen barrier property for the insulator 360 and a conductor having a hydrogen barrier property for the conductor, the transistor 300 can be separated from the transistor 700, the plurality of transistors 800, and the transistor 900 described below by a barrier layer. Therefore, diffusion of hydrogen from the transistor 300 to the transistor 700, the plurality of transistors 800, and the transistor 900 can be suppressed.

[0211] Next, the transistor 700, the plurality of transistors 800, and the transistor 900 included in the memory unit 100, as well as the insulators, conductors, and the like formed around them will be described.

[0212] 11 shows an example in which the memory unit 100 has a three-dimensional NAND memory circuit. The memory unit 100 of the information processing device shown in FIG. 11 has a transistor 700, a plurality of transistors 800, and a transistor 900 as components of the three-dimensional NAND memory circuit. Note that the transistor 700 and the transistor 900 correspond to transistors for selecting the plurality of transistors 800 located in the same opening as the transistors 700 and 900, and the transistor 800 corresponds to a cell transistor for storing data. Note that in this specification and the like, the transistor 700, the plurality of transistors 800, and the transistor 900 located in the same opening may be referred to as a string.

[0213] 11 is provided on the control unit 200. The memory unit 100 includes, above the control unit 200, insulators 111 to 117, insulators 121, 122, insulators 131, 132, and 133, conductors 151 to 156, and semiconductors 141 to 143.

[0214] The insulator 111 is provided above the control unit 200. For this reason, the insulator 360 located below the insulator 111 is preferably formed by a film forming method that provides good flatness. In addition, it is preferable that the insulator 360 is subjected to a CMP process.

[0215] For example, a material containing silicon oxide or silicon oxynitride can be used as the insulator 111. Also, for example, an insulator containing a material selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, tantalum, etc. can be used in a single layer or a multilayer structure.

[0216] The conductor 151 is provided by being laminated on the insulator 111. The conductor 151 functions as a wiring that applies a predetermined potential to all the strings in the memory unit 100, for example.

[0217] The conductor 151 may be, for example, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like. A semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used. A conductive material containing a metal element and oxygen contained in the metal oxide described in the sixth embodiment may be used. A conductive material containing a metal element such as titanium or tantalum and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. For example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide to which silicon has been added, and the like may be used. For example, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen or water that is mixed in from surrounding insulators, etc.

[0218] There is no particular limitation on the method for forming the conductor 151. For example, the conductor 151 can be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.), a molecular beam epitaxy (MBE) method, an atomic layer deposition (ALD) method, a pulsed laser deposition (PLD) method, etc.

[0219] The insulators 112 to 117 can be, for example, a material similar to that of the insulator 111. For the insulators 112 to 117, it is preferable to use, for example, a material with a low dielectric constant. By using a material with a low dielectric constant for the insulators 112 to 117, the value of parasitic capacitance generated by the conductors 152 to 156 and the insulators 112 to 117 can be reduced. As a result, the driving speed of the memory unit 100 can be improved.

[0220] There is no particular limitation on the method for forming the insulators 112 to 117. For example, the insulators can be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, and the like), an MBE method, an ALD method, a PLD method, or the like.

[0221] The conductor 152 functions as a gate of the transistor 900 and a wiring electrically connected to the gate. The conductors 153 to 155 function as gates of the multiple transistors 800 and wiring electrically connected to the gate. The conductor 156 functions as a gate of the transistor 700 and a wiring electrically connected to the gate.

[0222] The conductors 152 to 156 can be formed using, for example, a material similar to that of the conductor 151. The conductors 152 to 156 can be formed using a method similar to that of the conductor 151.

[0223] Openings are provided in the insulators 112 to 117 and the conductors 152 to 156. The insulators 121, 122, the insulators 131 to 133, and the semiconductors 141 to 143 are provided in the openings.

[0224] The semiconductor 141 is provided so as to be in contact with a part of the side surface and the bottom surface of the opening. Specifically, the semiconductor 141 is provided on a part of the conductor 151 and is provided so as to cover a part of the insulator 112 on the side surface of the opening.

[0225] The semiconductor 141 is preferably, for example, silicon in which an impurity is diffused. The impurity may be an n-type impurity (donor). The n-type impurity may be, for example, phosphorus, arsenic, or the like. The impurity may be a p-type impurity (acceptor). The p-type impurity may be, for example, boron, aluminum, gallium, or the like. The silicon may be, for example, single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like. In addition, other than silicon, metal oxides with high carrier concentration may be applied as the semiconductor 141. Semiconductors such as Ge, and compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe may be applied.

[0226] Note that the material applied to the semiconductor 142 and the semiconductor 143 described later is preferably the same as the material of the semiconductor 141, and the carrier concentration of the semiconductor 142 may preferably be lower than that of the semiconductor 141 and the semiconductor 143.

[0227] For example, when silicon with p-type impurities diffused therein is used as the semiconductor 141, it is preferable to add p-type impurities such as boron, aluminum, or gallium to the semiconductor 141 after forming the semiconductor 141 on the conductor 151. This forms a p-type region in the semiconductor 141. Also, when silicon with n-type impurities diffused therein is used, it is preferable to add n-type impurities such as phosphorus or arsenic to the semiconductor 141 after forming the semiconductor 141 on the conductor 151. This forms an n-type region in the semiconductor 141.

[0228] When a metal oxide is used as the semiconductor 141, for example, a metal element or the like is preferably added to the semiconductor 141 after the semiconductor 141 is formed over the conductor 151. This makes it possible to increase the carrier concentration in the semiconductor 141. In particular, when a metal oxide described in Embodiment 6 is used as the semiconductor 141, the semiconductor 141 is preferably provided with an n-type region (n+ Alternatively, instead of adding a metal element or the like to the semiconductor 141, water, hydrogen, or the like may be added and then a heat treatment may be performed to generate oxygen vacancies in the semiconductor 141. An n-type region is formed in the region of the semiconductor 141 where oxygen vacancies have occurred, and as a result, the carrier concentration of the semiconductor 141 increases.

[0229] The insulator 121 is provided so as to be in contact with a part of the bottom surface of the opening. Specifically, the insulator 121 is provided so as to cover a part of the top surface of the semiconductor 141 and the conductor 152 on the side surface of the opening.

[0230] The insulator 121 functions as a gate insulating film for the transistor 900.

[0231] As the insulator 121, for example, silicon oxide, silicon oxynitride, or the like can be used. In particular, when a metal oxide is used as the semiconductor 142 described later, the insulator 121 is preferably a material that releases oxygen by heating. By providing the insulator 121 containing oxygen in contact with the metal oxide used as the semiconductor 142, oxygen vacancies in the metal oxide can be reduced and the reliability of the transistor 900 can be improved.

[0232] Although there is no particular limitation on the method for forming the insulator 121, a method for forming the insulator 121 with high film-covering properties is required because the insulator 121 is formed on the side surfaces of the openings provided in the insulator 112, the conductor 152, and the insulator 113. Examples of the method for forming the insulator 121 with high film-covering properties include the ALD method.

[0233] The insulator 131 is provided so as to be in contact with a part of the side surface of the opening. Specifically, the insulator 131 is provided so as to cover the conductors 153 to 155 on the side surface of the opening. Therefore, the insulator 131 is provided so as to cover the insulators 114 and 115 on the side surface of the opening.

[0234] The insulator 132 is provided so as to be in contact with the insulator 131. The insulator 133 is provided so as to be in contact with the insulator 132. That is, the insulators 131 to 133 are stacked in order from the side surface of the opening toward the center.

[0235] The insulator 131 functions as a gate insulating film of the transistor 800. The insulator 132 functions as a charge storage layer of the transistor 800. The insulator 133 functions as a tunnel insulating film of the transistor 800.

[0236] As the insulator 131, for example, silicon oxide, silicon oxynitride, or the like can be used. As the insulator 131, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium can be used. As the insulator 131, an insulator in which these are stacked may be used. By making the insulator 131 thicker than the insulator 133, charge can be transferred from the semiconductor 142 described later to the insulator 132 through the insulator 133.

[0237] For example, silicon nitride, silicon nitride oxide, or the like can be used as the insulator 132. However, materials that can be used for the insulator 132 are not limited to these.

[0238] The insulator 133 is preferably made of, for example, silicon oxide or silicon oxynitride. Alternatively, the insulator 133 may be made of, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium. Alternatively, the insulator 133 may be a stack of these insulators.

[0239] The insulator 122 is provided so as to be in contact with a part of the side surface of the opening. Specifically, the insulator 122 is provided so as to cover the conductor 156 on the side surface of the opening.

[0240] The insulator 122 serves as a gate insulating film for the transistor 700 .

[0241] The insulator 122 can be formed using, for example, a material similar to that of the insulator 121. The insulator 122 can be formed using a method similar to that of the insulator 121.

[0242] The semiconductor 142 is provided in the opening so as to be in contact with the side surfaces of the insulators 121, 133, and 122 that have been formed.

[0243] The semiconductor 142 functions as channel formation regions of the transistor 700, the transistor 800, and the transistor 900, and as wiring for electrically connecting the transistor 700, the transistor 800, and the transistor 900 in series.

[0244] It is preferable to use, for example, silicon as the semiconductor 142. Furthermore, as the silicon, for example, single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like can be used. Furthermore, as the semiconductor 142, metal oxides other than silicon may be used in some cases. Furthermore, semiconductors such as Ge, and compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe may be used in some cases.

[0245] The semiconductor 143 is provided so as to fill the opening after the semiconductor 141, the semiconductor 142, the insulator 121, the insulator 122, the insulator 131, the insulator 132, and the insulator 133 are formed in the opening. Specifically, the semiconductor 143 is provided so as to be in contact with the insulator 122 and the semiconductor 142 and in contact with the side surface of the insulator 117.

[0246] The semiconductor 143 is preferably made of, for example, the same material as the semiconductor 141. Therefore, it is preferable that the polarities of the semiconductor 141 and the semiconductor 143 are the same.

[0247] A wiring layer may be provided over the insulator 117 and the semiconductor 143. For example, in FIG. 11, an insulator 382 and an insulator 384 are stacked in this order as a wiring layer. A conductor 386 is formed in the insulator 382 and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0248] Note that the data processing device of one embodiment of the present invention is not limited to the configuration of the NAND memory circuit included in the memory unit 100 illustrated in Figure 11. The NAND memory circuit used in the data processing device of one embodiment of the present invention may have a different configuration from the NAND memory circuit illustrated in Figure 11.

[0249] <Configuration example 2 of information processing device> Fig. 13 shows an example of the configuration of an information processing device different from that of Fig. 11. The information processing device shown in Fig. 13 has a configuration obtained by modifying the configuration of the storage unit 100 of the information processing device of Fig. 11, and specifically, the storage unit 100 of the information processing device of Fig. 13 has the configuration of the storage unit of Fig. 4A described in the second embodiment.

[0250] In the storage unit 100 of the information processing device shown in FIG. 13, as an example, a memory cell MC[1] included in a three-dimensional NAND type storage circuit has a transistor RTr, a transistor WTr, and a capacitance CS.

[0251] 13 is provided on the control unit 200, similar to the information processing device in FIG 11. The memory unit 100 includes, above the control unit 200, insulators 211 to 215, insulators 240 to 243, conductors 221, conductors 222, conductors 250 to 253, semiconductors 231, and semiconductors 232.

[0252] The insulator 240 is provided above the control unit 200. For this reason, the insulator 360 located below the insulator 240 is preferably formed by a film forming method that provides good flatness. In addition, it is preferable that the insulator 360 is subjected to a CMP process.

[0253] For the insulator 240, for example, a material applicable to the insulator 111 can be used.

[0254] The insulator 241 is provided by being laminated on the insulator 240 .

[0255] As the insulator 241, for example, a material that can be used for the insulator 111, similar to the insulator 240, can be used.

[0256] Moreover, a conductor 250 is embedded in the insulator 240, and a conductor 251 is embedded in the insulator 241. The conductor 250 and the conductor 251 function as plugs or wiring. As in FIG. 11, the conductors having the function of plugs or wiring shown in FIG. 13 may be collectively labeled with the same reference numerals as multiple structures. In this specification, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0257] The conductor 250 and the conductor 251 can be made of, for example, a material that can be used for the conductor 328 and the conductor 330.

[0258] The insulator 211 is provided on the insulator 241. The conductor 221 is provided on the insulator 211. The insulator 212 is provided on the conductor 221. The conductor 222 is provided on the insulator 212. That is, the insulator 211, the conductor 221, the insulator 212, and the conductor 222 are stacked in this order (these are referred to as a stack). The storage unit 100 of the information processing device in FIG. 13 has stacks equal to the number of memory cells MC included in one string.

[0259] 13, openings are provided in the insulator 211, the conductor 221, the insulator 212, and the conductor 222 by forming a resist mask and performing an etching process. At this time, the conductor 221 is selectively removed so that a recess is formed by the insulator 211, the conductor 221, and the insulator 212. In this case, the conductor 221 is preferably made of a material having a higher etching rate than the insulator 211, the insulator 212, and the conductor 222.

[0260] The resist mask can be formed by, for example, lithography, printing, inkjet, or the like. When the resist mask is formed by the inkjet method, a photomask is not used, so that the manufacturing cost can be reduced. The etching process may be a dry etching method or a wet etching method, or both may be used.

[0261] In addition, as will be described in detail later, in the opening formed by the etching process, an insulator 213, a semiconductor 231, an insulator 214, an insulator 215, a semiconductor 232, an insulator 216, and a conductor 223 are formed in this order.

[0262] As one example, it is preferable to use a film having a barrier property that prevents diffusion of hydrogen, impurities, and the like as the insulators 211 and 212. Therefore, as the insulators 211 and 212, for example, a material similar to that of the insulator 111 can be used.

[0263] For the conductor 221 and the conductor 222, it is preferable to use, for example, a material that can be used for the conductor 151. In particular, for the conductor 221 and the conductor 222, it is preferable to use a conductive material that has a function of suppressing the permeation of impurities such as water or hydrogen.

[0264] On the side surface of the opening formed by the above-mentioned etching process, an insulator 213 and a semiconductor 231 are formed in this order. Also, an insulator 214 is formed so as to fill the recess of the opening.

[0265] As a method of forming the insulator 214, for example, first, the insulator 214 is formed on the side surface of the opening to the extent that the recess of the opening is filled, and then, a part of the insulator 214 is removed by an etching process so that the insulator 214 remains in the recess and the semiconductor 231 is exposed.

[0266] As the insulator 213, for example, silicon oxide, silicon oxynitride, or the like can be used. Furthermore, as the insulator 213, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium can be used. Furthermore, as the insulator 213, an insulator having these stacked layers may be used.

[0267] It is preferable to use a metal oxide as described in the sixth embodiment for the semiconductor 231. In the following description of the present embodiment, it is assumed that a metal oxide is used for the semiconductor 231. In particular, it is preferable to use a CAAC-OS as the metal oxide, which will be described later. For example, when polycrystalline silicon is used for the semiconductor 231, grain boundaries that may be formed in the polycrystalline silicon may increase the electron trap density, which may cause a large variation in the transistor characteristics. On the other hand, since no clear grain boundaries are observed in the CAAC-OS, the variation in the transistor characteristics can be suppressed.

[0268] Furthermore, before forming the insulator 214, the formed semiconductor 231 is subjected to heat treatment in an oxygen atmosphere, thereby making it possible to supply oxygen to the metal oxide of the semiconductor 231. Then, after forming the insulator 214, a supply treatment of impurities or the like is performed on the metal oxide of the semiconductor 231, thereby making it possible to reduce the resistance of the region exposed to the opening of the semiconductor 231. In other words, the region of the semiconductor 231 in contact with the insulator 214 becomes a high-resistance region, and the region of the semiconductor 231 not in contact with the insulator 214 becomes a low-resistance region.

[0269] Furthermore, examples of the process of supplying impurities to the metal oxide of the semiconductor 231 include forming a conductor on the side surface of the opening after filling the recess of the opening with the insulator 214, and removing the conductor. When the conductive film comes into contact with the metal oxide of the semiconductor 231, the metal elements contained in the conductive film may diffuse into the semiconductor 231 and form a metal compound with the constituent elements of the semiconductor 231. This metal compound forms a low-resistance region in the semiconductor 231.

[0270] It is preferable that the insulator 214 does not contain a component that forms a compound with a component contained in the semiconductor 231 at or near the interface with the previously formed semiconductor 231. Specifically, for example, silicon oxide or the like can be used as the insulator 214.

[0271] Thereafter, the insulator 215, the semiconductor 232, the insulator 216, and the conductor 223 are formed in this order on the surfaces on which the semiconductor 231 and the insulator 214 are formed. Note that the formation of the conductor 223 is assumed to fill the openings provided in the stacked body.

[0272] For the insulators 215 and 216, it is preferable to use a material that can be used for the insulator 213, for example.

[0273] As the semiconductor 232, like the semiconductor 231, it is preferable to use the metal oxide described in the sixth embodiment, for example.

[0274] The conductor 223 is preferably made of, for example, a material that can be used for the conductor 151. In particular, the conductor 223 is preferably made of a conductive material that has a function of suppressing the permeation of impurities such as water or hydrogen.

[0275] An insulator 242 and an insulator 243 are provided in that order on top of the formed string.

[0276] As the insulator 242 and the insulator 243, for example, a material that can be used for the insulator 111 can be used.

[0277] Furthermore, a conductor 252 is embedded in the insulator 242, and a conductor 253 is embedded in the insulator 243. The conductor 252 and the conductor 253 function as plugs or wirings.

[0278] The conductor 252 and the conductor 253 can be made of, for example, a material that can be used for the conductor 328 and the conductor 330.

[0279] By carrying out the above-mentioned steps, it is possible to manufacture an information processing device having the storage unit 100 of FIG. 4A.

[0280] Specifically, the wiring WBL, wiring RBL, and wiring BGL in the storage unit in Fig. 4A correspond to the semiconductor 231, the semiconductor 232, and the conductor 223 in Fig. 13. Moreover, the wiring WWL and wiring RWL in the storage unit in Fig. 4A correspond to the conductor 221 and the conductor 222, respectively.

[0281] Therefore, a capacitance CS is configured in which the conductor 222 is one electrode, the region of the insulator 213 in contact with the conductor 222 is a dielectric, and the region of the semiconductor 231 overlapping with the conductor 222 is the other electrode. A transistor RTr is configured in which the region of the semiconductor 231 overlapping with the conductor 222 is a gate, the region of the insulator 215 overlapping with the conductor 222 is a gate insulating film, the region of the semiconductor 232 overlapping with the conductor 222 is a channel formation region, the region of the insulator 216 overlapping with the conductor 222 is a gate insulating film, and the region of the conductor 223 overlapping with the conductor 222 is a back gate. A transistor WTr is configured in which the conductor 221 is a gate, the insulator 213 overlapping with the conductor 221 is a gate insulating film, and the region of the semiconductor 231 overlapping with the conductor 221 is a channel formation region.

[0282] The insulators, conductors, semiconductors, and the like disclosed in this specification can be formed by a PVD (Physical Vapor Deposition) method or a CVD (Chemical Vapor Deposition) method. Examples of the PVD method include a sputtering method, a resistance heating deposition method, an electron beam deposition method, and a PLD (Pulsed Laser Deposition) method. Examples of the CVD method include a plasma CVD method and a thermal CVD method. In particular, examples of the thermal CVD method include a MOCVD (Metal Organic Chemical Vapor Deposition) method and an ALD (Atomic Layer Deposition) method.

[0283] The thermal CVD method is a film formation method that does not use plasma, and therefore has the advantage that defects caused by plasma damage are not generated.

[0284] In the thermal CVD method, a source gas and an oxidant are fed simultaneously into a chamber, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the materials are reacted near or on a substrate to deposit the materials on the substrate, thereby forming a film.

[0285] In addition, in the ALD method, the chamber may be under atmospheric pressure or reduced pressure, raw material gases for the reaction may be sequentially introduced into the chamber, and the order of gas introduction may be repeated to form a film. For example, two or more types of raw material gases may be sequentially supplied to the chamber by switching each switching valve (also called a high-speed valve), and an inert gas (argon, nitrogen, etc.) may be introduced simultaneously with or after the first raw material gas so that the multiple raw material gases are not mixed, and then the second raw material gas is introduced. When the inert gas is introduced simultaneously, the inert gas serves as a carrier gas, and the inert gas may be introduced simultaneously with the introduction of the second raw material gas. Alternatively, instead of introducing the inert gas, the first raw material gas may be exhausted by vacuum evacuation, and then the second raw material gas may be introduced. The first raw material gas is adsorbed on the surface of the substrate to form a first thin layer, and reacts with the second raw material gas introduced later, and the second thin layer is laminated on the first thin layer to form a thin film. By repeating this gas introduction order multiple times until a desired thickness is obtained while controlling the gas introduction order, a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by changing the number of times the gas introduction sequence is repeated, allowing precise adjustment of the film thickness, making this method suitable for fabricating fine FETs.

[0286] Thermal CVD methods such as MOCVD and ALD can form various films such as metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described above. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) are used. In addition, the combination is not limited to these, and triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

[0287] For example, when forming a hafnium oxide film using a film formation device that uses ALD, two types of gas are used: a source gas made by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide, hafnium amide such as tetrakis(dimethylamido)hafnium (TDMAH, Hf[N(CH3)2]4)), and ozone (O3) as an oxidizing agent. Other materials include tetrakis(ethylmethylamido)hafnium.

[0288] For example, when forming an aluminum oxide film using a film formation device that uses ALD, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA, Al(CH3)3)), and H2O as an oxidizing agent. Other materials include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0289] For example, when forming a silicon oxide film using a film formation apparatus that uses ALD, hexachlorodisilane is adsorbed onto the surface to be formed, and radicals of an oxidizing gas (O2, nitrous oxide) are supplied to react with the adsorbed material.

[0290] For example, when forming a tungsten film using a film forming apparatus that uses ALD, WF6 gas and B2H6 gas are repeatedly introduced in sequence to form an initial tungsten film, and then WF6 gas and H2 gas are repeatedly introduced in sequence to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0291] For example, when an oxide semiconductor film, such as an In-Ga-Zn-O film, is formed by a film forming apparatus using ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, then Ga(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form a GaO layer, and then Zn(CH3)2 gas and O3 gas are sequentially and repeatedly introduced to form a ZnO layer. The order of these layers is not limited to this example. Also, mixed oxide layers such as an In-Ga-O layer, an In-Zn-O layer, and a Ga-Zn-O layer may be formed using these gases. Note that, instead of O3 gas, H2O gas obtained by bubbling water with an inert gas such as Ar may be used, but it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3)3 gas, In(C2H5)3 gas may be used. Also, instead of Ga(CH3)3 gas, Ga(C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used.

[0292] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0293] (Embodiment 4) In this embodiment, an application example of a data processing device according to one embodiment of the present invention will be described.

[0294] Generally, a computer has components such as a processor, main memory, and storage on a motherboard, and the components are electrically connected by, for example, bus wiring. Therefore, the longer the bus wiring, the higher the parasitic resistance becomes, and the higher the power consumption required for signal transmission becomes.

[0295] Specifically, a computer may have a configuration as shown in Fig. 14A, for example. The computer has a motherboard BD, on which are provided an arithmetic processing device (processor, CPU, etc.) 10, a main memory (DRAM (Dynamic Random Access Memory) etc.) 30, a storage (a three-dimensional structure NAND type storage device, a 3D OS NAND type storage device etc.) 40, an interface 60, etc. Note that Fig. 14A also illustrates an SRAM (Static Random Access Memory) 20 that also functions as a main memory, but this does not necessarily have to be provided on the motherboard BD.

[0296] FIG. 14A illustrates a configuration in which the arithmetic processing device 10 has a register 11.

[0297] 14A, the arithmetic processing device 10 is electrically connected to the SRAM 20, the main memory 30, the storage 40, and the interface 60. The main memory 30 is also electrically connected to the SRAM 20 and the storage 40.

[0298] 14A is electrically connected to the components of the computer by bus wiring BSH. In other words, the more components of the computer are, or the larger the motherboard BD is, the longer the bus wiring BSH is, and the more power consumption is required to transmit signals.

[0299] Incidentally, the computer of Fig. 14A may be configured such that each component of the computer is integrated into one chip to form a monolithic IC (Integrated Circuit). In this case, the information processing device 50 of Fig. 1, etc., described in the above embodiment, can be applied as the main memory 30 and the storage 40. Fig. 14B shows the computer of Fig. 14A as a monolithic IC.

[0300] 14B includes a circuit layer LGC on a semiconductor substrate including Si, a memory layer STR on the circuit layer LGC, and a circuit layer OSC on the memory layer STR.

[0301] The circuit layer LGC has, for example, a plurality of circuits including Si transistors formed on a semiconductor substrate SBT having Si. For example, the arithmetic processing device 10, the SRAM 20, and the like in FIG. 14A may be part of the plurality of circuits. In addition, when the information processing device of FIG. 1 or the like is applied as the main memory 30 and the storage 40, a controller 1197 included in the information processing device 50 may be part of the plurality of circuits.

[0302] In particular, the SRAM 20 can increase the driving frequency of the SRAM by using Si transistors, for example.

[0303] The memory layer STR functions as a memory unit having a Si transistor and / or an OS transistor. The memory layer STR may be, for example, a three-dimensional NAND type memory circuit, a 3D OS NAND type memory circuit, or the like. Therefore, the memory layer STR has the memory unit 1196 in the information processing device of FIG. 1, the storage 40 in FIG. 14A, or the like.

[0304] It should be noted that by using a 3D OS NAND type memory circuit, the power consumption of the monolithic IC in FIG. 14B can be reduced.

[0305] The circuit layer OSC has, for example, a plurality of circuits including OS transistors. Some of the plurality of circuits may be circuits, such as the arithmetic processing device 10, the SRAM 20, and the like, that are different from the circuits included in the circuit layer LGC.

[0306] In the monolithic IC of Figure 14B, since there is no bus wiring BSH for wiring on the motherboard, the wiring for electrically connecting each component is short, which reduces the power consumption required for signal transmission.

[0307] Moreover, the monolithic IC in Fig. 14B has an information processing device 50. Therefore, the information processing device 50 functions as the storage 40 and the main memory 30 in Fig. 14A. Therefore, the monolithic IC in Fig. 14B can use the main memory 30 as the memory unit 1196 of the memory layer STR.

[0308] Since the bus wiring BSH is not provided and the storage unit 1196 is used instead of the main memory 30, the monolithic IC in FIG. 14B can reduce the circuit area more than the computer in FIG. 14A.

[0309] A specific schematic diagram of the monolithic IC of Fig. 14B is shown in Fig. 15. The monolithic IC 1500 shown in Fig. 15 has a 3D OS NAND type storage device described in the previous embodiment.

[0310] The circuit layer LGC, the memory layer STR, and the circuit layer OSC are shown in the monolithic IC 1500 in Fig. 15. Note that the semiconductor substrate SBT is omitted from the monolithic IC 1500 in Fig. 15.

[0311] The memory layer STR has a plurality of strings STG. The plurality of strings STG correspond to the strings ST1 to ST3 in the first embodiment.

[0312] Moreover, the conductor ME1 included in the memory layer STR functions as a wiring that electrically connects the circuit layer LGC and the circuit layer OSC.

[0313] Moreover, the conductor ME2 included in the memory layer STR functions as wiring that electrically connects the circuit layer OSC and the multiple conductors ME3.

[0314] Moreover, the conductor ME3 included in the memory layer STR functions as the gates of the cell transistors included in the multiple strings STG and as wiring electrically connected to the gates. That is, the conductor ME3 can be the conductor 152, conductor 153, conductor 154, conductor 155, conductor 156 in Fig. 11, the conductor 2221 (e.g., the wiring RWL[1], etc.) in Fig. 13, or the conductor 221 (e.g., the wiring WWL[1], etc.) in Fig. 13 in the above-mentioned embodiment.

[0315] Next, examples of memory hierarchies for the computer of FIG. 14A and the monolithic IC of FIG. 14B are shown in FIGS. 16A and 16B, respectively.

[0316] In general, in the memory hierarchy, the higher the storage device is located, the faster the operating speed is required, and the lower the storage device is located, the larger the storage capacity and the higher the recording density are required. In Fig. 16A, as an example, a register included in the CPU (arithmetic processing device 10), an SRAM, a DRAM included in the main memory 30, and a three-dimensional structure NAND type storage circuit included in the storage 40 are shown in order from the top layer.

[0317] The registers and SRAM included in the arithmetic processing device 10 are used for temporarily storing arithmetic results, and are therefore frequently accessed by the arithmetic processing device 10. Therefore, a higher operating speed is required rather than a larger memory capacity. The registers also have the function of storing setting information for the arithmetic processing device.

[0318] The DRAM included in the main memory 30 has a function of holding programs, data, etc. read from the storage 40, for example. The recording density of the DRAM is approximately 0.1 to 0.3 Gbit / mm 2 It is.

[0319] The storage 40 has a function of storing data that needs to be stored for a long time, various programs used by the processor, etc. Therefore, the storage 40 is required to have a large memory capacity and a high recording density rather than an operating speed. The recording density of the memory device used for the storage 40 is approximately 0.6 to 6.0 Gbit / mm 2 For this reason, the storage 40 may be a three-dimensional NAND type memory circuit (3D OS NAND), a hard disk drive (HDD), or the like.

[0320] Incidentally, in the monolithic IC of FIG. 14B, as mentioned above, the information processing device 50 of FIG. 1 plays the role of the storage 40 and main memory 30 of FIG. 14A, so the memory hierarchy of the monolithic IC of FIG. 14B is as shown in FIG. 16B.

[0321] That is, in the monolithic IC of Fig. 14B, the memory cells included in the storage unit 100 of the information processing device 50 of Fig. 1 can be treated not only as the cache memory of the storage unit 100 but also as the main memory 30 in the computer of Fig. 14A. Therefore, in the monolithic IC of Fig. 14B, it is not necessary to provide a main memory 30 such as a DRAM, so that the circuit area of ​​the monolithic IC of Fig. 14B can be reduced, and the power consumption required to operate the main memory 30 such as a DRAM can be reduced.

[0322] The configuration of the monolithic IC shown in Fig. 14B is an example and is not limited to one aspect of the present invention. The configuration of the monolithic IC shown in Fig. 14B may be changed depending on the situation. For example, in the monolithic IC of Fig. 14B, when a high-speed memory of 1 GHz or more is required as the SRAM, the SRAM may be embedded in the arithmetic processing device.

[0323] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0324] (Embodiment 5) In this embodiment, an example of a method for writing to a NAND type memory device such as that described in this specification will be described.

[0325] 17A shows an electrical connection between a processing device (processor, CPU, etc.) 70 and a storage device (a three-dimensional structure NAND type storage device, a 3D OS NAND type storage device) 80. Specifically, the processing device 70 is electrically connected to the storage device 80 via a plurality of wirings 90.

[0326] The arithmetic processing device 70 has a function of transmitting data to be written to memory cells included in the memory device 80 via the multiple wirings 90 to the memory device 80. That is, the multiple wirings 90 function as write bit lines, which correspond to the wirings WBL in the above-mentioned embodiment. For example, when the memory device 80 is a NAND-structure memory device and has multiple strings, each of the multiple wirings 90 is electrically connected to the multiple strings.

[0327] Incidentally, in order to increase the speed at which data is written to the memory cells included in the storage device 80, the wiring 90 may be formed using a material with a low resistance value, the length of the wiring 90 may be shortened, and so on.

[0328] Furthermore, the speed at which data is written to memory cells included in the memory device 80 can be increased by increasing the number of wirings 90. In other words, by increasing the number of wirings 90 (the number of strings of the memory device 80 electrically connected to the wirings 90), the number of pieces of data that can be written to memory cells at one time can be increased.

[0329] Next, a method of transmitting write data will be described with reference to FIG. 17B.

[0330] The arithmetic processing device 70 includes, for example, latch circuits LT1[1] to LT1[z] (z is an integer equal to or greater than 2), latch circuits LT2[1] to LT2[z], and wirings 90[1] to 90[z]. The memory device 80 includes, for example, strings STG[1] to STG[z] as NAND type memory devices.

[0331] In the arithmetic processing device 70, the latch circuits LT1[1] to LT1[z] constitute a shift register. Therefore, a wiring CLK that transmits a clock signal is electrically connected to each of the clock input terminals of the latch circuits LT1[1] to LT1[z]. The shift register can transmit the write data DA input to the input terminal of the latch circuit LT1[1] to the latch circuits LT1[2] to LT1[z] in sequence according to the number of pulse voltages input as a clock signal from the wiring CLK.

[0332] In addition, the output terminal of the latch circuit LT1[v] (where v is an integer between 1 and z) is electrically connected to the input terminal of the latch circuit LT2[v]. Therefore, the data DA output from the latch circuit LT1[v] is input to the latch circuit LT2[v]. In addition, the latch circuit LT2[v] is electrically connected to the string STG[v] via the wiring 90[v].

[0333] The wiring ENL is electrically connected to the clock input terminals of each of the latch circuits LT2[1] to LT2[z]. The wiring ENL functions as a wiring for transmitting a trigger signal for transmitting the data DA from the arithmetic processing device 70 to the storage device 80.

[0334] By serial transmission, data DA is input to the latch circuit LT1[1], and the data DA is sequentially input to the latch circuit LT1[1]. Here, data DA is sequentially input to the latch circuits LT1[1] through LT1[z], and data DA[1] through DA[z] are stored in the latch circuits LT1[1] through LT1[z], respectively.

[0335] At this time, data DA[1] through data DA[z] are output from the output terminals of latch circuits LT1[1] through LT1[z], respectively. Data DA[1] through data DA[z] are input to latch circuits LT2[1] through LT2[z], respectively.

[0336] In this way, the data DA input by serial transmission can be distributed to the latch circuits LT1[1] to LT1[z] as data DA[1] to data DA[z]. In other words, the data DA input by serial transmission can be distributed to the wirings 90[1] to 90[z] as data DA[1] to data DA[z].

[0337] Then, a trigger signal is provided to the clock signal input terminal of each of the latch circuits LT2[1] to LT2[z] via the wiring ENL, so that data DA[1] to DA[z] can be input in parallel from each of the latch circuits LT2[1] to LT2[z] to strings STG[1] to STG[z] of the memory device 80 via wirings 90[1] to 90[z].

[0338] By applying the above-described configuration and driving method, serially transmitted data to be written to the storage device 80 can be sent in parallel to the strings STG[1] to STG[z] of the storage device 80.

[0339] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0340] (Embodiment 6) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) which can be used for the OS transistor described in the above embodiment will be described.

[0341] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains aluminum, gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0342] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 18A. Fig. 18A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0343] As shown in FIG. 18A, oxide semiconductors are broadly classified into "Amorphous", "Crystalline", and "Crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and poly crystal). "Crystalline" excludes single crystal, poly crystal, and completely amorphous. "Crystal" includes single crystal and poly crystal.

[0344] The structure in the bold frame shown in Fig. 18A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from the energetically unstable "Amorphous" and "Crystal".

[0345] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. FIG. 18B shows an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline". The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 18B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in FIG. 18B is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 18B is 500 nm.

[0346] As shown in Figure 18B, a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 18B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0347] The crystal structure of the film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 18C. FIG. 18C shows a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in FIG. 18C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0348] As shown in FIG. 18C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0349] <<Structure of oxide semiconductor>> In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from that shown in FIG. 18A. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0350] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0351] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0352] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0353] In addition, in an In-M-Zn oxide (wherein element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Thus, the (M, Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0354] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0355] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the two spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0356] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a lattice arrangement such as a pentagon or heptagon. In addition, in the CAAC-OS, no clear grain boundary can be confirmed even in the vicinity of the distortion. That is, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms in the ab-plane direction is not dense and the bond distance between atoms changes due to the substitution of metal atoms.

[0357] A crystal structure in which clear grain boundaries are observed is called a polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0358] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities, the generation of defects, and the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0359] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS may be indistinguishable from an a-like OS and an amorphous oxide semiconductor depending on the analysis method. For example, when a structure analysis is performed on an nc-OS film using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. In addition, when an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0360] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0361] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0362] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0363] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0364] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0365] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc., and the second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region mainly composed of In, and the second region can be rephrased as a region mainly composed of Ga.

[0366] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0367] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0368] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in other parts of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching behavior can be achieved.

[0369] Oxide semiconductors have a variety of structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0370] <Transistor Having Oxide Semiconductor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0371] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0372] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than or equal to 1×10 15 cm -3 Less than 1×10, more preferably 13 cm -3 Less than or equal to 1×10 11 cm -3 Less than 1×10, more preferably 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0373] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0374] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0375] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0376] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0377] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentrations of silicon, carbon, etc. in the oxide semiconductor and the concentrations of silicon, carbon, etc. near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0378] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of an alkali metal or an alkaline earth metal in an oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0379] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 To the following:

[0380] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, when the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0381] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0382] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0383] (Embodiment 7) In this embodiment mode, an example of a semiconductor wafer on which the data processing device or the like shown in the above embodiment is formed and an example of an electronic component in which the data processing device is incorporated will be described.

[0384] <Semiconductor wafer> First, an example of a semiconductor wafer on which information processing devices and the like are formed will be described with reference to FIG. 19A.

[0385] 19A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that on the upper surface of the wafer 4801, a portion where the circuit portions 4802 are not present is a spacing 4803, which is a region for dicing.

[0386] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0387] The next step is a dicing step. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) shown by dashed lines. In order to facilitate the dicing step, it is preferable that the spacing 4803 is arranged so that the multiple scribe lines SCL1 are parallel to each other, the multiple scribe lines SCL2 are parallel to each other, and the scribe lines SCL1 and SCL2 are perpendicular to each other.

[0388] By performing a dicing process, a chip 4800a as shown in FIG. 19B can be cut out from the semiconductor wafer 4800. The chip 4800a has a wafer 4801a, a circuit portion 4802, and a spacing 4803a. It is preferable that the spacing 4803a is as small as possible. In this case, it is sufficient that the width of the spacing 4803 between adjacent circuit portions 4802 is approximately equal to the cutting allowance of the scribe line SCL1 or the cutting allowance of the scribe line SCL2.

[0389] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in Fig. 19A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process of the element and the device for manufacturing the element.

[0390] <Electronic components> FIG. 19C shows a perspective view of electronic component 4700 and a substrate (mounting substrate 4704) on which electronic component 4700 is mounted. Electronic component 4700 shown in FIG. 19C has chip 4800a in mold 4711. Note that chip 4800a shown in FIG. 19C has a configuration in which circuit section 4802 is stacked. That is, the information processing device described in the above embodiment can be applied as circuit section 4802. FIG. 19C omits a part in order to show the inside of electronic component 4700. Electronic component 4700 has land 4712 on the outside of mold 4711. Land 4712 is electrically connected to electrode pad 4713, and electrode pad 4713 is electrically connected to chip 4800a by wire 4714. Electronic component 4700 is mounted on, for example, printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on a printed circuit board 4702 to complete a mounting board 4704 .

[0391] 19D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 provided on interposer 4731.

[0392] The electronic component 4730 has a semiconductor device 4710. The semiconductor device 4710 can be, for example, the semiconductor device described in the above embodiment, a high bandwidth memory (HBM), or the like. The semiconductor device 4735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0393] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0394] The interposer 4731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate." In addition, a through electrode may be provided in the interposer 4731, and the integrated circuits and the package substrate 4732 may be electrically connected using the through electrode. In addition, in a silicon interposer, a TSV (Through Silicon Via) may be used as the through electrode.

[0395] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult to form with a resin interposer.

[0396] In HBM, many wirings need to be connected to realize a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts HBM.

[0397] In addition, in SiP, MCM, etc. that use silicon interposers, deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. In addition, since the surface of the silicon interposer is highly flat, connection failures between the integrated circuit mounted on the silicon interposer and the silicon interposer are unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged side by side on the interposer.

[0398] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 4730. When providing a heat sink, it is preferable to make the height of an integrated circuit provided on the interposer 4731 uniform. For example, in the electronic component 4730 shown in this embodiment, it is preferable to make the height of the semiconductor device 4710 and the height of the semiconductor device 4735 uniform.

[0399] In order to mount electronic component 4730 on another substrate, electrodes 4733 may be provided on the bottom of package substrate 4732. FIG. 19D shows an example in which electrodes 4733 are formed of solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Electrodes 4733 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be realized.

[0400] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA. For example, a mounting method such as a Staggered Pin Grid Array (SPGA), a Land Grid Array (LGA), a Quad Flat Package (QFP), a Quad Flat J-leaded package (QFJ), or a Quad Flat Non-leaded package (QFN) can be used.

[0401] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0402] (Embodiment 8) In this embodiment, an example of an electronic device having the information processing device described in the above embodiment will be described. Note that Fig. 20A to Fig. 20J show how an electronic component 4700 having the information processing device is included in each electronic device.

[0403] [mobile phone] 20A is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0404] The information terminal 5500 can store temporary files (such as caches when using a web browser) that are generated when an application is executed by applying the information processing device described in the above embodiment.

[0405] [Wearable devices] 20B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display unit 5902, operation buttons 5903, an operator 5904, a band 5905, and the like.

[0406] Like the information terminal 5500 described above, the wearable terminal can store temporary files generated when an application is executed by applying the information processing device described in the above embodiment.

[0407] [Information terminal] 20C also shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0408] The desktop information terminal 5300, like the information terminal 5500 described above, can hold temporary files generated when an application is executed by applying the information processing device described in the above embodiment.

[0409] In the above description, a smartphone and a desktop information terminal are illustrated in Fig. 20A and Fig. 20C as examples of information processing devices, but information terminals other than smartphones and desktop information terminals can also be applied. Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0410] [electric appliances] 20D illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0411] By applying the information processing device described in the above embodiment to the electric refrigerator-freezer 5800, the electric refrigerator-freezer 5800 can be used as, for example, IoT (Internet of Things). By using IoT, the electric refrigerator-freezer 5800 can transmit and receive information such as ingredients stored in the electric refrigerator-freezer 5800 and the expiration dates of the ingredients to the information terminals described above via the Internet or the like. Furthermore, when transmitting the information, the electric refrigerator-freezer 5800 can hold the information as a temporary file in the information processing device.

[0412] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water servers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0413] [Game consoles] 20E illustrates a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0414] Furthermore, FIG. 20F illustrates a stationary game machine 7500, which is an example of a game machine. The stationary game machine 7500 has a main body 7520 and a controller 7522. The controller 7522 can be connected to the main body 7520 wirelessly or by wire. Although not illustrated in FIG. 20F, the controller 7522 can include a display unit for displaying game images, a touch panel as an input interface other than buttons, a stick, a rotary knob, a sliding knob, and the like. The shape of the controller 7522 is not limited to the shape illustrated in FIG. 20F, and the shape of the controller 7522 may be changed in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller with a trigger as a button and a shape imitating a gun can be used. For example, in a music game, a controller with a shape imitating a musical instrument, a musical device, or the like can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0415] Furthermore, the images of the above-mentioned game machines can be output by display devices such as television sets, personal computer displays, game displays, and head-mounted displays.

[0416] A low-power consumption portable game machine 5200 can be realized by applying the information processing device described in the above embodiment to the portable game machine 5200. In addition, the low power consumption can reduce heat generation from a circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0417] Furthermore, by applying the information processing device described in the above embodiment to the portable game machine 5200, temporary files necessary for calculations occurring during game execution can be stored.

[0418] 20E and 20F illustrate a portable game machine as an example of a game machine, but the information processing device according to an embodiment of the present invention is not limited to this. Examples of the information processing device according to an embodiment of the present invention include a home-use stationary game machine, an arcade game machine installed in an entertainment facility (such as a game center or an amusement park), and a pitching machine for batting practice installed in a sports facility.

[0419] [Mobile object] The information processing device described in the above embodiment can be applied to a vehicle, which is a moving object, and to the vicinity of the driver's seat of the vehicle.

[0420] FIG. 20G illustrates an automobile 5700 as an example of a moving object.

[0421] An instrument panel that provides various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, an air conditioner setting, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows such information may also be provided around the driver's seat.

[0422] In particular, the display device can display images from an imaging device (not shown) installed in the automobile 5700, thereby compensating for visibility obstructed by pillars and blind spots from the driver's seat, thereby improving safety.

[0423] Since the information processing device described in the above embodiment can temporarily hold information, for example, the computer can be used to hold necessary temporary information in an automatic driving system of an automobile 5700, a system that performs road guidance, hazard prediction, etc. The display device may be configured to display temporary information such as road guidance and hazard prediction. Also, the display device may be configured to hold video of a driving recorder installed in the automobile 5700.

[0424] In the above description, an automobile is described as an example of a moving body, but the moving body is not limited to an automobile. For example, the moving body may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc.

[0425] [camera] The information processing device described in the above embodiment can be applied to a camera.

[0426] 20H shows a digital camera 6240 as an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, an operation button 6243, a shutter button 6244, and the like, and a detachable lens 6246 is attached to the digital camera 6240. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, and the like can be separately attached.

[0427] A low-power digital camera 6240 can be realized by applying the information processing device described in the above embodiment to the digital camera 6240. In addition, low power consumption can reduce heat generation from a circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0428] [Video camera] The information processing device described in the above embodiment can be applied to a video camera.

[0429] FIG. 20I illustrates a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation key 6304, a lens 6305, a connection unit 6306, and the like. The operation key 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The video on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0430] When recording video captured by the video camera 6300, it is necessary to perform encoding according to the data recording format. By using the above-mentioned information processing device, the video camera 6300 can hold temporary files generated during encoding.

[0431] [ICD] The information processing device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0432] 20J is a cross-sectional schematic diagram showing an example of an ICD. An ICD body 5400 has at least a battery 5401, electronic components 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0433] The ICD body 5400 is surgically placed inside the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0434] The ICD main body 5400 has a function as a pacemaker, and performs pacing on the heart when the heart rate is out of a specified range. If the heart rate does not improve by pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with an electric shock is performed.

[0435] The ICD main body 5400 needs to constantly monitor the heart rate in order to perform pacing and electric shock appropriately. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. In addition, the ICD main body 5400 can store in the electronic component 4700 the heart rate data acquired by the sensor, the number of times pacing treatment was performed, the time, and the like.

[0436] Moreover, the antenna 5404 can receive power, which is then charged in the battery 5401. Furthermore, the ICD main body 5400 can improve safety by having multiple batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can still function, so that the ICD main body 5400 also functions as an auxiliary power source.

[0437] In addition to the antenna 5404 capable of receiving power, an antenna capable of transmitting physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0438] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0439] (Embodiment 9) In this embodiment mode, a computer having the information processing device described in the above embodiment mode will be described.

[0440] 21A is an example of a large-scale computer. The computer 9600 includes a rack 9610 and a plurality of rack-mounted computers 9620 stored therein.

[0441] The computer 9620 can have the configuration shown in the perspective view of Fig. 21B, for example. In Fig. 21B, the computer 9620 has a motherboard 9630, which has a plurality of slots 9631 and a plurality of connection terminals. A PC card 9621 is inserted into the slot 9631. In addition, the PC card 9621 has a connection terminal 9623, a connection terminal 9624, and a connection terminal 9625, which are each connected to the motherboard 9630.

[0442] The PC card 9621 shown in FIG. 21C is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like. The PC card 9621 has a board 9622. The board 9622 also has a connection terminal 9623, a connection terminal 9624, a connection terminal 9625, a semiconductor device 9626, a semiconductor device 9627, a semiconductor device 9628, and a connection terminal 9629. Note that FIG. 21C illustrates semiconductor devices other than the semiconductor device 9626, the semiconductor device 9627, and the semiconductor device 9628, but for those semiconductor devices, the following description of the semiconductor device 9626, the semiconductor device 9627, and the semiconductor device 9628 may be referred to.

[0443] The connection terminal 9629 has a shape that allows it to be inserted into a slot 9631 of a motherboard 9630, and the connection terminal 9629 functions as an interface for connecting the PC card 9621 and the motherboard 9630. An example of the standard for the connection terminal 9629 is PCIe.

[0444] The connection terminals 9623, 9624, and 9625 can be interfaces for supplying power and inputting signals to the PC card 9621, for example. They can also be interfaces for outputting signals calculated by the PC card 9621, for example. Examples of the standards for the connection terminals 9623, 9624, and 9625 include Universal Serial Bus (USB), Serial ATA (SATA), and Small Computer System Interface (SCSI). In addition, when a video signal is output from the connection terminals 9623, 9624, and 9625, examples of the standards for each include HDMI (registered trademark).

[0445] The semiconductor device 9626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 9626 and the board 9622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 9622.

[0446] The semiconductor device 9627 has a plurality of terminals, and the semiconductor device 9627 and the board 9622 can be electrically connected to each other by, for example, soldering the terminals to wiring provided on the board 9622 by a reflow method. Examples of the semiconductor device 9627 include a field programmable gate array (FPGA), a GPU, and a CPU. For example, the electronic component 4730 can be used as the semiconductor device 9627.

[0447] The semiconductor device 9628 has a plurality of terminals, and the semiconductor device 9628 and the board 9622 can be electrically connected to each other by, for example, soldering the terminals to wiring provided on the board 9622 by a reflow method. Examples of the semiconductor device 9628 include a memory device and an information processing device. For example, the electronic component 4700 can be used as the semiconductor device 9628.

[0448] The computer 9600 can also function as a parallel computer. By using the computer 9600 as a parallel computer, it is possible to perform large-scale calculations required for learning and inference of artificial intelligence, for example.

[0449] By using the semiconductor device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be made smaller, faster, or consume less power. Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, so heat generation from a circuit can be reduced. Therefore, adverse effects of the heat on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, an electronic device that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the electronic device can be improved.

[0450] Next, a configuration example of a computer system applicable to the calculator 9600 will be described. Fig. 22 is a diagram illustrating a configuration example of a computer system 1000. The computer system 1000 is configured to include software and hardware. Note that the hardware included in the computer system may be called an information processing device.

[0451] The software constituting the computer system 1000 includes an operating system including device drivers, middleware, various development environments, AI-related application programs (AI applications), and application programs unrelated to AI.

[0452] The device driver includes application programs for controlling externally connected devices such as auxiliary storage devices, display devices, and printers.

[0453] The hardware constituting the computer system 1000 includes a first processor, a second processor, a first storage device, etc. The second processor includes a second storage device.

[0454] The first arithmetic processing unit may be, for example, a central processing unit such as a Noff OS CPU. The Noff OS CPU has a storage means (for example, a non-volatile memory) using OS transistors, and has a function of holding necessary information in the storage means and stopping the power supply to the central processing unit when no operation is required. By using a Noff OS CPU as the first arithmetic processing unit, the power consumption of the computer system 1000 can be reduced.

[0455] As the second arithmetic processing device, for example, a GPU, an FPGA, or the like can be used. It is preferable to use an AI OS Accelerator as the second arithmetic processing device. The AI ​​OS Accelerator is configured using OS transistors and has an arithmetic means such as a product-sum operation circuit. The AI ​​OS Accelerator consumes less power than a general GPU, etc. By using the AI ​​OS Accelerator as the second arithmetic processing device, the power consumption of the computer system 1000 can be reduced.

[0456] It is preferable that the semiconductor device according to one embodiment of the present invention is used as the first storage device and the second storage device. The semiconductor device according to one embodiment of the present invention may have, for example, a 3D OS NAND type storage device, in which case the 3D OS NAND type storage device can function as a cache, a main memory, and a storage. In addition, the use of a 3D OS NAND type storage device makes it easier to realize a non-von Neumann type computer system.

[0457] A 3D OS NAND type storage device consumes less power than a 3D NAND type storage device using Si transistors. By using a 3D OS NAND type storage device as a storage device, the power consumption of the computer system 1000 can be reduced. In addition, since a 3D OS NAND type storage device can function as a universal memory, the number of parts required to configure the computer system 1000 can be reduced.

[0458] By configuring the semiconductor device constituting the hardware with a semiconductor device including an OS transistor, it becomes easy to monolithically integrate the hardware including the central processing unit, the arithmetic processing unit, and the memory device. By monolithically integrating the hardware, it becomes easy to further reduce power consumption as well as to reduce the size, weight, and thickness of the hardware.

[0459] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0460] (Embodiment 10) In this embodiment, a computer system different from the computer system described in the ninth embodiment will be described.

[0461] First, a conventional computer system will be described with reference to Fig. 23. Fig. 23 shows an example of the configuration of a computer system 2000 on the right side, and an example of a storage hierarchy of a computer node 2100 and a storage node 2200 on the left side.

[0462] The computer system 2000 includes a plurality of computer nodes 2100 and a storage node 2200 .

[0463] As an example, a computer system 2000 has a configuration in which a plurality of computer nodes 2100 and a storage node 2200 are capable of electrically communicating with each other via a network 2900 .

[0464] The computer node 2100, for example, includes a processor (e.g., a CPU, a GPU, a Noff OS CPU, etc.) 2110, a main memory 2120, and a storage memory 2130. The storage node 2200, for example, includes a processor 2210, a main memory 2220, and a storage memory 2230.

[0465] Moreover, the processor 2110 included in the computer node 2100 has, as an example, a core 2111, a register 2112, and a cache memory 2113. Similarly, the processor 2210 included in the storage node 2200 has, as an example, a core 2211, a register 2212, and a cache memory 2213.

[0466] For example, a flip-flop can be applied as the register 2112 and / or the register 2212. Furthermore, for example, an SRAM can be applied as the cache memory 2113 and / or the cache memory 2213.

[0467] Furthermore, for example, a DRAM or the like can be applied as the main memory 2120 included in the computer node 2100. Furthermore, for example, a NAND type storage device, a hard disk drive (HDD), or the like can be applied as the storage memory 2130 included in the computer node 2100.

[0468] 23, the top layer is a memory area included in the core 2111. Next, from the top, flip-flops, SRAM, gap area, DRAM, SCM (storage class memory) (gap area), and NAND type storage device (hard disk drive) are located in this order.

[0469] As described in the fourth embodiment, in the memory hierarchy, the higher the storage device, the faster the operating speed is required, and the lower the storage device, the larger the storage capacity and the higher the recording density are required. In particular, the storage device at the bottom level is required to retain data for a long period of time.

[0470] Next, a computer system according to one embodiment of the present invention will be described with reference to Fig. 24A. Like Fig. 23, Fig. 24A shows an example of the configuration of a computer system 2000A on the right side, and an example of the storage hierarchy of a computer node 2500A (computer node 2500B) on the left side.

[0471] The computer system 2000A in FIG. 24A includes, as an example, a plurality of computer nodes 2500A and an overall management host 2400.

[0472] As an example, the computer system 2000A has a configuration in which a plurality of computer nodes 2500A can electrically communicate with each other via the overall management host 2400. Therefore, as an example, the overall management host 2400 has a function of transmitting and receiving signals including data, commands, etc. to the plurality of computer nodes 2500A. The computer system 2000A can be called a network having the overall management host 2400 and the plurality of computer nodes 2500A.

[0473] The computer node 2500A may be, for example, the monolithic IC of Fig. 15 described in the fourth embodiment. By applying the monolithic IC of Fig. 15 as the computer node 2500A, the wiring that electrically connects the components included in the monolithic IC to each other is shortened, so that the power consumption required for transmitting a signal can be reduced.

[0474] The computer node 2500A may have the configuration shown in the block diagram of the computer node 2500B, for example. The computer node 2500B includes a processor 2600 and a storage device 2700, for example.

[0475] As the processor 2600, for example, a processor applicable to the processor 2110 included in the computer node 2100 shown in FIG. 23 can be used.

[0476] The storage device 2700 is a storage device having the functions of the main memory 2120 and the storage memory 2130 included in the computer node 2100 in Fig. 23. Specifically, the storage device 2700 may be, for example, the information processing device 50 described in the first embodiment.

[0477] As described in the first embodiment, the information processing device 50 has a memory circuit including a plurality of NAND-type strings, and has a function of changing the way some of the strings are treated as cache memory in the information processing device 50. In other words, by applying the information processing device 50 to the memory device 2700, the function of the main memory 2120 in the computer node 2100 in Fig. 23 can be operated in the memory device 2700. Therefore, unlike the computer node 2100 in Fig. 23, the computer node 2500B in Fig. 24A can be configured not to have a main memory 2120 equivalent to a DRAM.

[0478] The storage device 2700 may be, for example, a 3D OS NAND type storage device. The 3D OS NAND type storage device has, for example, a cache unit 2711 and a storage unit 2712. The cache unit 2711 corresponds to, for example, the string ST2 and string ST3 described in the operation method example of the first embodiment. The storage unit 2712 corresponds to, for example, the string ST1 described in the operation method example of the first embodiment.

[0479] Also, if the storage device 2700 is, for example, a 3D OS NAND type storage device, the storage hierarchy in the computer node 2500B is as shown on the left side of FIG. 24A. The storage hierarchy in the computer node 2500B is configured such that the hierarchy from the NAND type storage device / HDD to the DRAM in the storage hierarchy of the computer node 2100 in FIG. 23 is replaced with a 3D OS NAND type storage device. For convenience, the storage hierarchy in FIG. 24 is illustrated as "3D OS NAND memory" for each of the layers corresponding to the cache unit 2711 and the storage unit 2712, but these storage hierarchies may be combined into one hierarchy.

[0480] Also, it is preferable that the circuits included in the computer node 2500A (computer node 2500B), such as a processor and a storage device, have an OS transistor. Since OS transistors are less likely to change in transistor characteristics, field effect mobility, and the like due to temperature changes compared to transistors having silicon in their channel formation regions, the use of OS transistors in the circuits included in the computer node 2500A (computer node 2500B) can make the computer node 2500A (computer node 2500B) a device that is resistant to heat generation due to operation.

[0481] Furthermore, the computer system according to an embodiment of the present invention is not limited to the configuration shown in Fig. 24A. The computer system according to an embodiment of the present invention may have a modified configuration shown in Fig. 24A depending on the situation.

[0482] For example, in computer node 2500A (computer node 2500B) in Fig. 24A, the flip-flops provided in processor 2600 (CPU) may be replaced with NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory) (registered trademark). Note that, although computer system 2000B in Fig. 24B shows a configuration in which flip-flops are replaced with NOSRAM, a configuration in which SRAM is replaced with NOSRAM, or a configuration in which SRAM and flip-flops are replaced with NOSRAM, may also be used.

[0483] NOSRAM is a storage device having memory cells, for example, as shown in Figures 25A to 25D. The memory cells are gain cell type memory cells having two transistors and one capacitance element, and are storage elements capable of retaining data for a long period of time.

[0484] 25A includes a transistor M2, a transistor M3, and a capacitor C2. The transistor M2 includes a front gate (sometimes simply referred to as a gate) and a back gate.

[0485] Each of the transistors M2 and M3 is preferably an OS transistor. Note that the metal oxide contained in the channel formation region of the OS transistor is described in Embodiment 6.

[0486] A first terminal of the transistor M2 is electrically connected to a first terminal of the capacitor C2, a second terminal of the transistor M2 is electrically connected to a wiring WBLL, a gate of the transistor M2 is electrically connected to a wiring WL, and a back gate of the transistor M2 is electrically connected to a wiring BGLL. A second terminal of the capacitor C2 is electrically connected to a wiring CL. A first terminal of the transistor M3 is electrically connected to a wiring RBLL, a second terminal of the transistor M3 is electrically connected to a wiring SL, and a gate of the transistor M3 is electrically connected to the first terminal of the capacitor C2.

[0487] The wiring WBLL functions as a write bit line, the wiring RBLL functions as a read bit line, and the wiring WL functions as a word line. The wiring CL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance C2. For example, during data retention, it is preferable that a low-level potential (sometimes called a reference potential) is applied to the wiring CL, and when writing data and when reading data, it is preferable that a high-level potential is applied to the wiring CL.

[0488] The wiring BGLL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGLL, the threshold voltage of the transistor M2 can be increased or decreased.

[0489] The method of writing data is as follows: first, a high-level potential is applied to the wiring SL. Next, a high-level potential is applied to the wiring WL to turn on the transistor M2 and establish electrical continuity between the wiring WBLL and the first terminal of the capacitor C2. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBLL, and the potential is written to the first terminal of the capacitor C2 and the gate of the transistor M3. After that, a low-level potential is applied to the wiring WL to turn off the transistor M2, thereby holding the potential of the first terminal of the capacitor C2 and the potential of the gate of the transistor M3.

[0490] As a method of reading data, first, a high-level potential is applied to the wiring SL. Since the current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3, the potential held in the first terminal of the capacitor C2 (or the gate of the transistor M3) can be read by reading the potential of the wiring RBLL connected to the first terminal of the transistor M3. In other words, the information written in this memory cell can be read from the potential held in the first terminal of the capacitor C2 (or the gate of the transistor M3).

[0491] Moreover, memory cells that can be applied to the NOSRAM of Fig. 24B are not limited to memory cells 1440. Depending on the situation, the circuit configuration can be changed.

[0492] For example, the memory cell included in the semiconductor device described in the above embodiment may have a memory cell configuration as shown in FIG. 25B. In the memory cell 1450, the back gate of the transistor M2 is electrically connected to the wiring WL instead of the wiring BGLL. With this configuration, the same potential as that of the gate of the transistor M2 can be applied to the back gate of the transistor M2, so that the current flowing through the transistor M2 can be increased when the transistor M2 is on.

[0493] For example, the memory cell included in the semiconductor device described in the above embodiment may be a memory cell including a transistor M2 that does not have a backgate. An example of a circuit configuration of the memory cell is shown in FIG. 25C. The memory cell 1460 is configured such that a backgate is not provided from the transistor M2 of the memory cell 1440. Note that by applying the memory cell 1460 to the semiconductor device, the manufacturing process of the semiconductor device can be shortened compared to the memory cell 1440 and the memory cell 1450 because the transistor M2 does not have a backgate.

[0494] Alternatively, for example, the wiring WBLL and the wiring RBLL may be integrated into a single wiring BL. An example of the circuit configuration of the memory cell is shown in FIG. 25D. The memory cell 1470 has a configuration in which the wiring WBLL and the wiring RBLL of the memory cell 1440 are integrated into a single wiring BL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are electrically connected to the wiring BL. In other words, the memory cell 1470 has a configuration in which the write bit line and the read bit line operate as a single wiring BL.

[0495] Note that the memory cells shown in Figures 25A to 25D can function as a memory device by being arranged in a matrix. For example, when the memory cells 1440 in Figure 25A are arranged in a matrix, the memory device shown in Figure 25E can be formed.

[0496] The memory device shown in FIG. 25E has a cell array CA, a circuit WBD, a circuit CD, a circuit WD, and a circuit RBD.

[0497] The cell array CA has, for example, a plurality of memory cells 1440 arranged in a matrix, as described above.

[0498] The circuit WBD is electrically connected to the wiring WBLL. The circuit WBD functions as, for example, a write circuit for writing data to a memory cell included in the cell array CA.

[0499] The circuit WD is electrically connected to the wiring WL and functions as, for example, a selection circuit for selecting a memory cell to which data is to be written.

[0500] The circuit RBD is electrically connected to the wirings RBLL and SL. The circuit RBD functions as, for example, a read circuit for reading data from a memory cell included in the cell array CA.

[0501] The circuit CD is electrically connected to the wiring CL. The circuit CD functions as, for example, a selection circuit for selecting a memory cell from which data is to be read.

[0502] Note that the circuit configuration of the memory device shown in FIG. 25E is just an example, and the circuit configuration can be changed as appropriate.

[0503] Furthermore, a computer system according to an embodiment of the present invention may be a computer system having a modified configuration of the computer system 2000 shown in FIG.

[0504] For example, computer system 2000C shown in FIG. 26 is configured such that in computer system 2000 of FIG. 23, processor 2110 (processor 2210) and storage memory 2130 (storage memory 2230) are electrically connected without going through main memory 2120 (main memory 2220) which corresponds to DRAM.

[0505] In particular, it is preferable that the storage memory 2130 (storage memory 2230) is the storage device 2700 described in the computer system 2000A of FIG. 24A, that is, the information processing device 50 described in the first embodiment.

[0506] By configuring computer node 2100 (storage node 2200) as shown in FIG. 26, it is possible to electrically connect processor 2110 (processor 2210) and storage device 2700 (storage memory 2130 or storage memory 2230) without going through main memory 2120 (main memory 2220) which corresponds to DRAM, and it is possible to operate computer system 2000C without main memory 2120 (main memory 2220).

[0507] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. [Explanation of symbols]

[0508] ST1, ST2, ST3: String, L[1], L[2], L[n]: Memory cell, M[1], M[2], M[n]: Memory cell, N[1], N[2], N[n]: Memory cell, SL1: Wiring, SL2: Wiring, SL3: Wiring, BL1: Wiring, BL2: Wiring, BL3: Wiring, ISG: Signal, OSG: Signal, DT: Data, STP1: Step, STP2: Step, STP3: Step, STP4: Step, STP5: Step, STP6: Step, STP7: Step, STP8: Step, MC[1]: Memory cell, MC[2]: Memory cell, M C[n]: memory cell,MC[1,1]: memory cell,MC[j,1]: memory cell,MC[n,1]: memory cell,MC[1,i]: memory cell,MC[j,i]: memory cell,MC[n,i]: memory cell,MC[1,m]: memory cell,MC[j,m]: memory cell,MC[n,m]: memory cell,N1: node,N2: node,RWL[1]: wiring,RWL[2]: wiring,RWL[j]: wiring,RWL[n]: wiring,WWL[1]: wiring,WWL[2]: wiring,WWL[j]: wiring,WWL[n]: wiring,WBL: wiring,WBL[1]: wiring,W BL[i]: wiring, WBL[m]: wiring, RBL: wiring, RBL[1]: wiring, RBL[i]: wiring, RBL[m]: wiring, BGL: wiring, BGL[1]: wiring, BGL[i]: wiring, BGL[m]: wiring, WTr: transistor, RTr: transistor, CS: capacitance, BLK_1: block, BLK_h: block, BLK_k: block, BLK_2: block, BLK_3: block, MC[1]_1: memory cell, MC[j]_1: memory cell, MC[n]_1: memory cell, MC[1]_h: memory cell, MC[j]_h: memory cell, MC[ n]_h: memory cell, MC[1]_k: memory cell, MC[j]_k: memory cell, MC[n]_k: memory cell, MC[2]_1: memory cell, MC[3]_1: memory cell, MC[1]_2: memory cell, MC[2]_2: memory cell, MC[3]_2: memory cell, MC[1]_3: memory cell, MC[2]_3: memory cell, MC[3]_3: memory cell, RWL[1]_1: wiring, RWL[j]_1: wiring, RWL[n]_1: wiring, RWL[1]_h: wiring, RWL[j]_h: wiring, RWL[n]_h: wiring, RWL[1]_k: wiring,RWL[j]_k: wiring, RWL[n]_k: wiring, RWL[2]_1: wiring, RWL[3]_1: wiring, RWL[1]_2: wiring, RWL[2]_2: wiring, RWL[3]_2: wiring, RWL[1]_3: wiring, RWL[2]_3: wiring, RWL[3]_3: wiring, WWL[1]_1: wiring, WWL[j]_1: wiring, WWL[n]_1: wiring, WWL[1]_h: wiring, WWL[j]_h: wiring, WWL[n]_h: wiring, WWL[1]_k: wiring, WWL[j]_k: wiring, WWL[n]_k: wiring, WWL[2]_1: wiring, WWL[3]_1: Wiring,WWL[1]_2:Wiring,WWL[2]_2:Wiring,WWL[3]_2:Wiring,WWL[1]_3:Wiring,WWL[2]_3:Wiring,WWL[3]_3:Wiring,RBL_1:Wiring,RBL_h:Wiring,RBL_k:Wiring,RBL_2:Wiring,RBL_3:Wiring,WBL_1:Wiring,WBL_h:Wiring,WBL_k:Wiring,WBL_2:Wiring,WBL_3:Wiring,LN1:Wiring,LN2:Wiring,BTr_1:Transistor,BTr_h:Transistor,BTr_k:Transistor,BTr_2:Transistor,BTr_3:Transistor,STr_1: Transistor, STr_h: transistor, STr_k: transistor, STr_2: transistor, STr_3: transistor, BD: motherboard, BSH: bus wiring, SBT: semiconductor substrate, LGC: circuit layer, STR: memory layer, OSC: circuit layer, ME1: conductor, ME2: conductor, ME3: conductor, LT1[1]: latch circuit, LT1[2]: latch circuit, LT1[3]: latch circuit, LT1[z]: latch circuit, LT2[1]: latch circuit, LT2[2]: latch circuit, LT2[3]: latch circuit, LT2[z]: latch circuit, DA: data, CL K: wiring, ENL: wiring, STG[1]: string, STG[2]: string, STG[3]: string, STG[z]: string, STG: string, M2: transistor, M3: transistor, C2: capacitance, WBLL: wiring, RBLL: wiring, SL: wiring, BL: wiring, WL: wiring, CL: wiring, BGLL: wiring, CA: cell array, WBD: circuit, WD: circuit, CD: circuit, RBD: circuit, 10: arithmetic processing unit, 11: register, 20: SRAM, 30: main memory, 40: storage, 50: information processing unit, 60: interface,70: Processing unit, 80: Storage device, 90: Wiring, 100: Storage unit, 111: Insulator, 112: Insulator, 113: Insulator, 114: Insulator, 115: Insulator, 116: Insulator, 117: Insulator, 121: Insulator, 122: Insulator, 131: Insulator, 132: Insulator, 133: Insulator, 141: Semiconductor, 142: Semiconductor, 143: Semiconductor, 151: Conductor, 152: Conductor, 153: Conductor, 154: Conductor, 155: Conductor, 156: Conductor, 200: Control unit, 211: Insulator, 212: Insulator, 213: Insulator, 214: Insulator, 215: Insulator, 21 6: insulator, 221: conductor, 222: conductor, 223: conductor, 231: semiconductor, 232: semiconductor, 240: insulator, 241: insulator, 242: insulator, 243: insulator, 250: conductor, 251: conductor, 252: conductor, 253: conductor, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 35 6: conductor, 360: insulator, 382: insulator, 384: insulator, 386: conductor, 700: transistor, 800: transistor, 900: transistor, 1000: computer system, 1196: memory unit, 1197: controller, 1198: bus interface, 1440: memory cell, 1450: memory cell, 1460: memory cell, 1470: memory cell, 2000: computer system, 2000A: computer system, 2000B: computer system, 2000C: computer system, 2100: computer node, 2110: processor, 2111: core, 2112: register, 2113: cache memory, 2120: main memory, 2130: storage memory, 2200: storage node, 2210: processor, 2211: core, 2212: register, 2213: cache memory, 2220: main memory, 2230: storage memory, 2400: overall management host, 2500A: computer node, 2500B: computer node, 2600: processor, 2700: storage device, 2711: cache unit, 2712: storage unit, 2900: network,4700: electronic component, 4702: printed circuit board, 4704: mounting board, 4710: semiconductor device, 4714: wire, 4730: electronic component, 4731: interposer, 4732: package board, 4733: electrode, 4735: semiconductor device, 4800: semiconductor wafer, 4800a: chip, 4801: wafer, 4801a: wafer, 4802: circuit section, 4803: spacing, 4803a: spacing, 5200: mobile game machine, 5201: housing, 5202: display unit, 5203: button, 5300: desktop information terminal, 5301: main body, 5302: display, 5303: keyboard, 5400: ICD main body, 5401: battery, 5402: wire, 5403: wire, 5404: antenna, 5405: subclavian vein, 5406: superior vena cava, 5500: information terminal, 5510: housing, 5511: display unit, 5700: automobile, 5800: electric refrigeration Refrigerator, 5801: housing, 5802: refrigerator door, 5803: freezer door, 5900: information terminal, 5901: housing, 5902: display unit, 5903: operation button, 5904: operator, 5905: band, 6240: digital camera, 6241: housing, 6242: display unit, 6243: operation button, 6244: shutter button, 6246: lens, 6300: video camera, 6301: first housing, 6302: second housing, 6303: front display unit, 6304: operation keys, 6305: lens, 6306: connection unit, 7520: main body, 7522: controller, 9600: computer, 9610: rack, 9620: computer, 9621: PC card, 9622: board, 9623: connection terminal, 9624: connection terminal, 9625: connection terminal, 9626: semiconductor device, 9627: semiconductor device, 9628: semiconductor device, 9629: connection terminal, 9630: motherboard, 9631: slot,

Claims

1. A processor having a memory unit, the storage unit has a NAND string ST1, a NAND string ST2, and a NAND string ST3, The NAND string ST1 includes memory cells L[1] to L[n] (n is an integer of 1 or more), The NAND string ST2 has memory cells M[1] to M[n], The NAND string ST3 has memory cells N[1] to N[n], A method for operating a processor having steps STP1 to STP8, The step STP1 includes a step of writing data for rewriting the memory cell L[m] (m is an integer of 1 to n) to the memory cell N[p] (p is an integer of 1 to n), The step STP2 includes a step of reading data stored in each of the memory cells L[1] to L[n] (excluding the memory cell L[m]), The step STP3 includes a step of copying the data read in the step STP2 to the memory cells M[1] to M[n], The step STP4 includes a step of erasing data stored in the memory cells L[1] to L[n] (excluding the memory cell L[m]), The step STP5 includes a step of reading data for rewriting from the memory cell N[p], The step STP6 includes a step of writing the data read in the step STP5 to the memory cell L[m], The step STP7 includes a step of reading the data copied in the step STP3, The method for operating an arithmetic processing device includes a step of writing the data read out in the step STP7 sequentially to the memory cells L[1] to L[n] (excluding memory cell L[m]).

2. A processor having a memory unit, the storage unit has a NAND string ST1, a NAND string ST2, and a NAND string ST3, The NAND string ST1 includes memory cells L[1] to L[n] (n is an integer of 1 or more), The NAND string ST2 has memory cells M[1] to M[n], The NAND string ST3 has memory cells N[1] to N[n], A method for operating a processor having steps STP1 to STP8, The step STP1 includes a step of writing data for rewriting the memory cell L[m] (m is an integer of 1 to n) to the memory cell N[p] (p is an integer of 1 to n), The step STP2 includes a step of reading data stored in each of the memory cells L[1] to L[q] (excluding the memory cell L[m], where q is an integer between 1 and m), The step STP3 includes a step of copying the data read in the step STP2 to the memory cells M[1] to M[q], The step STP4 includes a step of erasing data stored in the memory cells L[1] to L[q] (excluding the memory cell L[m]), The step STP5 includes a step of reading the rewrite data from the memory cell N[p], The step STP6 includes a step of writing the data read in the step STP5 to the memory cell L[m], The step STP7 includes a step of reading the data copied in the step STP3, The method for operating an arithmetic processing device includes a step of writing the data read out in the step STP7 sequentially to the memory cells L[1] to L[q] (excluding memory cell L[m]).

Images