Flexible circuit board and chip package including the same

Abstract

To provide a flexible circuit board for all-in-one COF capable of mounting a plurality of chips on one substrate, a chip package including the same, and an electronic device including the flexible circuit board.SOLUTION: A flexible circuit board according to an embodiment of the present invention includes: a substrate; a first wiring pattern layer disposed on a first surface of the substrate; a second wiring pattern layer disposed on a second surface opposite the first surface of the substrate; a first dummy pattern part disposed on the second surface of the substrate on which the second wiring pattern layer is not disposed; a first protective layer disposed on the first wiring pattern layer; and a second protective layer disposed on the second wiring pattern layer and the first dummy pattern part. At least a part of the first dummy pattern part overlaps with the first wiring pattern layer in a vertical direction.SELECTED DRAWING: Figure 5a

Description

[Technical field]

[0001] The present invention relates to a flexible circuit board for all-in-one COF and a chip package including the same. This is related to the page.

[0002] Specifically, the present invention relates to a flexible substrate that can mount different types of chips on a single substrate. and a chip package including the same. [Background technology]

[0003] Recently, various electronic products have become thinner, smaller, and lighter. Various researches are being conducted to mount semiconductor chips at high density in a small area.

[0004] Among them, the COF (Chip On Film) method uses a flexible substrate, so it is The present invention can be applied to both flat panel displays and flexible displays. That is, the COF method is attracting attention because it can be applied to a variety of wearable electronic devices. In addition, the COF method can realize fine peaches, so it is not possible to achieve high resolution due to an increase in the number of pixels. It can be used to realize (QHD) displays.

[0005] COF (Chip On Film) is a technology that attaches semiconductor chips to a thin film-type flexible circuit board. For example, a semiconductor chip is an integrated circuit (IC) chip. The chip may be a chip or a large scale integrated circuit (LSI) chip. can.

[0006] Meanwhile, in order to meet the recent trend of making electronic products smaller, thinner and lighter, As a mounting technology for conductor chips, various COF packaging technologies using flexible substrates are available. has been proposed. Summary of the Invention [Problem to be solved by the invention]

[0007] This invention is an all-in-one COF flexible board that can mount multiple chips on one board. and a chip package including the same, and an electronic device including the same. Let us assume that.

[0008] The present invention is an all-in-one solder mask that can eliminate pinholes that occur during solder resist printing. Flexible circuit board for COF, chip package including the same, and electronic device including the same Trying to provide the device.

[0009] The present invention is an all-in-one design system that allows the design of products to be made taking into account the solder resist printing process. Flexible circuit board for in-one COF and chip package including the same, The company aims to provide electronic devices that

[0010] The technical problem to be solved by the proposed embodiment is limited to the technical problem mentioned above. Other technical problems not mentioned, but not limited to, are not limited to the implementation proposed in the following description. This should be clearly understood by those skilled in the art to which the embodiments pertain. [Means for solving the problem]

[0011] A flexible circuit board according to an embodiment of the present invention includes a substrate and a first surface of the substrate. a first wiring pattern layer disposed on a second surface of the substrate opposite to the first surface; a second wiring pattern layer on the substrate, and a portion of the substrate on which the second wiring pattern layer is not disposed. a first dummy pattern portion disposed on the second surface; and a second dummy pattern portion disposed on the first wiring pattern layer. a first protective layer disposed on the second wiring pattern layer and the first dummy pattern portion; and a second protective layer formed on the first dummy pattern portion. It overlaps the pattern layer vertically.

[0012] Also, a wiring pattern layer is disposed on the first surface of the substrate on which the first wiring pattern layer is not disposed. a second dummy pattern portion at least a portion of which vertically overlaps the second wiring pattern layer; Further includes:

[0013] The first dummy pattern portion has the same width as the first wiring pattern layer, and one end It is disposed on the same vertical line as one end of the first wiring pattern layer.

[0014] The first dummy pattern portion has a width greater than that of the first wiring pattern layer, and is closer to the edge of the substrate than one end of the first wiring pattern layer.

[0015] Moreover, the first surface is an upper surface of the substrate, and the second surface is a lower surface of the substrate, The first dummy pattern portion is a first dummy pattern portion arranged at the leftmost side of the first wiring pattern layer. It is placed to the left of the wiring pattern layer.

[0016] The second dummy pattern portion is disposed on the rightmost side of the second wiring pattern layer. The second wiring pattern layer is disposed to the right of the first wiring pattern layer.

[0017] Also, a first plating layer including tin (Sn) arranged on the first wiring pattern layer; and a second plating layer including tin (Sn) disposed on the second wiring pattern layer. The dummy pattern portion includes a first dummy pattern layer corresponding to the second wiring pattern layer, and and a second dummy pattern layer corresponding to the second plating layer, the second dummy pattern portion comprising: A third dummy pattern layer corresponding to the first wiring pattern layer and a third dummy pattern layer corresponding to the first plating layer and a fourth dummy pattern layer.

[0018] On the other hand, the package according to the embodiment is an all-in-one COF flexible circuit board, A substrate, a conductive pattern portion disposed on the substrate, and a dummy pattern portion disposed on the substrate. a pattern portion, a region on the conductive pattern portion, and a region on the dummy pattern portion; and a protective portion disposed on the first surface of the substrate, the conductive pattern portion being disposed on the first surface of the substrate. a first wiring pattern layer formed on the first wiring pattern layer; and a first plating layer disposed on the first wiring pattern layer; a second wiring pattern layer disposed on a second surface of the substrate opposite to the first surface; a second plating layer disposed on the second wiring pattern layer, The tin (Sn) content of the plating layer in the second open region of the protective layer is A first chip disposed in the first open area has a tin (Sn) content greater than that of the plating layer. and a second chip disposed in the second open area, the dummy pattern portion comprising: The second wiring pattern layer is disposed on the second surface of the substrate on which the second wiring pattern layer is not disposed. a first dummy pattern portion at least partially overlapping the first wiring pattern layer in a vertical direction; A first wiring pattern layer is disposed on the first surface of the substrate on which the first wiring pattern layer is not disposed, and at least The second dummy pattern portion also includes a portion vertically overlapping the second wiring pattern layer.

[0019] Moreover, the first surface is an upper surface of the substrate, and the second surface is a lower surface of the substrate, The first dummy pattern portion is a first dummy pattern portion arranged at the leftmost side of the first wiring pattern layer. The second dummy pattern portion is disposed on the left side of the wiring pattern layer. The second wiring pattern layer is disposed to the right of the second wiring pattern layer, which is disposed at the rightmost side of the first wiring pattern layer.

[0020] The first chip is a drive IC chip, and the second chip is , Diode chip, Power supply IC chip, Touch sensor IC chip, MLCC chip, B All-in-one capacitors including at least one of GA chips and chip capacitors Includes flexible circuit boards for OF.

[0021] On the other hand, an electronic device according to an embodiment of the present invention includes a substrate and a conductive layer disposed on the substrate. a conductive pattern portion, a dummy pattern portion disposed on the substrate, and the conductive pattern portion a protective portion disposed partially on a region on the substrate, a first wiring pattern layer disposed on the first surface of the plate; and a second wiring pattern layer disposed on the first wiring pattern layer. a first plating layer disposed on a second surface of the substrate opposite the first surface; a wiring pattern layer and a second plating layer disposed on the second wiring pattern layer, The tin (Sn) content of the plating layer in the first open region of the protective layer is 2. An all-in-one plating layer containing more tin (Sn) than the plating layer in the open area A flexible circuit board for COF, and one end of the all-in-one flexible circuit board A display panel to be connected to the one end of the all-in-one flexible circuit board and a main board connected to the other end opposite to the dummy pattern part. The second wiring pattern layer is disposed on the second surface of the substrate on which the second wiring pattern layer is not disposed, and at least a first dummy pattern portion, a part of which vertically overlaps with the first wiring pattern layer; A wiring pattern layer is disposed on the first surface of the substrate on which the wiring pattern layer is not disposed, and at least A second dummy pattern portion is included, a portion of which overlaps the second wiring pattern layer in the vertical direction.

[0022] In addition, a first connection portion and a second connection portion are formed on the one region and the other region of the conductive pattern portion, respectively. A second connection portion is disposed, a first chip is disposed on the first connection portion, and A second chip is placed on top.

[0023] The display panel and the main board are disposed to face each other. The all-in-one flexible circuit board includes a display panel and a main board. The plate is folded and placed between the plate and the base. Effect of the Invention

[0024] According to an embodiment of the present invention, a first chip and a second chip of different types are integrated into one frame. All-in-one CO that can be mounted on flexible circuit boards and has improved reliability Flexible circuit board chip packages for F can be provided.

[0025] In addition, according to an embodiment of the present invention, one all-in-one COF flexible circuit is provided. The display panel and main board are directly connected by a substrate, and the The size and thickness of the flexible circuit board that transmits the signals to the main board is reduced. This allows for more space for other components and / or battery space. It is possible.

[0026] In addition, according to the embodiment of the present invention, a plurality of PCBs (printed circuit boards) are connected. Since no additional wiring is required, the convenience of the process and the reliability of the electrical connection are improved, thereby All-in-one COF flexible cable suitable for electronic devices with high resolution display A flexible circuit board can be provided.

[0027] According to the embodiment of the present invention, a circuit pattern corresponding to the circuit pattern arranged on the first surface of the substrate is formed. A dummy pattern is arranged on the second surface of the substrate so as to form a dummy pattern on the second surface of the substrate. A dummy pattern is disposed on the first surface of the substrate so as to correspond to the wiring pattern. Solder resist generated during printing of the solder resist on the first or second surface of the board This can solve the problems of the paste not being applied and pinholes. [Brief description of the drawings]

[0028] [Figure 1a] 1 is a cross-sectional view of an electronic device having a display unit including a conventional PCB. [Figure 1b] FIG. 1b is a cross-sectional view of the PCB of FIG. 1a in a folded configuration; [Figure 1c] FIG. 1b is a plan view of the PCB according to FIG. 1a in a folded configuration; [Figure 2a] FIG. 1 is a cross-sectional view of an electronic device having a display unit including a flexible circuit board for all-in-one COF according to an embodiment. [Figure 2b]FIG. 2b is a cross-sectional view of the all-in-one COF flexible circuit board of FIG. 2a in a folded state. [Figure 2c] FIG. 2b is a plan view of the all-in-one COF flexible circuit board of FIG. 2a in a folded state. [Figure 3a] FIG. 2 is a cross-sectional view of a chip package including a double-sided all-in-one COF flexible circuit board according to an embodiment. [Figure 3b] FIG. 2 is another cross-sectional view of a chip package including a double-sided all-in-one COF flexible circuit board according to an embodiment. [Figure 4a] 11 is a cross-sectional view of a flexible circuit board not including a dummy pattern portion according to a comparative example. [Figure 4b] 2 is a cross-sectional view of a flexible circuit board including a lower dummy pattern portion DP1 according to an embodiment of the present invention. [Figure 5a] 4A to 4C are diagrams showing various modified examples of the lower dummy pattern portion DP1 shown in FIG. 4b. [Figure 5b] 4A to 4C are diagrams showing various modified examples of the lower dummy pattern portion DP1 shown in FIG. 4b. [Figure 5c] 4A to 4C are diagrams showing various modified examples of the lower dummy pattern portion DP1 shown in FIG. 4b. [Figure 5d] 4A to 4C are diagrams showing various modified examples of the lower dummy pattern portion DP1 shown in FIG. 4b. [Figure 6] 2 is a diagram showing an upper dummy pattern part DP2 according to an embodiment of the present invention. [Figure 7a] FIG. 2 is another cross-sectional view of the double-sided all-in-one COF flexible circuit board according to the embodiment. [Figure 7b] FIG. 7b is a cross-sectional view of a chip package including a double-sided all-in-one COF flexible circuit board according to FIG. 7a. [Figure 8] FIG. 2 is another cross-sectional view of a chip package including a double-sided all-in-one COF flexible circuit board according to an embodiment. [Figure 9]FIG. 2 is an enlarged cross-sectional view of one area of ​​the double-sided all-in-one COF flexible circuit board according to the embodiment. [Figure 10] FIG. 7b is a plan view of the flexible circuit board for double-sided all-in-one COF according to FIG. 7a. [Figure 11] FIG. 7b is a bottom view of the flexible circuit board for double-sided all-in-one COF according to FIG. 7a. [Figure 12a] FIG. 7b is a schematic plan view of a chip package including a flexible circuit board for double-sided all-in-one COF according to FIG. [Figure 12b] FIG. 7b is a schematic plan view of a chip package including a flexible circuit board for double-sided all-in-one COF according to FIG. [Figure 13a] 7B is a diagram showing a process for manufacturing the flexible circuit board for double-sided all-in-one COF of FIG. 7A into a chip package including the flexible circuit board for double-sided all-in-one COF of FIG. 7B. [Figure 13b] 7B is a diagram showing a process for manufacturing the flexible circuit board for double-sided all-in-one COF of FIG. 7A into a chip package including the flexible circuit board for double-sided all-in-one COF of FIG. 7B. [Figure 14a] 7B is a diagram showing a process for manufacturing the flexible circuit board for double-sided all-in-one COF of FIG. 7A into a chip package including the flexible circuit board for double-sided all-in-one COF of FIG. 7B. [Figure 14b] 7B is a diagram showing a process for manufacturing the flexible circuit board for double-sided all-in-one COF of FIG. 7A into a chip package including the flexible circuit board for double-sided all-in-one COF of FIG. 7B. [Figure 15a] 7B is a diagram showing a process for manufacturing the flexible circuit board for double-sided all-in-one COF of FIG. 7A into a chip package including the flexible circuit board for double-sided all-in-one COF of FIG. 7B. [Figure 15b] 7B is a diagram showing a process for manufacturing the flexible circuit board for double-sided all-in-one COF of FIG. 7A into a chip package including the flexible circuit board for double-sided all-in-one COF of FIG. 7B. [Figure 16] FIG. 16 is a cross-sectional view of a chip package including the double-sided all-in-one COF flexible circuit board of FIG. [Figure 17] 1 is a diagram of various electronic devices including flexible circuit boards for all-in-one COF. [Figure 18] 1 is a diagram of various electronic devices including flexible circuit boards for all-in-one COF. [Figure 19a] 1 is a diagram of various electronic devices including flexible circuit boards for all-in-one COF. [Figure 19b] 1 is a diagram of various electronic devices including flexible circuit boards for all-in-one COF. [Figure 19c] 1 is a diagram of various electronic devices including flexible circuit boards for all-in-one COF. [Figure 20] 1 is a diagram of various electronic devices including flexible circuit boards for all-in-one COF. [Figure 21] 1 is a diagram of various electronic devices including flexible circuit boards for all-in-one COF. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] In the description of the embodiments, each layer, region, pattern or structure is a substrate, each layer, region, package, A statement that a part is formed "on" or "under" a part or pattern refers directly to the part. This includes layers that are formed directly or through other layers. The following description will be given with reference to the drawings.

[0030] Also, when a part is said to be "connected" to another part, this is called a "direct connection." This does not only apply when the two parts are connected to each other, but also when they are "indirectly connected" by placing other parts between them. In addition, when a part is described as "comprising" a certain component, this is not specifically stated to be the opposite. Unless otherwise specified, the present invention does not exclude other components, but may further include other components. It means it's possible.

[0031] In the drawings, the thickness and size of each layer, region, pattern or structure may be changed for clarity of description and The dimensions may be modified for convenience and do not reflect the actual size.

[0032] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0033] A PCB (printed circuit board) according to a comparative example will be described with reference to FIGS. 1a to 1c. .

[0034] An electronic device having a display unit transmits the signal from the display panel to the main board. At least two PCBs are required to transmit the signal.

[0035] The electronic device including the display unit according to the comparative example has at least two PCBs. It can be.

[0036] The electronic device including a display unit according to the comparative example has a first PCB 10 and a second PCB 2 May contain 0.

[0037] The first PCB 10 may be a flexible printed circuit board (FPCB). Specifically, the first PCB 10 is a FPCB for COF (Chip On Film). The first PCB 10 is a FPCB for COF on which the first chip C1 is mounted. More specifically, the first PCB 10 includes a drive IC chip ) for placing the COF.

[0038] The second PCB 20 may be a FPCB. 0 is a FPCB for arranging a second chip C2 of a different type from the first chip C1. Here, the second chip C2 may be a drive IC chip or Other than the drive IC chip, other chips, semiconductor elements, and so on It means various chips that are placed on the FPCB for electrical connection, such as a socket The second PCB 20 is a FPCB for arranging a plurality of second chips C2. For example, the second PCB 20 may include a plurality of second chips C of different types. 2a, C2b.

[0039] The first PCB 10 and the second PCB 20 may have different thicknesses. The thickness of the second PCB 20 is smaller than the thickness of the first PCB 10. For example, the first PCB 10 may have a thickness of about 20 μm to 100 μm. The second PCB 20 may have a thickness of about 100 μm to 200 μm. For example, the sum t1 of the thicknesses of the first PCB 10 and the second PCB is 200 μm to 2 50 μm.

[0040] The electronic device having a display unit according to the comparative example has a display panel and a main button. Since a first and second PCB are required between the boards, the overall thickness of the electronic device increases. Specifically, the electronic device having the display unit according to the comparative example has a Since stacked first and second PCBs are required, the overall thickness of the electronic device increases. This will be the case.

[0041] The first PCB 10 and the second PCB 20 are formed in different processes. For example, the first PCB 10 may be manufactured by a ROLL to ROLL process. The second PCB 20 may be manufactured in a sheet manner.

[0042] The first PCB 10 and the second PCB 20 have different types of chips on them. The pitch of the conductive pattern parts to connect the chips is For example, the conductive pattern portion disposed on the second PCB 20 may be different from the conductive pattern portion. The pitch is smaller than the pitch of the conductive pattern portion disposed on the first PCB 10. For example, the conductive layer 24 may have a larger spacing than the conductive layer 24 disposed on the second PCB 20. The pitch of the functional pattern is 100 μm or more, and the functional pattern is disposed on the first PCB 10. The pitch of the conductive pattern portions may be less than 100 μm.

[0043] Specifically, the first P has conductive pattern portions arranged at fine pitches. CB10 is manufactured through the roll to roll process, which makes the process more efficient and reduces process costs. On the other hand, a conductive pattern portion arranged at intervals of 100 μm or more can be used. The second PCB 20 is difficult to handle in a roll to roll process, so it is manufactured using a sheet process. It was common for

[0044] The first and second PCBs according to the comparative example are formed in different processes, so the process efficiency is Decreases.

[0045] In addition, the chip packages including the flexible circuit boards according to the comparative examples are of different types. Since it is difficult to place the chips on one substrate, the first and second PCs are separately B is required.

[0046] In addition, the chip packages including the flexible circuit boards according to the comparative examples are of different types. However, there is a problem in that it is difficult to connect the above chips on a single substrate.

[0047] In addition, the flexible circuit board according to the comparative example has an upper circuit pattern and a lower circuit pattern. The frame is designed taking into consideration only the signal transmission characteristics of each of the comparative examples. Flexible circuit boards are made of a protective layer (e.g., solder resist) that is placed on the outermost layer of the board. The upper and lower circuit patterns are printed without considering the reliability of the printing process. Therefore, in the flexible circuit board according to the comparative example, the protective layer is Pinholes due to positional differences between the upper and lower circuit patterns during the printing process There is a problem that occurs.

[0048] On the other hand, the first and second PCBs are placed between the conventional display panel and the main board. will be done.

[0049] To control, process or transmit the R, G, B signals generated by the display panel 30 Then, the first PCB 10 is connected to the display panel 30, and the first PCB 10 is again connected to the second The second PCB 20 is connected to the main board 40 .

[0050] One end of the first PCB 10 is connected to a display panel 30. The panel 30 is connected to the first PCB 10 by an adhesive layer 50 .

[0051] The other end of the first PCB 10 opposite to the one end is connected to a second PCB 20. The first PCB 10 is connected to the second PCB 20 by the adhesive layer 50 .

[0052] One end of the second PCB 20 is connected to the first PCB 10. The other end opposite to the one end is connected to the main board 40. The second PCB 20 is The adhesive layer 50 connects the main board 40 .

[0053] The electronic device having a display unit according to the comparative example has the display panel 30 and Between the first PCB 10, between the first PCB 10 and the second PCB 20, A separate adhesive layer 50 is required between the B20 and the main board 40. The electronic device having the display unit according to the comparative example requires a large number of adhesive layers. The reliability of electronic devices is reduced due to poor connection of the adhesive layer. The adhesive layer disposed between the first PCB 10 and the second PCB 20 is The thickness of the device is increased.

[0054] 1b and 1c, a first P that serves as a housing in an electronic device according to a comparative example is The CB 10, the second PCB 20, the display panel 30, and the main board 40 are described. .

[0055] FIG. 1b is a cross-sectional view of the PCB of FIG. 1a in a folded configuration, and FIG. 1c is , It is a plan view of the lower surface of FIG. 1b.

[0056] The display panel 30 and the main board 40 are arranged to face each other. Opposite Between the display panel 30 and the main board 40 arranged to face each other, there is a first PCB 10 including a bending region. is arranged.

[0057] One region of the first PCB 10 is bent, and the first chip C1 is arranged in the non-bent region. is arranged.

[0058] Also, the second PCB 20 is arranged to face the display panel 30. The second chip C2 is arranged in the non-bent region of the second PCB 20. is arranged.

[0059] Referring to FIG. 1c, in the comparative example, since a plurality of substrates are required, the length L1 in one direction is the sum of the lengths of the respective first PCB 10 and the second PCB 20. The length L1 in one direction of the first PCB 10 and the second PCB 20 is the sum of the length of the short side of the first PCB 10 and the length of the short side of the second PCB 20. As an example, the length L1 in one direction of the first PCB 10 and the second PCB 20 can be 30 mm to 40 mm. However, depending on the type of chip and the type of electronic device for mounting, the length L1 in one direction of the first PCB 10 and the second PCB 20 can have various sizes. can have. However, depending on the type of chip and the type of electronic device for mounting, the length L1 in one direction of the first PCB 10 and the second PCB 20 can have various sizes. Since the electronic device according to the comparative example requires a plurality of PCBs, the space for mounting other components or the space for arranging the battery 60 is reduced. can have.

[0060] Since the electronic device according to the comparative example requires a plurality of PCBs, the space for mounting other components or the space for arranging the battery 60 is reduced. for mounting other components or the space for arranging the battery 60 is reduced.

[0061] Recently, electronic devices such as smartphones have become more popular due to their convenience or security. In order to strengthen the functions of the smartphone, various parts with various functions have been added. Electronic devices such as smartwatches often have multiple camera modules (dual cameras). It is equipped with a variety of functions such as iris recognition and VR (Virtual Reality) Therefore, it is important to secure space to mount the added components. be.

[0062] In addition, various electronic devices, including wearable devices, are becoming more convenient for users. To improve this, an increase in battery space is required.

[0063] Therefore, it is possible to replace multiple PCBs used in existing electronic devices with one PCB. To secure space for mounting new components or to increase the size of the battery The importance of securing space is becoming apparent.

[0064] The electronic device according to the comparative example has a first chip and a second chip of different types. The first PCB 10 and the second PCB 30 are disposed separately. The thickness of the adhesive layer 50 between the two PCBs 30 and the thickness of the second PCB 30 are There was a problem with increasing the thickness.

[0065] In addition, the size of the second PCB 30 is used to provide space for a battery or to mount other components. There was a problem of reducing the space.

[0066] In addition, poor bonding between the first and second PCBs can reduce the reliability of electronic devices. there were.

[0067] In order to solve such problems, the embodiment is a device that can mount multiple chips on one substrate. A new structure of all-in-one COF flexible circuit board and chip package including the same A cage and an electronic device including the cage can be provided. The surface symbols represent the same components, and explanations that overlap with the comparative example described above will be omitted.

[0068] 2a to 2c, an all-in-one COF flexible circuit board according to an embodiment of the present invention is shown. An electronic device including the board is described.

[0069] The electronic device according to the embodiment transmits a signal from a display panel to a main board. A single PCB can be used for the electronic device including the display unit according to the embodiment. The PCB included in the device may consist of one FPCB. The flexible circuit board 100 for all-in-one COF (all in one chip on film) is The display is bent between the opposing display section and the main board. The A part and the main board can be connected.

[0070] Specifically, the flexible film for all-in-one COF (all in one chip on film) according to the embodiment The block circuit board 100 is a single substrate for mounting multiple chips of different types. It can be.

[0071] All-in-one COF (All in one chip on film) flexible circuit board according to the embodiment The board 100 is a substrate for arranging first and second chips C1 and C2 of different types. It can consist of:

[0072] All-in-one COF (All in one chip on film) flexible circuit board according to the embodiment The thickness t2 of the plate 100 can be 20 μm to 100 μm. The thickness of the flexible circuit board 100 for all-in-one COF (all in one chip on film) The thickness t2 can be 30 μm to 80 μm. For example, the all-in-one The thickness t2 of the flexible circuit board 100 for COF (All in one chip on film) is 50 μm. However, depending on the type of chip to be mounted and the electronic device, Depending on the type of the substrate, the all-in-one COF (All in one chip on film) filter according to the embodiment is used. The thickness of the flexible circuit board 100 can be designed to have various sizes.

[0073] Here, when the thickness t2 of the flexible circuit board 100 is less than 20 μm, When the cable circuit board 100 is bent, it may break. There is a possibility that damage may occur due to heat generated in the mounted chip. There is.

[0074] All-in-one COF (All in one chip on film) flexible circuit board according to the embodiment The thickness t2 of the plate 100 is 1 / 5 to 1 / 2 the thickness t1 of the first and second PCBs according to the comparative example. That is, the all-in-one COF (All i The thickness t2 of the flexible circuit board 100 for n-one chip on film is The thickness of the first and second PCBs may be about 20% to 50% of the thickness t1. For example, the flexible circuit for all-in-one COF (All in one chip on film) according to the embodiment The thickness t2 of the printed circuit board 100 is 25% of the thickness t1 of the first and second PCBs according to the comparative example. For example, the all-in-one CO according to the embodiment may have a thickness of about 40%. The thickness t2 of the F (All in one chip on film) flexible circuit board 100 is the same as that of the comparative example. The thickness of the first and second PCBs may be about 25% to 35% of the thickness t1 of the first and second PCBs. Cut.

[0075] The electronic device having a display unit according to the embodiment includes a display panel and a main button. Only one all-in-one COF (All in one chip on film) flexible Because the circuit board 100 is required, the overall thickness of the electronic device can be reduced. Specifically, the electronic device having a display unit according to the embodiment requires a single-layer PCB. Thus, the overall thickness of the electronic device is reduced.

[0076] In addition, the embodiment omits the adhesive layer 50 between the first and second PCBs included in the comparative example. Can be used for all-in-one COF chip packaging including flexible circuit boards And the overall thickness of the electronic device containing it can be reduced.

[0077] In addition, the embodiment can omit the adhesive layer 50 between the first PCB and the second PCB, and the adhesive layer 50 can be easily attached. This can eliminate problems caused by poor connection, thereby improving the reliability of electronic devices. This can be done.

[0078] In addition, the process of bonding multiple PCBs can be omitted, increasing process efficiency and reducing process costs. is reduced.

[0079] In addition, by replacing substrates that were previously managed in separate processes with one process, process efficiency and product The yield can be improved.

[0080] All-in-one COF (All in one chip on film) flexible circuit board according to the embodiment The plate 100 may include bent regions and non-bent regions. The flexible circuit board 100 for COF (All in one chip on film) includes a bending region. Thus, the display panel 30 and the main board 40 arranged opposite to each other are connected. It is possible.

[0081] All-in-one COF (All in one chip on film) flexible circuit board according to the embodiment The non-bending area of ​​the plate 100 is disposed opposite the display panel 30. All-in-one COF (All in one chip on film) flexible circuit board according to the embodiment A first chip C1 and a second chip C2 are disposed on the non-bending region of the plate 100. All-in-one COF (All in one chip on film) flexible circuit board according to the embodiment The board 100 enables the first chip C1 and the second chip C2 to be stably mounted.

[0082] FIG. 2c is a plan view of the underside of FIG. 2b.

[0083] Referring to FIG. 2c, an embodiment may be used in which one substrate is required, so the length in one direction is L 2 is the length of one substrate. The length L2 in one direction of the flexible circuit board 100 for an optical film is The length of the short side of the flexible circuit board 100 for all-in-one COF (all-in-one chip on film) As an example, an all-in-one COF (All in one chip on film) according to the embodiment The length L2 in one direction of the flexible circuit board 100 for use is 10 mm to 50 mm. For example, the all-in-one COF (All in one chip on film) according to the embodiment can be used The length L2 of the flexible circuit board 100 in one direction is 10 mm to 30 mm. For example, the all-in-one COF (all in one chip on film) frame according to the embodiment can be used. The length L2 of the flexible circuit board 100 in one direction may be 15 mm to 25 mm. However, the embodiment is not limited to this, and the type of chip to be arranged may be And / or the number of electronic devices, and the size can be designed according to the type of electronic device. As in the example, by mounting multiple chips on one substrate, The length of the circuit board can be reduced to 50 mm or less. The length of the flexible circuit board can be reduced to 10 If the spacing is reduced to less than mm, the design freedom of the many chips mounted will decrease, and the spacing between chips will Since the gap is narrow, it may affect the mutual electrical characteristics.

[0084] All-in-one COF (All in one chip on film) flexible circuit board according to the embodiment The length L2 in one direction of the board 100 is the length L2 in one direction of the first and second PCBs in the comparative example. For example, in the embodiment, The flexible circuit board 100 for all-in-one COF (all in one chip on film) The length L2 in one direction is the length in one direction of the plurality of first and second PCBs in the comparative example. The length of the all-in-one device according to the embodiment can be about 55% to 70% of the length L1. Length in one direction of the flexible circuit board 100 for COF (All in one chip on film) L2 is 60% to 70% of the length L1 in one direction of the plurality of first and second PCBs according to the comparative example. It may have a length of about 0%.

[0085] Thus, the embodiment is an all-in-one COF (All in one chip on film) in an electronic device. The size of the chip package including the flexible circuit board 100 for the battery is reduced, The space for placing the all-in-one COF (All i The chip package including the flexible circuit board 100 for one chip on film has a planar area of This reduces the weight and makes it possible to secure space for mounting other components.

[0086] Hereinafter, an all-in-one COF (All in one chip on film) according to an embodiment will be described with reference to the drawings. A flexible circuit board 100 for use in a laser printer and a chip package thereof will now be described.

[0087] FIG. 3a is a cross-sectional view of a flexible circuit board according to a first embodiment of the present invention, and FIG. 3b is a cross-sectional view of a flexible circuit board according to a first embodiment of the present invention. FIG. 4a shows a dummy pattern portion according to a comparative example. FIG. 4b is a cross-sectional view of a flexible circuit board not including a lower dummy according to an embodiment of the present invention. 5a to 5d are cross-sectional views of a flexible circuit board including a pattern portion DP1. FIG. 6 shows various modified examples of the lower dummy pattern portion DP1 shown in FIG. 7A is a diagram showing an upper dummy pattern part DP2 according to an embodiment of the present invention. FIG. FIG. 7b is another cross-sectional view of the flexible circuit board for double-sided all-in-one COF. 7a of the chip package including the double-sided all-in-one COF flexible circuit board FIG. 8 is a cross-sectional view of a double-sided all-in-one COF flexible circuit board according to an embodiment. 2 is another cross-sectional view of a chip package including

[0088] Figure 3a, Figure 3b, Figure 4a, Figure 4b, Figure 5a, Figure 5b, Figure 5c, Figure 5d, Figure 6, Figure 7a, 7b and 8, an all-in-one COF (All in one chip on film) according to an embodiment of the present invention is shown. The flexible circuit board 100 for lm is a double-sided all-in-one board having electrode pattern portions on both sides. The flexible circuit board for the COF can be used.

[0089] All-in-one COF (All in one chip on film) flexible circuit board according to the embodiment The plate 100 includes a substrate 110, a wiring pattern layer 120 disposed on the substrate 110, and a plating layer 120. The protective layer 130, the upper dummy pattern portion DP2, the lower dummy pattern portion DP1 and the protective layer 14 May contain 0.

[0090] A wiring pattern layer 120, a plating layer 130, and an upper datum are formed on one surface of a substrate 110 according to the embodiment. After disposing the Mie pattern portion DP2 and the protective layer 140, A wiring pattern layer 120, a plating layer 130, a lower dummy pattern portion DP1, and a protective layer 140 can be placed.

[0091] That is, on one surface of the substrate 110 according to the embodiment, an upper wiring pattern layer, an upper plating layer, an upper A dummy pattern portion DP2 and an upper protective layer are disposed on the other surface opposite to the one surface. A lower wiring pattern layer, a lower plating layer, a lower dummy pattern part DP1 and a lower protective layer are arranged. can be.

[0092] The upper wiring pattern layer may include a metal material corresponding to the lower wiring pattern layer. Therefore, the process efficiency is improved. However, the embodiment is not limited to this, and other embodiments may be used. Of course, it may contain conductive materials.

[0093] The thickness of the upper wiring pattern layer may correspond to the thickness of the lower wiring pattern layer. Improved process efficiency.

[0094] The upper plating layer may include a metal material corresponding to the lower plating layer. However, the embodiment is not limited thereto, and other conductive materials may be used. Of course it can be included.

[0095] The thickness of the upper plating layer may correspond to the thickness of the lower plating layer, thus improving process efficiency. To rise.

[0096] The upper dummy pattern portion DP2 is formed on the lower surface of the substrate 110. A lower dummy pattern part DP1 is arranged at a position corresponding to the arranged lower wiring pattern layer. corresponds to the upper wiring pattern layer disposed on the upper surface of the substrate 110 among the lower surfaces of the substrate Therefore, in the present invention, the upper protective layer or the lower protective layer is placed at a position where the In this way, the pinhole problem caused by the difference in height between the upper and lower parts of the substrate 110 can be solved. This can improve the reliability of the PCB.

[0097] The substrate 110 supports the wiring pattern layer 120, the plating layer 130, and the protective layer 140. The support substrate may comprise a support substrate.

[0098] The substrate 110 may include a bent region and a region other than the bent region. The substrate 110 may include a folded region and a non-folded region other than the folded region. do.

[0099] The substrate 110 may be a flexible substrate. That is, the substrate 110 is made of flexible plastic. For example, the substrate 110 may be a polyimide substrate. However, the embodiment is not limited to this, and polyethylene terephthalate may be used. Polyethylene terephthalate, polyethylene naphthalate The substrate may be made of a polymeric material such as phthalate. The flexible circuit board including the board 110 is adapted to accommodate various electrical wiring patterns including a curved display device. For example, a flexible circuit board including the substrate 110 may be used in a child device. Since it has excellent flexibility, it is suitable for mounting semiconductor chips in wearable electronic devices. In particular, the embodiments are adapted for use in electronic devices that include curved displays. do.

[0100] The substrate 110 may be an insulating substrate. It may be made of an insulating substrate that supports the wiring pattern.

[0101] The substrate 110 may have a thickness of 20 μm to 100 μm. The plate 110 may have a thickness of 25 μm to 50 μm. For example, the substrate 100 may be The thickness of the substrate 100 may be 30 μm to 40 μm. If it exceeds this, the overall thickness of the flexible circuit board will increase. When the thickness of 100 is less than 20 μm, the first chip C1 and the second chip C2 are simultaneously If the thickness of the substrate 110 is less than 20 um, it becomes difficult to arrange a large number of chips. In the process of mounting chips, the substrate 110 is vulnerable to heat / pressure, etc., and it is difficult to mount multiple chips at the same time. The wiring is disposed on the substrate 110. For example, the plurality of wirings may be arranged on the substrate 110. That is, a wiring pattern layer 120 is disposed on one surface of the substrate 110. It will be placed.

[0102] The area of ​​the substrate 110 is larger than the area of ​​the wiring pattern layer 120. Specifically, the planar area of ​​the substrate 110 is equal to or smaller than the planar area of ​​the wiring pattern layer 120. That is, the wiring pattern on the substrate 110 can have a larger planar area. For example, the lower surface of the wiring pattern layer 120 is The wiring panel is in contact with the substrate 110, and the substrate 110 is exposed between the wirings. The turning layer 120 may include a conductive material.

[0103] The substrate 110 may include a through hole. The substrate 110 may include a plurality of through holes. The through holes of the substrate 110 may be formed by a mechanical process or a chemical process. For example, the plurality of through holes in the substrate 110 may be formed by a single process. The through holes are formed by a drilling or etching process. The through holes in the plate are formed through a laser punching and desmearing process. The desmear step is a step of removing polyimide smears attached to the inner surface of the through hole. The desmear process may form a line or similar pattern on the inner surface of the polyimide substrate. The slanted surfaces may be similar.

[0104] On the substrate 110, a wiring pattern layer 120, a plating layer 130, and a dummy pattern portion D P1, DP2 and a protective layer 140 are disposed on both sides of the substrate 110. The wiring pattern layer 120, the plating layer 130, the dummy pattern parts DP1 and DP2, and the protective layer 1 At this time, the dummy pattern parts DP1 and DP2 are arranged in the front The height corresponds to the wiring pattern layer 120 and the plating layer 130. The dummy pattern portions DP1 and DP2 in the first embodiment of the present invention are The wiring pattern layer 120 is made of the same metal material as the wiring pattern layer 120 and has a thickness greater than that of the wiring pattern layer 120. Preferably, the dummy pattern portions DP1 and DP2 are The thickness of the plating layer 130 may be the sum of the thickness of the thermal expansion layer 120 and the thickness of the plating layer 130 .

[0105] The wiring pattern layer 120 is formed by a method such as evaporation, plating, sputtering, etc. The pores are formed by at least one of the following methods:

[0106] As an example, the wiring layer for forming the circuit is formed by electrolytic plating after sputtering. As an example, the wiring layer for forming the circuit is formed by electroless plating. Alternatively, the wiring layer may be made of a copper plating layer formed by electroless plating and electrolytic plating. It may be made of a copper plating layer formed by plating.

[0107] Next, a light film is laminated on the wiring layer, and then exposed, developed and etched. Through the bonding process, the patterned arrangement is formed on both sides of the flexible circuit board, i.e., the top and bottom. Thus, the wiring pattern layer 120 can be formed. do.

[0108] For example, the wiring pattern layer 120 may include a metal material having excellent electrical conductivity. More specifically, the wiring pattern layer 120 may include copper (Cu). Examples include, but are not limited to, copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), and the like. At least one of the following metals: nickel (Ni), silver (Ag), molybdenum (Mo), gold (Au), titanium (Ti) and their alloys Of course, both may contain one metal.

[0109] The wiring pattern layer 120 is disposed to a thickness of 1 μm to 15 μm. For example, The pattern layer 120 is disposed with a thickness of 1 μm to 10 μm. For example, 120 is disposed with a thickness of 2 μm to 10 μm.

[0110] When the thickness of the wiring pattern layer 120 is less than 1 μm, When the thickness of the wiring pattern layer 120 exceeds 10 μm, the resistance increases. This makes it difficult to realize the desired effect.

[0111] The via holes V1, V2, and V3 penetrating the substrate 110 are filled with a conductive material. The conductive material filled in the via hole corresponds to the wiring pattern layer 120. For example, the via hole may be filled with the same material or a different conductive material. The conductive materials used are copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), Contains at least one of the following metals: molybdenum (Mo), gold (Au), titanium (Ti) and their alloys. The electrical signal of the conductive pattern portion CP on the upper surface of the substrate 110 is The conductive pattern portion CP on the bottom surface of the substrate 110 is formed through the conductive material filled in the holes. is transmitted to.

[0112] Next, a plating layer 130 is formed on the wiring pattern layer 120. The plating layer 130 may include a first plating layer 131 and a second plating layer 132 .

[0113] A first plating layer 131 is disposed on the wiring pattern layer 120. The second plating layer 132 is disposed on the first plating layer 131. The second plating layer 132 is formed to prevent the formation of whiskers (whisker-kr00000374075b1). In addition, two layers are formed on the wiring pattern layer 120. In addition, the wiring pattern layer 120 can prevent short circuits between the patterns of the wiring pattern layer 20. Since two plating layers are placed on top, the bonding characteristics with the chip are improved. When the wiring pattern layer contains copper (Cu), the wiring pattern layer is directly bonded to the first chip C1. It is not possible to bond the wiring, and a separate process is required for bonding. When the plating layer disposed on the pattern layer contains tin (Sn), the surface of the plating layer Since the first chip C1 is a pure tin layer, it is easy to bond it to the first chip C1. The wire that connects to the chip C1 is simply connected to the pure tin layer with heat and pressure, The accuracy of wire bonding and the convenience of the manufacturing process can be improved.

[0114] The region in which the first plating layer 131 is disposed is the region in which the second plating layer 132 is disposed. That is, the area where the first plating layer 131 is disposed may correspond to the area where the second plating layer 131 is disposed. This may correspond to the area in which the layer 132 is disposed.

[0115] The plating layer 130 may include tin (Sn). For example, the first plating layer 131 The second plating layer 132 may include tin (Sn).

[0116] For example, the wiring pattern layer 120 is formed of copper (Cu), and the first plating layer 131 and The second plating layer 132 may be formed of tin (Sn). In the case where the tin (Sn) is contained, the corrosion resistance of the tin (Sn) is excellent, so that the oxidation of the wiring pattern layer 120 is prevented. It is possible.

[0117] Meanwhile, the material of the plating layer 130 has a lower electrical conductivity than the material of the wiring electrode layer 120. The plating layer 130 can be electrically connected to the wiring electrode layer 120.

[0118] The first plating layer 131 and the second plating layer 132 are formed of the same tin (Sn), or formed in a separate process.

[0119] In the manufacturing process of the flexible circuit board according to the embodiment, a heat treatment process such as thermosetting is included If so, diffusion of copper (Cu) in the wiring pattern layer 120 or tin (Sn) in the plating layer 130 occurs. Specifically, through the curing of the protective layer 140, diffusion of copper (Cu) in the wiring pattern layer 12 0 or tin (Sn) in the plating layer 130 occurs. As a result, in the first plating layer 131, the diffusion concentration of copper (Cu) decreases toward the surface of the second plating layer 132, so that the copper (Cu) content continuously decreases. On the other hand

[0120] In the first plating layer 131, the tin (Sn) content continuously increases toward the surface of the second plating layer 132. Therefore, the uppermost part of the plating layer 130 can contain pure tin. That is, due to the chemical action at the lamination interface between the wiring pattern layer 120 and the plating layer 130, at least a part of the plating layer 130 can be composed of an alloy of tin and copper. The thickness of the alloy of tin and copper after curing the protective layer 140 on the plating layer 130 is greater than the thickness of the alloy of tin and copper after forming the plating layer 130 on the wiring pattern layer 120.

[0121] That is, due to the chemical action at the lamination interface between the wiring pattern layer 120 and the plating layer 130, at least a part of the plating layer 130 can be composed of an alloy of tin and copper. The alloy of tin and copper contained in at least a part of the plating layer 130 has a chemical formula of Cu Sn and 0 < x + y < 12. For example, in the chemical formula, the sum of x and y is 4 ≤ x

[0122] x Sn y and y, and for example, in the chemical formula, the sum of x and y is 4 ≤ x ​​​​​​+y≦11. For example, the alloy of tin and copper contained in the plating layer 130 is Cu3S Specifically, the first plating may include at least one of Cu6Sn5 and Cu6Sn. The layer 131 may be made of an alloy layer of tin and copper.

[0123] In addition, the first plating layer 131 and the second plating layer 132 have mutually different contents of tin and copper. The first plating layer 131 that is in direct contact with the copper wiring pattern layer may be different from the first plating layer 131. The copper content is greater than that of the second plating layer 132 .

[0124] The second plating layer 132 has a higher tin content than the first plating layer 131. The second plating layer 132 may contain pure tin. Here, pure tin refers to a material containing only tin (Sn). The content is 50 atomic % or more, 70 atomic % or more, or 90 atomic % or more. In this case, the element other than tin may be copper. For example, The second plating layer 132 may have a tin (Sn) content of 50 atomic % or more. The second plating layer 132 may have a tin (Sn) content of 70 atomic % or more. The second plating layer 132 may have a tin (Sn) content of 90 atomic % or more. The second plating layer 132 may have a tin (Sn) content of 95 atomic % or more. The second plating layer 132 may have a tin (Sn) content of 98 atomic % or more.

[0125] The plating layer according to the embodiment is electrochemically migrated due to the diffusion development of Cu / Sn. Prevents electrochemical migration resistance (EMR) and prevents short circuit defects caused by metal growth It is possible.

[0126] However, the embodiment is not limited thereto, and the plating layer 130 may be Ni / A u alloy, gold (Au), electroless nickel immersion gold (ENIG) , Ni / Pd alloy, organic compound plating (Organic Solderability Preservative, OSP) Of course, it can contain either one.

[0127] The first plating layer 131 and the second plating layer 132 may have corresponding or different thicknesses. The total thickness of the first plating layer 131 and the second plating layer 132 may be 0. The first plating layer 131 and the second plating layer 132 may have a thickness of 0.3 μm to 1 μm. The total thickness of the first plating layer 132 may be 0.3 μm to 0.7 μm. The total thickness of the second plating layer 132 and the first plating layer 31 may be 0.3 μm to 0.5 μm. Either the first plating layer 131 or the second plating layer 132 can be For example, the first plating may have a thickness of 0.05 μm to 0.15 μm. The thickness of either the layer 131 or the second plating layer 132 is 0.07 μm to 0.1 It may have a thickness of 3 μm or less.

[0128] After that, the protective part PP can be screen-printed on the conductive pattern part CP. do.

[0129] The protective layer 140 is partially disposed on the wiring pattern layer 120. For example, The protective layer 140 is disposed on the plating layer 130 on the wiring pattern layer 120. The protective layer 140 may cover the plating layer 130, and the wiring pattern layer Therefore, damage or peeling caused by oxidation of the plating layer 120 and the plating layer 130 can be prevented.

[0130] The protective layer 140 is formed by removing the wiring pattern layer 120 and / or the plating layer 130 from the The display panel 30, the main board 40, the first chip C1 or the second chip C2 and the electrical The stencils are arranged partially in an area excluding an area for efficient connection.

[0131] Thus, the protective layer 140 is formed on the wiring pattern layer 120 and / or the plating. It may partially overlap with layer 130.

[0132] The area of ​​the protective layer 140 may be smaller than the area of ​​the substrate 110 . The protective layer 140 is disposed in an area other than the end of the substrate and includes a plurality of open areas. This can be done.

[0133] The protective layer 140 may include a first open area OA1 shaped like a hole. The first open area OA1 is formed by the wiring pattern layer 120 and / or the plating In the non-placement area of ​​the protective layer 140, the layer 130 is electrically connected to the first chip C1. It's fine.

[0134] The protective layer 140 may include a second open area OA2 shaped like a hole. The second open area OA2 is formed by the wiring pattern layer 120 and / or the plating In the non-placement area of ​​the protective layer 140, the layer 130 is electrically connected to the second chip C2. Therefore, in the second open area OA2, the plating layer 130 may be is exposed to

[0135] In the second open area OA2, the copper content of the plating layer 130 is 50 atomic percent. For example, the copper content in the plating layer 130 may be 60 atomic % or more. For example, the copper content in the plating layer 130 may be 60 atomic % to 80 atomic %. Specifically, the first SiO 2 measured in the second open area OA2 may be expressed as a percentage by atomic percent. The copper content of the plating layer 131 may be 60 atomic % to 80 atomic %.

[0136] The protective layer 140 is electrically connected to the main board 40 or the display panel 30. The conductive pattern portion may not be disposed on the conductive pattern portion for effectively connecting the conductive pattern portion to the substrate. A conductive pad for electrically connecting to the inboard 40 or the display panel 30 The third open area OA3 is a non-placement area of ​​the protective layer 140 on the turn portion. Therefore, the plating layer 130 is exposed to the outside in the third open area OA3. can be.

[0137] In the third open area OA3, the copper content of the plating layer 130 is 50 atomic % or more. Alternatively, in the third open area OA3, the plating layer 1 The copper content of the third open area OA3 may be less than 50 atomic %. The first open area OA1 may be located at an outer edge of the substrate. The open area OA3 may be located closer to the outer edge of the substrate than the second open area OA2. do.

[0138] The first open area OA1 and the second open area OA2 are Area OA3 may be located in a more central region of the substrate.

[0139] The protective layer 140 is disposed in the folding region. Therefore, the all-in-one according to the embodiment can disperse the stress that may occur when the The reliability of COF flexible circuit boards can be improved.

[0140] The protective layer 140 may include an insulating material. It contains a variety of substances that are applied and then heated to harden to protect the surface of the turn. The protective layer 140 may be a resist layer. For example, The protective layer 140 may be a solder resist layer including an organic polymer material. For example, the protective layer 140 may include an epoxy acrylate resin. Specifically, the protective layer 140 may include a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, etc. The examples may include, but are not limited to, the following: The protective layer 140 is not a photo solder resist layer, a cover layer, or the like. ay) and a polymeric substance.

[0141] The protective layer 140 may have a thickness of 1 μm to 20 μm. The thickness of the protective layer 140 may be 1 μm to 15 μm. When the thickness of the protective layer 140 exceeds 20 μm, In this case, the thickness of the flexible circuit board for all-in-one COF will increase. When the thickness of the protective layer 140 is less than 1 μm, the flexible substrate for all-in-one COF is The reliability of the conductive pattern portion included in the circuit board is reduced.

[0142] That is, the single-sided all-in-one COF flexible circuit board 100 according to the embodiment is a board 110, a conductive pattern portion CP and a dummy pattern portion DP1 arranged on one side of a substrate; DP2 and the dummy pattern portion DP1, DP2 and a portion above the conductive pattern portion CP A protective portion PP may be included, which is formed by disposing a protective layer 140 partially on the region.

[0143] The conductive pattern portion CP includes the wiring pattern layer 120 and the plating layer 130. It is possible to do so.

[0144] The protective portion PP is disposed on one region and another region on the conductive pattern portion CP. It's not necessary.

[0145] The protective portion PP is disposed on the dummy pattern portions DP1 and DP2. do.

[0146] As a result, the conductive pattern portion CP has a conductive layer on one region and a conductive layer on the other region. The pattern portion CP and the substrate 110 between the spaced apart conductive pattern portions CP are exposed. A first connection portion 70 and a second connection portion 71 are provided on one region and the other region of the conductive pattern portion CP. Specifically, the conductive pattern 80 on which the protective portion PP is not disposed is A first connection portion 70 and a second connection portion 80 are disposed on the upper surface of the connection portion CP.

[0147] The first connection portion 70 and the second connection portion 80 may have different shapes. For example, the first connection portion 70 may have a hexahedral shape. The cross section of the first connection part 70 may include a rectangular shape. The cross section of the second connecting portion 8 may include a rectangular or square shape. The cross section of the second connection portion 80 may include a spherical shape. Alternatively, the second connection portion 80 may include a round shape partially or entirely. For example, the cross-sectional shape of the second connection portion 80 may be flat on one side and flat on the front side. The side opposite the one side may be curved.

[0148] The first and second connection portions 70 and 80 may have different sizes. The first connecting portion 70 may have a smaller size than the second connecting portion 80. .

[0149] The first connection portion 70 and the second connection portion 80 may have different widths. For example, the width D1 between both side surfaces of one first connection portion 70 is It may have a width smaller than the width D2 between the sides.

[0150] The first chip C1 is disposed on the first connection portion 70. The first connection portion 70 The first connection portion 70 may include a conductive material. 0 and the first chip C1 disposed on the lower surface of the first connection portion 70. The conductive pattern portions CP can be electrically connected to each other.

[0151] The second chip C2 is disposed on the second connection portion 80. The second connection portion 80 The second connection portion 80 may include a conductive material. 0 and the second chip C2 disposed on the lower surface of the second connection portion 80. The conductive pattern portions CP can be electrically connected to each other.

[0152] On the same side of the single-sided all-in-one COF flexible circuit board 100 according to the embodiment In the embodiment, a first chip C1 and a second chip C2 of different types are arranged. On the same surface of the single-sided all-in-one COF flexible circuit board 100 according to the embodiment, In this case, one first chip C1 and multiple second chips C2 may be arranged. This can improve the efficiency of the chip packaging process.

[0153] The first chip C1 may include a drive IC chip.

[0154] The second chip C2 means a chip other than the drive IC chip. The second chip C2 can be a socket or a For example, the second chip C2 may be a DA Iode chips, power supply IC chips, touch sensor IC chips, MLCC chips, BGA The capacitor may include at least one of a chip and a chip capacitor.

[0155] A plurality of second chips arranged on the flexible circuit board 100 for all-in-one COF C2 is a diode chip, a power IC chip, a touch sensor IC chip, and an MLCC chip. This means that at least one of the following is placed multiple times: chip, BGA chip, and chip capacitor. As an example, the flexible circuit board 100 for all-in-one COF can be used On top of this are placed multiple MLCC chips.

[0156] The second chip C2 includes a diode chip, a power IC chip, a touch sensor I Contains at least two of the following: C chip, MLCC chip, BGA chip, and chip capacitor. That is, on the all-in-one COF flexible circuit board 100, A plurality of second chips C2a and C2b of different types are arranged. For example, an all-in-one On the flexible circuit board 100 for COF, a diode chip, a power IC chip, Touch sensor IC chips, MLCC chips, BGA chips, chip capacitors Any one of the second chips C2a, a diode chip, a power IC chip, and a touch sensor Any one of the following: IC chip, MLCC chip, BGA chip, chip capacitor and a second chip C2b different from the first chip C1.

[0157] Specifically, the all-in-one COF flexible circuit board 100 is provided with a diode chip, power IC chip, touch sensor IC chip, MLCC chip, BGA chip, A plurality of second chips C2a of any one of the chip capacitors are arranged, and the diode chip chip, power IC chip, touch sensor IC chip, MLCC chip, BGA chip, chip A plurality of second chips C2b are arranged, each of which is different from any one of the chip capacitors. One example is a flexible circuit board for all-in-one COF. On the upper surface of 100, a plurality of MLCC chips C2a and a plurality of power supply IC chips C2b are included. As an example, the all-in-one COF flexible circuit board 100 may be , a plurality of MLCC chips C2a and a plurality of diode chips C2b. As an example, the flexible circuit board 100 for all-in-one COF may have a plurality of ML It may include a CC chip C2a and multiple BGA chips C2b.

[0158] In the embodiment, the number of types of the second chips is not limited to two, and the number of driving IC chips may be any number. Of course, all of the various chips except the chip may be included in the second chip.

[0159] One end of the all-in-one COF flexible circuit board 100 is One end of the all-in-one COF flexible circuit board 100 is connected to the cable 30. , and is connected to the display panel 30 by an adhesive layer 50. The display panel 30 is disposed on the upper surface of the adhesive layer 50, and the The flexible circuit board 100 for all-in-one COF is arranged. The play panel 30 and the all-in-one COF flexible circuit board 100 are The upper and lower parts are joined together with an adhesive layer 50 sandwiched therebetween.

[0160] The other end of the flexible circuit board 100 for all-in-one COF is opposite to the one end. is connected to the main board 40. The other end of the 100 opposite to the one end is connected to the main board 40 by an adhesive layer 50. Specifically, the main board 40 is disposed on the upper surface of the adhesive layer 50. The flexible circuit board 100 for all-in-one COF is disposed on the lower surface of the The main board 40 and the all-in-one COF flexible circuit board 100 are bonded together from above and below with the adhesive layer 50 in between.

[0161] The adhesive layer 50 may include a conductive material. The adhesive layer 50 may include conductive particles. For example, the adhesive layer 50 may be an anisotropic conductive film. The ACF can be made of

[0162] Thus, the adhesive layer 50 can be attached to the display panel 30 and the all-in-one The flexible circuit board 100 transmits electrical signals between the flexible circuit board 100 and the main board 40. At the same time, it is possible to stably connect other components.

[0163] On the other hand, the above-mentioned dummy pattern portions DP1 and DP2 are arranged on the substrate 110. That is, the upper dummy pattern portion DP2 is disposed on the upper surface of the substrate 110. The lower dummy pattern portion DP1 is disposed on the lower surface of the substrate 110.

[0164] The upper dummy pattern portion DP2 is formed on the upper surface of the substrate 110 so as to be adjacent to the upper wiring pattern. The upper dummy pattern portion DP2 is preferably disposed in a region where no insulating layer is disposed. The upper surface of the substrate 110 is vertically overlapped with a lower wiring pattern layer disposed on the lower surface of the substrate 110. It is disposed on an area of ​​the surface where the upper wiring pattern layer is not disposed.

[0165] The lower dummy pattern portion DP1 is formed on the lower surface of the substrate 110 so as to be adjacent to the lower wiring pattern. The lower dummy pattern portion DP1 is preferably disposed in a region where no insulating layer is disposed. The upper wiring pattern layer is disposed on the upper surface of the substrate 110 and overlaps the upper wiring pattern layer vertically. It is disposed on an area of ​​the surface where the upper wiring pattern layer is not disposed.

[0166] That is, the upper wiring pattern layer and the lower wiring pattern layer disposed on the substrate 110 The positions of the do not correspond to each other, but are determined according to the functions and the number of signal wiring lines. are designed and placed on each surface of the substrate 110.

[0167] Therefore, the upper wiring pattern layer and the upper plating layer are vertically overlapped with each other. The lower surface of the substrate 110 is provided with the lower wiring pattern layer and the lower plating layer. Also, a region in which the lower wiring pattern layer and the lower plating layer are disposed may be perpendicular to the region. The upper surface of the substrate 110 is covered with the upper wiring pattern layer and the upper plating layer. It does not have to be placed.

[0168] At this time, the protective layer 140 is disposed on the substrate 110 by a printing process. The protective layer 140 is preferentially printed on one side of the substrate 110, and the printing on the one side After the printing process is completed, a printing process is performed on the other side of the substrate 110 .

[0169] Here, the protective layer 140 is printed on one side or the other side of the substrate. On the other hand, there is an area where no wiring pattern layer / plating layer is arranged, and on the other hand, there is an area where no wiring pattern layer / plating layer is arranged. The coexistence of areas where plating layers are arranged results in the generation of steps. If the step exists on the opposite side to the side on which the protective layer 140 is printed, the protective layer 1 During the printing process of 40, problems such as the protective layer 140 not being placed and pinholes may occur. This has a significant impact on the reliability of the PCB.

[0170] Therefore, in order to solve the above problem, the present invention is to provide a structure in which the step does not exist. On the surface opposite to the surface on which the protective layer 140 is printed, the dummy pattern portion DP1 as described above is formed. , forming DP2.

[0171] At this time, the protective layer 140 is printed preferentially on the upper surface of the substrate 110. When the step is performed, the dummy pattern portions DP1 and DP2 are formed as lower dummy pattern portions D That is, the protective layer 140 may be printed on the upper surface of the substrate 110. In this case, the lower dummy pattern portion DP1 disposed on the lower surface of the substrate 110 Thus, the upper surface of the substrate 110 is provided with a uniform height protection layer. A layer 140 is placed.

[0172] After the printing process of the protective layer 140 on the upper surface of the substrate 110 is completed, When the printing process of the protective layer 140 on the lower surface of the substrate 110 is performed, The protective layer 140 formed on the surface of the upper wiring pattern layer / upper plating layer is As a result, a uniform protective layer 140 is formed on the lower surface of the substrate 110. do.

[0173] However, the surface on which the protective layer 140 is printed first is The above-mentioned changes depending on the manufacturing environment of the PCB. Considering the manufacturing environment of the PCB, the lower wiring pattern is formed on the upper surface of the substrate 110. and forming an upper dummy pattern portion DP2 at a position corresponding to the lower plating layer and the lower plating layer on the substrate. The lower surface of 110 is provided with a lower duct at a position corresponding to the upper wiring pattern layer and the upper plating layer. The corresponding position is on one surface of the substrate 110. This refers to the position on the other side of the substrate that overlaps vertically with the wiring pattern layer and plating layer arranged on the .

[0174] The dummy pattern portions DP1 and DP2 may be made of a single layer. The dummy pattern portions DP1 and DP2 may include only a dummy pattern layer. The dummy pattern layer may include the same metal material as the wiring pattern layer, provided that: The present invention is not limited to this, and the dummy pattern layer may be the wiring pattern. For example, the dummy pattern layer may be made of a non-metallic material. It can include.

[0175] Also, as shown in FIG. 3b, the dummy pattern portions DP1 and DP2 The first dummy pattern layer 151, the second dummy pattern layer 152 and the third dummy pattern It may include layer 153.

[0176] The first dummy pattern layer 151 corresponds to the wiring pattern layer 120. The dummy pattern layer 151 includes the same metal material as the wiring pattern layer 120. The dummy pattern layer 151 may be a part of the wiring pattern layer 120. The surface of the substrate 110 is provided with a wiring pattern for electrically connecting to the chip and transmitting signals. At this time, the first dummy pattern layer 120 is disposed together with the wiring pattern layer 120. That is, a pattern layer may be formed on the substrate 110. This is formed by a wiring pattern layer 120 for transmitting the electrical signals and the first dummy The first dummy pattern layer 151 includes a first dummy pattern layer 151. Unlike the turn layer 120, it does not transmit electrical signals, and thus the wiring pattern layer 1 That is, the first dummy pattern layer 151 is not electrically connected to the substrate 11. The wiring pattern is formed on the surface of the substrate 100 in an area where the wiring pattern layer 120 is not formed. The insulating layer 120 is disposed independently without being connected to the insulating layer 120.

[0177] The second dummy pattern layer 152 is disposed on the first dummy pattern layer 151. The second dummy pattern layer 152 may be a part of the first plating layer 131. The third dummy pattern layer 152 is disposed on the second dummy pattern layer 152. The third dummy pattern layer 153 may be a part of the second plating layer 132. .

[0178] That is, the dummy pattern portions DP1 and DP2 in the present invention are the conductive pattern portions CP The dummy pattern portion may be formed of a single layer, unlike the layer structure of the dummy pattern portion. DP1 and DP2 have a three-layer structure similar to the layer structure of the conductive pattern portion CP. It is possible.

[0179] On the other hand, the protective layer 140 is disposed on the dummy pattern portions DP1 and DP2. That is, the protective layer 140 is formed on the surface of the conductive pattern portion CP to be opened. The dummy pattern portions DP1 and DP2 are not exposed to the outside. As a result, the protective layer 14 is formed on the dummy pattern portions DP1 and DP2. 0 is placed.

[0180] Meanwhile, referring to FIG. 3a, the area of ​​the wiring pattern layer 120 is approximately 100 mm thick. The area of ​​the first plating layer 131 may correspond to the area of ​​the second plating layer 132. It may be possible to respond.

[0181] Referring to FIG. 7, the area of ​​the wiring pattern layer 120 is different from that of the plating layer 130. The area of ​​the wiring pattern layer 120 may correspond to the area of ​​the first plating layer 131. The area of ​​the first plating layer 131 may be different from the area of ​​the second plating layer 132. For example, the area of ​​the first plating layer 131 may be larger than the area of ​​the second plating layer 132. It can have a large area.

[0182] Referring to FIG. 8, the area of ​​the wiring pattern layer 120 is different from that of the plating layer 130. This is also fine.

[0183] Referring to FIG. 9, the area of ​​the wiring pattern layer 120 on one surface of the substrate 110 is The wiring pattern layer is different from the plating layer 130 on the other surface of the substrate 110. The area of ​​120 may correspond to the plating layer 130 .

[0184] The protective layer 140 is disposed directly on the substrate 110 or is disposed over the wiring pattern. The first plating layer 131 is disposed on the first plating layer 120 in direct contact therewith, or on the first plating layer 131 in direct contact therewith. The second plating layer 132 is disposed on the second plating layer 132, or is disposed on the second plating layer 132 in direct contact therewith. The protective layer 140 is disposed in direct contact with the dummy pattern portions DP1 and DP2.

[0185] Referring to FIG. 3a and FIG. 3b, the first plating layer 110 is formed on the wiring pattern layer 120. 31 is disposed, the second plating layer 132 is formed on the first plating layer 131, and The protective layer 140 is partially disposed on the second plating layer 132. The protective layer 140 is disposed over the entire pattern portions DP1 and DP2.

[0186] Referring to FIG. 7a and FIG. 7b, the first plating layer 13 is formed on the wiring pattern layer 120. 1 is disposed on the first plating layer 131, and the protective layer 140 is disposed partially on the first plating layer 131. The second plating layer 132 is formed on the area where the protective layer 140 is disposed on the plating layer 131. It is placed in an area other than the

[0187] The first plating layer 131, which is in contact with the lower surface of the protective layer 140, is made of an alloy layer of copper and tin. The second plating layer 132 in contact with the side of the protective layer 140 may be a pure Therefore, the protective layer 140 and the first plating layer 131 can have a common layer. This can prevent the protective layer from peeling off due to the formation of the portion, and can prevent the formation of whiskers, Therefore, the embodiment can include two plating layers. This makes it possible to provide a highly reliable electronic device.

[0188] Also, a single tin plating layer 131 is disposed on the wiring pattern layer 120. When the protective layer 140 is disposed on the tin plating layer 131, the protective layer 140 is thermally cured. The tin-plated layer 131 is heated to diffuse copper into the tin-plated layer 131. Therefore, the tin plating layer 131 becomes an alloy layer of tin and copper, and the first Therefore, the plating layer 130 according to the embodiment is formed by bonding the chip to the substrate. The first plating layer 131 and the second plating layer 132 are required in which the tin concentration increases continuously with increasing distance. It is required.

[0189] As shown in FIG. 7a, the dummy pattern portions DP1 and DP2 are The first plating layer 131 may include a single dummy pattern layer corresponding to the first plating layer 120 and the second plating layer 131. can.

[0190] As shown in FIG. 7b, the dummy pattern portions DP1 and DP2 are a first dummy pattern layer 151 corresponding to the layer 120; 2, a dummy pattern layer 152, and a third dummy pattern corresponding to the second plating layer 132. The insulating layer 153 may include a conductive layer 153 .

[0191] Referring to FIG. 8, the first plating layer 131 is disposed on the wiring pattern layer 120. The protective layer 140 is disposed partially on the first plating layer 131. The plating layer 132 is formed on the plating layer 131 in an area other than the area where the protective layer 140 is disposed. are placed in the area.

[0192] At this time, the wiring pattern layer 120 includes a first wiring pattern layer 121 and a second wiring pattern layer 122. That is, a plurality of wiring pattern layers are disposed on the substrate. will be done.

[0193] In addition, although not shown, there is a layer between the substrate 110 and the first wiring pattern layer 121. A metal seed for improving the adhesion between the substrate 110 and the first wiring pattern layer 121. In this case, the metal seed layer is formed by sputtering. The metallic seed layer may include copper.

[0194] The first wiring pattern layer 121 and the second wiring pattern layer 122 are formed by a process corresponding to each other. The layers may be formed in the same or different steps.

[0195] The first wiring pattern layer 121 is formed by sputtering copper to a thickness of 0.1 μm to 0.5 μm. The first wiring pattern layer 121 is formed by connecting the upper and lower parts of the substrate and the through holes. At this time, since the thickness of the first wiring pattern layer 121 is thin, The inner surfaces of the holes are spaced apart from each other.

[0196] Next, the second wiring pattern layer 122 is disposed on the first wiring pattern layer 121. In addition, the second wiring pattern layer 122 is entirely formed inside the through-hole by plating. is fulfilled.

[0197] The first wiring pattern layer 121 is formed by sputtering, so that the substrate 110 or the metal seed layer has an advantage of being excellent in adhesion, but the manufacturing cost is high. Then, the second wiring pattern layer 121 is formed again on the first wiring pattern layer 121 by plating. By forming the through hole 22, the manufacturing cost can be reduced. The second wiring pattern layer 121 is formed on the first wiring pattern layer 121 without filling the holes with a conductive material. Since copper is filled into the via holes at the same time as the line pattern layer 122 is disposed, the process efficiency is improved. In addition, it is possible to prevent voids from being formed in the via holes, resulting in a highly reliable alloy. To provide a flexible circuit board for one-in-one COF and an electronic device including the same. can.

[0198] The dummy pattern portions DP1 and DP2 correspond to the first wiring pattern layer 121. and a second dummy pattern layer 151 corresponding to the second wiring pattern layer 122. a pattern layer 152, and a third dummy pattern layer 153 corresponding to the first plating layer 131; , a fourth dummy pattern layer 154 corresponding to the second plating layer 132 .

[0199] Referring to FIG. 9, a plurality of protective layers 140 are disposed on one side of the substrate. The layers can include a first protective layer 141 and a second protective layer 142 .

[0200] For example, a first protective layer 141 is partially disposed on one surface of the substrate, and the protective layer 14 The wiring pattern layer 120 is disposed on the area other than the area where the wiring pattern layer 120 is disposed.

[0201] The second protective layer 142 is disposed on the protective layer 141. 2 covers the first protective layer 141 and the wiring pattern layer 120, and the first protective layer 14 It is placed in an area greater than 1.

[0202] The protective layer 142 faces the first protective layer 141 while covering the upper surface of the first protective layer 141. The second protective layer 142 is disposed on a corresponding area. The width of the second protective layer 142 is larger than that of the protective layer 141. Therefore, the lower surface of the second protective layer 142 may be formed on the wiring pattern layer 141. 120 and the first protective layer 141. Therefore, the second protective layer 14 2, stress is concentrated at the interface between the first protective layer 141 and the wiring pattern layer 120. Therefore, the all-in-one COF flexible circuit according to the embodiment can be This can reduce the occurrence of peeling or cracks that may occur when the substrate is bent.

[0203] The plating layer 130 is disposed in the area other than the area where the second protective layer 142 is disposed. Specifically, the wiring pattern is formed in an area other than the area where the second protective layer 142 is disposed. The first plating layer 131 is disposed on the insulating layer 120, and a front plated layer 132 is disposed on the first plating layer 131. The second plating layer 132 is then disposed.

[0204] A wiring pattern layer 120 is disposed on the other surface of the substrate opposite to the one surface. The plating layer 130 is disposed on the line pattern layer 120. A partially protective layer 140 is disposed thereon.

[0205] The width of the protective layer disposed on one side of the substrate and the width of the protective layer disposed on the other side of the substrate are They may correspond to each other or may be different from each other.

[0206] In the drawings, a plurality of protective layers are arranged on only one side of the substrate. Without being limited thereto, the substrate may include multiple protective layers on both sides. In addition, multiple or one protective layer may be placed on only one side of the substrate. Of course, that is also good.

[0207] The structure of one or both surfaces of the substrate is shown in FIG. 3a, FIG. 3b, FIG. 7a, FIG. 7b, FIG. The conductive pattern part and the protective part according to at least one of FIG. 9 may be arranged in various combinations. Of course.

[0208] 4a and 4b, the flexible circuit board according to the comparative example has a substrate 110. An upper conductive pattern portion CP is disposed on an upper surface of the substrate 110, and a lower conductive pattern portion CP is disposed on a lower surface of the substrate 110. At this time, the upper conductive pattern portion CP and the lower conductive pattern portion CP are disposed. The printing process of the protective layer 140 is not taken into consideration when designing the core section CP. The upper conductive pattern portion CP is present on the upper surface of the substrate 110. The lower surface of the conductive pattern portion CP may include an area where the lower conductive pattern portion CP does not exist. The lower surface of the substrate 110 perpendicularly overlapping the surface on which the upper conductive pattern portion CP is disposed is provided with: There is a region where the lower conductive pattern portion CP is not disposed.

[0209] At this time, the lowermost surface of the flexible circuit board according to the comparative example is the lower conductive pattern. In the region where the lower conductive pattern portion CP exists, the lower conductive pattern portion CP is formed. The area where the functional pattern portion CP does not exist constitutes the lower surface of the substrate 110.

[0210] Then, a protective layer 140 is printed on the upper surface of the substrate 110, In the region where the chip portion CP is not arranged and where the chip portion CP is vertically overlapped, the lowermost surface is The lower surface of the conductive film 10 is the same as that of the lower surface of the conductive film 10, so that pinholes do not occur. In a state where the protective layer 140 is printed on an area where the conductive pattern portion CP does not exist, When the lower conductive pattern portion CP suddenly appears, the end of the lower conductive pattern portion CP and the vertical In the upper region of the substrate 110 overlapping the substrate 110, a sudden step occurs, causing a jumping phenomenon. Therefore, in the conventional method, the lower dummy pattern portion DP1 is first arranged at the end portion. The splashing phenomenon occurs in the area where the protective layer 140 is disposed. This will result in pinhole problems that are not fixed.

[0211] Meanwhile, as shown in FIG. 4b, in the present invention, the upper conductive pattern portion CP is disposed The lower dummy pattern portion DP1 is formed on the lower surface of the substrate 110 which is vertically overlapped with the region where the lower dummy pattern portion DP1 is formed. By disposing the protective layer 140, the generation of the step is eliminated, and a uniform protective layer 140 is formed. can be done.

[0212] The lower dummy pattern portion DP1 is a dummy pattern portion of the upper conductive pattern portion CP. That is, as shown in FIG. 4b, the lower conductive pattern portion CP The upper surface of the substrate 110 that vertically overlaps the area where no conductive paste is disposed is provided with three upper conductive pastes. It can be seen that the turn portion CP is disposed. The lower surface is provided with a first lower conductive pattern portion CP corresponding to each of the three upper conductive pattern portions CP. Dummy pattern portion DP1, second lower dummy pattern portion DP1 and third lower dummy pattern The parts DP1 are arranged in the respective

[0213] Meanwhile, the pinhole development in the protective layer 140 as described above occurs when the substrate on which the protective layer 140 is printed is The position where the first upper conductive pattern portion CP starts on the upper surface of 110 and the lower surface of the substrate This is because the positions at which the first lower conductive pattern portion CP starts are different from each other. , the lower portion of the first upper conductive pattern portion CP is located at a position where the first upper conductive pattern portion CP starts, based on the left end of the substrate. This is because the position where the conductive pattern portion CP starts is far away.

[0214] Therefore, the pinhole development occurs at the position where the first upper conductive pattern portion CP starts and the This can also be solved by making the starting positions of the lower conductive pattern portion CP the same.

[0215] That is, as shown in FIG. 5a, when the region A in FIG. 3a is enlarged, the upper surface of the substrate 110 is Make sure that the four upper conductive pattern parts CP are arranged around the left edge. The bottom surface of the substrate 110 has two lower conductive pads, one at the left end and the other at the right end. It can be seen that the turn part CP is arranged. That is, the four upper conductive layers The lower conductive pattern portion CP is located at the third upper conductive pattern portion CP. It can be seen that the conductive pattern portion CP starts first.

[0216] Therefore, in the present invention, the first upper conductive pattern portion on the lower surface of the substrate 110 A lower dummy pattern part DP1 is disposed on the region vertically overlapping with the CP. The left end of the upper conductive pattern portion of the second conductive pattern portion and the left end of the lower dummy pattern portion DP1 are mutually spaced apart. That is, on the upper and lower surfaces of the substrate 110, The starting position of the first upper conductive pattern portion CP and the lower dummy pattern portion DP1 The starting position was the same. And the area vertically overlapping with the second upper conductive pattern part CP The lower conductive pattern portion CP and the lower dummy pattern portion DP1 are not disposed above the It's okay.

[0217] That is, the lower portion of the substrate 110 overlapping the starting position of the first upper conductive pattern portion CP When the lower conductive pattern portion CP is not disposed on the surface, the first upper conductive pattern portion The lower dummy pattern is formed only on the lower surface of the substrate 110 that overlaps with the start position of the turn portion CP. By providing a pinhole portion DP1, the pinhole phenomenon can be solved.

[0218] However, the pinhole development is completed by using the one lower dummy pattern portion DP1. In order to solve this problem, the width of the lower dummy pattern portion DP1 is set to be equal to that of the first upper conductive pattern portion DP2. It is preferable that the width of the groove portion CP is larger than that of the groove portion CP.

[0219] In contrast, as shown in FIG. 5b, the first upper conductive layer on the lower surface of the substrate 110 A lower dummy pattern portion DP1 is disposed in an area vertically overlapping with the pattern portion CP. At this time, the left end of the first upper conductive pattern portion and the lower dummy pattern portion DP1 The left ends of the substrate 110 are not aligned vertically to each other. , the starting position of the first upper conductive pattern portion CP and the lower dummy pattern portion DP1 The starting positions of the pinhole development are not the same. To solve this problem, the protective layer 140 is first placed on the surface to be printed. From the start position of the printing pattern section CP and the dummy pattern sections DP1 and DP2 Therefore, the starting position of the pattern that is initially placed on the surface opposite to the surface to be printed must be early.

[0220] Therefore, in the present invention, the substrate is formed from the starting position of the first upper conductive pattern portion CP. In order to make the starting position of the lower dummy pattern portion DP1 arranged on the lower surface of 110 earlier, The first upper conductive pattern portion CP is vertically overlapped with the lower surface of the substrate 110. A lower dummy pattern portion DP1 is formed.

[0221] That is, the distance from the left end of the substrate 110 to the left end of the lower dummy pattern portion DP1 is The distance is from the left end of the substrate 110 to the left end of the first upper conductive pattern portion CP. Make it closer than the distance.

[0222] In conclusion, the lower dummy pattern CP is formed by dividing the first upper conductive pattern portion CP into the lower dummy pattern portion CP. The first upper conductive portion DP1 has a first gap a. The width of the functional pattern portion CP has a first width b, and the width of the lower dummy pattern portion DP1 is It has a second width c which is wider than the first width b.

[0223] According to this, in the present invention, the pinhole is prevented from being damaged by forming a minimum of dummy pattern parts. This can solve the problem of roll development.

[0224] Also, as shown in FIG. 5c, the lower dummy pattern portion DP1 may have a third width d. In this case, the third width d is the width of the first upper conductive pattern portion CP, the width of the th upper conductive pattern portion CP, and the width of the first upper conductive pattern portion CP The width corresponds to the total width of the gaps between the second upper conductive pattern portions CP.

[0225] That is, in FIG. 4b, the first upper conductive pattern portion CP is provided below the first upper conductive pattern portion CP. A first lower dummy pattern portion DP1 having the same width as the lower conductive pattern portion CP is formed. The second upper conductive pattern portion CP is provided at the bottom of the second upper conductive pattern portion CP. A second lower dummy pattern portion DP1 having the same width was formed.

[0226] In contrast, as shown in FIG. 5c, the first upper conductive pattern portion CP is 1 to the bottom surface of the substrate 110 corresponding to the end position of the second upper conductive pattern portion CP. Only one conductive pattern portion CP can be formed.

[0227] On the other hand, the dummy pattern portions DP1 and DP2 in the present invention have various shapes. That is, the dummy pattern portions DP1 and DP2 are formed by printing the protective layer 140. It is placed to eliminate the step at the bottom of the printing surface, so the thickness of the pattern part is made conductive. It is only necessary to maintain the thickness of the pattern portion CP the same as that of the dummy pattern portion CP. DP1 and DP2 can have a horizontally extending bar shape as shown in FIG. 5d(a). It can have a vertically extending bar shape as in (b) or a circular shape as in (c). and (d) may have a circular (ring-like) shape with an open center. , (e) can have a square shape (ladder shape) with an open center. The shapes of the dummy patterns DP1 and DP2 in the present invention are not limited to those shown. The shape can be changed into various shapes such as an ellipse, a sector, a polygon, or a triangle.

[0228] 6, when the region B in FIG. 3a is enlarged, the upper surface of the substrate 110 has an upper dummy layer. The upper dummy pattern portion DP2 is disposed. The conditions are the same as those for forming the lower dummy pattern portion DP1. The right end of the plate 110 is located in front of the starting position of the first lower conductive pattern portion CP. When the start position of the upper conductive pattern portion CP is delayed, the lower conductive pattern portion CP that is initially positioned An upper dummy pattern portion DP2 is formed on the upper surface of the substrate 110, which is vertically overlapped with the start of the turn portion CP. At this time, the upper dummy pattern portion DP2 is formed on each of the lower conductive patterns. The lower conductive pattern is arranged in multiple locations to correspond to the CP. Alternatively, one may be formed to correspond to the core portion CP.

[0229] 3a, 3b, 7a, 7b, 8, 10 and 11, according to an embodiment. A first chip C mounted on a double-sided all-in-one COF flexible circuit board 100 1. The connection relationship between the display panel 30 and the main board 40 will be described.

[0230] The double-sided all-in-one COF flexible circuit board 100 according to the embodiment has through holes. and a wiring board arranged on each side of the substrate including the through hole. A turn layer 120, a first plating layer 131 disposed on the wiring pattern layer 120, A second plating layer 132 disposed on the first plating layer 131 and a second plating layer 132 disposed on the wiring pattern layer It may include a protective layer 140 disposed partially thereover.

[0231] The region in which the protective layer 140 is formed is the protective portion PP. In a region other than the protective portion PP where the protective layer is not formed, the conductive pattern portion The CP is exposed to the outside, i.e., it is protected on the open area or conductive pattern of the protective layer. In the region where the protective portion is not arranged, the conductive pattern portion CP is The display panel 30 and the main board 40 are electrically connected.

[0232] The lead pattern portion and the lead of the all-in-one COF flexible circuit board according to the embodiment The lead pattern portion does not have to overlap with the protective portion. The test pattern portion is a conductive pattern located in an open area not covered by a protective layer. It can be divided into a lead pattern part and a test pattern part according to the function. It can be distinguished.

[0233] The lead pattern portion is connected to the first chip, the second chip, and the display panel. Alternatively, it may refer to a conductive pattern part for connection to the main board.

[0234] The test pattern section is a flexible circuit board for all-in-one COF according to an embodiment. Conductive pattern for checking the presence or absence of defects in chip packages including the same can mean:

[0235] The lead pattern portion is divided into an inner lead pattern portion and an outer lead pattern portion according to the position. It can be distinguished from the turn part. It is placed relatively close to the first tip C1 and has a retention The area of ​​the conductive pattern that is not overlapped by the protective layer is referred to as the inner lead pattern. The first chip C1 is located relatively far away from the first chip C2 and is covered by a protective layer. The area of ​​the conductive pattern portion that is not to be exposed can be expressed as an outer lead pattern portion. do.

[0236] Referring to Figs. 3a, 3b, 7a, 7b, 8, 10 and 11, the embodiment The all-in-one COF flexible circuit board 100 has a first inner lead pattern portion I1, a second inner lead pattern portion I2, a third inner lead pattern portion I3, and 4 may include an inner lead pattern portion I4.

[0237] The all-in-one COF flexible circuit board 100 according to the embodiment has a first outer rib a second outer lead pattern portion O2, a third outer lead pattern portion O3, and a fourth outer lead pattern portion O4. The fourth outer lead pattern portion O3 and the fourth outer lead pattern portion O4 may be included.

[0238] The all-in-one COF flexible circuit board 100 according to the embodiment is a first test pattern. The test pattern portion may include a first test pattern portion T1 and a second test pattern portion T2.

[0239] On one surface of the all-in-one COF flexible circuit board 100 according to the embodiment, The first inner lead pattern portion I1, the second inner lead pattern portion I2, 3 inner lead pattern portion I3, the first outer lead pattern portion O1, and the 2, an outer lead pattern portion O2 is disposed.

[0240] The opposite side of the flexible circuit board 100 for all-in-one COF according to the embodiment On the other surface, the fourth inner lead pattern portion I4 and the third outer lead pattern portion I5 are provided. The turn portion O3, the fourth outer lead pattern portion O4, and the first test pattern portion T1 and the second test pattern unit T2.

[0241] A flexible circuit board 100 for all-in-one COF according to the embodiment is arranged on one surface of the flexible circuit board 100. The first chip C1 is connected to the first inner lead pattern portion through the first connection portion 70. I1, the second inner lead pattern portion I2 or the third inner lead pattern portion It is connected to I3.

[0242] The first connection portion 70 is divided into a first sub-second connection portion 71 and a second sub-second connection portion 72 according to the position and / or function. The first connecting portion 72 and the third sub-first connecting portion 73 may be included.

[0243] A flexible circuit board 100 for all-in-one COF according to the embodiment is arranged on one surface of the flexible circuit board 100. The first chip C1 is connected to the first inner lead through the first sub-first connection portion 71. The insulating layer 11 is electrically connected to the insulating pattern portion I1.

[0244] The first inner lead pattern portion I1 is formed by forming a second via hole along the upper surface of the substrate 110. The first outer lead pattern portion O1 adjacent to the first outer lead pattern portion V2 can transmit an electrical signal. The second via hole V2 and the first outer lead pattern portion O1 are electrically That is, the first inner lead pattern portion I1 and the first outer lead The conductive pattern portion O1 may be one end and the other end of a conductive pattern portion extending in one direction. stomach.

[0245] For example, the main board 40 is connected to the first outer lead pattern portion O1. Therefore, the signal transmitted from the first chip is transmitted to the first The first outer lead pattern portion O1 is connected to the inner lead pattern portion I1. It is transmitted to the inboard 40.

[0246] The first inner lead pattern portion I1 is formed along the upper surface of the substrate 110. A conductive material is electrically connected to the second via hole V2 and filled in the second via hole V2. A third outer via hole V2 is formed along the lower surface of the substrate 110 through the third outer via hole V3. The second via hole V2 can transmit an electrical signal to the lead pattern portion O3. is electrically connected to the third outer lead pattern part O3. However, the main board 40 is attached to the third outer lead pattern portion O3 by an adhesive layer. Of course, electrical connection can be made through 50.

[0247] A flexible circuit board 100 for all-in-one COF according to the embodiment is arranged on one surface of the flexible circuit board 100. The first chip C1 is connected to the second inner lead through the second sub-first connection portion 72. The insulating layer 11 is electrically connected to the conductive pattern portion I2.

[0248] The second inner lead pattern portion I2 disposed on the upper surface of the substrate 110 is 2. A conductive material filled in the first via hole V1 located under the inner lead pattern portion I2 A fourth via hole adjacent to the first via hole V1 is formed along the lower surface of the substrate 110 through a conductive material. The inner lead pattern portion I4 and the first test pattern portion T1 are electrically connected to the inner lead pattern portion I4. The first via hole V1, the first test pattern portion T1 and the fourth via hole V2 may be formed by forming a first via hole V3 and a second via hole V4. The inner lead pattern portion I4 is electrically connected to the lower surface of the substrate.

[0249] The fourth inner lead pattern portion I4 and the fourth outer lead pattern portion O4 are A display panel 30 is attached.

[0250] The first test pattern portion T1 is a portion of the first via hole V1. For example, the first test pattern part T1 can be used to check for a signal defect. The accuracy of the signal transmitted to the fourth inner lead pattern portion I4 can be confirmed. Specifically, the voltage or current is measured in the first test pattern area T1. A short circuit or short circuit in a conductive pattern portion located between the first chip and the display panel It is possible to check the occurrence and location of defects, thereby improving product reliability.

[0251] A flexible circuit board 100 for all-in-one COF according to the embodiment is arranged on one surface of the flexible circuit board 100. The first chip C1 is connected to the third inner lead through the third sub-first connection portion 73. The insulating layer 11 is electrically connected to the insulating pattern portion I3.

[0252] The third inner lead pattern portion I3 is formed by forming a third via hole along the upper surface of the substrate 110. The second outer lead pattern portion O2 adjacent to the terminal V3 can transmit an electrical signal. The third via hole V3 and the second outer lead pattern portion O2 are electrically That is, the third inner lead pattern portion I3 and the second outer lead The conductive pattern portion O2 may be one end and the other end of a conductive pattern portion extending in one direction. stomach.

[0253] The third inner lead pattern portion I3 is a third inner lead pattern portion I4 extending along the upper surface of the substrate 110. A conductive material is electrically connected to the third via hole V3 and is filled in the third via hole V3. A fourth outer via hole V3 is disposed along the lower surface of the substrate 110 through the fourth outer via hole V4. The lead pattern portion O4 and the second test pattern portion T2 are connected to the lead pattern portion O4. can.

[0254] The second via hole V2, the fourth outer lead pattern portion O4, and the second test The pattern portion T2 is electrically connected to the lower surface of the substrate.

[0255] As described above, the fourth inner lead pattern portion I4 and the fourth outer lead pattern The display panel 30 is attached onto the bottom portion O4 via an adhesive layer 50.

[0256] The second test pattern portion T2 is electrically connected through the third via hole V3. For example, the second test pattern portion T2 can be used to check for a signal defect. The accuracy of the signal transmitted to the fourth outer lead pattern portion O4 can be confirmed. Specifically, the voltage or current is measured in the second test pattern area T2. A short circuit or short circuit in a conductive pattern portion located between the first chip and the display panel It is possible to check the occurrence and location of defects, thereby improving product reliability.

[0257] In the all-in-one COF flexible circuit board according to the embodiment, the first chip C1 is The display panel 30 can be disposed on the opposite side of the one side on which the display panel 30 is disposed, and the freedom of design is increased. In addition, the surface on which multiple chips are mounted can be made thinner. By disposing the display panel, effective heat dissipation is possible. This improves the reliability of all-in-one COF flexible circuit boards.

[0258] FIG. 10 is a plan view of FIG. 7a, and FIG. 11 is a bottom view of FIG. 7a.

[0259] Referring to FIG. 10 and FIG. 11, the flexible circuit board for all-in-one COF according to the embodiment is For the convenience of manufacturing or processing, the plate 100 has sprocket holes on both sides in the length direction. Therefore, the all-in-one COF flexible circuit board 100 can be provided with The wire is wound and unwound by the sprocket holes in the ROLL to ROLL method. Or it is done.

[0260] The all-in-one COF flexible circuit board 100 is cut along the dotted line. In the above, the inner region IR and the outer region OR can be defined.

[0261] The inner region IR of the all-in-one COF flexible circuit board 100 includes a first chip. , a conductive pad for connecting the second chip, the display panel and the main board, respectively. The turn portion is disposed.

[0262] The sprocket holes of the all-in-one COF flexible circuit board 100 are formed. By cutting the damaged part and placing the chip on the substrate, an all-in-one COF flexible substrate is created. The printed circuit board 100 is processed into a chip package and an electronic device including the chip package. It is possible.

[0263] Referring to FIG. 11, the upper surface of the flexible circuit board 100 for all-in-one COF is Then, a portion of the conductive pattern portion CP is exposed through the first open area OA1 of the protective layer 140. The first inner lead pattern portion I1 and the second inner lead pattern portion I The third inner lead pattern portion I2 and the third inner lead pattern portion I3 are exposed to the outside.

[0264] In addition, on the upper surface of the all-in-one COF flexible circuit board 100, the protective The conductive pattern portion CP is formed through the third open area OA3 of the layer 140. One outer lead pattern portion O1 is exposed to the outside.

[0265] The first inner lead pattern portion I1 and the third inner lead pattern portion I3 are , may be a conductive pattern portion for being connected to a chip via a first connection portion.

[0266] The end of the first inner lead pattern portion I1 and the third inner lead pattern portion The ends of I3 are arranged in a row. For example, the The first inner lead pattern portions I1 are spaced apart from each other, and the first inner lead pattern portions I For example, the ends of the third electrodes are arranged in a row in the lateral direction (x-axis direction) of the substrate. The inner lead pattern portions I3 are spaced apart from each other, and the third inner lead pattern portion I3 The ends are arranged in a line. The inner lead pattern portion I3 has excellent bonding with the first connection portion and the first chip.

[0267] The second via holes V2 are spaced apart from each other in the horizontal direction (x-axis direction) of the substrate and are arranged in a row. The third via holes V3 are spaced apart from each other in the horizontal direction (x-axis direction) of the substrate. and arranged in a row.

[0268] The end of the first inner lead pattern portion I1 is It is spaced apart from the end of I2.

[0269] The second inner lead pattern portion I2 is a conductive portion that is not bonded to the first chip. The second inner lead pattern portion I2 may be a pattern. At least one of the ends may not be aligned.

[0270] For example, the second inner lead pattern portions I 2 may be spaced apart from each other. At least one end of the first inner ring is closer to the lateral direction (x-axis direction) of the substrate. The distance between the end of the second inner lead pattern portion I1 and the second inner lead pattern portion I2 is reduced. At least one of the ends of I2 is as follows: The distance from the end of the first inner lead pattern portion I1 increases.

[0271] The first via holes V1 are spaced apart from each other in the lateral direction (x-axis direction) of the substrate. are placed in a row.

[0272] The length between one end and the other end of the second inner lead pattern portion I2 is The first set portion of the second inner lead pattern portion I2 gradually decreases in the x-axis direction. Specifically, one end and the other end of the second inner lead pattern portion I2 may include The length between the first and second lengths gradually decreases in the horizontal direction (x-axis direction) of the board. The second inner lead pattern portion I2 may include a first set portion. The length may be greater than the second length. Thus, on the substrate 110, a first set of The second inner lead pattern portion I2 may include a portion having a length gradually decreasing from the second inner lead pattern portion I2. The second inner lead pattern portion I2 has a length and the second inner lead pattern adjacent thereto. The loop portion I2 may again have a first length. The second inner lead pattern portion I gradually decreases in length from the first length to the second length. 2, and the second inner lead having a length gradually decreasing from a first length to a second length. The first set of pattern portions I2 is repeated.

[0273] At least one of the ends of the second inner lead pattern portion I2 is The closer to the lateral direction (x-axis direction) of the substrate, the closer the end of the first inner lead pattern portion I1 becomes. The separation distance decreases.

[0274] The first inner lead pattern portions I1 are spaced apart from each other at a first interval. The second inner lead pattern portion I1 is formed in the region between two adjacent first inner lead pattern portions I1. One end of the lead pattern portion I2 may be located thereon.

[0275] In the lateral direction of the substrate, an end of the first inner lead pattern portion I1 and an end of the second inner lead pattern portion I2 are The ends of the inner lead pattern portions I2 are arranged alternately.

[0276] Referring to FIG. 11, the bottom surface of the flexible circuit board 100 for all-in-one COF is Then, a part of the conductive pattern portion CP is exposed through the third open area OA3 of the protective layer 140. The fourth inner lead pattern portion I4 and the fourth outer lead pattern portion O4 are is exposed to the outside.

[0277] 7b and 12 to 16, a double-sided all-in-one COF flexible board according to an embodiment of the present invention will be described. A chip package including a first chip C1 and a second chip C2 on a flexible circuit board 100. will be explained in detail.

[0278] FIG. 12 shows a flexible circuit board 100 for double-sided all-in-one COF according to an embodiment. FIG. 2 is a schematic plan view of a chip package including the

[0279] Referring to FIG. 12a and FIG. 12b, a flexible circuit for a double-sided all-in-one COF according to an embodiment of the present invention is shown. The circuit board 100 has a first chip C1 and a second chip C2 arranged on the same surface. It can include.

[0280] The double-sided all-in-one COF flexible circuit board 100 according to the embodiment has a lateral direction (x The length in the vertical direction (y-axis direction) may be greater than the length in the vertical direction (y-axis direction). The double-sided all-in-one COF flexible circuit board 100 according to the embodiment has two lateral It can have a long side and two short sides running lengthwise.

[0281] The first chip C1 and the second chip C2 each have a length in the horizontal direction (x-axis direction) of In other words, the first chip C1 may have a length greater than the length in the y-axis direction. The second chip C2 may have two long sides in the horizontal direction and two short sides in the vertical direction. Cut.

[0282] The long side of the double-sided all-in-one COF flexible circuit board 100 according to the embodiment is Since the long sides of the first chip C1 and the long sides of the second chip C2 are arranged parallel to each other, Multiple chips can be efficiently mounted on one double-sided all-in-one COF flexible circuit board 100. It can be efficiently deployed.

[0283] The length (long side) of the first chip C1 in the horizontal direction is equal to the length (long side) of the second chip C2 in the horizontal direction. The length (short side) of the first chip C1 in the vertical direction may be longer than the length (short side) of the first chip C1. 1, may have a length smaller than the length (short side) of the second chip C2 in the vertical direction. Referring to FIG. 3a, the second chip C2 is disposed under the first chip C1. The long side of the first chip C1 and the long side of the second chip C2 may overlap each other vertically.

[0284] Referring to FIG. 13b, the second chip C2 is disposed on the side of the first chip C1. The long side of the first chip C1 and the long side of the second chip C2 do not need to overlap each other. .

[0285] The first chip C1 is a driving IC chip, and the second chip C2 is a diode chip. chip, power IC chip, touch sensor IC chip, MLCC chip, BGA chip, chip The second chip C2a of one of the capacitors and the diode chip, the power supply IC Chip, Touch sensor IC chip, MLCC chip, BGA chip, Chip capacitor . . , and a second chip C2b different from any one of the first and second chips C2a, C2b, C2b, and C2b.

[0286] 13 to 16, a flexible circuit for double-sided all-in-one COF according to an embodiment is shown. The steps of manufacturing a chip package including a circuit board will now be described.

[0287] FIG. 13 is a plan view of a double-sided all-in-one COF flexible circuit board 100 according to an embodiment. FIG.

[0288] Referring to FIG. 13a and FIG. 13b, a double-sided all-in-one COF flexible board according to an embodiment of the present invention is shown. The protective layer 140 located on one side of the flexible circuit board 100 may include a plurality of holes. That is, the protective layer 140 may include a plurality of open areas.

[0289] The first open area OA1 of the protective layer is exposed to be connected to the first connection part 70. The conductive pattern portion exposed in the first open area OA1 of the protective layer may be a conductive pattern portion exposed in the first open area OA1 of the protective layer. The CP may include a pure plating on a surface facing the first connection portion. The tin of the second plating layer included in the conductive pattern portion CP in the first open area OA1 The content may be 50 atomic % or more.

[0290] The second open area OA2 of the protective layer is exposed to be connected to the second connection part 80. The conductive pattern portion exposed in the second open area OA2 of the protective layer may be a conductive pattern portion exposed in the second open area OA2 of the protective layer. The CP may include a copper and tin alloy layer on a surface facing the second connection portion. The second plating included in the conductive pattern portion CP in the second open area OA2 of the protective layer The layer may have a tin content of less than 50 atomic %.

[0291] The first open area OA1 may be an area for connecting a first chip. The third open area OA3 is extended from the first outer lead pattern portion O1. The first inner lead pattern portion I1 facing the inside of the first open area OA1 is The first outer lead pattern may have a width corresponding to each other or may have a different width. For example, The width W1 of the first inner lead pattern portion O1 may correspond to the width W2 of the first inner lead pattern portion I1. For example, the width W1 of the first outer lead pattern portion O1 is The width of the first outer layer may be greater than the width W2 of the pattern portion I1. The width W1 of the first lead pattern portion O1 is 1 / 2 the width W2 of the first inner lead pattern portion I1. The difference may be within 20%.

[0292] The first inner lead pattern extends toward the inside of the first open area OA1. The lead portion I1 and the third inner lead pattern portion I3 have widths corresponding to each other. can be done.

[0293] The first outer lining extends from the first open area OA1 toward the outer edge of the substrate. The first outer lead pattern portion O1 and the second outer lead pattern portion O2 have widths corresponding to each other. Therefore, the first chip having a fine line width and requiring a large number of first connection parts can be manufactured. The first chip has a larger line width and requires fewer secondary connections, and the second chip is integrated into one all-in-one package. All can be mounted on the flexible circuit board 100 for one COF. At this time, the fine line width is , the first outer lead pattern portion O1 and the second outer lead pattern portion O2 Any one of the line widths is the fifth outer lead pattern portion O5 and the sixth outer lead pattern It can be said that the line width of the line portion O6 is smaller than that of any one of the lines. The width is either the outer lead pattern portion O5 or the sixth outer lead pattern portion O6. One line width is the first outer lead pattern portion O1 and the second outer lead pattern portion O2. The line width of any one of the fifth outer lead pattern portion O5 and the sixth outer lead pattern portion O2 is It can be said that the line width of the gate pattern portion O6 is relatively larger than that of any one of the gate pattern portions O1 and O2. do.

[0294] The all-in-one COF flexible circuit board 100 of the embodiment is A plurality of second open areas OA2 for connecting two chips C2a and C2b are provided. It can include.

[0295] The second open area OA2 is an area for connecting a second chip C2a. A fifth inner lead pattern located in the second open area OA2 may be The fifth outer lead pattern portion O5 extending from the portion I5 toward the outer edge of the substrate is For example, the width W of the fifth inner lead pattern portion I5 may be different from that of the fifth inner lead pattern portion I6. The fifth outer lead pattern portion O5 may have a width larger than the width W4 of the fifth outer lead pattern portion O5. Specifically, the width W3 of the fifth inner lead pattern portion I5 is It may be 1.5 times or more larger than the width W4 of the gate pattern portion O5.

[0296] The other second open area OA2 is used to connect the other second chip C2b. The sixth inner lead located in the second open area OA2 may be an area for A sixth outer lead pattern portion O6 extending from the pattern portion I6 toward the outer edge of the substrate For example, the sixth inner lead pattern portion I The width W5 of the sixth outer lead pattern portion O6 is greater than the width W6 of the sixth outer lead pattern portion O7. Specifically, the width W5 of the sixth inner lead pattern portion I6 is It may be 1.5 times or more larger than the width W6 of the outer lead pattern portion O6.

[0297] The width W3 and width W4 of the fifth inner lead pattern portion I5 exposed through the second open region are and the width W5 of the sixth inner lead pattern portion I6 is equal to or smaller than the width W1 of the first inner lead pattern portion I1. The width of the first inner lead pattern portion I1 exposed through the opening region is greater than the width W2 of the first inner lead pattern portion I1. Therefore, it is possible to provide leads that correspond to the first and second connection parts of various sizes / shapes. Since a dot pattern portion can be formed, the degree of freedom in design can be improved. For example, various sizes of inner leads are used to match different types of first and second tips. It can include various shapes of inner lead pattern parts, so it can be optimized Chip packaging is possible.

[0298] The shape of the inner lead pattern located under the first chip is the same as that of the second chip. The shape of the inner lead pattern portion located on the inner lead pattern portion may be different from that of the inner lead pattern portion located on the inner lead pattern portion. The first chip and the second chip can have excellent adhesion properties to each other. The inner lead pattern portion may have a different shape. Luinwan COF flexible circuit board is the bonding of the first chip and the second chip. Excellent characteristics.

[0299] That is, the inner lead pattern parts having different shapes are arranged on one substrate in different types. The first and second chips of the same type are mounted on the optimal pattern to ensure a certain bonding strength. It is a design.

[0300] The first inner lead pattern portion I1 has a rectangular stripe shape in a plan view. Specifically, in the plane of the first inner lead pattern portion I1, The shape of the stripe pattern is a rectangular stripe pattern that has a uniform width and extends in one direction. As an example, the width of one end and the other end of the first inner lead pattern portion I1 may be They may be the same.

[0301] For example, the fifth inner lead pattern portion I5 or the sixth inner lead pattern portion I6 The shape of the plane of the I6 section may be polygonal, circular, elliptical, mallet-shaped, T-shaped, or random. In particular, the fifth inner lead pad may have a protruding pattern having various shapes such as a The shape of the turn portion I5 or the sixth inner lead pattern portion I6 in a plane varies. A polygon, a circle, an ellipse, a mallet shape, a T shape, etc., having a width that is equal to or larger than the one direction and extending in a direction different from the one direction. The fifth inner rib may have a protruding pattern such as a letter shape, a random shape, etc. At least one of the lead pattern portion I5 and the sixth inner lead pattern portion I6 The fifth inner lead pattern portion may have a different width from one end to the other end. The sixth inner lead pattern portion I5 and the sixth inner lead pattern portion I6 are provided at their ends close to the protective layer. The width of the other end, which is the end far away from the protective layer, may be larger than the width at which the protective layer is placed. However, the fifth inner lead pattern portion I5 and the sixth inner lead pattern portion I6 are not limited thereto. The width of the inner lead pattern portion I6 at one end close to the protective layer is smaller than the width at the other end farther from the protective layer. Of course, the width of the other end, which is the portion, may be narrower.

[0302] For example, when the second chip is an MLCC chip, the inner lead pattern portion is , it may have a T-shape like the fifth inner lead pattern portion I5 of FIG. 13b.

[0303] For example, when the second chip is a BGA chip, the inner lead pattern portion is It may have a circular shape like the sixth inner lead pattern portion I6 in FIG. 13a. When the second chip is a BGA chip, the inner lead pattern portion is A shape having a semicircular shape or a rounded end like the sixth inner lead pattern I6 It can have a shape.

[0304] The first inner lead pattern portion and the first connection portion may have the same shape. For example, the planar shape (top view) of the first inner lead pattern portion and the first connection portion is Here, the first inner lead pattern portion and the The shape of the first connection part is the same means that the planar shape is the same polygon. , may include those of different sizes.

[0305] The fifth inner lead pattern portion and the second connection portion have shapes that are the same or different from each other. The sixth inner lead pattern portion and the second connection portion may have the same shape or may have the same shape. may be different.

[0306] 13a and 14a, the fifth inner lead pattern portion I5 has a planar shape The shape of the first connection portion may be a polygonal shape, and the planar shape of the second connection portion may be a circular shape. The sixth inner lead pattern portion I6 has a circular planar shape, and the second connection portion , may have a circular shape.

[0307] 13b and 14b, the fifth inner lead pattern portion I5 has a planar shape The shape of the first connecting portion is a polygonal shape, and the second connecting portion is a rectangular shape or an elliptical shape having rounded corners. The sixth inner lead pattern portion I6 may have a planar shape of a long semicircle. The second connection portion may have a circular shape.

[0308] The planar shape of the first connection portion 70 has a width and a length (aspect ratio) that correspond to each other or are different from each other. For example, the planar shape of the first connection portion 70 may be such that the horizontal length and vertical length (aspect ratio) are They have corresponding square shapes or rectangular shapes with different horizontal and vertical lengths (aspect ratios). It is possible.

[0309] The second connection portion 80 has a planar shape in which the horizontal length and the vertical length (aspect ratio) correspond to each other or are different from each other. For example, the planar shape of the second connection portion 80 may be such that the horizontal length and vertical length (aspect ratio) are The shapes may be circular or elliptical, with different horizontal and vertical lengths (aspect ratios). can.

[0310] The pitch between adjacent first outer lead pattern portions O1 is The fifth outer lead pattern portion O5 and the sixth outer lead pattern portion O6 adjacent to each other A second pitch between at least one of the outer lead pattern portions of O6. In this case, the first and second intervals may be smaller than the first and second intervals between two adjacent conductive patterns. It may refer to the average separation between the loop portions.

[0311] The first interval P1 may be less than 100 μm. For example, the first interval P1 is 30 μm. For example, the first interval may be 1 μm to 25 μm.

[0312] The second interval P2 may be 100 μm or more. For example, the second interval is 100 μm. For example, the second interval may be 100 μm to 300 μm. may have the following structure:

[0313] As a result, the conductive pattern portions connected to the first chip and the second chip are Signal interference can be prevented and signal accuracy can be improved.

[0314] In the first open area OA1, a plane of the first inner lead pattern portion I1 The product may correspond to or differ from the first connection portion 70 .

[0315] The width of the first inner lead pattern portion I1 and the width of the first connection portion 70 are the same. The difference between the first inner lead putter and the second inner lead putter may be within 20%. The first inner portion I1 and the first connecting portion 70 can be stably mounted. The adhesion characteristic between the lead pattern portion I1 and the first connecting portion 70 is improved.

[0316] In the second open area OA2, the fifth inner lead pattern portion I5 and the front A plane of any one of the sixth inner lead pattern portions I6 The product may correspond to or differ from the second connection 80 .

[0317] As an example, the width of the second connection portion 80 is equal to or larger than the width of the fifth inner lead pattern portion I5 and The width of any one of the sixth inner lead pattern portions I6 Therefore, the width of the second connection portion 80 may be 1.5 times or more larger than the width of the fifth inner connection portion 80. - Any one of the lead pattern portion I5 and the sixth inner lead pattern portion I6 and the front The second connecting portion 80 has improved adhesion characteristics.

[0318] 14a and 14b, the flexible circuit board 10 for all-in-one COF of the embodiment is The step of placing the first connecting portion 70 and the second connecting portion 80 on the substrate 10 will now be described.

[0319] The first inner lead pattern portion I1 exposed through the first open area OA1 and a first connection portion 70 is disposed on the third inner lead pattern portion I3. For example, the first connection portion 70 includes the first inner lead pattern portion I1 and the The upper surface of the third inner lead pattern portion I3 can be entirely or partially covered.

[0320] The first inner lead pattern portions I1 and I2 are spaced apart from each other. The total number of the third inner lead pattern portions I3 arranged in the first connection portion 7 It may correspond to the number 0.

[0321] For example, referring to FIG. 15a and FIG. 15b, a plurality of the first The number of the inner lead pattern portions I1 is nine, and the plurality of The number of the three inner lead pattern portions I3 is nine, and the number of the first connection portions 70 is The number of the inner lead pattern portions I1 is nine, and the third inner lead pattern portions I2 are spaced apart from each other. The total number of the lead pattern portions I1 and I2 is 9, which is 18.

[0322] The fifth inner lead pattern portion I5 exposed through the second open area OA2 and the sixth inner lead pattern portion I6 has a second connection portion 80 disposed thereon. For example, the second connection portion 80 includes the fifth inner lead pattern portion I5 and the The upper surface of the sixth inner lead pattern portion I6 can be covered entirely or partially.

[0323] The number of the fifth inner lead pattern portions I5 arranged at a distance from each other is 5 The number of the second connection parts 80 arranged on the inner lead pattern part I5 may be good.

[0324] For example, referring to FIG. 15a and FIG. 15b, a plurality of the fifth The number of the inner lead pattern portions I5 is two, and the fifth inner lead pattern portion I The number of the second connection portions 80 arranged on the first connection portion 5 is two.

[0325] The number of the sixth inner lead pattern portions I6 arranged at a distance from each other is 6 corresponds to the number of the second connection parts 80 arranged on the inner lead pattern part I6. good.

[0326] For example, referring to Figs. 15a and 15b, a plurality of the sixth inks are arranged at intervals. The number of the inner lead pattern portions I6 is three, and the sixth inner lead pattern portion I6 The number of the second connection portions 80 arranged on the first connection portion 80 is three.

[0327] The second connection portion 80 may be larger than the first connection portion 70. The fifth inner lead pattern portion I5 or the sixth inner lead pattern I6 exposed through the The width of the turn portion I6 is set to be equal to or larger than the width of the first inner lead pad exposed through the first open region. Since the width of the second connection portion 80 is larger than the width of the first connection portion 70, stomach.

[0328] 15a and 15b, an embodiment of an all-in-one COF flexible circuit board is shown. The step of placing the first chip C1 and the second chips C2a and C2b on the plate 100 will be described.

[0329] On the first connection portion 70, a first chip C1 is disposed.

[0330] On the second connection portion 80, a first chip C2 is disposed.

[0331] The first chip C1 and the second chip C2 are configured to prevent defects such as signal interference or disconnection, heat, In order to prevent problems such as defects caused by the above, they are spaced apart at a certain distance.

[0332] FIG. 16 shows a double-sided all-in-one COF flexible circuit board according to FIGS. 15a and 15b. 1 is a cross-sectional view of a chip package including a plate.

[0333] The first chip C1 and the second chip C2 are arranged on the same surface with different sizes. For example, the second chip C2 is larger than the first chip C1.

[0334] Via holes are disposed under the first chip C1 and the second chip C2. , the substrate 1 in the area corresponding to the first open area OA1 and the second open area OA2 10 may include a via hole.

[0335] The electrical signal of the second chip C2 passes through a conductive material disposed in the fourth via hole V4. Thus, the embodiment can be realized by forming a large number of conductive patterns at one The semiconductor device may be comprised on one substrate.

[0336] The all-in-one COF flexible circuit board 100 according to the embodiment has fine pins on both sides. The conductive pattern part of the light emitting diode can be realized, and the display part can have a high resolution. Fits your device.

[0337] In addition, the all-in-one COF flexible circuit board 100 according to the embodiment is a flexible It is easy to use, small in size and thin in thickness, so it can be used in a variety of electronic devices. do.

[0338] For example, referring to FIG. 17, a flexible circuit for all-in-one COF according to an embodiment of the present invention is shown. The substrate 100 can be used in edge displays, as it may reduce the bezel. Cut.

[0339] For example, referring to FIG. 18, a flexible circuit for all-in-one COF according to an embodiment of the present invention is shown. The substrate 100 can be included in a flexible electronic device. Therefore, a touch device including this can be a flexible touch device. Therefore, users can bend and twist it by hand. The touch window can be applied to wearable touch and the like.

[0340] For example, referring to FIG. 19, a flexible circuit for all-in-one COF according to an embodiment of the present invention is shown. The substrate 100 is applicable to various electronic devices to which a foldable display device is applied. Referring to FIG. 19a to FIG. 19c, the foldable display device is The foldable cover window can be folded. Foldable display device The device can be included in various portable electronic products. Ray devices are included in mobile terminals (cell phones), notebooks (portable computers), etc. This allows the display area of ​​portable electronic products to be enlarged while still allowing for easy storage and When moving, the size of the device can be reduced, and portability can be improved. It is possible to improve the convenience of users of portable electronic products. However, the embodiment is not limited thereto. The foldable display device is not limited to a single display device, but can be used in a variety of electronic products. Of course.

[0341] Referring to FIG. 19a, the foldable display device has one fold in the screen area. For example, a foldable display device may include a folded shape. That is, the foldable display device may have a C-shape at one end and at the front. The one end and the other end opposite to each other can be overlapped. At this time, the one end and the other end are close to each other. For example, the one end and the other end are disposed to face each other.

[0342] Referring to FIG. 19b, the foldable display device has two folds in the screen area. For example, a foldable display device may include a folded display area. That is, the foldable display device may have a G shape. The opposite ends of the two pieces are folded in the corresponding directions so that they overlap each other. At this time, the one end and the other end are disposed apart from each other. For example, the one end and the other end are are arranged parallel to each other.

[0343] Referring to FIG. 19c, the foldable display device has two folds in the screen area. For example, a foldable display device may include a folded shape. That is, the foldable display device may have an S-shape at one end and at the front. The one end and the other end opposite to the one end are bent in different directions. The ends are spaced apart from each other. For example, the one end and the other end are parallel to each other.

[0344] Although not shown, the all-in-one COF flexible circuit board according to the embodiment Of course, the board 100 can be applied to a rollable display.

[0345] Referring to FIG. 20, a flexible circuit board 10 for all-in-one COF according to an embodiment of the present invention is shown. 0 can be included in a variety of wearable touch devices, including curved displays. Therefore, the electric device including the all-in-one COF flexible circuit board 100 according to the embodiment The child device may be slimmer, smaller or lighter.

[0346] Referring to FIG. 21, a flexible circuit board 10 for all-in-one COF according to an embodiment of the present invention is shown. 0 is a device that has a display such as a TV, monitor, or notebook. It can be used for chairs.

[0347] In addition, the embodiment is not limited to this, and the all-in-one COF according to the embodiment The flexible circuit board 100 may be a multi-layer substrate having a flat or curved display portion. Of course, the present invention can be used in various electronic devices.

[0348] According to an embodiment of the present invention, a first chip and a second chip of different types are integrated into one frame. All-in-one CO that can be mounted on flexible circuit boards and has improved reliability Flexible circuit board chip packages for F can be provided.

[0349] In addition, according to an embodiment of the present invention, one all-in-one COF flexible circuit is provided. The display panel and main board are directly connected by a substrate, and the The size and thickness of the flexible circuit board that transmits the signals to the main board is reduced. This allows for more space for other components and / or battery space. It is possible.

[0350] In addition, according to the embodiment of the present invention, since it is not necessary to connect multiple PCBs, the process is simplified. Convenience and reliability of electrical connection are improved, enabling a high-resolution display unit. To provide an all-in-one COF flexible circuit board suitable for electronic devices This can be done.

[0351] According to the embodiment of the present invention, a circuit pattern corresponding to the circuit pattern arranged on the first surface of the substrate is formed. A dummy pattern is arranged on the second surface of the substrate so as to form a dummy pattern on the second surface of the substrate. A dummy pattern is disposed on the first surface of the substrate so as to correspond to the wiring pattern. Solder resist generated during printing of the solder resist on the first or second surface of the board This can solve the problems of the paste not being applied and pinholes.

[0352] The features, structures, advantages, etc. described in the above-described embodiments are included in at least one embodiment of the present invention. The present invention is not limited to one embodiment, but may be modified in any way without departing from the spirit and scope of the present invention. The features, structures, effects, etc. of the present invention may be easily understood by those having ordinary skill in the art to which the present invention pertains. The embodiments may be combined or modified. Such content is to be construed as being included within the scope of the present invention.

[0353] In addition, although the above description has been centered on the embodiment, this is merely an example and does not limit the present invention. It is understood that those skilled in the art will understand the essence of the present embodiment without departing from the spirit and scope of the present invention. Various modifications and applications not exemplified above are possible within the scope of the intended characteristics. For example, each component specifically presented in the embodiment can be modified and implemented. Such modifications and variations are within the scope of the present invention as defined in the appended claims. should be construed as being within the scope of

Claims

1. A substrate; A first wiring pattern layer disposed on a first surface of the substrate; a second wiring pattern layer disposed on a second surface of the substrate opposite to the first surface; The second wiring pattern layer is disposed in an area of ​​the second surface of the substrate where the second wiring pattern layer is not disposed. a first dummy pattern portion; a first protective layer disposed on the first wiring pattern layer; a second protective layer disposed on the second wiring pattern layer and the first dummy pattern portion; 、 Including, At least a part of the first dummy pattern portion is located on the first wiring pattern layer in the vertical direction. Overlapping flexible circuit board.

2. The first wiring pattern layer is disposed in an area of ​​the first surface of the substrate where the first wiring pattern layer is not disposed. a second dummy pattern having at least a portion vertically overlapping the second wiring pattern layer; The flexible circuit board of claim 1 further comprising a portion.

3. The first dummy pattern portion has the same width as the first wiring pattern layer, and one end of the first dummy pattern portion is 2. The flexible circuit of claim 1, wherein the first wiring pattern layer is disposed on the same vertical line as one end of the first wiring pattern layer. Road board.

4. The first dummy pattern portion has a width greater than that of the first wiring pattern layer, and one end of the first dummy pattern portion is The flexible substrate according to claim 1 , wherein the first wiring pattern layer is closer to an end of the substrate than one end of the first wiring pattern layer. Circuit board.

5. the first surface is a top surface of the substrate; the second surface is a lower surface of the substrate; The first dummy pattern portion is a second dummy pattern portion arranged at the leftmost side of the first wiring pattern layer. The flexible circuit board according to claim 2 , which is disposed to the left of the first wiring pattern layer.

6. The second dummy pattern portion is a second dummy pattern portion arranged on the rightmost side of the second wiring pattern layer. The flexible circuit board according to claim 2 , which is disposed to the right of the second wiring pattern layer.

7. a first plating layer including tin (Sn) disposed on the first wiring pattern layer; A second plating layer including tin (Sn) disposed on the second wiring pattern layer, The first dummy pattern portion includes a first dummy pattern corresponding to the second wiring pattern layer. a second dummy pattern layer corresponding to the second plating layer; The second dummy pattern portion includes a third dummy pattern corresponding to the first wiring pattern layer.

3. The method according to claim 2, further comprising: forming a first dummy pattern layer corresponding to the first plating layer; and forming a fourth dummy pattern layer corresponding to the first plating layer. Flexible circuit board.

8. All-in-one COF (All in one chip on film) flexible circuit boards are A substrate; A conductive pattern portion disposed on the substrate; a dummy pattern portion disposed on the substrate; A protection layer is disposed on the conductive pattern portion and the dummy pattern portion. Department and Including, The conductive pattern portion is a first wiring pattern layer disposed on a first surface of the substrate; a first plating layer disposed on the first wiring pattern layer; a second wiring pattern layer disposed on a second surface of the substrate opposite the first surface; a second plating layer disposed on the second wiring pattern layer; The tin (Sn) content of the plating layer in the first open region of the protective layer is the tin (Sn) content of the plating layer in the second open area is greater than the tin (Sn) content of the plating layer in the second open area; a first chip disposed in the first open area; a second chip disposed in the second open area; The dummy pattern portion is A second wiring pattern layer is disposed on the second surface of the substrate on which the second wiring pattern layer is not disposed. a first dummy pattern portion at least partially overlapping the first wiring pattern layer in a vertical direction; a first wiring pattern layer disposed on the first surface of the substrate on which the first wiring pattern layer is not disposed; and a second dummy pattern portion at least a part of which overlaps with the second wiring pattern layer in a vertical direction. Hmm, chip package.

9. the first surface is a top surface of the substrate; the second surface is a lower surface of the substrate; The first dummy pattern portion is a second dummy pattern portion arranged at the leftmost side of the first wiring pattern layer. It is located to the left of the first wiring pattern layer, The second dummy pattern portion is a second dummy pattern portion arranged on the rightmost side of the second wiring pattern layer.

9. The chip package of claim 8, which is disposed to the right of the second wiring pattern layer.

10. The first chip is a drive IC chip, The second chip includes a diode chip, a power supply IC chip, a touch sensor IC chip, At least one of the following is included: MLCC chip, BGA chip, and chip capacitor. The chip package according to claim 9, further comprising an all-in-one COF flexible circuit board. Page.

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