Semiconductor device

Abstract

To provide a semiconductor device of which the electrical characteristics are hardly varied even if operated under an environment where moisture is present.SOLUTION: An insulation layer consisting of an inorganic insulation material is provided on a top face, which is one face of a support substrate consisting of polymers or filler-containing polymers. A circuit formation layer including a semiconductor element is provided on the insulation layer. A bottom face, which is at the opposite side of the top face, and side faces of the support substrate are covered by a coating formed from a material having lower moisture permeability than that of the support substrate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A semiconductor device including an SOI-CMOS FET in which the silicon substrate of a silicon-on-insulator (SOI) substrate is removed and a semiconductor layer and an insulating layer made of silicon are transferred to a polymer substrate is disclosed in the following Patent Document 1. In the semiconductor device disclosed in Patent Document 1, an interface adhesive layer is provided at the interface between the polymer substrate and the insulating layer for the purpose of preventing the intrusion of moisture from the polymer substrate into the insulating layer and the semiconductor layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 9,812,350 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device disclosed in Patent Document 1, it is possible to suppress the deterioration of reliability caused by the intrusion of moisture into the insulating layer or the semiconductor layer. However, according to the study by the inventors of the present application, it was found that the electrical characteristics of the semiconductor device fluctuate when it is operated in an environment where moisture is present. It is believed that one of the causes of this fluctuation in electrical characteristics is distortion that occurs in the semiconductor layer as a result of expansion of the polymer substrate due to moisture absorption.

[0005] An object of the present invention is to provide a semiconductor device whose electrical characteristics are unlikely to fluctuate even when it is operated in an environment where moisture is present. [Means for solving the problem]

[0006] According to one aspect of the present invention, A supporting substrate made of a polymer or a filler-containing polymer; an insulating layer made of an inorganic insulating material provided on an upper surface, which is one surface of the support substrate; a circuit formation layer including a semiconductor element provided on the insulating layer; a coating covering a lower surface of the support substrate opposite to the upper surface and a side surface thereof, the coating being made of a material having a lower moisture permeability than the support substrate; A semiconductor device comprising:

[0007] According to another aspect of the invention, A supporting substrate made of a polymer or a filler-containing polymer; an insulating layer made of an inorganic insulating material provided on an upper surface, which is one surface of the support substrate; a circuit formation layer including a semiconductor element provided on the insulating layer; a coating film formed of an inorganic insulating material that covers a lower surface opposite to the upper surface and a side surface of the support substrate; A semiconductor device comprising: Effect of the Invention

[0008] The coating prevents moisture from penetrating into the support substrate, thereby preventing the support substrate from expanding due to moisture absorption, which reduces the risk of distortion in the semiconductor element and the resulting fluctuations in electrical characteristics. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 2A, 2B, 2C, and 2D are cross-sectional views of the semiconductor device according to the first embodiment at intermediate stages in its manufacture. [Diagram 3] 3A, 3B, and 3C are cross-sectional views of the semiconductor device according to the first embodiment during the manufacturing process. [Figure 4] FIG. 4 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment. [Diagram 5]FIG. 5 is a cross-sectional view of a semiconductor device according to the second embodiment. [Figure 6] 6A, 6B, and 6C are cross-sectional views of a semiconductor device according to the second embodiment during its manufacture. [Figure 7] FIG. 7 is a cross-sectional view of a semiconductor device according to a modification of the second embodiment. [Figure 8] FIG. 8 is a cross-sectional view of a semiconductor device according to another modification of the second embodiment. [Figure 9] FIG. 9A is a cross-sectional view of the semiconductor device according to the third embodiment, and FIG. 9B is a plan cross-sectional view taken along dashed line 9B-9B in FIG. 9A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [First Example] A semiconductor device according to a first embodiment will be described with reference to FIGS. 1 to 3C. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. An insulating layer 11 made of an inorganic insulating material is provided on one surface (hereinafter referred to as upper surface 10U) of a support substrate 10 made of a polymer or a filler-containing polymer. A lower surface 10L opposite to the upper surface 10U of the support substrate 10 and a side surface 10S are covered with a coating 18. The coating 18 is formed of an insulating material having a lower moisture permeability than the support substrate 10. An upper end of a portion of the coating 18 covering the side surface 10S of the support substrate 10 (an end surface along the upper surface 10U of the support substrate 10) is in contact with the lower surface of the insulating layer 11.

[0011] "Low moisture permeability" means that the moisture permeability is low when comparing films of the same thickness. "Moisture permeability" refers to the amount of water vapor that passes through a unit area of ​​a membrane-like material in a certain period of time. As an example, when a membrane-like material is used as an interface at a certain temperature, for example 25°C, and the air on one side is kept at a certain relative humidity, for example 90%, and the air on the other side is kept dry by a moisture absorbent, the mass of water vapor that passes through this interface in a certain period of time, for example 24 hours, is calculated as the mass of water vapor that passes through 1 m of that membrane-like material. 2 The value converted per unit can be defined as the moisture permeability of the film-like material.

[0012] The support substrate 10 is made of, for example, a resin containing a filler. Examples of the resin that can be used include epoxy resin, polyimide resin, and benzocyclobutene resin. The coating 18 is made of, for example, an inorganic insulating material such as silicon nitride (SiN), aluminum oxide (Al2O3), diamond-like carbon (DLC), etc. Alternatively, the coating 18 may be made of a polymer that has lower moisture permeability than the polymer used in the support substrate 10, such as a liquid crystal polymer (LCP).

[0013] A circuit formation layer 14 is disposed on the upper surface of the insulating layer 11. A semiconductor element 20, for example, a MOSFET 20, is provided on the circuit formation layer 14. More specifically, the circuit formation layer 14 includes a semiconductor layer 12 disposed on the insulating layer 11, a semiconductor element 20 provided on the semiconductor layer 12, and a multilayer wiring layer 13 disposed on the semiconductor layer 12. A plurality of terminals 17 for external connection are provided on the multilayer wiring layer 13.

[0014] A part of the semiconductor layer 12 is made into an insulating element isolation region 12I, and an active region surrounded by the element isolation region 12I is defined. A semiconductor element 20 is formed in this active region. The semiconductor element 20 is, for example, a MOSET including a source region 20S and a drain region 20D arranged in the active region of the semiconductor layer 12, and a gate electrode 20G arranged on the upper surface of the semiconductor layer via a gate insulating film (not shown). Although only one active region is shown in FIG. 1, multiple active regions may be provided. The semiconductor element 20 may also be a multi-finger type MOSFET.

[0015] The multi-layer wiring layer 13 includes a plurality of wirings 15 and a plurality of vias 16 arranged therein. Some terminals 17 are connected to the semiconductor element 20 via the wirings 15 and the vias 16. The total thickness of the semiconductor layer 12 and the multi-layer wiring layer 13 is, for example, 20 μm or less. For example, a bump structure is used as the terminal 17, and its height is, for example, about 160 μm. The thickness of the insulating layer 11 is, for example, preferably 100 nm or more and 1500 nm or less, and more preferably 200 nm or more and 1000 nm or less. The thickness of the support substrate 10 is, for example, about 100 μm. The thickness of the coating 18 is, for example, about 1 μm. The size of each component shown in FIG. 1 does not reflect the actual dimensions.

[0016] Next, a method for manufacturing a semiconductor device according to a first embodiment will be described with reference to Figures 2A to 3C. Figures 2A to 3C are cross-sectional views of a semiconductor device according to a first embodiment at intermediate stages in its manufacture. In Figures 2A to 3C, the semiconductor element 20, wiring 15, via 16, etc. of the circuit formation layer 14 are omitted.

[0017] As shown in Fig. 2A, an SOI substrate including a semiconductor substrate 41, an insulating layer 11, and a semiconductor layer 12 is prepared. The insulating layer 11 included in the SOI substrate is also called a buried silicon oxide layer (BOX layer). An element isolation region 12I, a semiconductor element 20, a multilayer wiring layer 13, a terminal 17 (Fig. 1), and the like are formed on the SOI substrate using a general semiconductor process technology.

[0018] As shown in Fig. 2B, a protective tape 42 is attached to the upper surfaces of the circuit formation layer 14 and the terminals 17. With the protective tape 42 attached, the semiconductor substrate 41 (Fig. 2B) is removed as shown in Fig. 2C. For example, wet etching can be used to remove the semiconductor substrate 41. Alternatively, back grinding and chemical mechanical etching (CMP) may be used. By removing the semiconductor substrate 41, the insulating layer 11 is exposed.

[0019] 2D, a support substrate 10 made of a filler-containing polymer is provided on the exposed surface of the insulating layer 11. The support substrate 10 is formed, for example, by adhering a polymer sheet by a lamination method and then heating it.

[0020] As shown in Fig. 3A, half-cut dicing is performed from the lower surface 10L of the support substrate 10 to form a groove 45 in the support substrate 10, the groove 45 reaching the lower surface of the insulating layer 11. As shown in Fig. 3B, the groove 45 is filled with a coating film 18, and the lower surface 10L of the support substrate 10 is covered with the coating film 18. The coating film 18 can be formed by, for example, chemical vapor deposition (CVD), sputtering, atomic layer deposition (ALD), or the like.

[0021] 3C, the wafer is separated into a plurality of chips by full-cut dicing at dicing points 46 where grooves 45 are formed. The width of the full-cut dicing is narrower than the width of grooves 45. Therefore, coating 18 remains on the side surfaces of grooves 45.

[0022] Next, the excellent effects of the first embodiment will be described. In the first embodiment, the coating 18, which has low moisture permeability, suppresses the intrusion of moisture into the support substrate 10 made of a polymer. As a result, the support substrate 10 is less likely to expand due to moisture absorption, and the semiconductor layer 12 is less likely to be distorted due to the expansion of the support substrate 10. This suppresses fluctuations in the electrical characteristics of the semiconductor element 20 due to the distortion of the semiconductor layer 12. In general, inorganic insulating materials have lower moisture permeability than polymers. Therefore, it is preferable to use an inorganic insulating material as the coating 18. Furthermore, the semiconductor substrate 41 (FIG. 2A) of the SOI substrate is removed and the support substrate 10 made of an insulating polymer is bonded, thereby improving the high frequency characteristics.

[0023] Next, the results of an evaluation experiment conducted to confirm the moisture resistance performance will be described. The semiconductor devices according to the first embodiment and the comparative example were left in a high-temperature and high-humidity environment (temperature 130°C, humidity 85%) for a certain period of time (96 hours), and the amount of change in threshold voltage of the semiconductor element 20 (FIG. 1) was measured. In the semiconductor device according to the comparative example not provided with the coating 18, the threshold voltage decreased by about 0.2 V before and after the humidity test, and the device changed from a normally-off type to a normally-on type. In contrast, in the semiconductor device provided with the coating 18 as in the first embodiment, no change in threshold voltage was observed before and after the humidity test. The effect of providing the coating 18 was confirmed by this evaluation experiment.

[0024] Next, a semiconductor device according to a modification of the first embodiment will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view of the semiconductor device according to a modification of the first embodiment. In the first embodiment (Fig. 1), the side surface of the insulating layer 11 is exposed and not covered with the coating 18. In contrast, in this modification, the coating 18 continuously covers the side surface 10S of the support substrate 10 to the side surface 11S of the insulating layer 11. The upper end face of the coating 18 contacts the lower surface of the element isolation region 12I formed in the semiconductor layer 12.

[0025] As in this modified example, coating 18 with low moisture permeability covers from side surface 10S of support substrate 10 to side surface 11S of insulating layer 11, thereby further enhancing the effect of suppressing the intrusion of moisture into support substrate 10.

[0026] [Second Example] Next, a semiconductor device according to a second embodiment will be described with reference to Figures 5 to 6C. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figures 1 to 3C will be omitted.

[0027] 5 is a cross-sectional view of a semiconductor device according to the second embodiment. In the first embodiment (FIG. 1), the coating 18 covers the side surface 10S of the support substrate 10, and the side surfaces of the insulating layer 11 and the circuit-formation layer 14 are exposed. In contrast, in the second embodiment, the coating 18 continuously covers the area from the side surface 10S of the support substrate 10, through the side surface 11S of the insulating layer 11, to the side surface 14S of the circuit-formation layer 14.

[0028] Next, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to Figures 6A, 6B, and 6C. Figures 6A, 6B, and 6C are cross-sectional views of the semiconductor device according to the second embodiment during the manufacturing process.

[0029] In the first embodiment, half-cut dicing is performed in the process shown in Fig. 3A, but in the second embodiment, full-cut dicing is performed from the lower surface 10L of the support substrate 10 to the upper surface 14U of the circuit formation layer 14, as shown in Fig. 6A. As a result, a groove 45 is formed that reaches from the lower surface 10L of the support substrate 10 to the protective tape 42.

[0030] Next, as shown in Fig. 6B, the grooves 45 are filled with the coating film 18, and the lower surface 10L of the support substrate 10 is covered with the coating film 18. The coating film 18 reaches the bottom surface (protective tape 42) of the grooves 45. Thereafter, as shown in Fig. 6C, the dicing portion 46 where the grooves 45 are formed is full-cut diced to separate into a plurality of chips. The coating film 18 remains on the side surface of the grooves 45.

[0031] Next, the advantageous effects of the second embodiment will be described. In the second embodiment, the coating 18 continuously covers from the side surface 10S of the support substrate 10 to the side surface 14S of the circuit formation layer 14, so that the effect of suppressing the intrusion of moisture into the support substrate 10 is further enhanced.

[0032] Next, a semiconductor device according to a modification of the second embodiment will be described with reference to FIGS. 7 is a cross-sectional view of a semiconductor device according to a modified example of Example 2. In Example 2 (FIG. 5), the thicknesses of the portions of coating 18 that cover side surface 10S of support substrate 10, side surface 11S of insulating layer 11, and side surface 14S of circuit-formation layer 14 are substantially constant.

[0033] 7, the thickness of the portions of the coating 18 covering the side surface 10S of the support substrate 10, the side surface 11S of the insulating layer 11, and the side surface 14S of the circuit-formation layer 14 gradually decreases from the end of the lower surface 10L of the support substrate 10 toward the end of the upper surface 14U of the circuit-formation layer 14. In other words, the thickness of the coating 18 covering the side surface 10S of the support substrate 10 is greater than the thickness of the coating 18 covering the side surface 11S of the insulating layer 11 and the side surface 14S of the circuit-formation layer 14.

[0034] The coating 18 having the thickness distribution shown in Fig. 7 can be obtained, for example, by employing a film-forming method with a low step coverage rate in the step of forming the coating 18 shown in Fig. 6B. In this modification, the portions of the coating 18 covering the lower surface 10L and the side surface 10S of the support substrate 10 have a sufficient thickness, so that the effect of suppressing the intrusion of moisture into the support substrate 10 can be obtained. Moreover, in the step of forming the coating 18, it is possible to employ a film-forming method with a low step coverage rate, so that the freedom of selection of the film-forming method is increased.

[0035] Fig. 8 is a cross-sectional view of a semiconductor device according to another modification of the second embodiment. In the modification shown in Fig. 8, similar to the modification shown in Fig. 7, the coating 18 gradually becomes thinner from the end on the lower surface 10L side of the support substrate 10 toward the end on the upper surface 14U side of the circuit-formation layer 14, and covers the area near the edge of the upper surface 14U of the circuit-formation layer 14. The thickness T2 of the portion of the coating 18 covering the upper surface 14U is equal to or less than the thickness of the portion covering the side surface 14S of the circuit-formation layer 14.

[0036] 6A, a gap may be generated at the interface between the protective tape 42 and the circuit-formation layer 14 around the groove 45. The coating 18 covering the upper surface 14U of the circuit-formation layer 14 is formed, for example, by the film-forming material penetrating into the gap when the coating 18 is formed. In this manner, the coating 18 may cover an area near the edge of the upper surface 14U of the circuit-formation layer 14.

[0037] [Third Example] Next, a semiconductor device according to a third embodiment will be described with reference to Figures 9A and 9B. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figures 1 to 3C will be omitted.

[0038] Fig. 9A is a cross-sectional view of the semiconductor device according to the third embodiment, and Fig. 9B is a plan cross-sectional view taken along dashed line 9B-9B in Fig. 9A. In the semiconductor device according to the third embodiment, as shown in Fig. 9A, the lower surface 10L and the side surface 10S of the support substrate 10 are covered with a coating film 18, similar to the semiconductor device according to the first embodiment (Fig. 1).

[0039] A guard ring 30 is provided that passes through the insulating layer 11 in the thickness direction from inside the circuit formation layer 14 and reaches the upper surface 10U of the support substrate 10. The guard ring 30 can be formed using a general semiconductor manufacturing process before removing the semiconductor substrate 41 (FIG. 2A) of the SOI substrate. The guard ring 30 is made of, for example, a metal, a nitride, or polycrystalline silicon.

[0040] The guard ring 30 includes a plurality of peripheral wirings 31 arranged in a plurality of wiring layers of the circuit formation layer 14, a plurality of via layers, an element isolation region 12I, and a peripheral via 32 arranged in the insulating layer 11. Each of the peripheral wirings 31 and the peripheral vias 32 (FIG. 9B) continuously surrounds the semiconductor element 20 when the upper surface 10U of the support substrate 10 is viewed in plan. That is, when the upper surface 10U of the support substrate 10 is viewed in plan, the guard ring 30 (FIG. 9B) continuously surrounds the semiconductor element 20.

[0041] Next, the excellent effects of the third embodiment will be described. In the third embodiment, the guard ring 30 prevents moisture from entering from the side surfaces of the insulating layer 11 and the circuit formation layer 14. This makes it possible to improve the moisture resistance of the semiconductor device.

[0042] The above-mentioned embodiments are merely examples, and it goes without saying that partial replacement or combination of the configurations shown in different embodiments is possible. Similar effects due to similar configurations of multiple embodiments are not mentioned in each embodiment. Furthermore, the present invention is not limited to the above-mentioned embodiments. For example, it will be obvious to those skilled in the art that various modifications, improvements, combinations, etc. are possible. [Explanation of symbols]

[0043] 10 Support substrate 10L Underside of support board 10S Side of the support board Top of 10U support board 11 Insulating layer 11S Insulation layer side 12 Semiconductor layer 12I Element isolation region 13 Multi-layer wiring layer 14 Circuit forming layer 14S Side of circuit formation layer 14U Top of circuit board 15 Wiring 16 Via 17 Terminal 18 Coating 20 Semiconductor elements 20D drain region 20G gate electrode 20S Source Area 30 Guard Ring 31 Periphery wiring 32 Periphery vias 41 Semiconductor Substrate 42 Protective Tape 45 Groove 46 Dicing points

Claims

1. A supporting substrate made of a polymer or a filler-containing polymer; an insulating layer made of an inorganic insulating material provided on an upper surface, which is one surface of the support substrate; a circuit formation layer including a semiconductor element provided on the insulating layer; a coating covering a lower surface of the support substrate opposite to the upper surface and a side surface thereof, the coating being made of a material having a lower moisture permeability than the support substrate; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the coating further covers from the side surface of the support substrate to the side surface of the insulating layer.

3. 3. The semiconductor device according to claim 2, wherein the coating further covers from a side surface of the insulating layer to a side surface of the circuit formation layer.

4. 4. The semiconductor device according to claim 3, wherein the thickness of the coating covering the side surfaces of the support substrate, the insulating layer, and the circuit formation layer decreases from the support substrate toward the circuit formation layer.

5. 5. The semiconductor device according to claim 1, further comprising a guard ring that extends from inside the circuit formation layer, passes through the insulating layer in a thickness direction, reaches the upper surface of the support substrate, and continuously surrounds the semiconductor element when the upper surface of the support substrate is viewed in a plan view.

6. A supporting substrate made of a polymer or a filler-containing polymer; an insulating layer made of an inorganic insulating material provided on an upper surface, which is one surface of the support substrate; a circuit formation layer including a semiconductor element provided on the insulating layer; a coating film formed of an inorganic insulating material that covers a lower surface opposite to the upper surface and a side surface of the support substrate; A semiconductor device comprising:

7. 7. The semiconductor device according to claim 6, wherein the coating further covers from the side surface of the support substrate to the side surface of the insulating layer.

8. 8. The semiconductor device according to claim 7, wherein the coating further covers from a side surface of the insulating layer to a side surface of the circuit formation layer.

9. 9. The semiconductor device according to claim 8, wherein the thickness of the coating covering the side surfaces of the support substrate, the insulating layer, and the circuit formation layer decreases from the support substrate toward the circuit formation layer.

10. The semiconductor device according to any one of claims 6 to 9, further comprising a guard ring made of metal that extends from inside the circuit formation layer, passes through the insulating layer in a thickness direction, reaches the upper surface of the support substrate, and continuously surrounds the semiconductor element when the upper surface of the support substrate is viewed in a plan view.

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