Epitaxial growth substrate and method for manufacturing semiconductor device

Abstract

To provide an epitaxial growth substrate capable of suppressing the occurrence of cracks on a semiconductor layer when separating a substrate from the semiconductor layer.SOLUTION: An epitaxial growth substrate includes: a substrate made of a group III-V compound semiconductor containing Ga or In as a group III element; a sacrificial layer epitaxially grown on the substrate; and a semiconductor layer epitaxially grown on the sacrificial layer. The sacrificial layer includes a layer consisting of a mixed crystal semiconductor containing Al or In as the group III element. The composition ratio of Al or In varies in a thickness direction. A portion where the composition ratio of Al or In exhibits a maximum value is located on the interior of the sacrificial layer, excluding the upper and lower surfaces.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an epitaxial growth substrate and a method for manufacturing a semiconductor device. [Background technology]

[0002] A technique is known in which a sacrificial layer such as AlGaAs or AlAs is epitaxially grown on a substrate such as GaAs, a semiconductor layer is epitaxially grown thereon, and then the sacrificial layer is etched to separate the semiconductor layer from the substrate (Patent Documents 1 and 2). When etching the sacrificial layer, a groove is formed that extends from the semiconductor layer to the underside of the sacrificial layer. After the groove is formed, the sacrificial layer is etched from the side of the groove. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 2658493 [Patent Document 2] Patent No. 5394091 Summary of the Invention [Problem to be solved by the invention]

[0004] Etching of the sacrificial layer progresses laterally from the end surface exposed in the groove. Due to the crystal plane orientation dependency of the etching rate, the portion of the sacrificial layer in contact with the semiconductor layer may be etched faster than the portion in contact with the substrate. When etching proceeds under these conditions, the sacrificial layer and the semiconductor layer are connected in a minute region, and the sacrificial layer and the substrate are connected in a relatively large region. If the substrate and the sacrificial layer fall off the semiconductor layer in a state where the sacrificial layer and the semiconductor layer are connected in a minute region, cracks or the like will occur in the semiconductor layer.

[0005] An object of the present invention is to provide an epitaxial growth substrate capable of suppressing the occurrence of cracks in a semiconductor layer when the substrate is separated from the semiconductor layer. Another object of the present invention is to provide a method for manufacturing a semiconductor device using the epitaxial growth substrate. [Means for solving the problem]

[0006] According to one aspect of the present invention, a substrate made of a III-V group compound semiconductor containing Ga or In as a group III element; a sacrificial layer epitaxially grown on the substrate; a semiconductor layer epitaxially grown on the sacrificial layer; Equipped with The sacrificial layer includes a layer made of a mixed crystal semiconductor containing Al or In as a group III element, and an epitaxial growth substrate is provided in which the composition ratio of Al or In varies in the thickness direction, and a location where the composition ratio of Al or In shows a maximum value is located inside the sacrificial layer other than on the upper and lower surfaces.

[0007] According to another aspect of the invention, forming at least one semiconductor element selected from the group consisting of a transistor and a diode in the semiconductor layer of the epitaxial growth substrate; A method for manufacturing a semiconductor device is provided, in which the sacrificial layer is etched away to separate the substrate from the semiconductor layer. Effect of the Invention

[0008] At the portion of the sacrifice where the composition ratio of Al or In is at its maximum value, the etching rate for the acidic etchant or alkaline etchant is relatively large. Therefore, when the sacrifice layer is etched, etching proceeds relatively quickly at the portion other than the lower surface and the upper surface of the sacrifice layer, and the portion on the substrate side and the portion on the semiconductor layer side are separated at the portion other than the lower surface and the upper surface of the sacrifice layer. Since the sacrifice layer on the substrate side and the sacrifice layer on the semiconductor layer side are separated at the portion away from the surface of the semiconductor layer, cracks are unlikely to occur in the semiconductor layer during separation. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1A is a cross-sectional view of an epitaxial growth substrate according to a first embodiment, and FIG. 1B is a graph showing an example of the distribution of etching rates of each layer of the epitaxial growth substrate. [Diagram 2] 2A, 2B, and 2C are cross-sectional views of an epitaxial growth substrate, a temporary substrate, and an adhesive layer at intermediate stages in a procedure for separating a semiconductor layer of the epitaxial growth substrate from the substrate according to the first embodiment. [Diagram 3] Figures 3A and 3C are cross-sectional views of an epitaxial growth substrate, a temporary substrate, and an adhesive layer at an intermediate stage in the procedure for separating the semiconductor layer of the epitaxial growth substrate from the substrate according to the first embodiment, Figure 3B is a diagram showing the positional relationship in a plan view of the substrate, semiconductor layer, and sacrificial layer at the intermediate stage shown in Figure 3A, and Figure 3D is a cross-sectional view of the semiconductor layer, temporary substrate, and adhesive layer from which the substrate has been separated. [Figure 4] 4A and 4B are diagrams showing a procedure for separating the substrate from the semiconductor layer in an epitaxial growth substrate according to a comparative example. [Diagram 5] FIG. 5A is a graph showing the distribution of the Al composition ratio in the thickness direction in a sacrificial layer of an epitaxial growth substrate according to the first embodiment, and FIGS. 5B to 5F are graphs showing the distribution of the Al composition ratio in the thickness direction in a sacrificial layer of an epitaxial growth substrate according to a modified example of the first embodiment. [Figure 6] 6A to 6F are graphs showing the distribution of the In composition ratio in the thickness direction in a sacrificial layer of an epitaxial growth substrate according to another modified example of the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view of an epitaxial growth substrate according to the second embodiment. [Figure 8] 8A and 8B are cross-sectional views of a semiconductor device according to the third embodiment during its manufacture. [Figure 9] 9A and 9B are cross-sectional views of a semiconductor device according to the third embodiment during its manufacture. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [First Example] An epitaxial growth substrate according to a first embodiment will be described with reference to FIGS. 1A to 4B.

[0011] 1A is a cross-sectional view of an epitaxial growth substrate 40 according to a first embodiment. A sacrificial layer 20 and a semiconductor layer 30 are epitaxially grown in this order on a substrate 10 made of a III-V group compound semiconductor containing Ga as a group III element, for example GaAs. The sacrificial layer 20 includes layers 20A and 20C made of a III-V group mixed crystal semiconductor containing Al as a group III element, for example AlGaAs. In addition, a layer 20B made of a compound semiconductor containing Al as a group III element, for example AlAs, is included between the two. The semiconductor layer 30 includes a layer made of a compound semiconductor lattice-matched to the substrate 10, for example GaAs.

[0012] The epitaxial growth substrate 40 according to the first embodiment is used as a thin semiconductor layer 30 by separating the semiconductor layer 30 from the substrate 10 by etching away the sacrificial layer 20. For example, various electronic circuit elements such as transistors, diodes, and other passive elements can be formed in the semiconductor layer 30 before separation from the substrate 10, and then the semiconductor layer 30 is separated from the substrate 10, thereby fabricating a very thin integrated circuit element.

[0013] FIG. 1B is a graph showing an example of the distribution of the etching rate of each layer of the epitaxial growth substrate 40. The horizontal axis represents the position in the thickness direction of the epitaxial growth substrate 40, and the vertical axis represents the etching rate. When the composition ratio of Al is increased, the etching rate becomes faster when wet etching is performed with an acidic etchant or an alkaline etchant. Therefore, the etching rate of the layer 20B made of AlAs is faster than the etching rates of the layers 20A and 20C made of AlGaAs. The etching rates of the substrate 10 and the semiconductor layer 30 made of GaAs are sufficiently lower than the etching rates of the three layers 20A, 20B, and 20C included in the sacrificial layer 20.

[0014] Next, with reference to the drawings from FIG. 2A to FIG. 3D, a procedure for separating the semiconductor layer 30 of the epitaxial growth substrate 40 from the substrate 10 according to the first embodiment will be described. FIG. 2A, FIG. 2B, FIG. 2C, FIG. 3A, and FIG. 3C are cross-sectional views of the epitaxial growth substrate 40, the temporary substrate 50, and the adhesive layer 51 at intermediate stages of the procedure for separating the semiconductor layer 30 of the epitaxial growth substrate 40 from the substrate 10 according to the first embodiment. FIG. 3B is a diagram showing the positional relationship in a plan view of the substrate 10, the semiconductor layer 30, and the sacrificial layer 20 at the intermediate stage shown in FIG. 3A. FIG. 3D is a cross-sectional view of the semiconductor layer 30, the temporary substrate 50, and the adhesive layer 51 from which the substrate 10 has been separated.

[0015] 2A, the semiconductor layer 30 of the epitaxial growth substrate 40 according to the first embodiment is placed opposite a temporary substrate 50, and the epitaxial growth substrate 40 is bonded to the temporary substrate 50 by an adhesive layer 51. For example, a silicon substrate is used as the temporary substrate 50, and a polyimide-based adhesive is used for the adhesive layer 51.

[0016] 2B, the epitaxial growth substrate 40 is separated into a plurality of small pieces (chips) by dicing the epitaxial growth substrate 40 to form separation grooves 55. The plurality of small pieces of the epitaxial growth substrate 40 are bonded to and supported by a temporary substrate 50.

[0017] As shown in Fig. 2C, the epitaxial growth substrate 40 after being separated into small pieces is immersed in an acidic or alkaline etchant to wet etch the sacrificial layer 20. The sacrificial layer 20 is etched in the lateral direction from the exposed end face. As shown in Fig. 1B, the etching rate of the sacrificial layer 20 is high in the center in the thickness direction and low in the vicinity of the interface with the substrate 10 and the semiconductor layer 30, so that the lateral etching depth of the center part in the thickness direction of the sacrificial layer 20 is relatively deep compared to other parts.

[0018] As the etching proceeds further, a state is obtained in which the portion of the sacrificial layer 20 on the substrate 10 side and the portion on the semiconductor layer 30 side are connected by a minute dot-like region 20D at the center of the thickness direction of the sacrificial layer 20, as shown in Figures 3A and 3B. As the etching proceeds further, the sacrificial layer 20 is separated into a portion 20E on the substrate 10 side and a portion 20F on the semiconductor layer 30 side, as shown in Figure 3C.

[0019] After the sacrificial layer 20 is separated into two parts 20E and 20F, etching is further carried out to completely remove the part 20F (FIG. 3C) remaining on the semiconductor layer 30 side, as shown in FIG. 3D. Through the steps up to this point, the substrate 10 (FIG. 3C) can be separated from the semiconductor layer 30. The semiconductor layer 30 is hardly etched by the etchant.

[0020] Next, the excellent effects of the first embodiment will be described in comparison with the comparative example shown in FIGS. 4A and 4B.

[0021] 4A and 4B are diagrams showing a procedure for separating the substrate 10 from the semiconductor layer 30 in the epitaxial growth substrate 40 according to the comparative example. In the epitaxial growth substrate 40 according to the comparative example, the Al composition ratio of the sacrificial layer 20 is constant in the thickness direction. When the sacrificial layer 20 is etched from the exposed end face, the sacrificial layer 20 becomes a quadrangular pyramid shape with the crystal plane with the slower etching rate as the inclined surface, as shown in FIG. 4A, due to the crystal plane orientation dependency of the etching rate. The surface (upper surface) of the quadrangular pyramid connected to the semiconductor layer 30 is smaller than the surface (lower surface) connected to the substrate 10.

[0022] 4B, the top surface of the truncated pyramid sacrificial layer 20 becomes substantially dot-like, and the sacrificial layer 20 is separated from the semiconductor layer 30. Just before the sacrificial layer 20 is separated from the semiconductor layer 30, the sacrificial layer 20 is supported by a minute dot-like region relative to the semiconductor layer 30. Stress is concentrated in this minute dot-like region, which makes it easy for cracks 30C to occur in the semiconductor layer 30.

[0023] In contrast, in the first embodiment, the etching rate changes in the thickness direction of the sacrificial layer 20, and the portion where the etching rate is maximum is located inside the sacrificial layer 20. Therefore, as shown in FIG. 3A and FIG. 3B, immediately before the substrate 10 is separated from the semiconductor layer 30, the portion of the sacrificial layer 20 on the substrate 10 side and the portion on the semiconductor layer 30 side are connected in a minute dot-like region. That is, the connection portion (FIG. 3A, FIG. 3C) between the sacrificial layer 20 and the semiconductor layer 30 does not become a minute dot-like state. Therefore, an excellent effect is obtained that cracks are unlikely to occur in the semiconductor layer 30. In order to preferentially etch and remove the sacrificial layer 20 with respect to the substrate 10 and the semiconductor layer 30, it is preferable to set the maximum value of the Al composition ratio in the sacrificial layer 20 to 0.5 or more.

[0024] If the layer 20A made of AlGaAs (FIG. 1A) is omitted and the layer 20B made of AlAs is directly epitaxially grown on the substrate 10, the crystal quality of the sacrificial layer 20 is degraded due to lattice mismatch. As a result, the crystal quality of the semiconductor layer 30 epitaxially grown on the sacrificial layer 20 is also degraded. The layer 20A made of AlGaAs disposed between the layer 20B made of AlAs and the substrate 10 made of GaAs has the function of alleviating the lattice mismatch. This makes it possible to suppress the degradation of the crystallinity of the sacrificial layer 20 and the semiconductor layer 30.

[0025] Next, a preferred range for the thickness of the sacrificial layer 20 will be described. Due to the lattice mismatch between the substrate 10 and the sacrificial layer 20, distortion occurs in the sacrificial layer 20. If the sacrificial layer 20 is made too thick, dislocations will occur in the sacrificial layer 20, and the distortion will be relieved. It is preferable that the sacrificial layer 20 is made thin enough to prevent distortion relief. If the sacrificial layer 20 is made too thin, it becomes difficult for an etchant to penetrate into the space from which the sacrificial layer 20 has been removed in the etching step shown in FIG. 2C. It is preferable that the sacrificial layer 20 is made thick enough to allow the etchant to penetrate.

[0026] Next, a preferred relationship between the thicknesses of the substrate 10, the sacrificial layer 20, and the semiconductor layer 30 will be described. The substrate 10 functions as a support substrate that mechanically supports the semiconductor layer 30 in a semiconductor process for forming various electronic circuit elements, such as transistors, diodes, capacitors, inductors, etc., in the thin semiconductor layer 30. The semiconductor layer 30 is thin enough that it cannot stably maintain its shape by itself. The substrate 10 is separated from the semiconductor layer 30 in order to thin the members including the semiconductor layer 30 on which the electronic circuit elements are formed. Therefore, it is preferable that the thickness of the semiconductor layer 30 is thinner than that of the substrate 10.

[0027] When a transistor or the like is formed in the semiconductor layer 30, it is preferable to use a material that is lattice-matched to a compound semiconductor of one layer that constitutes the transistor as the substrate 10. In other words, it is preferable that the semiconductor layer 30 includes a layer made of a compound semiconductor that is lattice-matched to the substrate 10.

[0028] If the sacrificial layer 20 is too thick, dislocations are likely to occur in the sacrificial layer 20, and the crystal quality of the semiconductor layer 30 epitaxially grown thereon will deteriorate. In order to suppress deterioration in the crystal quality of the semiconductor layer 30, it is preferable to make the sacrificial layer 20 as thin as possible. As an example, it is preferable to make the thickness of the sacrificial layer 20 thinner than the thickness of the semiconductor layer 30. For example, the thickness of the sacrificial layer 20 is 0.01 μm or more and 0.5 μm or less, and the thickness of the semiconductor layer 30 is 0.5 μm or more and 10 μm or less.

[0029] Next, epitaxial growth substrates according to the first embodiment and a modified example of the first embodiment will be described with reference to Figures 5A to 5F. Figure 5A is a graph showing the distribution of the Al composition ratio in the thickness direction in the sacrificial layer 20 of the epitaxial growth substrate 40 according to the first embodiment, and Figures 5B to 5F are graphs showing the distribution of the Al composition ratio in the thickness direction in the sacrificial layer 20 of the epitaxial growth substrate 40 according to a modified example of the first embodiment. In each example, the sacrificial layer 20 is Al x Ga 1-x 5A to 5F, the horizontal axis represents the position in the thickness direction of the substrate 10, the sacrificial layer 20, and the semiconductor layer 30, and the vertical axis represents the Al composition ratio x.

[0030] As shown in FIG. 5A, in the first embodiment, the sacrificial layer 20 is composed of three layers, the Al composition ratio x of the central layer 20B is 1, and the Al composition ratios x of the layers 20A and 20C on both sides are the same and less than 1.

[0031] 5B, the Al composition ratio x of the central layer of the sacrificial layer 20 is also 1. However, the Al composition ratio x of the layer on the substrate 10 side is lower than the Al composition ratio of the layer on the semiconductor layer 30 side. With this configuration, the lattice mismatch at the interface between the substrate 10 and the sacrificial layer 20 is reduced, and the effect of suppressing deterioration in the crystal quality of the sacrificial layer 20 and the semiconductor layer 30 is enhanced.

[0032] In addition, since the Al composition ratio x of the layer of the sacrificial layer 20 in contact with the semiconductor layer 30 is higher than the Al composition ratio of the layer in contact with the substrate 10, the etching rate of the layer of the sacrificial layer 20 in contact with the semiconductor layer 30 is faster than the etching rate of the layer in contact with the substrate 10. Therefore, the portion 20F of the sacrificial layer 20 on the semiconductor layer 30 side shown in FIG. 3C is smaller than the portion 20E on the substrate side. As a result, after the substrate 10 is separated from the semiconductor layer 30, the portion 20F of the sacrificial layer 20 remaining on the semiconductor layer 30 side can be removed in a shorter time.

[0033] In the modification shown in FIG. 5C, two layers with different Al composition ratios x less than 1 are disposed between the layer with Al composition ratio x of 1 and the substrate 10. Of these two layers, the layer on the substrate 10 side has a relatively low Al composition ratio x. By gradually increasing the Al composition ratio from the substrate 10 toward the layer with Al composition ratio x of 1, it is possible to make the lattice constant of the portion of the sacrificial layer 20 in contact with the substrate 10 closer to the lattice constant of the substrate 10 while suppressing a sudden change in the lattice constant. This makes it possible to further suppress deterioration of crystal quality due to lattice mismatch.

[0034] In the modification shown in Fig. 5D, the Al composition ratio x is 1 at two locations in the thickness direction of the sacrificial layer 20. In the modification shown in Fig. 5E, the Al composition ratio x is 1 at three locations in the thickness direction of the sacrificial layer 20. The layer with the Al composition ratio x of 1, which has the largest lattice mismatch with the substrate 10, has a relatively large inherent strain due to the lattice mismatch. If each layer with an Al composition ratio of 1 becomes thick, dislocations will occur and the strain will be alleviated.

[0035] By configuring the sacrificial layer 20 so that the Al composition ratio x is 1 at multiple points in the thickness direction, it is possible to thicken the sacrificial layer 20 without relaxing the strain (without generating dislocations) in the sacrificial layer 20. When the sacrificial layer 20 is thickened, the etchant can easily penetrate between the substrate 10 and the semiconductor layer 30 in the etching step shown in FIG. 2C, and the stability of the etching step of the sacrificial layer 20 can be improved.

[0036] The number of locations where the Al composition ratio x is 1 may be two, three, or even four or more locations in the thickness direction of the sacrificial layer 20 .

[0037] 5D, as in the modification shown in Fig. 5B, the Al composition ratio x of the layer in contact with the substrate 10 is lower than the Al composition ratio x of the layer in contact with the semiconductor layer 30, so that the lattice mismatch at the interface between the substrate 10 and the sacrificial layer 20 can be alleviated, as in the modification shown in Fig. 5B. Note that, in the modification shown in Fig. 5E, the Al composition ratio x of the layer in contact with the substrate 10 may also be lower than the Al composition ratio x of the layer in contact with the semiconductor layer 30.

[0038] In the modification shown in FIG. 5F, the Al composition ratio x changes continuously in the thickness direction in the sacrificial layer 20. Even in this case, as in the modification shown in FIG. 5D, the Al composition ratio x is 1 at two points in the thickness direction of the sacrificial layer 20. If the Al composition ratio x changes discontinuously, stress tends to concentrate at the interface of the layer where the Al composition ratio x becomes discontinuous. By continuously changing the Al composition ratio x, it is possible to suppress the localization of stress. As a result, it is possible to improve the crystal quality of the sacrificial layer 20.

[0039] 5D, the Al composition ratio x of the sacrificial layer 20 at the interface with the substrate 10 is set lower than the Al composition ratio x of the sacrificial layer 20 at the interface with the semiconductor layer 30. This makes it possible to suppress lattice mismatch and improve the crystal quality of the semiconductor layer 30.

[0040] 5A and the modified examples of the first embodiment shown in FIGS. 5B to 5F, the Al composition ratio x in the portion where it is desired to make the etching rate relatively fast is set to 1, but the Al composition ratio does not necessarily have to be 1. With respect to the thickness direction of the sacrificial layer 20, the Al composition ratio x may be set to have a maximum value in at least one portion inside the sacrificial layer 20 other than the interface with the substrate 10 and the interface with the semiconductor layer 30.

[0041] In the step of etching the sacrificial layer 20 from FIG. 2C to FIG. 3D, in order to reduce etching damage to the semiconductor layer 30, it is preferable to increase the ratio of the etching rate of the sacrificial layer 20 to the etching rate of the semiconductor layer 30 when using an etchant used in the step of etching the sacrificial layer 20 (etching selectivity). For example, when the semiconductor layer 30 and the substrate 10 are made of GaAs, it is preferable to set the Al composition ratio x at the point where the Al composition ratio x in the sacrificial layer 20 has a maximum value to 0.5 or more, and more preferably to set it to 0.7 or more. When the Al composition ratio x at the point where the Al composition ratio x in the sacrificial layer 20 has a maximum value is less than 0.5, the time required for etching to separate the semiconductor layer 30 and the substrate 10 becomes long, and as a result, the damage to the semiconductor layer 30 and the substrate 10 becomes large.

[0042] Next, another modified example of the first embodiment will be described with reference to FIGS. 6A to 6F. In the first embodiment, a GaAs substrate was used as the substrate 10 (FIG. 1A), but a substrate made of other III-V group compound semiconductors, for example, an InP substrate, may be used. When an InP substrate is used, the sacrificial layer 20 is made of In y Ga 1-y It is possible to use As.

[0043] 6A to 6F are graphs showing the distribution of the In composition ratio y in the thickness direction in the sacrificial layer 20 of the epitaxial growth substrate 40 according to another modification of the first embodiment. In each example, an InP substrate is used as the substrate 10, and the sacrificial layer 20 is In y Ga 1-y The sacrificial layer 20 is made of As. The distributions of the In composition ratio y in the sacrificial layer 20 shown in the graphs of Figures 6A to 6F are the same as the distributions of the Al composition ratio x in the sacrificial layer 20 shown in the graphs of Figures 5A to 5F, respectively. The semiconductor layer 30 includes a layer made of a semiconductor material that is lattice-matched to the InP substrate, for example, InP.

[0044] The etching rate of InGaAs with an acidic etchant or an alkaline etchant increases as the In composition ratio y increases. Therefore, by making the distribution of the In composition ratio y in the sacrificial layer 20 be the distribution shown in the graphs of FIG. 6A to FIG. 6F, the same excellent effect as that of the first embodiment and its modified example shown in the graphs of FIG. 5A to FIG. 5F can be obtained. In order to etch and remove the sacrificial layer 20 preferentially with respect to the semiconductor layer 30 and the substrate 10, it is preferable that the In composition ratio y is 0.5 or more. For example, when the semiconductor layer 30 and the substrate 10 are made of InP, it is preferable that the In composition ratio y at the point where the In composition ratio y in the sacrificial layer 20 shows a maximum value is 0.5 or more, and more preferably 0.7 or more.

[0045] In another modification, the sacrificial layer 20 is made of Al x In y Ga 1-x-y Alternatively, the sacrificial layer 20 may be formed of a quaternary mixed crystal semiconductor containing GaAs and InP. In this case, the substrate 10 may be a GaAs substrate or an InP substrate. The distribution of the total composition ratio x+y of Al and In in the sacrificial layer 20 may be similar to the distribution of the Al composition ratio x shown in the graphs of Figures 5A to 5F. Alternatively, the substrate 10 may be an InP substrate or a GaAs substrate, and the sacrificial layer 20 may be InAlP.

[0046] [Second Example] Next, an epitaxial growth substrate according to a second embodiment will be described with reference to Fig. 7. Below, a description of the configuration common to the epitaxial growth substrate 40 according to the first embodiment described with reference to Figs. 1A to 3D will be omitted.

[0047] 7 is a cross-sectional view of an epitaxial growth substrate 40 according to the second embodiment. As in the first embodiment, the epitaxial growth substrate 40 in the second embodiment includes a substrate 10, a sacrificial layer 20, and a semiconductor layer 30. In the second embodiment, the semiconductor layer 30 includes a stopper layer 30S epitaxially grown from the sacrificial layer 20, and a device layer 30D epitaxially grown from the stopper layer 30S.

[0048] The device layer 30D includes a layer made of a compound semiconductor lattice-matched to the substrate 10, for example, a layer made of the same compound semiconductor as the substrate 10. The stopper layer 30S has a function of protecting the device layer 30D from an etchant in the step of etching the sacrificial layer 20 (FIGS. 2C, 3A, 3C, and 3D). Therefore, in wet etching using an etchant for etching the sacrificial layer 20, the etching rate of the stopper layer 30S is slower than the etching rate of the layer at the interface between the device layer 30D and the stopper layer 30S.

[0049] As an example, when the sacrificial layer 20 is formed of AlGaAs or AlAs and the device layer 30D includes an AlGaAs layer, the stopper layer 30S can be an AlGaInP layer, a GaInP layer, an AlInP layer, a GaInAs layer, or the like. By adjusting the composition ratio of the group III elements of the alloy semiconductor constituting the stopper layer 30S, it is possible to make the lattice constant of the stopper layer 30S almost match the lattice constant of the substrate 10 made of GaAs. Even if the lattice constants do not match completely, the occurrence of dislocations in the stopper layer 30S can be suppressed by making the stopper layer 30S thin enough not to cause strain relaxation. In addition, the impurity concentrations of the stopper layer 30S and the device layer 30D may be made different from each other to utilize the impurity concentration dependency of the etching rate.

[0050] [Third Example] Next, a method for manufacturing a semiconductor device using an epitaxial growth substrate according to a third embodiment will be described with reference to Figures 8A to 9B. Figures 8A to 9B are cross-sectional views of the semiconductor device according to the third embodiment during the manufacturing process.

[0051] As shown in Fig. 8A, an epitaxial growth substrate 40 according to the first embodiment is prepared. The epitaxial growth substrate 40 includes a substrate 10, a sacrificial layer 20, and a semiconductor layer 30 made of n-type GaAs. A part of the semiconductor layer 30 is made to have a high resistance to form an element isolation region 30I. A plurality of active regions 30N made of n-type GaAs that are electrically isolated from each other are defined by the element isolation region 30I.

[0052] Semiconductor elements such as transistors 31 and diodes 32 are formed on each of the multiple active regions 30N of the semiconductor layer 30. The transistor 31 is a heterojunction bipolar transistor including a collector layer made of n-type GaAs, a base layer made of p-type GaAs, and an emitter layer made of n-type InGaP. The diode 32 includes a cathode layer made of n-type GaAs and an anode layer made of p-type GaAs, which are formed in the same process as the collector layer and base layer of the transistor 31. The active region 30N is used as a current path that supplies carriers to the collector layer of the transistor 31 and the cathode layer of the diode 32.

[0053] An insulating film 33 is formed on the semiconductor layer 30 to cover the transistor 31 and the diode 32. The insulating film 33 is made of an inorganic insulating material such as silicon nitride, an insulating resin, or the like.

[0054] 8B, in a state where the surface on which the semiconductor layer 30 is formed faces the temporary substrate 50, the epitaxial growth substrate 40 is attached to the temporary substrate 50 via an adhesive layer 51. More specifically, the insulating film 33 is attached to the temporary substrate 50.

[0055] As shown in Fig. 9A, the epitaxial growth substrate 40 and the insulating film 33 are diced to separate the epitaxial growth substrate 40 and the insulating film 33 into a plurality of small pieces. In Fig. 9A, only one small piece is shown. As shown in Fig. 9B, the sacrificial layer 20 of the epitaxial growth substrate 40 is etched away to separate the substrate 10 from the semiconductor layer 30. Through the process up to this point, a plurality of thin electronic circuit chips including transistors 31 and diodes 32 are obtained.

[0056] As an example, these electronic circuit chips can be detached from the temporary substrate 50 and the semiconductor layer 30 can be bonded to another electronic circuit chip including a silicon substrate to produce electronic circuit components including silicon-based electronic circuit elements and compound semiconductor-based electronic circuit elements.

[0057] Next, the excellent effects of the third embodiment will be described. In the third embodiment, as in the first embodiment, the occurrence of cracks in the semiconductor layer 30 can be suppressed in the step of separating the substrate 10 from the semiconductor layer 30 shown in FIG. 9B.

[0058] In the heterojunction transistor 31, an n-type compound semiconductor is used as a collector layer. In order to form a current path in the semiconductor layer 30 that supplies carriers to the collector layer, the semiconductor layer 30 preferably includes an n-type compound semiconductor layer. In the step of etching the sacrificial layer 20 shown in FIG. 9B, the transistor 31 and the diode 32 are covered with the insulating film 33 and are therefore not exposed to the etchant for etching the sacrificial layer 20. For this reason, the transistor 31 and the diode 32 may include a compound semiconductor layer whose etching selectivity with respect to the sacrificial layer 20 is not sufficiently large.

[0059] The above-mentioned embodiments are merely examples, and it goes without saying that partial replacement or combination of the configurations shown in different embodiments is possible. Similar effects due to similar configurations of multiple embodiments are not mentioned in each embodiment. Furthermore, the present invention is not limited to the above-mentioned embodiments. For example, it will be obvious to those skilled in the art that various modifications, improvements, combinations, etc. are possible.

[0060] Based on the above examples described in this specification, the following invention is disclosed. <1> a substrate made of a III-V group compound semiconductor containing Ga or In as a group III element; a sacrificial layer epitaxially grown on the substrate; a semiconductor layer epitaxially grown on the sacrificial layer; Equipped with The sacrificial layer includes a layer made of a mixed crystal semiconductor containing Al or In as a group III element, the composition ratio of Al or In varies in the thickness direction, and a location where the composition ratio of Al or In shows a maximum value is located inside the sacrificial layer other than on the lower surface and upper surface of the epitaxial growth substrate.

[0061] <2> The layer made of the mixed crystal semiconductor included in the sacrificial layer contains Ga in addition to Al or In as a group III element, and contains at least one of As and P as a group V element, and the maximum composition ratio of Al or In is 0.5 or more. <1> 2. The epitaxial growth substrate according to claim 1 .

[0062] <3> The sacrificial layer has a lower Al or In composition ratio in a portion in contact with the substrate than in a portion in contact with the semiconductor layer. <1> or <2> 2. The epitaxial growth substrate according to claim 1 .

[0063] <4> The composition ratio of Al or In has a maximum value at a plurality of points in the thickness direction of the sacrificial layer. <1> ~ <3> 13. The epitaxial growth substrate according to claim 12,

[0064] <5> The thickness of the semiconductor layer is less than the thickness of the substrate and is greater than the thickness of the sacrificial layer. <1> ~ <4> 13. The epitaxial growth substrate according to claim 12,

[0065] <6> The substrate is made of GaAs or InP, and the semiconductor layer includes a layer made of a semiconductor that is lattice-matched to the substrate. <1> ~ <5> 13. The epitaxial growth substrate according to claim 12,

[0066] <7> The semiconductor layer includes a stopper layer in contact with the sacrificial layer, and an etching rate of the stopper layer is slower than an etching rate of the sacrificial layer in wet etching using an acidic etchant or an alkaline etchant. <1> ~ <6> 13. The epitaxial growth substrate according to claim 12,

[0067] <8> The semiconductor layer includes a layer made of an N-type semiconductor. <1> ~ <7> 13. The epitaxial growth substrate according to claim 12,

[0068] <9> In wet etching using an acidic etchant or an alkaline etchant, a portion of the sacrificial layer at which the etching rate is maximum is located inside the sacrificial layer other than the lower surface and the upper surface. <1> ~ <8> 13. The epitaxial growth substrate according to claim 12,

[0069] <10> <1> ~ <9> forming at least one semiconductor element selected from the group consisting of a transistor and a diode in the semiconductor layer of the epitaxial growth substrate according to any one of the preceding claims; The method for manufacturing a semiconductor device further comprises the steps of: etching away the sacrificial layer to separate the substrate from the semiconductor layer. [Explanation of symbols]

[0070] 10 Substrate 20 Sacrificial Layer 20A AlGaAs layer 20B AlAs layer 20C AlGaAs layer 20D Small dot-like area 20E Substrate side of the sacrificial layer 20F Semiconductor layer side of the sacrificial layer 30 Semiconductor layer 30C Crack 30D Device Layer 30I Element isolation region 30N active area 30S stopper layer 31 Transistor 32 Diode 33 Insulating film 40 Epitaxial growth substrate 50 Temporary board 51 Adhesive layer 55 Separation groove

Claims

1. A substrate made of a III-V group compound semiconductor containing Ga or In as a group III element; a sacrificial layer epitaxially grown on the substrate; a semiconductor layer epitaxially grown on the sacrificial layer; Equipped with The sacrificial layer includes a layer made of a mixed crystal semiconductor containing Al or In as a group III element, the composition ratio of Al or In varies in the thickness direction, and a location where the composition ratio of Al or In shows a maximum value is located inside the sacrificial layer other than on the lower surface and the upper surface of the epitaxial growth substrate.

2. 2. The epitaxial growth substrate according to claim 1, wherein the layer made of the mixed crystal semiconductor included in the sacrificial layer contains Ga in addition to Al or In as a group III element, and contains at least one of As and P as a group V element, and the maximum value of the composition ratio of Al or In is 0.5 or more.

3. 3. The epitaxial growth substrate according to claim 1, wherein the sacrificial layer has a lower Al or In composition ratio in a portion in contact with the substrate than in a portion in contact with the semiconductor layer.

4. 3. The epitaxial growth substrate according to claim 1, wherein the composition ratio of Al or In has a maximum value at a plurality of points in the thickness direction of the sacrificial layer.

5. 3. The epitaxial growth substrate according to claim 1, wherein the thickness of the semiconductor layer is smaller than the thickness of the substrate and larger than the thickness of the sacrificial layer.

6. 3. The epitaxial growth substrate according to claim 1, wherein the substrate is made of GaAs or InP, and the semiconductor layer includes a layer made of a semiconductor that is lattice-matched to the substrate.

7. 3. The epitaxial growth substrate according to claim 1, wherein the semiconductor layer includes a stopper layer in contact with the sacrificial layer, and an etching rate of the stopper layer is slower than an etching rate of the sacrificial layer in wet etching using an acidic etchant or an alkaline etchant.

8. 3. The epitaxial growth substrate according to claim 1, wherein the semiconductor layer includes a layer made of an N-type semiconductor.

9. 3. The epitaxial growth substrate according to claim 1, wherein a portion of the sacrificial layer at which the etching rate is maximized during wet etching using an acidic etchant or an alkaline etchant is located inside the sacrificial layer other than the upper and lower surfaces.

10. forming at least one semiconductor element selected from the group consisting of a transistor and a diode in the semiconductor layer of the epitaxial growth substrate according to claim 1 or 2; The method for manufacturing a semiconductor device further comprises the steps of: etching away the sacrificial layer to separate the substrate from the semiconductor layer.

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