Semiconductor device, electronic apparatus, and vehicle

Abstract

To suppress changeover delay of a constant current setting value.SOLUTION: A semiconductor device 400 includes: a drive circuit 410 for driving a transistor QH; a reference current generation circuit 420 for generating a predetermined reference current I2; a variable resistance circuit 450 provided on a path along which the reference current I2 flows, for generating a setting voltage V1H according to a control signal CTL; and a constant current control circuit 440 for generating a feedback control signal V3H of the drive circuit 410 so that a sense voltage V2H according to an output current IH flowing through the transistor QH matches the setting voltage V1H.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, an electronic device, and a vehicle. [Background technology]

[0002] Conventionally, signal transmission devices that transmit signals between a primary circuit system and a secondary circuit system while electrically insulating the primary circuit system and the secondary circuit system have been used in various applications (such as power supplies or motor drive devices).

[0003] As an example of the related art, Patent Document 1 by the applicant of the present application can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2022 / 070944

[0005] [overview] In the conventional signal transmission device, there is room for consideration regarding constant current driving of the output current.

[0006] The semiconductor device according to the present disclosure comprises a drive circuit configured to drive a transistor, a reference current generating circuit configured to generate a predetermined reference current, a variable resistance circuit provided in a path through which the reference current flows and configured to generate a set voltage corresponding to a control signal, and a constant current control circuit configured to generate a feedback control signal for the drive circuit so that a sense voltage corresponding to an output current flowing through the transistor matches the set voltage. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a basic configuration of a signal transmission device. [Diagram 2] FIG. 2 is a diagram showing the basic structure of a transformer chip. [Diagram 3] FIG. 3 is a perspective view of a semiconductor device used as a two-channel type transformer chip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. [Diagram 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 8] FIG. 8 is an enlarged view (isolation structure) of the region XIII shown in FIG. [Figure 9] FIG. 9 is a diagram illustrating an example of the layout of a transformer chip. [Figure 10] FIG. 10 is a diagram showing a first comparative example of an electronic device. [Figure 11] FIG. 11 is a diagram showing a first embodiment of an electronic device. [Figure 12] FIG. 12 is a diagram showing a second comparative example of an electronic device. [Figure 13] FIG. 13 is a diagram showing a second embodiment of the electronic device. [Figure 14] FIG. 14 is a diagram showing the external appearance of the vehicle.

[0008] [Detailed Description] <Signal transmission device (basic configuration)> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while isolating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0009] The controller chip 210 is a semiconductor chip that operates by receiving a supply of a power supply voltage VCC1 (for example, a maximum of 7 V with respect to GND1). In the controller chip 210, for example, a pulse transmission circuit 211 and buffers 212 and 213 are integrated.

[0010] The pulse transmitting circuit 211 is a pulse generator that generates the transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputs a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either one of the transmission pulse signals S11 and S21 in response to the logical level of the input pulse signal IN.

[0011] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0012] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0013] The driver chip 220 is a semiconductor chip that operates by receiving a power supply voltage VCC2 (for example, a maximum of 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0014] The buffer 221 shapes the waveform of the reception pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse reception circuit 223.

[0015] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0016] The pulse receiving circuit 223 generates an output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so as to raise the output pulse signal OUT to a high level in response to the pulse drive of the received pulse signal S12, and to lower the output pulse signal OUT to a low level in response to the pulse drive of the received pulse signal S22. That is, the pulse receiving circuit 223 switches the logical level of the output pulse signal OUT in response to the logical level of the input pulse signal IN. Note that, for example, an RS flip-flop can be suitably used as the pulse receiving circuit 223.

[0017] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0018] The transformer chip 230 uses transformers 231 and 232 to provide DC insulation between the controller chip 210 and the driver chip 220, and outputs the transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 to the pulse reception circuit 223 as reception pulse signals S12 and S22, respectively. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0019] More specifically, the transformer 231 outputs a receiving pulse signal S12 from the secondary coil 231s in response to a transmitting pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a receiving pulse signal S22 from the secondary coil 232s in response to a transmitting pulse signal S21 input to the primary coil 232p.

[0020] As described above, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to a rise signal and a fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0021] Incidentally, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0022] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), making it possible to reduce manufacturing costs.

[0023] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (BEVs [battery electric vehicles], HEVs [hybrid electric vehicles], PHEVs / PHVs (plug-in hybrid electric vehicle / plug-in hybrid vehicle), or xEVs such as FCEVs / FCVs (fuel cell electric vehicle / fuel cell vehicle)).

[0024] <Trans chip (basic structure)> Next, the basic structure of the transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of the transformer chip 230. In the transformer chip 230 of this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that face each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that face each other in the vertical direction.

[0025] Both the primary coils 231p and 232p are formed in a first wiring layer (lower layer) 230a of the transformer chip 230. Both the secondary coils 231s and 232s are formed in a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0026] The primary coil 231p is laid in a spiral shape starting from a first end connected to the internal terminal X21 so as to surround the periphery of the internal terminal X21 in a clockwise direction, and a second end corresponding to the end point is connected to the internal terminal X22. On the other hand, the primary coil 232p is laid in a spiral shape starting from a first end connected to the internal terminal X23 so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and a second end corresponding to the end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0027] The internal terminal X21 is connected to the external terminal T21 of the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 of the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 of the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged in a straight line and are used for wire bonding with the controller chip 210.

[0028] The secondary coil 231s is laid in a spiral shape so as to surround the external terminal T24 in a counterclockwise direction, starting from a first end connected to the external terminal T24, and a second end corresponding to the end point is connected to the external terminal T25. On the other hand, the secondary coil 232s is laid in a spiral shape so as to surround the external terminal T26 in a clockwise direction, starting from a first end connected to the external terminal T26, and a second end corresponding to the end point is connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the illustrated order, and are used for wire bonding with the driver chip 220.

[0029] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0030] <Trans chip (2 channel type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low potential coil 22 (corresponding to a primary coil of a transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which a high potential coil 23 (corresponding to a secondary coil of a transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0031] 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide band gap semiconductor, and a compound semiconductor.

[0032] The wide band gap semiconductor is made of a semiconductor whose band gap exceeds that of silicon (about 1.12 eV). The band gap of the wide band gap semiconductor is preferably 2.0 eV or more. The wide band gap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride) and GaAs (gallium arsenide).

[0033] In this embodiment, the semiconductor chip 41 includes a semiconductor substrate made of silicon. The semiconductor chip 41 may be an epitaxial substrate having a layered structure including a semiconductor substrate made of silicon and an epitaxial layer made of silicon. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0034] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0035] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0036] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface in a plan view. The insulating main surface 52 extends parallel to the first main surface .

[0037] The insulating side walls 53A-53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A-53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A-44D. Specifically, the insulating side walls 53A-53D are formed flush with the chip side walls 44A-44D. The insulating side walls 53A-53D form ground surfaces flush with the chip side walls 44A-44D.

[0038] The insulating layer 51 has a multi-layer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 layers in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the thickness of the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0039] Each of the interlayer insulating layers 57 has a laminated structure including a first insulating layer 58 on the lowermost insulating layer 55 side and a second insulating layer 59 on the uppermost insulating layer 56 side. The first insulating layer 58 may include silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, about 0.3 μm).

[0040] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, about 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0041] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of layers of the interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be realized. In addition, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0042] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformer). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed in the inner part of the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0043] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side to the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. In the following, the structure of the first transformer 21A will be described as an example. The structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D are omitted because the description of the structure of the first transformer 21A applies mutatis mutandis.

[0044] 5 to 7, the first transformer 21A includes a low potential coil 22 and a high potential coil 23. The low potential coil 22 is formed in an insulating layer 51. The high potential coil 23 is formed in the insulating layer 51 so as to face the low potential coil 22 in the normal direction Z. In this embodiment, the low potential coil 22 and the high potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0045] The low potential coil 22 is formed on the lowermost insulating layer 55 (semiconductor chip 41) side within the insulating layer 51, and the high potential coil 23 is formed on the uppermost insulating layer 56 (insulating main surface 52) side of the low potential coil 22 within the insulating layer 51. In other words, the high potential coil 23 faces the semiconductor chip 41 with the low potential coil 22 in between. The low potential coil 22 and the high potential coil 23 may be disposed in any position. Furthermore, it is sufficient that the high potential coil 23 faces the low potential coil 22 with one or more interlayer insulating layers 57 in between.

[0046] The distance between the low potential coil 22 and the high potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is appropriately adjusted according to the dielectric strength and electric field strength between the low potential coil 22 and the high potential coil 23. In this embodiment, the low potential coil 22 is formed in the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high potential coil 23 is formed in the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0047] The low potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape extending in an elliptical shape (oval shape) in a plan view. A portion forming the innermost periphery of the first spiral portion 26 defines a first inner region 66 having an elliptical shape in a plan view.

[0048] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0049] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the form shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0050] The low potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low potential coil 22 may have a laminated structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0051] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape extending in an elliptical shape (oval shape) in a plan view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 having an elliptical shape in a plan view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0052] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. It is preferable that the number of turns of the second helical portion 29 exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26, or may be equal to the number of turns of the first helical portion 26.

[0053] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0054] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0055] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0056] The high potential coil 23 is preferably formed of the same conductive material as the low potential coil 22. That is, like the low potential coil 22, the high potential coil 23 preferably includes a barrier layer and a body layer.

[0057] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0058] The low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the low potential terminals 11 are formed in a region on the insulating sidewall 53B side at intervals in the second direction Y from the transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0059] The low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E and a sixth low potential terminal 11F. In this embodiment, two of each of the low potential terminals 11A to 11F are formed. The number of the low potential terminals 11A to 11F is arbitrary.

[0060] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in a plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in a plan view.

[0061] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0062] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0063] The multiple high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the multiple low potential terminals 11. Specifically, the multiple high potential terminals 12 are formed in a region on the insulating sidewall 53A side at intervals from the multiple low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0064] The multiple high potential terminals 12 are formed in areas close to the corresponding transformers 21A to 21D in a plan view. The closeness of the high potential terminals 12 to the transformers 21A to 21D means that the distance between the high potential terminals 12 and the transformers 21 in a plan view is less than the distance between the low potential terminals 11 and the high potential terminals 12.

[0065] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A-21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A-21D in the first direction X in a plan view.

[0066] The multiple high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the multiple high potential terminals 12A to 12F are formed. The number of the multiple high potential terminals 12A to 12F is arbitrary.

[0067] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in a region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in a region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0068] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0069] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0070] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0071] The first low potential wiring 31 and the second low potential wiring 32 fix the low potential coil 22 of the first transformer 21A and the low potential coil 22 of the second transformer 21B to the same potential. The first low potential wiring 31 and the second low potential wiring 32 also fix the low potential coil 22 of the third transformer 21C and the low potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low potential wiring 31 and the second low potential wiring 32 fix all the low potential coils 22 of the transformers 21A to 21D to the same potential.

[0072] The first high potential wiring 33 and the second high potential wiring 34 fix the high potential coil 23 of the first transformer 21A and the high potential coil 23 of the second transformer 21B to the same potential. The first high potential wiring 33 and the second high potential wiring 34 also fix the high potential coil 23 of the third transformer 21C and the high potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high potential wiring 33 and the second high potential wiring 34 fix all the high potential coils 23 of the transformers 21A to 21D to the same potential.

[0073] The multiple first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The multiple first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The structure of the other first low potential wirings 31 will be omitted, as the description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis.

[0074] The first low potential wiring 31 includes a through wiring 71, a low potential connection wiring 72, a pull-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0075] The through wiring 71, the low potential connection wiring 72, the lead-out wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low potential coil 22, etc. In other words, the through wiring 71, the low potential connection wiring 72, the lead-out wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably each include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0076] The through wiring 71 penetrates the interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape extending along the normal direction Z. In this embodiment, the through wiring 71 is formed in a region between the lowermost insulating layer 55 and the uppermost insulating layer 56 in the insulating layer 51. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low potential coil 22.

[0077] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrode 80 are each formed of the same conductive material as the low potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrode 80 each include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0078] The first electrode layer 78 forms an upper end of the through wiring 71. The second electrode layer 79 forms a lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0079] The multiple wiring plug electrodes 80 are embedded in the multiple interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be electrically connected to each other, and electrically connect the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 each have a planar area less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0080] The number of layers of the multiple wiring plug electrodes 80 coincides with the number of layers of the multiple interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 penetrating the multiple interlayer insulating layers 57 may be formed.

[0081] The low potential connecting wire 72 is formed in the first inner region 66 of the first transformer 21A (low potential coil 22) in the same interlayer insulating layer 57 as the low potential coil 22. The low potential connecting wire 72 is formed in an island shape and faces the high potential terminal 12 (first high potential terminal 12A) in the normal direction Z. It is preferable that the low potential connecting wire 72 has a planar area larger than the planar area of ​​the wiring plug electrode 80. The low potential connecting wire 72 is electrically connected to the first inner end 24 of the low potential coil 22.

[0082] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the lowermost insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in a region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in a region between the semiconductor chip 41 and the low potential connection wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0083] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0084] The multiple pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The multiple substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0085] 6 and 7, the first high potential wirings 33 are electrically connected to the corresponding high potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high potential coils 23). The first high potential wirings 33 each have a similar structure. In the following, the structure of the first high potential wiring 33 connected to the first high potential terminal 12A and the first transformer 21A will be described as an example. The structure of the other first high potential wirings 33 will be omitted, since the description of the structure of the first high potential wiring 33 connected to the first transformer 21A applies mutatis mutandis.

[0086] The first high potential wiring 33 includes a high potential connection wiring 81 and one or more (in this embodiment, multiple) pad plug electrodes 82. The high potential connection wiring 81 and the pad plug electrode 82 are preferably formed of the same conductive material as the low potential coil 22, etc. In other words, the high potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0087] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (the first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connection wiring 81 is formed at an interval from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z. Thereby, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the breakdown voltage of the insulating layer 51 is enhanced.

[0088] The plurality of pad plug electrodes 82 are formed in the region between the high-potential terminal 12 (the first high-potential terminal 12A) and the high-potential connection wiring 81 within the uppermost insulating layer 56, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively. The plurality of pad plug electrodes 82 each have a planar area less than the planar area of the high-potential connection wiring 81 in a plan view.

[0089] Referring to FIG. 7, it is preferable that the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). It is preferable that the distance D1 exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. It is preferable that the distance D1 is 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the breakdown voltage to be achieved.

[0090] Referring to FIGS. 6 and 7, the semiconductor device 5 includes dummy patterns 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0091] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high potential coil 23 and the low potential coil 22, and is independent of the transformers 21A to 21D. In other words, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low potential coil 22 and the high potential coil 23 in the transformers 21A to 21D and suppresses electric field concentration on the high potential coil 23. In this embodiment, the dummy pattern 85 is routed with a line density equal to the line density of the high potential coil 23 per unit area. The line density of the dummy pattern 85 being equal to the line density of the high potential coil 23 means that the line density of the dummy pattern 85 falls within a range of ±20% of the line density of the high potential coil 23.

[0092] The depth position of the dummy pattern 85 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high potential coil 23 than the low potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low potential coil 22.

[0093] In this case, electric field concentration on the high potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high potential coil 23 in the normal direction Z, the more the electric field concentration on the high potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high potential coil 23. In this case, electric field concentration on the high potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes a plurality of dummy patterns having different electrical states. The dummy pattern 85 may include a high potential dummy pattern.

[0094] The depth position of the high-potential dummy pattern 86 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0095] Dummy pattern 85 includes a floating dummy pattern formed in an electrically floating state within insulating layer 51 so as to be located around transformers 21A to 21D.

[0096] In this embodiment, the floating dummy pattern is laid out in a dense line shape so as to partially cover and partially expose the area around the high potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0097] The depth position of the floating dummy pattern within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0098] The number of floating lines is arbitrary and is adjusted according to the electric field to be relaxed. The floating dummy pattern may be composed of a plurality of floating lines.

[0099] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed by utilizing a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is shown in a simplified manner by a dashed line drawn on the surface layer portion of the first main surface 42.

[0100] The second functional device 60 is electrically connected to the low potential terminal 11 via a low potential wiring, and is electrically connected to the high potential terminal 12 via a high potential wiring. The low potential wiring has a similar structure to the first low potential wiring 31 (second low potential wiring 32) except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high potential wiring has a similar structure to the first high potential wiring 33 (second high potential wiring 34) except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A specific description of the low potential wiring and high potential wiring related to the second functional device 60 will be omitted.

[0101] The second functional device 60 may include at least one of a passive device, a semiconductor rectifier device, and a semiconductor switching device. The second functional device 60 may include a circuit network in which any two or more of the passive devices, the semiconductor rectifier device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0102] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifier device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0103] 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape spaced apart from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0104] The device region 62 is a region including the first functional device 45 (multiple transformers 21), the second functional device 60, the multiple low potential terminals 11, the multiple high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. The outer region 63 is a region outside the device region 62.

[0105] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (the multiple transformers 21), the second functional device 60, the multiple low potential terminals 11, the multiple high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path connected to the device region 62.

[0106] The seal conductor 61 is formed in a band shape along the insulating side walls 53 to 53D in a plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in a plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in a plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in a plan view.

[0107] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending between the upper end and the lower end in a wall shape. In this embodiment, the upper end of the seal conductor 61 is formed on the semiconductor chip 41 side with a gap therebetween from the insulating principal surface 52, and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed on the upper end side with a gap therebetween from the semiconductor chip 41.

[0108] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the multiple low potential terminals 11 and the multiple high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (multiple transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0109] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or a plurality (a plurality in this embodiment) of seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed of the same conductive material as the low potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0110] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in a plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be connected to each other. The number of stacked seal plug conductors 64 matches the number of stacked interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0111] As long as one annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless shape (annular shape).

[0112] The multiple seal via conductors 65 are formed in the lowermost insulating layer 55 in the region between the semiconductor chip 41 and the seal plug conductor 64. The multiple seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The multiple seal via conductors 65 have a planar area less than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or greater than the planar area of ​​the seal plug conductor 64.

[0113] The width of the sealing conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the sealing conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the sealing conductor 61 is defined by the width in a direction perpendicular to the direction in which the sealing conductor 61 extends.

[0114] 7 and 8, the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0115] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0116] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a band shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion in which the lower end portion (seal via conductor 65) of the seal conductor 61 is embedded toward the semiconductor chip 41 side. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0117] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body portion 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0118] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 with a gap therebetween from the chip sidewalls 44A to 44D.

[0119] The main body portion 130C has a flat surface extending approximately parallel to the first main surface 42 of the semiconductor chip 41. The main body portion 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body portion 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 may take various forms in addition to the field insulating film 131.

[0120] 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0121] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may include silicon oxide. The first inorganic insulating layer 141 preferably includes USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may include silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high potential coil 23 can be increased.

[0122] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of the USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0123] The first inorganic insulating layer 141 may contain at least one of BPSG (boron doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0124] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral portion of the low potential terminal 11. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral portion of the high potential terminal 12.

[0125] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0126] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low potential coil 22 and the high potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. According to these structures, the thickness of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high potential coil 23.

[0127] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0128] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high potential terminal openings 149 that expose the plurality of high potential terminals 12 (high potential pad openings 144). The second portion 147 may have an overlap portion that rises onto the periphery (overlap portion) of the high potential pad opening 144.

[0129] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the multiple high potential coils 23, the multiple high potential terminals 12, the first high potential dummy pattern 87, the second high potential dummy pattern 88, and the floating dummy pattern 121.

[0130] The embodiment of the present invention can be embodied in further other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form having only the second functional device 60 without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0131] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the sealing conductor 61. Also, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the sealing conductor 61.

[0132] In the above embodiment, an example has been described in which the second functional device 60 is formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0133] In the above embodiment, an example has been described in which the dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required, and may be removed.

[0134] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type device including a plurality of transformers 21. However, a first functional device 45 of a single-channel type device including a single transformer 21 may be adopted.

[0135] <Transformer arrangement> 9 is a plan view (top view) showing a schematic example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the above-mentioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0136] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s forming a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s forming a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0137] Moreover, pads a3 and b3 are connected to one end of a secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0138] Note that the primary coil forming the first transformer 301, the primary coil forming the second transformer 302, the primary coil forming the third transformer 303, and the primary coil forming the fourth transformer 304 are not shown in the figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s, respectively.

[0139] That is, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0140] Moreover, pads a7 and b7 are connected to one end of a primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Moreover, pads a8 and b8 are connected to one end of a primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0141] However, the above-mentioned pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0142] Among the above-mentioned pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0143] Therefore, the transformer chip 300 of this configuration example can accurately measure the series resistance component of each coil during the defective product inspection. Therefore, it is possible to not only reject defective products in which each coil has a break in wiring, but also to appropriately reject defective products in which each coil has an abnormal resistance value (for example, a short circuit between coils), and ultimately to prevent defective products from being released onto the market.

[0144] For the transformer chip 300 that has passed the defective product inspection, the above-mentioned multiple pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0145] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0146] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0147] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner of being coupled for each signal transmission direction, as shown in Fig. 9. In accordance with this figure, for example, the first transformer 301 and the second transformer 302 which transmit signals from the primary side chip to the secondary side chip are made into a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 which transmit signals from the secondary side chip to the primary side chip are made into a second pair by a second guard ring 306.

[0148] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil forming each of the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0149] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0150] In the transformer chip 300, the pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. The pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. The pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. The pads c4 and d4 are shared between the corresponding primary coils. With this configuration, the number of pads can be reduced, and the transformer chip 300 can be made smaller.

[0151] 9, the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are desirably wound in a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. With this configuration, the area of ​​the overlapping portion between the primary coil and the secondary coil becomes larger, and the transmission efficiency of the transformer can be improved.

[0152] Of course, the transformer arrangement in this figure is merely one example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. In addition, the chip structure and transformer arrangement described so far can be applied to semiconductor devices in general in which coils are integrated on a semiconductor chip.

[0153] <Electronic device (first comparative example)> 10 is a diagram showing a first comparative example of an electronic device (= an example of a configuration to be compared with the first embodiment described later). The electronic device A of this comparative example includes a transistor QH (e.g., a P-channel MOSFET [metal oxide semiconductor field effect transistor]), a sense resistor RH, and a semiconductor device 400.

[0154] In this specification, a MOSFET refers to a transistor whose gate structure is composed of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value, an insulating layer, and a P-type, N-type, or intrinsic semiconductor layer. In other words, the gate structure of a MOSFET is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0155] A first end of the sense resistor RH is connected to a terminal to which a power supply voltage VCC2 is applied. A second end of the sense resistor RH and the source and back gate of the transistor QH are all connected to a sense terminal REFH of the semiconductor device 400. A drain of the transistor QH is connected to an output node ND. A gate of the transistor QH is connected to an output terminal OUTH of the semiconductor device 400 (=a terminal to which a gate signal GH is applied).

[0156] The transistor QH is an upper switch connected between the application terminal of the power supply voltage VCC2 and the output node ND. The transistor QH is driven by the semiconductor device 400. Specifically, the transistor QH is turned on when the gate signal GH is at a low level. When the transistor QH is on, an output current IH flows from the application terminal of the power supply voltage VCC2 to the output node ND via the transistor QH. On the other hand, the transistor QH is turned off when the gate signal GH is at a high level. When the transistor QH is off, the output current IH is cut off.

[0157] The sense resistor RH is provided in a path through which the output current IH flows. The sense resistor RH generates a sense voltage V2H (=VCC2-IH×RH) according to the output current IH. The sense voltage V2H is drawn from a second end of the sense resistor RH.

[0158] Although not shown in the figure, the gate of a power transistor (for example, an IGBT [insulated gate bipolar transistor]) may be connected to the output node ND.

[0159] Continuing with the description of the semiconductor device 400, the semiconductor device 400 includes a drive circuit 410, a reference current generating circuit 420, a set voltage generating circuit 430, and a constant current control circuit 440.

[0160] The driving circuit 410 generates a gate signal GH for driving the transistor QH. With reference to this figure, the driving circuit 410 includes a transistor 411 (e.g., a P-channel MOSFET), a transistor 412 (N-channel MOSFET), and a driver 413. Although not shown in this figure, the driving circuit 410 may include a means for turning off the transistor 412 (e.g., a switch element for shorting the gate and source of the transistor 412).

[0161] The source and back gate of the transistor 411 are connected to the application terminal of the power supply voltage VCC2. The drains of the transistors 411 and 412 are connected to the output terminal OUTH (=the application terminal of the gate signal GH). The source and back gate of the transistor 412 are connected to the ground terminal. The gate of the transistor 411 is connected to the output terminal of the driver 413. The gate of the transistor 412 is connected to the application terminal of the feedback control signal V3H (described in detail later). In this way, the transistors 411 and 412 form a half-bridge output stage for outputting the gate signal GH to the output terminal OUTH.

[0162] When the transistor 411 is on and the transistor 412 is off, the gate signal GH goes to a high level (≈VCC2), and the transistor QH goes to an off state, so that the output current IH does not flow.

[0163] On the other hand, when the transistor 411 is in an off state and the transistor 412 is in an on state, the gate signal GH becomes a low level (≦V2H−Vth(QH)). Note that Vth(QH) is the on threshold voltage of the transistor QH. Therefore, the transistor QH is in an on state, and the output current IH flows.

[0164] The reference current generating circuit 420 generates predetermined reference currents I2 and I3. Referring to this figure, the reference current generating circuit 420 includes transistors 421 to 423 (for example, N-channel MOSFETs) and a current source 424.

[0165] A first terminal of the current source 424 is connected to the application terminal of the power supply voltage VCC2. A second terminal of the current source 424 is connected to the drain of the transistor 421. The gates of the transistors 421 to 423 are all connected to the drain of the transistor 421. The sources and back gates of the transistors 421 to 423 are all connected to the ground terminal. The drain of the transistor 423 is connected to the gate of the transistor 412 (=the application terminal of the feedback control signal V3H).

[0166] The current source 424 generates a reference current I1. The transistors 421 to 423 generate reference currents I2 and I3 (for example, I2=I3=α×I1) according to the reference current I1 input to the drain of the transistor 421, and output them from the drains of the transistors 422 and 423. That is, the transistors 421 to 423 function as a current mirror.

[0167] The set voltage generating circuit 430 includes a DAC [digital-to-analog converter] 431, amplifiers 432 and 433, a transistor 434 (for example, an N-channel MOSFET), and resistors 435 and 436 (each having a resistance value of R0).

[0168] The DAC 431 converts a digital input signal (not shown) into an analog output signal (variable reference voltage VrefHx in this figure). The digital input signal can be understood as a control signal for switching the constant current setting value IrefH of the output current IH.

[0169] A non-inverting input terminal (+) of the amplifier 432 is connected to an output terminal (= application terminal of the variable reference voltage VrefHx) of the DAC 431. An output terminal of the amplifier 432 is connected to a gate of a transistor 434. An inverting input terminal (-) of the amplifier 432, a source and a back gate of the transistor 434, and a first terminal of a resistor 435 are all connected to an application terminal of a node voltage Va. A second terminal of the resistor 435 is connected to a ground terminal. A first terminal of the resistor 436 is connected to an application terminal of a power supply voltage VCC2. A second terminal of the resistor 436 and a drain of the transistor 434 are all connected to an application terminal of a node voltage Vb.

[0170] The amplifier 432, the transistor 434, and the resistor 435 convert the variable reference voltage VrefHx into a variable reference current IrefHx (=VrefHx / R0). The resistor 436 converts the variable reference current IrefHx into a node voltage Vb (=VCC2-IrefHx×R0=VCC2-VrefHx).

[0171] A non-inverting input terminal (+) of the amplifier 433 is connected to an application terminal of the node voltage Vb. An inverting input terminal (-) of the amplifier 433 and an output terminal of the amplifier 433 are both connected to an application terminal of the set voltage V1H. The amplifier 433 functions as a buffer that outputs the node voltage Vb as the set voltage V1H.

[0172] The constant current control circuit 440 generates a feedback control signal V3H for the drive circuit 410 so that the sense voltage V2H (=VCC2-IH×RH) coincides with the set voltage V1H (=VCC2-VrefHx). In other words, the constant current control circuit 440 generates the feedback control signal V3H so that the output current IH coincides with the constant current set value IrefH (=VrefHx / RH).

[0173] Referring to this figure, the constant current control circuit 440 includes resistors 441 and 442, and transistors 443 to 446 (e.g., P-channel MOSFETs). A first terminal of the resistor 441 is connected to an application terminal of the set voltage V1H. A first terminal of the resistor 442 is connected to an application terminal of the sense voltage V2H.

[0174] The source and back gate of the transistor 443 are connected to the second end of the resistor 441. The source and back gate of the transistor 444 are connected to the second end of the resistor 442. The gates of the transistors 443 and 444 are both connected to the drain of the transistor 443.

[0175] The source and back gate of the transistor 445 are connected to the drain of the transistor 443. The source and back gate of the transistor 446 are connected to the drain of the transistor 444. The gates of the transistors 445 and 446 are both connected to the drain of the transistor 445. The drain of the transistor 445 is connected to the drain of the transistor 422. The drain of the transistor 446 is connected to the gate of the transistor 412 (=the application terminal of the feedback control signal V3H).

[0176] The resistor 441 corresponds to a first resistor connected between the application terminal of the set voltage V1H and the source of the transistor 443. The resistor 442 corresponds to a second resistor connected between the application terminal of the sense voltage V2H and the source of the transistor 444.

[0177] The transistor 443 corresponds to a first transistor connected between the application terminal of the set voltage V1H and the application terminal of the reference current I2. The transistor 444 corresponds to a second transistor connected between the application terminal of the sense voltage V2H and the application terminal of the feedback control signal V3H. The transistors 443 and 444 are preferably formed to have a higher pairing property than the transistors 445 and 446.

[0178] The transistor 445 corresponds to a third transistor connected between the drain of the transistor 443 and the application terminal of the reference current I2. The transistor 446 corresponds to a fourth transistor connected between the drain of the transistor 444 and the application terminal of the feedback control signal V3H. The transistors 445 and 446 are preferably formed to have a higher drain-source breakdown voltage than the transistors 443 and 444.

[0179] The feedback control signal V3H rises when the sense voltage V2H is higher than the set voltage V1H, in other words, when the output current IH is smaller than the constant current set value IrefH. The higher the feedback control signal V3H, the more conductive the transistor 412 becomes, and the lower the gate signal GH becomes. As a result, the conductive degree of the transistor QH increases, and the output current IH increases.

[0180] On the other hand, the feedback control signal V3H decreases when the sense voltage V2H is lower than the set voltage V1H, in other words, when the output current IH is greater than the constant current set value IrefH. The lower the feedback control signal V3H, the lower the conductivity of the transistor 412, and the higher the gate signal GH. As a result, the conductivity of the transistor QH decreases, and the output current IH decreases.

[0181] The series of feedback controls described above adjusts the output current IH to the constant current setting value IrefH.

[0182] <Considerations regarding switching delay of constant current setting value IrefH> In the semiconductor device 400 of this comparative example, the set voltage V1H (and hence the constant current set value IrefH) is switched by controlling the switching of the variable reference voltage VrefHx. However, two amplifiers 432 and 433 are interposed between the application terminal of the variable reference voltage VrefHx and the application terminal of the set voltage V1H. Therefore, the transition time from when the variable reference voltage VrefHx is switched to when the set voltage V1H (and hence the constant current set value IrefH) is switched becomes long. As a result, a delay in switching the constant current set value IrefH may occur. Below, a first embodiment that can solve the above problem is proposed.

[0183] <Electronic Device (First Embodiment)> 11 is a diagram showing a first embodiment of an electronic device. The electronic device A of this embodiment is based on the above-mentioned first comparative example (FIG. 10), but has a modification to the internal configuration of the semiconductor device 400. In accordance with this figure, the semiconductor device 400 includes a variable resistance circuit 450 instead of the above-mentioned set voltage generating circuit 430.

[0184] The variable resistance circuit 450 is provided in a path through which the reference current I2 flows, and generates a set voltage V1H according to a control signal CTL. The variable resistance circuit 450 includes, for example, a plurality of resistors 451(1) to 451(n) (n≧2) and at least one switch 452 (for example, a P-channel MOSFET). The switch 452 may be a CMOS [complementary MOS] analog switch that combines a P-channel MOSFET and an N-channel MOSFET, a so-called transmission gate.

[0185] The resistors 451(1) to 451(n) may be connected in series between the application terminal of the power supply voltage VCC2 and the application terminal of the set voltage V1H (= the first terminal of the resistor 441), for example. However, the connection form of the resistors 451(1) to 451(n) is not limited to this. As another connection form, the resistors 451(1) to 451(n) may be connected in parallel between the application terminal of the power supply voltage VCC2 and the application terminal of the set voltage V1H, for example.

[0186] The switch 452 switches the connection relationship of the resistors 451(1) to 451(n) so that the combined resistance value R2 of the resistors 451(1) to 451(n) changes in response to the control signal CTL. The switch 452 may be connected in parallel to the resistor 451(1) as shown in this diagram.

[0187] For example, consider a case where the resistance value of each of the resistors 451(1) to 451(n) is R. In this case, when the control signal CTL is at a high level, the switch 452 is turned off. Therefore, both ends of the resistor 451(1) are opened. As a result, the combined resistance value R2 becomes n×R. On the other hand, when the control signal CTL is at a low level, the switch 452 is turned on. Therefore, both ends of the resistor 451(1) are shorted. As a result, the combined resistance value R2 becomes (n-1)×R. In this way, the combined resistance value R2 is switched according to the logic level of the control signal CTL. That is, the control signal CTL can be understood as a control signal for switching the constant current setting value IrefH of the output current IH.

[0188] For ease of explanation, only one switch 452 is provided in this diagram. However, the number of switches 452 is not limited to this. For example, switches 452(1)-452(n) may be connected in parallel to resistors 451(1)-451(n), respectively. In this case, switches 452(1)-452(n) may be individually controlled in response to control signals CTL(1)-CTL(n), respectively.

[0189] Furthermore, the resistance values ​​of the resistors 451(1) to 451(n) do not necessarily have to be a common value (resistance value R). For example, the resistance values ​​of the resistors 451(1) to 451(n) may be R, 2×R, 4×R, . . . , 2 n-1 It may also have weighting such as ×R.

[0190] In this embodiment, the components of the current source 424 include an amplifier 425, a transistor 426 (for example, an N-channel MOSFET), a resistor 427 (resistance value: R1), and transistors 428 and 429 (for example, P-channel MOSFETs).

[0191] A non-inverting input terminal (+) of the amplifier 425 is connected to an application terminal of a reference voltage VrefH. An output terminal of the amplifier 425 is connected to a gate of a transistor 426. An inverting input terminal (-) of the amplifier 425, a source and a back gate of the transistor 426, and a first terminal of a resistor 427 are all connected to an application terminal of a node voltage Vc. A second terminal of the resistor 427 is connected to a ground terminal.

[0192] The amplifier 425, the transistor 426, and the resistor 427 convert the reference voltage VrefH into a reference current I0 (=VrefH / R1).

[0193] The drain of the transistor 426 is connected to the drain of the transistor 428. The gates of the transistors 428 and 429 are both connected to the drain of the transistor 428. The sources and back gates of the transistors 428 and 429 are both connected to the application terminal of the power supply voltage VCC2. The drain of the transistor 429 is connected to the drain of the transistor 421.

[0194] The transistors 428 and 429 generate a reference current I1 (for example, I1=β×I0) according to a reference current I0 input to the drain of the transistor 428, and output it from the drain of the transistor 429. That is, the transistors 428 and 429 function as a current mirror.

[0195] In the semiconductor device 400 of this embodiment, the variable resistance circuit 450 converts the reference current I2 into a set voltage V1H (=VCC2-I2×R2=VCC2-α×β×VrefH / R1×R2). Therefore, the output current IH is feedback-controlled so as to match the constant current set value IrefH (=α×β×VrefH / R1×R2 / RH).

[0196] Here, the set voltage V1H is switched without delay by turning on / off the switch 452. Therefore, compared to the above-mentioned first comparative example (FIG. 10), the switching delay of the set voltage V1H (and hence the constant current set value IrefH) is suppressed.

[0197] Like the signal transmission device 200 described above, the semiconductor device 400 may be an insulated gate driver IC that transmits a drive signal (IN → OUT) from the primary circuit system 200p to the secondary circuit system 200s while isolating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system).

[0198] In this case, the drive circuit 410, the reference current generating circuit 420, the constant current control circuit 440, and the variable resistance circuit 450 may all be provided in the secondary circuit system 200s. The drive circuit 410 may drive the transistor QH in response to a drive signal (IN→OUT) transmitted from the primary circuit system 200p to the secondary circuit system 200s.

[0199] <Electronic device (second comparative example)> 12 is a diagram showing a second comparative example of an electronic device (= an example of a configuration to be compared with the second embodiment described later). The electronic device A of this comparative example includes a transistor QL (e.g., an N-channel MOSFET), a sense resistor RL, and a semiconductor device 500.

[0200] A first end of the sense resistor RL is connected to a ground end (= an application end of a ground voltage GND2). A second end of the sense resistor RL and a source and a back gate of the transistor QL are all connected to a sense terminal REFL of the semiconductor device 500. A drain of the transistor QL is connected to an output node ND. A gate of the transistor QL is connected to an output terminal OUTH of the semiconductor device 500 (= an application end of a gate signal GL).

[0201] The transistor QL is a lower switch connected between the output node ND and the ground terminal. The transistor QL is driven by the semiconductor device 500. Specifically, the transistor QL is turned on when the gate signal GL is at a high level. When the transistor QL is on, an output current IL flows from the output node ND to the ground terminal via the transistor QL. On the other hand, the transistor QL is turned off when the gate signal GL is at a low level. When the transistor QL is off, the output current IL is cut off.

[0202] The sense resistor RL is provided in a path through which the output current IL flows. The sense resistor RL generates a sense voltage V2L (=IL×RL) according to the output current IL. The sense voltage V2L is drawn from a second terminal of the sense resistor RL.

[0203] Although not shown in the figure, the output node ND may be connected to the gate of a power transistor (for example, an IGBT).

[0204] Continuing with the description of the semiconductor device 500, with reference to Fig. 12, the semiconductor device 500 includes a drive circuit 510, a reference current generating circuit 520, a set voltage generating circuit 530, and a constant current control circuit 540.

[0205] The driving circuit 510 generates a gate signal GL for driving the transistor QL. With reference to this figure, the driving circuit 510 includes a transistor 511 (e.g., a P-channel MOSFET), a transistor 512 (N-channel MOSFET), and a driver 513. Although not shown in this figure, the driving circuit 510 may include a means for turning off the transistor 511 (e.g., a switch element for shorting the gate and source of the transistor 511).

[0206] The source and back gate of the transistor 511 are connected to the application terminal of the power supply voltage VCC2. The drains of the transistors 511 and 512 are connected to the output terminal OUTL (=the application terminal of the gate signal GL). The source and back gate of the transistor 512 are connected to the ground terminal. The gate of the transistor 512 is connected to the output terminal of the driver 513. The gate of the transistor 511 is connected to the application terminal of the feedback control signal V3L (described in detail later). In this way, the transistors 511 and 512 form a half-bridge output stage for outputting the gate signal GL to the output terminal OUTL.

[0207] When the transistor 512 is on and the transistor 511 is off, the gate signal GL goes to a low level (≈GND2), and the transistor QL goes to an off state, so that the output current IL does not flow.

[0208] On the other hand, when the transistor 512 is in an off state and the transistor 511 is in an on state, the gate signal GL becomes a high level (≧VLH+Vth(QL)). Note that Vth(QL) is the on threshold voltage of the transistor QL. Therefore, the transistor QL is in an on state, and the output current IL flows.

[0209] The reference current generating circuit 520 generates predetermined reference currents I2 and I3. Referring to the figure, the reference current generating circuit 520 includes transistors 521 to 523 (eg, P-channel MOSFETs) and a current source 524.

[0210] A first terminal of the current source 524 is connected to the ground terminal. A second terminal of the current source 524 is connected to the drain of the transistor 521. The gates of the transistors 521 to 523 are all connected to the drain of the transistor 521. The sources and back gates of the transistors 521 to 523 are all connected to the application terminal of the power supply voltage VCC2. The drain of the transistor 523 is connected to the gate of the transistor 512 (=the application terminal of the feedback control signal V3L).

[0211] The current source 524 generates a reference current I1. The transistors 521 to 523 generate reference currents I2 and I3 (for example, I2=I3=α×I1) according to the reference current I1 input to the drain of the transistor 521, and output them from the drains of the transistors 522 and 523, respectively. That is, the transistors 521 to 523 function as a current mirror.

[0212] The set voltage generating circuit 530 includes a DAC 531 and an amplifier 532 .

[0213] The DAC 531 converts a digital input signal (not shown) into an analog output signal (variable reference voltage VrefLx in this figure). The digital input signal can be understood as a control signal for switching the constant current setting value IrefL of the output current IL.

[0214] A non-inverting input terminal (+) of the amplifier 532 is connected to an application terminal of the variable reference voltage VrefLx. An inverting input terminal (-) of the amplifier 532 and an output terminal of the amplifier 532 are both connected to an application terminal of the set voltage V1L. The amplifier 532 functions as a buffer that outputs the variable reference voltage VrefLx as the set voltage V1L.

[0215] The constant current control circuit 540 generates a feedback control signal V3L for the drive circuit 510 so that the sense voltage V2L (=IL×RL) coincides with the set voltage V1L (=VrefLx). In other words, the constant current control circuit 540 generates the feedback control signal V3L so that the output current IL coincides with the constant current set value IrefL (=VrefLx / RL).

[0216] Referring to this figure, the constant current control circuit 540 includes resistors 541 and 542 and transistors 543 to 546 (e.g., N-channel MOSFETs). A first terminal of the resistor 541 is connected to an application terminal of the set voltage V1L. A first terminal of the resistor 542 is connected to an application terminal of the sense voltage V2L.

[0217] The source and back gate of the transistor 543 are connected to the second end of the resistor 541. The source and back gate of the transistor 544 are connected to the second end of the resistor 542. The gates of the transistors 543 and 544 are both connected to the drain of the transistor 543.

[0218] The source and back gate of transistor 545 are connected to the drain of transistor 543. The source and back gate of transistor 546 are connected to the drain of transistor 544. The gates of transistors 545 and 546 are both connected to the drain of transistor 545. The drain of transistor 545 is connected to the drain of transistor 522. The drain of transistor 546 is connected to the gate of transistor 511 (=application terminal of feedback control signal V3L).

[0219] The resistor 541 corresponds to a first resistor connected between the application terminal of the set voltage V1L and the source of the transistor 543. The resistor 542 corresponds to a second resistor connected between the application terminal of the sense voltage V2L and the source of the transistor 544.

[0220] The transistor 543 corresponds to a first transistor connected between the application terminal of the set voltage V1L and the application terminal of the reference current I2. The transistor 544 corresponds to a second transistor connected between the application terminal of the sense voltage V2L and the application terminal of the feedback control signal V3L. The transistors 543 and 544 are preferably formed to have a higher pairing property than the transistors 545 and 546.

[0221] The transistor 545 corresponds to a third transistor connected between the drain of the transistor 543 and the application terminal of the reference current I2. The transistor 546 corresponds to a fourth transistor connected between the drain of the transistor 544 and the application terminal of the feedback control signal V3L. The transistors 545 and 546 are preferably formed to have a higher drain-source breakdown voltage than the transistors 543 and 544.

[0222] The feedback control signal V3L decreases when the sense voltage V2L is lower than the set voltage V1L, in other words, when the output current IL is smaller than the constant current set value IrefL. The lower the feedback control signal V3L, the higher the conductivity of the transistor 511, and the higher the gate signal GL. As a result, the conductivity of the transistor QL increases, and the output current IL increases.

[0223] On the other hand, the feedback control signal V3L rises when the sense voltage V2L is higher than the set voltage V1L, in other words, when the output current IL is greater than the constant current set value IrefL. The higher the feedback control signal V3L, the lower the conductivity of the transistor 511, and the lower the gate signal GL. As a result, the conductivity of the transistor QL decreases, and the output current IL decreases.

[0224] The above series of feedback controls causes the output current IL to match the constant current setting value IrefL.

[0225] <Considerations regarding switching delay of constant current setting value IrefL> In the semiconductor device 500 of this comparative example, the set voltage V1L (and hence the constant current set value IrefL) is switched by controlling the switching of the variable reference voltage VrefLx. However, an amplifier 532 is interposed between the application terminal of the variable reference voltage VrefLx and the application terminal of the set voltage V1L. Therefore, the transition time from when the variable reference voltage VrefLx is switched to when the set voltage V1L (and hence the constant current set value IrefL) is switched becomes long. As a result, a delay in switching the constant current set value IrefL may occur. Below, a second embodiment that can solve the above problem is proposed.

[0226] <Electronic Device (Second Embodiment)> 13 is a diagram showing a second embodiment of an electronic device. The electronic device A of this embodiment is based on the above-mentioned second comparative example (FIG. 12), but has a modification to the internal configuration of the semiconductor device 500. In accordance with this figure, the semiconductor device 500 includes a variable resistance circuit 550 instead of the above-mentioned set voltage generating circuit 530.

[0227] The variable resistance circuit 550 is provided in a path through which the reference current I2 flows, and generates a set voltage V1L according to a control signal CTL. The variable resistance circuit 550 includes, for example, a plurality of resistors 551(1) to 551(n) (where n≧2) and at least one switch 552 (for example, an N-channel MOSFET). The switch 552 may be a CMOS analog switch that combines a P-channel MOSFET and an N-channel MOSFET, a so-called transmission gate.

[0228] The resistors 551(1) to 551(n) may be connected in series between the ground terminal and the application terminal of the set voltage V1L (= the first terminal of the resistor 541), for example. However, the connection form of the resistors 551(1) to 551(n) is not limited to this in any way. As another connection form, the resistors 551(1) to 551(n) may be connected in parallel between the ground terminal and the application terminal of the set voltage V1L, for example.

[0229] The switch 552 switches the connection relationship of the resistors 551(1) to 551(n) so that the combined resistance value R4 of the resistors 551(1) to 551(n) changes in response to the control signal CTL. The switch 552 may be connected in parallel to the resistor 551(1) as shown in this diagram.

[0230] For example, consider a case where the resistance value of each of the resistors 551(1) to 551(n) is R. In this case, when the control signal CTL is at a low level, the switch 552 is turned off. Therefore, both ends of the resistor 551(1) are opened. As a result, the combined resistance value R2 becomes n×R. On the other hand, when the control signal CTL is at a high level, the switch 552 is turned on. Therefore, both ends of the resistor 551(1) are shorted. As a result, the combined resistance value R2 becomes (n-1)×R. In this way, the combined resistance value R2 is switched according to the logical level of the control signal CTL. That is, the control signal CTL can be understood as a control signal for switching the constant current setting value IrefL of the output current IL.

[0231] For ease of explanation, only one switch 552 is provided in this diagram. However, the number of switches 552 is not limited to this. For example, switches 552(1)-552(n) may be connected in parallel to resistors 551(1)-551(n), respectively. In this case, switches 552(1)-552(n) may be individually controlled in response to control signals CTL(1)-CTL(n), respectively.

[0232] Furthermore, the resistance values ​​of the resistors 551(1) to 551(n) do not necessarily have to be a common value (resistance value R). For example, the resistance values ​​of the resistors 551(1) to 551(n) may be R, 2×R, 4×R, . . . , 2 n-1 It may also have weighting such as ×R.

[0233] In this embodiment, the components of the current source 524 include an amplifier 525, a transistor 526 (for example, an N-channel MOSFET), and a resistor 527 (resistance value: R3).

[0234] A non-inverting input terminal (+) of the amplifier 525 is connected to an application terminal of a reference voltage VrefL. An output terminal of the amplifier 525 is connected to a gate of a transistor 526. An inverting input terminal (-) of the amplifier 525, a source and a back gate of the transistor 526, and a first terminal of a resistor 527 are all connected to an application terminal of a node voltage Vd. A second terminal of the resistor 527 is connected to a ground terminal.

[0235] An amplifier 525, a transistor 526, and a resistor 527 convert the reference voltage VrefL into a reference current I1 (=VrefL / R3).

[0236] In the semiconductor device 500 of this embodiment, the variable resistor circuit 550 converts the reference current I2 into a set voltage V1L (=I2×R4=α×VrefL / R3×R4). Therefore, the output current IL is feedback-controlled so as to match the constant current set value IrefL (=α×VrefL / R3×R4 / RL).

[0237] Here, the set voltage V1L is switched without delay by turning on / off the switch 552. Therefore, compared to the above-mentioned second comparative example (FIG. 12), the switching delay of the set voltage V1L (and hence the constant current set value IrefL) is suppressed.

[0238] In addition, like the previously described signal transmission device 200, the semiconductor device 500 may be an insulated gate driver IC that transmits a drive signal (IN → OUT) from the primary circuit system 200p to the secondary circuit system 200s while isolating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system).

[0239] In this case, the drive circuit 510, the reference current generating circuit 520, the constant current control circuit 540, and the variable resistance circuit 550 may all be provided in the secondary circuit system 200s. The drive circuit 510 may drive the transistor QL in response to a drive signal (IN→OUT) transmitted from the primary circuit system 200p to the secondary circuit system 200s.

[0240] <Application to vehicles> 14 is a diagram showing the exterior of a vehicle B. Vehicle B of this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0241] Vehicle B includes not only engine vehicles but also electric vehicles (BEVs [battery electric vehicles], HEVs [hybrid electric vehicles], PHEVs / PHVs (plug-in hybrid electric vehicle / plug-in hybrid vehicle), or xEVs such as FCEVs / FCVs (fuel cell electric vehicle / fuel cell vehicle)).

[0242] The signal transmission device 200 and the semiconductor devices 400 and 500 described above can be incorporated into any of the electronic devices mounted on the vehicle B.

[0243] <Additional Notes> According to the present disclosure, the switching delay of the set voltages V1H and V1L, and further the switching delay of the constant current set values ​​IrefH and IrefL, can be suppressed.

[0244] [Appendix 1] a drive circuit (410, 510) configured to drive the transistors (QH, QL); a reference current generating circuit (420, 520) configured to generate a predetermined reference current (I2); A variable resistance circuit (450, 550) provided in a path through which the reference current (I2) flows and configured to generate a set voltage (V1H, V1L) according to a control signal (CTL); a constant current control circuit (440, 540) configured to generate a feedback control signal (V3H, V3L) for the drive circuit (410, 510) so that a sense voltage (V2H, V2L) corresponding to an output current (IH, IL) flowing through the transistor (QH, QL) coincides with the set voltage (V1H, V1L); A semiconductor device (400, 500) comprising:

[0245] [Appendix 2] The semiconductor device (400, 500) according to appended claim 1, wherein the variable resistance circuit (450, 550) includes a plurality of resistors (451(1) to 451(n), 551(1) to 551(n)) and at least one switch (452, 552) configured to switch a connection relationship of the plurality of resistors (451(1) to 451(n), 551(1) to 551(n)) so that a combined resistance value of the plurality of resistors (451(1) to 451(n), 551(1) to 551(n)) changes in response to the control signal (CTL).

[0246] [Appendix 3] The constant current control circuit (440, 540) includes a first transistor (443, 543) connected between an application terminal of the set voltage (V1H, V1L) and an application terminal of the reference current (I2), and a second transistor (444, 544) connected between an application terminal of the sense voltage (V2H, V2L) and an application terminal of the feedback control signal (V3H, V3L), The semiconductor device (400, 500) according to appendix 1 or 2, wherein the gates of the first transistor (443, 543) and the second transistor (444, 544) are both connected to the drain of the first transistor (443, 543).

[0247] [Appendix 4] The constant current control circuit (440, 540) further includes a third transistor (445, 545) connected between the drain of the first transistor (443, 543) and an application terminal of the reference current (I2), and a fourth transistor (446, 546) connected between the drain of the second transistor (444, 544) and an application terminal of the feedback control signal (V3H, V3L), The semiconductor device (400, 500) according to appended claim 3, wherein a gate of each of the third transistor (445, 545) and the fourth transistor (446, 546) is connected to a drain of the third transistor (445, 545).

[0248] [Appendix 5] The semiconductor device (400, 500) described in Appendix 3 or 4, wherein the constant current control circuit (440, 540) includes a first resistor (441, 541) connected between an application terminal of the set voltage (V1H, V1L) and a source of the first transistor (443, 543), and a second resistor (442) connected between an application terminal of the sense voltage (V2H, V2L) and a source of the second transistor (444, 544).

[0249] [Appendix 6] The semiconductor device (400, 500) is a signal transmission device (200) configured to transmit a drive signal from a primary circuit system (200p) to a secondary circuit system (200s) while insulating the primary circuit system (200p) from the secondary circuit system (200s), the drive circuit (410, 510), the reference current generating circuit (420, 520), the variable resistance circuit (450, 550), and the constant current control circuit (440, 540) are all provided in the secondary circuit system (200s); The semiconductor device (400, 500) according to any one of appendices 1 to 5, wherein the drive circuit (410, 510) drives the transistors (QH, QL) in response to the drive signal.

[0250] [Appendix 7] A semiconductor device (400, 500) according to any one of appendixes 1 to 6; The transistors (QH, QL) configured to be driven by the semiconductor device (400, 500); An electronic device (A).

[0251] [Appendix 8] The electronic device (A) described in Appendix 7, wherein the transistor (QH, QL) is an upper switch (QH) connected between an application terminal of a power supply voltage (VCC2) and an output node (ND), or a lower switch (QL) connected between the output node (ND) and a ground terminal (GND2).

[0252] [Appendix 9] The electronic device (A) described in Appendix 7 or 8, further comprising a sense resistor (RH, RL) provided in a path through which the output current (IH, IL) flows and configured so that the sense voltage (V2H, V2L) is drawn from one end.

[0253] [Appendix 10] A vehicle (B) equipped with an electronic device (A) according to any one of appendices 7 to 9.

[0254] <Other> In addition, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation, in addition to the above-mentioned embodiment. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects. In addition, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0255] 5. Semiconductor Devices 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor Chip 42 First main surface 43 Second main surface 44A~44D Chip side wall 45 First Functional Device 51 Insulating layer 52 Insulating surface 53A~53D Insulated sidewall 55 Bottom insulation layer 56 Top insulation layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through Wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 Board plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 2nd Pattern 95 3rd Pattern 96 First Outer Line 97 2nd Outer Line 98 1st Intermediate Line 99 First connecting line 100 Slits 130 Separation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic Insulating Layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmission circuit (pulse generator) 212, 213 Buffer 220 Driver Chip (2nd Chip) 221, 222 Buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Trans Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 Transformers 231p, 232p Primary coil 231s, 232s Secondary coil 300 Trans Chip 301 1st transformer 302 2nd Transformer 303 3rd Transformer 304 4th Transformer 305 1st Guard Ring 306 2nd Guard Ring 400 Semiconductor equipment 410 Drive circuit 411 Transistor (P-channel MOSFET) 412 Transistor (N-channel MOSFET) 413 Driver 420 Reference current generation circuit 421~423 Transistors (N-channel MOSFETs) 424 Current Source 425 Amplifier 426 Transistor (N-channel MOSFET) 427 Resistance 428, 429 Transistor (P-channel MOSFET) 430 Set voltage generation circuit 431 DAC 432, 433 Amplifier 434 Transistor (N-channel MOSFET) 435, 436 Resistance 440 Constant current control circuit 441, 442 Resistance 443~446 Transistors (P-channel MOSFETs) 450 Variable Resistor Circuit 451(1)~451(n) Resistance 452 Switch (P-channel MOSFET) 500 Semiconductor device 510 Drive circuit 511 Transistor (P-channel MOSFET) 512 Transistor (N-channel MOSFET) 513 Driver 520 Reference current generation circuit 521~523 Transistors (P-channel MOSFETs) 524 Current Source 525 Amplifier 526 Transistor (N-channel MOSFET) 527 Resistance 530 Setting voltage generation circuit 531 DAC 532 Amplifier 540 Constant current control circuit 541, 542 Resistance 543~546 Transistors (N-channel MOSFETs) 550 Variable Resistor Circuit 551(1)~551(n) Resistance 552 Switch (N-channel MOSFET) a1 to a8 pads (corresponding to the first current supply pads) b1~b8 Pads (corresponding to the first voltage measurement pads) c1~c4 Pads (corresponding to the second current supply pads) d1~d4 Pads (corresponding to the second voltage measurement pads) e1, e2 pads A Electronic equipment B Vehicle L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil ND Output Node OUTH, OUTL output terminals QH transistor (P-channel MOSFET) QL transistor (N-channel MOSFET) REFH, REFL sense terminals RH, RL sense resistor T21, T22, T23, T24, T25, T26 External terminals X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias

Claims

1. a drive circuit configured to drive the transistor; a reference current generating circuit configured to generate a predetermined reference current; a variable resistance circuit provided in a path through which the reference current flows and configured to generate a set voltage in response to a control signal; a constant current control circuit configured to generate a feedback control signal for the drive circuit so that a sense voltage corresponding to an output current flowing through the transistor coincides with the set voltage; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the variable resistance circuit includes a plurality of resistors and at least one switch configured to switch a connection relationship of the plurality of resistors so that a combined resistance value of the plurality of resistors changes in response to the control signal.

3. the constant current control circuit includes a first transistor connected between an application terminal of the set voltage and an application terminal of the reference current, and a second transistor connected between an application terminal of the sense voltage and an application terminal of the feedback control signal, 2 . The semiconductor device according to claim 1 , wherein a gate of each of said first transistor and said second transistor is connected to a drain of said first transistor.

4. the constant current control circuit further includes a third transistor connected between the drain of the first transistor and an application terminal of the reference current, and a fourth transistor connected between the drain of the second transistor and an application terminal of the feedback control signal, The semiconductor device according to claim 3 , wherein a gate of each of said third transistor and said fourth transistor is connected to a drain of said third transistor.

5. 4. The semiconductor device according to claim 3, wherein the constant current control circuit includes: a first resistor connected between an application terminal of the set voltage and a source of the first transistor; and a second resistor connected between an application terminal of the sense voltage and a source of the second transistor.

6. the semiconductor device is a signal transmission device configured to transmit a drive signal from a primary circuit system to a secondary circuit system while insulating the primary circuit system from a secondary circuit system, the drive circuit, the reference current generating circuit, the variable resistance circuit, and the constant current control circuit are all provided in the secondary circuit system; 6. The semiconductor device according to claim 1, wherein the drive circuit drives the transistor in response to the drive signal.

7. A semiconductor device according to claim 1; the transistor configured to be driven by the semiconductor device; An electronic device comprising:

8. 8. The electronic device according to claim 7, wherein the transistor is an upper switch connected between an application terminal of a power supply voltage and an output node, or a lower switch connected between the output node and a ground terminal.

9. 8. The electronic device according to claim 7, further comprising a sense resistor provided in a path through which the output current flows and configured so that the sense voltage is extracted from one end thereof.

10. A vehicle comprising the electronic device according to claim 7.

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