Semiconductor device

Abstract

To improve the reliability of a transistor including an oxide semiconductor by suppressing the variation in electric characteristics.SOLUTION: A semiconductor device includes a transistor. The transistor includes a first oxide semiconductor film on a first insulating film, a gate insulating film on the first oxide semiconductor film, a second oxide semiconductor film on the gate insulating film, and a second insulating film on the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film includes a channel region in contact with the gate insulating film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film. The second oxide semiconductor film has higher carrier density than the first oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. Regarding the device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to a product, a method, or a manufacturing method. process, machine, manufacture, or composition of matter In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, The present invention relates to a device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Semiconductor elements such as transistors, semiconductor circuits, computing devices, memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (field-effect transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology that makes up the field-effect transistor (FET) or thin-film transistor (TFT) is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices. Silicon is a semiconductor thin film that can be used in transistors. Semiconductor materials such as silicon are widely known, but oxide semiconductors are also attracting attention. It is being watched.

[0005] For example, amorphous oxides containing In, Zn, Ga, Sn, etc. are used as oxide semiconductors. A technique for fabricating a transistor using self-aligned transistors has been disclosed (see Patent Document 1). A technique for fabricating a transistor using a thin oxide film having a top gate structure has been disclosed (Patent (See Patent Document 2).

[0006] In addition, a base insulating layer of the oxide semiconductor layer in which a channel is formed is heated to release oxygen. A semiconductor device is disclosed in which an insulating layer is used to reduce oxygen vacancies in the oxide semiconductor layer. (See Patent Document 3). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2006-165529 A [Patent Document 2] JP 2009-278115 A [Patent Document 3] JP 2012-009836 A Summary of the Invention [Problem to be solved by the invention]

[0008] As a transistor having an oxide semiconductor film, for example, an inverted staggered type (bottom gate structure) The oxide semiconductor When a transistor having a thin film is applied to a display device, it is preferable to use an inverted type transistor rather than a staggered type transistor. The manufacturing process of staggered transistors is relatively simple and the manufacturing costs are reduced. However, as the screen size of display devices increases, Higher resolution image quality (for example, 4K x 2K (horizontal pixel count = 3840 pixels, vertical pixel count = 2160 pixels) or 8K x 4K (horizontal pixel count = 7680 pixels, vertical pixel count = As the development of high-resolution display devices (represented by 4320 pixels) progresses, the use of inverted staggered transistors Since there is a parasitic capacitance between the gate electrode and the source electrode and between the gate electrode and the drain electrode, This causes a problem of signal delay and the like becoming large, deteriorating the image quality of the display device. The present invention relates to a staggered transistor having an oxide semiconductor film, and There is a need to develop a highly reliable structure.

[0009] In addition, when a transistor is manufactured by using an oxide semiconductor film for a channel region, Oxygen vacancies formed in the channel region of the conductive film affect transistor characteristics. For example, when oxygen vacancies are formed in the channel region of the oxide semiconductor film, the oxygen Carriers are generated due to electron vacancies. Carriers are generated in the channel region of the oxide semiconductor film. When the oxide semiconductor film is generated, the electrical characteristics of a transistor having a channel region including the oxide semiconductor film change. Typically, a shift in threshold voltage occurs. In addition, the electrical characteristics of each transistor vary. Therefore, in the channel region of the oxide semiconductor film, oxygen vacancies are formed. On the other hand, in a transistor using an oxide semiconductor film for a channel region, In the present invention, the oxide semiconductor film in contact with the source electrode and the drain electrode is In order to reduce the contact resistance with the drain electrode, it is preferable that the contact has many oxygen vacancies and has low resistance.

[0010] In view of the above problems, one embodiment of the present invention is to provide a transistor including an oxide semiconductor. One of the objectives is to suppress fluctuations in thermal characteristics and improve reliability. An object of one embodiment of the present invention is to provide a staggered transistor including an oxide semiconductor. Alternatively, one embodiment of the present invention is a transistor having an oxide semiconductor and having a large on-state current. Another object of the present invention is to provide a transistor including an oxide semiconductor. Another object of the present invention is to provide a transistor having a low off-state current. An object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0011] The above description of the problem does not preclude the existence of other problems. The embodiment does not necessarily have to solve all of these problems. Problems other than those mentioned above may be solved by the specification. The above problems are obvious from the description of the specification, etc., and problems other than those mentioned above cannot be extracted from the description of the specification, etc. It is possible to issue it. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a transistor, the transistor comprising: a first oxide semiconductor film on the insulating film; a gate insulating film on the first oxide semiconductor film; a second oxide semiconductor film on the insulating film, a first oxide semiconductor film, and a second oxide semiconductor film and a second insulating film on the first oxide semiconductor film. a source region in contact with the second insulating film; a drain region in contact with the second insulating film; the second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film. It is a semiconductor device.

[0013] Another embodiment of the present invention is a semiconductor device including a transistor. The gate insulating film includes a first oxide semiconductor film on the first insulating film and a gate insulating film on the first oxide semiconductor film. a gate insulating film, a second oxide semiconductor film over the gate insulating film, and a conductive film over the second oxide semiconductor film; a first oxide semiconductor film and a second insulating film over the conductive film; The gate insulating film is connected to a channel region, the source region is connected to a second insulating film, and the second a drain region in contact with the insulating film, the second oxide semiconductor film being a first oxide semiconductor This is a semiconductor device having a higher carrier density than a film.

[0014] In the above embodiment, the upper end of the gate insulating film is in contact with the lower end of the second oxide semiconductor film. or a region located outside a bottom edge of the second oxide semiconductor film. I wish.

[0015] In the above embodiment, the second insulating film is formed of either or both of nitrogen and hydrogen. It is preferable that the compound has the following structure:

[0016] In the above embodiment, the transistor further includes a third insulating film on the second insulating film. A solenoid connected to the source region is formed through an opening provided in the second insulating film and the third insulating film. The source electrode is connected to the drain region through an opening provided in the second insulating film and the third insulating film. and a drain electrode connected to

[0017] In the above embodiment, the source region and the drain region are formed by a second oxide semiconductor film and a water In the above embodiment, the source region and the drain region have the same concentration of oxygen. The region contains one or more of the following elements: hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, or a rare gas. This would be preferable.

[0018] In the above embodiment, any one of the first oxide semiconductor film and the second oxide semiconductor film or one or both of oxygen, In, Zn, and M (wherein M is Al, Ga, Y, or Sn); In the above embodiment, the first oxide semiconductor film and the second oxide semiconductor film are preferably Either one or both of the nitride semiconductor films has a crystalline portion, and the crystalline portion has a c-axis orientation. It is preferable to do so.

[0019] Another embodiment of the present invention is a semiconductor device and a display device according to any one of the above embodiments. Another embodiment of the present invention is a display device including the display device and a touch sensor. In addition, another aspect of the present invention is a display module having any one of the above aspects. The semiconductor device according to any one of claims 1 to 5, the display device, or the display module, and an operation key or and a battery. Effect of the Invention

[0020] According to one embodiment of the present invention, a transistor including an oxide semiconductor can be prevented from fluctuating in electrical characteristics. By suppressing the above, the reliability can be improved. It is possible to provide a staggered transistor including an oxide semiconductor. According to one embodiment of the present invention, a transistor including an oxide semiconductor and having high on-state current can be provided. According to one embodiment of the present invention, a transistor having an oxide semiconductor and low off-state current can be provided. According to one embodiment of the present invention, a transistor having reduced power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. can be provided.

[0021] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other effects from the descriptions in the claims, etc. [Brief description of the drawings]

[0022] [Figure 1] 1A and 1B are diagrams illustrating a top view and a cross section of a semiconductor device. [Diagram 2] 1A and 1B are diagrams illustrating a top view and a cross section of a semiconductor device. [Diagram 3] 1A and 1B are diagrams illustrating a top view and a cross section of a semiconductor device. [Figure 4] 1A and 1B are diagrams illustrating a top view and a cross section of a semiconductor device. [Diagram 5] 1A and 1B are diagrams illustrating a top view and a cross section of a semiconductor device. [Figure 6] 1A and 1B are diagrams illustrating a top view and a cross section of a semiconductor device. [Figure 7] 1A and 1B are cross-sectional views of a semiconductor device. [Figure 8] 1A and 1B are cross-sectional views of a semiconductor device. [Figure 9] 1A and 1B are cross-sectional views of a semiconductor device. [Figure 10] 1A and 1B are cross-sectional views of a semiconductor device. [Figure 11] 1A and 1B are cross-sectional views of a semiconductor device. [Figure 12] FIG. 2 is a diagram for explaining a band structure. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 15]1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 20] 1A and 1B are diagrams illustrating structural analyses of a CAAC-OS and a single crystal oxide semiconductor by XRD, and diagrams showing selected-area electron diffraction patterns of a CAAC-OS. [Figure 21] Cross-sectional TEM image and planar TEM image of CAAC-OS, and their image analysis images. [Figure 22] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Diagram 23] Cross-sectional TEM image of a-like OS. [Figure 24] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Diagram 25] FIG. 1 is a top view illustrating one embodiment of a display device. [Figure 26] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 27] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 28] FIG. 1 illustrates a circuit configuration of a semiconductor device. [Figure 29] 2A and 2B are a diagram for explaining the configuration of a pixel circuit and a timing chart for explaining the operation of the pixel circuit; [Diagram 30] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Diagram 31] FIG. 2 is a diagram illustrating a display module. [Diagram 32] 1A to 1C are diagrams illustrating electronic devices. [Diagram 33] FIG. 13 is a graph showing Id-Vg characteristics of a transistor in an embodiment. [Diagram 34] 1A to 1C are cross-sectional TEM images of a transistor in an embodiment. [Diagram 35]1A and 1B are a top view and a cross-sectional view illustrating a comparative transistor structure in an embodiment. [Diagram 36] 13A to 13C show electrical characteristics of a transistor in an embodiment. [Figure 37] 13A to 13C show electrical characteristics of a transistor in an embodiment. [Figure 38] 13A to 13C show electrical characteristics of a transistor in an embodiment. [Figure 39] 13A to 13C show electrical characteristics of a transistor in an embodiment. [Diagram 40] 13A to 13C show electrical characteristics of a transistor in an embodiment. [Diagram 41] 11A to 11C are diagrams illustrating the Id change rate of a transistor, the Id-Vg characteristics before and after a stress test, and the Id-Vd characteristics before and after a stress test in an embodiment. [Diagram 42] 1A to 1C are cross-sectional TEM images of a transistor in an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, the embodiment and examples will be described with reference to the drawings. The aspects and embodiments can be implemented in many different ways, and are not intended to be limiting of the scope of the invention. It will be readily understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the following description of the embodiments and examples. It is not something that can be done.

[0024] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown in the drawings. The drawings are merely schematic illustrations and are not limited to the shapes or values ​​shown in the drawings.

[0025] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the components of the It should be noted that this is added to avoid confusion and is not intended to limit the numbers.

[0026] In addition, in this specification, the words "above" and "below" indicating the position of the components are used. The positional relationship is used for convenience in describing the drawings. The relationship changes depending on the direction in which each component is depicted. The above words and phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0027] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) A current flows through the drain, the channel region, and the source. In this specification and the like, the channel region refers to a region through which a current mainly flows. The flow area.

[0028] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0029] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0030] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0031] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to:

[0032] In this specification and the like, unless otherwise specified, the off-state current refers to the current that occurs when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also called a cut-off state). Unless otherwise specified, for n-channel transistors, V is the voltage between the gate and source When gs is lower than the threshold voltage Vth, the gate and This refers to a state in which the voltage Vgs between the n-channel transistors is higher than the threshold voltage Vth. The off-state current of a transistor is the voltage between the gate and source, Vgs, that is, the threshold voltage, Vt This may refer to the drain current when it is lower than h.

[0033] The off-state current of a transistor may depend on Vgs. The off-state current is I or less if there exists a Vgs value at which the off-state current of the transistor is I or less. The off-state current of a transistor is the current that flows through it in the off-state at a given Vgs. , an off-state at Vgs within a given range or a sufficiently reduced off-current is obtained. In some cases, it may refer to the off-state current at Vgs.

[0034] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -1 3 A, and the drain current at Vgs of -0.5 V is 1×10 -19 A and Vg The drain current at s = -0.8V is 1×10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: , or 1×10 when Vgs is in the range of -0.5V to -0.8V -19 A or below Therefore, the off-state current of the transistor is 1×10 -19 There are cases where it is said to be A or lower. The drain current of the transistor is 1×10 -22 A or less Vgs exists. Therefore, the off-state current of the transistor is 1×10 -22 It may be said that it is below A.

[0035] In this specification, the off-state current of a transistor having a channel width W is expressed as It is sometimes expressed as the current value that flows per watt. Also, for a given channel width (for example, 1 μm), In the latter case, the unit of the off-state current is current / length. It may be expressed in units with an element (e.g., A / μm).

[0036] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the operating temperature is room temperature, 60°C, 85°C, 95°C, or 125°C. Or, the reliability of a semiconductor device including the transistor may be guaranteed. The temperature at which the transistor is certified, or the temperature at which a semiconductor device or the like that contains the transistor is used (e.g. For example, the off-state current at any one of temperatures from 5° C. to 35° C. The off-state current of the transistor is I or less at room temperature, 60°C, 85°C, 95°C, 125°C, The temperature at which the reliability of a semiconductor device including the transistor is guaranteed, or the temperature at which the transistor is The temperature at which the semiconductor device containing the transistor is used (for example, between 5°C and 35°C) There exists a value of Vgs at which the off-state current of the transistor at a certain temperature is equal to or less than I. It may refer to.

[0037] The off-state current of a transistor may depend on the voltage Vds between the drain and source In this specification, unless otherwise specified, the off-state current is measured when Vds is 0.1 V, 0.8 V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or In some cases, it indicates the off-state current at 20 V. In other cases, it indicates the off-state current at 20 V. Vds that guarantees the reliability of semiconductor devices, or semiconductor devices including the transistor The term may also refer to the off-state current at Vds used in the transistor off-state. The current is less than I when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, transistors included Vds that guarantees the reliability of the semiconductor device, etc., in which the transistor is included, or The off-state current of a transistor at Vds used in semiconductor devices is I or less. This may refer to the existence of a Vgs value.

[0038] In the above description of the off-state current, the drain may be read as the source. The current may also refer to the current through the source when the transistor is in the off state.

[0039] In this specification and the like, the term "leak current" may be used to mean the same thing as the "off current." In this specification, the off-state current refers to, for example, the current flowing when a transistor is in an off state. , may refer to the current flowing between the source and drain.

[0040] (Embodiment 1) In this embodiment mode, a semiconductor device having a transistor and a manufacturing method of the semiconductor device will be described. An example will be described with reference to FIGS.

[0041] <1-1. Configuration example 1 of semiconductor device> 1A, 1B, and 1C show examples of a semiconductor device including a transistor. The transistors shown in 1(A), (B), and (C) have a top-gate structure.

[0042] FIG. 1A is a top view of a transistor 100, and FIG. 1B is a dot-dash diagram of FIG. FIG. 1(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 1(A). In FIG. 1(A), components such as an insulating film 110 are omitted for clarity. In the top view of the transistor, the same structure as that shown in FIG. 1( As in A), some of the components may be omitted. The two directions are called the channel length (L) direction, and the dashed line Y1-Y2 direction is called the channel width (W) direction. This may be the case.

[0043] The transistor 100 shown in FIGS. 1A, 1B, and 1C includes an insulating layer formed on a substrate 102. The insulating film 104, the oxide semiconductor film 108 on the insulating film 104, and the insulating film on the oxide semiconductor film 108 The insulating film 110, the oxide semiconductor film 112 on the insulating film 110, the insulating film 104, the oxide semiconductor film 108 and an insulating film 116 over the oxide semiconductor film 112. The film 108 is a channel region 1 that is overlapped with the oxide semiconductor film 112 and is in contact with the insulating film 110. 08i, a source region 108s in contact with the insulating film 116, and a drain region 108b in contact with the insulating film 116. and region 108d.

[0044] The transistor 100 also includes an insulating film 118 on the insulating film 116 and an insulating film 116 on the insulating film 117. A conductive layer electrically connected to the source region 108s through an opening 141a provided in the semiconductor substrate 108 is The drain region is connected to the insulating film 120a through an opening 141b provided in the insulating films 116 and 118. and a conductive film 120b electrically connected to the region 108d.

[0045] In this specification and the like, the insulating film 104 is referred to as a first insulating film, and the insulating film 116 is referred to as a second insulating film. The insulating film 116 and the insulating film 118 may be referred to as a third insulating film. The oxide semiconductor film 112 functions as a gate electrode. The conductive film 120a also functions as a source electrode. 0b functions as a drain electrode.

[0046] The insulating film 116 contains either nitrogen or hydrogen, or both. By configuring 16 to have either nitrogen or hydrogen or both, an oxide semiconductor Either nitrogen or hydrogen or both are supplied to the oxide semiconductor film 108 and the oxide semiconductor film 112. can be provided.

[0047] The oxide semiconductor film 112 has a function of supplying oxygen to the insulating film 110. The semiconductor film 112 has a function of supplying oxygen to the insulating film 110. By having an excess oxygen region in the insulating film 110, The excess oxygen is supplied to the oxide semiconductor film 108, more specifically, to the channel region 108i. Therefore, a highly reliable semiconductor device can be provided.

[0048] In order to supply excess oxygen to the oxide semiconductor film 108, The insulating film 104 formed below the insulating film 108 may have excess oxygen. In the case where the insulating film 104 contains excess oxygen, the excess oxygen contained in the oxide semiconductor film 10 The source region 108s and the drain region 108d of the semiconductor device 8 may also be supplied with the same. When excess oxygen is provided in the source region 108s and the drain region 108d, s and the resistance in the drain region 108d may become high.

[0049] On the other hand, the insulating film 110 formed above the oxide semiconductor film 108 has excess oxygen. By forming the semiconductor layer 108 in this manner, it is possible to selectively supply excess oxygen only to the channel region 108i. Alternatively, the channel region 108i, the source region 108s, and the drain region 10 After supplying excess oxygen to the source region 108s and the drain region 108d, The carrier density can be selectively increased.

[0050] In addition, the oxide semiconductor film 112 is formed by supplying oxygen to the insulating film 110 and then oxidizing the insulating film 116. By supplying either nitrogen or hydrogen or both from the source, the carrier density becomes higher. In other words, the oxide semiconductor film 112 is an oxide conductor (OC). Therefore, the oxide semiconductor film 112 also functions as an oxide semiconductor. The carrier density is higher than that of the body membrane 108.

[0051] In addition, the source region 108s and the drain region 108d of the oxide semiconductor film 108 The oxide semiconductor film 112 may each contain an element that forms oxygen vacancies. Representative elements that form the oxygen vacancies are hydrogen, boron, carbon, nitrogen, and fluorine. Examples of rare gas elements include nitrogen, phosphorus, sulfur, chlorine, and rare gases. Examples of fluorine include lithium, neon, argon, krypton, and xenon.

[0052] When an impurity element is added to an oxide semiconductor film, a bond between a metal element and oxygen in the oxide semiconductor film is formed. The bond is broken, and oxygen vacancies are formed. Alternatively, an impurity element is added to the oxide semiconductor film. Then, oxygen that has been bonded to a metal element in the oxide semiconductor film is bonded to an impurity element, and the metal element As a result, oxygen is released from the oxide semiconductor film, and oxygen vacancies are formed. The carrier density increases and the conductivity becomes higher.

[0053] In the transistor 100, the side edge of the insulating film 110 and the oxide semiconductor film 112 In other words, in the transistor 100, In this case, the upper end of the insulating film 110 and the lower end of the oxide semiconductor film 112 are substantially aligned with each other. For example, the insulating film 110 can be processed using the oxide semiconductor film 112 as a mask to form the above structure. It is possible.

[0054] Next, the components of the semiconductor device shown in FIGS. 1(A), 1(B), and 1(C) will be described in detail.

[0055] [substrate] Various substrates can be used as the substrate 102 and are not limited to a specific one. Examples of the substrate include a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), a SO I substrate, glass substrate, quartz substrate, plastic substrate, metal substrate, stainless steel substrate , Substrate with Stainless Steel Foil, Tungsten Substrate, Tungsten Foil A substrate having a fibrous material, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film Examples of glass substrates include barium borosilicate glass and aluminophore. silicate glass, or soda lime glass. Flexible substrates, lamination films Examples of the materials and base films are as follows: Polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulf For example, there are plastics such as polyether ether sulphate (PES). Synthetic resins, etc. Examples include polypropylene, polyester, and polyfluorine. Examples of the polyvinyl chloride include polyvinyl chloride and polyvinyl chloride. Examples of the polyamide and polyimide are , aramid, epoxy, inorganic deposition film, paper, etc. In particular, semiconductor substrates, By manufacturing transistors using single crystal substrates or SOI substrates, etc., Small size transformers with low variation in size, shape, and current capability. When a circuit is constructed using such transistors, This makes it possible to reduce the power consumption of the circuit or to increase the degree of circuit integration.

[0056] In addition, a flexible substrate is used as the substrate 102, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the transistor. After a semiconductor device is partially or entirely completed on the substrate, the semiconductor device is separated from the substrate 102 and another In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The transfer can also be performed on a flexible substrate. The above-mentioned release layer may be, for example, a tungsten film and a silicon oxide film. A laminated structure of inorganic films with silicon films, or an organic resin film such as polyimide is formed on the substrate The above-mentioned configurations and the like can be used.

[0057] An example of a substrate on which a transistor is transferred is a substrate on which the above-mentioned transistor is formed. In addition to the substrates that can be used, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, Rubber substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, hemp), synthetic fibers (nylon) , polyurethane, polyester) or regenerated fibers (acetate, cupra, rayon, These substrates include recycled polyester, leather substrates, and rubber substrates. By using this, it is possible to form transistors with good characteristics and low power consumption. It is possible to form, manufacture devices that are less likely to break, are heat resistant, or are lighter or thinner. .

[0058] [First insulating film] The insulating film 104 can be formed by sputtering, CVD, vapor deposition, pulsed laser deposition ( The insulating film 104 can be formed by appropriately using a photolaser laser deposition (PLD) method, a printing method, a coating method, or the like. For example, a single layer or a stacked layer of an oxide insulating film or a nitride insulating film can be formed. Note that in order to improve the interface characteristics with the oxide semiconductor film 108, In this case, at least a region in contact with the oxide semiconductor film 108 is preferably formed using an oxide insulating film. It is preferable to use an oxide insulating film that releases oxygen by heating as the insulating film 104. Then, oxygen contained in the insulating film 104 is transferred to the oxide semiconductor film 108 by heat treatment. It is possible.

[0059] The thickness of the insulating film 104 is 50 nm or more, or 100 nm or more and 3000 nm or less, or The thickness of the insulating film 104 can be set to 200 nm or more and 1000 nm or less. This can increase the amount of oxygen released from the insulating film 104 and also can prevent the insulating film 104 and the oxide semiconductor from The interface state at the interface with the conductive film 108 and the channel region 1 of the oxide semiconductor film 108 It is possible to reduce the oxygen vacancies contained in 08i.

[0060] The insulating film 104 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitrogen. Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The insulating film may be a single layer or a stacked layer. The layer structure of the silicon nitride film and the silicon oxynitride film is used as the layer 104. The insulating film 104 has a laminated structure, with a silicon nitride film on the lower layer and an oxynitride film on the upper layer. By using a silicon film, oxygen can be efficiently introduced into the oxide semiconductor film 108. Cut.

[0061] [Oxide semiconductor film] One or both of the oxide semiconductor films 108 and 112 may be In- It is formed of metal oxides such as M-Zn oxide (M is Al, Ga, Y, or Sn). The oxide semiconductor film 108 and the oxide semiconductor film 112 may be formed of In-Ga oxide or In-Z In particular, the oxide semiconductor film 108 and the oxide semiconductor film 112 may be made of an n-type oxide. It is preferable that the metal oxide is made of the same constituent elements, since the manufacturing cost can be reduced. stomach.

[0062] Note that when the oxide semiconductor film 108 and the oxide semiconductor film 112 are an In-M-Zn oxide, The atomic ratio of In to M is 2 when the sum of In and M is 100 atomic %. 5 atomic% or higher, M is less than 75 atomic%, or In is 34 atomic% or higher c% or higher and M is less than 66 atomic%.

[0063] The oxide semiconductor film 108 and the oxide semiconductor film 112 each have an energy gap of 2 eV or more. , or 2.5 eV or more, or 3 eV or more.

[0064] The thickness of the oxide semiconductor film 108 is 3 nm to 200 nm, preferably 3 nm to 100 nm. The thickness of the oxide semiconductor film is preferably 00 nm or less, and more preferably 3 nm or more and 60 nm or less. The thickness of 112 is 5 nm or more and 500 nm or less, preferably 10 nm or more and 300 nm or less. More preferably, it is 20 nm or more and 100 nm or less.

[0065] When the oxide semiconductor film 108 and the oxide semiconductor film 112 are In-M-Zn oxides, I Atoms of metal elements in sputtering target used to deposit nM-Zn oxide film The numerical ratio preferably satisfies In≧M and Zn≧M. The atomic ratio of the metal elements in the ZnO solution is In:M:Zn=1:1:1, In:M:Zn=1: 1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In :M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4. In the oxide semiconductor film 108 to be formed, the composition ratio of In to M is preferably 5:1:7. and the oxide semiconductor film 112 have the atomic ratios of The atomic ratio of the metal elements contained may vary by about plus or minus 40%. For example, The atomic ratio of In:Ga:Zn=4:2:4.1 was used as the sputtering target. In this case, the atomic ratio of the oxide semiconductor film 108 and the oxide semiconductor film 112 to be formed is I In some cases, the n:Ga:Zn ratio is approximately 4:2:3.

[0066] In addition, the oxide semiconductor film 108 contains silicon or carbon, which is one of the Group 14 elements. When the oxide semiconductor film 108 is filled with oxygen, oxygen vacancies are increased and the oxide semiconductor film 108 may become an n-type film. In particular, in the channel region 108i, the concentration of silicon or carbon (secondary ion mass distribution) The concentration obtained by the analytical method is 2 x 10 18 atoms / cm 3 or less, or 2×10 1 7 atoms / cm 3 As a result, the transistor has a threshold voltage of It has electrical characteristics in which the applied voltage is positive (also called normally-off characteristics).

[0067] In addition, in the channel region 108i, an alkali metal ion is obtained by secondary ion mass spectrometry. The concentration of metal or alkaline earth metal is 1×10 18 atoms / cm 3 Less than or equal to 2 ×10 16 atoms / cm 3 It can be: Alkali metals and alkaline earths When a metal combines with an oxide semiconductor, carriers may be generated, causing the transistor to turn off. For this reason, the current may increase. It is preferable to reduce the concentration of alkaline earth metals. The device has electrical characteristics in which the lowest voltage is positive (also called normally-off characteristics).

[0068] In addition, when nitrogen is contained in the channel region 108i, electrons that act as carriers are generated, and The carrier density increases and the semiconductor becomes n-type. As a result, the oxide semiconductor containing nitrogen A transistor using a thin film is likely to have normally-on characteristics. In the 08i, it is preferable that nitrogen is reduced as much as possible. For example, secondary ions The nitrogen concentration obtained by mass spectrometry was 5×10 18 atoms / cm 3Let's say the following: stomach.

[0069] In addition, by reducing the impurity elements in the channel region 108i, Therefore, in the channel region 108i, the carrier density can be reduced. Carrier density is 1×10 17 pieces / cm 3 or less, or 1×10 15 pieces / cm 3 The following also is 1×10 13 pieces / cm 3 or less, or 1×10 11 pieces / cm 3 It can be .

[0070] The channel region 108i is an oxide semiconductor film having a low impurity concentration and a low density of defect states. By using such a material, a transistor having better electrical characteristics can be manufactured. Here, a high-purity pure silicon has a low impurity concentration and a low defect level density (few oxygen vacancies). Alternatively, they are called pure or substantially pure. A highly intrinsic or substantially highly purified intrinsic oxide semiconductor has a small carrier generation source; Therefore, the carrier density can be reduced in the oxide semiconductor film. The transistor in which the junction region is formed has electrical characteristics in which the threshold voltage is positive (normal Also known as off-state characteristics.) Also, high purity intrinsic or substantially high purity intrinsic Since the oxide semiconductor film has a low density of defect states, the oxide semiconductor film may also have a low density of trap states. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a significantly low off-state current. Therefore, a channel region is formed in the oxide semiconductor film. Such a transistor may have small fluctuations in electrical characteristics and become a highly reliable transistor. do.

[0071] On the other hand, the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are The source region 108s, the drain region 108d, and the oxide semiconductor The film 112 comes into contact with the insulating film 116, so that the source region 108s, the drain region 108s, and the One or both of hydrogen and nitrogen are added to the oxide semiconductor region 108d and the oxide semiconductor film 112. The carrier density increases due to the addition.

[0072] In addition, one or both of the oxide semiconductor film 108 and the oxide semiconductor film 112 may be The non-single crystal structure may be, for example, CAAC-OS (CAx is Aligned Crystalline Oxide Semiconductor or), polycrystalline structure, microcrystalline structure (described later), or amorphous structure. In the amorphous structure, the defect density is the highest, and the CAAC-OS structure has the lowest defect density. .

[0073] Note that the oxide semiconductor film 108 may have an amorphous structure, a microcrystalline structure, or a polycrystalline structure. a monolayer film having two or more of a CAAC-OS region, a CAAC-OS region, and a single crystal structure region, or Alternatively, the oxide semiconductor film 112 may have an amorphous structure. The regions are microcrystalline, polycrystalline, CAAC-OS, and single crystal. The film may be a single layer film having two or more of the above-mentioned regions, or may have a laminated structure of such films.

[0074] In the oxide semiconductor film 108, the channel region 108i and the source region 108s The crystallinity of the oxide semiconductor film 108c may be different from that of the drain region 108d. In the case of 108, the source region 108s and the drain region 108 are closer to each other than the channel region 108i. The source region 108s and the drain region 108d may have a lower crystallinity. When an impurity element is added to the source region 108s and the drain region 108d, This is because damage occurs and the crystallinity decreases.

[0075] [Insulating film functioning as a gate insulating film] The insulating film 110 is formed by forming a single layer or a stack of an oxide insulating film or a nitride insulating film. Note that in order to improve the interface characteristics with the oxide semiconductor film 108, At least a region in contact with the oxide semiconductor film 108 is formed using an oxide insulating film. The insulating film 110 is preferably made of, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. Silicon, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide or Ga The insulating layer 11 may be formed of a single layer or a multilayer structure, such as a -Zn oxide.

[0076] In addition, the insulating film 110 is provided with a blocking effect against oxygen, hydrogen, water, etc. By this, oxygen can be diffused from the oxide semiconductor film 108 to the outside, and oxygen can be absorbed from the oxide semiconductor film 108 to the outside. It is possible to prevent hydrogen, water, etc. from entering the film 108. Examples of insulating films having such a function include an aluminum oxide film, an aluminum oxynitride film, and a gallium oxide film. GaN film, gallium oxide nitride film, yttrium oxide film, yttrium oxide nitride film, hafnium oxide Examples of the oxide film include hafnium oxide nitride film.

[0077] The insulating film 110 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate (HfAl x O y N z ), high-k materials such as hafnium oxide and yttrium oxide The use of this material can reduce gate leakage of transistors.

[0078] In addition, by using an oxide insulating film that releases oxygen by heating as the insulating film 110, Oxygen contained in the insulating film 110 is transferred to the oxide semiconductor film 108 by heat treatment. is possible.

[0079] The thickness of the insulating film 110 is 5 nm or more and 400 nm or less, or 5 nm or more and 300 nm or less. , or may be 10 nm or more and 250 nm or less.

[0080] [Second insulating film] The insulating film 116 contains either nitrogen or hydrogen, or both. Examples of the nitride insulating film include silicon nitride, It can be formed using silicon nitride oxide, aluminum nitride, aluminum nitride oxide, etc. The hydrogen concentration in the insulating film 116 is 1×10 22 atoms / cm 3 That's all. The insulating film 116 is preferably formed on the source region 108s of the oxide semiconductor film 108 and The insulating film 116 is in contact with the oxide semiconductor film 112 and the drain region 108d. Therefore, the source region 108s, the drain region 108d, and The hydrogen concentration in the source region 108s and the oxide semiconductor film 112 increases. The carrier density of the source semiconductor film 08d and the oxide semiconductor film 112 can be increased. The region 108s, the drain region 108d, and the oxide semiconductor film 112 are each made of an insulating material. By contacting the insulating film 116, there may be regions in the film where the hydrogen concentration is the same.

[0081] [Third insulating film] The insulating film 118 is formed as a single layer or a stack of an oxide insulating film or a nitride insulating film. The insulating film 118 can be made of, for example, silicon oxide, silicon oxynitride, or silicon nitride. Silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide or G It is sufficient to use a-Zn oxide or the like, and the film can be provided as a single layer or a multilayer.

[0082] The insulating film 118 functions as a barrier film against hydrogen, water, and the like from the outside. It is preferable that

[0083] The thickness of the insulating film 118 is 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less. m or less.

[0084] [Conductive film] The conductive films 120a and 120b can be formed by sputtering, vacuum deposition, pulse laser, etc. The conductive film 120a can be formed by using a deposition (PLD) method, a thermal CVD method, or the like. , 120b may be, for example, aluminum, chromium, copper, tantalum, titanium, molybdenum, A metal element selected from the group consisting of tungsten, nickel, iron, cobalt, and tungsten, or the above-mentioned metals. The alloy is made of an element or a combination of the above-mentioned metal elements. In addition, the metal element selected from one or more of manganese and zirconium can be used. The conductive films 120a and 120b may have a single-layer structure or a laminate structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a single layer structure of a manganese film containing A single-layer structure of copper film, a two-layer structure of titanium film laminated on aluminum film, a titanium nitride film laminated on titanium film Two-layer structure with a titanium film laminated on top, a two-layer structure with a tungsten film laminated on top of a titanium nitride film, A two-layer structure in which a tungsten film is laminated on a tantalum film or a tungsten nitride film, and manganese a two-layer structure in which a copper film is laminated on a copper film containing titanium; A titanium film is then formed on the aluminum film, which is then stacked on the titanium film. Layer structure: A copper film is laminated on a copper film containing manganese, and a copper film containing manganese is formed on top of that. There are also three-layer structures made up of aluminum, titanium, tantalum, tungsten, molybdenum, etc. A combination of one or more of the following: rhodium, chromium, neodymium, and scandium A gold film or a nitride film may also be used.

[0085] The conductive films 120a and 120b are made of indium tin oxide (InTinO xide:ITO), indium oxide containing tungsten oxide, Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium zinc oxide, indium tin oxide with silicon (In-Sn Alternatively, a conductive material having a light-transmitting property such as silicon oxide (ITSO) may be used. In addition, a laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element may be used. do.

[0086] The thickness of the conductive films 120a and 120b is 30 nm or more and 500 nm or less, or 10 The thickness can be 0 nm or more and 400 nm or less.

[0087] <1-2. Configuration example 2 of semiconductor device> Next, regarding the semiconductor device having a different structure from that shown in FIG. 1(A)(B)(C), Explain using B)(C).

[0088] 2A is a top view of a transistor 150, and FIG. 2B is a dot-dash diagram of FIG. 2A. 2(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 2(A). FIG.

[0089] The transistor 150 shown in FIGS. 2A, 2B, and 2C includes an insulating layer formed on a substrate 102. The insulating film 104, the oxide semiconductor film 108 on the insulating film 104, and the insulating film on the oxide semiconductor film 108 A film 110, an oxide semiconductor film 112 on the insulating film 110, and a conductive film on the oxide semiconductor film 112 The insulating film 114, the insulating film 104, the oxide semiconductor film 108, and the insulating film 116 over the conductive film 114 The oxide semiconductor film 108 overlaps with the oxide semiconductor film 112 and has an insulating layer. A channel region 108i contacting the insulating film 110 and a source region 108s contacting the insulating film 116 and a drain region 108d in contact with the insulating film 116.

[0090] The transistor 150 also includes an insulating film 118 on the insulating film 116 and an insulating film 116 on the insulating film 117. A conductive layer electrically connected to the source region 108s through an opening 141a provided in the semiconductor substrate 108 is The drain region is connected to the insulating film 120a through an opening 141b provided in the insulating films 116 and 118. and a conductive film 120b electrically connected to the region 108d.

[0091] Note that in the transistor 150, the oxide semiconductor film 112 and the conductive film 114 are The conductive film 114 serves as a gate electrode. The conductive film 114 has a function of making the oxide semiconductor film 112 n-type. In this way, the oxide semiconductor film 112 functions as part of a gate electrode.

[0092] The insulating film 116 contains either nitrogen or hydrogen, or both. 16 has either nitrogen or hydrogen or both, Nitrogen or hydrogen is supplied to the drain region 108s and the drain region 108d. It is possible.

[0093] The oxide semiconductor film 112 has a function of supplying oxygen to the insulating film 110. The semiconductor film 112 has a function of supplying oxygen to the insulating film 110. By having an excess oxygen region in the insulating film 110, The excess oxygen can be supplied to the channel region 108i. A semiconductor device can be provided.

[0094] Note that after oxygen is supplied to the insulating film 110, the carrier density of the oxide semiconductor film 112 is In addition, the oxide semiconductor film 112 is in contact with the conductive film 114, The constituent element of 14 might diffuse into the oxide semiconductor film 112, increasing the carrier density. In other words, the oxide semiconductor film 112 also functions as an oxide conductor (OC). Therefore, the oxide semiconductor film 112 can be formed as a part of the gate electrode without increasing the manufacturing process. It is possible to function as a

[0095] The conductive film 114 is formed by the same method as the conductive films 120a and 120b described above. In particular, the conductive film 114 is formed using a material similar to that of the conductive film 112. It is preferable to form the conductive film 114 using titanium by a sputtering method. By using tungsten, copper, or tungsten, the oxide semiconductor film 11 in contact with the conductive film 114 can be The conductivity of the conductive film 114 can be improved. The laminated structure may be, for example, a structure having a copper film on a copper film containing manganese, or a structure having a tungsten film on a copper film containing manganese. For this purpose, a structure having an aluminum film on a stainless steel film may be used.

[0096] <1-3. Configuration example 3 of semiconductor device> Next, regarding the semiconductor device having a different structure from that shown in FIG. 1(A)(B)(C), Explain using B)(C).

[0097] FIG. 3A is a top view of a transistor 100A, and FIG. 3B is a cross-sectional view of a portion of FIG. 3A. 3(C) is a cross-sectional view taken along dashed line X1-X2, and FIG. 3(C) is a cross-sectional view taken along dashed line Y1-Y2 in FIG. 3(A). FIG.

[0098] The transistor 100A shown in FIGS. 3A, 3B, and 3C includes a conductive layer formed on a substrate 102. A conductive film 106, an insulating film 104 on the conductive film 106, and an oxide semiconductor film 10 on the insulating film 104. 8, an insulating film 110 on the oxide semiconductor film 108, and an oxide semiconductor film 11 on the insulating film 110. 2, and the insulating film 11 on the insulating film 104, the oxide semiconductor film 108, and the oxide semiconductor film 112. The oxide semiconductor film 108 has a channel region 1 in contact with the insulating film 110. 08i, a source region 108s in contact with the insulating film 116, and a drain region 108b in contact with the insulating film 116. and region 108d.

[0099] The transistor 100A has the same structure as the transistor 100 described above, and further includes a conductive film 106 and , and an opening 143.

[0100] The opening 143 is provided in the insulating films 104 and 110. The conductive film 106 is The conductive film is electrically connected to the oxide semiconductor film 112 through the opening 143. The same potential is applied to the oxide semiconductor film 106 and the oxide semiconductor film 112. Alternatively, different potentials may be applied to the conductive film 106 and the oxide semiconductor film 112.

[0101] Note that the conductive film 106 functions as a first gate electrode (also referred to as a bottom gate electrode). The oxide semiconductor film 112 serves as a second gate electrode (also referred to as a top gate electrode). The insulating film 104 also functions as a first gate insulating film. The insulating film 110 functions as a second gate insulating film.

[0102] In this way, the transistor 100A shown in FIGS. Unlike the transistor 100, the oxide semiconductor film 108 has conductive layers functioning as gate electrodes above and below it. As shown in the transistor 100A, the present invention has a structure including a conductive film and an oxide semiconductor film. The semiconductor device according to one embodiment of the present invention may be provided with two or more gate electrodes.

[0103] As shown in FIG. 3C, the oxide semiconductor film 108 functions as a first gate electrode. The conductive film 106 functioning as a second gate electrode and the oxide semiconductor film 112 functioning as a second gate electrode are A conductive film and an oxide semiconductor, which function as two gate electrodes, are disposed opposite to each other. is sandwiched between the membrane.

[0104] The length of the oxide semiconductor film 112 in the channel width direction is The length of the oxide semiconductor film 108 in the channel width direction is longer than the length of the insulating film 1 The oxide semiconductor film 112 is covered with the conductive layer 10. The insulating film 104 and the insulating film 110 are connected to each other through an opening 143 provided in the insulating film 104 and the insulating film 110. Therefore, one of the side surfaces of the oxide semiconductor film 108 in the channel width direction is It is opposite to 2.

[0105] In other words, in the channel width direction of the transistor 100A, the conductive film 106 and the oxide film The semiconductor film 112 is formed in an opening 143 provided in the insulating film 104 and the insulating film 110. The insulating film 104 and the insulating film 110 are disposed between the oxide semiconductor film 108 and the insulating film 110. This is a configuration that includes:

[0106] With such a structure, the oxide semiconductor film 10 included in the transistor 100A 8 is a conductive film 106 functioning as a first gate electrode and a conductive film 108 functioning as a second gate electrode. The oxide semiconductor film 112 can be electrically surrounded by the electric field of the oxide semiconductor film 112. As shown in FIG. 00A, the electric field of the first gate electrode and the second gate electrode causes the channel region The device structure of the transistor electrically surrounding the oxide semiconductor film 108 on which the This can be called a surrounded channel (S-channel) structure.

[0107] Since the transistor 100A has an S-channel structure, the conductive film 106 or The oxide semiconductor film 112 effectively applies an electric field for inducing a channel to the oxide semiconductor. This allows the current drive capability of the transistor 100A to be improved. It is possible to obtain high on-current characteristics. It is also possible to increase the on-current. Therefore, the transistor 100A can be miniaturized. 8 has a structure surrounded by the conductive film 106 and the oxide semiconductor film 112. In this way, the mechanical strength of the oxide semiconductor film 108 can be increased.

[0108] Note that an opening in the oxide semiconductor film 108 in the channel width direction of the transistor 100A An opening different from opening 143 may be formed on the side surface on which portion 143 is not formed.

[0109] As shown in the transistor 100A, a transistor is formed with a semiconductor film sandwiched therebetween. In the case of a pair of gate electrodes, one of which is connected to a signal A and the other is connected to a signal B. A fixed potential Vb may be applied to the gate electrodes. A signal A may be applied to one gate electrode and a signal B may be applied to the other gate electrode. A signal B may be applied to one of the gate electrodes. A fixed potential V a, and the other gate electrode may be given a fixed potential Vb.

[0110] The signal A is, for example, a signal for controlling the conductive state or the non-conductive state. It is a digital signal that can take two types of potential: potential V1 or potential V2 (V1>V2). For example, the potential V1 may be a high power supply potential and the potential V2 may be a low power supply potential. Signal A may be an analog signal.

[0111] The fixed potential Vb is, for example, a potential for controlling the threshold voltage VthA of a transistor. The fixed potential Vb may be the potential V1 or the potential V2. The fixed potential Vb is The fixed potential Vb may be different from the potential V1 or the potential V2. As a result, the gate-source voltage Vg Reducing the drain current when s is 0V, and reducing the leakage current of circuits that have transistors For example, the fixed potential Vb may be lower than the low power supply potential. By increasing Vb, it may be possible to lower the threshold voltage VthA. Improve the drain current when the to-source voltage Vgs is VDD, and have a transistor For example, if the fixed potential Vb is set higher than the low power supply potential, the operating speed of the circuit can be improved. It may be possible to do so.

[0112] The signal B is, for example, a signal for controlling the conductive state or the non-conductive state. It is a digital signal that can take two types of potential: potential V1, potential V2, or potential V3 (V3>V4). For example, the potential V3 may be a high power supply potential and the potential V4 may be a low power supply potential. Signal B may be an analog signal.

[0113] If signal A and signal B are both digital signals, signal B will have the same digital value as signal A. In this case, the on-current of the transistor is improved, and the transistor In this case, the operation speed of the circuit having the potential V1 and The potential V2 may be different from the potentials V3 and V4 in the signal B. For example, The gate insulating film corresponding to the gate to which signal B is input is the gate insulating film corresponding to the gate to which signal A is input. If the gate insulating film is thicker than the gate insulating film, the potential amplitude of signal B (V3-V4) is It may be set to be larger than (V1-V2). This will allow the transistor to be in a conducting state or The effect of signal A on the non-conducting state is set to the same degree as the effect of signal B on the non-conducting state. It may be possible to do this.

[0114] If signal A and signal B are both digital signals, signal B has a different digital value than signal A. In this case, the transistors are controlled by signals A and B separately. For example, a transistor can be In the case of the channel type, when signal A is at potential V1 and signal B is at potential V3, When only the signal A is in a conductive state, or when the signal B is at a potential V4, If only one transistor is non-conducting, a single transistor can function as a NAND circuit or a NOR circuit. In addition, the signal B is a signal for controlling the threshold voltage VthA. For example, the signal B may be a period during which a circuit having a transistor is in operation. The signal B may be a signal having a different potential during a period when the circuit is not operating. In this case, signal B may be a signal with a different potential depending on the operation mode of the circuit. In some cases, the potential may not switch as frequently as

[0115] When signal A and signal B are both analog signals, signal B is an analog signal with the same potential as signal A. analog signal obtained by multiplying the potential of signal A by a constant, or adding a constant to the potential of signal A Alternatively, it may be an analog signal obtained by subtracting the signal. In this case, the on-current of the transistor is The signal B may be increased in response to the signal P, thereby increasing the operating speed of a circuit having a transistor. A may be a different analog signal. In this case, the transistor control is signal A and signal B can be performed separately, which may result in higher functionality.

[0116] Signal A may be a digital signal and signal B may be an analog signal. Or, signal A may be It is also possible that signal A is an analog signal and signal B is a digital signal.

[0117] When a fixed potential is applied to both gate electrodes of a transistor, the transistor is For example, a transistor can function as an n-channel transistor. In the case of a transistor type, the fixed potential Va or the fixed potential Vb can be increased (or decreased). In some cases, the effective resistance of the resistor can be lowered (higher). By making both Vb high (low), a transistor with only one gate In some cases, a lower (higher) effective resistance may be obtained.

[0118] The other configurations of the transistor 100A are the same as those of the transistor 100 shown above. Yes, and it has the same effect.

[0119] In addition, in the transistor 150 shown above, similar to the transistor 100A, A film 106 and an opening 143 may be provided. In that case, an example is shown in FIG. FIG. 4A is a top view of a transistor 150A, and FIG. 4B is a top view of the transistor 150A shown in FIG. 4(C) is a cross-sectional view taken along dashed line X1-X2, and FIG. 4(C) is a cross-sectional view taken along dashed line Y1-Y2 in FIG. 4(A). FIG.

[0120] In this manner, in the transistor of one embodiment of the present invention, the transistor described above They can be used in appropriate combination.

[0121] <1-4. Configuration example 4 of semiconductor device> Next, regarding the semiconductor device having a different structure from that shown in FIG. 1(A)(B)(C), Explain using B)(C).

[0122] FIG. 5A is a top view of a transistor 100B, and FIG. 5B is a cross-sectional view of a portion of FIG. 5A. 5(C) is a cross-sectional view taken along dashed line X1-X2, and FIG. 5(C) is a cross-sectional view taken along dashed line Y1-Y2 in FIG. 5(A). FIG.

[0123] The transistor 100B shown in FIGS. 5A, 5B, and 5C is the same as the transistor 100 shown above. The shape of the oxide semiconductor film 112 in the transistor 100A is different from that in the transistor 100B. The bottom end of the oxide semiconductor film 112 is formed inside the top end of the insulating film 110. Then, the side edge of the insulating film 110 is positioned outside the side edge of the oxide semiconductor film 112. .

[0124] For example, the oxide semiconductor film 112 and the insulating film 110 are processed using the same mask. The conductive film 112 is etched by a wet etching method, and the insulating film 110 is etched by a dry etching method. By processing the above, the above structure can be obtained.

[0125] In addition, when the oxide semiconductor film 112 has the above structure, Region 108f may be formed. Region 108f may include channel region 108i and source The region 108s and the channel region 108i and the drain region 108d are formed. can be.

[0126] The region 108f functions as either a high resistance region or a low resistance region. The resistance region is an oxide film that has a resistance equivalent to that of the channel region 108i and functions as a gate electrode. When the region 108f is a high resistance region, the region 10 Region 8f functions as a so-called offset region. Region 108f functions as an offset region. In this case, in order to suppress a decrease in the on-current of the transistor 100B, In the direction of the length (L), the region 108f may be set to 1 μm or less.

[0127] The low resistance region is a region having a lower resistance than the channel region 108i and a The region 108f is a low resistance region. In this case, the region 108f is a so-called LDD (Lightly Doped Drain) region. When the region 108f functions as an LDD region, the drain This allows the electric field in the drain region to be relaxed, which reduces the threshold voltage of the transistor caused by the electric field in the drain region. This can reduce fluctuations in the value voltage.

[0128] In addition, when the region 108f is to be a low resistance region, for example, Hydrogen or nitrogen or both are supplied to the insulating film 110 and The oxide semiconductor film 112 is used as a mask to inject an impurity element from above the oxide semiconductor film 112. By the addition, the impurity is added to the oxide semiconductor film 108 through the insulating film 110. This forms region 108f.

[0129] The transistor 150 described above also has an oxide semiconductor functioning as a second gate electrode. By changing the shape of the film 112, it is possible to obtain a structure similar to that of the transistor 100B. An example of this case is shown in Figures 6(A), 6(B), and 6(C). 6(B) is a cross-sectional view taken along dashed line X1-X2 in FIG. 6(A). 6(C) is a cross-sectional view taken along dashed line Y1-Y2 in FIG. 6(A).

[0130] <1-5. Modification 1 of the semiconductor device> Next, regarding the modified example of the semiconductor device shown in FIG. 3(A), (B), and (C), FIG. 7(A) and FIG. This will be explained using:

[0131] 7A and 7B are cross-sectional views of the transistor 100C. The top view is the same as that of the transistor 100B shown in FIG. FIG. 7(A) is a cross-sectional view taken along dashed line X1-X2 in FIG. 5(A). FIG. 7B is a cross-sectional view taken along dashed line Y1-Y2 in FIG.

[0132] The transistor 100C has a structure that functions as a planarizing insulating film for the transistor 100B shown above. The difference is that an insulating film 122 is provided. It has the same configuration as the transistor 100B and exerts the same effects.

[0133] The insulating film 122 has a function of planarizing unevenness due to transistors and the like. The film 122 may be made of any insulating material, and may be made of an inorganic or organic material. The inorganic material may be a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a nitride Examples of the organic material include a silicon film, an aluminum oxide film, and an aluminum nitride film. Examples of the material include photosensitive resin materials such as acrylic resin and polyimide resin. .

[0134] In addition, in FIG. 7(A) and (B), the size of the opening in the insulating film 122 is However, the shape is not limited to this. For example, the opening 14 The shape may be the same as that of the openings 141a and 141b, or may be larger than the openings 141a and 141b. good.

[0135] In addition, in FIG. 7(A) and (B), conductive films 120a and 120b are provided on an insulating film 122. However, the present invention is not limited to this. For example, a conductive film 120 on an insulating film 118 Alternatively, a configuration may be adopted in which the conductive films 120a and 120b are provided, and an insulating film 122 is provided on the conductive films 120a and 120b. good.

[0136] <1-6. Modification 2 of the semiconductor device> Next, regarding the modified example of the semiconductor device shown in FIG. 1(A), (B), and (C), FIG. 8 and FIG. 9 are used. I will explain this in more detail.

[0137] 8A and 8B are cross-sectional views of the transistor 100D. The top view is the same as that of the transistor 100 shown in FIG. FIG. 8(A) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 8(B) is a cross-sectional view taken along dashed line Y1-Y2 in FIG. 1(A).

[0138] The transistor 100D is different from the transistor 100 shown above in that the shape of the insulating film 110 is different. The rest of the configuration is the same as that of the transistor 100 shown above. It has an effect.

[0139] The insulating film 110 included in the transistor 100D is located inside the oxide semiconductor film 112. In other words, the side surface of the insulating film 110 is located on the inner side than the bottom end of the oxide semiconductor film 112. For example, after the oxide semiconductor film 112 is processed, an insulating film is formed by using an etchant or the like. By side-etching the insulating film 110, the structure shown in FIG. 8(A) and (B) can be obtained. Note that when the insulating film 110 has the above structure, A hollow region 147 is formed.

[0140] The hollow region 147 contains air and functions as a part of the gate insulating film. The dielectric constant of 147 is approximately 1, the same as that of air. Therefore, the transistor 100D By using this structure, a voltage is applied to the oxide semiconductor film 112 which functions as a gate electrode. In this case, the voltage applied to the oxide semiconductor film 108 below the hollow region 147 is 0, which is lower than the voltage applied to the oxide semiconductor film 108 (channel region 108i). Therefore, the oxide semiconductor film 108 below the hollow region 147 is effectively overlapped. The Lov region is formed in the oxide semiconductor film 108. By providing the insulating layer, it is possible to reduce the electric field concentrated at the source end and the drain end. The Lov region is a region that overlaps with the oxide semiconductor film 112 functioning as a gate electrode and is a region that This region has a lower resistance than the hole region 108i.

[0141] 9A and 9B are cross-sectional views of the transistor 100E. The top view is the same as that of the transistor 100 shown in FIG. FIG. 9A is a cross-sectional view taken along the dashed line X1-X2 in FIG. 9(B) is a cross-sectional view taken along dashed line Y1-Y2 in FIG. 1(A).

[0142] The transistor 100E is a transistor including the transistor 100 and the insulating film 110 and the insulating film 11 The shape of the transistor 6 is different. Other than that, the structure is the same as that of the transistor 100 shown above. It is composed of the same components and has the same effect.

[0143] The insulating film 110 in the transistor 100E is located inside the oxide semiconductor film 112. In other words, the side surface of the insulating film 110 is located on the inner side than the bottom end of the oxide semiconductor film 112. For example, after the oxide semiconductor film 112 is processed, an insulating film is formed by using an etchant or the like. By side-etching the insulating film 110, the configuration shown in FIG. 9(A) and (B) can be obtained. In addition, after the insulating film 110 is formed into the above structure, the insulating film 116 is formed. The insulating film 116 also extends under the oxide semiconductor film 112. The film 112 is in contact with the oxide semiconductor film 108 located below the film 112 .

[0144] With the above-mentioned configuration, the source region 108s and the drain region 108d are made of oxide semiconductor. The transistor 100E is located inside the lower end of the conductive film 112. Has an area.

[0145] A structure having a Lov region such as transistor 100D and transistor 100E. By this, the channel region 108i, the source region 108s, and the drain region 108d are Since no high resistance region is formed between the do.

[0146] <1-7. Modification of semiconductor device 3> Next, regarding the modified examples of the semiconductor device shown in FIGS. 3(A), 3(B), and 3(C), FIGS. 10 to 12 will be described. This will be explained using:

[0147] 10A and 10B are cross-sectional views of the transistor 100F. 3A. The top view of the transistor 100A is the same as that of the transistor 100A shown in FIG. 10A is a cross-sectional view taken along the dashed line X1-X2 in FIG. FIG. 10B is a cross-sectional view taken along dashed line Y1-Y2 in FIG.

[0148] The transistor 100F has a structure including the above-described transistor 100B and an oxide semiconductor film 108. The other configurations are the same as those of the transistor 100B shown above. Yes, and it has the same effect.

[0149] The oxide semiconductor film 108 included in the transistor 100F is an oxide semiconductor film over the insulating film 116. an oxide semiconductor film 108_1, an oxide semiconductor film 108_2 on the oxide semiconductor film 108_1, and an oxide and an oxide semiconductor film 108_3 over the semiconductor film 108_2.

[0150] The channel region 108i, the source region 108s, and the drain region 108d are The oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 1 It has a three-layer laminated structure of 08_3.

[0151] 11A and 11B are cross-sectional views of the transistor 100G. 3A. The top view of the transistor 100A is the same as that of the transistor 100A shown in FIG. 11A is a cross-sectional view taken along the dashed line X1-X2 in FIG. FIG. 11B is a cross-sectional view taken along dashed line Y1-Y2 in FIG.

[0152] The transistor 100G has a structure including the above-described transistor 100A and an oxide semiconductor film 108. The other components are the same as the transistor 100A shown above. Yes, and it has the same effect.

[0153] The oxide semiconductor film 108 included in the transistor 100G is an oxide semiconductor film over the insulating film 116. and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. do.

[0154] The channel region 108i, the source region 108s, and the drain region 108d are Each of the oxide semiconductor films 108_1 and 108_2 has a stacked structure of two layers, an oxide semiconductor film 108_3, be.

[0155] <1-8.Band structure> Here, the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film The band structure of the insulating film 110, the insulating film 104, and the oxide semiconductor films 108_2 and 108_ The band structure of the insulating film 110 will be described with reference to FIG.

[0156] FIG. 12A shows the insulating film 104 and the oxide semiconductor films 108_1, 108_2, and 108_3. 1 and an insulating film 110. 2(B) shows the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and the insulating film 110. This is an example of a band structure in the thickness direction of a laminated structure having a structure having a band structure in the thickness direction. For ease of understanding, the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and The energy level (Ec) at the bottom of the conduction band of the insulating film 110 is shown.

[0157] FIG. 12A shows a case where a silicon oxide film is used as the insulating films 104 and 110, and an oxide semiconductor film is used as the insulating films 104 and 110. The conductor film 108_1 is a metal oxide film having an atomic ratio of metal elements of In:Ga:Zn=1:3:2. An oxide semiconductor film formed using an oxide semiconductor target was used as the oxide semiconductor film 108_2. A metal oxide target with an atomic ratio of metal elements of In:Ga:Zn=4:2:4.1 was used. The oxide semiconductor film 108_3 is formed by using an oxide semiconductor film formed by The oxide formed using a metal oxide target with a numerical ratio of In:Ga:Zn=1:3:2 FIG. 1 is a band diagram of a structure using a semiconductor film.

[0158] FIG. 12B shows a case where a silicon oxide film is used as the insulating films 104 and 110, and an oxide semiconductor film is used as the insulating films 104 and 110. The conductor film 108_2 is a metal film having an atomic ratio of metal elements of In:Ga:Zn=4:2:4.1. The oxide semiconductor film 108_3 is formed by using an oxide semiconductor film formed by using an oxide target. A metal oxide target with an atomic ratio of metal elements of In:Ga:Zn=1:3:2 was used. FIG. 13 is a band diagram of a structure using an oxide semiconductor film formed in accordance with the present invention.

[0159] As shown in FIG. 12A, in the oxide semiconductor films 108_1, 108_2, and 108_3, In addition, as shown in FIG. 12(B), the energy level at the bottom of the conduction band changes gradually. As shown in FIG. 1, the energy levels of the conduction band minimums of the oxide semiconductor films 108_2 and 108_3 are In other words, it can be said that the change is continuous or that the connection is continuous. In order to have such a band structure, the oxide semiconductor film 108_1 and the oxide semiconductor or between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. At the interface, impurities that form defect levels such as trap centers and recombination centers exist. Assume it does not exist.

[0160] In order to form a continuous junction in the oxide semiconductor films 108_1, 108_2, and 108_3, A multi-chamber deposition system (sputtering system) equipped with a load lock chamber was used. It is necessary to laminate each film in succession without exposing them to the atmosphere.

[0161] By using the structure shown in FIG. 12A and FIG. 12B, the oxide semiconductor film 108_2 is a well. In the transistor having the above stacked structure, the channel region is an oxide semiconductor film It can be seen that it is formed at 108_2.

[0162] Note that by providing the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor film 1 Therefore, a trap state that may be formed in the oxide semiconductor film 108_2 can be kept away from the oxide semiconductor film 108_2. Cut.

[0163] In addition, the trap states are in the conduction band of the oxide semiconductor film 108_2 functioning as a channel region. The energy level at the bottom (Ec) can be farther from the vacuum level, and the charge is transferred to the trap level. When electrons accumulate in the trap level, negative electrons are trapped. This results in a constant charge, and the threshold voltage of the transistor shifts in the positive direction. The trap level is higher than the energy level (Ec) of the conduction band minimum of the oxide semiconductor film 108_2. It is preferable to use a structure in which the trap level is as close to the vacuum level as possible. This makes it difficult for electrons to accumulate at the gate potential, which makes it possible to increase the on-state current of the transistor. Together, the field effect mobility can be increased.

[0164] In addition, the oxide semiconductor films 108_1 and 108_3 are more conductive than the oxide semiconductor film 108_2. The energy level of the conduction band minimum is close to the vacuum level. The energy levels of the conduction band minimum and the conduction band minimum of the oxide semiconductor films 108_1 and 108_3 are The difference between the energy levels is 0.15 eV or more, or 0.5 eV or more and 2 eV or less. That is, the electron affinity of the oxide semiconductor films 108_1 and 108_3 is The difference between the electron affinity of the oxide semiconductor film 108_2 and the electron affinity of the oxide semiconductor film 108_2 is 0.15 eV or more, or 0. The electron transport energy is 5 eV or more and 2 eV or less, or 1 eV or less.

[0165] With such a structure, the oxide semiconductor film 108_2 serves as a main current path. That is, the oxide semiconductor film 108_2 functions as a channel region. The films 108_1 and 108_3 function as oxide insulating films. The films 108_1 and 108_3 constitute the oxide semiconductor film 108_2 in which a channel region is to be formed. It is preferable to use an oxide semiconductor film formed of one or more metal elements that form the oxide semiconductor layer. By adopting such a structure, the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2, Alternatively, the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3 may be diffused at the interface between them. Therefore, the movement of carriers is not hindered at the interface, and therefore, The field effect mobility of the transistor is increased.

[0166] The oxide semiconductor films 108_1 and 108_3 function as part of a channel region. To prevent this, materials with sufficiently low electrical conductivity are used. The conductive films 108_1 and 108_3 are each made of oxide insulating material based on their physical properties and / or functions. Alternatively, the oxide semiconductor films 108_1 and 108_3 may be formed of a material having a high electron affinity (vacuum the energy level of the oxide semiconductor film 108_2 is smaller than that of the oxide semiconductor film 108_2, The energy level of the conduction band minimum is the same as that of the oxide semiconductor film 108_2. A material with a band offset is used. In order to suppress the occurrence of a difference in threshold voltage depending on the thickness of the oxide semiconductor film 108, The energy levels of the conduction band minimums of the oxide semiconductor films 108_1 and 108_3 are lower than the conduction band minimum of the oxide semiconductor film 108_2. It is preferable to use a material that is closer to the vacuum level than the lower energy level. For example, an oxide The energy level of the conduction band minimum of the semiconductor film 108_2 and the oxide semiconductor films 108_1 and 10 The difference between the energy level of the conduction band minimum of 8_3 is 0.2 eV or more, preferably 0.5 eV. It is preferable that the amount is equal to or more than that.

[0167] In addition, the oxide semiconductor films 108_1 and 108_3 each have a spinel crystal structure. It is preferable that the oxide semiconductor films 108_1 and 108_3 do not include a spinel type crystal. When the spinel type crystal structure is included, the conductive film 120 is In some cases, the constituent elements of the oxide semiconductor film 108_2 may diffuse into the oxide semiconductor film 108_2. When the oxide semiconductor films 108_1 and 108_3 are CAAC-OS, the conductive film 120a , 120b, for example, the blocking property of copper element is increased, which is preferable.

[0168] In this embodiment, the oxide semiconductor films 108_1 and 108_3 are made of a metal The atomic ratio of elements was In:Ga:Zn=1:3:2. However, the present invention is not limited to this structure. The compound semiconductor films 108_1 and 108_3 are made of In:Ga:Zn=1:1:1 [atomic ratio] ], In:Ga:Zn=1:1:1.2[atomic ratio], In:Ga:Zn=1:3:4[ or a metal oxide target with In:Ga:Zn=1:3:6 [atomic ratio] Alternatively, an oxide semiconductor film formed using the above may be used.

[0169] Note that the oxide semiconductor films 108_1 and 108_3 are made of In:Ga:Zn=1:1:1 When a metal oxide target having an atomic ratio of 108 is used, the oxide semiconductor films 108_1 and 108 _3 is the case where In:Ga:Zn=1:β1(0<β1≦2):β2(0<β2≦2) In addition, the oxide semiconductor films 108_1 and 108_3 may be formed of In:Ga:Zn=1. When a metal oxide target having an atomic ratio of 3:4 is used, the oxide semiconductor film 108_1 , 108_3 is In:Ga:Zn=1:β3(1≦β3≦5):β4(2≦β4≦6) In addition, the oxide semiconductor films 108_1 and 108_3 may be formed of In:Ga: When a metal oxide target with an atomic ratio of Zn=1:3:6 is used, the oxide semiconductor film 1 08_1 and 108_3 are In:Ga:Zn=1:β5(1≦β5≦5):β6(4≦β 6≦8).

[0170] <1-9. Manufacturing method of semiconductor device 1> Next, an example of a method for manufacturing the transistor 100 shown in FIG. 1 will be described with reference to FIGS. 13 to 15 are used to explain a method for manufacturing the transistor 100. 1 is a cross-sectional view in the channel length (L) direction and the channel width (W) direction.

[0171] First, an insulating film 104 is formed on a substrate 102, and an oxide semiconductor film is formed on the insulating film 104. After that, the oxide semiconductor film is processed into an island shape to form the oxide semiconductor film 107. (See FIG. 13(A)).

[0172] The insulating film 104 can be formed by sputtering, CVD, vapor deposition, pulsed laser deposition ( The film can be formed by appropriately using a PLD method, a printing method, a coating method, or the like. In this case, a silicon nitride film having a thickness of 400 nm was deposited as the insulating film 104 using a PECVD apparatus. Then, a silicon oxynitride film having a thickness of 50 nm is formed.

[0173] After the insulating film 104 is formed, oxygen may be added to the insulating film 104. The oxygen added to 4 can be oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions. The doping method includes ion doping, ion implantation, plasma treatment, etc. In addition, a film that suppresses oxygen desorption is formed on the insulating film, and then the insulating film is formed through the film. The film 104 may be doped with oxygen.

[0174] The above-mentioned oxygen desorption-suppressing film may be made of indium, zinc, gallium, tin, aluminum, or the like. Aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, tungsten A metal element selected from the above, an alloy containing the above metal element, or a combination of the above metal elements. an alloy having the above-mentioned metal element, a metal nitride having the above-mentioned metal element, a metal oxide having the above-mentioned metal element, The insulating layer 11 is formed by using a conductive material such as a metal nitride oxide having the above-mentioned metal element. This can be done.

[0175] In addition, when oxygen is added in plasma treatment, the oxygen is excited by microwaves to produce high-density oxygen. By generating atomic plasma, the amount of oxygen added to the insulating film 104 can be increased. .

[0176] The oxide semiconductor film 107 can be formed by a sputtering method, a coating method, a pulsed laser deposition method, or a method using a deposition method such as a deposition method. It can be formed by a laser ablation method, a thermal CVD method, etc. To process the conductive film 107, a mask is formed on the oxide semiconductor film by a lithography process. Then, part of the oxide semiconductor film is etched using the mask. Alternatively, the island-shaped oxide semiconductor film 107 may be directly formed by a printing method.

[0177] When an oxide semiconductor film is formed by a sputtering method, a power source for generating plasma The device may be an RF power supply device, an AC power supply device, a DC power supply device, or the like. In the case of forming an oxide semiconductor film, a sputtering gas is a rare gas (typically, argon). ), oxygen, rare gas, and mixed gas of oxygen are used as appropriate. Note that the mixed gas of rare gas and oxygen In this case, it is preferable to increase the gas ratio of oxygen to the rare gas.

[0178] Note that when the oxide semiconductor film is formed by, for example, a sputtering method, Temperature: 150℃ to 750℃, 150℃ to 450℃, or 200℃ By forming the oxide semiconductor film at a temperature of 350° C. or less, the crystallinity can be improved. Therefore, it is preferable.

[0179] Note that in this embodiment, the oxide semiconductor film 107 is formed by a sputtering apparatus. The sputtering target was In-Ga-Zn metal oxide (In:Ga:Zn =1:1:1.2 [atomic ratio]) to form a 40-nm-thick oxide semiconductor film.

[0180] After the oxide semiconductor film 107 is formed, heat treatment is performed. The temperature of the heat treatment is typically 150° C. or higher. Less than the strain point, or 250°C to 450°C, or 300°C to 450°C .

[0181] Heat treatment is carried out using rare gases such as helium, neon, argon, xenon, krypton, or It can be carried out in an inert gas atmosphere containing nitrogen. Alternatively, it can be heated in an inert gas atmosphere. After that, heating may be performed in an oxygen atmosphere. Note that hydrogen, water, etc. may be added to the inert atmosphere and oxygen atmosphere. It is preferable that the treatment time does not include the above-mentioned. The treatment time may be from 3 minutes to 24 hours.

[0182] The heat treatment can be performed using an electric furnace, an RTA device, or the like. Therefore, heat treatment can be performed at a temperature above the distortion point of the substrate for a short period of time. The processing time can be reduced.

[0183] The oxide semiconductor film is formed while being heated, or the oxide semiconductor film is formed and then subjected to heat treatment. By performing the process, the hydrogen concentration in the oxide semiconductor film obtained by secondary ion mass spectrometry can be Degrees 5×10 19 atoms / cm 3 or less, or 1×10 19 atoms / cm 3 below , 5×1018 atoms / cm 3 or less, or 1×10 18 atoms / cm 3 below, or 5×10 17 atoms / cm 3 or less, or 1×10 16 atoms / cm 3 Below It can be below.

[0184] Next, the insulating film 110_0 is formed over the insulating film 104 and the oxide semiconductor film 107 (FIG. 1 3(B)).

[0185] The insulating film 110_0 is a silicon oxide film or a silicon oxynitride film formed by PECVD. In this case, the source gas is a deposition gas containing silicon. It is preferable to use a gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silicon include Examples of oxidizing gases include silane, disilane, trisilane, and fluorinated silane. Examples of oxidizing gases include oxygen. , ozone, nitrous oxide, nitrogen dioxide, etc.

[0186] In addition, for the insulating film 110_0, the flow rate of the oxidizing gas is set to 20 times the flow rate of the deposition gas. The pressure in the treatment chamber should be 100P or more but less than 100 times, or 40 times or more but less than 80 times. By using the PECVD method with a pressure of less than a or 50 Pa or less, the amount of defects is reduced. A silicon hydride film can be formed.

[0187] In addition, the insulating film 110_0 is placed in a vacuum-evacuated processing chamber of a PECVD apparatus. The substrate is maintained at a temperature of 280° C. or higher and 400° C. or lower, and a source gas is introduced into the processing chamber. The pressure in the chamber is set to 20 Pa or more and 250 Pa or less, and more preferably 100 Pa or more and 250 Pa or less. By supplying high-frequency power to the electrodes in the treatment chamber, the dense oxide A silicon film or a silicon oxynitride film can be formed.

[0188] The insulating film 110_0 may be formed by using a PECVD method using microwaves. Microwaves refer to the frequency range from 300MHz to 300GHz. The temperature is low and the electron energy is small. In addition, a microwave PECVD device is used. Then, the amount of power used to generate plasma, i.e., to ionize molecules, is The proportion of power used to accelerate electrons is high, and the proportion of power used to accelerate electrons is low. This allows the plasma (high density plasma) to be excited. The insulating film 110_0 can be formed with less plasma damage and fewer defects.

[0189] In addition, the insulating film 110_0 can be formed by a CVD method using an organic silane gas. As an organic silane gas, ethyl silicate (TEOS: chemical formula Si(OC2H5)4 ), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetramethylsilane (TMS: chemical formula Si(CH3)4), Lasiloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), Silicon-containing compounds such as trisdimethylaminosilane (SiH(N(CH3)2)3) By using the CVD method using organic silane gas, it is possible to obtain a high coating property. An insulating film 110_0 can be formed.

[0190] In this embodiment, a PECVD apparatus is used to deposit a 100 nm thick insulating film 110_0. A silicon oxynitride film is formed.

[0191] Next, an oxide semiconductor film 112_0 is formed over the insulating film 110_0. During the formation of the oxide semiconductor film 112_0, Oxygen is added (see FIG. 13(C)).

[0192] The oxide semiconductor film 112_0 is formed by a sputtering method. It is preferable to form the oxide semiconductor in an atmosphere containing oxygen gas during the formation. By forming the insulating film 112_0, oxygen can be suitably added to the insulating film 110_0. Cut.

[0193] In FIG. 13C, oxygen added to the insulating film 110_0 is indicated by arrows. In addition, as the oxide semiconductor film 112_0, the oxide semiconductor film 10 Materials similar to those in 7 can be used.

[0194] In this embodiment, the oxide semiconductor film 112_0 is formed by a sputtering apparatus. As a sputtering target, In-Ga-Zn metal oxide (In:Ga:Zn = A 100-nm-thick oxide semiconductor film is formed using a 4:2:4.1 (atomic ratio) mixture.

[0195] Next, a mask 1 is formed at a desired position on the oxide semiconductor film 112_0 by a lithography process. 40 is formed (see FIG. 13(D)).

[0196] Next, etching is performed from above the mask 140 to remove the oxide semiconductor film 112_0 and the After processing the insulating film 110_0, the mask 140 is removed to form an island-shaped oxide semiconductor. A conductor film 112 and an island-shaped insulating film 110 are formed (see FIG. 14(A)).

[0197] In this embodiment, the oxide semiconductor film 112_0 and the insulating film 110_0 are processed. This is done by using a dry etching method.

[0198] When the oxide semiconductor film 112 and the insulating film 110 are processed, In some cases, the thickness of the oxide semiconductor film 107 in a region where the oxide semiconductor film 107 does not overlap with the oxide semiconductor film 107 may be thin. When the semiconductor film 112 and the insulating film 110 are processed, the oxide semiconductor film 107 does not overlap with the semiconductor film 112. In some cases, the thickness of the insulating film 104 in the region may become thin.

[0199] Next, impurities were removed from above the insulating film 104, the oxide semiconductor film 107, and the oxide semiconductor film 112. Then, the material element 145 is added (see FIG. 14(B)).

[0200] The impurity element 145 can be added by ion doping, ion implantation, plasma In the case of plasma treatment, the plasma is heated in a gas atmosphere containing the impurity element to be added. Impurity elements can be added by generating a plasma and performing a plasma treatment. The plasma generating device may be a dry etching device, an ashing device, A PECVD apparatus, a high density PECVD apparatus, or the like can be used.

[0201] The source gas for the impurity element 145 is B2H6, PH3, CH4, N2, NH3 , AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2 and rare gases (e.g. Argon) or B2H6 diluted with rare gases, PH 3. Use one or more of N2, NH3, AlH3, AlCl3, F2, HF, and H2 B2H6, PH3, N2, NH3, AlH3, AlCl3 diluted with rare gases can be produced. The impurity element 145 is added to the oxide semiconductor film 107 and the oxide semiconductor film 108 using one or more of F 2 , HF, and H 2 . By adding an element such as a rare gas, hydrogen, boron, carbon, nitrogen, fluorine, or the like to the oxide semiconductor film 112, One or more of phosphorus, sulfur, and chlorine is added to the oxide semiconductor film 107 and the oxide semiconductor film 112. It is possible.

[0202] Or, the impurity element 145 is added as a source gas, and then B2H6, PH3 , CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, and H2 are added to the oxide semiconductor film 107 and the oxide semiconductor film 112 as a source gas. may be added.

[0203] Or, the impurity element 145 is B2H6, PH3, CH4, N2, NH3, AlH3, Add one or more of AlCl3, SiH4, Si2H6, F2, HF, and H2 as source gas. After the addition, a rare gas is added as a source gas to the oxide semiconductor films 107 and 112. may be added.

[0204] The addition of the impurity element 145 is controlled by appropriately setting implantation conditions such as acceleration voltage and dose amount. For example, when argon is added by ion implantation, the acceleration voltage is set to 10 kV or more. 00kV or less, dose amount is 1×10 13 ions / cm 2 More than 1×10 16 ions / c m 2 For example, 1×10 14 ions / cm 2 Also, When phosphorus ions are added by the on-implantation method, the acceleration voltage is 30 kV and the dose is 1×1013 ions / cm 2 5×10 or more 16 ions / cm 2 For example, 1×1 0 15 ions / cm 2 This can be done as follows.

[0205] In this embodiment, the mask 140 is removed, and then the impurity element 145 is added. However, the present invention is not limited to this. For example, the mask 140 may be left in place. The impurity element 145 may be added in this state.

[0206] In this embodiment, the impurity element 145 is doped using a doping device. Argon is added to the oxide semiconductor film 107 and the oxide semiconductor film 112. In the embodiment, a configuration in which the impurity element 145 is added is illustrated, but the present invention is not limited to this. For example, the step of adding the impurity element 145 may not be performed.

[0207] Next, the insulating film 1 is formed over the insulating film 104, the oxide semiconductor film 107, and the oxide semiconductor film 112. Note that by forming the insulating film 116, the oxide semiconductor in contact with the insulating film 116 is The conductive film 107 becomes a source region 108s and a drain region 108d. The oxide semiconductor film 107 that is not in contact with the insulating film 110 107 becomes a channel region 108i. As a result, the channel region 108i and the source region The oxide semiconductor film 108 having the drain region 108s and the drain region 108d is formed (FIG. 1 (See 4(C)).

[0208] The insulating film 116 can be formed by selecting the above-mentioned material. In this example, a PECVD apparatus was used to deposit silicon nitride having a thickness of 100 nm as the insulating film 116. A film is formed.

[0209] By using a silicon nitride film as the insulating film 116, the oxide semiconductor layer in contact with the insulating film 116 The conductive film 112, the source region 108s, and the drain region 108d are provided with water in the silicon nitride film. The oxide semiconductor film 112, the source region 108s, and the drain region 108d The carrier density can be increased.

[0210] Next, the insulating film 118 is formed over the insulating film 116 (see FIG. 14(D)).

[0211] The insulating film 118 can be formed by selecting the above-mentioned material. In this example, a PECVD apparatus is used to deposit a silicon oxynitride film having a thickness of 300 nm as the insulating film 118. Form a cone film.

[0212] Next, a mask is formed at a desired position of the insulating film 118 by a lithography process, and then the insulating film By etching a part of the insulating film 118 and the insulating film 116, the source region 108s is reached. An opening 141a reaching the drain region 108d and an opening 141b reaching the drain region 108d are formed (see FIG. 15(A)).

[0213] The method for etching the insulating film 118 and the insulating film 116 is a wet etching method. and / or dry etching can be appropriately used. The insulating film 118 and the insulating film 116 are processed by dry etching.

[0214] Next, a conductive film 120 is formed on the insulating film 118 so as to cover the openings 141a and 141b. (See FIG. 15(B)).

[0215] For the conductive film 120, a material that can be used for the conductive films 120a and 120b is selected. In this embodiment, the conductive film 120 is formed by a sputtering device. The titanium film with a thickness of 50 nm, the aluminum film with a thickness of 400 nm, and the aluminum film with a thickness of 100 A laminate film of a titanium film having a thickness of nm is formed.

[0216] Next, a mask is formed at a desired position on the conductive film 120 by a lithography process, and then, A part of the conductive film 120 is etched to form conductive films 120a and 120b (FIG. 15(C)).

[0217] The conductive film 120 may be processed by wet etching and / or dry etching. In this embodiment, a dry etching method is used to remove the conductive film. 120 is processed to form conductive films 120a and 120b.

[0218] Through the above steps, the transistor 100 illustrated in FIG. 1 can be manufactured.

[0219] Note that the films constituting the transistor 100 (the insulating film, the oxide semiconductor film, the conductive film, and the like) are Sputtering, Chemical Vapor Deposition (CVD), Vacuum Evaporation, Pulsed Laser Deposition (PLD) ) method, ALD (atomic layer deposition) method, or coating method or printing method. The film can be formed by a sputtering method, a plasma chemical vapor deposition method, etc. The most typical method is the plasma-enhanced chemical vapor deposition (PECVD) method, but the thermal CVD method may also be used. One example is the OCVD (metal organic chemical vapor deposition) method.

[0220] In the thermal CVD method, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the source gas and the oxidizing agent are simultaneously The reaction is carried out in the chamber near or on the substrate, where it is deposited on the substrate to form a film. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0221] In addition, in the ALD method, the pressure inside the chamber is set at atmospheric pressure or reduced pressure, and the source gas for the reaction is The film is formed by repeatedly introducing the gas into the chamber and reacting it. A reactive gas (such as argon or nitrogen) may be introduced as a carrier gas. For example, two types of At least one type of source gas may be supplied to the chamber in sequence. In order to avoid this, after the reaction of the first raw material gas, an inert gas is introduced, and then the second raw material gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is discharged by evacuation. After that, the second source gas may be introduced. The first source gas is adsorbed and reacted with the surface of the substrate. The first layer is formed, and the second source gas introduced later is adsorbed and reacted with the first layer. The order of gas introduction is controlled to obtain a thin film of the desired thickness. By repeating the process several times up to 1000 nm, a thin film with excellent step coverage can be formed. The thickness can be adjusted by repeating the gas introduction, allowing precise adjustment of the film thickness. This makes it suitable for fabricating miniaturized FETs.

[0222] Thermal CVD methods such as MOCVD can be used to form the above-mentioned conductive films, insulating films, oxide semiconductor films, etc. For example, when forming an In-Ga-Zn-O film, the trimer In(CH3)3, trimethylgallium (Ga(CH3)3), and Dimethyl zinc (Zn(CH3)2) is used. Triethylgallium (Ga(C2H5)3) can be used instead of triethylgallium. Diethylzinc (Zn(C2H5)2) can also be used instead of dimethylzinc.

[0223] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and liquids containing hafnium precursors (hafnium alkoxides and tetrakisdimethylamide Hafnium (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamine) C) Hafnium amide (e.g. hafnium) is vaporized as a raw material gas, and ozone is used as an oxidizer. Two types of gases are used:

[0224] For example, when forming an aluminum oxide film using an ALD deposition system, A liquid containing a catalyst and an aluminum precursor (trimethylaluminum (TMA, Al(CH3) 3) and other) are used as the raw material gas and as the oxidizing agent, H2O. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate) There are some.

[0225] For example, when forming a silicon oxide film using a deposition system that uses ALD, Chlorodisilane is adsorbed on the surface to be coated, and the radicals of oxidizing gases (O2, nitrous oxide) are The adsorbate is reacted with the adsorbate.

[0226] For example, when forming a tungsten film using an ALD deposition system, WF6 The initial tungsten film is formed by sequentially introducing B2H6 gas and WF6 gas. The tungsten film is formed using H2 gas. Note that SiH4 gas is used instead of B2H6 gas. A suction cup may also be used.

[0227] For example, an oxide semiconductor film, such as In-Ga-Zn- When forming an O film, an In-O layer is formed using In(CH3)3 gas and O3 gas. Then, a Ga-O layer is formed using Ga(CH3)3 gas and O3 gas, and then The Zn-O layer is formed using Zn(CH3)2 gas and O3 gas. The order is not limited to this example. In addition, In-Ga-O layers and In-Zn- It is also possible to form a mixed compound layer such as an O layer or a Ga-Zn-O layer. H2O gas obtained by bubbling water with an inert gas such as Ar may be used. It is preferable to use O3 gas, which does not cause oxidation.

[0228] <1-10. Manufacturing method of semiconductor device 2> Next, an example of a method for manufacturing the transistor 100C shown in FIG. 7 will be described with reference to FIGS. 16 to 19 illustrate a method for manufacturing the transistor 100C. 1 is a cross-sectional view in the channel length (L) direction and the channel width (W) direction.

[0229] First, the conductive film 106 is formed on the substrate 102. Next, the substrate 102 and the conductive film 106 are An insulating film 104 is formed over the insulating film 104, and an oxide semiconductor film is formed over the insulating film 104. The oxide semiconductor film is processed into an island shape to form an oxide semiconductor film 107 (FIG. 16(A) )reference).

[0230] The conductive film 106 may be formed using a material similar to the oxide semiconductor film 112 or the conductive films 120a and 120b. In this embodiment, the conductive film can be formed by using the same material and method. As the film 106, a tungsten film having a thickness of 100 nm is formed by sputtering.

[0231] Next, the insulating film 110_0 is formed over the insulating film 104 and the oxide semiconductor film 107 (FIG. 1 6(B)).

[0232] Next, a mask is formed by lithography at a desired position on the insulating film 110_0, The insulating film 110_0 and the insulating film 104 are partly etched to reach the conductive film 106. An opening 143 is formed (see FIG. 16(C)).

[0233] The opening 143 can be formed by wet etching and / or dry etching. In this embodiment, a dry etching method is used. An opening 143 is formed.

[0234] Next, an oxide semiconductor film 112_0 is formed on the insulating film 110_0 so as to cover the opening 143. Note that when the oxide semiconductor film 112_0 is formed, 0, oxygen is added to the insulating film 110_0 (see FIG. 16D).

[0235] In FIG. 16D, oxygen added to the insulating film 110_0 is indicated by arrows. In addition, the oxide semiconductor film 112_0 is formed so as to cover the opening 143. As a result, the conductive film 106 and the oxide semiconductor film 112_0 are electrically connected to each other.

[0236] Next, a mask 1 is formed at a desired position on the oxide semiconductor film 112_0 by a lithography process. 40 is formed (see FIG. 17(A)).

[0237] Next, the oxide semiconductor film 112_0 is processed by etching from above the mask 140. Then, an island-shaped oxide semiconductor film 112 is formed (see FIG. 17B).

[0238] In this embodiment, the oxide semiconductor film 112_0 is formed by wet etching. To process.

[0239] Subsequently, the insulating film 110_0 is processed by etching from above the mask 140, and the island Then, a tubular insulating film 110 is formed (see FIG. 17(C)).

[0240] In this embodiment, the insulating film 110_0 is processed by using a dry etching method.

[0241] Next, the mask 140 is removed, and then the insulating film 104, the oxide semiconductor film 107, and the oxide An impurity element 145 is added from above the semiconductor film 112 (see FIG. 17D).

[0242] Note that when the impurity element 145 is added, the oxide semiconductor film 107 is doped with the impurity element 145 in a region where the surface of the oxide semiconductor film 107 is exposed. There are many impurities in the regions (which will later become the source region 108s and the drain region 108d). On the other hand, the oxide semiconductor film 107 does not overlap with the oxide semiconductor film 112, In addition, the insulating film 110 is not applied to the region overlapping the insulating film 110 (the region that will become the region 108f later). Since the impurity element 145 is added through the source region 108s and the drain region 10 The amount of the impurity element 145 added is smaller than that of 8d.

[0243] In this embodiment, the impurity element 145 is doped using a doping device. Argon is added to the oxide semiconductor film 107 and the oxide semiconductor film 112.

[0244] In this embodiment, argon is added as the impurity element 145. However, the present invention is not limited to this. For example, the step of adding the impurity element 145 may be omitted. If the step of adding the impurity element 145 is not performed, the region 108f is a channel region. The impurity concentration is the same as that of the hole region 108i.

[0245] Next, the insulating film 104, the oxide semiconductor film 107, the insulating film 110, and the oxide semiconductor film 11 An insulating film 116 is formed on the insulating film 116. The oxide semiconductor film 107 in contact with the source region 108s and the drain region 108d. In addition, the oxide semiconductor film 107 that is not in contact with the insulating film 116, in other words, the oxide semiconductor film 107 that is in contact with the insulating film 110 The oxide semiconductor film 107 becomes a channel region 108i. i, a source region 108s, and a drain region 108d are formed in the oxide semiconductor film 108. (See FIG. 18(A)).

[0246] In addition, between the channel region 108i and the source region 108s, and between the channel region 108 A region 108f is formed between the drain region 108d and the drain region 108i.

[0247] Next, the insulating film 118 is formed over the insulating film 116 (see FIG. 18B).

[0248] Next, a mask is formed at a desired position of the insulating film 118 by a lithography process, and then the insulating film By etching a part of the insulating film 118 and the insulating film 116, the source region 108s is reached. An opening 141a reaching the drain region 108d and an opening 141b reaching the drain region 108d are formed (see FIG. 18(C)).

[0249] Next, the insulating film 122 is formed over the insulating film 118 (see FIG. 18D).

[0250] Note that the insulating film 122 functions as a planarization insulating film. An opening is provided at a position overlapping the opening 141a and the opening 141b.

[0251] In this embodiment, the insulating film 122 is formed by coating a photosensitive adhesive using a spin coater. An opening is formed by applying an acrylic resin and then exposing the desired area of ​​the acrylic resin to light. An insulating film 122 having a portion is formed.

[0252] Next, a conductive film 120 is formed on the insulating film 122 so as to cover the openings 141a and 141b. (See FIG. 19(A)).

[0253] Next, a mask is formed at a desired position on the conductive film 120 by a lithography process, and then, A part of the conductive film 120 is etched to form conductive films 120a and 120b (FIG. 19(B)).

[0254] In this embodiment, the conductive film 120 is processed by dry etching. When the conductive film 120 is processed, a part of the upper portion of the insulating film 122 may be removed.

[0255] Through the above steps, the transistor 100C shown in FIG. 7 can be manufactured.

[0256] Note that in the manufacturing process of the transistor 100C, the insulating film 104, the oxide semiconductor film 107, insulating film 110_0, oxide semiconductor film 112_0, impurity element 145, insulating film 11 6. The insulating film 118, the openings 141a and 141b, and the conductive film 120 are as follows: <1-9. The present invention can be formed by incorporating the contents described in Manufacturing method of semiconductor device 1.

[0257] In this embodiment, an example in which a transistor includes an oxide semiconductor film is shown. However, one embodiment of the present invention is not limited thereto. As an example, the channel region of a transistor may not have a nitride semiconductor film. In the vicinity of the gate region, the source region, or the drain region, rumanium), SiGe (silicon germanium), GaAs (gallium arsenide), etc. The insulating layer 11 may be formed of a material having such a structure.

[0258] The configuration and method described in this embodiment may be different from the configuration and method described in other embodiments or examples. The method can be used in combination with the above method.

[0259] (Embodiment 2) In this embodiment, the structure of an oxide semiconductor will be described with reference to FIGS. He explains.

[0260] <2-1. Structure of oxide semiconductor> Oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned d crystalline oxide semiconductor), polycrystalline oxide Nanocrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconducting ductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- like oxide semiconductor) and amorphous oxide semiconductor. be.

[0261] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductors, and nc-OS.

[0262] Amorphous structures are generally isotropic and have no inhomogeneous structure, and are characterized by the arrangement of atoms in a metastable state. The positions are not fixed, the bond angles are flexible, and there is short-range order but no long-range order. It is said that there is no such thing.

[0263] From the other perspective, a stable oxide semiconductor can be considered as completely amorphous. In addition, the oxide semiconductor is not isotropic (for example, a small area). An oxide semiconductor having a periodic structure in the above structure cannot be called a completely amorphous oxide semiconductor. On the other hand, a-like OS is not isotropic but has voids (also called voids) and is unstable. In terms of instability, a-like OS is physically an amorphous oxide. It is close to a semiconductor.

[0264] <2-2.CAAC-OS> First, let me explain about CAAC-OS.

[0265] CAAC-OS is an oxide that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0266] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystals was analyzed by the out-of-plane method. As shown in FIG. 20(A), a peak appears at a diffraction angle (2θ) of about 31°. The peak is attributed to the (009) plane of the InGaZnO4 crystal, so In this case, the crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be confirmed that the direction is perpendicular to the surface of the crystal, or perpendicular to the surface of the crystal. In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The nearby peak is due to a crystal structure classified into the space group Fd-3m. It is preferred that the C-OS does not exhibit such a peak.

[0267] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS in a direction parallel to the surface on which the X-ray is to be formed. When structural analysis was performed using the ane method, a peak appeared at 2θ of approximately 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. And, 2θ is fixed at around 56°. Then, the sample is rotated around the normal vector of the sample surface as an axis (φ axis) while analyzing (φ scan). Even if this is done, no clear peak appears as shown in FIG. 20(B). On the other hand, single crystal InGa When 2θ is fixed at around 56° and φ is scanned for ZnO4, the results shown in Figure 20(C) As shown in the figure, six peaks attributable to crystal planes equivalent to the (110) plane are observed. XRD structural analysis revealed that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0268] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the process was parallel to the CAAC-OS surface. When an electron beam with a probe diameter of 300 nm is incident, a diffraction pattern ( This is also called a selected area electron diffraction pattern.) may appear. This diffraction pattern includes I The spots are due to the (009) plane of the nGaZnO4 crystal. Diffraction also confirmed that the pellets contained in the CAAC-OS have a c-axis orientation and that the c-axis is the unformed On the other hand, for the same sample, the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly to the ) is shown. From FIG. 20(E), a ring-shaped diffraction pattern is confirmed. Electron diffraction using an electron beam with a diameter of 300 nm also revealed that the PEG-1000 nanometers in the CAAC-OS It can be seen that the a-axis and b-axis of the slits have no orientation. The first ring is due to the (010) and (100) planes of the InGaZnO4 crystal. The second ring in Fig. 20(E) is thought to be due to the (110) plane. It is thought that.

[0269] In addition, a transmission electron microscope (TEM) Combined analysis of bright-field images and diffraction patterns of CAAC-OS using a microscope. When observing the image (also called a high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain boundaries), are not clearly visible. (also called underly.) may not be clearly identified. It can be said that C-OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0270] Figure 21(A) shows a high-resolution cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image is shown. A spherical aberration correction (SCA) was used for high-resolution TEM imaging. The spherical aberration corrector function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. Therefore, it can be observed.

[0271] From FIG. 21(A), a pellet, which is an area where metal atoms are arranged in layers, can be confirmed. The size of each pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). CAAC-OS can also be used as a C-Axis Aligned Navigator (CANC). The pellets can also be called oxide semiconductors with no crystals. The C-OS film reflects the unevenness of the surface on which it is formed or the top surface, and the CAAC-OS film Or parallel to the top surface.

[0272] 21(B) and 21(C) show CAA images observed from a direction approximately perpendicular to the sample surface. Cs-corrected high-resolution TEM images of the C-OS surface. 21(B) and 21(C), respectively. First, the method of processing is explained. Then, the FFT image is obtained by Fourier Transform (FFT) processing. In the acquired FFT image, the origin is used as the reference point, and the -1 From 5.0 nm -1 The range between Next, the masked FFT image is transformed by inverse fast Fourier transform (IFFT : Inverse Fast Fourier Transform) processing is used to The image obtained in this way is called an FFT filtered image. The filtered image is an image in which periodic components are extracted from a Cs-corrected high-resolution TEM image. This indicates a child array.

[0273] In FIG. 21(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area indicated by the dashed line is the connection between the pellets. The broken line shows the hexagonal shape, so we can see that the pellet is hexagonal. The shape of the let is not limited to a regular hexagon, and is often a non-regular hexagon.

[0274] In FIG. 21(E), a dot is drawn between an area with a uniform lattice arrangement and an area with a different uniform lattice arrangement. The grain boundaries are shown by dotted lines. Even in the vicinity of the dotted lines, no clear crystal grain boundaries can be confirmed. By connecting the neighboring lattice points with the center, a distorted hexagon can be formed. It can be seen that the formation of grain boundaries is suppressed by distorting the rows. C-OS has a non-closely packed atomic arrangement in the ab-plane direction and metal elements are substituted. This is because the bond distance between atoms changes, allowing distortion to be tolerated. It is possible.

[0275] As described above, the CAAC-OS has a c-axis orientation and is Multiple pellets (nanocrystals) are connected to form a distorted crystal structure. AAC-OS, CAA crystal(c-axis-aligned abp It can also be called an oxide semiconductor having lane-anchored crystals. Cut.

[0276] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors is determined by the presence of impurities. Conversely, CAAC-O may be degraded due to contamination or defect generation. S can be considered an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0277] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0278] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the ZnO traps hydrogen and becomes a carrier generation source.

[0279] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. There is. Specifically, 8×1011 pieces / cm 3 Less than 1 x 10 11 / cm 3 less than , and more preferably 1×10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 The above Such an oxide semiconductor can be obtained by using a high-purity pure oxide semiconductor. CAAC-OS is a highly pure or substantially intrinsic oxide semiconductor with low impurity concentration. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0280] <2-3.nc-OS> Next, we will explain nc-OS.

[0281] The following describes the case where nc-OS is analyzed by XRD. However, when structural analysis was performed using the out-of-plane method, no peaks indicating orientation appeared. That is, the crystals of the nc-OS do not have any orientation.

[0282] For example, an nc-OS having InGaZnO4 crystals was sliced ​​to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on the region of m, the result shown in Fig. 2 A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in 2(A) was observed. In addition, the diffraction pattern when an electron beam with a probe diameter of 1 nm is incident on the same sample ( The nanobeam electron diffraction pattern is shown in Figure 22(B). Therefore, the nc-OS has a probe diameter of 50 nm. No order was observed when an electron beam with a probe diameter of 1 nm was incident. When light is incident on it, order is confirmed.

[0283] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 22(C), an electron diffraction pattern was observed in which the spots were arranged in a substantially regular hexagonal shape. Therefore, it is considered that the nc-OS is ordered in the range of thickness less than 10 nm. It can be seen that the crystals are highly ordered. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0284] FIG. 22(D) shows the Cs-corrected height of the cross section of the nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image as the area indicated by the auxiliary lines. How to identify the crystals and the areas where no clear crystals can be identified The crystal parts in the nc-OS have a size of 1 nm to 10 nm. In particular, the size of the crystals is often between 1 nm and 3 nm. An oxide semiconductor having a size of 10 nm or more and 100 nm or less is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). o crystalline oxide semiconductor) For example, in the case of nc-OS, the grain boundaries are often not clearly visible in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, below, the crystalline part of the nc-OS may be referred to as a pellet.

[0285] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, particularly The atomic arrangement has periodicity in the region of 1 nm to 3 nm. In the case of the Cr-Al-Al-Fe-Al-Fe-O-Pb-Al-Zn ... Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. In some cases, it may be difficult to distinguish them from solid oxide semiconductors.

[0286] In addition, since the crystal orientation between the pellets (nanocrystals) is not regular, nc-OS is , oxidation with RANC (Random Aligned nanocrystals) Semiconductors or NANC (Non-Aligned nanocrystals) In other words, the oxide semiconductor has a conductivity of 1000.

[0287] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0288] <2-4.a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a semiconductor.

[0289] FIG. 23 shows a high-resolution cross-sectional TEM image of the a-like OS. is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. B) is 4.3 x 10 8 e - / nm 2 Electrons (e - ) A-like OS after irradiation High-resolution cross-sectional TEM images. Figures 23(A) and 23(B) show that a-like O It can be seen that striped bright regions extending in the vertical direction are observed in S from the start of electron irradiation. It can also be seen that the shape of the bright regions changes after electron irradiation. It is suspected to be a density region.

[0290] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the change in structure due to electron irradiation.

[0291] As samples, a-like OS, nc-OS and CAAC-OS are prepared. Both samples are In-Ga-Zn oxides.

[0292] First, high-resolution cross-sectional TEM images of each sample are obtained. All of the materials have crystalline parts.

[0293] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn It is known that the structure has a total of nine layers, six of which are -O layers, stacked in layers in the c-axis direction. The distance between these adjacent layers is the lattice spacing (also called the d value) of the (009) plane. The value is about the same, and is calculated to be 0.29 nm from crystal structure analysis. In the following, the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less is called InGaZ. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0294] Figure 24 shows an example of the average size of the crystal parts (22 to 30 places) of each sample. The length of the lattice fringes is the size of the crystal part. e. The crystal part of the OS grows larger according to the cumulative dose of electrons used in obtaining the TEM image. From Figure 24, it can be seen that in the early stages of TEM observation, the size of the particles is about 1.2 nm. The part of the crystal that was raised (also called the initial nucleus) absorbs electrons (e - ) cumulative exposure of 4.2 × 10 8 e - / nm 2 It can be seen that the size of the crystals grows to about 1.9 nm in the n For c-OS and CAAC-OS, the cumulative electron irradiation dose was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of 100 to 150 mm. Therefore, the size of the crystalline parts of nc-OS and CAAC-OS is , and 1.3 nm and 1.8 nm, respectively. The Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. The conditions were an acceleration voltage of 300 kV and a current density of 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter of the region was set to 230 nm.

[0295] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. That is, a-like OS is not seen in comparison with nc-OS and CAAC-OS. , it is clear that this is an unstable structure.

[0296] In addition, because of the presence of porosity, a-like OS is more difficult to treat than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is The density of the nc-OS and the CAA The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0297] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0298] If single crystals of the same composition are not available, single crystals of different compositions may be combined in any ratio. By combining these, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density of a single crystal of a desired composition is calculated based on the ratio of the single crystals of different compositions. However, the density can be estimated by using as few types of single crystals as possible. A combined estimate is preferred.

[0299] As described above, oxide semiconductors have various structures and each structure has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the CAAC-OS and CAAC-OS.

[0300] The configuration shown in this embodiment may be combined with other configurations shown in other embodiments or examples. They can be used in combination.

[0301] (Embodiment 3) In this embodiment, a display device including the transistor described in the above embodiment will be An example will be described below with reference to FIGS.

[0302] 25 is a top view showing an example of a display device. The display device 700 shown in FIG. A pixel portion 702 is provided on the first substrate 701, and a source driver is provided on the first substrate 701. A pixel portion 702, a source driver circuit portion 704, a gate driver circuit portion 706, A sealant 712 is disposed so as to surround the path portion 704 and the gate driver circuit portion 706. and a second substrate 705 disposed so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 seal the entire structure. Although not shown in FIG. 25, a display element is provided between the first substrate 701 and the second substrate 705. can be done.

[0303] The display device 700 is surrounded by a sealant 712 on the first substrate 701. A pixel section 702, a source driver circuit section 704, and a gate driver circuit section 705 are arranged in a region different from the region. and a flexible printed circuit (FPC) terminal section 708 (FPC: Flex Also, an FPC terminal portion 708 is provided. An FPC 716 is connected to the pixel section 702 and the source driver circuit. Various signals are supplied to the path section 704 and the gate driver circuit section 706. 702, a source driver circuit section 704, a gate driver circuit section 706, and an FPC terminal section Signal lines 710 are connected to the terminals 708. Various signals are supplied by the FPC 716. The signals are transmitted through a signal line 710 to a pixel section 702, a source driver circuit section 704, a gate driver A driver circuit portion 706 and an FPC terminal portion 708 are provided.

[0304] The display device 700 may include a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit is formed (for example, A driving circuit board formed of a monocrystalline semiconductor film or a polycrystalline semiconductor film is mounted on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead, we use COG (Chip On Glass) method, wire bonding method, etc. can be used.

[0305] The display device 700 also includes a pixel portion 702, a source driver circuit portion 704, and a gate The driver circuit portion 706 includes a plurality of transistors. A transistor having a specific position can be applied.

[0306] The display device 700 can also include various elements, such as: For example, electroluminescence (EL) elements (EL elements including organic and inorganic materials, Organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistors (transistors that emit light according to the current transistor), electron emission element, liquid crystal element, electronic ink element, electrophoretic element, electron Etching elements, plasma displays (PDP), MEMS (microelectromechanical systems) Mechanical systems) displays (e.g., Grating Light Valve (GLV) ), Digital Micromirror Device (DMD), Digital Micro Shutter (D MS elements, interference modulation (IMOD) elements, piezoelectric and photonic displays.

[0307] An example of a display device using an EL element is an EL display. An example of a display device using emission elements is a field emission display (FE D) or SED type flat panel display (SED: Surface-conductio n Electron-emitter Display) and others. An example of such a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). Display, reflective LCD display, direct-view LCD display, projection LCD display Examples of display devices using electronic ink elements or electrophoretic elements include: Electronic paper. Semi-transmissive LCDs and reflective LCDs are also used. In this case, a part or the whole of the pixel electrode should function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, a memory circuit such as an SRAM may be provided under the reflective electrode. This can further reduce power consumption.

[0308] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying in color are R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a pixel, and a pixel of white (W). As in the column, two colors of RGB form one color element, and different two colors are generated depending on the color element. You can also select colors to configure the color. Or, you can select one or more colors such as yellow, cyan, and magenta for RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, and may be used in monochrome display devices. The present invention can also be applied to display devices.

[0309] Also, white light is emitted from the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) In order to display full color using (W), a colored layer (also called a color filter) is The colored layer may be, for example, red (R), green (G), blue (B), or red (C). ), yellow (Y), etc. can be used in appropriate combination. In this case, the color reproducibility can be improved compared to when no color layer is used. By disposing a region having a color layer and a region not having a color layer, The white light in the region may be directly used for display. By placing the colored layer over the entire display, the decrease in brightness caused by the colored layer can be reduced during bright display, and power consumption can be reduced by 2. However, in some cases, the emission of light from organic EL elements and inorganic EL elements can be reduced by about 10 to 30%. When using optical elements to display full color, R, G, B, Y, and W are each emitted in different colors. By using a self-luminous element, it is possible to obtain a light emission from a colored layer. In some cases, power consumption can be reduced even further.

[0310] In addition, as a colorization method, a part of the light emitted from the above-mentioned white light is passed through a color filter. In addition to the color filter method, which converts the light into red, green, and blue by filtering the light, A method that uses two colors of light (three-color method), or a method that uses part of the light emitted from the blue light to emit red or A method for converting to green (color conversion method, quantum dot method) may be applied.

[0311] In this embodiment, a liquid crystal element and an EL element are used as display elements. 26 and 27. Note that FIG. 26 shows the area indicated by the dashed line QR in FIG. FIG. 27 is a cross-sectional view of the liquid crystal display device, which uses a liquid crystal element as a display element. 25 is a cross-sectional view taken along dashed line QR in FIG. 25, and shows a configuration in which an EL element is used as a display element. It is.

[0312] First, the common parts shown in FIG. 26 and FIG. 27 will be explained, and then the different parts will be explained. This will be explained below.

[0313] <3-1. Explanation of common parts of display devices> The display device 700 shown in FIG. 26 and FIG. 27 includes a wiring portion 711 and a pixel portion 702. The display panel 700 includes a source driver circuit section 704 and an FPC terminal section 708. The line portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and The source driver circuit portion 704 includes a transistor 752. Yes.

[0314] Transistor 750 and transistor 752 are similar to transistor 100 shown above. The structures of the transistors 750 and 752 are the same as those described above. Any other transistors than those shown in the embodiment modes may be used.

[0315] The transistor used in this embodiment is made of a highly purified oxide film in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. It is possible to extend the retention time of electrical signals such as signals, and the write interval can be extended when the power is on. This allows the frequency of refresh operations to be reduced, resulting in reduced power consumption. It has the effect of suppressing power.

[0316] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed operation can be used for a liquid crystal display. By using this in a display device, the switching transistor in the pixel section and the driver circuit section In other words, the driver transistor can be formed on the same substrate as the driver circuit. Therefore, it is not necessary to use a semiconductor device formed from a silicon wafer or the like. The number of components can be reduced. By using a register, a high quality image can be provided.

[0317] The capacitor 790 includes a lower electrode and an upper electrode. The oxide semiconductor film and the first The oxide semiconductor film is formed through the same process. The upper electrode is formed through a process of processing the conductive film. The conductive film and the source electrode and the drain electrode of the transistor 750 are The functional conductive film is formed through the same process. The insulating film serving as the second insulating film of the transistor 750 and the third insulating film That is, the capacitor 790 has an insulating film between a pair of electrodes that functions as a dielectric. It has a laminated structure in which an insulating film that functions as a gate insulating film is sandwiched.

[0318] 26 and 27, a transistor 750, a transistor 752, and a capacitor A planarization insulating film 770 is provided on the capacitor 790 .

[0319] The planarization insulating film 770 may be made of a polyimide resin, an acrylic resin, or a polyimide amide resin. Heat-resistant organic materials such as benzocyclobutene resin, polyamide resin, and epoxy resin In addition, by stacking multiple insulating films made of these materials, A planarization insulating film 770 may be formed. Alternatively, the planarization insulating film 770 may not be provided. This is also fine.

[0320] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed through the same process as the conductive film that functions as the transistor. A conductive film formed through a process different from that of the source electrode and drain electrode of 750 and 752, e.g. For example, an oxide semiconductor film formed through the same process as an oxide semiconductor film functioning as a gate electrode may be used. For example, when a material containing copper is used as the signal line 710, the wiring There is little signal delay caused by line resistance, making it possible to display on a large screen.

[0321] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed through the same process as the conductive film that functions as the drain electrode. , and is electrically connected to a terminal of the FPC 716 via an anisotropic conductive film 780 .

[0322] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0323] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film. A device for controlling the distance (cell gap) between the first substrate 701 and the second substrate 705 is provided. In addition, a spherical spacer may be used as the structure 778.

[0324] In addition, on the second substrate 705 side, a light-shielding film 738 functioning as a black matrix and A colored film 736 that functions as a color filter, a light-shielding film 738 that is in contact with the colored film 736, and An insulating film 734 is provided.

[0325] <3-2. Configuration examples of display devices using liquid crystal elements> The display device 700 shown in FIG. 26 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film The conductive film 774 is a second substrate 705. The display device 700 shown in FIG. The alignment state of the liquid crystal layer 776 changes depending on the voltage applied to the conductive film 772 and the conductive film 774. By controlling the light transmission or non-transmission, an image can be displayed.

[0326] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is connected to a conductive film that functions as a pixel electrode. The conductive film 772 functions as a reflective electrode, that is, one of the electrodes of the display element. The display device 700 shown in FIG. The liquid crystal display device 730 is a so-called reflective color liquid crystal display device, which reflects the light and displays it through the colored film 736.

[0327] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a reflectivity can be used. For example, a material containing one of the elements indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum In this embodiment, the conductive film 772 may be formed of A conductive film that is reflective in visible light is used.

[0328] In the display device 700 shown in FIG. 26, the planarization insulating film 770 of the pixel section 702 The unevenness is provided in a part. For example, the flattening insulating film 770 is made of a resin film. The surface of the resin film may be provided with irregularities to form the reflecting electrode. The conductive film 772 is formed along the above-mentioned unevenness. When the light is incident on the conductive film 772, the light can be diffusely reflected on the surface of the conductive film 772. It is possible to improve the performance.

[0329] The display device 700 shown in FIG. 26 is a reflective color liquid crystal display device. However, the present invention is not limited to this. For example, the conductive film 772 may be a conductive film that transmits visible light. A transmissive color liquid crystal display device may be formed by using the above-mentioned. In this case, the unevenness provided in the planarization insulating film 770 does not necessarily have to be provided.

[0330] Although not shown in FIG. 26, the conductive films 772 and 774 on the side in contact with the liquid crystal layer 776 In addition, although not shown in FIG. Optical members (optical substrates) such as optical members, phase difference members, and anti-reflection members may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. Crites, sidelights, etc. may also be used.

[0331] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, the liquid crystal material can have a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0332] In addition, when the in-plane switching method is adopted, liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. Since the liquid crystal display has a short rotational angle and is optically isotropic, no alignment treatment is required. Since the rubbing process is unnecessary, electrostatic damage caused by the rubbing process is prevented. This can prevent the occurrence of defects or damage to the liquid crystal display device during the manufacturing process. Furthermore, liquid crystal materials exhibiting a blue phase have little viewing angle dependency.

[0333] In addition, when liquid crystal elements are used as display elements, TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero lectric Liquid Crystal) mode, AFLC (AntiFerr Electrochemical Liquid Crystal (ECC) mode can be used. .

[0334] In addition, normally black type liquid crystal display devices, for example, those using a vertical alignment (VA) mode The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode mode, ASV mode, etc. can be used.

[0335] <3-3. Display devices using light-emitting elements> The display device 700 shown in FIG. 27 includes a light-emitting element 782. The light-emitting element 782 includes a conductive film The display device 700 shown in FIG. The EL layer 786 of the light element 782 emits light, thereby displaying an image. do.

[0336] The conductive film 784 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is connected to a conductive film that functions as a pixel electrode. The conductive film 784 functions as an electrode, that is, one of the electrodes of the display element. In the above, a conductive film that transmits light or a conductive film that reflects visible light can be used. Examples of conductive films that are transparent to visible light include indium (In), zinc (Zn), and ZnO. It is recommended to use a material containing one of the following elements: Zn (Zn) or tin (Sn). The reflective conductive film may be made of a material containing aluminum or silver. stomach.

[0337] In addition, in the display device 700 shown in FIG. 27, an insulating film is provided over the planarization insulating film 770 and the conductive film 784. An insulating film 730 is provided. The insulating film 730 covers a part of the conductive film 784. 782 has a top emission structure. Therefore, the conductive film 788 has a light transmitting property, and It transmits the light emitted by the L layer 786. In this embodiment, the top emission The structure is exemplified, but is not limited to this. For example, a bottom emission structure in which light is emitted to both the conductive film 784 and the conductive film 788; It can also be applied to al-emission structures.

[0338] A colored film 736 is provided at a position overlapping the light emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided at the position where the light-shielding film 738 is to be formed, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is illustrated. For example, when the EL layer 786 is formed by coloring, The film 736 may not be provided.

[0339] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes or examples. It can be used.

[0340] (Embodiment 4) In this embodiment, the memory contents can be retained even when power is not supplied, and writing is possible. An example of a circuit configuration of a semiconductor device with no limit on the number of times of reading will be described with reference to FIG.

[0341] <4-1. Circuit configuration> FIG. 28 is a diagram illustrating a circuit configuration of a semiconductor device. In FIG. 1st Line) and the source electrode or drain electrode of p-type transistor 1280a The other side is electrically connected to the source electrode of the p-type transistor 1280a. The other of the source and drain electrodes of the n-type transistor 1280b is connected to the source or drain electrode of the n-type transistor 1280c. The source voltage of the n-type transistor 1280b is electrically connected to one of the electrodes. The other of the electrode or drain electrode of the n-type transistor 1280c is connected to the source electrode or drain electrode of the n-type transistor 1280c. The electrode is electrically connected to one of the electrodes.

[0342] In addition, the second wiring (2nd Line) and the source electrode of the transistor 1282 or The source electrode of the transistor 1282 is electrically connected to one of the drain electrodes. The other of the source electrode or drain electrode, one of the electrodes of the capacitor 1281 and the n-type transistor The gate electrode of the second transistor 1280c is electrically connected to the gate electrode of the first transistor 1280a.

[0343] In addition, a third wiring (3rd Line), a p-type transistor 1280a, and an n-type transistor The gate electrode of the transistor 1280b is electrically connected to the fourth wiring (4 th Line) and the gate electrode of the transistor 1282 are electrically connected In addition, the fifth wiring (5th Line), the other electrode of the capacitor element 1281, and the n-type transistor The other of the source electrode or the drain electrode of the transistor 1280c is electrically connected. In addition, the sixth line and the source of the p-type transistor 1280a The other of the electrode or drain electrode and the source electrode or drain electrode of the n-type transistor 1280b The electrode is electrically connected to one of the in-electrodes.

[0344] Note that the transistor 1282 is an oxide semiconductor (OS). Therefore, in FIG. 28, the transistor The symbol “OS” is added to the transistor 1282. Note that the transistor 1282 is made of an oxide semiconductor. It may be formed from materials other than those.

[0345] In addition, in FIG. 28, the other of the source electrode and the drain electrode of the transistor 1282 One of the electrodes of the capacitor 1281 and the gate electrode of the n-type transistor 1280c The connection point is labeled as a floating node (FN). By turning off the floating node, one of the electrodes of the capacitor 1281, and the n The potential applied to the gate electrode of the second type transistor 1280c can be maintained.

[0346] In the circuit configuration shown in FIG. 28, the potential of the gate electrode of the n-type transistor 1280c can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0347] <4-2. Writing and storing information> First, writing and holding of data will be described. The transistor 1282 is turned on by applying a potential to the transistor 1282. As a result, the potential of the second wiring is applied to the gate electrode of the n-type transistor 1280c and the capacitor 12 That is, a predetermined voltage is applied to the gate electrode of the n-type transistor 1280c. Then, the potential of the fourth wiring is applied to the transistor 1282. The transistor 1282 is turned off by applying a potential to the n-type transistor 1281. The charge applied to the gate electrode of transistor 1280c is retained (retained).

[0348] Since the off-state current of the transistor 1282 is extremely small, the The charge on the gate electrode is retained for a long period of time.

[0349] <4-3. Reading information> Next, the reading of information will be described. At this time, the p-type transistor 1280a is turned on and the n-type transistor 1280b is turned off. At this time, the potential of the first wiring is applied to the sixth wiring. On the other hand, When the potential is set to a high level potential, the p-type transistor 1280a is turned off, and At this time, the floating node (FN) Depending on the amount of charge stored, the sixth wire has a different potential. By looking at the position, the stored information can be read (read).

[0350] In addition, the transistor 1282 is extremely The off-state current of the transistor 1282 using an oxide semiconductor is small. The off-state current is less than 1 / 100,000 of that of transistors made of silicon semiconductors, etc. Since the transistor 1282 is a current, the floating node (FN) It is possible to ignore the loss of the stored charge. A non-volatile memory circuit that can retain information even without power supply using the transistor 1282 It is possible to achieve the following.

[0351] In addition, a semiconductor device using such a circuit configuration may be used as a register, a cache memory, or the like. By using it in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire storage device or one or more components constituting the storage device can be In logic circuits, the power can be stopped for a short time during standby, so the power consumption is reduced. This can reduce power consumption.

[0352] The configurations and methods described in the present embodiment may be used in combination with configurations and methods described in other embodiments or examples. , and the like can be used in appropriate combination.

[0353] (Embodiment 5) In this embodiment, a configuration of a pixel circuit that can be used in a semiconductor device of one embodiment of the present invention will be described. The following will explain this with reference to FIG.

[0354] <5-1. Pixel circuit configuration> FIG. 29(A) is a diagram illustrating the configuration of a pixel circuit. The circuit shown in FIG. Electrical conversion element 1360, transistor 1351, transistor 1352, transistor 13 53, and a transistor 1354.

[0355] The anode of the photoelectric conversion element 1360 is connected to the wiring 1316, and the cathode is connected to the transistor The transistor 1351 is connected to one of the source electrode and the drain electrode of the transistor 1351. The other of the source electrode and the drain electrode is connected to the charge storage section (FD), and the gate electrode is The source electrode or drain electrode of the transistor 1352 is connected to the line 1312 (TX). One of the electrodes is connected to the wiring 1314 (GND), and the other of the source electrode or drain electrode is The gate electrode is connected to one of the source electrode and the drain electrode of the transistor 1354. The source electrode or drain electrode of the transistor 1353 is connected to the charge storage portion (FD). One of the electrodes is connected to the charge storage section (FD), and the other is the source electrode or drain electrode. The gate electrode of the transistor 1 is connected to the wiring 1311 (RS). The other of the source electrode or drain electrode of 354 is connected to the wiring 1315 (OUT). The port electrode is connected to a wiring 1313 (SE). Note that all of the above connections are electrical connections. do.

[0356] The wiring 1314 may be supplied with a potential such as GND, VSS, or VDD. Here, potential and voltage are relative. Therefore, the magnitude of the GND potential is always However, it is not necessarily 0 volts.

[0357] The photoelectric conversion element 1360 is a light receiving element that generates a current according to the light incident on the pixel circuit. The transistor 1353 functions as a charge storage portion (F The transistor 1354 has a function of controlling charge accumulation in the charge accumulation unit (FD The transistor 1352 has a function of outputting a signal according to the potential of the charge storage portion ( The transistor 1352 has a function of resetting the potential of the pixel It has the function of controlling the selection of circuits.

[0358] The charge storage unit (FD) is a charge storage node, and the photoelectric conversion element 1360 receives It holds an electrical charge that changes depending on the amount of light.

[0359] The transistor 1352 and the transistor 1354 are connected to the wiring 1315 and the wiring 131 4. Therefore, the wiring 1314 and the transistor 13 52, the transistor 1354, and the wiring 1315 may be arranged in this order. Alternatively, the transistor 1354, the transistor 1352, and the wiring 1315 may be arranged in this order.

[0360] The wiring 1311 (RS) functions as a signal line for controlling the transistor 1353. The wiring 1312 (TX) serves as a signal line for controlling the transistor 1351. The wiring 1313 (SE) is a signal for controlling the transistor 1354. The wiring 1314 (GND) serves as a reference potential (for example, GND). The wiring 1315 (OUT) functions as a signal line for determining whether The wiring 1316 functions as a signal line for reading out a signal output from the As a signal line for outputting electric charge from the storage unit (FD) via the photoelectric conversion element 1360 The wiring 1317 has a charge transfer function and is a low potential line in the circuit of FIG. It has a function as a signal line for resetting the potential of the storage section (FD), and is shown in FIG. In the circuit, it is a high potential line.

[0361] Next, the configuration of each element shown in FIG. 29(A) will be described.

[0362] <5-2. Photoelectric conversion element> The photoelectric conversion element 1360 contains selenium or a compound containing selenium (hereinafter referred to as a selenium-based material). or silicon-containing devices (e.g., devices in which pin-type junctions are formed). In addition, a transistor using an oxide semiconductor and a transistor using selenium By combining it with a photoelectric conversion element using a material based on ZnO, reliability can be improved. preferable.

[0363] <5-3.Transistor> Transistor 1351, transistor 1352, transistor 1353, and transistor Zysta 1354 is a material that can be used for amorphous silicon, microcrystalline silicon, polycrystalline silicon, and single crystal silicon. Although it is possible to form the transistor using a silicon semiconductor such as oxide semiconductor, It is preferable that the transistor has a channel formation region formed of an oxide semiconductor. The transistor has the characteristic of exhibiting an extremely low off-state current. As a transistor having a channel forming region, for example, the transistor shown in the first embodiment may be used. A star can be used.

[0364] In particular, a transistor 1351 connected to the charge storage unit (FD) and a transistor If the leakage current of 1353 is large, the charge stored in the charge storage section (FD) can be held for a long time. Therefore, the distance between the two transistors is insufficient. By using a transistor that uses this technology, unnecessary charge leakage from the charge storage section (FD) is prevented. It can be stopped.

[0365] In addition, the transistor 1352 and the transistor 1354 also have a large leakage current. If the voltage is too high, unnecessary charge will be output to the wiring 1314 or wiring 1315. A transistor in which a channel formation region is formed using an oxide semiconductor is used as the transistor. It is preferred.

[0366] FIG. 29A illustrates a transistor having one gate electrode. However, the present invention is not limited to this, and may have a configuration having a plurality of gate electrodes. As a transistor having a gate electrode, for example, a semiconductor having a channel forming region is used. a first gate electrode and a second gate electrode (also called a backgate electrode) overlapping the body membrane; The back gate electrode may have a structure having, for example, a first gate electrode and The same potential, a floating potential, or a potential different from that of the first gate electrode may be applied.

[0367] <5-4. Circuit operation timing chart> Next, an example of the circuit operation of the circuit shown in FIG. 29(A) will be described with reference to the timing diagram shown in FIG. 29(B). This will be explained using a diagram.

[0368] In FIG. 29B, for the sake of simplicity, the potential of each wiring is given as a signal that changes into two values. However, since each potential is an analog signal, it is not limited to binary values ​​and may be various depending on the situation. Note that the signal 1401 shown in FIG. 29B can take the value of the potential of the wiring 1311 (RS). A signal 1402 is the potential of the wiring 1312 (TX), and a signal 1403 is the potential of the wiring 1313 (SE). The potential, signal 1404, is the potential of the charge storage unit (FD), and the signal 1405 is the potential of the wiring 1315 (OUT The potential of the wiring 1316 is always “Low”, and the potential of the wiring 1317 is always “Low”. is always set to “High”.

[0369] At time A, the potential of the wiring 1311 (signal 1401) is set to “High” and the potential of the wiring 1312 is set to “High”. When the potential (signal 1402) of the charge storage unit (FD) is set to "High", the potential (signal 14 04) is initialized to the potential of the wiring 1317 ("High"), and the reset operation begins. Note that the potential of the wiring 1315 (signal 1405) is precharged to "High". .

[0370] At time B, when the potential of the wiring 1311 (signal 1401) is set to “Low”, the reset The operation ends and the accumulation operation begins. Here, the photoelectric conversion element 1360 has a reverse bias. Since a reverse current flows, the potential (signal 1404) of the charge storage section (FD) When the photoelectric conversion element 1360 is irradiated with light, the reverse current increases, so The rate at which the potential (signal 1404) of the charge storage section (FD) drops varies depending on the amount of light irradiated. That is, the transistor 135 The channel resistance between the source and drain of 4 changes.

[0371] At time C, when the potential of the wiring 1312 (signal 1402) is set to “Low”, the accumulation operation Then, the potential (signal 1404) of the charge storage unit (FD) becomes constant. is determined by the amount of charge generated by the photoelectric conversion element 1360 during the accumulation operation. The output of the transistor 135 changes depending on the amount of light irradiated onto the conversion element 1360. The transistor 1353 is an off-state current transistor having a channel formation region formed of an oxide semiconductor. Since it is composed of transistors with extremely low It is possible to keep the potential of the charge storage section (FD) constant until

[0372] When the potential of the wiring 1312 (signal 1402) is set to “Low”, The potential of the charge storage unit (FD) changes due to the parasitic capacitance between the charge storage unit (FD) and the If the change in the potential is large, the photoelectric conversion element 136 may Therefore, the amount of charge generated by 0 cannot be accurately obtained. To reduce the amount of change in the potential, , the gate electrode-source electrode (or gate electrode-drain electrode) of the transistor 1351 ) capacitance, increasing the gate capacitance of the transistor 1352, and In this embodiment, it is effective to provide a storage capacitor for the The change in potential is assumed to be negligible due to the above measures.

[0373] At time D, when the potential of the wiring 1313 (signal 1403) is set to “High”, the transistor The transistor 1354 becomes conductive to start the selection operation, and the wiring 1314 and the wiring 1315 become Then, the potential of the wiring 1315 ( The signal 1405) drops. Note that the precharge of the wiring 1315 is completed before time D. The rate at which the potential of the wiring 1315 (signal 1405) decreases is It depends on the current between the source and drain electrodes of the transistor 1352. It changes depending on the amount of light irradiated onto the photoelectric conversion element 1360 during operation.

[0374] At time E, when the potential of the wiring 1313 (signal 1403) is set to “Low”, the transistor The resistor 1354 is cut off, the selection operation is terminated, and the potential of the wiring 1315 (signal 1405) Here, the constant value is determined by the amount of light irradiated onto the photoelectric conversion element 1360. Therefore, by acquiring the potential of the wiring 1315, Therefore, the amount of light irradiated onto the photoelectric conversion element 1360 can be known.

[0375] More specifically, when the light irradiating the photoelectric conversion element 1360 is strong, the charge storage portion (F D), i.e., the gate voltage of transistor 1352, drops. The current flowing between the source electrode and the drain electrode of the transistor 1352 becomes small, and the wiring 1315 Therefore, the potential of the signal 1405 is relatively low from the wiring 1315. A high potential can be read out.

[0376] Conversely, when the light irradiating the photoelectric conversion element 1360 is weak, the potential of the charge storage unit (FD) That is, the gate voltage of the transistor 1352 becomes high. The current flowing between the source electrode and the drain electrode of 352 becomes large, and the potential of the wiring 1315 ( The signal 1405) falls quickly. Therefore, a relatively low potential is read from the wiring 1315. It can be put out.

[0377] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes or examples. It can be used as such.

[0378] (Embodiment 6) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0379] <6. Circuit configuration of display device> The display device shown in FIG. 30A includes a region having pixels (hereinafter, referred to as a pixel portion 502). A circuit section (hereinafter, a driving section) is disposed outside the pixel section 502 and has a circuit for driving the pixel. A circuit portion 504) and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 506) and a terminal portion 507. Note that the protection circuit 506 does not necessarily have to be provided.

[0380] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or the whole of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Band). It can be implemented by using the onding.

[0381] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter, referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter, a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a) to provide a signal (data signal) for driving the display element of the pixel. The pixel circuit 504 includes a driver circuit such as a circuit (hereinafter, referred to as a source driver 504b).

[0382] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is input via a terminal unit 507, and a signal is output. For example, a start pulse signal, a clock signal, etc. are input to the gate driver 504a. The gate driver 504a outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it. However, the gate driver 50 has a function of supplying 4a may also provide another signal.

[0383] The source driver 504b includes a shift register and the like. Through the terminal section 507, a signal for driving the shift register as well as a source of a data signal are input. The source driver 504b outputs a pixel circuit based on the image signal. The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated according to a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data line 101 through the data line 102. Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may also supply other signals. It is possible.

[0384] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a number of analog switches, The image signal can be time-division-divided and output as a data signal. Also, a shift register, etc. This may be used to configure the source driver 504b.

[0385] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is inputted through the data line DL, and a data signal is given through one of the data lines DL. A data signal is input to each of the pixel circuits 501. 504a controls writing and holding of data of the data signal. For example, The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or smaller than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via a source driver 504c (n is a natural number equal to or smaller than Y).

[0386] The protection circuit 506 shown in FIG. 30(A) is, for example, a gate driver 504a and a pixel circuit 5 01. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the driver 504b and the pixel circuit 501. The protection circuit 506 can be connected to a wiring between the gate driver 504a and the terminal unit 507. Alternatively, the protection circuit 506 may be a wiring between the source driver 504b and the terminal unit 507. The terminal unit 507 can be connected to a power supply and a power supply line from an external circuit to the display device. This refers to the part provided with terminals for inputting control signals and image signals.

[0387] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit This is a circuit that brings one wire into electrical continuity with another wire.

[0388] As shown in FIG. 30A, a pixel section 502 and a driver circuit section 504 are provided with a protection circuit 50. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrent caused by electrostatic discharge (ESD) and the like. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a protection circuit 506 is connected to the source driver 504b Alternatively, a protection circuit 506 may be connected to the terminal portion 507. It can also be done like this.

[0389] In FIG. 30A, the gate driver 504a and the source driver 504b Therefore, although an example in which the driver circuit portion 504 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a source driver circuit is formed separately. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is It may also be configured to be equipped with

[0390] In addition, the pixel circuits 501 shown in FIG. 30(A) may be, for example, a configuration shown in FIG. It can be said that:

[0391] The pixel circuit 501 shown in FIG. 30B includes a liquid crystal element 570, a transistor 550, and a capacitor. The transistor 550 may be any of the transistors described in the previous embodiment. can be applied.

[0392] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. A different potential may be applied to one of the electrodes.

[0393] For example, the display device including the liquid crystal element 570 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned M icro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode, etc. may also be used. In addition to the above-mentioned driving method, the display device can be driven by an ECB (Electric Carrier Bipolar Transistor) or the like. Ally Controlled Birefringence mode, PDLC(P Oligomeric Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest hole However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of different types of sensors can be used.

[0394] In the pixel circuit 501 in the mth row and the nth column, One of the electrodes is electrically connected to the data line DL_n, and the other is a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the scan lines G L_m. The transistor 550 can be turned on or off. Thus, the write control circuit 100 has a function of controlling the writing of data of the data signal.

[0395] One of a pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0396] For example, in a display device having the pixel circuit 501 shown in FIG. The pixel circuits 501 in each row are sequentially selected by a gate driver 504a shown in FIG. 550 is turned on to write data of the data signal.

[0397] In the pixel circuit 501 in which data has been written, the transistor 550 is turned off. By repeating this process row by row, an image can be displayed.

[0398] In addition, the pixel circuits 501 shown in FIG. 30(A) may have a configuration shown in FIG. It can be said that:

[0399] The pixel circuit 501 shown in FIG. 30C includes transistors 552 and 554 and a capacitance element. The transistor 552 and the transistor 554 The transistor described in the above embodiment can be used for either or both of the above. .

[0400] A data signal is applied to one of the source and drain electrodes of the transistor 552. The transistor 5 is electrically connected to a line (hereinafter, referred to as a data line DL_n). The gate electrode 52 is connected to a wiring (hereinafter, referred to as a scanning line GL_m) to which a gate signal is applied. are electrically connected.

[0401] Transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of data.

[0402] One of a pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL _a), and the other is electrically connected to the source electrode and drain electrode of the transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0403] The capacitor 562 functions as a storage capacitor for storing written data.

[0404] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. In addition, the gate electrode of the transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0405] One of the anode and the cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b. The other one is electrically connected to the other of the source electrode and drain electrode of the transistor 554. will be done.

[0406] The light-emitting element 572 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light-emitting element 572 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0407] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0408] In a display device having the pixel circuit 501 shown in FIG. 30C, for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0409] In the pixel circuit 501 to which the data has been written, the transistor 552 is turned off. Furthermore, the transistor 554 is in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted with a brightness that corresponds to the flow rate. By performing this process row by row, an image can be displayed.

[0410] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes or examples. It can be used.

[0411] (Embodiment 7) In this embodiment, a display module and an electronic device each including a semiconductor device according to one embodiment of the present invention will be described. This will be described with reference to FIG. 31 and FIG.

[0412] <7-1. Display module> The display module 8000 shown in FIG. 31 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003, A display panel 8006, a backlight 8007, a frame 8009, and a printed circuit board 801 0, has battery 8011.

[0413] The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0414] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel The shape and dimensions can be changed as appropriate to match the size of 8006.

[0415] The touch panel 8004 is a resistive or capacitive touch panel. The display panel 8006 can be used by overlapping it with the opposing substrate (sealing substrate). It is also possible to provide the display panel 8 with a touch panel function. It is also possible to provide an optical sensor in each pixel of the display panel 006 to make it into an optical touch panel.

[0416] The backlight 8007 has a light source 8008. In FIG. In the above embodiment, the light source 8008 is disposed on the light source 8007, but the present invention is not limited to this. For example, a light source 8008 is arranged at the end of a backlight 8007, and a light diffusion plate is further used. In addition, when a self-luminous light-emitting element such as an organic EL element is used, or when a reflective In the case of a flat panel or the like, the backlight 8007 need not be provided.

[0417] The frame 8009 protects the display panel 8006 and also supports the movement of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the frame. The frame 8009 may also function as a heat sink.

[0418] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. , this can be omitted when using a commercial power source.

[0419] In addition, the display module 8000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0420] <7-2.Electronic equipment> 32(A) to 32(G) are diagrams showing electronic devices. These electronic devices are A body 9000, a display unit 9001, a speaker 9003, and operation keys 9005 (power switch, etc.) includes an operation switch), a connection terminal 9006, a sensor 9007 (force, displacement, position, speed, Acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electricity Measures field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays The device may have a built-in microphone 9008, etc.

[0421] The electronic devices illustrated in FIGS. 32A to 32G can have various functions. For example, the function to display various information (still images, videos, text images, etc.) on the display, Panel function, calendar, date or time display function, various software ( A function to control processing by a program, wireless communication function, and various functions using wireless communication function Functions for connecting to computer networks, transmitting various data using wireless communication functions, or receiving the program or data recorded on the recording medium, and displaying the program or data. The function of displaying the information on the display unit can be provided. The functions that the electronic device shown in the figure can have are not limited to these, and the electronic device may have a variety of functions. Although not shown in FIG. 32(A) to FIG. 32(G), the electronic device may include The electronic device may have a plurality of display units. The function to take pictures, record videos, and store the images on a recording medium (external or built-in to the camera) ) and a function for displaying the captured image on a display unit.

[0422] The electronic devices shown in FIGS. 32A to 32G will be described in detail below.

[0423] FIG. 32A is a perspective view showing a television device 9100. 100 is a display unit 9001 with a large screen of, for example, 50 inches or more or 100 inches or more. It is possible to incorporate.

[0424] FIG. 32B is a perspective view showing a portable information terminal 9101. For example, the device has one or more functions selected from a telephone, a notebook, an information viewing device, etc. Specifically, the mobile information terminal 9101 can be used as a smartphone. A speaker, a connection terminal, a sensor, and the like may be provided. Image information can be displayed on multiple sides of the screen. For example, three operation buttons 9050 ( Operation icons or simply icons) can be displayed on one side of the display unit 9001. Also, information 9051 shown in a dashed rectangle can be displayed on the other side of the display unit 9001. Examples of information 9051 include e-mail and social networking sites (SNS). Display to notify of incoming calls, e-mails, SNS, etc. Subject, sender name of email or SNS, date and time, time, remaining battery level, antenna reception Or, instead of information 9051, Alternatively, operation buttons 9050 and the like may be displayed.

[0425] FIG. 32C is a perspective view showing a portable information terminal 9102. , and has a function of displaying information on three or more faces of the display unit 9001. An example is shown in which information 9053 and information 9054 are displayed on different sides. The user of the portable information terminal 9102 holds the portable information terminal 9102 in the breast pocket of the clothes. In this state, the display (information 9053 in this case) can be confirmed. The telephone number or name of the caller is displayed on the mobile information terminal 9102 so that it can be observed from above. The user can read the display without taking the mobile information terminal 9102 out of his pocket. You can check the number and decide whether to answer the call or not.

[0426] 32(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The 9200 is used for mobile phone calls, e-mail, document browsing and writing, music playback, and Internet communications. It is possible to execute various applications such as computer games. The display unit 9001 has a curved display surface, and displays information along the curved display surface. In addition, the portable information terminal 9200 can perform short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, The mobile information terminal 9200 also has a connection terminal 9006. It has a connector and can directly exchange data with other information terminals. Charging can also be performed via the connection terminal 9006. Power may also be supplied wirelessly without going through 6.

[0427] 32(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 32(E) is a perspective view of the portable information terminal 9201 in an unfolded state. (F) shows the mobile information terminal 9201 being changed from one of the unfolded and folded states to the other. FIG. 32(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 is highly portable when folded and is unfolded. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 9001 is made up of three housings 9000 connected by hinges 9055. The two housings 9000 are supported by the hinge 9055. The portable information terminal 9201 can be reversibly transformed from an unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0428] The electronic device described in this embodiment has a display unit for displaying some information. However, the semiconductor device of one embodiment of the present invention is an electronic device that does not have a display portion. This can also be applied to vessels.

[0429] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes or examples. It can be used. EXAMPLES

[0430] In this example, a transistor according to one embodiment of the present invention was manufactured. The thermal properties were measured and the cross-sectional shape was observed.

[0431] In this example, sample A1 was prepared. First, the method for preparing sample A1 will be described. The sample A1 corresponds to the transistor 100C shown in FIGS. In the following description, the sample shown in FIG. ) The same components as those of the transistor 100C shown in (B) are denoted by the same reference numerals. This will be explained using:

[0432] <1-1. Preparation method of sample A1> First, a substrate 102 was prepared. A glass substrate was used as the substrate 102. Next, A conductive film 106 was formed on the conductive film 102. The conductive film 106 was a tungsten film having a thickness of 100 nm. The TEN film was formed using a sputtering device.

[0433] Next, an insulating film 104 was formed on the substrate 102 and the conductive film 106. In the insulating film 104, the insulating film 104_1, the insulating film 104_2, and the insulating film 104 7(A)(B)) in turn by PECVD. The insulating film 104_1 was formed continuously in a vacuum using a 50 nm thick film. The insulating film 104_2 was a silicon nitride film having a thickness of 300 nm. The insulating film 104_3 was a silicon nitride film having a thickness of 50 nm. The insulating film 104_4 was a silicon oxynitride film having a thickness of 50 nm.

[0434] Next, an oxide semiconductor film is formed over the insulating film 104 and processed into an island shape. The oxide semiconductor film 108 was formed by depositing a 40 The oxide semiconductor film 108 was formed using a sputtering method. Using a sputtering device, metal oxide with the atomic ratio of In:Ga:Zn=1:1:1.2 was sputtered. A ring target was used, and an AC power source was used as the power source applied to the sputtering target. The oxide semiconductor film 108 was processed by a wet etching method. Ta.

[0435] Next, an insulating film that will become the insulating film 110 later is formed over the insulating film 104 and the oxide semiconductor film 108. The insulating film was formed by a 10-nm-thick silicon oxynitride film and a 90-nm-thick A silicon oxynitride film was successively formed in vacuum using a PECVD apparatus.

[0436] Next, a heat treatment was performed. The heat treatment was performed in a mixed gas atmosphere of nitrogen and oxygen for 3 h. The heat treatment was carried out at 50°C for 1 hour.

[0437] Next, an oxide semiconductor film is formed over the insulating film and processed into an island shape. After the oxide semiconductor film 112 was formed, The insulating film in contact with the lower side of the oxide semiconductor film 112 was processed to form the insulating film 110. .

[0438] Note that the oxide semiconductor film 112 is processed by a wet etching method, and the insulating film 110 The dry etching method was used for processing.

[0439] Next, the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the oxide semiconductor film 11 The impurity element was added from the top of the substrate. The impurity element used was argon.

[0440] Next, the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the oxide semiconductor film 11 An insulating film 116 was formed on the substrate 2. The insulating film 116 was a silicon nitride film having a thickness of 100 nm. The film was formed using a PECVD apparatus.

[0441] Next, an insulating film 118 was formed on the insulating film 116. The insulating film 118 had a thickness of 300 mm. A silicon oxynitride film with a thickness of 1 nm was formed using a PECVD apparatus.

[0442] Next, a mask is formed on the insulating film 118, and the insulating films 116 and 118 are The openings 141a and 141b were formed in the substrate 141. A light etching apparatus was used.

[0443] Next, an insulating film 122 was formed on the insulating film 118. The insulating film 122 had a thickness of 1.5 The insulating film 122 was an acrylic photosensitive resin film having a thickness of 1 μm. An opening was provided in the area overlapping with 141a and 141b.

[0444] Next, a conductive film is formed on the insulating film 122 so as to fill the openings 141a and 141b. The conductive film was processed into island shapes to form conductive films 120a and 120b.

[0445] The conductive films 120a and 120b are made of a titanium film having a thickness of 50 nm and an alumina film having a thickness of 400 nm. The aluminum film and the titanium film with a thickness of 100 nm were continuously deposited in a vacuum using a sputtering device. It was subsequently formed.

[0446] Through the above steps, a transistor corresponding to the transistor 100C shown in FIGS. A star was created.

[0447] In this embodiment, the transistor corresponding to the transistor 100C is The channel width W is set to 50 μm, and the channel length L is set to 1.5 μm, 2.0 μm, and 3.0 μm. In addition, 20 transistors of each channel width L were formed on the substrate.

[0448] <1-2. Electrical characteristics of transistors> 33(A), (B), and (C) show the drain of the transistor of the sample A1 fabricated in this example. The current-gate voltage (Id-Vg) characteristics are shown.

[0449] FIG. 33(A) shows the characteristic results for a size of W / L=50 μm / 1.5 μm. 3(B) shows the characteristic results for a W / L=50μm / 2.0μm size, and FIG. 33(C) shows the characteristic results for a W / L=50μm / 2.0μm size. The characteristics are shown for the W / L=50μm / 3.0μm size. ), the first vertical axis is Id [A], and the second vertical axis is field effect mobility (μFE [cm 2 / V s]) and the horizontal axis represents Vg [V].

[0450] The Id-Vg characteristics of the transistor were measured under the following conditions: A voltage (hereinafter also referred to as a gate voltage (Vg)) is applied to the conductive film 106 which functions as a gate electrode. ), and a voltage applied to the oxide semiconductor film 112 functioning as a second gate electrode (hereinafter, The backgate voltage (Vbg) is -15V to +20V, with a range of 0.25V. The voltage applied to the conductive film 120a functioning as the source electrode was (Hereinafter, also referred to as source voltage (Vs)) is set to 0V (comm), and the The voltage applied to the conductive film 120b (hereinafter, also referred to as drain voltage (Vd)) is set to 1 V. and 10 V. However, for a transistor with a W / L=50 μm / 1.5 μm size, In this case, Vg and Vbg were set to −15V to +15V.

[0451] As shown in FIG. 33(A), (B), and (C), the sample A1 fabricated in this embodiment has a channel length of It was shown that the electrical properties were good regardless of the length of (L).

[0452] Next, the cross section of the transistor with W / L=50μm / 2.0μm size was observed. The cross-sectional observation results of the transistor are shown in Figure 34 (A) and (B). The observation was made using a transmission electron microscope (TEM). A microscope was used.

[0453] FIG. 34(A) corresponds to a cross section taken along the dashed line X1-X2 shown in FIG. 7(A). 34(B) corresponds to a cross section taken along dashed line Y1-Y2 shown in FIG. 7(A).

[0454] As shown in Figs. 34(A) and (B), the sample A1 produced in this example has a good cross-sectional shape. there were.

[0455] The configurations and methods shown in the present embodiment may be the same as those shown in other embodiments or modes. The method can be used in combination with other methods. EXAMPLES

[0456] In this example, a transistor corresponding to the transistor 100A shown in FIG. The evaluation included the electrical characteristics of the transistor and the The reliability test was carried out as follows.

[0457] In this embodiment, a transistor corresponding to the transistor 100A shown in FIG. Samples B1 to B3 were fabricated as samples in which the transistor size of Sample B1 was The channel length L is 3 μm, the channel width W is 50 μm, and the transistor size of sample B2 is The channel length L was 2 μm and the channel width W was 50 μm. The channel length L was set to 1.5 μm and the channel width W was set to 3 μm.

[0458] For comparison with sample B1, sample C in which a comparative transistor 300A is formed is used. The structure of a comparative transistor 300A is shown in FIGS. vinegar.

[0459] The transistor 100A shown in FIG. 3 has a staggered transistor structure, whereas the The transistor 300A for use in the power supply has an inverted staggered transistor structure.

[0460] FIG. 35(A) is a top view of a transistor 300A, and FIG. 35(B) is a top view of a transistor 300B. 35(C) corresponds to a cross-sectional view taken along the dashed line X1-X2 shown in FIG. 5(A) along dashed line Y1-Y2.

[0461] The transistor 300A includes a conductive film 300A on a substrate 302, the conductive film 300A serving as a first gate electrode. 4, an insulating film 306 on the substrate 302 and the conductive film 304, and an insulating film 307 on the insulating film 306. The oxide semiconductor film 308 over the insulating film 307 and the insulating film 308 electrically connected to the oxide semiconductor film 308 are The conductive film 312 a serving as a source electrode is electrically connected to the oxide semiconductor film 308. the conductive film 312b serving as a drain electrode connected to the oxide semiconductor film 308, and the conductive film 312b serving as a drain electrode connected to the oxide semiconductor film 308. An insulating film 314 on the films 312a and 312b, an insulating film 316 on the insulating film 314, and an insulating film 3 16 and a conductive film 320 on the insulating film 318. The conductive film 308 is a film including an oxide semiconductor film 308_2 and an oxide semiconductor film on the oxide semiconductor film 308_2. A laminated structure with a conductive film 308_3 was formed.

[0462] In the transistor 300A, the insulating films 314, 316, and 318 are the second gate insulating films. It functions as an insulating film.

[0463] In the transistor 300A, the conductive film 320 is a second gate electrode (backgate As shown in FIG. 35(C), the conductive film 320 functions as an insulating film. An opening 341 is provided in the insulating films 306 and 307, and an insulating film 314, 316, and 318 is provided In the opening 342, a conductive film 312c is formed through the opening 342. Therefore, the conductive film 320 and the conductive film 304 are applied with the same potential. The transistor 300A has the S-channel structure described above. .

[0464] The transistor size of sample C1 is a channel length L of 3 μm and a channel width W of 50 In this embodiment, the samples B1 to B3 and the sample C1 each have a thickness of 1 μm. , 10 transistors were formed.

[0465] <2-1. Method for preparing samples B1 to B3> A method for manufacturing the samples B1 to B3 used in this embodiment will be described below. In the description, the same structure as that of the transistor 100A shown in FIGS. The configuration will be described using the same reference numerals.

[0466] First, a substrate 102 was prepared. A glass substrate was used as the substrate 102. Next, A conductive film 106 was formed on the conductive film 102. The conductive film 106 was a tungsten film having a thickness of 100 nm. The TEN film was formed using a sputtering device.

[0467] Next, an insulating film 104 was formed on the substrate 102 and the conductive film 106. In the insulating film 104, the insulating film 104_1, the insulating film 104_2, and the insulating film 104 The insulating film 104_3 and the insulating film 104_4 are successively formed in vacuum in this order using a PECVD apparatus. The insulating film 104_1 was a silicon nitride film having a thickness of 50 nm. The insulating film 104_2 is a silicon nitride film having a thickness of 300 nm. The insulating film 104_3 is a silicon nitride film having a thickness of 50 nm. The silicon oxynitride film was 50 nm thick.

[0468] Next, an oxide semiconductor film is formed over the insulating film 104 and processed into an island shape. The oxide semiconductor film 108 was formed by depositing a 40 The oxide semiconductor film 108 was formed using a sputtering method. Using a sputtering device, metal oxide with an atomic ratio of In:Ga:Zn=4:2:4.1 was sputtered. A ring target was used, and an AC power source was used as the power source applied to the sputtering target. The oxide semiconductor film 108 was processed by a wet etching method. Ta.

[0469] Next, an insulating film that will become the insulating film 110 later is formed over the insulating film 104 and the oxide semiconductor film 108. The insulating film was formed by a 30-nm-thick silicon oxynitride film and a 100-nm-thick silicon oxide film. A silicon oxynitride film with a thickness of 10 nm and a silicon oxynitride film with a thickness of 20 nm were deposited on the silicon oxynitride film using a PECVD apparatus. The layers were then successively formed in a vacuum.

[0470] Next, a heat treatment was performed. The heat treatment was performed at 350° C. for 1 hour in a nitrogen atmosphere. The treatment was carried out.

[0471] Next, the opening 143 was formed. The opening 143 was processed by dry etching. Ta.

[0472] Next, an oxide semiconductor film is formed over the insulating film and processed into an island shape. The oxide semiconductor film 112 was formed with a thickness of 100 nm. The oxide semiconductor film 112 had the composition described above. The oxide semiconductor film 112 was formed in the same manner as the oxide semiconductor film 108. By processing the insulating film 110, an island shape was formed.

[0473] Note that the oxide semiconductor film 112 is processed by a wet etching method, and the insulating film 110 The dry etching method was used for processing.

[0474] Next, the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the oxide semiconductor film 11 The impurity element was added from the top of the substrate. The impurity element used was argon.

[0475] Next, an insulating film 1 is formed over the insulating film 104, the oxide semiconductor film 108, and the oxide semiconductor film 112. The insulating film 116 is a silicon nitride film having a thickness of 100 nm, which is formed by PECV. The film was formed using the D apparatus.

[0476] Next, an insulating film 118 was formed on the insulating film 116. The insulating film 118 had a thickness of 300 mm. A silicon oxynitride film with a thickness of 1 nm was formed using a PECVD apparatus.

[0477] Next, a mask is formed on the insulating film 118, and the insulating films 116 and 118 are The openings 141a and 141b were formed in the substrate 141. A light etching apparatus was used.

[0478] Next, a conductive film is formed on the insulating film 118 so as to fill the openings 141a and 141b. The conductive film was processed into island shapes to form conductive films 120a and 120b.

[0479] The conductive films 120a and 120b are made of a titanium film having a thickness of 50 nm and an alumina film having a thickness of 400 nm. The aluminum film and the titanium film with a thickness of 100 nm were continuously deposited in a vacuum using a sputtering device. It was subsequently formed.

[0480] Next, a heat treatment was performed. The heat treatment was performed at 250° C. for 1 hour in a nitrogen atmosphere. The treatment was carried out.

[0481] Through the above steps, samples B1 to B3 were fabricated.

[0482] <2-2. Preparation method of sample C1> Next, a method for producing the sample C1 used in this embodiment will be described below.

[0483] First, a substrate 302 was prepared. A glass substrate was used as the substrate 302. Next, A conductive film 304 was formed on the conductive film 302. The conductive film 304 was a tungsten film having a thickness of 100 nm. The TEN film was formed using a sputtering device.

[0484] Next, insulating films 306 and 307 were formed on the substrate 302 and the conductive film 304. In the embodiment, the insulating film 306 includes a first insulating film, a second insulating film, and a third insulating film. The first insulating film and the second insulating film were formed successively in a vacuum in this order using a PECVD apparatus. The first insulating film was a silicon nitride film with a thickness of 50 nm. The third insulating film was a silicon nitride film with a thickness of 50 nm. The insulating film 307 was a silicon oxynitride film having a thickness of 50 nm. .

[0485] Next, an oxide semiconductor film is formed over the insulating film 307 and processed into an island shape. The oxide semiconductor film 308 was formed by depositing a 100% SiO 2 thin film of The oxide semiconductor film 308_2 having a thickness of 10 nm and the oxide semiconductor film 308_3 having a thickness of 15 nm are stacked together. Note that the oxide semiconductor film 308_2 was formed by a sputtering apparatus. The metal oxide with the atomic ratio of In:Ga:Zn=4:2:4.1 was used as the sputtering target. The power source applied to the sputtering target was an AC power source. The oxide semiconductor film 308_3 was formed by a sputtering apparatus using In:Ga: A metal oxide with an atomic ratio of Zn=1:1:1.2 was used as a sputtering target. The power applied to the sputtering target was an AC power source. The semiconductor film 308 was processed by wet etching.

[0486] Next, an opening 341 was formed in the insulating film 306 and the insulating film 307. was processed using a dry etching device.

[0487] Next, a conductive film is formed over the insulating film 307 and the oxide semiconductor film 308. The conductive films 312a and 312b were formed by processing the conductive film 312a into a shape similar to that of the conductive film 312b. , 312c is a tungsten film with a thickness of 50 nm, An aluminum film having a thickness of 400 nm and a titanium film having a thickness of 100 nm were laminated in this order.

[0488] Next, the surface (back channel side) of the oxide semiconductor film 308 was cleaned. Using a spin cleaning device, phosphoric acid (concentration 85% by volume) was diluted 1 / 100 with water. The phosphoric acid solution was applied from above the oxide semiconductor film 308 and the conductive films 312a and 312b. The cleaning time was 15 seconds.

[0489] Next, insulating films 314 and 316 are formed over the oxide semiconductor film 308 and the conductive films 312a and 312b. As the insulating film 314, a silicon oxynitride film having a thickness of 40 nm was formed by PECV. The insulating film 316 was formed by using a silicon oxynitride film having a thickness of 400 nm. The SiO2 film was formed using a PECVD apparatus.

[0490] Next, a heat treatment was performed. The heat treatment was performed at 350° C. for 1 hour in a nitrogen atmosphere. The treatment was carried out.

[0491] Next, a 5 nm thick ITSO film is formed on the insulating film 316 using a sputtering device. Subsequently, the oxide semiconductor film 308 and the insulating films 306 and 307 were formed through the ITSO film. The oxygen addition treatment was carried out on the substrate 7 using an ashing device. The temperature was set to 40°C, oxygen gas was introduced into the chamber at a flow rate of 250 sccm, and the pressure was set to 15 Pa. The parallel plate was set in the ashing device so that a bias was applied to the substrate side. An RF power of 4500 W was supplied between the electrodes for 120 seconds.

[0492] Next, the ITSO film was removed to expose the insulating film 316. The etching was performed using a wet etching device with a 5% oxalic acid solution for 300 seconds. After etching, 0.5% hydrofluoric acid was used for 15 seconds. We conducted a survey.

[0493] Next, an insulating film 318 was formed on the insulating film 316. The insulating film 318 had a thickness of 100 A silicon nitride film with a thickness of 1 nm was formed using a PECVD apparatus.

[0494] Next, an opening 342 was formed down to the conductive film 312c. The wafer was processed using an etching device.

[0495] Next, a desired position on the conductive film 312c and the insulating film 318 is coated with a A conductive film was formed to form the conductive film 320. The conductive film 320 had a thickness of 100 mm. A 100 nm thick ITSO film was formed using a sputtering system.

[0496] Next, a heat treatment was performed at 250° C. for 1 hour in a nitrogen atmosphere. .

[0497] Through the above steps, a comparative sample C1 was prepared.

[0498] <2-3. Electrical characteristics of transistors> The drain current-gate voltage (Id The Id-Vg characteristics of the transistor of sample C1 and the Id-Vg characteristics of the transistor of sample C2 are shown in FIGS. FIG 36 shows the characteristics of the transistor of Sample B1, and FIG 37 shows the characteristics of the transistor of Sample B2. FIG. 37 shows the results of the transistor characteristics of sample B3. FIG. 39 shows the characteristics of the transistor of sample B1, and FIG. 40 shows the characteristics of the transistor of sample C1. FIG. 39 shows the characteristics of the Id-Vg characteristic shown in FIG. 36 with the field effect transfer. In addition, in Figs. 36 to 40, a total of 10 tracks are displayed. The data from the two sensors are shown overlaid on each other.

[0499] 36 to 38, the vertical axis represents Id [A] and the horizontal axis represents Vg [V]. 39 and 40, the first vertical axis represents Id [A] and the second vertical axis represents the field effect transfer degree(μFE[cm 2 / Vs]) and the horizontal axis represents Vg [V].

[0500] In addition, in the sample B1, the Id-Vg characteristics of the transistor were measured under the following conditions: A voltage (hereinafter, referred to as back gate) applied to the conductive film 106 functioning as the first gate electrode of the transistor is a gate voltage (Vbg) and an oxide semiconductor film 1 serving as a second gate electrode. The voltage applied to 12 (hereinafter referred to as the gate voltage (Vg)) is -15V to +2 The voltage was applied in steps of 0.25 V down to 0 V. In addition, in sample B2, the I The measurement conditions for the d-Vg characteristics are the back gate voltage (Vbg) and the gate voltage (Vg ) was applied in steps of 0.25 V from -15 V to +15 V. In 3, the measurement conditions for the Id-Vg characteristics of the transistor are the back gate voltage (V bg), and the gate voltage (Vg) is from -15V to +10V in 0.25V steps. In addition, the measurement conditions for the Id-Vg characteristics of the transistor in sample C1 were Specifically, the voltage ( A gate voltage (Vg) and a conductive film 32 serving as a second gate electrode of the transistor The voltage applied to 0 (backgate voltage (Vbg)) can range from -15V to +15V. The voltage was applied in steps of 0.25 V.

[0501] In the samples B1 to B3 and C1, the conductive film (conductive film 120a or the conductive film 312a) (hereinafter, also referred to as source voltage (Vs) ) is set to 0 V (comm), and the conductive film (conductive film 120b, The voltage applied to the conductive film 312b (hereinafter also referred to as drain voltage (Vd)) is set to 0.1 V and 20V.

[0502] 36 to 38, the transistor of one embodiment of the present invention has a channel length of 1 Even when the thickness was shortened to 0.5 μm, the device was normally off. In addition, there was little variation within the substrate surface. The result was confirmed.

[0503] From the results shown in FIG. 39 and FIG. 40, in both the transistors of Sample B1 and Sample C1, Effective mobility is 30cm 2 / Vs, when comparing sample B1 and sample C1. However, the field-effect mobility of Sample B1, which is one embodiment of the present invention, was higher.

[0504] <2-5. Constant current stress test> Next, a constant current stress test was performed on the samples B1 and C1 prepared above. The constant current stress test was carried out in an air atmosphere in a dark state.

[0505] The Id-Vg characteristics were measured at drain voltages of 0.1 V and 10 V, and at gate voltages The drain current was measured when the voltage was swept from -15V to 15V.

[0506] In the constant current stress test for sample B1, the board temperature was set to room temperature and the first Id-V The g characteristic and Id-Vd characteristic were measured. After that, the substrate temperature was set to 60°C, and the source The potential is set to ground potential (GND), the drain potential is set to 10V, and the gate potential is set to 1.88V. After that, the second measurement of the Id-Vg characteristics and the Id-Vd characteristics was carried out.

[0507] In the constant current stress test of sample C1, the board temperature was set to room temperature and the first I The d-Vg and Id-Vd characteristics were measured. After that, the substrate temperature was set to 60°C. The source potential is set to ground potential (GND), the drain potential is set to 10V, and the gate potential is set to 1.99V. The device was then held for 24 hours. After that, the second Id-Vg and Id-Vd characteristics were measured. I did.

[0508] Figure 41 (A), (B), and (C) show the results of the constant current stress test for samples B1 and C1. FIG. 41(A) shows the drain current ( FIG. 41(B) is a graph showing the change rate of Id of sample B1 before and after the stress test. FIG. 41(C) shows the Id-Vg characteristics of sample B1 before and after the stress test. This is the Vd characteristic result.

[0509] In FIG. 41(A), the black solid line indicates the measurement result of sample B1, and the gray solid line indicates The measurement results of sample C1. In FIG. 41B, the solid line indicates the state before the stress test, and the dashed line indicates the state before the stress test. The Id-Vg characteristic results after the stress test are shown in FIG. 41(C). The dashed line shows the Id-Vd characteristics before the stress test, and the dashed line shows the Id-Vd characteristics after the stress test.

[0510] 41A, 41B, and 41C show that sample B1 of one embodiment of the present invention has a low thermal conductivity before and after the stress test. It can be seen that the change in drain current is small. It has been shown that semiconductor devices having such a stator have high reliability.

[0511] The configurations and methods shown in the present embodiment may be the same as those shown in other embodiments or modes. The method can be used in combination with other methods. EXAMPLES

[0512] In this example, a sample D1 in which a transistor of one embodiment of the present invention was formed was manufactured. The cross-sectional shape of sample D1 was observed.

[0513] <3-1. Cross-sectional observation> As the sample D1, a transistor corresponding to the transistor 100A shown in FIG. The transistor size of sample D1 was 100 μm in length, 100 μm in width, and 100 μm in height. The dimensions L was 2 μm and the channel width W was 50 μm.

[0514] The structure of the sample D1 will be described below using the reference numerals of the transistor 100A shown in FIG. Reveal.

[0515] The conductive film 106 was formed by a sputtering apparatus using a tantalum nitride film having a thickness of 10 nm. A laminated film was formed with a copper film having a thickness of 100 nm. Using this device, a silicon nitride oxide film with a thickness of 400 nm and a silicon oxynitride film with a thickness of 50 nm were In addition, a 40-nm-thick In-Ga-Z oxide semiconductor film was formed as the oxide semiconductor film 108. The In-Ga-Zn oxide was formed using a sputtering device. Using this, metal oxide with an atomic ratio of In:Ga:Zn=1:1:1.2 was sputtered. The target is a sputtering target, and an AC power source is used as the power source applied to the sputtering target. In addition, a PECVD apparatus was used to form an oxide film having a thickness of 100 nm as the insulating film 110. A silicon nitride film was formed as the oxide semiconductor film 112 using a sputtering apparatus. Using this, an In-Ga-Zn oxide having a thickness of 100 nm was formed. Zn oxide was prepared by sputtering with In:Ga:Zn=4:2:4.1[ A metal oxide having a ratio of 1 to 10 atomic percent is used as a sputtering target. The power source applied to the insulating film 116 was an AC power source. A silicon nitride film having a thickness of 100 nm was formed using a VD apparatus. Then, a silicon oxynitride film having a thickness of 400 nm was formed using a PECVD apparatus. The conductive films 120a and 120b were formed by depositing a copper alloy film having a thickness of 50 nm using a sputtering device. A (Cu-Mn) film and a copper film having a thickness of 100 nm were formed.

[0516] In addition, in the sample D1, an insulating film was formed on the insulating film 118 and the conductive films 120a and 120b. As the film 158, an acrylic resin film having a thickness of 1.5 μm was formed.

[0517] The cross-sectional observation result of the sample D1 prepared as above is shown in FIG. 42. As shown in FIG. It was confirmed that the fabricated sample D1 had a good cross-sectional shape. In particular, the channel length L was 2. The conductive film 106 serving as the first gate electrode and the conductive film 107 serving as the source electrode and the drain electrode are Since the distance between the conductive films 120a and 120b functioning as the in-electrodes is long, the parasitic capacitance is This suggests that it is small.

[0518] The configuration shown in this embodiment may be appropriately combined with the configurations shown in other embodiments or modes. It can be used in combination. [Explanation of symbols]

[0519] 100 transistors 100A Transistor 100B Transistor 100C transistor 100D Transistor 100E Transistor 100F transistor 100G Transistor 102 Substrate 104 Insulating film 104_1 Insulating film 104_2 Insulating film 104_3 Insulating film 104_4 Insulating film 106 Conductive Film 107 Oxide Semiconductor Film 108 Oxide semiconductor film 108_1 Oxide semiconductor film 108_2 Oxide semiconductor film 108_3 Oxide semiconductor film 108d Drain region 108f area 108i Channel Area 108s Source Area 110 Insulating film 110_0 Insulating film 112 Oxide semiconductor film 112_0 Oxide semiconductor film 114 Conductive Film 116 Insulating film 118 Insulating film 120 Conductive Film 120a Conductive film 120b Conductive film 122 Insulating film 140 Mask 141a opening 141b opening 143 Opening 145 Impurity elements 147 Hollow area 150 Transistors 150A Transistor 150B Transistor 158 Insulating film 300A Transistor 302 Substrate 304 Conductive film 306 Insulating film 307 Insulating Film 308 Oxide Semiconductor Film 308_2 Oxide semiconductor film 308_3 Oxide semiconductor film 312a Conductive film 312b Conductive film 312c conductive film 314 Insulating film 316 Insulating Film 318 Insulating Film 320 Conductive Film 341 Opening 342 Opening 501 Pixel circuit 502 Pixel section 504 Drive circuit section 504a Gate Driver 504b source driver 506 Protection circuit 507 Terminal section 550 Transistor 552 Transistor 554 Transistor 560 Capacitive element 562 Capacitive element 570 Liquid crystal element 572 Light emitting element 700 Display device 701 Substrate 702 Pixel section 704 Source driver circuit section 705 Substrate 706 Gate driver circuit section 708 FPC terminal section 710 Signal Line 711 Wiring section 712 Sealing material 716 FPC 730 Insulating film 732 Sealing film 734 Insulating film 736 Colored film 738 Light-shielding film 750 Transistors 752 Transistor 760 Connection electrode 770 Planarizing Insulating Film 772 Conductive Film 774 Conductive Film 775 Liquid crystal elements 776 Liquid crystal layer 778 Structure 780 Anisotropic Conductive Film 782 Light emitting element 784 Conductive Film 786 EL layer 788 Conductive Film 790 Capacitive element 1280a p-type transistor 1280b n-type transistor 1280c n-type transistor 1281 Capacitive element 1282 Transistor 1311 Wiring 1312 Wiring 1313 Wiring 1314 Wiring 1315 Wiring 1316 Wiring 1317 Wiring 1351 Transistor 1352 Transistor 1353 Transistor 1354 Transistor 1360 Photoelectric conversion element 1401 Signal 1402 Signal 1403 Signal 1404 Signal 1405 Signal 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery 9000 Chassis 9001 Display section 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Television equipment 9101 Portable information terminal 9102 Portable information terminal 9200 Mobile Information Terminal 9201 Portable information terminals

Claims

[Claim 1] A semiconductor device having a transistor, The transistor is a first oxide semiconductor film on a first insulating film; a gate insulating film on the first oxide semiconductor film; a second oxide semiconductor film on the gate insulating film; a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film; The first oxide semiconductor film is a channel region in contact with the gate insulating film; a source region in contact with the second insulating film; a drain region in contact with the second insulating film, The second oxide semiconductor film is The semiconductor device further comprises a first oxide semiconductor film having a higher carrier density than the first oxide semiconductor film.

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