Semiconductor device

Abstract

To provide a semiconductor device having an excellent electric characteristic or a semiconductor device having a stable electric characteristic.SOLUTION: A semiconductor device comprises a first transistor, a second transistor, a first insulator, a second insulator, a first wiring, and a first plug. The first transistor has silicon, the second transistor has an oxide semiconductor, the first insulator is positioned on the first transistor, the second insulator is positioned on the first insulator, the second transistor is positioned on the second insulator, the first wiring is positioned on the second insulator and the first plug, the first transistor and the second transistor are electrically connected through the first wiring and the first plug, the first wiring has a low hydrogen permeability, and the second insulator has a lower hydrogen permeability than the first insulator.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. In particular, the term "composition of matter" refers to a process, manufacture, or composition of matter. The present invention relates to, for example, an electrode, a device, a semiconductor, a semiconductor device, a display device, a light-emitting device, and a lighting device. , storage device, mirror device, memory device or processor. A semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, a mirror device, a memory device or a process The present invention also relates to a method for manufacturing a semiconductor device, a display device, a light-emitting device, a lighting device, The present invention relates to a method for driving a power storage device, a mirror image device, a storage device, or a processor.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic The device may include semiconductor devices. [Background technology]

[0003] The technology of constructing transistors using semiconductor materials is attracting attention. Electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices) Silicon-based semiconductor materials are widely used as semiconductor materials that can be used in transistors. are widely known, but oxide semiconductors are attracting attention as another material.

[0004] In recent years, miniaturized transistors have become more common as electronic devices become more powerful, smaller, and lighter. 2. Description of the Related Art There is an increasing demand for integrated circuits in which semiconductor elements such as transistors are densely integrated.

[0005] Here, a transistor including an oxide semiconductor has a very low leakage current in a non-conducting state. For example, the leakage current of a transistor using an oxide semiconductor is known to be small. A low-power CPU that utilizes the low current characteristic has been disclosed (see Patent Document 1). Light. ). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2012-257187 A Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device having excellent electrical characteristics. Another embodiment of the present invention is to provide a semiconductor device having stable electrical characteristics. Another object of the present invention is to provide a method for embedding a conductor in an insulator. Another object of one embodiment of the present invention is to provide a miniaturized semiconductor device. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with high yield. One of the goals of the project is to

[0008] Another object of one embodiment of the present invention is to provide a method for manufacturing a miniaturized semiconductor device. Another embodiment of the present invention is to provide a method for manufacturing a highly reliable device. Another object of the present invention is to provide a method for manufacturing a device with high yield. One of the challenges we face is to

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0010] One aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulator, and The first transistor includes a second insulator, a first wiring, and a first plug. the first transistor has an oxide semiconductor; and the first insulator is a second insulator disposed on the first insulator; and a second transistor disposed on the first insulator. , the first wiring is located on the second insulator and on the first plug The first transistor and the second transistor are connected to each other through the first wiring and the first plug. The first wiring has low hydrogen permeability, and the second insulator is electrically connected to the first insulator. This semiconductor device has comparatively low hydrogen permeability.

[0011] Alternatively, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first insulator. a first transistor having an insulating layer, a second insulating layer, a first wiring, and a first plug; the first transistor includes silicon, the second transistor includes an oxide semiconductor, and the first insulator includes a a first insulator disposed on the first transistor and a second insulator disposed on the first insulator and a second insulator disposed on the second transistor; The resistor is located on the second insulator, and the first wiring is located on the second insulator and the first plug. The first transistor and the second transistor are connected to the first wiring and the first plug. The first wiring and the first plug are electrically connected via a plug having low hydrogen permeability. The second insulator is a semiconductor device having a lower hydrogen permeability than the first insulator.

[0012] In the above structure, the first wiring preferably contains tantalum nitride. In the above structure, the first plug preferably contains tantalum nitride. In the above configuration, at least one of the first wiring and the first plug has low copper permeability. It is preferable.

[0013] In the above structure, at least one of the first wiring and the first plug is made of nitride. It is preferable that the insulating layer has a structure in which titanium nitride and tantalum are laminated. It is preferable that the tantalum layer has a laminated structure.

[0014] In the above structure, the second insulator is made of aluminum oxide and hafnium oxide. It is preferable to have at least one of them.

[0015] Another embodiment of the present invention is an electronic device including any one of the above-described semiconductor devices. It is a vessel. Effect of the Invention

[0016] According to one embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device having stable electrical characteristics can be provided. According to another aspect of the present invention, a method for embedding a conductor in an insulator can be provided. According to one embodiment of the present invention, a miniaturized semiconductor device can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with high yield can be provided.

[0017] According to one embodiment of the present invention, a method for manufacturing a miniaturized semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a highly reliable device can be provided. According to one embodiment of the present invention, a method for manufacturing a device with high yield can be provided. do.

[0018] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these are described in the specification. The above will become apparent from the description, drawings, claims, etc. From the above description, it is possible to extract other effects. [Brief description of the drawings]

[0019] [Figure 1] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Diagram 2] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Diagram 3] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Diagram 5] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor according to one embodiment of the present invention. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor according to one embodiment of the present invention. [Figure 7] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor according to one embodiment of the present invention. [Figure 8]FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 9] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 10] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 11] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 13] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 15] FIG. 1 is a cross-sectional view illustrating an example of a capacitor according to one embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 23] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 24] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 25] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 26] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 27] FIG. 1 is a circuit diagram according to one embodiment of the present invention. [Figure 28] FIG. 1 is a circuit diagram according to one embodiment of the present invention. [Figure 29] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Diagram 30] FIG. 1 is a top view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Diagram 31] FIG. 1 is a top view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Diagram 32] FIG. 1 is a perspective view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Diagram 33] FIG. 1 is a top view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Diagram 34] FIG. 1 is a cross-sectional view illustrating an example of a transistor according to one embodiment of the present invention. [Diagram 35] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Diagram 36] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 37] FIG. 1 is a band diagram of a region including an oxide semiconductor according to one embodiment of the present invention. [Figure 38] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor according to one embodiment of the present invention. [Figure 39] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor according to one embodiment of the present invention. [Diagram 40] FIG. 1 is a cross-sectional view illustrating an example of a transistor according to one embodiment of the present invention. [Diagram 41] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor according to one embodiment of the present invention. [Diagram 42] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor according to one embodiment of the present invention. [Diagram 43] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor according to one embodiment of the present invention. [Diagram 44] FIG. 1 is a cross-sectional view illustrating an example of a transistor according to one embodiment of the present invention. [Diagram 45]Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 46] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 47] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 48] Electron diffraction pattern of CAAC-OS. [Figure 49] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 50] 3 shows an example of the configuration of a CPU according to the embodiment. [Figure 51] 1 is a circuit diagram of a memory element according to an embodiment. [Figure 52] 3 shows an example of the configuration of an RF tag according to the embodiment. [Diagram 53] 1 shows an example of how an RF tag is used according to an embodiment. [Figure 54] 1A and 1B are a top view and a circuit diagram of a display device according to an embodiment. [Figure 55] 1A to 1C are diagrams illustrating examples of electronic devices. [Figure 56] FIG. 1 illustrates an example of an imaging apparatus. [Figure 57] FIG. 1 illustrates an example of an imaging apparatus. [Figure 58] FIG. 1 illustrates an example of an imaging apparatus. [Figure 59] 1A to 1C are diagrams illustrating an example of the configuration of a pixel. [Figure 60] 1A to 1C are diagrams illustrating an example of the configuration of a pixel. [Figure 61] FIG. 1 is a circuit diagram showing an example of an imaging device. [Figure 62] FIG. 1 is a cross-sectional view showing an example of the configuration of an imaging apparatus. [Figure 63] FIG. 1 is a cross-sectional view showing an example of the configuration of an imaging apparatus. [Figure 64] TDS analysis results. [Figure 65] SIMS analysis results. [Figure 66] SIMS analysis results. [Figure 67] An example of a CPU layout. [Figure 68] 1 is an example of a layout of a storage device. [Figure 69] 1 shows an example of a layout of an imaging device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The present invention will be described in detail with reference to the drawings. The present invention is not limited to the description, and various modifications in form and details are possible. In addition, the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same reference numerals are used It is used commonly across different drawings. Note that when referring to similar objects, the hatch pattern is used in the same way. In some cases, no particular reference numeral may be used. When referring to the description of components with different reference numerals, In this case, descriptions of the thickness, composition, structure, shape, etc. of the referenced components are used as appropriate. It is possible.

[0021] In the figures, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where this is the case.

[0022] Also, a voltage is a voltage between a certain potential and a reference potential (such as ground potential (GND) or source potential). Therefore, voltage can be replaced with electric potential. In general, potential (voltage) is relative, and the magnitude is relative to a reference potential. Therefore, even if it is described as "ground potential", The potential is not necessarily 0V. For example, the lowest potential in a circuit may be the "ground potential." In some cases, the intermediate potential in the circuit may be the "ground potential." In this case, the positive potential and the negative potential are defined based on that potential.

[0023] The ordinal numbers 1 and 2 are used for convenience and do not indicate the order of processes or stacking. It does not indicate the layer order. Therefore, for example, "first" should not be changed to "second" or "third" In addition, the ordinal numbers described in this specification and the like can be appropriately replaced with the ordinal numbers. In some cases, the term may not match the ordinal number used to identify an aspect of the invention.

[0024] The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor. Elements present at less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of States) in the conductor and carrier migration In some cases, the mobility and crystallinity of the semiconductor may decrease. In the case of semiconductors, impurities that change the properties of the semiconductor include, for example, group 1 elements, There are elements from Group 2, Group 13, Group 14, Group 15, and transition metals other than the main component. In particular, hydrogen (which is also contained in water), lithium, sodium, silicon, and boron In the case of oxide semiconductors, for example, impurities such as hydrogen can cause In addition, when the semiconductor is silicon, the characteristics of the semiconductor Impurities that change the properties of the material include, for example, oxygen, elements of Group 1 except hydrogen, elements of Group 2, and elements of Group 3. These include the Group 13 elements and the Group 15 elements.

[0025] In this specification, when it is stated that A has a shape protruding from B, this is a top view. Or in the cross-sectional view, at least one end of A is outside at least one end of B. Therefore, it is written that A has a shape that protrudes more than B. For example, in the top view, one end of A is on the outside of one end of B. This can be read as having the following.

[0026] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to two lines that are arranged at an angle between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0027] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0028] In the present specification, the term "semiconductor" may be read as "oxide semiconductor." Other semiconductors include group 14 semiconductors such as silicon and germanium, silicon carbide, Copper, germanium silicide, gallium arsenide, indium phosphide, zinc selenide, cadmium sulfide Compound semiconductors such as tungsten and organic semiconductors can be used.

[0029] In this specification, the term "device" refers to, for example, a semiconductor device, a display device, a light-emitting device, or a lighting device. It may refer to devices such as power storage devices, mirror devices, storage devices, and electro-optical devices.

[0030] (Embodiment 1) In this embodiment, an example of a semiconductor device of one embodiment of the present invention will be described.

[0031] [Semiconductor Devices] Fig. 1 shows an example of a cross-sectional view of a semiconductor device 500. Fig. 2 shows a cross-sectional view taken along the line A1-A2 shown in Fig. 1. The semiconductor device 500 shown in FIG. The layer 627 includes transistors 491 to 493. Layer 629 includes transistor 490 .

[0032] <layer 627> Layer 627 includes substrate 400 and transistors 491 through 499 on substrate 400. 3, insulator 464 over transistors 491, etc., and plugs such as plug 541. The plugs 541 and the like are, for example, gate electrodes, source electrodes, or drain electrodes of the transistors 491 and the like. The plug 541 is connected to an electrode or the like. The plug 541 is formed so as to be embedded in the insulator 464. is preferred.

[0033] The transistors 491 to 493 will be described in detail later.

[0034] The insulator 464 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitrogen. Silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride Aluminum or the like may be used.

[0035] Insulator 464 is made by sputtering, CVD (thermal CVD, MOCVD, PECVD) The thin film can be formed by a method such as a GaN thin film deposition method, an MBE method, an ALD method, or a PLD method. In particular, when the insulator is formed into a film by a CVD method, preferably a plasma CVD method, the coating property is excellent. In addition, in order to reduce damage caused by plasma, The CVD method, the MOCVD method or the ALD method is preferred.

[0036] The insulator 464 is silicon carbonitride. Silicon oxycarbide, silicon oxycarbide, etc. In addition, USG (Undoped Silicate Glass), BPS G(Boron Phosphorus Silicate Glass), BSG(B orosilicate glass) can be used. USG, BPSG, etc. The film may be formed by atmospheric pressure CVD. For example, HSQ (hydrogen silsesquioxane) may be used. The insulating layer 11 may be formed by using a coating method.

[0037] The insulator 464 may be a single layer or a laminate of multiple materials.

[0038] Here, in FIG. 1, the insulator 464 is shown as an insulator 464a and an insulator 464 on the insulator 464a. An example of two layers, b and c, is shown below.

[0039] The insulator 464a has adhesion to the region 476 of the transistor 491, the conductor 454, etc. Good coverage is preferred.

[0040] An example of the insulator 464a is silicon nitride formed by a CVD method. Here, it may be preferable that the insulator 464a contains hydrogen. By having such a structure, defects in the substrate 400 can be reduced, and the characteristics of the transistors 491, etc. can be improved. For example, when a material containing silicon is used as the substrate 400, Hydrogen can terminate defects such as dangling bonds of silicon.

[0041] Here, the conductor under the insulator 464a, such as the conductor 454, and the insulator 46, such as the conductor 511, It is preferable that the parasitic capacitance formed between the conductor formed on 4b is small. Insulator 464b preferably has a low dielectric constant. It is preferable that the insulator 464b has a lower dielectric constant than the insulator 464a. For example, the relative dielectric constant of the insulator 464b is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 464b is preferably less than the relative dielectric constant of the insulator 464a. It is preferably 0.7 times or less, and more preferably 0.6 times or less.

[0042] As an example, silicon nitride is used for the insulator 464a and USG is used for the insulator 464b. It is possible.

[0043] Here, the insulator 464a, the insulator 581a, etc. are made of silicon nitride or silicon carbonitride. By using a material with low copper permeability, when copper is used for the conductor 511, etc., In some cases, the diffusion of copper into layers above and below the insulators 464a and 581a can be suppressed. .

[0044] As shown in FIG. 3, the conductor 511 is a laminate of the conductor 511a and the conductor 511b. In this case, for example, the insulator 511b is applied from the upper surface of the conductor 511b that is not covered by the conductor 511a. Impurities such as copper may diffuse to the upper layer through the conductor 511b. The upper insulator 584 is preferably made of a material that has low impurity permeability, such as copper. For example, the insulator 584 may be formed by forming an insulator 584a and a metal layer on the insulator 584a as shown in FIG. The insulating layer 584a and the insulating layer 584b are laminated together. See body 581a and insulator 581b.

[0045] <layer 628> Layer 628 includes an insulator 581, an insulator 584 on insulator 581, and an insulator 584 on insulator 584. The insulating member 571 and the insulating member 585 on the insulating member 571 are also provided. A conductor 511, etc., a plug 543 etc. connected to the conductor 511, etc., and a conductor on an insulator 571 The conductor 511 is formed so as to be embedded in the insulator 581. The plugs 543, etc. are shaped to be embedded in the insulators 584 and 571. The conductor 513 is preferably formed so as to be embedded in the insulator 585. It is preferable that

[0046] The layer 628 may also include a conductor 413. The conductor 413 is embedded in an insulator 585. It is preferable that the recess is formed so as to be recessed.

[0047] The insulators 584 and 585 may be, for example, silicon oxide, silicon oxynitride, or nitride. Silicon oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide Aluminum, aluminum nitride, etc. may be used.

[0048] The insulators 584 and 585 are formed by sputtering, CVD (thermal CVD, MO CVD, PECVD, etc.), MBE, ALD, or PLD methods. In particular, the insulator can be formed by a CVD method, preferably a plasma CVD method. It is preferable to form the film by using a plasma because it is possible to improve the coating property. To reduce the size, the thermal CVD method, the MOCVD method, or the ALD method is preferable.

[0049] Also, silicon carbide, silicon carbonitride (silicon carbide nitride) and the like are used as the insulating material 584 and the insulating material 585. silicon oxycarbide rbide) can be used. USG (Undoped Silica TE Glass), BPSG (Boron Phosphorus Silicate) Glass), BSG (Borosilicate Glass), etc. can be used. USG, BPSG, etc. can be formed by using atmospheric pressure CVD. The layer may be formed by coating hydrogen silsesquioxane (SQ) or the like.

[0050] The insulators 584 and 585 may be single layers or may be laminated with a plurality of materials. .

[0051] The insulator 581 may be formed by stacking multiple layers. For example, as shown in FIG. The insulator 581 may be a two-layer insulator, 581a and 581b on the insulator 581a.

[0052] The plug 543 also has a protrusion on the insulator 571 .

[0053] Metal materials, alloys, etc., as the conductor 511, the conductor 513, the conductor 413, the plug 543, etc. Conductive materials such as aluminum or metal oxide materials can be used. Aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, niobium, molybdenum The metals, such as tantalum, silver, tungsten, etc., or alloys with these as the main components, are used. It can be used as a layered structure or a laminated structure. Tungsten nitride, molybdenum nitride, etc. Metal nitrides such as titanium nitride and the like can be used.

[0054] Here, the conductors such as the conductor 511 and the conductor 513 function as wiring of the semiconductor device 500. Therefore, these conductors are sometimes called wiring or wiring layers. Furthermore, these conductors are preferably connected by plugs such as plug 543.

[0055] In the semiconductor device according to one embodiment of the present invention, the conductor 511 and the conductor The conductor 413, the plug 543, etc. may have a laminated structure of two or more layers. 3A. The semiconductor device 500 shown in FIG. In FIG. 3A, detailed description of the layers 627, 630, and 631 is omitted. For example, Please refer to the description of FIG. 1 etc.

[0056] In FIG. 3(A), the area surrounded by the dashed line is shown in FIG. 3(B). In the layer 628, the conductor 511 is a conductor 511a and a conductor 511b formed on the conductor 511a. Similarly, the conductor 513 includes a conductor 513a and a conductor 511b. The conductor 413 has a conductor 413a and a conductor 513b formed on the conductor 413a. The plug 543 has a conductor 413b formed on the conductor 413a. and a plug 543b formed on the plug 543a.

[0057] The conductor 511a is formed along the side of the opening formed in the insulator 581, and the conductor 5 It is preferable that 11b is formed so as to fill the opening covered by the conductor 511a.

[0058] Here, the conductor 511a, the conductor 413a, the conductor 513a, and the plug 54 The lower conductors such as 3a have low permeability to elements contained in the upper conductors such as conductor 511b. For example, it is preferable that the conductor 513a has an element that is different from the element contained in the conductor 513b. It is preferable to suppress the diffusion of the ions to other regions.

[0059] The conductor 511a, the conductor 413a, and the conductors below the conductor 513a are insulated. It is preferable that the conductor, such as the edge 581, has high adhesion to the insulator on which it is formed.

[0060] As an example, consider the case where the upper conductor, such as conductor 511b, comprises copper. Copper has a low resistance. It is small and is preferable to use it as a conductor such as a plug or wiring. On the other hand, copper is easily diffused. However, diffusion into the semiconductor element may deteriorate the characteristics of the semiconductor element. The lower conductors such as 11a are made of materials with low copper permeability, such as tantalum, tantalum nitride, and nitride. Titanium oxide or the like may be used, and tantalum is particularly preferred.

[0061] In addition, the conductor 511a, the conductor 413a, the conductor 513a, the plug 543a, etc. The lower conductor or plug preferably has low hydrogen and water permeability. It is possible to suppress the diffusion of hydrogen and water from the layer 629 to layers above the layer 629. Hydrogen and water contained in 627, etc., diffuses from layer 629 to upper layers through the plug and conductor. Therefore, for example, the deterioration of the characteristics of the transistor 490 can be suppressed. Stable characteristics can be obtained. For example, metal nitrides are used as materials with low hydrogen permeability. In particular, it is more preferable to use tantalum nitride.

[0062] The lower layers of the conductor 511a, the conductor 413a, the conductor 513a, and the plug 543a, etc. The thickness of the conductor is preferably 5 nm to 100 nm, more preferably 10 nm to 7 0 nm or less, and more preferably 20 nm or more and 70 nm or less.

[0063] Here, the conductor 511a, the conductor 413a, the conductor 513a, the plug 543a, etc. The lower layer conductor is, for example, a laminate of a material with low hydrogen permeability and a material with low copper permeability. For example, tantalum nitride and tantalum are preferably laminated together. Alternatively, it is preferable to use a laminate of titanium nitride and tantalum. stomach.

[0064] In addition, the conductor 511a, the conductor 413a, the conductor 513a, the plug 543a, etc. The lower conductor is a first conductive layer made of a material with low hydrogen permeability and a second conductive layer made of a material with low copper permeability. Consider the case where the first conductive layer is formed by laminating the first conductive layer and the second conductive layer made of a thin material. The thickness of the conductive layer is preferably 5 nm to 50 nm, more preferably 10 nm to 50 nm or less, more preferably 10 nm or more and 30 nm or less, and the film thickness of the second conductive layer is Preferably, the thickness is 5 nm or more and 50 nm or less, more preferably, 10 nm or more and 50 nm or less, and Preferably, the thickness is 10 nm or more and 40 nm or less. Here, for example, the second conductive layer is It is preferable that the third conductive layer is disposed on the first conductive layer and the second conductive layer. It may have a conductive layer.

[0065] Here, the conductor 511a, the conductor 413a, the conductor 513a, the plug 543a, etc. The thickness of the lower conductor may be different between the sidewall and the bottom. The thicker of the two thicknesses, or the thickest part of the thickness, is 5 nm or more. For example, a conductive film can be formed by using a collimated sputtering method. In addition, the coating property of the film may be improved, which is preferable. In some cases, the bottom film thickness may be thicker than the sidewall film thickness. The thickness may be 1.5 times or more, or even 2 times or more, the thickness of the sidewall film.

[0066] In addition, the conductor 511a, the conductor 413a, the conductor 513a, the plug 543a, etc. The thickness of the lower conductor may be less than 5 nm. For example, it is preferably 1 nm or more and less than 5 nm. The thickness of the conductor 511a, the conductor 413a, and the like is preferably 2 nm or more and less than 5 nm. The conductor 513a and the conductors under the plug 543a are made of a material having low hydrogen permeability. The first conductive layer is made of a material with low copper permeability, and the second conductive layer is made of a material with low copper permeability. In the case where the first conductive layer and the second conductive layer are formed, each of the first conductive layer and the second conductive layer may be less than 5 nm. For example, the thickness is preferably 1 nm or more and less than 5 nm, and more preferably 2 nm or more and less than 5 nm.

[0067] In addition, materials such as titanium nitride, tantalum nitride, titanium, and tantalum are used as the conductor 511a, the conductor By using the conductive layer 413a and the conductive layer 543a as the conductive layer under the plug 543a, the conductive layer In some cases, the adhesiveness of the insulating material to the opening can be improved.

[0068] Here, the conductors 511a, 413a, and the lower conductors such as the plug 543a are In the case of a laminated film, a layer containing, for example, copper may be formed on the surface side. For example, a nitride layer may be formed on the surface side. It may be a three-layer stack of tantalum, tantalum on tantalum nitride, and copper on tantalum. By forming a layer containing copper as a layer on the surface side of the conductor 511a, for example, When copper is used as the conductor 511b, the adhesion between the conductor 511b and the conductor 511a is improved. This may be the case.

[0069] The description of the insulator 464 may be referred to for the insulator 581. The insulator 581 is a single layer. Alternatively, a plurality of materials may be laminated. In this example, the insulator 581a is an insulator 581b on the insulator 581a. The materials and the formation methods that can be used for the insulator 581b are described in detail below. Please refer to the description of materials and formation methods that can be used for the body 464a and the insulator 464b. It is possible.

[0070] As an example of the insulator 581a, silicon nitride formed by a CVD method can be used. Here, in the semiconductor element of the semiconductor device 500, for example, the transistor 490, However, hydrogen may diffuse into the semiconductor element, resulting in a deterioration in the characteristics of the semiconductor element. Therefore, it is preferable to use a film that releases less hydrogen as the insulator 581a. The amount of desorption can be measured, for example, by thermal desorption spectrometry (TDS). The water in the insulator 581a can be analyzed using a method such as spectroscopy. The amount of desorption of oxygen was measured by TDS analysis in the range of 50°C to 500°C. The calculated amount of desorption is, for example, 5 × 10 20 atoms / cm 3 Less than or equal to 1×10 20 a toms / cm 3 Alternatively, the amount of desorption of the insulator 581a converted into hydrogen atoms is , for example, 5 × 10 per insulating film area 15 atoms / cm 2 Below, preferably 1×1 0 15 atoms / cm 2 The following is acceptable.

[0071] Moreover, it is preferable that the insulator 581b has a lower dielectric constant than the insulator 581a. For example, The relative dielectric constant of the insulator 581b is preferably less than 4, and more preferably less than 3. The relative dielectric constant of the insulator 581b is preferably 0.7 times or less the relative dielectric constant of the insulator 581a, and is preferably 0. Six times or less is more preferable.

[0072] The insulator 571 is preferably formed using an insulating material that has low impurity permeability. For example, it is preferable that the insulator 571 has low oxygen permeability. It is preferable that the insulator 571 has low hydrogen permeability. Also, for example, the insulator 571 has low water permeability. is preferred.

[0073] The insulator 571 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, or Zirconium, lead zirconate titanate (PZT), strontium titanate (SrTiO 3) Or (Ba,Sr)TiO3 (BST), silicon nitride, etc. are used in a single layer or multilayer. Alternatively, these insulators may be made of, for example, aluminum oxide, bismuth oxide, or Germanium, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide Sodium oxide, zirconium oxide, or gallium oxide may be added. The above insulator may be treated with a silicon oxide, a silicon oxynitride, or the like. In particular, aluminum oxide has high resistance to water and hydrogen. This is preferred because of its excellent barrier properties.

[0074] The insulator 571 may be, for example, silicon carbide, silicon carbonitride, or silicon carbide oxide. etc. may also be used.

[0075] Insulator 571 is made of layers of material with low water and hydrogen permeability, as well as layers containing other insulating materials. For example, a layer containing silicon oxide or silicon oxynitride, a layer containing metal oxide, A layer containing a fluorine compound may be laminated.

[0076] For example, the semiconductor device 500 includes an insulator 571, so that the conductor 513, The elements contained in the conductor 413, etc. are mixed with the insulator 571 and the layers thereunder (insulator 584, insulator 5 81, layer 627, etc.) can be suppressed.

[0077] Here, when the dielectric constant of the insulator 571 is higher than that of the insulator 584, the thickness of the insulator 571 is It is preferable that the relative dielectric constant of the insulator 584 is smaller than the film thickness of the insulator 584. For example, the relative dielectric constant of the insulator 571 is preferably 0.7 times or less, more preferably 0.6 times or less. For example, the thickness of the insulator 571 is preferably 5 nm or more and 200 nm or less. The thickness of the insulator 584 is preferably 30 nm or more. The thickness is preferably at least 800 nm, more preferably at least 50 nm and at most 500 nm. The thickness of the edge 571 is preferably one third or less of the thickness of the insulator 584 .

[0078] FIG. 4 is a cross-sectional view showing some of the components of the semiconductor device 500. In FIG. 4b, a plug 541 formed to be embedded in the insulator 464b, and the insulator 464 b, the conductor 511 on the plug 541 and the insulator 464b, and the insulator 581 on the insulator 584, and the insulator 571 on the insulator 584, and the insulator 584 and the insulator A plug 543 is formed so as to be embedded in the insulating layer 571 and positioned on the conductor 511. an insulator 585 on the edge 571; a plug 543 and a conductor 513 on the insulator 571; In the cross section shown in FIG. 4, the height of the highest region of the upper surface of the plug 543 is The height 641 is preferably greater than the height 642 of the highest region of the upper surface of the insulator 571. I wish.

[0079] As shown in FIG. 4, the corners of the conductor 511, the conductor 513 and the plug 543 are rounded. The opening for forming the conductor 513 may be a portion of the insulator 571. In that case, the bottom surface of the conductor 513 in the cross section shown in FIG. Of these, it is preferable that the height 643 of the lowest region is lower than the height 642 .

[0080] Here, as an example, silicon nitride is used as the insulator 464a and nitrogen dioxide is used as the insulator 581a. Here, at least one of the insulator 571a and the insulator 571 is made of silicon dioxide. A material with low permeability is used. In this case, titanium nitride, for example, is used as the conductor 513b. As a result, hydrogen contained in silicon nitride or silicon carbonitride diffuses into the transistor 490. This can prevent the particles from scattering.

[0081] <layer 629> Layer 629 includes transistor 490 and plugs such as plug 544 and plug 544b. The plugs, such as plug 544 and plug 544b, are formed by conductors in layer 628. 513, a gate electrode, a source electrode, or a drain electrode of the transistor 490. To be continued.

[0082] The transistor 490 includes a semiconductor layer 406. The semiconductor layer 406 includes a semiconductor material. Examples of the semiconductor material include oxide semiconductor materials, silicon, germanium, and gallium. semiconductor materials such as silicon, germanium, gallium, arsenic, and aluminum In particular, the semiconductor layer 4 may be a compound semiconductor material having the above structure or an organic semiconductor material. 06 preferably includes an oxide semiconductor.

[0083] A top view of the transistor 490 shown in FIG. 1 is shown in FIG. Cross-sectional views corresponding to the dashed dotted line E1-E2 and the dashed dotted line E3-E4 are shown in FIG. Layer 625 may be a substrate, or a substrate on which an insulator or conductor is formed. good.

[0084] Here, the transistor 490 is connected to the conductor 413 and the insulator on the conductor 413 as shown in FIG. It is preferable that the insulating layer 571 has an edge 571a.

[0085] In the transistor 490 shown in FIG. 1, the semiconductor layer 406 includes an oxide layer 406a, an oxide The transistor 490 is formed of three layers: a first oxide layer 406b, and an oxide layer 406c. The insulator 571a, the insulator 402 on the insulator 571a, and the oxide layer 40 on the insulator 402. 6a, an oxide layer 406b on the oxide layer 406a, and a conductor 416 on the oxide layer 406b. a and conductor 416b, the top and side surfaces of oxide layer 406b, and the top of conductor 416a. an oxide layer 406c in contact with the upper surface of the conductor 416b and an insulating layer 406c on the oxide layer 406c; The insulating layer 412 has an insulator 408 on the insulator 412, and an insulator 591 on the insulator 408. In addition, the conductor 404 is disposed in the region between the conductor 416a and the conductor 416b (separate It is preferable that the insulating layer 412 is formed on the insulating layer 412 .

[0086] Conductor 416a and conductor 416b are the source or drain electrodes of transistor 490. The conductor 404 preferably serves as an in-electrode of the transistor 490. The conductor 413 of the layer 628 preferably functions as an electrode. For example, the conductor 404 may function as a gate electrode of the first gate electrode 490. The electrode, conductor 413, may function as a second gate electrode.

[0087] For example, the material shown in the insulator 571 may be used as the insulator 571a in a single layer or a laminated layer. Here, the transistor 490 traps charge between the semiconductor layer 406 and the conductor 413. By having a charge trapping layer, the transistor 490 can be made to operate normally by trapping charges in the charge trapping layer. This is preferable because the threshold voltage can be controlled. Therefore, the insulator 571a is a charge trapping layer. In this specification, the threshold value is, for example, a value that is smaller than the channel shape. The threshold voltage is the gate voltage when the gate is turned on. For example, the threshold voltage is expressed as In the curve plotting the square root of the rain current Id on the vertical axis (Vg-√Id characteristics), When the tangent line, which is the slope, is extrapolated, the square root of the drain current Id is 0 (Id is 0A). The gate voltage (Vg) at the intersection of

[0088] The material shown in the insulator 571 can be used as the charge trap layer. For example, hafnium oxide or silicon nitride is preferably used. The charge trapping layer may be an insulating film having metal clusters. This may shift the threshold voltage of the transistor 490 to the positive side. do.

[0089] The insulator 571a is formed by stacking a layer that easily captures charges and a layer that is difficult for impurities to pass through. For example, hafnium oxide may be formed as a layer that easily captures electric charges. Aluminum oxide may be laminated on the surface of the oxide film as a layer that is difficult for impurities to pass through. Hafnium oxide may be formed on the aluminum oxide.

[0090] Alternatively, a triple layer of silicon oxide can be used in addition to hafnium oxide and aluminum oxide. The three layers may be laminated in any order.

[0091] In addition, the insulator 571a uses silicon oxide as a lower layer, so that the transistor 490 The characteristics and reliability of the insulator 571a may be improved, which is preferable. A layer of silicon oxide may be used, with an upper layer of hafnium oxide. Silicon is used, hafnium oxide is used on silicon oxide, and aluminum oxide is used on hafnium oxide. A three-layer structure using miniature may be used. For example, silicon oxide is used as the insulator 571a, and silicon oxide is used as the insulator 571b. The structure uses two layers of hafnium oxide on silicon, and silicon oxide as the insulator 402. It can be said that it is completed.

[0092] Here, since the semiconductor device 500 has the insulators 571 and 571a, the layer 6 It is possible to prevent hydrogen, water, and the like contained in the conductive layer 27 from diffusing into the transistor 490. Conductors such as conductor 511, conductor 513, and conductor 413 and plugs such as plug 543 are provided. In addition, the conductor 513 and the like can be prevented from diffusing into the transistor 490. In addition, the semiconductor device 500 can suppress the element contained in the insulator 4 from diffusing into the layer 627. By having the insulator 408, the diffusion of impurities, such as hydrogen and water, from above the insulator 408 is prevented. It can be suppressed.

[0093] For example, when the transistor 490 includes an oxide semiconductor, hydrogen is introduced into the oxide semiconductor. By suppressing the diffusion, it may be possible to suppress the deterioration of the transistor characteristics.

[0094] Here, the semiconductor device 500 may not have the insulator 571a, but the insulator 571a It is more preferable that the .alpha.-methylphenyl.

[0095] The conductor 416a and the conductor 416b are made of the material shown in the conductor 511, for example. It is possible.

[0096] The conductors 416a and 416b are made of, for example, tungsten or titanium. When the material is easily bonded to oxygen, an oxide of the material is formed, which makes the conductor In the region where the conductor 416a and the conductor 416b contact the semiconductor layer 406 and in the vicinity thereof Oxygen vacancies in the semiconductor layer 406 may increase. When hydrogen is bonded to the oxygen vacancies, The carrier density in the region increases and the resistivity decreases.

[0097] The conductor 416a and the conductor 416b are connected to the plug 5 formed on their upper surfaces. It is preferable that 44b be made of a material that has low permeability to the elements contained therein.

[0098] Alternatively, the conductor 416a and the conductor 416b may be a stacked film. The conductor 416a and the conductor 416b are a stack of a first layer and a second layer. A first layer is formed on the oxide layer 406b, and a second layer is formed on the first layer. For example, tungsten is used as the first layer, and tantalum nitride is used as the second layer. For example, copper is used for the lug 544b. Copper has low resistance and is suitable for use as a conductor for plugs, wiring, etc. On the other hand, copper is easily diffused and is used in the semiconductor layer and gate of a transistor. Diffusion into the insulating film etc. may degrade the transistor characteristics. Since the conductor 416a and the conductor 416b are made of tantalum nitride, the plug 544b and the like In some cases, it may be possible to suppress the diffusion of copper into the oxide layer 406b.

[0099] In the semiconductor device 500 according to one embodiment of the present invention, plugs, wiring, etc., cause a deterioration in the characteristics of the semiconductor element. When an element or compound is contained, the element or compound is prevented from diffusing into a semiconductor element. It is preferable that the compound has a structure as follows.

[0100] The insulator 408 can be made of the material shown in the insulator 571. As shown in FIG. 1, during the deposition of the insulator 408, excess is generated at the interface between the insulator 408 and the underlying film and in the vicinity thereof. It is preferred that excess oxygen is provided.

[0101] In addition, the insulators 571, 571a and 408 are made of a material having low oxygen permeability. By using a material, oxygen is prevented from diffusing outward from the transistor 490 (e.g., the insulating layer). It is possible to suppress the diffusion of the ions from the insulator 571 to the layer below the insulator 408 or from the layer above the insulator 408. In some cases, it may be possible to efficiently supply oxygen to the transistor 490. When the electrode 490 includes an oxide semiconductor, oxygen can be easily supplied to the oxide semiconductor. This may lead to improved transistor characteristics.

[0102] <layer 630> Layer 630 includes insulator 592, conductors such as conductor 514, and plugs such as plug 545. , The plugs 545, etc. connect with conductors such as conductor 514.

[0103] <layer 631> The layer 631 includes a capacitor 150. The capacitor 150 includes a conductor 516 and a conductive The insulator 572 is a conductor 516 and a conductor 517. Layer 631 also includes an area sandwiched between insulator 594 and plug 517 on conductor 517. It is preferable that the plug 547 is embedded in the insulator 594. Also, the layer 631 is preferably provided with a conductor 5 that connects to a plug in the layer 630. 16b and plug 547b on conductor 516b.

[0104] Layer 631 may also include a wiring layer that connects to plug 547 and plug 547b. In the example shown in FIG. 1, the wiring layer includes the conductor 518 connected to the plug 547 and the plug 547b. , a plug 548 on the conductor 518, an insulator 595, a conductor 519 on the plug 548, , and an insulator 599 on the conductor 519. The plug 548 is embedded in the insulator 595. In addition, the insulator 599 is preferably formed so as to have an opening on the conductor 519. Yes.

[0105] <Transistor 490> A top view of the transistor 490 shown in FIG. 1 is shown in FIG. FIG. 5B shows cross-sectional views corresponding to the dashed dotted line E1-E2 and the dashed dotted line E3-E4.

[0106] As shown in FIG. 5B, the oxide layer 406b is electrically (The electric field of a conductor can electrically surround a semiconductor.) This structure is called the surrounded channel (s-channel) structure. As a result, a channel may be formed throughout the bulk of the oxide layer 406b. The s-channel structure allows a large current to flow between the source and drain of a transistor. This makes it possible to increase the current (on-state current) when the transistor is conductive.

[0107] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, the structure is suitable for devices having the transistor. It is possible to make highly integrated and highly dense devices. For example, The channel length is preferably 40 nm or less, more preferably 30 nm or less, and even more preferably The transistor preferably has a channel width of 40 nm or less. m or less, more preferably 30 nm or less, and further preferably 20 nm or less.

[0108] Here, instead of the configuration shown in FIG. 5, the transistor 490 may have the configuration shown in FIGS. may also be used.

[0109] The transistor 490 shown in FIG. 6 includes an oxide layer 406c, an insulator 412, and a conductor 40 4. The structure of the insulator 408 is different from that in FIG. 5. FIG. 6(A) shows a top view of the transistor 490. In addition, cross-sectional views corresponding to the dashed line E1-E2 and the dashed line E3-E4 shown in Figure 6(A) are 6B. The transistor 490 shown in FIG. 6B includes a layer 625 and a The insulator 402, the oxide layer 406a on the insulator 402, and the oxide layer 406a on the oxide layer 406a. layer 406b, conductor 416a and conductor 416b on oxide layer 406b, and oxide layer An oxide layer 406c in contact with the upper surface of 406b, an insulator 412 on the oxide layer 406c, Conductor 404 on edge 412 and insulator 591 on conductor 416a and conductor 416b and an insulator 408 on the insulator 591 and the conductor 404.

[0110] As shown in FIG. 6B, an insulator 412 is preferably laminated on the oxide layer 406c. In addition, the oxide layer 406c and the insulator 412 are formed on the side of the opening of the insulator 591. In addition, the conductor 404 is preferably covered with an oxide layer 406c and an insulator 412. It is preferable that the conductor 404 is formed so as to fill the opening. 6a and the conductor 416b are formed on the region (the region between them) via the insulator 412. It is preferable that

[0111] The transistor 490 shown in FIG. 7 includes an oxide layer 406c, an insulator 412, and a conductor 40 The structure of the transistor 490 is different from that of the transistor 490 shown in FIG. The cross-sectional view corresponding to the dashed line E1-E2 and the dashed line E3-E4 shown in FIG. 7(B) is In the transistor 490 shown in FIG. 7B, the insulator 412 is an oxide layer 406c. The oxide layer 406c is laminated on the side of the opening of the insulator 591 and on the insulator 59. An insulator 412 is formed on the oxide layer 406c. The dielectric 404 is shaped to fill the openings covered by the oxide layer 406c and the insulator 412. The conductor 404 is also formed as an insulator through the oxide layer 406c and the insulator 412. The insulator 408 is formed on the upper surface of the conductor 404. In addition, the insulator 408 is preferably in contact with at least a part of the side surface of the conductor 404. .

[0112] <Modifications of Transistor 490> FIG. 38(A) is a top view of a transistor 490. FIG. 38(B) shows the structure of FIG. 4A and 4B show cross sections corresponding to dashed dotted lines C1-C2 and C3-C4 shown in FIG.

[0113] The transistor 490 shown in FIG. 38B includes an insulator 402 and an oxide layer on the insulator 402. The oxide layer 406a, the oxide layer 406b on the oxide layer 406a, the side of the oxide layer 406a, etc. Conductor 416a and conductor 416b are in contact with the top and side surfaces of oxide layer 406b. b, the side surface of the oxide layer 406a, the top surface and side surface of the oxide layer 406b, and the conductor 416a The oxide layer 406c contacts the top and side surfaces of the conductor 416b and the top and side surfaces of the conductor 416b. , an insulator 412 on the oxide layer 406c, and a conductor 404 on the insulator 412.

[0114] FIG. 39(A) is a top view of a transistor 490. FIG. 39(B) is a top view of the transistor 490 shown in FIG. 1 is a cross-sectional view corresponding to dashed dotted lines G1-G2 and G3-G4 shown in FIG.

[0115] The transistor 490 shown in FIG. 39(A) and FIG. 39(B) includes an insulator 402 and an insulating The oxide layer 406a on the protruding portion of the body 402, the oxide layer 406b on the oxide layer 406a, and the oxide The oxide layer 406c on the oxide layer 406b, and the oxide layer 406a, the oxide layer 406b and the oxide layer 406c on the oxide layer 406b are A conductor 416a and a conductor 416b are disposed in contact with the oxide layer 406c and spaced apart from each other. , an insulator 412 on the oxide layer 406c, on the conductor 416a, and on the conductor 416b; The conductor 404 on the edge 412, the conductor 416a, the conductor 416b, and the insulator 412 and an insulator 408 on the conductor 404.

[0116] In addition, the insulator 412 is formed on at least the side surface of the oxide layer 406b in the G3-G4 cross section. In addition, the conductor 404 is in contact with at least the insulator 412 in the G3-G4 cross section. The upper and side surfaces of the oxide layer 406b are exposed through the insulating layer 406.

[0117] As shown in FIG. 40(A), the end of the oxide layer 406c and the end of the insulator 412 As shown in FIG. 40B, the end of the conductor 404 and An end of the oxide layer 406c and an end of the insulator 412 may be roughly aligned.

[0118] 41A is an example of a top view of a transistor 490. An example of a cross-sectional view corresponding to F1-F2 and dashed line F3-F4 is shown in FIG. In FIG. 41(A), some insulators and the like are omitted for ease of understanding.

[0119] The transistor 490 shown in FIG. 41 does not include the conductor 416a and the conductor 416b. The conductor 426a and the conductor 426b are in contact with the oxide layer 406b. At least the conductor 426a and the conductor layer 426b and / or the oxide layer 406a It is preferable to provide a low resistance region 423a (low resistance region 423b) in the region in contact with the body 426b. The low resistance region 423a and the low resistance region 423b are formed by masking, for example, the conductor 404. The oxide layer 406b and / or the oxide layer 406a are doped with impurities to form a The conductor 426a and the conductor 426b may be formed by filling the holes ( The conductive material may be provided in a through hole (one that penetrates) or a recess (one that does not penetrate). Conductor 426a and conductive material 426b are provided in holes or depressions in oxide layer 406b. As a result, the contact area between the conductor 426a and the oxide layer 406b is large. Therefore, the effect of contact resistance can be reduced. It can be made bigger.

[0120] 42(A) and 42(B) are top views and diagrams of a transistor 490 according to one embodiment of the present invention. FIG. 42(A) is a top view, and FIG. 42(B) is a cross-sectional view of the structure shown in FIG. 42 is a cross-sectional view corresponding to the dashed line I1-I2 and the dashed line I3-I4. In the top view of (A), some elements are omitted for clarity.

[0121] The transistor 490 shown in FIG. 42(A) and FIG. 42(B) includes a conductor 6 on a layer 625. 14, an insulator 612 on the conductor 614, an oxide layer 606a on the insulator 612, and an oxide layer 606b on the oxide layer 606c. An oxide layer 606b on the oxide layer 606a, an oxide layer 606c on the oxide layer 606b, and an oxide layer 606c on the oxide layer 606a. The oxide layer 606a is in contact with the oxide layer 606b and the oxide layer 606c, and is disposed at intervals. The conductor 616a and the conductor 616b are formed on the oxide layer 606c, the conductor 616a, and the The conductor 614 has an insulator 612 and an insulator 618 on the conductor 616b. The insulator 612 faces the lower surface of the oxide layer 606b through a protrusion. The oxide layer 606a may be omitted. Also, the insulator 618 may be omitted. That's fine.

[0122] Note that the oxide layer 606b functions as a channel formation region of the transistor 490. The conductor 614 is connected to the first gate electrode (front gate) of the transistor 490. The conductor 616a and the conductor 616b function as a , which serve as the source and drain electrodes of the transistor 490.

[0123] It is preferable that the insulator 618 be an insulator containing excess oxygen.

[0124] For the conductor 614, refer to the description of the conductor 404. For details, refer to the description of the insulator 412. Also, the oxide layer 606a is The oxide layer 606b is the same as the oxide layer 406b. For the oxide layer 606c, see the description of the oxide layer 406c. In addition, the conductor 616a and the conductor 616b are connected to the conductor 416a and the conductor 41 6b. Also, the insulator 618 may be the same as the insulator 402. See:

[0125] Therefore, the transistor 490 shown in FIG. 42 is similar to the transistor 490 shown in FIG. In some cases, it can be considered that only a part of the structure is different. Specifically, the transistor shown in Figure 5 490 without the conductor 404. Thus, the transistor shown in FIG. The description of the transistor 490 shown in FIG. 5 may be referred to as appropriate. do.

[0126] Note that the transistor 490 is a conductor that overlaps with the oxide layer 606b via the insulator 618. The conductor may serve as a second gate electrode of the transistor 490. The conductor 413 is described in detail below. It is also acceptable to form an s-channel structure.

[0127] Note that a display element may be provided on the insulator 618. For example, a pixel electrode, a liquid crystal display, A crystal layer, a common electrode, a light-emitting layer, an organic EL layer, an anode, a cathode, etc. may be provided. The terminals are connected to, for example, conductors 616a and the like.

[0128] In addition, an insulator that can function as a channel protection film is placed on the oxide layer. Alternatively, as shown in FIG. 43, a conductor 616a and a conductor 616b may be formed by oxidizing the conductor 616a and the conductor 616b. An insulator 619 may be disposed between the conductive layer 616a and the conductive layer 606c. The insulator 616b) and the oxide layer 606c are connected through an opening in the insulator 619. For the insulator 619, refer to the description of the insulator 618.

[0129] In addition, in FIG. 42(B) and FIG. 43(B), the conductor 613 is disposed on the insulator 618. An example of this case is shown in FIG. 44(A) and FIG. 44(B). For conductor 13, refer to the description of conductor 413. The same potential or signal as the electric power source 614 may be supplied, or a different potential or signal may be supplied. For example, a constant potential may be applied to the conductor 613 to turn on the threshold of the transistor 490. In other words, the conductor 613 functions as a second gate electrode. It is possible.

[0130] <Transistor 491> Next, the transistors 491 to 493 will be described.

[0131] The transistor 491 includes a channel formation region 407, an insulator 462 on a substrate 400, and A conductor 454 on an insulator 462, an insulating film 470 in contact with the side surface of the conductor 454, and a substrate 4 00, and a region 476 which is a region that does not overlap with the conductor 454 and the insulating film 470; The region 474 is a region overlapping the insulating film 470. The region 476 is a low resistance layer. 491. Additionally, region 474 preferably functions as an LDD (lightly doped drain) region. stomach.

[0132] The transistor 491 may be either a p-channel type or an n-channel type. An appropriate transistor may be used depending on the driving method.

[0133] The substrate 400 preferably comprises a semiconductor, such as a silicon-based semiconductor, and is preferably a single crystal It is preferable to have silicon. Alternatively, Ge (germanium), SiGe (silicon Germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide) ) or the like. Also, a configuration using silicon having a distortion in the crystal lattice may be used. Alternatively, the transistor 491 can be made into a HEMT ( High Electron Mobility Transistor) .

[0134] Region 476 may be doped with an element that provides n-type conductivity, such as phosphorus, or a p-type conductive element, such as boron. It is preferable that the material contains an element that imparts electrical conductivity.

[0135] The conductor 454 is an element that provides n-type conductivity, such as phosphorus, or a p-type element, such as boron. Semiconductor materials such as silicon that contain elements that give them electrical conductivity, metal materials, alloy materials, or gold Conductive materials such as metal oxide materials can be used. In particular, It is preferable to use a high melting point material such as tungsten or molybdenum, and particularly tungsten. It is preferable to use:

[0136] The transistor 491 shown in FIG. 1 and FIG. 2 is formed by a trench isolation method (STI method: Shallo Isolation). Here is an example of device isolation using trench isolation. In FIG. 1, a trench formed in a substrate 400 by etching or the like contains silicon oxide or the like. After embedding the insulating material, the insulating material is partially removed by etching, etc. 4 shows an example in which a transistor 491 is isolated by an element isolation region 460 formed in the semiconductor device. is.

[0137] In addition, the region of the transistor 491 is formed on the protruding portion of the substrate 400 that exists in the region other than the trench. A region 476 and a region 474, and a channel forming region 407 are provided. The transistor 491 is formed by a semiconductor device having an insulator 462 that covers a channel forming region 407 and a semiconductor device having an insulator 462 therebetween. A conductor 454 overlaps with the channel formation region 407 on both sides.

[0138] In the transistor 491, the side and upper parts of the convex part in the channel forming region 407 and the conductor The insulator 454 and the insulator 462 are overlapped with each other with the insulator 462 interposed therebetween, so that the side of the channel formation region 407 Carriers flow over a wide area, including the upper and lower parts. While keeping the area occupied on the board small, the amount of carrier movement in the transistor 491 As a result, when the on-current of the transistor 491 increases, In particular, the field effect mobility is improved in the convex portion of the channel forming region 407. The length in the width direction of the channel (channel width) is W, and the film thickness of the protruding part in the channel formation region 407 is T Then, when the aspect ratio, which corresponds to the ratio of the thickness T to the channel width W (T / W), is high, In this case, the range in which carriers flow is wider, so the on-current of transistor 491 is increased. The field effect mobility can be further increased.

[0139] In the case of the transistor 491 using a bulk semiconductor substrate, the aspect ratio is 0.5. It is preferable that the number is equal to or greater than 1, and it is more preferable that the number is equal to or greater than 1.

[0140] In addition, as shown in FIG. 34A, the transistor 491 does not have a protrusion on the substrate 400. The transistor 491 may be formed of SOI (silicon). Alternatively, the insulating layer 14 may be formed using a (on-on-insulator) substrate.

[0141] The transistors 492 and 493 are the same as those of the transistor 491. Please refer to the following.

[0142] [Modification of the semiconductor device] Next, an example of a semiconductor device 500 having a structure different from that shown in FIG. 1 will be described.

[0143] 8 shows a cross-section of semiconductor device 500. Semiconductor device 500 shown in FIG. For the sake of brevity, the details of layers 630 and 631 are omitted. 8. Compared to the semiconductor device 500 shown in FIG. 1, the structure of layer 628 is different in FIG.

[0144] Layer 628 shown in FIG. 1 has conductor 513 on plug 543. Conductor 513 may be, for example, On the other hand, the conductor 613 shown in FIG. Alternatively, the conductor 613 may be a plug 543 and a conductor 513. Here, the semiconductor device 500 has a conductor 511 as shown in FIG. As shown in the example, the height of the lower surface of the conductor 511 is lower than the height of the upper surface of the insulator 464b. Good too.

[0145] In addition, the conductor such as the conductor 613 may be a laminate of multiple conductors. For example, the conductor 613a 9A shows a stack of the conductor 613 in FIG. An example of stacking a conductor 613a and a conductor 613b is shown. The area enclosed by the dashed line is shown in FIG.

[0146] Materials that can be used for the conductor 613, the conductor 613a, and the conductor 613b are These may refer to conductor 513, conductor 513a, and conductor 513b, respectively. .

[0147] The conductors and plugs, such as the conductor 513, the plug 543, and the conductor 613, are rounded. In the cross section shown in FIG. 9B, the corners of the conductor 613 and the like are rounded. Here is an example of how this can be useful.

[0148] As shown in FIG. 11, the semiconductor device 500 has an insulator 571 on an insulator 581. Alternatively, a structure in which an insulator 584 is provided over the insulator 571 may be used.

[0149] As shown in FIG. 12, the semiconductor device 500 has an insulator 571b on the insulator 581. Even if the insulator 584 is provided on the insulator 571b and the insulator 571 is provided on the insulator 584, For the insulator 571b, refer to the description of the insulator 571.

[0150] When the dielectric constant of the insulator 571b is higher than that of the insulator 584, the thickness of the insulator 571b is It is preferable that the thickness of the insulator 571b is smaller than that of the insulator 584. For example, the thickness of the insulator 571b is preferably or 5 nm to 200 nm, more preferably 5 nm to 60 nm, The thickness of the body 584 is preferably 30 nm or more and 800 nm or less, more preferably 50 nm or more. The thickness of the insulator 571b is 3 times that of the insulator 584. It is preferable that the ratio is 1 or less.

[0151] Next, an example in which the transistor 490 of the semiconductor device 500 has the configuration shown in FIG. is shown in Figure 13.

[0152] The semiconductor device 500 shown in FIG. 13 includes layers 627 to 631. Details of the layer 628 and the layer 631 are omitted. For the layer 628, see the description of FIG. can be done.

[0153] In the example shown in FIG. 1, the layer 629 includes the insulator 408 on the transistor 490. An insulator 591 is provided on the insulator 408. In addition, the top surface of the insulator 591 is planarized. On the other hand, in FIG. 13, an insulator 591 is provided to cover at least a part of the transistor 490. , the insulator 408 is disposed on the insulator 591 whose upper surface is planarized.

[0154] The semiconductor device 500 shown in FIG. 13 also includes a layer 630 on the insulator 408. The insulator 592 is provided on the insulator 408. The insulator 592 includes an insulator 592a and an insulator 592b. 92a and an insulator 592c on the insulator 592b. In FIG. 13, the plug 544 and the plug 544b have a protrusion on the insulator 408 and are conductive. The conductive body 514 is preferably located on the upper part or the side part of the protrusion. , preferably formed so as to fill the plugs 544 and 544b. On top of 514, etc., plugs are formed to connect to the conductors of layer 631, etc., so as to fill plug 544c. is formed.

[0155] Here, in the semiconductor device 500 shown in FIG. The plug 544c is in contact with the insulator 408. The plug 544c has a protrusion on the insulator 408. The protrusion has a conductor on the top and sides.

[0156] Here, by forming the insulator 408 on the planarized surface to be formed, for example, This is preferable because it may improve the covering property of the body 408 and reduce the hydrogen permeability. In some cases, the insulator 408 can be made thinner due to its improved blocking ability.

[0157] <Capacitive element> FIG. 14 shows a configuration in which a capacitor 150 is provided adjacent to a transistor 490 shown in FIG. The conductor 404b formed in the opening 591 is used as one electrode of the capacitor 150, and the insulator The insulator 408 is connected to the dielectric of the capacitance element 150, and the conductor on the insulator 408 is connected to the other Here, the conductor 404b is manufactured in the same process as the conductor 404. This can be done.

[0158] In addition, the structures shown in FIGS. 15(A) to 15(C) may be used in place of the capacitance element 150 shown in FIG. It can be used.

[0159] The capacitance element 150 shown in FIG. 15A includes an insulator 592, a conductor 514, and a plug 54. 5, and also conductor 516 on insulator 592 and plug 545, and insulator 592 on conductor 516. The insulator 592 and the conductor 517 on the insulator 572 are included. 4 and plug 545, please refer to the description of FIG. 1. In addition, conductor 517 is Alternatively, as shown in FIG. 15, the conductive layer 517 may be formed in two layers, a conductive layer 517a and a conductive layer 517b. The conductor 517a and the conductor 517b are, for example, the conductors 511a and 511b. Just turn it on.

[0160] In the capacitance element 150 shown in FIG. 15A, the conductor 516 is disposed in the recess of the insulator 593. An insulator 572 and a conductor 517 are formed on the conductor 516 and the insulator 593. A film that will become a is formed, and then a film that will become the conductor 517b is formed so as to fill the recess. Then, the conductor 517b, the conductor 517a, and the insulator 572 are formed using a mask.

[0161] FIG. 15B shows a capacitance element 150 in which a conductor 516 and a plug are disposed in a different region from the capacitance element 150 shown in FIG. 5 in that there is a conductor 515 between the connector 545 and the connector 546.

[0162] As shown in FIG. 15C, the conductor 516 and the like are formed in the recess of the insulator 592. In FIG. 15C, the insulator 592 is disposed on the bottom and part of the side of the conductor 516. The insulator 593 contacts the side of the conductor 516. Insulator 581c may be provided between insulators 592 and 593. For example, the insulator 581a may be referred to as 81c.

[0163] [Method for manufacturing semiconductor device] Next, a manufacturing method of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. Reveal.

[0164] A method for manufacturing the semiconductor device 500 shown in FIG. 1 will be described with reference to FIGS. Here, a method for forming layers 628 to 630 will be described.

[0165] An insulator 581 is deposited on the layer 627. Then, a mask 207 is formed on the insulator 581. (See FIG. 16(A)). The mask 207 is formed by lithography using, for example, a resist. Alternatively, a hard mask made of an inorganic film or a metal film may be formed. .

[0166] Next, a portion of the insulator 581 is etched using the mask 207 to form an opening ( (See FIG. 16(B).) Next, the mask 207 is removed, and then the inside of the opening and the insulator are A conductor 511d is formed on the substrate 581 (see FIG. 16C).

[0167] Next, the surface of the conductor 511d is planarized and removed to expose the insulator 581. conductors such as the conductor 511 are formed (see FIG. 16(D)). For example, chemical mechanical polishing It is preferable to use a polishing method such as a CMP method. Alternatively, dry etching may be used. For example, a technique such as etch-back may be used. A polishing technique such as the CMP method may be used. When using the polishing speed of the conductor 511d, the polishing speed may have a distribution within the surface of the sample. In this case, in a portion where the polishing speed is high, the exposure time of the insulator 581 may be long. It is preferable that the polishing speed of the insulator 581 is slower than that of the conductor 511d. Since the polishing speed of the insulator 581 is slow, in the polishing process of the conductor 511d, The insulator 581 can serve as a polishing stopper film. The flatness of the surface of 581 can be improved.

[0168] Here, the CMP method is a method for flattening the surface of a workpiece by a combination of chemical and mechanical processes. Generally, a polishing cloth is attached to the polishing stage, and the workpiece is placed between the polishing cloth and the polishing While supplying slurry (abrasive) to the workpiece, the polishing stage and the workpiece are rotated or swung. The chemical reaction between the slurry and the surface of the workpiece and the mechanical abrasion between the polishing cloth and the workpiece occur simultaneously. This is a method of polishing the surface of a workpiece by the action of abrasive grains.

[0169] In the CMP method, the polishing cloth may be, for example, polyurethane foam, nonwoven fabric, suede, etc. As the abrasive grains, for example, silica (silicon oxide) or ceramic oxide can be used. As the silica, sodium oxide, manganese oxide, aluminum oxide, etc. can be used. For example, fumed silica or colloidal silica can be used.

[0170] The slurry used in the CMP method is selected from the viewpoints of ease of removal of the workpiece and stability of the slurry solution. For example, if an acidic slurry is used, the pH may be adjusted at the stock solution. It is preferable that the insulator 581 serving as the permeable film has high resistance to acids. When using a slurry, it is preferable that the insulator 581 has high resistance to alkali. .

[0171] In addition, an oxidizing agent such as hydrogen peroxide may be added to the slurry.

[0172] Here, as an example, the conductor 511d includes tungsten and the insulator 581 includes silicon oxide. The slurry may contain, for example, fumed silica or It is preferable to use colloidal silica. It is also preferable to use an acidic slurry, for example. is preferable, and for example, hydrogen peroxide solution is preferably used as the oxidizing agent.

[0173] Next, an insulator 584 is formed on the insulator 581 and the conductor 511. An insulator 571 is formed, and an insulator 585a is formed over the insulator 571 (see FIG. 16E). In the example shown in FIG. 16 to FIG. 19, the insulator 585 is divided into an insulator 585a and an insulator 585b. Here, the same material is used for the insulators 585a and 585b. Alternatively, different materials may be used.

[0174] The insulator 571 is formed by sputtering, CVD (thermal CVD, MOCVD, PECV The thin-film transistor can be formed by a method such as MBE, ALD, or PLD. Here, as an example, aluminum oxide is used as the insulator 571 by sputtering. Form.

[0175] Next, a mask is formed on the insulator 585a, and the insulator 585a, the insulator 571, and the insulator An opening is formed in the body 584 (see FIG. 17(A)). After that, the mask is removed, and the A conductor is formed on the opening and the insulator 585a, and the surface of the conductor is removed to be flattened. Then, plugs such as plug 543 are formed (see FIG. 17(B)). A layer containing tungsten is used as the insulator 543, and silicon oxide is used as the insulator 585a. By using the layer having the above structure, when removing the conductor to be the plug 543 by using the CMP method, In addition, the etching rate of the insulator 585a may be reduced. In some cases, the flatness of the surface of the insulator 585a can be improved. In some cases, it may be possible to reduce the variation in height.

[0176] Next, an insulator 585b is formed on the insulator 585a and the plug 543, and an insulator 585 (See FIG. 17(C)). After that, a mask is formed on the insulator 585, and the mask An opening is formed in the insulator 585 using a dummy wire (see FIG. 17(D)). When forming an opening in the body 585, dry etching, wet etching, or the like may be used. In this case, when the opening is formed, the etching rate of the insulator 585 is higher than that of the insulating material 585. When the etching rate of the plug 543 is slow, the plug 543 and the like are etched away as shown in FIG. The plug forms a protrusion within the opening.

[0177] Next, after removing the mask, a conductor is formed in the opening of the insulator 585 and on the insulator 585. The conductors are then removed so as to flatten the surfaces thereof, and the conductors 513 and 413 are removed. Then, the insulator 571a is formed (see FIG. 18(A)). The method for forming the insulator 71a can be referred to as the insulator 571.

[0178] Next, the transistor 490 is formed over the insulator 571a. First, the insulator 402 is formed. Next, a first oxide layer that will become the oxide layer 406a is formed, and an oxide layer is formed on the first oxide layer. A second oxide film is formed, which becomes 406b, and then a first conductor film, which becomes conductor 416a, etc. Then, the first oxide and the second oxide are formed using the first conductor as a hard mask. The oxide is processed to form oxide layer 406a and oxide layer 406b. Dry etching or the like may be used.

[0179] Next, the first conductor is processed to form conductor 416a and conductor 416b. Then, the oxide layer 406c and the insulator 412 are formed. Then, the conductor 404 is formed. A transistor 490 is fabricated.

[0180] Here, the insulator 402 may be formed so as to contain excess oxygen. Oxygen may be added after the deposition of the film 02. The addition of oxygen may be performed, for example, by ion implantation. The acceleration voltage is set to 2 kV or more and 100 kV or less, and the dose is set to 5 × 10 14 ions / cm 2 5×10 or more 16 ions / cm 2 This can be done as follows.

[0181] Alternatively, oxygen may be added to the first oxide which is to be the oxide layer 406a after the first oxide is formed.

[0182] Here, heat treatment may be performed after the second oxide to be the oxide layer 406b is formed. The heat treatment is carried out at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C., more preferably The heat treatment may be performed at a temperature of 350° C. or higher and 450° C. or lower. The treatment is carried out in an atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. Alternatively, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed under an inert gas atmosphere followed by To compensate for the oxygen that has been removed, the gas contains 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. The heat treatment may be performed in an atmosphere containing SiO 2 . It is possible to increase the crystallinity of the solid layer 406b and remove impurities such as hydrogen and water. During the heat treatment, hydrogen and water are released from the material below the insulator 402, forming oxides. It may diffuse into layer 406b.

[0183] The oxide layers 406a, 406b, and 406c may be formed by, for example, For example, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like can be used. The films to be the oxide layers 406a, 406b, and 406c can be formed by When forming an In-Ga-Zn oxide layer by MOCVD, the source gas is Trimethylindium, trimethylgallium, dimethylzinc, etc. may be used. The combination of raw material gases is not limited to the above, and may be replaced with triethyl indium. Indium, etc. may be used. Also, triethylgallium may be used instead of trimethylgallium. Alternatively, diethyl zinc may be used in place of dimethyl zinc. The oxide layer 406a, the oxide layer 406b, and the oxide layer 406c are dry-etched. For example, a mixture of methane (CH4) and argon (Ar) can be used as the gas source. Cut.

[0184] Next, an insulator 408 is formed over the transistor 490 (see FIG. 18B). The method for manufacturing the insulator 408 can be referred to as the insulator 571. An enlarged view of the area surrounded by the dashed line is shown in FIG.

[0185] Here, if the insulator 408 is formed by, for example, a sputtering method, the insulator 408 and the insulating A mixed layer is formed at the interface of the surface of the substrate 408 and in its vicinity, where the two are mixed together. Specifically, the insulators 408 and 402, and the insulators 408 and 412 are preferably At and near the interface, a mixed layer 145 is formed.

[0186] In this embodiment, the insulator 408 is formed of aluminum oxide by sputtering. In addition, a gas containing oxygen is used as the sputtering gas.

[0187] The mixed layer 145 contains a part of the sputtering gas. Since a gas containing oxygen is used as the ring gas, the mixed layer 145 contains oxygen. , the mixed layer 145 has excess oxygen.

[0188] Next, a heat treatment is performed. The heat treatment is preferably performed at a temperature of 200° C. or higher and 500° C. or lower, more preferably Preferably, the reaction is carried out at a temperature of 300°C or higher and 450°C or lower, and more preferably at a temperature of 350°C or higher and 400°C or lower. good.

[0189] The heat treatment causes the oxygen contained in the mixed layer 145 to diffuse. The excess oxygen is transferred to the oxide layer 406a through the insulator 402 and the insulator 412, etc. The oxide layer 406b and the oxide layer 406c are diffused into the insulator 408, the insulator 571 and the insulator 406. By using a material that is difficult for oxygen to permeate as the edge 571a, the excess oxygen contained in the mixed layer 145 The excess oxygen is removed through the insulators 402 and 412 to the oxide layer 406a and the oxide layer 406b. 6b, and the oxide layer 406c. The arrows in FIG. 19(A) show how the excess oxygen diffuses through the oxide layer 406b. By moving the oxide layer 406b to the oxide layer 406c, defects (oxygen vacancies) in the oxide layer 406b can be reduced. Cut.

[0190] Next, the insulator 591 is formed over the insulator 408. 8, an opening is provided in the insulator 402 and the insulator 571a, and the plug 544 or the plug Plugs such as lugs 544b are formed (see FIG. 19(B)). Then, layers 630 and 631 is formed, and the semiconductor device 500 shown in FIG. 1 can be manufactured.

[0191] Next, in the case where the semiconductor device 500 has a conductor 613 as shown in FIG. 8 and FIG. A method for manufacturing the layer 628 will be described with reference to FIGS. 20 and 21. A method for manufacturing the semiconductor device 500 in FIG. 9 will be described.

[0192] First, the insulator 581, the conductor 511, etc. are formed on the layer 627. Then, the insulator 581 An insulator 584 is formed on the insulator 584, an insulator 571 is formed on the insulator 571, and An insulator 585 is formed. Then, a mask is formed on the insulator 585. An opening is formed in the insulator 585 (see FIG. 20(A)). In forming the insulating layer 571, the etching rate of the insulating layer 571 is higher than the etching rate of the insulating layer 585. When the degree is small, the film loss of the insulator 571 can be reduced. When forming an opening in the insulator 584, the etching time may be easily controlled. This is preferable because it may be possible to reduce the time during which the body 511 is exposed. Then, the mask is removed. Remove.

[0193] Next, mask 2 is applied onto the insulator 585 and onto the insulator 571 in the openings of the insulator 585. 20B. Here, the insulator 571 is compared with the insulator 584. If the etching rate of the insulator 571 is low, the insulator 571 is etched away by the insulator 584. In some cases, it acts as a hard mask for the

[0194] Next, the insulators 571 and 584 are etched using the mask 208 to form openings. (See FIG. 20(C)).

[0195] Next, after removing the mask 208, the insulator 571 and the insulator 572 are formed in the opening of the insulator 585. In the opening of 84 and on the insulator 585, a conductive material such as a conductor 613a or a conductor 413a is formed. A film of a dielectric 613d is formed (see FIG. 21(A)).

[0196] Next, a conductor 613e, which will become a conductor 613b or a conductor 413b, is formed on the conductor 613d. A film is formed (see FIG. 21(B)).

[0197] Here, as an example, the conductor 613d is made of tantalum nitride and tantalum on tantalum nitride. The structure used here is a laminate of tantalum and copper on tantalum. The copper used in the deposition is sometimes called the "copper seed layer." Tantalum nitride is deposited, for example, by the sputtering method. Copper may be formed by using, for example, a CVD method or a sputtering method. Here, a copper-manganese alloy layer may be used for the conductor 613d. A layer of copper may be formed on the nickel alloy layer.

[0198] Here, copper is used as an example of the conductor 613e. Copper can be formed by using a plating method, for example. It can be formed by

[0199] Next, the conductor 613e and the conductor 613d are cut so as to flatten the surface of the conductor 613e. The surface of the insulator 585 is exposed, and conductors such as the conductor 613 and the conductor 413 are formed. By forming the layer 628 shown in FIG. 9, it is possible to manufacture the layer 628 (see FIG. 21(C)). .

[0200] Next, a method for producing the layer 628 shown in FIG. 11 is shown in FIG.

[0201] First, a conductor such as an insulator 581 and a conductor 511 is formed on a layer 627. An insulator 571 is formed on an insulator 581, and an insulator 584 is formed on the insulator 571. After that, an opening is formed in the insulator 584 using a mask (see FIG. 22(A)). In forming an opening in the insulator 584, for example, the etching rate of the insulator 584 is When the etching rate of the insulator 571 is low, the insulating layer 571 serves to protect the conductor 511 and the like. There may be cases where this occurs.

[0202] Next, a mask 209 is formed on the insulator 584 (see FIG. 22(B)). 22(A) is formed. The insulator 571 is etched using the opening 584 (see FIG. 22(C)).

[0203] Next, after removing the mask 209, a conductive layer is formed in the openings of the insulator 584 and the insulator 571. 11. The layer 628 shown in FIG. 11 is formed by forming the conductive material 613 and the conductive material 413. It is possible to form (see FIG. 22(D)).

[0204] Next, a method for manufacturing the layer 629 and the layer 630 shown in FIG. 13 will be described with reference to FIGS. explain.

[0205] First, the layer 628 is formed over the layer 627. Next, the insulator 571a and the insulator Next, a first oxide film is formed on the insulator 402 to become an oxide layer 406a. Then, a second oxide layer is formed on the first oxide layer to become the oxide layer 406b. Then, the conductor 4 A first conductor is formed as a film, which will become 16a, etc. Then, the first conductor is used as a hard mask. The first oxide and the second oxide are processed to form oxide layer 406a and oxide layer 406 The film b is formed by, for example, dry etching.

[0206] Next, an insulator 591 is formed. Then, a mask is formed on the insulator 591. An opening is formed in the insulator 591 using the above, and the first conductor is further processed to form the conductor 416a. And a conductor 416b is formed (see FIG. 23(A)).

[0207] After that, the mask is removed, and the oxide layer 406f, which becomes the oxide layer 406c, and the insulator 4 Then, an insulator 412d which becomes the insulating film 12 and a conductor 404d which becomes the conductor 404 are formed (FIG. 2 See 3(B). ).

[0208] Next, the conductor 404d, the insulator 412d, and the acid are removed so as to planarize the surface of the conductor 404d. The oxide layer 406f is removed, and the conductor 404, the insulator 412, and the oxide layer 406c are formed. Through the above steps, a transistor 490 is manufactured.

[0209] Next, an insulator 591 is formed on the insulator 591, the conductor 404, the insulator 412, and the oxide layer 406c. A film 408 is formed (see FIG. 24(A)).

[0210] Here, if the insulator 408 is formed by, for example, a sputtering method, the insulator 408 and the insulating A mixed layer 145 is formed at the interface and in the vicinity of the surface of the body 408 to be formed. This is preferable.

[0211] In this embodiment, the insulator 408 is formed of aluminum oxide by sputtering. A gas containing oxygen is used as the sputtering gas. 5 preferably has excess oxygen.

[0212] Next, a heat treatment is performed to diffuse the oxygen contained in the mixed layer 145. Excess oxygen contained in the alloy layer 145 is transferred to the oxide layer 40 via the insulators 591 and 412. 6a, oxide layer 406b, and oxide layer 406c. By using a material that is difficult for oxygen to permeate as the insulating layer 571 and the insulating layer 571a, the mixed layer 145 The excess oxygen contained in the oxide layer 406a is removed through the insulator 402 and the insulator 412, etc. The mixed layer can be effectively diffused into the oxide layer 406b and the oxide layer 406c. The way in which the excess oxygen contained in 145 diffuses is shown by arrows in FIG. In B) layer 629 is shown at a larger scale.

[0213] Here, for ease of understanding, the mixed layer 145 may not be shown.

[0214] Next, the insulator 592a is deposited over the insulator 408. 408, an opening is formed in the insulator 591, the insulator 402, and the insulator 571a (FIG. 2 See 5(A). ).

[0215] Next, the insulator 592a, the insulator 408, the insulator 591, the insulator 402, and the insulator 5 Plugs such as plug 544 and plug 544b are formed in the openings formed in 71a (FIG. 25 See (B). ).

[0216] Next, the insulator 592b is formed on the insulator 592a. A mask 210 is formed (see FIG. 25(C)).

[0217] Next, openings are formed in the insulators 592b and 592a using the mask 210. (See FIG. 26(A).) Here, the plug 544 and the plug 544b are insulated with an insulator 592b. In addition, in the case where the insulator 592a has a protrusion on the insulator 408 in the opening formed in the insulator 592a, There is a match.

[0218] Next, after removing the mask, a conductor such as the conductor 514 is formed in the formed opening. Then, an insulator 592c is formed on the insulator 592b and the conductor 514. An opening is formed in 92c (see FIG. 26(B)). Then, a conductor is formed in the opening. , layers 629 and 630 shown in FIG. 13 can be produced.

[0219] Conductors such as conductor 511, conductor 513, conductor 413, conductor 613, conductor 514, etc. The plugs 541, 543, 544, and 545 are sputtered. Ring method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, The film can be formed by the ALD method, the PLD method, or a plating method. For example, in the ring method, the collimator method and the long distance method that increases the distance between the target and the substrate are used. The fillability can be improved by using the Guslow method or a combination of these.

[0220] [Example of a circuit] Next, an example of a circuit to which the device of one embodiment of the present invention can be applied is shown.

[0221] FIG. 27A illustrates an example of a circuit including three transistors and a capacitor. The transistor 490, which is described in FIG. 1 as one of the three transistors, In the case where the capacitor 491 and the transistor 492 are used and the capacitor 150 is used as the capacitor, Think about it.

[0222] Here, the transistor used in the circuit of FIG. 27(A) is, for example, a semiconductor device as shown in FIG. In the cross section of the conductor device, it is preferably provided on either layer 627 or layer 629. In particular, transistors 491 and 492 are placed on layer 627, and transistor 4 90 in layer 629 and layer 628 in between, transistors 490 to In addition, the capacitor element 150 has a layer structure. It may be provided in any of layers 628 to 631.

[0223] As an example of a device having the circuit shown in FIG. 27(A), the structure shown in FIG. 1 can be used. In FIG. 1, transistor 491 and transistor 492 are formed in layer 627, The transistor 490 is formed in a layer 629 , and the capacitor is formed in a layer 631 .

[0224] In FIG. 27A, one of the source and drain of a transistor 490 is a floating gate. The gate electrode of the transistor 491 and the capacitance element 150 are connected to each other via a coupling node (FN). The other of the source and drain of the transistor 490 is connected to The transistor 492 is connected to either the source or drain of the transistor 492. These connections are made by the layer 628. It is preferable to connect the source of the transistor 491 through a conductor provided in the One of the source electrode and the drain electrode is connected to the layer 628 via a conductor or the like provided in the layer 628. The source or drain of the transistor 491 is connected to the terminal SL connected to the terminal 631. One end is connected to the other of the source or drain of the transistor 492 .

[0225] In FIG. 1, the conductor 454, which is the gate electrode of the transistor 491, is provided in the layer 628. The capacitance element 15 of the layer 631 is connected to the conductive plug 543 and the conductive material such as the conductive material 513. The conductor 516 is connected to the layer 629 and the layer 630. The source electrode or drain electrode of the transistor 490 is connected to the conductor and plug. The source or drain of the transistor 492 is connected to the conductor 416b, which is one of the poles. One of the two is connected to the transistor 490 via the conductors and plugs of layers 628 to 630. It is connected to the conductor 416a which is one of the source electrode and the drain electrode.

[0226] Here, a transistor provided in layer 627, such as transistor 493 in FIG. For example, peripheral circuits such as driver circuits and converters connected to the circuit shown in FIG. It may also be used for the following purposes.

[0227] FIG. 27B is different from FIG. 27A in that the transistor 492 is not included. By eliminating the transistor 492, the degree of integration of the circuit may be increased. be.

[0228] As an example of a semiconductor device 500 having the circuit shown in FIG. 27B, An apparatus 500 is shown.

[0229] 29, in comparison with FIG. 1, the plug 544 contacts the conductor 513 and the conductor 416b. 1 has plug 544 and plug 544b, whereas FIG. Since the plug 544b is not required, the degree of circuit integration can be increased.

[0230] In FIG. 29, a first opening is formed in the insulator 571a and the insulator 402. A mouth portion 632 is formed, and then the insulator 591, the insulator 408, the insulator 412 and the oxide are A second opening is formed in layer 406c, and a plug 544 is inserted into opening 632 and into the second opening. For example, the insulator 571a is preferably formed of aluminum oxide. and hafnium oxide. These materials are, for example, silicon oxide. In comparison with other materials, the etching rate during dry etching may be slower. Therefore, by forming the opening 632 in advance and then forming the second opening, for example, The exposure time of the conductor 416b to the dry etching atmosphere can be reduced, and the conductor 4 This is preferable because it may be possible to reduce the film loss of 16b.

[0231] 29 is compared with FIG. 1 in that the insulator 581 is located between the insulator 581 and the insulator 584. The insulator 582 and the insulator 583 on the insulator 582 are disposed on the upper surface of the insulator 583. The plug 542 and the conductor 512 are in contact with an insulator 582 and an insulator 584, respectively. The plug 542 is formed so as to be embedded in the conductive body 583. The conductor 512 preferably contacts the top surface of the plug 542.

[0232] 29, in comparison with FIG. 1, an insulator 593 is disposed on the insulator 592, and an insulator 593 is disposed on the insulator 593. The conductive material 515 and the plug 546 are formed to be embedded. Preferably, plug 545 is in contact with the upper surface of conductor 515, and plug 546 is in contact with the upper surface of conductor 515. It is also preferable that the plug 546 contacts the lower surface of the conductor 516. stomach.

[0233] Top views of a layout that can be used in FIG. 27(B) are shown in FIG. 30 and FIG. The area enclosed by the two-dot chain line in FIG. 30 and FIG. 31 is the circuit (or cell) shown in FIG. 27(B). Below is an example of the area that makes up one unit of land area (sometimes called a square meter).

[0234] FIG. 30(A) shows the channel region and source-drain region of a transistor 491 (diagonal The region indicated by the line, a conductor 454 acting as a gate electrode, and the source-drain region The region (dotted line) in which the conductor 454 forms a plug 541 or the like that connects to the conductor in the upper layer is shown. .

[0235] FIG. 30B shows a conductor such as the conductor 511 and a plug that connects the conductor to a conductor in an upper layer. The area in which lugs 542 etc. are formed (dashed line) is shown.

[0236] FIG. 30C shows a conductor such as the conductor 512 and a plate that connects the conductor to a conductor in an upper layer. The areas forming lugs 543 etc. (dotted lines) are shown.

[0237] FIG. 30D shows the conductor 413 and the plug 543 as well as the opening 632.

[0238] FIG. 30E illustrates a semiconductor layer 406 and a conductor 404 included in a transistor 490. Shown are openings 632 and the areas in which plugs 544 will be formed to connect with overlying conductors.

[0239] FIG. 30(F) shows a conductor such as the conductor 514 and a protrusion that connects the conductor to the conductor in the upper layer. The area where lugs 545 and the like are formed (dashed line) is also shown.

[0240] FIG. 31(A) shows a plan view of a conductor 515 and a plate connecting the conductor 515 and an upper conductor 516. The area where lug 546 is formed is shown.

[0241] FIG. 31B shows a conductor 516, a conductor 517, and a conductor 517 and an upper conductor. The area in which the connecting plug 547 is formed is shown.

[0242] FIG. 31(C) shows conductor 518b.

[0243] FIG. 32 shows a perspective view in which the top views shown in FIG. 30 and FIG. 31 are stacked in order. For ease of viewing, the distances between layers are shown larger than they actually are.

[0244] FIG. 33 shows another example of the layout other than those shown in FIG. 30 to FIG. 32. Compared with the top view, the area required for the circuit can be made smaller in FIG. In FIG. 33, the plug 544b contacts the conductor 416b and the plug 544b contacts the conductor 513. 30(E) does not require plug 544b, so the circuit can be integrated. The accumulation rate can be increased.

[0245] Next, an example of a cross section of a semiconductor device 500 having the circuit shown in FIG. 27(C) is shown in FIG. The circuit shown in FIG. 27C is, for example, a cell that functions as a memory device. Figure 1 shows an example of two adjacent cells connected together. The adjacent cells are connected to the terminal BL. The plug 544b is shared by the other terminals 544 and 544c. This allows the circuit integration density to be increased. The conductors 416a of the two adjacent transistors 490 are in contact with each other. Plug 544b connects to conductor 512 via conductor 513 and plug 543. The conductor 512 preferably functions as the terminal BL.

[0246] In FIG. 35, the capacitor 150 overlaps the transistor 490. The conductor 416a of the capacitor 150 is connected to the plug 544, the conductor 514, etc. The conductor 516 is connected to the conductor 516 .

[0247] As also shown in FIG. 35, semiconductor device 500 includes transistor 494 in layer 627. Here, for example, the transistor 494 may be a p-type channel and the transistor 491 may be an n-type channel. It may also be a channel.

[0248] FIG. 36 shows an example of a cross section of a semiconductor device 500 having the circuit shown in FIG. In FIG. 35, a connection is made from transistor 490 to terminal BL via a conductor in layer 628. 36 shows a conductor in layer 631 leading from transistor 490 to terminal BL. The connection points are different.

[0249] In FIG. 36, two adjacent transistors 490 share a conductor 416b. Therefore, the degree of integration of the circuit can be increased. 30 and connects to conductor 518 via conductors and plugs formed in layer 631. The conductor 518 preferably functions as the terminal BL.

[0250] <Circuit operation> The circuits shown in FIG. 27(A), (B), (C) and FIG. 28(A) function as a memory device. It is possible.

[0251] The operation of the circuit shown in FIG. 27(B) will be described.

[0252] The circuit shown in FIG. 27B has a characteristic that the potential of the gate of the transistor 491 can be held. By having this, it is possible to write, hold, and read information, as shown below.

[0253] The writing and retention of information will be explained. First, the potential of the terminal WWL is set to This sets the transistor 490 to a potential at which it becomes conductive, thereby making the transistor 490 conductive. The potential of the terminal BL is connected to the gate of the transistor 491 and one of the electrodes of the capacitor 150. That is, the gate of the transistor 491 is electrically connected to the node FN. A certain charge is applied to the memory cell (write). Here, two different potential levels are applied. Either the low-level charge or the high-level charge is given. After that, the potential of the terminal WWL is set to a potential at which the transistor 490 is turned off. This causes the charge to be held (retained) at the node FN.

[0254] By using an oxide semiconductor for the semiconductor layer of the transistor 490, the off-state current can be reduced extremely. Since the capacitance can be made extremely small, the charge on the node FN is retained for a long period of time.

[0255] Next, the reading of information will be explained. A state in which a predetermined potential (constant potential) is applied to the terminal BL Then, when an appropriate potential (read potential) is applied to the terminal CL, the terminal SL is held at the node FN. The potential depends on the amount of charge transferred. If the transistor 491 is an n-channel type, When a high-level charge is applied to the gate of transistor 491, Threshold voltage V th_H A low-level charge is applied to the gate of transistor 491. The apparent threshold voltage V th_L This is because the temperature is lower than that of the The threshold voltage on the output of transistor 491 is the voltage required to turn on the terminal C Therefore, the potential of the terminal CL is V th_H and V th_L Between By setting the potential of the node FN to V0, the charge applied to the node FN can be determined. When a high-level charge is applied to node FN, When the potential is V0 (>V th_H ), transistor 491 is in a "conducting state." If a low-level charge is applied to node FN, the potential of terminal CL becomes V0 (< V th_L ), transistor 491 remains in a "non-conducting state." By determining the potential of the terminal SL, the data stored in the node FN can be read out. can.

[0256] When memory cells are arranged in an array, the information of a desired memory cell is read out. In a memory cell where information is not to be read, the node FN The potential at which transistor 491 is in a "non-conducting state" regardless of the charge applied to it, i.e. V th_H By applying a lower potential to the terminal CL, the information in the desired memory cell can be read. Alternatively, in a memory cell from which information is not read, The potential at which transistor 491 is "on" regardless of the charge applied to FN, Mari, V th_L By applying a higher potential to the terminal CL, only the information of the desired memory cell can be read. It is sufficient to have a configuration in which the information can be read out.

[0257] Next, in the circuit shown in FIG. 27(A), information is written and stored in the same manner as in FIG. 27(B). In FIG. 27A, the transistor 492 is included, so that For example, in order not to read information from other memory cells, the transistor 492 is turned off. By doing so, it may be possible to suppress the leakage current from terminal BL to terminal SL. In addition, in order not to read information from other memory cells during reading, A high voltage is applied to the terminal RWL so that the resistor 492 is in a non-conducting state. In some cases, it is not necessary to provide a voltage to terminal CL.

[0258] The above-described semiconductor device is a transistor using an oxide semiconductor and having an extremely small off-state current. By applying the memory, it is possible to retain the memory contents for a long period of time. Refresh operations are no longer necessary or can be performed very infrequently. Therefore, a semiconductor device with low power consumption can be realized. Even if there is no potential (but it is preferable that the potential is fixed), It is possible to retain the stored contents.

[0259] In addition, the semiconductor device does not require a high voltage to write information, so there is no risk of element deterioration. For example, unlike conventional non-volatile memory, the flow of electrons to the floating gate is Since there is no injection or extraction of electrons from the floating gate, there is no degradation of the insulator. That is, the semiconductor device according to one embodiment of the present invention does not have the same problem as the conventional nonvolatile memory. There is no limit to the number of times that memory can be rewritten, which is a problem with memory, and the reliability of the semiconductor has been dramatically improved. Furthermore, information can be written by turning on or off the transistor. This enables high speed operation.

[0260] The semiconductor device shown in FIG. 27C differs from the semiconductor device shown in FIG. 27B in that it does not include the transistor 491. In this case, the operation is the same as that of the semiconductor device shown in FIG. This makes it possible to write and retain information.

[0261] The reading of data in the semiconductor device shown in FIG. When the capacitor 490 is in a conductive state, the terminal BL in a floating state and the capacitance element 150 are conductive. Charge is redistributed between the terminal BL and the capacitive element 150. As a result, the potential of the terminal BL changes. The amount of change in the potential of the terminal BL is determined by the potential of one of the electrodes of the capacitance element 150 (or the capacitance element It takes on different values ​​depending on the charge stored at 150.

[0262] For example, the potential of one of the electrodes of the capacitance element 150 is V, the capacitance of the capacitance element 150 is C, and the terminal B If the capacitance component of L is CB and the potential of terminal BL before the charge is redistributed is VB0, then The potential of terminal BL after the charge is redistributed is (CB×VB0+C×V) / (CB+C). Therefore, the state of the memory cell is such that one potential V of the capacitance element 150 is V1 and the other potential V 0 (V1>V0), the terminal BL when the potential V1 is held is The potential (=(CB×VB0+C×V1) / (CB+C)) is the potential V0. When the potential of terminal BL is It can be seen that.

[0263] Then, by comparing the potential of the terminal BL with a predetermined potential, information can be read out. .

[0264] In this case, the peripheral circuit for driving the memory cells is, for example, a transistor included in layer 627. A configuration using a resistor 493 or the like may be used.

[0265] The circuit diagram shown in FIG. 28B includes a p-channel transistor 2200 and an n-channel The transistors 2100 are connected in series and the gates of the transistors are connected together. The configuration of the OS circuit is shown in FIG. 28B. In that case, for example, transistor 2200 may be provided in layer 629. The transistor 2100 is provided on the layer 627, and the source electrode or the drain electrode of the transistor is It is preferable to use a conductor provided in the layer 628 or the like for connection to the electrodes and gate electrodes.

[0266] The circuit diagram shown in FIG. 28C shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. The semiconductor device shown in FIG. The device 500 may have a circuit as shown in FIG. 28(C). In that case, for example, a transistor The transistor 2200 is provided on a layer 629, the transistor 2100 is provided on a layer 627, and the transistor A conductor provided in layer 628 or the like for connection of a source electrode, a drain electrode, or a gate electrode It is preferable to use:

[0267] FIG. 28A illustrates an example of a circuit that can be used in a device according to one embodiment of the present invention. vinegar.

[0268] The circuit shown in FIG. 28A includes a capacitor 660a, a capacitor 660b, and a transistor 661a, transistor 661b, transistor 662a, and transistor 662b , an inverter 663a, an inverter 663b, a wiring BL, a wiring BLB, and a wiring W L, wiring CL, and wiring GL.

[0269] In the circuit shown in FIG. 28A, an inverter 663a and an inverter 663b are connected in a ring. The output of the inverter 663b is a memory cell that constitutes a flip-flop. The node from which the signal is output is designated as node VN1, and the output signal of inverter 663a is output. The node where the memory cells are arranged in a matrix is ​​called node VN2. A memory device (memory cell array) can be configured.

[0270] One of the source and drain of the transistor 662a is electrically connected to the wiring BL. The other drain is electrically connected to a node VN1, and the gate is electrically connected to a wiring WL. One of the source and drain of the transistor 662b is electrically connected to the node VN2. The other of the source and drain is electrically connected to the wiring BLB, and the gate is electrically connected to the wiring WL. To be continued.

[0271] One of the source and drain of the transistor 661a is electrically connected to a node VN1. The other of the source and drain is electrically connected to one electrode of the capacitor 660a, and the gate is connected to a wiring GL. Here, the other of the source and drain of the transistor 661a is A node between one electrode of the capacitor 660a and the transistor 660 is referred to as a node NVN1. One of the source and drain of 661b is electrically connected to the node VN2. The other electrode of the capacitor 660b is electrically connected to one electrode of the capacitor 660b, and the gate of the capacitor 660b is electrically connected to the wiring GL. Here, the other of the source and drain of the transistor 661b and the capacitance element 660 The node between one electrode of b and is called node NVN2.

[0272] The other electrode of the capacitor 660a is electrically connected to the wiring CL. One electrode is electrically connected to the wiring CL.

[0273] The conductive state or non-conductive state of the transistor 662a and the transistor 662b is selected by the arrangement. The transistors 661a and 661b can be controlled by applying a potential to the line WL. The selection of the conductive state or non-conductive state of the gate 661b is controlled by the potential applied to the wiring GL. It is possible.

[0274] The write, hold and read operations of the memory cell shown in FIG. do.

[0275] When writing data, a potential corresponding to data 0 or data 1 is first applied to the wiring BL and the wiring BLB. is applied.

[0276] For example, if you want to write data 1, set the line BL to a high-level power supply potential (VDD), The wiring BLB is set to the ground potential. Next, the transistor 662a and the transistor 6 A potential (VH) equal to or higher than the potential obtained by adding VDD to the threshold voltage of 62b is applied.

[0277] Next, the potential of the wiring WL is set to the threshold voltage of the transistor 662a and the transistor 662b. By setting it to less than 1, the data 1 written to the flip-flop will be held.

[0278] When reading, the wiring BL and wiring BLB are set to VDD in advance. Next, By applying VH, the line BL remains at VDD, but the line BLB becomes a transistor. The line BL and the line 663a are discharged to the ground potential. The potential difference between the line BLB is amplified by a sense amplifier (not shown). Data 1 can be read out.

[0279] If you want to write data 0, set the line BL to ground potential and the line BLB to VDD. Then, VH is applied to the wiring WL. a, the flip-flop is written by making the transistor 662b lower than the threshold voltage. When reading, the data 0 is held. By applying VH to the wiring WL, the wiring BLB remains at VDD, but BL is discharged through the transistor 662b and the inverter 663b to the ground potential. The potential difference between the wiring BL and the wiring BLB is amplified by a sense amplifier. Data 0 can be read.

[0280] Therefore, the semiconductor device shown in FIG. 28(A) is a so-called SRAM (Static Random Access Memory). SRAM functions as a flip-flop. Since data is retained using the EEPROM, no refresh operation is required. In addition, the flip-flop uses a capacitance element, Therefore, it is suitable for applications requiring high speed operation.

[0281] In addition, in the semiconductor device shown in FIG. 28A, the node VN 1 to the node NVN1. Similarly, transistor 66 It is possible to write data from node VN2 to node NVN2 via node 1b. The written data sets the transistor 661a or the transistor 661b in a non-conducting state. For example, even if the supply of the power supply potential is stopped, the node VN 1 and node VN2 may be able to hold data.

[0282] Unlike conventional SRAMs, in which data is lost immediately when the power supply voltage is stopped, The semiconductor device shown in (A) can retain data even after the supply of power potential is stopped. Therefore, by appropriately turning on or off the power supply potential, a semiconductor device with low power consumption can be realized. For example, the semiconductor device shown in FIG. This also reduces the power consumption of the CPU.

[0283] The period during which data is held at the nodes NVN1 and NVN2 is the period during which the transistors 6 It can be seen that the change depends on the off-current of the transistors 61a and 661b. In order to extend the data retention period, the transistors 661a and 661b are A transistor with low off-state current may be used for the capacitor 66. The capacitance of the capacitance element 660a and the capacitance of the capacitance element 660b should be increased.

[0284] For example, the transistor 490 and the capacitor 660a are used as the transistor 661a and the capacitor 660a. By using the quantum element 150, data can be stored in the node NVN1 for a long period of time. Similarly, the transistor 490 and the capacitor 150 can be connected to the transistor 66. 1b and the capacitance element 660b, data can be stored in the node NVN2 for a long period of time. Therefore, the transistor 661a and the transistor 661b For details, refer to the description of the transistor 490. For the capacitance element 660a and the capacitance element 660b, refer to the description of the capacitance element 150. .

[0285] The transistor 662a, the transistor 662b, and the inverter 663 shown in FIG. The transistors included in the inverter 663a and the transistors included in the inverter 663b are transistors. At least a transistor 661a, a transistor 661b, a capacitor 660a, and a capacitor 660b. Therefore, the semiconductor device shown in FIG. It can be fabricated without significantly increasing the area occupied by the SRAM compared to conventional SRAM. In some cases, the transistor 662a, the transistor 662b, and the inverter 663a include The transistors included in the inverter 663b are Please refer to the description of Sta 491.

[0286] In the structures shown in FIGS. 1 to 14, 21, 22, and 24, The connection between the source electrode or the drain electrode of the transistor 490 and the capacitance element 150 is shown in FIG. One of the source electrode or the drain electrode of the transistor 661a in the circuit of (A) and a capacitor 660a. Also, the source electrode or drain of the transistor 490 may be connected to the The other of the input electrodes is connected to one of the source electrode or drain electrode of the transistor 491. , the source electrode or drain electrode of the transistor 661a in the circuit of FIG. The other is applied to the connection between the source electrode or the drain electrode of the transistor 662a. Good too.

[0287] [Semiconductor layer 406] The semiconductor layer 406 includes an oxide layer 406a, an oxide layer 406b, and an oxide layer 406c. It is preferred to have a laminated configuration.

[0288] For example, an oxide semiconductor containing indium (In) is used as the semiconductor layer 406. For example, when the oxide semiconductor contains indium, the carrier mobility (electron mobility) is improved. In addition, it is preferable that the oxide semiconductor contains an element M.

[0289] The element M is preferably aluminum, gallium, yttrium or tin. Other elements that can be used for element M include boron, silicon, titanium, iron, and nickel. Ru, Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium However, the element M is the same as above. In some cases, it is acceptable to combine multiple elements of the above. For example, the element M has a bond energy with oxygen of The element M has a high energy. For example, the element M increases the energy gap of an oxide semiconductor. In addition, the oxide semiconductor preferably contains zinc. Semiconductors may be more prone to crystallization if they contain zinc.

[0290] However, the semiconductor layer 406 is not limited to an oxide containing indium. For example, indium oxide, zinc tin oxide, gallium tin oxide, gallium oxide, etc. However, oxides containing zinc, oxides containing gallium, oxides containing tin, etc. may be used. I don't.

[0291] The semiconductor layer 406 is made of, for example, an oxide semiconductor having a wide energy gap. The energy gap of the oxide semiconductor used in the oxide layer 406 is, for example, 2.5 eV or more and 4. 2 eV or less, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3 It is less than .5 eV.

[0292] Oxide semiconductors are formed by sputtering, CVD (Chemical Vapor Deposition) osition) method (MOCVD (Metal Organic Chemical V apor deposition) method, ALD (Atomic Layer Depos) method ition), thermal CVD or PECVD (Plasma Enhanced Ch (including, but not limited to, empirical vapor deposition) MBE (Molecular Beam Epitaxy) method or PLD (Pulse d Laser Deposition) method. Plasma CVD method The MOCVD method, ALD method, or thermal CVD method can provide high-quality films at relatively low temperatures. When a deposition method that does not use plasma is used, damage to the deposition surface is less likely to occur. Furthermore, a film with fewer defects can be obtained.

[0293] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is not easily affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it ideal for achieving high aspect ratios. However, the ALD method is relatively slow in forming a film. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a faster deposition rate. may be preferred.

[0294] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, the film formation By changing the flow rate ratio of the source gas while heating, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition using a vacuum, the time required for deposition is shorter due to the time required for transportation and pressure adjustment. Therefore, the productivity of the transistor and the semiconductor device can be improved. There may be cases where this occurs.

[0295] For example, the semiconductor layer 406 is formed by thermal CVD using InGaZnO X (X>0) Film is formed In the case of trimethylindium (In(CH3)3), trimethylgallium (Ga( The compounds used are dimethylzinc (Zn(CH3)2), and dimethylzinc (Zn(CH3)2). Not limited to the above, triethylgallium (Ga(C2H5 )3) can also be used, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc. can also be used.

[0296] For example, the semiconductor layer 406 may be formed by ALD of InGaZnO X (X>0) Film is formed In this case, In(CH3)3 gas and O3 gas are introduced in sequence to form an InO2 layer. Then, Ga(CH3)3 gas and O3 gas are repeatedly introduced to form a GaO layer. Then, Zn(CH3)2 gas and O3 gas are repeatedly introduced to form a ZnO layer. The order of these layers is not limited to this example. Mixed compounds such as O2 layers, InZnO2 layers, GaInO layers, ZnInO layers, and GaZnO layers Alternatively, a layer may be formed by bubbling H2 with an inert gas such as Ar instead of O3 gas. Although O gas may be used, it is preferable to use O gas that does not contain H. Instead of In(C2H5)3 gas, tris(acetylacetonato)indium(C2H5)3 gas is used. Tris(acetylacetonato)indium may also be used. Also called c)3. Also, instead of Ga(CH3)3 gas, Ga(C2H5)3 gas or tritium gas can be used. Tris(acetylacetonato)gallium may also be used. Gallium is also known as Ga(acac)3. It is also known as Zn(CH3)2 gas or zinc acetate. The gas species is not limited to these.

[0297] When oxide semiconductor is deposited by sputtering, in order to reduce the number of particles, It is preferable to use a target containing M. Also, it is preferable to use an oxide target having a high atomic ratio of element M. When using a target containing indium, the electrical conductivity of the target may be reduced. When using a sintered material, the conductivity of the target can be increased, making DC and AC discharge easier. This makes it easier to handle large-area substrates. This improves the productivity of semiconductor devices. It is possible.

[0298] In addition, when forming an oxide semiconductor film by sputtering, the atomic ratio of the target is I n:M:Zn is 3:1:1, 3:1:2, 3:1:4, 1:1:0.5, 1:1:1, 1 :1:2, 1:4:4, 4:2:4.1 etc. would be good choices.

[0299] When an oxide semiconductor film is formed by a sputtering method, the atomic ratio of the target may deviate. In particular, the atomic ratio of zinc in the target is The atomic ratio of the oxide semiconductor film may be smaller than the atomic ratio of the oxide semiconductor film. The ratio of the number of zinc atoms contained in the get is between 40 and 90 atomic %. This may be the case.

[0300] The oxide layer 406a and the oxide layer 406c are formed of oxide other than the oxygen constituting the oxide layer 406b. It is preferable that the metal layer is made of a material containing one or more of the same metal elements. When such a material is used, the interface between the oxide layer 406a and the oxide layer 406b, and The interface state can be made less likely to occur at the interface between the oxide layer 406c and the oxide layer 406b. This makes it difficult for carriers to be scattered or captured at the interface, and the field effect of the transistor is improved. It is also possible to improve the mobility of the transistor. Therefore, it is possible to realize a semiconductor device having good electrical characteristics. This makes it possible.

[0301] The thickness of the oxide layer 406a and the oxide layer 406c is preferably 3 nm or more and 100 nm or less. The thickness of the oxide layer 406b is preferably 3 nm or more and 50 nm or less. 00 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0302] The oxide layer 406b is an In-M-Zn oxide (an oxide containing In, the element M, and Zn). and when the oxide layer 406a and the oxide layer 406c are also In-M-Zn oxide, The oxide layer 406a and the oxide layer 406c are formed by mixing In:M:Zn=x1:y1:z1 [atomic number The oxide layer 406b has an atomic ratio of In:M:Zn=x2:y2:z2. The oxide layer 406a, the oxide layer 406c, and the oxide layer 406b are formed by applying a ratio of 1 / x1 to y2 / x2. Preferably, y1 / x1 is 1.5 times larger than y2 / x2. The oxide layer 406a, the oxide layer 406c, and the oxide layer 406b are selected so that the thickness of the oxide layer 406a, the oxide layer 406c, and the oxide layer 406b is larger than the thickness of the oxide layer 406b. More preferably, the oxide layer 406a has y1 / x1 at least twice as large as y2 / x2. The oxide layer 406c and the oxide layer 406b are selected. More preferably, y1 / x1 is The oxide layer 406a, the oxide layer 406c, and the oxide layer 406d are each three times larger than y2 / x2. In this case, in the oxide layer 406b, if y2 is equal to or larger than x2, This is preferable because it can provide stable electrical characteristics to the transistor. However, y2 must be three times larger than x2. If the value exceeds this value, the field effect mobility of the transistor will decrease, so y2 should be three times x2. The oxide layer 406a and the oxide layer 406c each have the above structure. As a result, the oxide layers 406a and 406c have a smaller oxygen deficiency than the oxide layer 406b. It is possible to make the layer less susceptible to defects.

[0303] When the oxide layer 406a is an In-M-Zn oxide, the sum of In and M is 100a. When In is less than 50 atomic %, M is preferably less than 50 atomic %. ic% or more, more preferably In is less than 25 atomic % and M is 75 atomic % or less. When the oxide layer 406b is an In-M-Zn oxide, In and When the sum of M is 100 atomic %, In is preferably higher than 25 atomic %. Preferably, M is less than 75 atomic %, and more preferably, In is more than 34 atomic %. In addition, the oxide layer 406c is an In-M-Zn oxide. When the sum of In and M is 100 atomic %, In is preferably 50 atomic %. %, M is higher than 50 atomic %, and more preferably In is 25 atomic %. The oxide layer 406c is made of an oxide material. Alternatively, the same type of oxide as that of the oxide layer 406a may be used.

[0304] For example, the oxide layer 406a containing In or Ga and the oxide layer 406b containing In or Ga Layer 406c is In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, 1:6: In-Ga-ZnO oxide formed using targets with atomic ratios of 4, 1:9:6, etc. Formed using targets with atomic ratios such as In:Ga=1:9 or 7:93. The oxide layer 406b may be, for example, an In-Ga oxide. Using targets with atomic ratios of In:Ga:Zn=1:1:1 or 3:1:2, The oxide layer 406a and the oxide layer 406b can be formed of In-Ga-Zn oxide. The atomic ratios of the oxide layer 406b are the above atomic ratios plus or minus 20 as an error. Includes % variation.

[0305] The oxide layer 406b has a higher electron affinity than the oxide layer 406a and the oxide layer 406c. For example, the oxide layer 406b is made of the oxide layer 406a and the oxide layer 406b. The electron affinity of the layer 406c is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or less. More preferably, the oxide is 0.15 eV or more and 0.4 eV or less. The electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0306] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the oxide layer 406c contains indium gallium oxide. The Ga atom ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more. More preferably, it is set to 90% or more.

[0307] However, the oxide layer 406a and / or the oxide layer 406c is made of gallium oxide. For example, when gallium oxide is used as the oxide layer 406c, the conductor 416a Alternatively, the leakage current occurring between the conductor 416b and the conductor 404 can be reduced. That is, the off-state current of the transistor 490 can be reduced.

[0308] The oxide layer 406a and the oxide layer 406c have a higher electron affinity than, for example, the oxide layer 406b. Since the force is smaller, it is closer to an insulator than the oxide layer 406b. Therefore, when a gate voltage is applied, Among the oxide layers 406a, 406b, and 406c, the oxide layer 406b Channels are easily formed in the

[0309] In addition, a transistor using an oxide semiconductor in the semiconductor layer where the channel is formed ("OS transistor") In order to give stable electrical characteristics to the oxide semiconductor, it is necessary to reduce the insulators in the oxide semiconductor. The oxide layer 406b is made intrinsic or substantially intrinsic by reducing impurities and oxygen vacancies. For example, the oxide layer 406b may be formed of an oxide semiconductor that can be regarded as being non-oxidative. By supplying at least the oxide layer 4, oxygen vacancies may be reduced. The channel formation region in the insulating film 06b is an oxide semiconductor that can be regarded as intrinsic or substantially intrinsic. is preferred.

[0310] In addition, at least the oxide layer 406b of the semiconductor layer 406 is made of CAAC-OS (CA xis Aligned Crystalline Oxide Semiconductor It is preferable to use the CAAC-OS. Explain in detail.

[0311] The CAAC-OS has a dielectric anisotropy. The dielectric constant in the c-axis direction is larger than that in the b-axis direction. The transistor with the gate electrode arranged in the c-axis direction using CAAC-OS has Since the dielectric constant of is large, the electric field generated from the gate electrode easily reaches the entire CAAC-OS. This makes it possible to reduce the subthreshold swing value (S value). Transistors that use CAAC-OS as the body film are less susceptible to increases in S value due to miniaturization.

[0312] In addition, the dielectric constant of CAAC-OS in the a-axis and b-axis directions is small, so the source and drain Therefore, the effect of the electric field between the insulators is reduced. This makes it difficult for defects such as short circuiting to occur, thereby improving the reliability of the transistor.

[0313] Here, the channel length modulation effect is the effect that occurs when the drain voltage is higher than the threshold voltage. This refers to the phenomenon in which the depletion layer expands from the drain side, shortening the effective channel length. The channel effect is a phenomenon in which the electrical properties such as the threshold voltage decrease due to the shortening of the channel length. The smaller the transistor, the greater the deterioration of electrical characteristics due to these phenomena. is likely to occur.

[0314] [Energy band structure of oxide semiconductor film] Here, the oxide layer 406a, the oxide layer 406b, and the oxide layer 406c are stacked. The function and effect of the semiconductor layer 406 will be described with reference to the energy band shown in FIG. FIG. 37 shows the energy distribution of the channel formation region of the transistor 490. The Gee band structure is shown.

[0315] In Figure 37, Ec382, Ec383a, Ec383b, Ec383c, and Ec386 are The insulator 402, the oxide layer 406a, the oxide layer 406b, the oxide layer 406c, and the insulator 406b are respectively 4 shows the energy of the conduction band minimum of the insulator 412.

[0316] Here, the electron affinity is the difference between the vacuum level and the energy at the top of the valence band (the "ionization potential"). It is also called the potential. It is the value obtained by subtracting the energy gap from the potential. The chip is equipped with a spectroscopic ellipsometer (HORIBA JOBIN YVON UT-300 The energy difference between the vacuum level and the top of the valence band can be measured using ultraviolet photoelectron Spectroscopic analysis (UPS:Ultraviolet Photoelectron Spectrum) This can be measured using a fluoroscopy device (PHI VersaProbe).

[0317] The In- The energy gap of Ga-Zn oxide is about 3.5 eV and the electron affinity is about 4.5 eV. In addition, the In was formed using a target with an atomic ratio of In:Ga:Zn=1:3:4. The energy gap of Ga-Zn oxide is about 3.4 eV, and the electron affinity is about 4.5 eV. In addition, the I was formed using a target with an atomic ratio of In:Ga:Zn=1:3:6. The energy gap of n-Ga-Zn oxide is about 3.3 eV, and the electron affinity is about 4.5 eV. In addition, the film was formed using a target with an atomic ratio of In:Ga:Zn=1:6:2. The energy gap of In-Ga-Zn oxide is about 3.9 eV, and the electron affinity is about 4.3 e V. The target was formed with an atomic ratio of In:Ga:Zn=1:6:8. The energy gap of the In-Ga-Zn oxide is about 3.5 eV and the electron affinity is about 4.4 The atomic ratio of In:Ga:Zn was 1:6:10. The energy gap of the synthesized In-Ga-Zn oxide is about 3.5 eV, and the electron affinity is about 4 0.5 eV. In addition, a target with an atomic ratio of In:Ga:Zn=1:1:1 was used. The energy gap of the formed In-Ga-Zn oxide is about 3.2 eV, and the electron affinity is about The atomic ratio of the target was In:Ga:Zn=3:1:2. The energy gap of the In-Ga-Zn oxide formed by this method is about 2.8 eV, and the electron affinity is It is about 5.0 eV.

[0318] Since the insulators 402 and 412 are insulators, Ec382 and Ec386 are It is closer to the vacuum level than Ec383a, Ec383b, and Ec383c (it has a smaller electron affinity). ).

[0319] Also, Ec383a is closer to the vacuum level than Ec383b. a is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more, higher than Ec383b 0.7 eV or less, more preferably 0.15 eV to 0.4 eV, close to the vacuum level is preferred.

[0320] Also, Ec383c is closer to the vacuum level than Ec383b. c is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more, higher than Ec383b 0.7 eV or less, more preferably 0.15 eV to 0.4 eV, close to the vacuum level is preferred.

[0321] Here, between the oxide layer 406a and the oxide layer 406b, there is a layer of oxide In some cases, the oxide layer 406b may have a mixed region with the oxide layer 406b. Between the oxide layer 406b and the oxide layer 406c, there may be a mixed region of the oxide layer 406b and the oxide layer 406c. The mixed region has a low interface state density. The stack of the oxide layer 406c and the oxide layer 406b has a continuous energy distribution near the interface between the stack. (also called a continuous junction).

[0322] At this time, the electrons are not transferred to the oxide layer 406a and the oxide layer 406c but to the oxide layer Therefore, the oxide layer 406a and the oxide layer 406b are mainly moved. the interface state density at the interface between the oxide layer 406b and the oxide layer 406c; By lowering the surface state density, the movement of electrons in the oxide layer 406b is inhibited. Therefore, the on-state current of the transistor 490 can be increased.

[0323] In addition, the interface between the oxide layer 406a and the insulator 402 and the interface between the oxide layer 406c and the insulator 41 Although a trap level 390 due to impurities or defects may be formed near the interface of 2, The oxide layer 406a and the oxide layer 406c are present, and therefore the oxide layer 406b and the corresponding Therefore, the distance between the trap level and the ion beam can be increased.

[0324] When the transistor 490 has an s-channel structure, the oxide layer 406b Thus, the thicker the oxide layer 406b, the larger the channel area. That is, the thicker the oxide layer 406b, the higher the on-state current of the transistor 490. For example, the thickness can be set to 20 nm or more, preferably 40 nm or more, and more preferably The oxide layer 406b has a region having a thickness of 60 nm or more, more preferably 100 nm or more. However, the productivity of a semiconductor device including the transistor 490 may decrease. Therefore, for example, the thickness is 300 nm or less, preferably 200 nm or less, and more preferably 1 The oxide layer 406b may have a thickness of less than 50 nm in some areas.

[0325] In order to increase the on-state current of the transistor 490, the thickness of the oxide layer 406c is For example, less than 10 nm, preferably 5 nm or less, and more preferably The oxide layer 406c may have a region of 3 nm or less. The oxide layer 406b in which the channel is formed is doped with an element other than oxygen constituting the adjacent insulator ( It has the function of blocking the intrusion of oxides (hydrogen, silicon, etc.). The layer 406c preferably has a certain thickness, for example, 0.3 nm or more. or an oxide layer 406c having a region with a thickness of 1 nm or more, more preferably 2 nm or more. This can be done as follows.

[0326] Also, in order to increase reliability, the oxide layer 406a is thick and the oxide layer 406c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 4 0 nm or more, more preferably 60 nm or more. By increasing the thickness of the oxide layer 406a, the oxide layer 406 and the adjacent insulator can be prevented from being damaged. The distance from the interface with a to the oxide layer 406b in which the channel is formed can be increased. However, the productivity of a semiconductor device having the transistor 490 may be reduced. For example, a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less. The oxide layer 406a may have a thick region.

[0327] Note that silicon in an oxide semiconductor can become a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the oxide layer 406b, the more preferable it is. Between the inorganic layer 406b and the oxide layer 406a, for example, secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry (1×1 0 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, more Preferably 2 x 10 18 atoms / cm 3 The silicon concentration is less than 100 nm. In addition, between the oxide layer 406b and the oxide layer 406c, a concentration of 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, even more preferred Or 2×10 18 atoms / cm 3 The silicon concentration is less than 100 nm.

[0328] In order to reduce the hydrogen concentration in the oxide layer 406b, the oxide layer 406a and the oxide It is preferable to reduce the hydrogen concentration in the oxide layer 406c. is 2×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Further details are below. Preferably 5 x 10 18 atoms / cm 3 The hydrogen concentration range is as follows: In order to reduce the nitrogen concentration in the oxide layer 406b, the oxide layer 406a and the oxide layer 406 It is preferable to reduce the nitrogen concentration in the oxide layer 406a and the oxide layer 406c. In MS, 5 × 10 19 atoms / cm 3 Less than 5 x 10 18 atom s / cm 3 Less than or equal to 1×10 18 atoms / cm 3 The following is more preferable: is 5 x 10 17 atoms / cm 3 The nitrogen concentration ranges as follows:

[0329] Note that when copper is mixed into an oxide semiconductor, electron traps may be generated. A jump may cause the threshold voltage of a transistor to shift in the positive direction. Therefore, it is preferable that the copper concentration on the surface or inside of the oxide layer 406b is low. Layer 406b, copper concentration 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 or less, or 1×10 18 atoms / cm 3 It is preferred that the region stomach.

[0330] The above three-layer structure is an example. For example, the oxide layer 406a or the oxide layer 406c Alternatively, a two-layer structure may be used. On or under the layer 406c, an oxide layer 406a, an oxide layer 406b, and an oxide layer 406 Alternatively, the semiconductor layer may have a four-layer structure having any one of the semiconductors exemplified as c. On the oxide layer 406a, under the oxide layer 406a, on the oxide layer 406c, and under the oxide layer 406c. At least two of the oxide layers 406a, 406b and 406 It may also be an n-layer structure (n is an integer of 5 or more) having any one of the semiconductors exemplified as c. I don't.

[0331] In particular, the transistor 490 illustrated in this embodiment has an oxidized The upper surface and side surfaces of the oxide layer 406b are in contact with the oxide layer 406c, and the lower surface of the oxide layer 406b is in contact with the oxide layer 406c. The oxide layer 406 is formed in contact with the oxide layer 406a (see FIG. 5B). b is covered with the oxide layer 406a and the oxide layer 406c. The effect can be further reduced.

[0332] The band gaps of the oxide layer 406a and the oxide layer 406c are the same as those of the oxide layer 40 It is preferable that the band gap is wider than that of 6b.

[0333] According to one embodiment of the present invention, a transistor with little variation in electrical characteristics can be realized. Therefore, a semiconductor device with little variation in electrical characteristics can be realized. According to one embodiment of the present invention, a highly reliable transistor can be realized. It is possible to realize a highly reliable semiconductor device.

[0334] In addition, the band gap of oxide semiconductors is 2 eV or more, so A transistor that uses an oxide semiconductor for a conductor film can have an extremely small off-state current. Specifically, when the source-drain voltage is 3.5 V and the temperature is 25°C, The off-state current per 1 μm of channel width is 1×10 -20 Less than A, 1×10 -22 Less than A, yes Iwa 1×10 -24 That is, the on-off ratio can be increased by 20 orders of magnitude to less than 15 A. It can contain zero or less digits.

[0335] According to one embodiment of the present invention, a transistor with low power consumption can be realized. As a result, a semiconductor device with low power consumption can be realized.

[0336] (Embodiment 2) In this embodiment, a structure of an oxide semiconductor will be described.

[0337] <Structure of oxide semiconductor> Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous l Examples include amorphous oxide semiconductors, amorphous oxide semiconductors, etc.

[0338] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC- These include OS, polycrystalline oxide semiconductor, and nc-OS.

[0339] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond length is short. In other words, it is a structure that has discrete order but does not have long-range order.

[0340] On the other hand, in the case of an essentially stable oxide semiconductor, In addition, it cannot be called an oxide semiconductor because it is not isotropic. The oxide semiconductor, which is not amorphous (for example, has a periodic structure in a microscopic region), is transformed into a completely amorphous oxide. However, a-like OS is a semiconductor that can be used in a small area. Although it has a periodic structure, it has voids and is an unstable structure. In terms of physical properties, it can be said that the semiconductor is close to an amorphous oxide semiconductor.

[0341] <caac-os> First, let me explain about CAAC-OS.

[0342] CAAC-OS is an oxide that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0343] Transmission Electron Microscope (TEM) A combined analysis image (high resolution) of the bright-field image and diffraction pattern of CAAC-OS was obtained by using a microscope. When observing a high-resolution TEM image, multiple pellets can be confirmed. On the other hand, in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is difficult to clearly confirm the presence of the CAAC-OS at the grain boundaries. It can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0344] The following describes the CAAC-OS observed by TEM. 1 shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction is required. The spherical aberration corrector function was used. In particular, this is called a Cs-corrected high-resolution TEM image. For example, a Cs-corrected high-resolution TEM image can be obtained by This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0345] An enlarged Cs-corrected high-resolution TEM image of region (1) in Figure 45(A) is shown in Figure 45(B). From Figure 45(B), it can be confirmed that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). Or it reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0346] As shown in FIG. 45(B), CAAC-OS has a characteristic atomic arrangement. ) shows the characteristic atomic arrangement with auxiliary lines. ) the size of each pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the inclination between the plate and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). CAAC-OS is also used as a C-Axis Aligned Nanoclip The semiconductor may also be referred to as an oxide semiconductor having metal ions.

[0347] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on the substrate 5120 were The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 45(D)). Between the pellets observed in FIG. 45(C), The portion where the inclination occurs corresponds to the area 5161 shown in FIG.

[0348] FIG. 46(A) shows the C The s-corrected high-resolution TEM images are shown for regions (1), (2) and (3) in FIG. ) are enlarged Cs-corrected high-resolution TEM images shown in Fig. 46(B), Fig. 46(C), and Fig. 46(D), respectively. As shown in Figure 46(D), from Figure 46(B), Figure 46(C) and Figure 46(D), the pellet It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0349] Next, C was analyzed by X-ray diffraction (XRD). We will explain AAC-OS. For example, CAAC-O with InGaZnO4 crystals When the out-of-plane structural analysis is performed on S, the result is as shown in Figure 47(A). As shown in the figure, a peak may appear at a diffraction angle (2θ) of around 31°. Since this is attributed to the (009) plane of the ZnO4 crystal, it is believed that the CAAC-OS crystal has a c-axis orientation. It can be seen that the crystal has a c-axis oriented in a direction substantially perpendicular to the surface on which the crystal is formed or to the upper surface.

[0350] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31 In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks in the vicinity indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is a structure obtained by the out-of-plane method. The analysis shows a peak at 2θ around 31° and no peak at 2θ around 36°.

[0351] On the other hand, in-pla, X-rays are incident on CAAC-OS from a direction nearly perpendicular to the c-axis. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I It is attributed to the (110) plane of the crystal of nGaZnO4. In the case of CAAC-OS, 2θ is set to 5 The sample was fixed at approximately 6° and analyzed while rotating around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears, as shown in FIG. On the other hand, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane, as shown in Figure 47(C). Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and the b-axis is irregular.

[0352] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, a probe diameter of 300 nm was used parallel to the sample surface. When an electron beam is incident on the sample, a diffraction pattern (selected area transmission electron diffraction) as shown in FIG. This diffraction pattern may appear due to the InGaZnO4 The spots due to the (009) plane of the crystal are included. Therefore, even by electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis faces the surface to be formed or the upper surface. On the other hand, when the probe was applied perpendicular to the sample surface, The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in FIG. 8(B), a ring-shaped diffraction pattern is observed. Therefore, electron diffraction also It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. In addition, the first ring in FIG. 48(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and the like. This is thought to be due to the (110) surface, etc.

[0353] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the generation of defects, so the opposite view can be taken. Therefore, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0354] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0355] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can act as carrier traps and In some cases, the GaN layer may act as a carrier generation source by capturing hydrogen.

[0356] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. There is. Specifically, 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than 100 Such an oxide semiconductor can be a high-purity intrinsic or The CAAC-OS is essentially a high-purity intrinsic oxide semiconductor. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0357] <nc-os> Next, we will explain nc-OS.

[0358] In the high-resolution TEM image, the nc-OS is divided into two regions: one where the crystals can be confirmed, and the other where the clear The crystalline parts in nc-OS are In most cases, the size is between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In some cases, the nanocrystals are not clearly visible in the pellets of CAAC-OS. Therefore, in the following, the crystalline part of nc-OS is referred to as the pellet. There is a chance to call.

[0359] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. For example, the nc-OS may be a pellet with a larger diameter than the pellet. When X-rays are used, the peaks that indicate the crystal planes are In addition, for nc-OS, the probe diameter is larger than the pellet (e.g., 50 When electron diffraction is performed using an electron beam of 1 nm or more, a halo-like diffraction pattern is produced. On the other hand, for nc-OS, pellets with sizes close to or smaller than the pellets were observed. When nanobeam electron diffraction is performed using an electron beam with a lobe diameter, spots are observed. When nanobeam electron diffraction was performed on nc-OS, high brightness regions were observed in a circular (ring-like) pattern. In addition, multiple spots may be observed within a ring-shaped area. There may be cases where this occurs.

[0360] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc -OS with RANC (Random Aligned nanocrystals) The oxide semiconductor or NANC (Non-Aligned Nanocrystal The semiconductor may also be referred to as an oxide semiconductor having a structure including a metal oxide layer.

[0361] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0362] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a semiconductor.

[0363] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen, and areas where crystals can be seen. and areas where it is not possible to

[0364] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the change in structure due to electron irradiation.

[0365] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (hereinafter referred to as sample B) and CAAC-OS (hereinafter referred to as sample C) are prepared. Both samples are In-Ga-Zn oxides.

[0366] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that all the materials have crystalline parts.

[0367] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, six of which are layered in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing between the crystals is 0.28 nm to 0.30 nm are considered to be crystal parts of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0368] Figure 49 shows an example of investigating the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes is the size of the crystal part. It can be seen that the crystalline part of the ke OS grows in size according to the cumulative dose of electron irradiation. Specifically, as shown by (1) in Figure 49, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus), which was 4.2×10 8 e - / n m 2 On the other hand, in the nc-O For S and CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in Figure 49, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. It can be seen that.

[0369] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not seen as a nc-OS or CAAC-OS. It is clear that it has an unstable structure compared to the OS.

[0370] In addition, because of the porosity, a-like OS is more difficult to treat than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is The density of the nc-OS and the CAA The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0371] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0372] In some cases, single crystals of the same composition do not exist. In such cases, crystals of different compositions may be used in any ratio. By combining single crystals of the desired composition, the density equivalent to that of a single crystal of the desired composition can be estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate the size of the single crystal by combining different types of single crystals.

[0373] As described above, oxide semiconductors have various structures and each structure has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the CAAC-OS and CAAC-OS.

[0374] (Embodiment 3) In this embodiment, at least the transistors described in the embodiment can be used. Next, a CPU including the storage device described in the above embodiment will be described.

[0375] FIG. 50 shows an example of a CPU using the storage device described in the previous embodiment as at least a part thereof. FIG.

[0376] The CPU shown in FIG. 50 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. tic logic unit, ALU controller 1192, instruction action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, a SOI substrate, A plate, a glass substrate, etc. are used. The ROM 1199 and the ROM interface 1189 are It may be provided on a separate chip. Of course, the CPU shown in FIG. 50 is a simplified version of the configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, A configuration including the CPU or arithmetic circuit shown in FIG. 50 is considered as one core, and a configuration including multiple such cores is considered as Alternatively, each core may be configured to operate in parallel. The number of bits that can be handled by a circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits, It can be, for example, a .

[0377] The instructions input to the CPU via the bus interface 1198 are The signal is input to the input decoder 1193, decoded, and then passed to the ALU controller 1192, the input The interrupt controller 1194, the register controller 1197, the timing controller It is entered into RA 1195.

[0378] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to control the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it. It generates an address and reads or writes register 1196 depending on the CPU state. .

[0379] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. Supplied to various circuits.

[0380] In the CPU shown in FIG. 50, a register 1196 is provided with a memory cell.

[0381] In the CPU shown in FIG. 50, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or the capacity Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. When data retention in the capacitive element is selected, rewriting data to the capacitive element The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0382] FIG. 51 is an example of a circuit diagram of a memory device that can be used as the register 1196. The storage device 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 in which memory data is not volatile, a switch 1203, a switch 1204, and a logic The circuit includes an element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitance element 1208, a transistor 1209, and a transistor 1210. The memory device 1200 may include a diode, a resistor, an inductor, etc., as necessary. The transistor 1209 is an oxide semiconductor. It is preferable that the transistor 1209 has a channel formed in the semiconductor layer. As an example, the transistor 490 described in the above embodiment can be referred to.

[0383] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the memory device 1200 is stopped, the transistor 12 The gate of 09 is supplied with ground potential (0V) or a potential that turns off transistor 1209. For example, the gate of the transistor 1209 is connected to the load such as a resistor. It is configured to be grounded.

[0384] Here, for example, the source electrode or the drain electrode of the transistor 490 in the structure shown in FIG. The connection between one of the drain electrodes and the capacitance element 150 is made by the transistor 1209 in the circuit of FIG. This may be applied to the connection between one of the source electrode or the drain electrode and the capacitor element 1208. In addition, the other of the source electrode or the drain electrode of the transistor 490 and the other of the source electrode or the drain electrode of the transistor 491 The gate electrode is connected to the source electrode of the transistor 1209 in the circuit of FIG. This may be applied to the connection between one of the drain electrodes and the gate electrode of the transistor 1210 .

[0385] The switch 1203 is a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first transistor 1214 of the switch 1203 is used. The terminal corresponds to one of the source and drain of the transistor 1213, and the first terminal of the switch 1203. The terminal 2 corresponds to the other of the source and drain of the transistor 1213, and the terminal 2 corresponds to the other of the source and drain of the switch 1203. The first terminal and the second terminal are connected to each other by a control signal RD input to the gate of the transistor 1213. Conduction or non-conduction between the terminals of the transistor 1213 (i.e., the on or off state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of a transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the The switch 1204 is connected to the gate of the transistor 1214. A control signal RD is input to the first terminal and the second terminal to establish or break continuity (i.e., The on or off state of transistor 1214 is selected.

[0386] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The other of the two is electrically connected to the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213). The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source terminal of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and a first terminal of the switch 1204 (one of the source and drain of the transistor 1214 ), an input terminal of a logic element 1206, and one of a pair of electrodes of a capacitor 1207; are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (such as GND) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitance element 120. The other of the pair of electrodes 8 is connected to a wiring capable of supplying a low power supply potential (for example, GND The power supply is electrically connected to the power supply line.

[0387] The capacitors 1207 and 1208 are used to reduce parasitic capacitance of transistors and wirings. It is possible to omit it by making active use of it.

[0388] A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are connected to a control signal RD, which is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the There is no continuity between the two terminals.

[0389] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 51, the signal output from the circuit 1201 corresponds to the In the example shown, the other of the source and drain of the switch 1203 is connected to the source of the transistor 1209. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value of the inverted signal is inverted by the logic element 1206 and is output via the circuit 1220. The signal is then input to the circuit 1201.

[0390] In FIG. 51, the second terminal of the switch 1203 (the source of the transistor 1213) The signal output from the other drain is routed through logic element 1206 and circuit 1220. The second terminal of the switch 1203 is connected to the first terminal of the switch 1203. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal with the inverted logical value of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the input terminal can be input to the node.

[0391] In addition, in FIG. 51, among the transistors used in the memory device 1200, The transistors other than the transistor 1209 are formed of a layer or a substrate 11 made of a semiconductor other than an oxide semiconductor. 90. For example, a silicon layer or The memory device may be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the device 1200 are transistors whose channels are formed in oxide semiconductor layers. Alternatively, the memory device 1200 may include transistors other than the transistor 1209. In addition, a transistor in which a channel is formed in an oxide semiconductor layer may be included. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be formed by

[0392] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0393] In the semiconductor device according to one embodiment of the present invention, a power supply voltage is not supplied to the memory device 1200. During this period, data stored in the circuit 1201 is transferred to the capacitor 12 in the circuit 1202. It can be retained by 08.

[0394] In addition, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer varies depending on the crystallinity. The off-state current is significantly lower than that of a transistor having a channel formed in silicon. Therefore, by using the transistor as the transistor 1209, Even when the power supply voltage is not supplied to the capacitor 1200, the signal held in the capacitor 1208 remains constant for a long period of time. In this way, the storage device 1200 can maintain the stored contents ( It is possible to retain the data.

[0395] In addition, by providing the switches 1203 and 1204, the precharge operation Since the circuit 1201 is a memory element that performs the above-mentioned operation after the power supply voltage is restarted, This shortens the time it takes to restore the original data.

[0396] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory device 1200 is restarted. After the signal is released, the signal held by the capacitive element 1208 is transferred to the transistor 1210 in the state (on or off state) and can be read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0397] Such a storage device 1200 may be a register or cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, or multiple logic circuits, the power can be stopped for a short period of time, reducing power consumption. can be suppressed.

[0398] In the present embodiment, the storage device 1200 is used as a CPU. The 1200 is equipped with a DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device) and other LSIs, Also supports RF-ID (Radio Frequency Identification) It is possible to use.

[0399] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0400] (Embodiment 4) In this embodiment, the RF tag including the storage device exemplified in the above embodiment will be described with reference to FIG. 2 will be used to explain.

[0401] The RF tag in this embodiment has a memory circuit inside and stores necessary information in the memory circuit. The information is stored in the memory, and information is exchanged with the outside world using a non-contact means, for example, wireless communication. Due to these characteristics, RF tags can identify items by reading their individual information. It can be used for individual authentication systems. Extremely high reliability is required.

[0402] The structure of an RF tag will be described with reference to FIG. 52. FIG. 52 is a block diagram showing an example of the structure of an RF tag. FIG.

[0403] As shown in FIG. 52, an RF tag 800 includes a communicator 801 (such as an interrogator or a reader / writer). An antenna 802 connected to the The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 804, and a 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor having the rectifying effect included in the demodulation circuit 807 is sufficiently suppressed. A material capable of suppressing the electric field, such as an oxide semiconductor, may be used. This suppresses the deterioration of the rectification effect caused by the reverse current and prevents the output of the demodulation circuit from becoming saturated. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linear. The data transmission format is a pair of coils arranged facing each other and communication is carried out by mutual induction. The electromagnetic coupling method uses electromagnetic fields to communicate, the electromagnetic induction method uses radio waves to communicate, The RF tag 800 shown in this embodiment is compatible with any of these three methods. It can also be used in formulas.

[0404] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 805 is a filter for adjusting an input AC signal generated by receiving a radio signal through the antenna 804. For example, the current is rectified by half-wave double voltage rectification, and the rectified signal is averaged by a capacitive element provided in the latter stage. The rectifier circuit 805 is a circuit for smoothing the input potential. A limiter circuit may be provided on the output side or on the input side. When the internally generated voltage is large, power above a certain level is not input to the downstream circuit. This is a circuit for controlling the above.

[0405] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0406] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0407] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds input information, such as a row decoder, a column decoder, a memory area, etc. The ROM 811 stores a unique number (ID) and outputs the information according to the processing. This is a circuit for doing so.

[0408] It should be noted that the above-mentioned circuits can be appropriately selected or omitted as necessary.

[0409] Here, the memory device described in the above embodiment can be used as the memory circuit 810. By using the memory device described in the above embodiment as the memory circuit 810, Since the information can be retained even when the power is cut off, it can be used effectively as an RF tag. Furthermore, in the memory device according to one embodiment of the present invention, the power (voltage) required for writing data is smaller than that of the conventional memory device. Since it is significantly smaller than non-volatile memory, the maximum communication speed when reading and writing data is It is also possible to eliminate the difference in distance. Therefore, it is possible to suppress the occurrence of malfunction or erroneous writing.

[0410] The storage device of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must A separate command is provided to write data, so that users cannot freely rewrite it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to each RF tag that is produced, only good products are shipped. This means that the unique numbers of products will be discontinuous after shipment. This makes it easier to manage customers' accounts after products are shipped.

[0411] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0412] (Embodiment 5) In this embodiment, a usage example of an RF tag according to one embodiment of the present invention will be described with reference to FIG. RF tags are used in a wide range of applications, including bills, coins, securities, and unregistered securities. Bonds, certificates (driver's licenses, resident cards, etc., see Figure 53 (A)), recording media (DVDs, videos, etc.) Deotapes, etc., see Figure 53(B), packaging containers (wrapping paper, bottles, etc., see Figure 53(C) (See Figure 53(D)), vehicles (bicycles, etc.), personal belongings (bags, glasses, etc.), food, Plants, animals, the human body, clothing, daily necessities, medical products including medicines and pharmaceuticals, or electronic devices ( Liquid crystal display devices, EL display devices, television sets, or mobile phones) or other articles, It can be used by attaching it to tags (see Figure 53 (E) and Figure 53 (F)) to each item. can.

[0413] The RF tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface of a device. It is fixed to the object. For example, in a book, it is embedded in the paper and the packaging is made of organic resin. If the RF terminal is used, it is embedded in the organic resin and fixed to each article. The 4000 is small, thin, and lightweight, so even after it is attached to an object, it does not lose its functionality. In addition, the design of banknotes, coins, securities, bearer bonds, or certificates is not affected. By providing an RF tag 4000 according to one embodiment of the present invention to a document or the like, an authentication function is provided. This authentication function can be used to prevent counterfeiting. The present invention can be applied to vessels, recording media, personal belongings, food, clothing, household goods, electronic devices, etc. By attaching an RF tag according to one embodiment, the efficiency of a system such as an inspection system can be improved. In addition, even in the case of vehicles, the RF tag according to one embodiment of the present invention can be attached. This can improve security against theft and the like.

[0414] As described above, the RF tag according to one aspect of the present invention can be used for each of the applications described in this embodiment. This reduces the power consumption during operation, including writing and reading information, and therefore the maximum communication distance It is also possible to store information for a very long time even when the power is cut off. Since the data can be stored for a long period of time, it can be used for applications where the frequency of writing and reading is low. can.

[0415] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0416] (Embodiment 6) The semiconductor device of one embodiment of the present invention may include a display panel. The semiconductor device according to one embodiment of the present invention may be used in a circuit for driving the semiconductor device. The present embodiment may include a display panel and the semiconductor device described in the other embodiments. In this embodiment, a configuration example of the display panel will be described.

[0417] [Configuration example] FIG. 54(A) is a top view of a display panel of one embodiment of the present invention, and FIG. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one embodiment of the present invention. FIG. 54C is a circuit diagram illustrating a display panel according to one embodiment of the present invention. A circuit for explaining a pixel circuit that can be used when an organic EL element is applied to a pixel FIG.

[0418] The transistors disposed in the pixel portion can be formed according to the above-described embodiment. For example, the transistor 490 described in the above embodiment can be referred to. Since it is easy to make the transistor an n-channel type, the driver circuit is an n-channel type transistor. A part of the driver circuit, which can be composed of transistors, is placed on the same substrate as the transistors in the pixel area. In this manner, the transistor described in the above embodiment is used in the pixel portion or the driver circuit. This makes it possible to provide a highly reliable display device.

[0419] Here, the transistor disposed in the pixel portion of the display panel and the n-channel type A part of a driver circuit that can be formed using a transistor is formed on the layer 629 shown in the above embodiment. In this case, it is preferable to provide a transistor in the driver circuit. The driver circuit portion and the pixel portion may be provided in the layer 627 shown in the embodiment mode. The electrical connection may be made via a wiring provided in the layer 628 shown in the embodiment mode.

[0420] An example of a block diagram of an active matrix display device is shown in FIG. On the substrate 700, a pixel section 701, a first scanning line driving circuit 702, a second scanning line driving circuit 703, and a The pixel portion 701 includes a signal line driver circuit 703 and a signal line driver circuit 704. A first scanning line driving circuit 702 and a second scanning line driving circuit 704 are arranged to extend from the first scanning line driving circuit 702 and a second scanning line driving circuit 704. The second scanning line driving circuit 703 is extended from the second scanning line driving circuit 703. In each region, pixels each having a display element are arranged in a matrix. The substrate 700 of the device is a flexible printed circuit (FPC) or the like. It is connected to a timing control circuit (also called a controller or control IC) via a connection part. do.

[0421] In FIG. 54A, a first scanning line driver circuit 702, a second scanning line driver circuit 703, a signal The line driver circuit 704 is formed on the same substrate 700 as the pixel section 701. The number of components such as the drive circuits to be provided is reduced, which contributes to cost reduction. 700 If a driving circuit is provided externally, it becomes necessary to extend the wiring, and the number of connections between the wiring increases. When a driver circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced. This can improve reliability or yield.

[0422] [Liquid crystal panel] An example of the circuit configuration of a pixel is shown in FIG. 54(B). Here, a VA type liquid crystal display panel 4 shows a pixel circuit that can be applied to the pixel of

[0423] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels of the multi-domain design to be The signals applied to the electrode layers can be controlled independently.

[0424] A gate wiring 712 of a transistor 716 and a gate wiring 713 of a transistor 717 The data lines are separated so that different gate signals can be applied. The source electrode layer or drain electrode layer 714 functioning as a transistor 716 is Transistors 716 and 717 are used in common in the above embodiment. The transistor 490 described in the embodiment can be appropriately used. Therefore, it is possible to provide a high quality liquid crystal display panel.

[0425] The transistor 716 is electrically connected to a first pixel electrode layer. The first pixel electrode layer and the second pixel electrode layer are electrically connected to each other. The first pixel electrode layer and the second pixel electrode layer are separated from each other. The first pixel electrode layer may be, for example, V-shaped.

[0426] The gate electrode of the transistor 716 is connected to the gate wiring 712, and the transistor 717 The gate electrode of the gate electrode 712 is connected to the gate wiring 713. 3, different gate signals are applied to transistors 716 and 717. By varying the thickness, the alignment of the liquid crystal can be controlled.

[0427] In addition, the capacitance wiring 710, the gate insulating film functioning as a dielectric, and the first pixel electrode layer Alternatively, a storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0428] The multi-domain structure has a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. can be.

[0429] Note that the pixel circuit shown in FIG. 54(B) is not limited to this. For example, in FIG. A switch, a resistor, a capacitor, a transistor, a sensor, or a logic circuit may be newly added to the pixel shown in FIG. etc. may be added.

[0430] [Organic EL Panel] Another example of the circuit configuration of a pixel is shown in FIG. 1 shows the pixel structure of a display panel.

[0431] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of a pair of electrodes. and holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The electrons and holes recombine to form an excited state in the light-emitting organic compound, which then When the excited state of the electron returns to the ground state, light is emitted. The element is called a current-excited light-emitting element.

[0432] FIG. 54C is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. It can be used for the channel formation region of an n-channel transistor. The circuit can apply digital time gray scale driving.

[0433] Regarding the configuration of an applicable pixel circuit and the operation of a pixel when digital time gray scale driving is applied, I will explain it below.

[0434] The pixel 720 includes a switching transistor 721, a driving transistor 722, and a light emitting The switching transistor 721 has a gate element 724 and a capacitor element 723. The first electrode (one of the source and drain electrode layers) is connected to the scan line 726. The second electrode (the other of the source electrode layer and the drain electrode layer) is connected to a signal line 725. It is connected to the gate electrode layer of the driving transistor 722. The gate electrode layer is connected to a power supply line 727 through a capacitor element 723, and the first electrode is connected to the power supply line 727, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the light emitting element 724 corresponds to a common electrode 728. It is electrically connected to a common potential line formed thereon.

[0435] The switching transistor 721 and the driving transistor 722 are the same as those in the above embodiment. The transistor 490 described later can be used appropriately. This allows for highly reliable organic An EL display panel can be provided.

[0436] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727. For example, D, 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage of the light emitting element 72. By applying a voltage to the light emitting element 724, a current flows through the light emitting element 724, causing it to emit light. The forward voltage in 24 refers to the voltage required to achieve the desired brightness, and should be at least 100%. Includes threshold voltage.

[0437] The capacitance element 723 is substituted for the gate capacitance of the driving transistor 722. The gate capacitance of the driving transistor 722 can be omitted. A capacitance may be formed between the gate electrode layer and the gate electrode layer.

[0438] Next, a signal input to the driving transistor 722 will be described. In the case of the above method, the driving transistor 722 is in two states, that is, fully on or off. A video signal that satisfies the above requirement is input to the driving transistor 722. In order to operate the actuator 722 in a linear region, a voltage higher than the voltage of the power supply line 727 is applied to the drive A gate electrode layer of the transistor 722 is connected to a signal line 725. A voltage equal to or greater than the threshold voltage Vth of the driving transistor 722 is applied.

[0439] When analog gradation driving is performed, the gate electrode layer of the driving transistor 722 is connected to the light emitting element 7 A voltage equal to or greater than the sum of the forward voltage of the transistor 724 and the threshold voltage Vth of the driving transistor 722 is applied. In addition, a video signal is input so that the driving transistor 722 operates in the saturation region. This causes a current to flow through the light emitting element 724. In addition, the driving transistor 722 is operated in a saturation region. In order to achieve this, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By converting the video signal into an analog signal, a current corresponding to the video signal is passed to the light emitting element 724. Moreover, analog gray scale driving can be performed.

[0440] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. A switch, a resistor, a capacitor, a sensor, a transistor or a logic element is added to the pixel circuit shown in 4(C). A logic circuit or the like may be added.

[0441] When the transistors illustrated in the above embodiments are applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. The potential of the first gate electrode is controlled by a control circuit or the like. The second gate electrode is supplied with a potential lower than that applied to the source electrode by a wiring (not shown). Any of the above-mentioned potentials may be input.

[0442] For example, in this specification, a display element, a display device which is a device having a display element, a light-emitting A light-emitting device, which is a device having an element and a light-emitting element, can be used in various forms or can be used in various forms. The display element, the display device, the light-emitting element, or the light-emitting device can have, for example, EL (electroluminescence) elements (EL elements containing organic and inorganic materials, organic EL elements child, inorganic EL element), LED chip (white LED chip, red LED chip, green LED chips, blue LED chips, etc.), transistors (transistors that emit light according to the current) , electron emission element, liquid crystal element, electronic ink, electrophoretic element, plasma display (PDP) ), display elements using MEMS (microelectromechanical systems) (e.g. For example, Grating Light Valve (GLV), Digital Micromirror Device (DMD) ), DMS (Digital Micro Shutter), IMOD (Interference Modulation modulation element, shutter-type MEMS display element, optical interference-type MEMS display elements, piezoelectric ceramic displays, etc.), electrowetting elements, quantum dots The display device has at least one display element using a carbon nanotube. In addition, the contrast, brightness, reflectance, transmittance, etc. can be improved by electrical or magnetic effects. An example of a display device using an EL element is as follows: An example of a display device using electron emission elements is a field Field Emission Display (FED) or Single Ended Emission Display (SED:S surface-conduction Electron-emitter Displ One example of a display device that uses quantum dots for each pixel is the quantum dot display. Quantum dots are not used as display elements but as backlights. By using quantum dots, it is possible to achieve a display with high color purity. An example of a display device using a liquid crystal element is a liquid crystal display (transmission type liquid crystal display). Play, Semi-transmissive LCD, Reflective LCD, Direct-view LCD Display devices using electronic ink or electrophoretic elements. An example of such a device is electronic paper. When realizing a liquid crystal display, a part or all of the pixel electrodes are used as reflective electrodes. For example, a part or the whole of the pixel electrode may be made of aluminum. In this case, the reflective electrode may have a SR It is also possible to provide a memory circuit such as AM. This further reduces power consumption. When using an LED chip, the electrodes of the LED chip and the nitride semiconductor Graphene or graphite may be placed under the A multi-layer film may be formed by stacking several layers. By this, a nitride semiconductor, for example, a crystal-containing n-type GaN semiconductor layer, etc., can be formed thereon. It is easy to form a film. Furthermore, a p-type GaN semiconductor layer having crystals can be formed on it. In addition, the graphene and graphite can be used together to form an LED chip. An AlN layer may be provided between the n-type GaN semiconductor layer having crystals. The GaN semiconductor layer of the chip may be formed by MOCVD. This allows the GaN semiconductor layer of the LED chip to be deposited by sputtering. In addition, in the case of a display element using MEMS, the space in which the display element is sealed (For example, a device substrate on which a display device is disposed and a counter substrate disposed opposite the device substrate.) By disposing a desiccant, it is possible to prevent the MEMS This prevents moisture from making the material less mobile and causing it to deteriorate. .

[0443] For example, in this specification, it is possible to form transistors using various substrates. The type of substrate is not limited to a specific one. Conductor substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrate, metal substrate, stainless steel substrate, stainless steel foil Substrate with tungsten foil, Tungsten substrate, Substrate with tungsten foil, Flexible substrate, Adhesive There are laminated films, papers containing fibrous materials, and base films. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates, laminated films, and base films include glass. Examples of such materials include polyethylene terephthalate (PET), polyethylene Plastics such as polyolefin naphthalate (PEN) and polyethersulfone (PES) One example is synthetic resin such as acrylic. Another example is Examples of the material include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy, and inorganic vapor deposition. Films, papers, etc. In particular, semiconductor substrates, single crystal substrates, and SOI substrates, etc. By manufacturing transistors using this method, there is little variation in characteristics, size, shape, etc. This allows the manufacture of transistors with fewer gates, higher current capability, and smaller size. When a circuit is constructed using such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated. It is possible to achieve this.

[0444] In addition, a flexible substrate is used as the substrate, and a transistor is formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be formed of an inorganic material such as a tungsten film and a silicon oxide film. The structure may be a laminated structure of films or a structure in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0445] That is, one substrate is used to form a transistor, and then another substrate is used to form the transistor. The transistor may be transposed and placed on another substrate. As an example, in addition to the substrate on which the above-mentioned transistors can be formed, a paper substrate, a cellophane substrate, etc. Fan boards, aramid film boards, polyimide film boards, stone boards, wood boards, cloth Substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), There are leather substrates, rubber substrates, etc. By using these substrates, Formation of transistors, formation of transistors with low power consumption, manufacturing of devices that are not easily damaged, heat resistance It is possible to provide a thinner, lighter, or thinner device.

[0446] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0447] (Embodiment 7) Examples of electronic devices using a semiconductor device according to one embodiment of the present invention include display devices such as televisions and monitors. equipment, lighting equipment, desktop or notebook personal computers, word processors It is stored on recording media such as a digital camera or a DVD (Digital Versatile Disc). Image reproducing devices that reproduce still or moving images recorded on a DVD player, portable CD players, radios, tapes, etc. Pre-recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephones mobile phones, mobile information terminals, tablet terminals, portable games gaming machines, pachinko machines and other fixed game machines, calculators, electronic organizers, e-book terminals, electronic translators , voice input devices, video cameras, digital still cameras, electric shavers, microwave ovens, etc. High frequency heating devices, electric rice cookers, electric washing machines, vacuum cleaners, water heaters, electric fans, hair dryers, Air conditioning equipment such as air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, and clothing Dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, freezers for DNA storage, Examples include tools such as flashlights and chainsaws, smoke detectors, and medical equipment such as dialysis machines. In addition, emergency lights, traffic lights, conveyor belts, elevators, escalators, and industrial robots , power storage systems, power leveling and smart grid storage devices and other industrial equipment. In addition, there are electric motors that use electricity from storage batteries and engines that use fuel. Mobile objects that move around may also be included in the category of electronic devices. , electric vehicles (EV), hybrid vehicles (HEV) that combine internal combustion engines and electric motors, Hybrid electric vehicles (PHEVs), tracked vehicles that use these tires and wheels as tracks, Motorized bicycles including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, Small or large ships, submarines, helicopters, aircraft, rockets, satellites, space probes, etc. Examples include planetary probes and spacecraft.

[0448] A portable game machine 2900 shown in FIG. 55(A) includes a housing 2901, a housing 2902, a display unit 2903, display unit 2904, microphone 2905, speaker 2906, operation key 290 7. The portable game machine shown in FIG. 55(A) has two display units 2903 and The display unit 2903 has a display unit 2904, but the number of display units is not limited to this. The device is equipped with a touch screen as an input device, and can be operated with a stylus 2908 or the like. It is possible to create

[0449] The information terminal 2910 shown in FIG. 55(B) includes a housing 2911, a display unit 2912, a microphone 2913, and a 917, a speaker unit 2914, a camera 2913, an external connection unit 2916, and operation buttons The display unit 2912 includes a display panel using a flexible substrate and a The information terminal 2910 is, for example, a smartphone, a mobile phone, , tablet information terminals, tablet personal computers, e-book terminals, etc. It can be used.

[0450] A notebook personal computer 2920 shown in FIG. 55(C) includes a housing 2921, a display 2922, a keyboard 2923, and a pointing device 2924.

[0451] The video camera 2940 shown in FIG. 55(D) includes a housing 2941, a housing 2942, a display unit 2 943, operation keys 2944, a lens 2945, and a connection part 2946. The lens 2945 and the lens 2944 are provided in the housing 2941, and the display unit 2943 is provided in the housing. The housing 2941 and the housing 2942 are connected to each other via a connection portion 2946. The angle between the housing 2941 and the housing 2942 is determined by the connection 2946. The angle of the housing 2942 relative to the housing 2941 can be changed. This allows you to change the orientation of the image displayed on the display unit 2943 and switch between displaying and hiding the image. This can be done.

[0452] An example of a bangle-type information terminal is shown in FIG. The display unit 2952 is attached to a housing 2951 having a curved surface. The display unit 2952 is provided with a display panel using a flexible substrate. It is possible to provide an information terminal 2950 that is flexible, lightweight, and easy to use.

[0453] FIG. 55(F) shows an example of a wristwatch-type information terminal. The information terminal 2960 has a housing 2961. , display unit 2962, band 2963, buckle 2964, operation button 2965, input / output terminal The information terminal 2960 is equipped with a mobile phone, an electronic mail, a text browsing and writing device, etc. Various applications such as music playback, Internet communication, and computer games can be executed.

[0454] The display surface of the display unit 2962 is curved, and display can be performed along the curved display surface. The display unit 2962 is also equipped with a touch sensor, and can be used to touch the screen with a finger or a stylus. For example, the icon 2967 displayed on the display unit 2962 can be operated by By touching the operation button 2965, an application can be started. In addition to settings, you can also turn the power on and off, turn wireless communication on and off, activate silent mode, and It can have various functions such as turning on and off the power saving mode, turning on and off the power saving mode, etc. The operating system installed in the information terminal 2960 controls the operation of the operation button 296 You can also set the 5 functions.

[0455] In addition, the information terminal 2960 is capable of performing short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, hands-free communication is possible. The information terminal 2960 also has an input / output terminal 2966, and can communicate with other information terminals. Data can be exchanged directly through the terminal and connector. Charging can also be performed via the input / output terminal 2966. This may be achieved by wireless power supply.

[0456] FIG. 55(G) shows an electric refrigerator as an example of a household electrical appliance. The refrigerator has a housing 2971, a refrigerator door 2972, and a freezer door 2973.

[0457] FIG. 55(H) is an external view showing an example of an automobile. The automobile 2980 has a body 2981. , wheels 2982, dashboard 2983, and lights 2984.

[0458] The electronic devices described in this embodiment include the above-described transistors or the above-described semiconductor devices. It is equipped with:

[0459] This embodiment may be combined, at least in part, with other embodiments described in this specification. For example, the electronic devices described in this embodiment can be implemented in combination with other embodiments. By mounting the semiconductor device shown in the embodiment, the performance of electronic devices can be improved. Alternatively, it may be possible to reduce the power consumption of electronic devices.

[0460] (Embodiment 8)

[0461] [Imaging device] In this embodiment, an imaging device using one embodiment of the present invention will be described.

[0462] <Configuration example of imaging device 600> FIG. 56A is a plan view showing a configuration example of an imaging device 600. The element unit 621, the first circuit 260, the second circuit 270, the third circuit 280, and the fourth circuit In this specification, the first circuit 260 to the fourth circuit 290 are 0 may be referred to as a "peripheral circuit" or a "drive circuit." For example, the first circuit 26 0 can be considered part of the peripheral circuit.

[0463] FIG. 56B is a diagram showing a configuration example of the pixel section 621. The pixel section 621 has p columns and q rows ( p and q are natural numbers of 2 or more) are arranged in a matrix of a plurality of pixels 622 (imaging element In FIG. 56(B), n is a natural number between 1 and p, and m is a natural number between 1 and q. are the natural numbers below.

[0464] For example, if pixels 622 are arranged in a 1920 x 1080 matrix, a so-called full High definition (also called "2K resolution," "2K1K," or "2K") resolution In addition, for example, the pixel 622 can be set to 40 When arranged in a 96 x 2160 matrix, it becomes what is known as ultra-high definition (4K resolution). (also called "4K2K", "4K", etc.) 00 can be realized. Also, for example, pixel 622 can be a matrix of 8192 x 4320. When these are arranged in a grid, they form what is known as super high vision (8K resolution, 8K4K, It is possible to realize an imaging device 600 capable of capturing images at a resolution of 1080p (also called "8K"). By increasing the number of display elements, it is possible to realize an imaging device 600 capable of imaging at a resolution of 16K or 32K. It is also possible to achieve this.

[0465] The first circuit 260 and the second circuit 270 are connected to a plurality of pixels 622. The first circuit 260 has a function of supplying a signal for driving the pixel 622. The third circuit may have a function of processing the analog signal output from the third circuit. The circuit 280 may have a function of controlling the operation timing of the peripheral circuits. The clock signal may be generated by the external clock signal. The third circuit 280 may have a function of converting the frequency of the reference potential signal. The input / output terminal may have a function of supplying a signal (for example, a ramp signal).

[0466] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier circuit, or a converter circuit. The transistors used in the peripheral circuits are the same as those in the pixel driving circuit 6 described later. It may be formed by using a part of the semiconductor formed to fabricate 10. A semiconductor device such as an IC chip may be used in part or in whole.

[0467] Note that the peripheral circuits include at least one of the first circuit 260 to the fourth circuit 290. For example, the function of either the first circuit 260 or the fourth circuit 290 may be omitted. In addition to the other of the first circuit 260 or the fourth circuit 290, Alternatively, for example, the second circuit 270 or the third circuit 290 may be omitted. The function of one of the circuits 280 is added to the other of the second circuit 270 or the third circuit 280, Either the second circuit 270 or the third circuit 280 may be omitted. By adding the functions of other peripheral circuits to any one of the first circuit 260 to the fourth circuit 290, In this way, other peripheral circuits may be omitted.

[0468] As shown in FIG. 57, the first circuit 260 to the fourth circuit 261 are arranged along the periphery of the pixel portion 621. In addition, the pixel 6 in the pixel portion 621 of the imaging device 600 may be provided with a circuit 290. By arranging the pixels 622 at an angle, the row direction and the column direction can be adjusted. This allows the pixel interval (pitch) in the direction to be shortened. This can improve the quality of the captured image.

[0469] As shown in FIG. 58, a picture is overlapped above the first circuit 260 to the fourth circuit 290. A base portion 621 may be provided. FIG. 58(A) shows the top of the first circuit 260 to the fourth circuit 290. 58(B) is a top view of an imaging device 600 in which a pixel portion 621 is formed on the other side. 58(A) is a perspective view for explaining the configuration of the imaging device 600 shown in FIG.

[0470] By providing the pixel portion 621 above the first circuit 260 to the fourth circuit 290, The area occupied by the pixel portion 621 relative to the size of the imaging device 600 can be increased. This improves the light receiving sensitivity of the imaging device 600. In addition, the resolution of the imaging device 600 can be improved. In addition, the reproducibility of the image captured by the imaging device 600 can be improved. Therefore, the integration density of the imaging device 600 can be improved.

[0471] [Color filters, etc.] The pixels 622 included in the imaging device 600 are used as sub-pixels, and each of the pixels 622 By providing filters (color filters) that transmit light of different wavelengths, a color image can be produced. It is possible to obtain information for realizing the display.

[0472] FIG. 59(A) is a plan view showing an example of a pixel 623 for acquiring a color image. FIG. 59(A) shows a pixel 62 provided with a color filter that transmits light in the red (R) wavelength range. 2 (hereinafter also referred to as "pixel 622R"), a color filter that transmits light in the green (G) wavelength range. A pixel 622 (hereinafter also referred to as "pixel 622G") in which the pixel 622 is provided and a wavelength band of blue (B) A pixel 622 (hereinafter, also referred to as “pixel 622B”) is provided with a color filter that transmits light of The pixels 622R, 622G, and 622B are grouped together to form a single pixel 623. Function as.

[0473] The color filters used in the pixel 623 are not limited to red (R), green (G), and blue (B). The color filters transmit cyan (C), yellow (Y) and magenta (M) light. A pixel 623 may include a pixel 623 that detects light of at least three different wavelength ranges. By providing 22, a full color image can be obtained.

[0474] Figure 59(B) shows color filters that transmit red (R), green (G) and blue (B) light, respectively. In addition to the pixel 622 having the filter, a color filter that transmits yellow (Y) light is provided. FIG. 59(C) illustrates a pixel 623 having a pixel 622 with a cyan (C) A pixel provided with a color filter that transmits yellow (Y) and magenta (M) light. In addition to the pixel 622, a pixel 622 is provided with a color filter that transmits blue (B) light. A pixel 623 is shown as an example. A single pixel 623 detects light of four or more different wavelength ranges. By providing the pixel 622, the color reproducibility of the acquired image can be further improved. .

[0475] In addition, the pixel number ratio (or light receiving area) of the pixel 622R, the pixel 622G, and the pixel 622B The pixel ratio (ratio) does not necessarily have to be 1:1:1. As shown in FIG. 59(D), The ratio of the light receiving areas of red, green, and blue may be 1:2:1. The numerical ratio (light receiving area ratio) may be red:green:blue=1:6:1.

[0476] Although the number of pixels 622 used for the pixel 623 may be one, it is preferable to use two or more. By providing two or more pixels 622 that detect light in the same wavelength range, redundancy is increased, and the imaging device This can improve the reliability of the device 600.

[0477] In addition, it acts as a filter by absorbing or reflecting light with wavelengths shorter than the wavelength of visible light, and by blocking infrared light. By using an IR (IR: Infrared) filter that transmits light, infrared light can be detected. In addition, it is possible to realize an imaging device 600 that can detect wavelengths longer than the wavelength of visible light. UV (UV: Ultra Vio) By using a filter, it is possible to realize an imaging device 600 that detects ultraviolet light. In addition, a scintillator that converts radiation into ultraviolet light or visible light is used as a filter. This allows the imaging device 600 to function as a radiation detector for detecting X-rays, gamma rays, etc. It is also possible.

[0478] In addition, a Neutral Density (ND) filter is used as a filter. When a large amount of light is incident on the photoelectric conversion element (light receiving element), This can prevent the phenomenon of output saturation (hereinafter also referred to as "output saturation") that occurs when By combining ND filters with different light intensities, the dynamic range of the imaging device can be expanded. can be made larger.

[0479] In addition to the above-mentioned filter, a lens may be provided in the pixel 622. An example of the arrangement of the pixel 622, the filter 624, and the lens 635 will be described with reference to the cross-sectional view of the pixel 622. By providing the lens 635, incident light can be efficiently received by the photoelectric conversion element. Specifically, as shown in FIG. 60A, a lens 635 and a filter 624 (filter 624R, filter 624G, filter 624B), and the pixel drive circuit The structure may be such that light 660 is incident on the photoelectric conversion element 601 through a path 610 or the like. .

[0480] However, as shown in the area surrounded by the two-dot chain line, a part of the light 660 indicated by the arrow is connected to the wiring group 62. 6, transistors, and / or capacitors may block the light. Therefore, as shown in FIG. 60(B), a lens 635 and a and a filter 624 are formed to allow the photoelectric conversion element 601 to efficiently receive incident light. By making the light 660 incident from the photoelectric conversion element 601 side, an image with high light receiving sensitivity can be obtained. An imaging device 600 can be provided.

[0481] 61(A) to 61(C) show a pixel driving circuit 6 that can be used in the pixel section 621. 61A shows an example of a pixel driver circuit 610 including a transistor 602, The transistor 604 and the capacitor element 606 are connected to the photoelectric conversion element 601. One of the source and drain of the transistor 602 is electrically connected to the photoelectric conversion element 601. The other of the source and drain of the transistor 602 is connected to a node 607 (a charge storage portion). ) is electrically connected to the gate of the transistor 604.

[0482] The transistor 602 is preferably an OS transistor. Since the off-current can be made extremely small, the capacitor 606 can be made small. Alternatively, as shown in FIG 61(B), the capacitor 606 can be omitted. In addition, when an OS transistor is used as the transistor 602, the potential of the node 607 changes. Therefore, it is possible to realize an imaging device that is less susceptible to the effects of noise. Alternatively, the transistor 604 may be an OS transistor.

[0483] The photoelectric conversion element 601 has a pn-type or pin-type junction formed on a silicon substrate. A diode element can be used. Alternatively, an amorphous silicon film or a microcrystalline silicon film can be used. Alternatively, a pin-type diode element using a diode may be used. A variable resistor utilizing the photoelectric effect may also be used. It may be formed using selenium, selenium, etc.

[0484] In addition, materials capable of absorbing radiation and generating electric charges are used as photoelectric conversion elements. The material capable of absorbing radiation and generating a charge may be iodine. These include lead iodide, mercury iodide, gallium arsenide, CdTe, and CdZn.

[0485] The pixel driving circuit 610 shown in FIG. 61C includes a transistor 602 and a transistor 603. 604, a transistor 605, and a capacitor 606. The pixel driving circuit 610 shown in FIG. The element 601 is a photodiode. One of the source and drain is electrically connected to the cathode of the photoelectric conversion element 601, and the other is The anode of the photoelectric conversion element 601 is electrically connected to the wiring 611. The source or drain of the transistor 603 is electrically connected to the node The other end is electrically connected to a wiring 608. The gate of 604 is electrically connected to a node 607, and either the source or the drain is connected to a wiring. 609, and the other is electrically connected to one of the source and drain of the transistor 605. The other of the source and the drain of the transistor 605 is electrically connected to the wiring 60 One electrode of the capacitor 606 is electrically connected to a node 607. The other electrode is electrically connected to a wiring 611.

[0486] The transistor 602 can function as a transfer transistor. A transfer signal TX is supplied to the transistor 603. The transistor 603 serves as a reset transistor. A reset signal RST is supplied to the gate of the transistor 603. Transistor 604 can function as an amplifying transistor. Transistor 605 can function as a selection transistor. The gate of the transistor 605 is supplied with a selection signal SEL. In addition, VDD is supplied to the wiring 608, and VSS is supplied to the wiring 611.

[0487] Next, the operation of the pixel driving circuit 610 shown in FIG. The resistor 603 is turned on to supply VDD to the node 607 (reset operation). After that, when the transistor 603 is turned off, VDD is held at the node 607. When the transistor 602 is turned on, the photoelectric conversion element 601 receives a light amount. The potential of the node 607 changes (storage operation). Then, the transistor 602 is turned off. Then, the potential of the node 607 is held. Next, when the transistor 605 is turned on, A potential corresponding to the potential of the node 607 is output from the wiring 609 (selection operation). By detecting the potential of the photoelectric conversion element 601, the amount of light received by the photoelectric conversion element 601 can be known.

[0488] The transistors 602 and 603 may be OS transistors. As described above, the off-state current of the OS transistor can be made extremely small. Therefore, the capacitance element 606 can be made smaller. Alternatively, the capacitance element 606 can be omitted. In addition, the transistors 602 and 603 may be OS transistors. When a capacitor is used, the potential of the node 607 is less likely to fluctuate. Therefore, the node 607 is less susceptible to noise. An imaging device can be realized.

[0489] A pixel 6 using any one of the pixel driving circuits 610 shown in FIG. 61(A) to FIG. 61(C) By arranging the pixels 22 in a matrix, a high-resolution imaging device can be realized.

[0490] For example, if the pixel driving circuits 610 are arranged in a 1920×1080 matrix, Loose full HD (also called "2K resolution", "2K1K", "2K", etc.) In addition, for example, the pixel driving circuit 6 When 10 pixels are arranged in a 4096 x 2160 matrix, this becomes what is known as Ultra Hi-Vision. (also called "4K resolution", "4K2K", "4K", etc.) In addition, for example, the pixel driving circuit 610 can be configured to have a pixel size of 8192×43 When arranged in a matrix of 20, it produces what is known as super high vision (8K resolution, It is also called "8K4K" or "8K". By increasing the number of display elements, it is possible to create an imaging device capable of capturing images at resolutions of 16K or 32K. It is also possible to achieve this.

[0491] A structural example of a pixel 622 using the above-mentioned transistor is shown in FIG. FIG. 2 is a cross-sectional view of a portion of FIG.

[0492] The pixel 622 shown in FIG. 62 uses an n-type semiconductor as the substrate 400. The p-type semiconductor 221 of the photoelectric conversion element 601 is provided in the substrate 400. A part of it functions as the n-type semiconductor 223 of the photoelectric conversion element 601 .

[0493] The transistor 604 is provided on the substrate 400. In addition, a p-type semiconductor layer is formed on a portion of the substrate 400. The well 220 is formed in a similar manner to the formation of the p-type semiconductor 221. In addition, the well 220 and the p-type semiconductor 221 can be formed at the same time. Note that the transistor 604 may be, for example, the transistor 491. can be done.

[0494] In addition, an insulator 464 a and an insulating film are formed on the photoelectric conversion element 601 and the transistor 604. The insulator 464a and the insulator 464b are formed on the substrate 400 (n-type An opening 224 is formed in the region overlapping the semiconductor 223, and the insulator 464a and the insulator 46 An opening 225 is formed in a region of the p-type semiconductor 221 of the first insulating film 4b. A plug 541b is formed in the opening 225. The plug 541b is the above-mentioned plug. The openings 224 and 225 can be provided in the same manner as the opening 541. There are no particular restrictions on the arrangement, so an imaging device with a high degree of freedom in layout can be realized.

[0495] In addition, the conductor 421, the conductor 422, and the conductor 429 are formed on the insulator 464b. The conductor 421 is connected to an n-type semiconductor via a plug 541b provided in the opening 224. The conductor 429 is electrically connected to the conductor 223 (substrate 400). The p-type semiconductor 221 is electrically connected to the p-type semiconductor 221 via a plug 541b provided in the conductor 5. The electrode 422 can function as one electrode of the capacitor 606 .

[0496] In addition, an insulator 581 is formed to cover the conductor 421, the conductor 429, and the conductor 422. The conductor 421, the conductor 422, and the conductor 429 are the same as the conductor 51 described above. It can be formed using the same materials and methods as those used in Example 1.

[0497] In addition, an insulator 571 is formed on the insulator 581, and a conductor 513 is formed on the insulator 571. , a conductor 413, and an electrode 273 are formed. The conductor 513 is connected to the The conductor 413 is electrically connected to the conductor 429 through the transistor 602. The electrode 273 can function as the other electrode of the capacitor element 606. The transistor 602 can be, for example, the transistor 490 described above. do.

[0498] The conductor 416a of the transistor 602 is connected to the conductor 5 through the plug 544. 62 is electrically connected to the plug 544b shown in FIG. Plug 544b can be seen.

[0499] <Variation 1> An example of the configuration of the pixel 622 different from that shown in FIG. 62 is shown in FIG. 63. FIG. 63 shows a cross-section of a part of the pixel 622. FIG.

[0500] The pixel 622 shown in FIG. 63 includes a transistor 604 and a transistor 605 on a substrate 400. The transistor 604 can function as an n-channel transistor. The transistor 605 can function as a p-channel transistor. For example, the transistor 491 described above can be used as the transistor 604. The transistor 605 can be, for example, the transistor 494 described above.

[0501] Conductors 413a to 413d are formed over the insulator 464b. 13a is electrically connected to one of the source and drain of the transistor 604, and 413b is electrically connected to the other of the source and drain of the transistor 604 The conductor 413c is electrically connected to the gate of the transistor 604. 13b is electrically connected to one of the source and drain of the transistor 605, and 413d is electrically connected to the other of the source and drain of the transistor 605 .

[0502] An insulator 581 is formed on the insulator 464b. An insulator 57 is formed on the insulator 581. On the insulator 571, an insulator 585, a conductor 413, and a conductor 51 are formed. 3 is formed. The conductor 513 is connected to the conductor 413c via the plug 543. Here, the plug 543 has a protrusion on the insulator 571 .

[0503] In addition, an insulator 571a is formed over the conductor 513, the conductor 413, and the insulator 585. The transistor 602 is formed on the insulator 571a. An insulator 408 is formed on the insulating film 02, and an insulator 591 is formed on the insulator 408. A conductor 514 and an insulator 592 are formed on 591 .

[0504] In addition, the pixel 622 shown in FIG. 63 has a photoelectric conversion element 601 provided on an insulator 592. In addition, an insulator 442 is provided over the photoelectric conversion element 601, and a conductor is provided over the insulator 442. The insulator 442 is formed of the same material and in the same manner as the insulator 591. It is possible.

[0505] The photoelectric conversion element 601 shown in FIG. 63 includes a conductor 686 formed of a metal material or the like and a light-transmitting A photoelectric conversion layer 681 is provided between the conductive layer 682. In FIG. The photoelectric conversion element 601 using a selenium-based material is a visible The photoelectric conversion element has a high external quantum efficiency. This makes it possible to provide a highly sensitive sensor with a large amplification of electrons relative to the amount of incident light. In addition, since selenium-based materials have a high light absorption coefficient, they have the advantage that the photoelectric conversion layer 681 can be easily made thin. do.

[0506] As the selenium-based material, amorphous selenium or crystalline selenium can be used. For example, amorphous selenium can be obtained by forming a film of amorphous selenium and then performing a heat treatment. By making the grain size of the crystalline selenium smaller than the pixel pitch, the characteristic variation between pixels is reduced. Crystalline selenium also has a higher spectral sensitivity to visible light than amorphous selenium. It has the characteristics of high sensitivity and light absorption coefficient.

[0507] Although the photoelectric conversion layer 681 is illustrated as a single layer, the selenium-based material has holes on the light receiving surface side. Gallium oxide or cerium oxide is provided as an injection blocking layer, and electron injection is performed on the conductor 686 side. The blocking layer may be nickel oxide or antimony sulfide. .

[0508] The photoelectric conversion layer 681 is a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, a layer containing a compound of copper, indium, gallium, and selenium (CIGS) may be used. In CIS and CIGS, the avalanche phenomenon is similar to that in the case of a single layer of selenium. A usable photoelectric conversion element can be formed.

[0509] In addition, CIS and CIGS are p-type semiconductors, and n-type semiconductors are used to form junctions. Cadmium sulfide, zinc sulfide, or the like may be provided in contact with the metal.

[0510] In order to generate the avalanche phenomenon, a relatively high voltage (for example, 1 It is preferable to apply a voltage of 0 V or more to the OS transistor. Since it has high rain withstand voltage characteristics, it is easy to apply a relatively high voltage to the photoelectric conversion element. Therefore, we have developed an OS transistor with a high drain withstand voltage and a selenium-based photoconductive By combining it with a photoelectric conversion element with a photodiode, a highly sensitive and reliable imaging device can be obtained. It is possible.

[0511] The transparent conductive layer 682 may be made of, for example, indium tin oxide or indium tin containing silicon. Oxides, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, aluminum Zinc oxide containing fluorine, tin oxide, tin oxide containing antimony, or graphite In addition, the light-transmitting conductive layer 682 is not limited to a single layer, but may be a stack of different films. In FIG. 63, the light-transmitting conductive layer 682 and the wiring 487 are formed by the conductor 48 8 and a plug 489. 82 and wiring 487 may be in direct contact.

[0512] The conductor 686 and the wiring 487 may have a structure in which a plurality of conductive layers are stacked. For example, the conductor 686 can be formed in two layers, and the wiring 487 can be formed in two layers. For example, the lower layers of the conductors 686 and 487 are formed by selecting a low-resistance metal or the like. The upper layers of the conductor 686 and the conductor 487 are made of a metal or the like having good contact characteristics with the photoelectric conversion layer 681. By adopting such a structure, the electrical characteristics of the photoelectric conversion element can be improved. In addition, some metals can be electrically conductive by contacting the transparent conductive layer 682. Even if such a metal is used for the conductor 487a, the conductor 487 By using b, electrolytic corrosion can be prevented.

[0513] The upper layer of the conductor 686 and the conductor 487 is made of, for example, molybdenum or tungsten. In addition, the lower layer of the conductor 686 and the conductor 487 may be, for example, Aluminum, titanium, or laminates such as aluminum sandwiched between titanium can be used. do.

[0514] The insulator 442 may have a multi-layer structure. The partition wall 477 can be formed of an organic resin or the like. Black, etc., to block light from the surroundings and / or to determine the area of ​​the light receiving part per pixel The composition may be colored.

[0515] The photoelectric conversion element 601 is made of p-type semiconductor using an amorphous silicon film or a microcrystalline silicon film. An in-type diode element or the like may be used. The photodiode has an n-type semiconductor layer The i-type semiconductor layer has a structure in which an i-type semiconductor layer and a p-type semiconductor layer are laminated in this order. The conductor layer is preferably made of amorphous silicon. The semiconductor layers are made of amorphous silicon or microcrystalline silicon containing dopants that impart the respective conductivity types. A photodiode using amorphous silicon as a photoelectric conversion layer can be used. The card has high sensitivity in the visible light wavelength range and can easily detect weak visible light.

[0516] In addition, pn-type and pin-type diode elements are designed so that the p-type semiconductor layer is the light-receiving surface. By using a p-type semiconductor layer as a light receiving surface, the output of the photoelectric conversion element 601 The current can be increased.

[0517] The photoelectric conversion element 601 formed using the above-mentioned selenium-based material, amorphous silicon, etc. It is made using general semiconductor manufacturing processes such as film formation, lithography, and etching. It is possible to manufacture.

[0518] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0519] (Additional Notes Regarding the Description of the Present Specification, etc.) The above embodiment and each configuration in the embodiment will be described below with additional notes.

[0520] <Additional Notes on One Aspect of the Invention Described in the Embodiments> The configurations shown in each embodiment may be appropriately combined with the configurations shown in other embodiments to realize the present invention. In addition, in one embodiment, a plurality of configuration examples may be shown. In this case, the configuration examples can be appropriately combined with each other.

[0521] In addition, the contents (or even a part of the contents) described in one embodiment may be used in the embodiment. Another content (or a part of the content) described in the form, and / or one or more other implementations The contents (or a part of the contents) described in the embodiments may be applied, combined, or replaced. It is possible to do things like drawing.

[0522] The contents described in the embodiments are explained in detail with reference to various figures in each embodiment. The content is described in the specification or using sentences in the description.

[0523] In addition, a figure (or a part of it) described in one embodiment may be replaced with another part of the figure. , another figure (or a part thereof) described in the embodiment, and / or one or more By combining the figures (or a part of them) described in the other embodiments of the present invention, This allows even more diagrams to be constructed.

[0524] In addition, although one aspect of the present invention has been described in each embodiment, one aspect of the present invention is not limited to these. For example, in the first embodiment of the present invention, a transistor having a low off-current is In the above description, a structure in which an OS transistor is used as a transistor is described. The transistor is not limited to an OS transistor as long as it has a low flicker current. Therefore, depending on the situation, for example, a configuration that does not use an OS transistor may be considered as one embodiment of the present invention. good.

[0525] <Notes regarding the description of the drawings> In this specification, the terms "above" and "below" that indicate an arrangement refer to the positional relationship between components. The relationship between the components is used for convenience in the description with reference to the drawings. The wording of the arrangement changes accordingly depending on the direction in which the composition is depicted. The above description is not limited to the above, and may be rephrased appropriately depending on the situation.

[0526] In addition, the terms "above" and "below" refer to the positional relationship of a component directly above or directly below it. For example, the expression "electrode B on insulating layer A" does not necessarily mean that the electrodes are in contact with each other. For example, it is not necessary for electrode B to be formed directly on insulating layer A. This does not exclude the inclusion of other components between the

[0527] In the present specification and the like, in the block diagrams, components are classified by function and are independent of each other. However, in actual circuits, the components are divided into functional blocks. In some cases, it is difficult to separate the functions into separate circuits, and multiple functions are involved in one circuit, or multiple circuits are involved in a single circuit. Therefore, the blocks in the block diagram may be expressed as The present invention is not limited to the described components, and may be rephrased appropriately depending on the situation.

[0528] In addition, in the drawings, the size, layer thickness, and area are shown arbitrarily for convenience of explanation. The drawings are not necessarily limited to the scale shown. The figures are merely schematic illustrations for the purpose of illustration, and are not limited to the shapes or values ​​shown in the drawings. , noise, signal, voltage, or current variations, or timing errors These may include variations in signal, voltage, or current.

[0529] In addition, in the drawings, in top views (also called plan views or layout views) and perspective views, In order to clarify the drawings, some components may be omitted.

[0530] <Notes on possible alternative descriptions> In this specification and the like, when describing the connection relationship of a transistor, The first electrode or the first terminal is called the source or drain. The other of the source and drain is referred to as the "other of the source or drain" (or the second electrode, or the second terminal). This is because the source and drain of a transistor are This is because the names of the source and drain of a transistor change depending on the operating conditions. In this case, it is appropriate to use the term source (drain) terminal, source (drain) electrode, etc., depending on the situation. It can be replaced.

[0531] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not intended to be limiting. For example, an "electrode" may be used as a part of a "wire." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the wiring is formed integrally.

[0532] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. This is the potential difference from a reference potential. For example, if the reference potential is the ground voltage, In other words, voltage can be expressed as potential. Ground voltage does not necessarily mean 0V. Note that the potential is relative, and depending on the reference potential, the potential applied to wiring, etc. This may change the electrical potential at the electrode.

[0533] In this specification, the terms "film" and "layer" are used in some cases or in other situations. Depending on the circumstances, the terms may be interchangeable. For example, the term "conductive film" may be replaced with " In some cases, it may be possible to change the term to "conductive layer." Or, for example, to "insulating film." In some cases, the term "insulating layer" may be changed to the term "insulating layer."

[0534] <Notes on definitions of terms> The following provides definitions of terms not mentioned in the above embodiments.

[0535] <<About switches>> In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state). It refers to a device that has the function of controlling whether or not a current flows by switching to a non-operating state. A switch has a function of selecting and switching a path through which a current flows.

[0536] As an example, an electrical switch or a mechanical switch can be used. In other words, the switch is not limited to a specific one as long as it can control the current.

[0537] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these There is.

[0538] When a transistor is used as a switch, the "conduction state" of the transistor is This refers to a state in which the source and drain of a transistor can be considered to be electrically shorted. The "non-conducting state" of a transistor is when the source and drain of the transistor are electrically isolated. In addition, if the transistor is operated as a simple switch, In this case, the polarity (conductivity type) of the transistor is not particularly limited.

[0539] An example of a mechanical switch is a digital micromirror device (DMD). In 2013, a switch using MEMS (microelectromechanical system) technology was developed. The switch has a mechanically movable electrode, and when the electrode moves, Therefore, the device operates by controlling conduction and non-conduction.

[0540] <<About channel length>> In this specification and the like, the channel length is, for example, the length of a semiconductor the body (or the part of the semiconductor through which current flows when the transistor is on) and the gate The distance between the source and drain in the region where they overlap or where the channel is formed. It means separation.

[0541] In addition, in one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of a transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one of the lengths in the region where the channel is formed. The value, maximum, minimum or average value.

[0542] <<About channel width>> In this specification, the channel width refers to, for example, the width of a semiconductor (or a transistor) when it is in an on-state. The region where the gate electrode overlaps with the gate electrode (the part of the semiconductor through which current flows when the semiconductor is in the insulated state), or the channel This refers to the length of the portion where the source and drain face each other in the region where the MOSFET is formed. .

[0543] In addition, in one transistor, the channel width does not necessarily have the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is defined as any one of the widths in the region where the channel is formed. It may be a single value, a maximum value, a minimum value or an average value.

[0544] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The channel width becomes larger than the apparent width shown in the figure, and the effect becomes non-negligible. For example, in transistors with a fine, three-dimensional structure, the lateral surface of the semiconductor In this case, the ratio of the channel region formed in the top view may be large. The effective channel width of the channel is actually formed rather than the apparent channel width shown. will be larger.

[0545] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width unless the exact channel conditions are known. .

[0546] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent thickness is the length of the part where the source and drain face each other in the region where the The channel width is defined as the "surrounded channel width (SCW)". In this specification, when it is simply referred to as the channel width, In some cases, this refers to the enclosed channel width or apparent channel width. In the detailed description, when the term "channel width" is used simply, it may refer to the effective channel width. In addition, channel length, channel width, effective channel width, apparent channel width, enclosure The channel width, etc., can be determined by acquiring cross-sectional TEM images and analyzing those images. , values ​​can be determined.

[0547] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0548] <<About connection>> In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to those that are electrically connected, A and B are also included. "Connected" means that there is an object between A and B that has some electrical effect. When a device is connected to a power source, it enables the transmission and reception of electrical signals between A and B.

[0549] For example, the source (or the first terminal, etc.) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. It may be electrically connected to Y through Z2 (or not), or the source of the transistor may be A part of Z1 is directly connected to X, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. When a part of Z2 is directly connected to Y, and another part of Z2 is directly connected to Y, the following expression is obtained: It is possible to manifest it.

[0550] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" 2 terminals, etc.) are electrically connected to each other, and X, the source (or The first terminal, the drain of the transistor, the second terminal, etc., and the Y are electrically connected in this order. "The source (or The drain (or second terminal, etc.) of the transistor is electrically connected to X. ) is electrically connected to Y, and X is the source (or first terminal, etc.) of the transistor, The drains (or second terminals, etc.) of the transistors, Y, are electrically connected in this order. Alternatively, "X is the source (or first terminal) of the transistor." ) and the drain (or the second terminal, etc.), and Y is electrically connected to X, The source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor, In these examples, Y is provided in this order. By using various expressions to specify the order of connections in a circuit configuration, The source (or first terminal, etc.) and the drain (or second terminal, etc.) of the transistor are separated. The technical scope can be determined separately.

[0551] Alternatively, for example, "the source (or first terminal, etc.) of a transistor" may be expressed as ) is electrically connected to X through at least a first connection path, and the first connection path does not have a second connection path, and the second connection path is a The source (or first terminal, etc.) of a transistor and the drain (or second terminal, etc.) of a transistor The first connection path is a path via Z1, and the second connection path is a path between the transistor The drain (or second terminal, etc.) of the transistor is connected to Y through at least a third connection path. the third connection path does not include the second connection path, and the third connection path is electrically connected to the The connection path of is the path through Z2. The source (or first terminal, etc.) of the resistor is connected to Z1 by at least the first connection path. and the first connection path does not have a second connection path. The second connection path has a connection path through a transistor, and the drain of the transistor The pin (or the second terminal, etc.) is connected to Y through Z2 by at least a third connection path. The third connection path is electrically connected to the second connection path. Alternatively, the source (or the first terminal, etc.) of the transistor may be The first electric path is electrically connected to X through Z1, The electrical path does not include a second electrical path, and the second electrical path includes a transistor. From the source (or first terminal, etc.) of the transistor to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is an electrical path of at least The third electrical path is electrically connected to Y through Z2, and the third electrical path does not have a fourth electrical path, and the fourth electrical path is An electrical connection from the input (or second terminal, etc.) to the source (or first terminal, etc.) of a transistor. Using the same expression as these examples, the circuit configuration can be expressed as By defining the connection path in the structure, the source (or first terminal) of the transistor The technical scope is determined by distinguishing between the first terminal (or the first terminal, etc.) and the drain (or the second terminal, etc.). This can be done.

[0552] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. X, Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive layers). , layer, etc.). EXAMPLES

[0553] In this example, the hydrogen permeability of conductive membranes was investigated using TDS. Reveal.

[0554] The sample was prepared by forming a 100 nm thick silicon oxide layer on a silicon substrate using thermal oxidation. After that, a silicon oxynitride film having a thickness of 280 nm was formed using a PECVD apparatus. The silicon oxynitride film was formed using 40 sccm silane gas and 300 sccm ammonia gas. The pressure was adjusted to 30 sccm of nitrous oxide gas and 900 sccm of nitrogen gas. Controlled at 160 Pa, substrate temperature 325°C, power output 250 W (frequency 27.12 MHz) The distance between the electrode and the substrate was 20 mm. The silicon oxynitride film contained a large amount of hydrogen. It functions as a hydrogen release film.

[0555] Next, tantalum nitride or titanium nitride is deposited as a barrier film on the silicon oxynitride film by spat deposition. The film was formed using a quartz crystallography apparatus.

[0556] The tantalum nitride film was deposited using a gas atmosphere containing 50 sccm of argon gas and 10 sccm of nitrogen gas. The pressure is controlled to 0.6 Pa in the atmosphere, the substrate temperature is room temperature (about 25°C), and the power output is 1k The tantalum nitride film was deposited at a thickness of 1000 nm and a target-substrate distance of 60 mm. The thicknesses were 10 nm, 20 nm, and 30 nm. For comparison, a tantalum nitride film was not formed. We also prepared a new sample.

[0557] The titanium nitride film was deposited in an atmosphere containing 50 sccm of nitrogen gas with the pressure controlled at 0.2 Pa. The substrate temperature was room temperature, the power output was 12 kW (DC power supply), and the target-substrate distance was 400 The thickness of the titanium nitride film was 10 nm.

[0558] The results of TDS analysis of the samples prepared as described above are shown in Figure 64. The TDS result of 4 shows that the mass-to-charge ratio m / z is 2 (H2, etc.). ) are samples with and without a tantalum nitride barrier film. Figure 64(B) shows the analysis results of the sample with the titanium nitride film formed. show.

[0559] As can be seen from Figures 64(A) and (B), no barrier film is formed on the silicon oxynitride film. Compared with the uncoated sample, the samples with the tantalum nitride film and the titanium nitride film were The temperature at which the outgassing of m / z 2 begins shifts to the higher temperature side, and the thickness of the tantalum nitride film increases. It was found that the temperature at which the degassing of m / z 2 begins shifts to the higher temperature side as the temperature increases. Therefore, tantalum nitride and titanium nitride films have low hydrogen permeability and are effective as hydrogen blocking films. In addition, when the thickness of the tantalum nitride film was 20 nm or more, It was found that the amount of hydrogen released was kept low even at temperatures around 400°C. EXAMPLES

[0560] In this example, the copper blocking property of the conductive film was examined using SIMS (Secondary Electron Microscopy) The results of the investigation using Ion Mass Spectrometry (IMS) are explained below. Here, the SIMS analysis was carried out from the substrate side.

[0561] The sample was prepared by forming a 400 nm thick silicon oxide layer on a silicon substrate by thermal oxidation. After that, a titanium nitride film having a thickness of 200 nm was formed using a sputtering device. A barrier film was formed using a sputtering device. Next, a copper film with a thickness of 200 nm was formed on the The film was formed using a sputtering device. Then, tantalum nitride was sputtered to a thickness of 50 nm. After the deposition, a silicon nitride film of 100 nm was deposited. The barrier film was subjected to heat treatment at 00° C. for 1 hour under four conditions, Conditions 1 to 4. was used.

[0562] Under condition 1, a tantalum film was formed to a thickness of 40 nm. Under condition 2, a tantalum nitride film was formed to a thickness of 40 nm. In condition 3, a tantalum film was formed at 20 nm, and then a tantalum nitride film was formed at 20 nm. In condition 4, a tantalum nitride film was formed at 20 nm, and then a tantalum film was formed at 20 nm. The tantalum film was formed by sputtering at 100 sccm argon gas. The pressure is controlled to 1.4 Pa in an atmosphere containing, the substrate temperature is room temperature (about 25°C), and the power output The experiment was carried out at 2kW (DC power supply) and a target-substrate distance of 60mm. The deposition conditions were sputtering, argon gas 50 sccm and nitrogen gas 1 The pressure was controlled at 0.6 Pa in an atmosphere containing 0 sccm, the substrate temperature was room temperature, and the power output was 1K. The test was performed at 100 W (DC power supply) and a target-substrate distance of 60 mm.

[0563] Next, the results of SIMS analysis of the samples prepared as described above are shown in FIG. The results are shown in Figures 65 and 66. Note that Figures 65 and 66 show the copper concentration in the titanium nitride film.

[0564] From the results shown in Figures 65 and 66, the specimen using a tantalum nitride film as the barrier film (Condition 2 ) the copper concentration in the titanium nitride film is 8×10 19 atoms / cm 3 The degree of In the sample using a tantalum film as the barrier film (condition 1), the copper concentration in the titanium nitride film was 2×10 17 atoms / cm 3 In addition, tantalum and tantalum nitride were used as barrier films. The copper concentration in the titanium nitride film was also kept low in the laminated samples (conditions 3 and 4). These results show that tantalum films have excellent copper blocking properties. Understood. EXAMPLES

[0565] In this embodiment, a design example of a CPU having a storage device according to one embodiment of the present invention will be described.

[0566] Figures 67(A) and (B) show the layout of the CPU. The CPU shown in the figure has a CPU core area and a built-in memory device. Both (A) and (B) of FIG. 67 show the memory area. The area of ​​the CPU core area is 467μm×444μm, and the area of ​​the memory area is 900μm× FIG. 67(A) shows the circuit shown in FIG. 27(C) used as the memory area. FIG. 67(B) shows an example in which the circuit shown in FIG. 27(B) is used as a memory area. Shows.

[0567] The specifications of the CPU in Figures 67(A) and (B) are shown below.

[0568] The chip size was 2.99mm x 2.45mm. The supply voltage was 3.3V and 1 0.2V. A gate voltage input section for a transistor 490 in a memory device. The supply voltage to the peripheral circuits, including the logic circuits, is 3.3V. The supply voltage to the peripheral circuits is 1.2V. The name was V.

[0569] The clock frequency was set to 50 MHz. The minimum gate dimension was set to 65 nm. The power consumption in standby mode is 16.78μW at 27℃ and 12.5μW at 85℃. The power consumption per frequency during operation is estimated to be 3.13μW at 27℃. It was estimated to be 22.07μW / MHz.

[0570] As a storage device for holding, in addition to the storage device shown in FIG. 27(C) or FIG. 27(B), A memory device in which a transistor having an oxide semiconductor and a capacitor are connected to a flip-flop. A transistor including an oxide semiconductor and a capacitor are connected to a flip-flop. This allows the data to be retained even when the power is turned off. The time it takes for data to be stored in the flash memory is estimated to be 20ns at 50MHz operation. The recovery time of the data held in the flip-flop is 40n when operating at 50MHz. The flip-flops were also estimated to last for more than one hour at 85°C. Can be maintained.

[0571] Next, a layout example of a storage device applicable to the memory area of ​​FIG. 67(A) is shown in FIG. The capacity is 2kbytes, and one block consists of 8 word lines and 256 folded lines. It has a total of 16 blocks, with a digit line that is separated by a 100MHz maximum frequency. The power consumption during read and write is 0.539μW and 0.646μW at 50MHz operation. mW (0.40 pJ / bit), read power is 0.521 mW at 50 MHz operation (0.33 pJ / bit), respectively. The data retention time was The area of ​​one bit is 2.9 μm 2 (5.01μm×0.58μm) The chip area is 0.083 mm 2 (0.375mm x 0.22mm). The effective area refers to the area of ​​the memory cell array relative to the entire chip.

[0572] Next, a layout example of a storage device applicable to the memory area of ​​FIG. 67(B) is shown in FIG. The memory capacity is 8kbytes, and the memory is 128 rows x 128 columns, with a capacity of 1 bit. There are four blocks in total, one for resell. The maximum frequency is 67MHz, The power consumption during read is 1.1μW, and the write power is 2.0mW (41 The read power is estimated to be 1.7 mW (34 pJ) at 50 MHz operation. The data retention time is longer than 1 hour at 85°C. The area of ​​1 bit is 1.1 2μm 2 (1.4μm×0.8μm). The chip area was 0.184mm 2 (0.5 49mm x 0.336mm). EXAMPLES

[0573] In this embodiment, a design example of an imaging device using one embodiment of the present invention will be described.

[0574] Fig. 69 shows an example of the layout of an imaging device. The imaging device shown in Fig. 69 has an O An example of an image pickup device using OS transistors is Please refer to embodiment 8.

[0575] The specifications of the imaging device shown in Figure 69 are as follows. The area of ​​the pixel region is 5.2 mm long x 2.8 mm wide. The number of pixels was 1920 x 1080. The size of one pixel was 2.7 μm vertically. The photoelectric conversion element is a photodiode, and the pixel area is four pixels. OS transistors are used. The peripheral circuitry includes a row driver circuit. The readout circuit is a 12-bit single-slope counter type analog A digital conversion circuit and CDS (Correlated Double Sampling g) a circuit. [Explanation of symbols]

[0576] 145 Mixed layer 150 Capacitive element 207 Mask 208 Mask 209 Mask 210 Mask 220 wells 221 p-type semiconductors 223 n-type semiconductor 224 Aperture 225 Aperture 260 First Circuit 270 Second Circuit 273 Electrode 280 Third Circuit 290 4th Circuit 390 Trap Levels 400 Substrates 402 Insulator 404 Conductors 404b Conductor 404d Conductors 406 Semiconductor Layer 406a oxide layer 406b Oxide layer 406c oxide layer 406f oxide layer 407 Channel formation region 408 Insulator 412 Insulators 412d Insulator 413 Conductors 413a Conductors 413b Conductors 413c Electrical conductor 413d Conductor 416a Conductor 416b Conductor 421 Conductors 422 Conductors 423a Low resistance area 423b Low resistance region 426a Conductors 426b Conductors 429 Conductors 442 Insulator 454 Conductors 460 Element isolation area 462 Insulator 464 Insulator 464a Insulators 464b Insulators 470 Insulating Film 474 area 476 area 477 Bulkhead 487 Wiring 488 Conductors 489 Plug 490 Transistors 491 Transistor 492 Transistors 493 Transistor 494 Transistors 500 Semiconductor device 511 Conductors 511a Conductor 511b Conductor 511d Conductor 512 Conductors 513 Conductors 513a Conductors 513b Conductor 514 Conductors 515 Conductors 516 Conductors 516b Conductor 517 Conductors 517a Conductor 517b Conductor 518 Conductor 518b Conductor 519 Conductors 541 Plug 541b Plug 542 Plug 543 Plug 543a Plug 543b Plug 544 Plug 544b Plug 544c plug 545 Plug 546 Plug 547 Plug 547b Plug 548 Plug 571 Insulators 571a Insulator 571b Insulator 572 Insulators 581 Insulators 581a Insulator 581b Insulator 581c Insulator 582 Insulator 583 Insulators 584 Insulators 584a Insulators 584b Insulator 585 Insulator 585a Insulator 585b Insulator 591 Insulators 592 Insulators 592a Insulator 592b Insulator 592c Insulator 593 Insulators 594 Insulators 595 Insulator 599 Insulators 600 Imaging device 601 Photoelectric conversion element 602 Transistor 603 Transistor 604 Transistor 605 Transistor 606 Capacitor 606a Oxide layer 606b Oxide layer 606c oxide layer 607 nodes 608 Wiring 609 Wiring 610 Pixel driving circuit 611 Wiring 612 Insulators 613 Conductors 613a Conductors 613b Conductors 613d Conductor 613e Conductors 614 Conductors 616a Conductor 616b Conductor 618 Insulators 619 Insulators 621 Pixel section 622 pixels 622B pixels 622G pixels 622R pixels 623 pixels 624 Filter 624B Filter 624G Filter 624R Filter 625 layers 626 Wiring group 627 layers 628 layers 629 layers 630 layers 631 layers 632 Opening 635 Lens 641 Height 642 Height 643 Height 660 light 660a Capacitive element 660b Capacitive element 661a Transistor 661b Transistor 662a Transistor 662b Transistor 663a Inverter 663b Inverter 681 Photoelectric conversion layer 682 Transparent conductive layer 686 Conductors 700 Substrates 701 Pixel section 702 First scanning line driving circuit 703 Second scanning line driver circuit 704 Signal Line Driver Circuit 710 Capacitance wiring 712 Gate wiring 713 Gate wiring 714 Drain electrode layer 716 Transistor 717 Transistor 718 Liquid crystal element 719 Liquid crystal element 720 pixels 721 Switching Transistors 722 Driving Transistor 723 Capacitive element 724 Light emitting element 725 Signal Line 726 scan lines 727 Power line 728 Common electrode 800 RF Tags 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 storage device 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 2100 Transistor 2200 Transistor 2900 Portable Game Console 2901 Case 2902 Case 2903 Display section 2904 Display section 2905 Microphone 2906 Speaker 2907 Operation key 2908 Stylus 2910 Information terminal 2911 Case 2912 Display section 2913 Camera 2914 Speaker section 2915 Button 2916 External connection part 2917 Mike 2920 Notebook Personal Computer 2921 Case 2922 Display section 2923 Keyboard 2924 Pointing Device 2940 Video Camera 2941 Case 2942 Case 2943 Display section 2944 Operation key 2945 Lens 2946 Connection 2950 Information terminal 2951 Case 2952 Display section 2960 Information terminal 2961 Case 2962 Display section 2963 Band 2964 Buckle 2965 Operation button 2966 Input / output terminal 2967 Icons 2970 Electric refrigerator 2971 Case 2972 Refrigerator door 2973 Freezer door 2980 Automobiles 2981 Body 2982 wheels 2983 Dashboard 2984 Light 4000 RF tags 5100 pellets 5120 Circuit Board 5161 area

Claims

1. a first layer, a second layer provided on an upper surface of the first layer, and a third layer provided on an upper surface of the second layer; the first layer includes a substrate and first to third transistors located on the substrate; a first insulator on the first to third transistors; a first conductor functioning as a gate electrode of the first transistor; a second conductor functioning as a gate electrode of the second transistor; a first plug electrically connected to the first conductor and embedded in the first insulator; a second plug electrically connected to the second conductor and embedded in the first insulator; a region in which a second insulator is embedded in a trench provided in the substrate between the first transistor and the third transistor; the second layer has a third insulator, a fourth insulator having a region located on the third insulator, a fifth insulator having a region located on the fourth insulator, a sixth insulator having a region located on the fifth insulator, a third conductor disposed so as to be embedded in the third insulator, a fourth conductor disposed so as to be embedded in the sixth insulator, and a third plug disposed so as to be embedded in the fourth insulator and the fifth insulator; the first plug is electrically connected to the first conductor and the third conductor; the third plug is electrically connected to the third conductor and the fourth conductor; the third conductor, the fourth conductor, and the second plug each comprise tantalum nitride; the third layer includes a fourth transistor; one of a source electrode and a drain electrode of the fourth transistor is electrically connected to the fourth conductor; the fourth transistor has a channel formation region formed of an oxide semiconductor.

2. The semiconductor device according to claim 1 , wherein the first insulator comprises hydrogen.

Images