Silicon carbide epitaxial substrate, method of manufacturing silicon carbide epitaxial substrate, and method of manufacturing silicon carbide semiconductor device

Abstract

To provide a silicon carbide epitaxial substrate capable of reducing downfall defects, a method of manufacturing the silicon carbide epitaxial substrate, and a method of manufacturing a silicon carbide semiconductor device.SOLUTION: The silicon carbide epitaxial substrate includes a silicon carbide substrate, a silicon carbide epitaxial layer, and a downfall defect region. The silicon carbide epitaxial layer is on the silicon carbide substrate. The downfall defect region is on the silicon carbide substrate. The downfall defect region includes three or more downfall defects arranged in a straight line when viewed in a direction from the silicon carbide epitaxial layer toward the silicon carbide substrate. The areal density of the downfall defects is 0.2 cm-2 or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a silicon carbide epitaxial substrate, a method for manufacturing a silicon carbide epitaxial substrate, and a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2017-145150 (Patent Document 1) describes a method for manufacturing a silicon carbide epitaxial substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-145150 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present disclosure is to provide a silicon carbide epitaxial substrate capable of reducing downfall defects, a method for manufacturing a silicon carbide epitaxial substrate, and a method for manufacturing a silicon carbide semiconductor device. [Means for solving the problem]

[0005] A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate, a silicon carbide epitaxial layer, and a downfall defect region. The silicon carbide epitaxial layer is on the silicon carbide substrate. The downfall defect region is on the silicon carbide substrate. The downfall defect region includes three or more downfall defects arranged in a straight line when viewed in a direction from the silicon carbide epitaxial layer toward the silicon carbide substrate. The areal density of the downfall defects is less than 0.2 cm -2 The following is the result. Effect of the Invention

[0006] Advantageous Effects of Invention According to the present disclosure, it is possible to provide a silicon carbide epitaxial substrate capable of reducing downfall defects, a method for manufacturing a silicon carbide epitaxial substrate, and a method for manufacturing a silicon carbide semiconductor device. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view illustrating a configuration of a silicon carbide epitaxial substrate according to the first embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 4 is a plan view illustrating a configuration of a silicon carbide epitaxial substrate according to the second embodiment. As shown in FIG. [Diagram 5] FIG. 5 is a partial cross-sectional schematic diagram showing the configuration of an apparatus for manufacturing a silicon carbide epitaxial substrate. [Figure 6] FIG. 6 is a flowchart showing an outline of the method for manufacturing a silicon carbide epitaxial substrate according to this embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a step of transporting the first holder to a chamber. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a step of transporting the second holder to the chamber. [Figure 9] FIG. 9 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device in accordance with this embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a step of forming a body region. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a step of forming a source region. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a step of forming a trench in the first main surface. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a step of forming a gate insulating film. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a step of forming a gate electrode and an interlayer insulating film. [Figure 15] FIG. 15 is a schematic plan view showing a state in which a large number of downfall defects are arranged in a straight line. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] [Overview of the embodiment of the present disclosure] First, an overview of the embodiments of the present disclosure will be described. In the crystallographic description in this specification, an individual orientation is represented by [], a collective orientation by <>, an individual plane by (), and a collective plane by {}. A negative index in crystallography is usually represented by placing a "-" (bar) above the number, but in this specification, a negative index in crystallography is represented by placing a negative sign before the number.

[0009] (1) A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate, a silicon carbide epitaxial layer, and a downfall defect region. The silicon carbide epitaxial layer is on the silicon carbide substrate. The downfall defect region is on the silicon carbide substrate. The downfall defect region includes three or more downfall defects arranged in a straight line when viewed in a direction from the silicon carbide epitaxial layer toward the silicon carbide substrate. The areal density of the downfall defects is less than 0.2 cm -2 The following is the result.

[0010] (2) In the silicon carbide epitaxial substrate according to (1) above, the length of the downfall defect region in the longitudinal direction as viewed in a direction from the silicon carbide epitaxial layer toward the silicon carbide substrate may be not less than 20 mm and not more than 200 mm.

[0011] (3) In the silicon carbide epitaxial substrate according to (1) or (2) above, the length of the downfall defect region in a short side direction as viewed in a direction from the silicon carbide epitaxial layer toward the silicon carbide substrate may be not less than 5 mm and not more than 50 mm.

[0012] (4) In the silicon carbide epitaxial substrate according to any one of (1) to (3) above, the areal density of downfall defects is less than 0.1 cm -2It may be the following.

[0013] (5) A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate, a silicon carbide epitaxial layer, and downfall defects. The silicon carbide epitaxial layer is on the silicon carbide substrate. The downfall defects are on the silicon carbide substrate. The areal density of the downfall defects is less than 0.2 cm -2 The following is the result.

[0014] (6) In the silicon carbide epitaxial substrate according to (5) above, the surface density of downfall defects is less than 0.1 cm -2 It may be the following.

[0015] (7) In the silicon carbide epitaxial substrate according to any one of (1) to (6) above, the downfall defects may be exposed from the silicon carbide epitaxial layer.

[0016] (8) A method for manufacturing a silicon carbide semiconductor device according to the present disclosure includes the following steps: preparing a silicon carbide epitaxial substrate according to any one of (1) to (7) above; forming an electrode on the silicon carbide epitaxial substrate;

[0017] (9) A method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure includes the following steps: A first holder is transferred to a chamber at 300° C. or higher; The first holder is removed from the chamber without forming a silicon carbide epitaxial layer on the first holder; The second holder on which the silicon carbide substrate is disposed is transferred to a chamber at 300° C. or higher; In the chamber, a silicon carbide epitaxial layer is formed on the silicon carbide substrate.

[0018] (10) According to the method for manufacturing a silicon carbide epitaxial substrate according to (9) above, in the step of transporting the first holder to a chamber at 300° C. or higher, the temperature of the chamber may be 1000° C. or lower.

[0019] (11) In the method for manufacturing a silicon carbide epitaxial substrate according to (9) or (10) above, in the step of transporting the first holder to a chamber at 300° C. or higher, the temperature of the chamber may be 600° C. or higher.

[0020] (12) According to any one of the methods for producing a silicon carbide epitaxial substrate according to (9) to (11) above, in the step of transporting the second holder on which the silicon carbide substrate is placed to a chamber at 300° C. or higher, three or more particles present inside the chamber may fall onto the silicon carbide substrate. The three or more particles may be aligned on the silicon carbide substrate in a direction perpendicular to the transport direction of the second holder. The surface density of the three or more particles may be greater than or equal to 0.2 cm. -2 It may be the following.

[0021] (13) In the method for manufacturing a silicon carbide epitaxial substrate according to any one of (9) to (12) above, the first holder may be different from the second holder.

[0022] (14) In the method for manufacturing a silicon carbide epitaxial substrate according to any one of (9) to (12) above, the first holder may be the same as the second holder.

[0023] [Details of the embodiment of the present disclosure] Hereinafter, the details of the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated. (First embodiment) First, the configuration of silicon carbide epitaxial substrate 100 according to the first embodiment will be described. Fig. 1 is a plan view schematic diagram showing the configuration of silicon carbide epitaxial substrate 100 according to the first embodiment. Fig. 2 is a cross-sectional schematic diagram taken along line II-II in Fig. 1.

[0024] As shown in Fig. 1 and Fig. 2, a silicon carbide epitaxial substrate 100 according to the first embodiment has a silicon carbide substrate 10 and a silicon carbide epitaxial layer 20. The silicon carbide epitaxial layer 20 is on the silicon carbide substrate 10. The silicon carbide epitaxial layer 20 has a buffer layer 11 and a drift layer 13. The buffer layer 11 is on the silicon carbide substrate 10. The buffer layer 11 is in contact with the silicon carbide substrate 10. The drift layer 13 is on the buffer layer 11. The drift layer 13 is in contact with the buffer layer 11.

[0025] Silicon carbide epitaxial substrate 100 has a first main surface 1, a second main surface 2, and an outer circumferential edge 5. Drift layer 13 constitutes a front surface (first main surface 1) of silicon carbide epitaxial substrate 100. Silicon carbide substrate 10 constitutes a back surface (second main surface 2) of silicon carbide epitaxial substrate 100. Outer circumferential edge 5 is continuous with each of first main surface 1 and second main surface 2. Outer circumferential edge 5 has, for example, an orientation flat 3 and an arc-shaped portion 4.

[0026] 1 , when viewed in a direction from silicon carbide epitaxial layer 20 toward silicon carbide substrate 10, orientation flat 3 is linear. Orientation flat 3 extends along first direction 101, for example. Arc-shaped portion 4 is continuous with orientation flat 3. Arc-shaped portion 4 is arc-shaped when viewed in a direction perpendicular to first main surface 1.

[0027] 1, when viewed in a direction from silicon carbide epitaxial layer 20 toward silicon carbide substrate 10, first main surface 1 extends along each of a first direction 101 and a second direction 102. When viewed in a direction perpendicular to first main surface 1, first direction 101 is a direction perpendicular to second direction 102.

[0028] The first direction 101 is, for example, the <11-20> direction. The first direction 101 may be, for example, the [11-20] direction. The first direction 101 may be a direction obtained by projecting the <11-20> direction onto the first main surface 1. From another perspective, the first direction 101 may be, for example, a direction including a <11-20> directional component.

[0029] The second direction 102 is, for example, the <1-100> direction. The second direction 102 may be, for example, the [1-100] direction. The second direction 102 may be, for example, a direction obtained by projecting the <1-100> direction onto the first principal surface 1. From another perspective, the second direction 102 may be, for example, a direction including a <1-100> directional component.

[0030] Third direction 103 is a direction perpendicular to each of first direction 101 and second direction 102. Third direction 103 is parallel to the direction from silicon carbide epitaxial layer 20 toward silicon carbide substrate 10.

[0031] The first main surface 1 may be a surface inclined with respect to the {0001} plane. When the first main surface 1 is inclined with respect to the {0001} plane, the inclination angle (off angle) with respect to the {0001} plane is, for example, 2° or more and 6° or less. When the first main surface 1 is inclined with respect to the {0001} plane, the inclination direction (off direction) of the first main surface 1 is, for example, the <11-20> direction.

[0032] As shown in FIG. 1, the maximum diameter W of the first main surface 1 is not particularly limited, but is, for example, 100 mm (4 inches). It may be 150 mm (6 inches) or more. The upper limit of the maximum diameter W is not particularly limited. The maximum diameter W may be, for example, 200 mm (8 inches) or less. When viewed in the third direction 103, the maximum diameter W is the longest straight line distance between two different points on the outer circumferential edge 5.

[0033] In this specification, 4 inches means 100 mm or 101.6 mm (4 inches x 25.4 mm / inch). 6 inches means 150 mm or 152.4 mm (6 inches x 25.4 mm / inch). 8 inches means 200 mm or 203.2 mm (8 inches x 25.4 mm / inch).

[0034] The polytype of silicon carbide constituting silicon carbide substrate 10 is, for example, 4H. The polytype of silicon carbide constituting silicon carbide epitaxial layer 20 is, for example, 4H. Silicon carbide substrate 10 contains an n-type impurity such as nitrogen (N). The conductivity type of silicon carbide substrate 10 is, for example, n-type (first conductivity type). Silicon carbide substrate 10 has a thickness of, for example, 350 μm or more and 500 μm or less.

[0035] Silicon carbide epitaxial layer 20 contains an n-type impurity such as nitrogen. The conductivity type of silicon carbide epitaxial layer 20 is, for example, n-type. The concentration of the n-type impurity contained in buffer layer 11 may be lower than the concentration of the n-type impurity contained in silicon carbide substrate 10. The concentration of the n-type impurity contained in drift layer 13 may be lower than the concentration of the n-type impurity contained in buffer layer 11.

[0036] Fig. 3 is a schematic cross-sectional view taken along line III-III in Fig. 1. As shown in Fig. 3, silicon carbide epitaxial substrate 100 has downfall defects 6. Downfall defects 6 are deposits that have accumulated on the inner wall of chamber 201 (described later) and have fallen onto silicon carbide substrate 10. Downfall defects 6 are made of, for example, polycrystalline silicon carbide, carbon, tantalum carbide (TaC), or the like.

[0037] The downfall defect 6 is in the silicon carbide substrate 10. The bottom of the downfall defect 6 may be in contact with the silicon carbide substrate 10. When viewed in a direction from the silicon carbide epitaxial layer 20 toward the silicon carbide substrate 10, the downfall defect 6 is surrounded by the silicon carbide epitaxial layer 20. When viewed in a direction from the silicon carbide epitaxial layer 20 toward the silicon carbide substrate 10, the downfall defect 6 may be surrounded by the buffer layer 11 or the drift layer 13.

[0038] A recess 8 is provided on the first main surface 1 of silicon carbide epitaxial substrate 100. Downfall defects 6 are present inside the recess 8. Buffer layer 11 has a first side surface 15. Drift layer 13 has a second side surface 16. Second side surface 16 is continuous with first side surface 15 and first main surface 1. Recess 8 is, for example, composed of first side surface 15 and second side surface 16.

[0039] When viewed in a direction from the silicon carbide epitaxial layer 20 toward the silicon carbide substrate 10, the first side surface 15 surrounds the downfall defect 6. The downfall defect 6 may be exposed from the silicon carbide epitaxial layer 20. A part of the first side surface 15 may be in contact with the downfall defect 6 or may be spaced apart from the downfall defect 6. When viewed in a direction from the silicon carbide epitaxial layer 20 toward the silicon carbide substrate 10, the second side surface 16 surrounds the downfall defect 6. The second side surface 16 may be in contact with the downfall defect 6 or may be spaced apart from the downfall defect 6.

[0040] As viewed in a direction from silicon carbide epitaxial layer 20 toward silicon carbide substrate 10, maximum width D of downfall defect 6 may be smaller than, larger than, or the same as the thickness of silicon carbide epitaxial layer 20. Maximum width D of downfall defect 6 may be larger than, smaller than, or the same as the depth of recess 8.

[0041] The maximum width D is, for example, 2 μm or more and 300 μm or less. The maximum width D may be 100 μm or less, or 40 μm or less. The maximum width D may be 4 μm or more, or 6 μm or more.

[0042] Next, the areal density of the downfall defects 6 in the silicon carbide epitaxial substrate 100 according to the first embodiment will be described. In the silicon carbide epitaxial substrate 100 according to this embodiment, the areal density of the downfall defects 6 is 0.2 cm -2 The surface density of downfall defect 6 is 0.01 cm -2 It may be more than 0.02 cm -2 The surface density of the downfall defects 6 may be 0.15 cm -2 May be less than 0.1cm -2 May be less than 0.08cm -2 It may be the following.

[0043] (Method of measuring downfall defects) Next, a method for measuring the downfall defect 6 will be described.

[0044] The downfall defects 6 can be identified by observing the surface (first main surface 1) of the silicon carbide epitaxial layer 20 using a defect inspection device equipped with, for example, a confocal differential interference microscope. As a defect inspection device equipped with a confocal differential interference microscope, for example, the WASAVI series "SICA 6X" manufactured by Lasertec Corporation can be used. The magnification of the objective lens is, for example, 10 times. The detection sensitivity threshold of the defect inspection device is determined using a standard sample. The downfall defects 6 are defined in advance taking into consideration the typical planar shape, dimensions, etc. of the downfall defects 6. The positions and number of defects that meet the definition of the downfall defects 6 are identified based on the observed image.

[0045] While moving silicon carbide epitaxial substrate 100 in a direction parallel to the surface (first main surface 1) of silicon carbide epitaxial layer 20, a confocal differential interference microscope image of the entire first main surface 1 is taken. Downfall defects 6 are observed in the acquired confocal differential interference microscope image. The total number of downfall defects 6 is determined in the acquired confocal differential interference microscope image. The number of downfall defects 6 divided by the area of ​​the measurement region of first main surface 1 is determined as the areal density. The measurement region is the region of first main surface 1 excluding the peripheral region within 3 mm from the outer periphery 5. Second embodiment Next, the configuration of the silicon carbide epitaxial substrate according to the second embodiment will be described. The silicon carbide epitaxial substrate according to the second embodiment differs from the silicon carbide epitaxial substrate according to the first embodiment in that it has a downfall defect region, and is substantially the same as the silicon carbide epitaxial substrate according to the first embodiment in other respects. The following description will focus on the configuration that differs from the silicon carbide epitaxial substrate according to the first embodiment.

[0046] Fig. 4 is a plan view schematic diagram showing a configuration of a silicon carbide epitaxial substrate 100 according to the second embodiment. As shown in Fig. 4, the silicon carbide epitaxial substrate 100 has a downfall defect region 7. The downfall defect region 7 is on a silicon carbide substrate 10. The downfall defect region 7 includes three or more downfall defects 6 arranged in a straight line when viewed in a direction from the silicon carbide epitaxial layer 20 toward the silicon carbide substrate 10.

[0047] The direction in which three or more downfall defects 6 are aligned is defined as a fourth direction 104. The fourth direction 104 is the longitudinal direction of the downfall defect region 7. The fourth direction 104 is perpendicular to the direction from the silicon carbide epitaxial layer 20 to the silicon carbide substrate 10. When viewed in the direction from the silicon carbide epitaxial layer 20 to the silicon carbide substrate 10, the fourth direction 104 may be parallel to the first direction 101 or may be inclined with respect to the first direction 101.

[0048] A direction perpendicular to the fourth direction 104 when viewed from the silicon carbide epitaxial layer 20 toward the silicon carbide substrate 10 is defined as a fifth direction 105. The fifth direction 105 is a short-side direction of the downfall defect region 7. The fifth direction 105 is perpendicular to a direction from the silicon carbide epitaxial layer 20 toward the silicon carbide substrate 10. When viewed from the silicon carbide epitaxial layer 20 toward the silicon carbide substrate 10, the fifth direction 105 may be parallel to the second direction 102 or may be inclined with respect to the second direction 102.

[0049] The downfall defect region 7 may include four or more downfall defects 6 arranged in a straight line when viewed in a direction from the silicon carbide epitaxial layer 20 toward the silicon carbide substrate 10, or may include five or more downfall defects 6 arranged in a straight line. The downfall defect region 7 may include ten or less downfall defects 6 arranged in a straight line when viewed in a direction from the silicon carbide epitaxial layer 20 toward the silicon carbide substrate 10, or may include eight or less downfall defects 6 arranged in a straight line.

[0050] 4, the length of the downfall defect region 7 in the longitudinal direction as viewed in a direction from the silicon carbide epitaxial layer 20 toward the silicon carbide substrate 10 (hereinafter also referred to as a first length A1) is, for example, 20 mm or more and 200 mm or less. The first length A1 may be 30 mm or more, or 40 mm or more. The first length A1 may be 180 mm or less, or 150 mm or less.

[0051] 4, the length of the downfall defect region 7 in the short side direction as viewed in the direction from the silicon carbide epitaxial layer 20 toward the silicon carbide substrate 10 (hereinafter also referred to as the second length A2) is, for example, 5 mm or more and 50 mm or less. The second length A2 may be 8 mm or more, or 10 mm or more. The second length A2 may be 40 mm or less, or 30 mm or less.

[0052] As shown in FIG. 4, three or more rows of downfall defects 6 arranged along the fourth direction 104 may be arranged in two or more rows along the fifth direction 105. In this case, the length between the end of the downfall defect 6 located on the outermost side in the fourth direction 104 and the end of the downfall defect 6 located on the outermost side in the direction opposite to the fourth direction 104 is defined as a first length A1. Similarly, the length between the end of the downfall defect 6 located on the outermost side in the fifth direction 105 and the end of the downfall defect 6 located on the outermost side in the direction opposite to the fifth direction 105 is defined as a second length A2. In FIG. 4, three or more rows of downfall defects 6 arranged along the fourth direction 104 are arranged in three rows along the fifth direction 105.

[0053] In consideration of the distance between each of the multiple downfall defects 6 in the silicon carbide epitaxial substrate 100 and their overall distribution, when the distance between each of the multiple downfall defects 6 is relatively small, the multiple downfall defects 6 are close to each other, and it is possible to consider a downfall defect region 7 as a band-like rectangular region as shown in FIG. 4 (i.e., it is possible to consider the multiple downfall defects 6 as being arranged in a straight line), it is considered that a downfall defect region 7 exists in the silicon carbide epitaxial substrate 100.

[0054] Next, the areal density of the downfall defects 6 in the silicon carbide epitaxial substrate 100 according to the second embodiment will be described. In the silicon carbide epitaxial substrate 100 according to this embodiment, the areal density of the downfall defects 6 is 0.2 cm -2 The surface density of downfall defect 6 is 0.01 cm -2 It may be more than 0.02 cm -2 The surface density of the downfall defects 6 may be 0.15 cm -2 May be less than 0.1cm -2 May be less than 0.08cm -2 It may be the following.

[0055] (Silicon carbide epitaxial substrate manufacturing equipment) Next, the configuration of manufacturing apparatus 200 for silicon carbide epitaxial substrate 100 will be described.

[0056] Fig. 5 is a partial cross-sectional schematic diagram showing the configuration of an apparatus for manufacturing silicon carbide epitaxial substrate 100. As shown in Fig. 5, manufacturing apparatus 200 for silicon carbide epitaxial substrate 100 is, for example, a hot-wall type horizontal CVD (Chemical Vapor Deposition) apparatus. Manufacturing apparatus 200 mainly includes a chamber 201, a stage 206, a gas supply unit 235, a control unit 245, a heating element 203, and an induction heating coil (not shown).

[0057] The heating element 203 has, for example, a cylindrical shape. The heating element 203 is made of, for example, graphite. The induction heating coil is wound around the chamber 201, for example. The induction heating coil is configured so that an alternating current can be supplied to it by an external power source (not shown). This causes the heating element 203 to be induction heated. As a result, the chamber 201 is heated by the heating element 203.

[0058] Chamber 201 constitutes a space surrounded by inner wall surface 205 of heating element 203. Silicon carbide substrate 10 is disposed in chamber 201. Chamber 201 is configured to be capable of heating silicon carbide substrate 10. A holder for holding silicon carbide substrate 10 is disposed in chamber 201. The holder is disposed on stage 206. Stage 206 is configured to be rotatable about its axis by rotation shaft 209. The holder rotates as stage 206 rotates.

[0059] The manufacturing apparatus 200 further has a gas inlet 207 and a gas exhaust port 208. The gas exhaust port 208 is connected to an exhaust pump (not shown). The arrows in FIG. 5 indicate the flow of gas. The gas is introduced into the chamber 201 from the gas inlet 207 and exhausted from the gas exhaust port 208. The pressure inside the chamber 201 is adjusted by balancing the amount of gas supplied and the amount of gas exhausted.

[0060] The gas supply unit 235 is configured to be able to supply a mixed gas containing, for example, silane, propane, ammonia, and hydrogen to the chamber 201. Specifically, the gas supply unit 235 may include a first gas supply unit 231, a second gas supply unit 232, a third gas supply unit 233, and a carrier gas supply unit 234.

[0061] The first gas supply unit 231 is configured to be able to supply the first gas. The first gas supply unit 231 is, for example, a gas cylinder filled with the first gas. The first gas is, for example, propane (C3H8) gas. The first gas may be, for example, methane (CH4) gas, ethane (C2H6) gas, acetylene (C2H2) gas, or the like.

[0062] The second gas supply unit 232 is configured to be able to supply the second gas. The second gas supply unit 232 is, for example, a gas cylinder filled with the second gas. The second gas is, for example, silane (SiH4) gas. The second gas may be a mixed gas of silane gas and a gas other than silane.

[0063] The third gas supply unit 233 is configured to be able to supply the third gas. The third gas supply unit 233 is, for example, a gas cylinder filled with the third gas. The third gas is a doping gas containing N (nitrogen atom). Ammonia gas is more easily thermally decomposed than nitrogen gas having a triple bond. By using ammonia gas, it is expected that the in-plane uniformity of the carrier concentration can be improved.

[0064] The carrier gas supply unit 234 is configured to be able to supply a carrier gas such as hydrogen, for example. The carrier gas supply unit 234 is, for example, a gas cylinder filled with hydrogen.

[0065] The control unit 245 is configured to be able to control the flow rate of the mixed gas supplied from the gas supply unit 235 to the chamber 201. Specifically, the control unit 245 may include a first gas flow rate control unit 241, a second gas flow rate control unit 242, a third gas flow rate control unit 243, and a carrier gas flow rate control unit 244. Each control unit may be, for example, an MFC (Mass Flow Controller). The control unit 245 is disposed between the gas supply unit 235 and the gas inlet 207. In other words, the control unit 245 is disposed in a flow path connecting the gas supply unit 235 and the gas inlet 207.

[0066] (Method for manufacturing silicon carbide epitaxial substrate) Next, a method for manufacturing silicon carbide epitaxial substrate 100 in accordance with this embodiment will be described.

[0067] Fig. 6 is a flow chart showing an outline of a method for manufacturing a silicon carbide epitaxial substrate 100 according to this embodiment. As shown in Fig. 6, the method for manufacturing a silicon carbide epitaxial substrate 100 according to this embodiment mainly includes a step (S10) of transporting a first holder to a chamber, a step (S20) of removing the first holder from the chamber, a step (S30) of transporting a second holder on which a silicon carbide substrate is arranged to the chamber, and a step (S40) of forming a silicon carbide epitaxial layer on the silicon carbide substrate.

[0068] First, a silicon carbide substrate 10 is prepared. A silicon carbide single crystal of polytype 4H is manufactured, for example, by sublimation. Next, the silicon carbide single crystal is sliced, for example, by a wire saw, to prepare the silicon carbide substrate 10. The silicon carbide substrate 10 contains an n-type impurity, for example, nitrogen. The conductivity type of the silicon carbide substrate 10 is, for example, an n-type.

[0069] Next, a step (S10) of transporting first holder 31 to chamber 201 is performed. FIG. 7 is a schematic cross-sectional view showing the step of transporting first holder 31 to chamber 201. As shown in FIG. 7, first holder 31 is transported to chamber 201. First holder 31 is transported along transport direction B1. First holder 31 moves from the outside of chamber 201 to the inside of chamber 201 along transport direction B1. In the step (S10) of transporting first holder 31 to chamber 201, no silicon carbide substrate 10 is disposed on first holder 31.

[0070] The chamber 201 is heated by, for example, a heating element 203. The temperature of the chamber 201 is 300° C. or higher. The temperature of the chamber 201 may be 400° C. or higher, 500° C. or higher, or 600° C. or higher. The temperature of the chamber 201 may be 1000° C. or lower, 900° C. or lower, or 800° C. or lower. When there is a temperature variation inside the chamber 201, the temperature of the chamber 201 refers to the highest temperature inside the chamber 201. The pressure of the chamber 201 is, for example, 1×10 -1 It is Pa.

[0071] As shown in FIG. 7, first holder 31 is disposed in a region surrounded by heating element 203 inside chamber 201. First holder 31 is formed with substrate placement portion 33 on which silicon carbide substrate 10 is disposed. The bottom surface of substrate placement portion 33 faces heating element 203. First holder 31 is disposed in chamber 201 for, for example, three minutes. First holder 31 is heated for, for example, three minutes at a temperature of 600° C. or more and 900° C. or less. The heating time of first holder 31 may be three minutes or more.

[0072] In the step (S10) of transporting first holder 31 to chamber 201, the three or more particles present inside chamber 201 may fall onto the bottom surface of substrate placement section 33. The particles present inside chamber 201 are, for example, silicon carbide particles or carbon particles attached to heating element 203. The three or more particles may be aligned on the bottom surface of substrate placement section 33 in a direction perpendicular to the transport direction of first holder 31. The surface density of the three or more particles on the bottom surface of substrate placement section 33 may be, for example, 0.2 cm -2 It may be larger than.

[0073] Next, a step (S20) of removing first holder 31 from chamber 201 is performed. First holder 31 is removed from chamber 201. First holder 31 is removed along a carrying-out direction B2. First holder 31 moves from inside chamber 201 to outside chamber 201 along carrying-out direction B2. In the step (S20) of removing first holder 31 from chamber 201, no silicon carbide substrate 10 is placed on first holder 31.

[0074] Between the step (S10) of transporting first holder 31 to chamber 201 and the step (S20) of removing first holder 31 from chamber 201, silicon carbide epitaxial layer 20 is not formed on first holder 31. In the step (S20) of removing first holder 31 from chamber 201, first holder 31 is removed from chamber 201 without forming silicon carbide epitaxial layer 20 on first holder 31.

[0075] Next, a step (S30) of transporting second holder 32 on which silicon carbide substrate 10 is arranged to chamber 201 is performed. FIG. 8 is a schematic cross-sectional view showing the step of transporting second holder 32 to chamber 201. As shown in FIG. 8, second holder 32 is transported to chamber 201. Second holder 32 is transported along transport direction B1. Second holder 32 moves from the outside of chamber 201 to the inside of chamber 201 along transport direction B1. Silicon carbide substrate 10 is arranged on second holder 32. Specifically, silicon carbide substrate 10 is arranged on substrate arrangement portion 34 formed on second holder 32.

[0076] The temperature of the chamber 201 is 300° C. or higher. The temperature of the chamber 201 may be 400° C. or higher, 500° C. or higher, or 600° C. or higher. The temperature of the chamber 201 may be 1000° C. or lower, 900° C. or lower, or 800° C. or lower.

[0077] In the step (S30) of transporting second holder 32 on which silicon carbide substrate 10 is arranged to chamber 201, three or more particles present inside chamber 201 may fall onto silicon carbide substrate 10. The particles present inside chamber 201 are, for example, silicon carbide particles or carbon particles attached to heating element 203. The three or more particles may be aligned on silicon carbide substrate 10 in a direction perpendicular to the transport direction of second holder 32. The surface density of the three or more particles on silicon carbide substrate 10 is, for example, 0.2 cm -2 May be less than 0.15cm -2 May be less than 0.1cm -2 It may be the following.

[0078] Next, a step (S40) of forming silicon carbide epitaxial layer 20 on silicon carbide substrate 10 is performed. First, second holder 32 is transferred to chamber 201, and then chamber 201 is further heated. The temperature of chamber 201 is heated from a temperature of, for example, 600° C. or more and 900° C. or less to 1600° C. After the temperature of chamber 201 reaches, for example, about 1600° C., a source gas, a dopant gas, and a carrier gas are supplied to chamber 201. Specifically, a mixed gas containing silane, propane, ammonia, and hydrogen is supplied to chamber 201. The flow rate of silane is, for example, 29 sccm. The flow rate of propane is, for example, 46 sccm. The flow rate of ammonia is, for example, 1.5 sccm. The pressure of chamber 201 is, for example, 2 kPa or more and 6 kPa or less.

[0079] As a result, silicon carbide epitaxial layer 20 is formed on silicon carbide substrate 10 in chamber 201. In this manner, silicon carbide epitaxial substrate 100 (FIG. 1) according to the present embodiment is manufactured.

[0080] The second holder 32 may be the same as the first holder 31 or may be different from the first holder 31. When the second holder 32 is the same as the first holder 31, the first holder 31 is heated to a temperature of 300° C. or higher, and then the silicon carbide substrate 10 is placed on the substrate placement portion 33 formed on the first holder 31. Next, the first holder 31 on which the silicon carbide substrate 10 is placed is placed again in the chamber 201, and the silicon carbide epitaxial layer 20 is formed on the silicon carbide substrate 10 in the chamber 201.

[0081] (Silicon carbide semiconductor device) Next, the configuration of the silicon carbide semiconductor device 300 according to this embodiment will be described. FIG. 9 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device 300 according to this embodiment. As shown in FIG. 9, the silicon carbide semiconductor device 300 according to this embodiment mainly includes a silicon carbide epitaxial substrate 100, a gate insulating film 115, a gate electrode 127, a source electrode 116, a drain electrode 120, a source wiring 119, and an interlayer insulating film 126. The silicon carbide epitaxial substrate 100 includes a silicon carbide substrate 10, a silicon carbide epitaxial layer 20, a first main surface 1, and a second main surface 2. The silicon carbide epitaxial layer 20 includes a buffer layer 11, a drift layer 13, a body region 113, a source region 114, and a contact region 118.

[0082] The body region 113 is formed on the drift layer 13. The body region 113 is in contact with the drift layer 13. The body region 113 contains p-type impurities such as aluminum. The body region 113 has a p-type conductivity. The source region 114 is formed on the body region 113. The source region 114 contains n-type impurities such as phosphorus. The source region 114 has an n-type conductivity. The concentration of the n-type impurities contained in the source region 114 may be higher than the concentration of the p-type impurities contained in the body region 113.

[0083] The contact region 118 penetrates the source region 114 and the body region 113. The contact region 118 is in contact with each of the source region 114, the body region 113, and the drift layer 13. The contact region 118 contains a p-type impurity such as aluminum. The concentration of the p-type impurity contained in the contact region 118 may be higher than the concentration of the n-type impurity contained in the source region 114.

[0084] A trench 106 is provided in the first main surface 1. The trench 106 is defined by a side surface 123 and a bottom surface 124. The side surface 123 is formed by the source region 114, the body region 113, and the drift layer 13. The bottom surface 124 is formed by the drift layer 13.

[0085] The gate insulating film 115 is in contact with the drift layer 13 at a bottom surface 124, and is in contact with each of the drift layer 13, the body region 113, and the source region 114 at a side surface 123. The gate electrode 127 is disposed on the gate insulating film 115. The gate electrode 127 is in contact with the gate insulating film 115 inside the trench 106. The gate electrode 127 faces each of the side surface 123 and the bottom surface 124 of the trench 106.

[0086] The interlayer insulating film 126 covers the gate electrode 127. The interlayer insulating film 126 is in contact with the gate insulating film 115. The interlayer insulating film 126 is made of a material containing, for example, silicon dioxide. The source electrode 116 is in contact with each of the source region 114 and the contact region 118. The source electrode 116 is made of a material containing, for example, Ti, Al, and Si. The source wiring 119 is in contact with the source electrode 116. The source wiring 119 is electrically connected to the source electrode 116. The source wiring 119 covers the source electrode 116 and the interlayer insulating film 126. The drain electrode 120 is in contact with the silicon carbide substrate 10 on the second main surface 2.

[0087] In the above embodiment, the silicon carbide semiconductor device 300 is a MOSFET, but the silicon carbide semiconductor device 300 is not limited to a MOSFET. The silicon carbide semiconductor device 300 may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like.

[0088] (Method for manufacturing silicon carbide semiconductor device) Next, a method for manufacturing the silicon carbide semiconductor device 300 according to this embodiment will be described.

[0089] First, a silicon carbide epitaxial substrate 100 according to this embodiment is prepared (see FIG. 1). Next, a step of forming a body region is performed. FIG. 10 is a schematic cross-sectional view showing the step of forming a body region. Specifically, p-type impurities such as aluminum are ion-implanted into drift layer 13 of silicon carbide epitaxial layer 20. This forms body region 113 having p-type conductivity. Body region 113 has a thickness of, for example, 0.9 μm.

[0090] Next, a step of forming a source region is performed. Fig. 11 is a schematic cross-sectional view showing the step of forming a source region. Specifically, n-type impurities such as phosphorus are ion-implanted into the body region 113. This forms a source region 114 having an n-type conductivity. The thickness of the source region 114 is, for example, 0.4 µm. The concentration of the n-type impurity contained in the source region 114 may be higher than the concentration of the p-type impurity contained in the body region 113.

[0091] Next, a p-type impurity such as aluminum is ion-implanted into the source region 114 to form a contact region 118. The contact region 118 is formed so as to penetrate the source region 114 and the body region 113 and to be in contact with the drift layer 13. The concentration of the p-type impurity contained in the contact region 118 may be higher than the concentration of the n-type impurity contained in the source region 114.

[0092] Next, activation annealing is performed to activate the implanted impurities. The temperature of the activation annealing is, for example, 1500° C. to 1900° C. The activation annealing time is, for example, about 30 minutes. The atmosphere of the activation annealing is, for example, an Ar atmosphere.

[0093] Next, a step of forming a trench in the first main surface 1 is performed. FIG. 12 is a cross-sectional schematic diagram showing a step of forming a trench in the first main surface 1. As shown in FIG. 12, a mask 117 having an opening is formed on the first main surface 1 including the source region 114 and the contact region 118. Using the mask 117, the source region 114, the body region 113, and a part of the drift layer 13 are removed by etching. As an etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching, can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF6 or a mixed gas of SF6 and O2 as a reactive gas can be used. A recess is formed in the first main surface 1 by etching.

[0094] Next, thermal etching is performed in the recess. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms, with the mask 117 formed on the first main surface 1. The at least one or more types of halogen atoms include at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, Cl2, BCl3, SF6, or CF4. For example, a mixed gas of chlorine gas and oxygen gas is used as the reactive gas, and the thermal etching is performed at a heat treatment temperature of, for example, 700°C or more and 1000°C or less. Note that the reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. For example, nitrogen gas, argon gas, or helium gas can be used as the carrier gas.

[0095] 12, trench 106 is formed in first main surface 1 by thermal etching. Trench 106 is defined by side surface 123 and a bottom surface 124. Side surface 123 is composed of source region 114, body region 113, and drift layer 13. Bottom surface 124 is composed of drift layer 13. Next, mask 117 is removed from first main surface 1.

[0096] Next, a step of forming a gate insulating film is performed. Fig. 13 is a cross-sectional schematic diagram showing the step of forming a gate insulating film. Specifically, silicon carbide epitaxial substrate 100 having trench 106 formed in first main surface 1 is heated in an atmosphere containing oxygen at a temperature of, for example, 1300°C or more and 1400°C or less. As a result, gate insulating film 115 is formed, which is in contact with drift layer 13 at bottom surface 124, in contact with drift layer 13, body region 113, and source region 114 at side surface 123, and in contact with source region 114 and contact region 118 at first main surface 1.

[0097] Next, a step of forming a gate electrode is performed. Fig. 14 is a schematic cross-sectional view showing a step of forming a gate electrode and an interlayer insulating film. The gate electrode 127 is formed in the trench 106 so as to contact the gate insulating film 115. The gate electrode 127 is disposed in the trench 106, and is formed on the gate insulating film 115 so as to face each of the side surface 123 and the bottom surface 124 of the trench 106. The gate electrode 127 is formed, for example, by a low pressure chemical vapor deposition (LPCVD) method.

[0098] Next, the interlayer insulating film 126 is formed. The interlayer insulating film 126 is formed so as to cover the gate electrode 127 and to be in contact with the gate insulating film 115. The interlayer insulating film 126 is formed, for example, by chemical vapor deposition. The interlayer insulating film 126 is made of a material containing, for example, silicon dioxide. Next, the interlayer insulating film 126 and the gate insulating film 115 are partly etched so as to form openings on the source region 114 and the contact region 118. As a result, the contact region 118 and the source region 114 are exposed from the gate insulating film 115.

[0099] Next, a step of forming a source electrode is performed. The source electrode 116 is formed so as to be in contact with each of the source region 114 and the contact region 118. The source electrode 116 is formed by, for example, a sputtering method. The source electrode 116 is made of, for example, a material including Ti, Al, and Si.

[0100] Next, alloying annealing is performed. Specifically, the source electrode 116 in contact with each of the source region 114 and the contact region 118 is held at a temperature of, for example, 900° C. or more and 1100° C. or less for about 5 minutes. As a result, at least a portion of the source electrode 116 is silicided. As a result, the source electrode 116 that forms an ohmic junction with the source region 114 is formed. The source electrode 116 forms an ohmic junction with the contact region 118.

[0101] Next, the source wiring 119 is formed. The source wiring 119 is electrically connected to the source electrode 116. The source wiring 119 is formed so as to cover the source electrode 116 and the interlayer insulating film 126.

[0102] Next, a step of forming the drain electrode 120 is performed. First, the silicon carbide substrate 10 is polished at the second main surface 2. Next, the drain electrode 120 is formed. The drain electrode 120 is formed so as to be in contact with the silicon carbide substrate 10 at the second main surface 2. In this manner, the silicon carbide semiconductor device 300 according to this embodiment is manufactured (see FIG. 9).

[0103] Next, the effects of silicon carbide epitaxial substrate 100, a method for manufacturing silicon carbide epitaxial substrate 100, and a method for manufacturing silicon carbide semiconductor device 300 according to this embodiment will be described.

[0104] A CVD apparatus is generally used when forming the silicon carbide epitaxial layer 20 on the silicon carbide substrate 10. When the silicon carbide substrate 10 is placed in a chamber 201 of the CVD apparatus, particles adhering to the heating element 203 and the like inside the chamber 201 may fall onto the silicon carbide substrate 10. When the silicon carbide epitaxial layer 20 is formed on the silicon carbide substrate 10 onto which the particles have fallen, downfall defects 6 are formed due to the particles.

[0105] One method for reducing downfall defects 6 is to remove particles that have fallen onto silicon carbide substrate 10 by hydrogen etching. Another method is to clean the inside of chamber 201 before epitaxial growth to remove particles within chamber 201. However, these methods have a problem in that the manufacturing process of silicon carbide epitaxial substrate 100 becomes longer.

[0106] Therefore, the inventors have intensively studied measures for effectively reducing the downfall defects 6, and have obtained the following findings. First, immediately before the silicon carbide epitaxial layer 20 is actually formed on the silicon carbide substrate 10, the holder is transported to the high-temperature chamber 201. Since the temperature of the holder is approximately room temperature, when the holder is placed inside the high-temperature chamber 201, the inside of the chamber 201 is rapidly cooled. Therefore, inside the chamber 201, particles attached to the heating element 203 and the like contract and fall onto the holder. As a result, inside the chamber 201, the particles attached to the heating element 203 and the like are removed. Next, the holder on which the silicon carbide substrate 10 is placed is transported to the chamber 201, and the silicon carbide epitaxial layer 20 is formed on the silicon carbide substrate 10.

[0107] According to the method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment, first holder 31 is transferred to chamber 201 at 300° C. or higher. First holder 31 is removed from chamber 201 without forming silicon carbide epitaxial layer 20 on first holder 31. Second holder 32 on which silicon carbide substrate 10 is placed is transferred to chamber 201 at 300° C. or higher. In chamber 201, silicon carbide epitaxial layer 20 is formed on silicon carbide substrate 10. This makes it possible to reduce downfall defects 6 in silicon carbide epitaxial substrate 100.

[0108] According to the method for manufacturing silicon carbide epitaxial substrate 100 in accordance with the present embodiment, in the step of transporting first holder 31 to chamber 201 at 300° C. or higher, the temperature of chamber 201 may be 1000° C. or lower. If the temperature of chamber 201 is excessively high, first holder 31 will be severely damaged. By setting the temperature of chamber 201 to 1000° C. or lower, damage to first holder 31 can be suppressed.

[0109] According to the method for manufacturing silicon carbide epitaxial substrate 100 according to the present embodiment, in the step of transporting first holder 31 to chamber 201 at 300° C. or higher, the temperature of chamber 201 may be 600° C. or higher. This increases the temperature difference between first holder 31 and chamber 201, making it easier for particles inside chamber 201 to fall. As a result, downfall defects 6 can be further reduced in silicon carbide epitaxial substrate 100.

[0110] According to the method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment, in the step of transporting second holder 32, on which silicon carbide substrate 10 is arranged, to chamber 201 at 300° C. or higher, three or more particles present inside chamber 201 may fall onto silicon carbide substrate 10. The three or more particles may be aligned on silicon carbide substrate 10 in a direction perpendicular to the transport direction of second holder 32. The surface density of the three or more particles is 0.2 cm -2This can reduce the surface density of the particles aligned in a direction perpendicular to the conveying direction of the second holder 32.

[0111] According to the method for manufacturing silicon carbide epitaxial substrate 100 in accordance with the present embodiment, first holder 31 may be different from second holder 32. In this case, the step of removing particles that have fallen onto first holder 31 can be omitted, thereby simplifying the manufacturing process.

[0112] According to the manufacturing method of the silicon carbide epitaxial substrate 100 according to the present embodiment, the first holder 31 may be the same as the second holder 32. In this case, the silicon carbide epitaxial layer 20 can be formed on the silicon carbide substrate 10 using the first holder 31. Therefore, the removal of particles and the formation of the silicon carbide epitaxial layer 20 can be performed with one holder. Furthermore, in the step of transporting the second holder 32 on which the silicon carbide substrate 10 is arranged to the chamber 201 at 300° C. or higher, if the first holder 31 corresponding to the second holder 32 is higher than room temperature, the temperature difference between the first holder 31 and the chamber 201 becomes small. Therefore, in the step of transporting the second holder 32 on which the silicon carbide substrate 10 is arranged to the chamber 201 at 300° C. or higher, it is possible to further suppress particles in the chamber 201 from falling onto the silicon carbide substrate 10.

[0113] The inventors have noticed that, while observing a silicon carbide epitaxial substrate 100 having downfall defects 6, a downfall defect region 7 including three or more downfall defects 6 arranged in a straight line may occur in the silicon carbide epitaxial substrate 100. The inventors have made extensive investigations into the cause of the occurrence of the downfall defect region 7, and have come to the following findings.

[0114] Specifically, it was found that when a holder on which silicon carbide substrate 10 is placed is transported to high-temperature chamber 201, particles aligned in a direction perpendicular to the direction of transport of the holder fall onto silicon carbide substrate 10. When the inventors investigated the cause, it was found that a member (e.g., a heat insulating material or a heating element) inside chamber 201 has a shape having sides extending in a direction perpendicular to the direction of transport of the holder, and foreign matter (particles) attached to the sides of the member fall onto silicon carbide substrate 10, causing three or more downfall defects 6 aligned in a straight line. That is, due to particles aligned in a direction perpendicular to the direction of transport of the holder, a downfall defect region 7 including three or more downfall defects 6 aligned in a straight line was generated in silicon carbide epitaxial substrate 100 when viewed in a direction from silicon carbide epitaxial layer 20 toward silicon carbide substrate 10. Furthermore, downfall defect region 7 including three or more downfall defects 6 arranged in a straight line was effectively reduced by using the method for manufacturing silicon carbide epitaxial substrate 100 described above.

[0115] In the silicon carbide epitaxial substrate 100 according to this embodiment, the surface density of the downfall defects 6 is 0.2 cm -2 This makes it possible to reduce the surface density of downfall defects 6. EXAMPLES

[0116] (Sample preparation) First, silicon carbide epitaxial substrates 100 according to Samples 1 to 18 were prepared. The silicon carbide epitaxial substrates 100 according to Samples 1 to 18 had a diameter of 150 mm (6 inches). The silicon carbide epitaxial substrates 100 according to Samples 1 to 12 are comparative examples. In the manufacturing methods of the comparative examples, empty transport was not performed. The silicon carbide epitaxial substrates 100 according to Samples 13 to 18 are examples. In the manufacturing methods of the examples, empty transport was performed.

[0117] Specifically, in the method for manufacturing silicon carbide epitaxial substrate 100 according to Samples 1 to 12, the step (S10) of transporting a first holder to a chamber and the step (S20) of removing the first holder from the chamber were not performed. In the method for manufacturing silicon carbide epitaxial substrate 100 according to Samples 1 to 12, the step (S30) of transporting a second holder on which a silicon carbide substrate was placed to a chamber and the step (S40) of forming a silicon carbide epitaxial layer on the silicon carbide substrate were performed.

[0118] In the manufacturing method of silicon carbide epitaxial substrate 100 of samples 13 to 18, a step (S10) of transporting a first holder into a chamber, a step (S20) of removing the first holder from the chamber, a step (S30) of transporting a second holder on which a silicon carbide substrate is placed into the chamber, and a step (S40) of forming a silicon carbide epitaxial layer on the silicon carbide substrate were performed.

[0119] (Experimental Method) Next, the presence or absence of three or more downfall defects 6 arranged in a straight line was confirmed in the silicon carbide epitaxial substrates 100 of Samples 1 to 18 using a WASAVI series "SICA 6X" manufactured by Lasertec Corporation. Next, the number of downfall defects 6 was counted on the first main surface 1 excluding the peripheral region within 3 mm from the peripheral edge 5. The value obtained by dividing the number of downfall defects 6 by the area of ​​the measurement region of the downfall defects 6 was determined as the areal density of the downfall defects 6.

[0120] (Experimental Results)

[0121] [Table 1]

[0122] Table 1 shows the presence or absence of three or more downfall defects 6 arranged in a straight line, and the surface density of the downfall defects 6. In Table 1, when the number of downfall defects 6 arranged in a straight line is 10 or more, it is recorded as "present (large)". When the number of downfall defects 6 arranged in a straight line is 3 or more and less than 10, it is recorded as "present (small)". When the number of downfall defects 6 arranged in a straight line is less than 3, it is recorded as "absent".

[0123] Fig. 15 is a schematic plan view showing a state in which a large number of downfall defects are arranged in a straight line. As shown in Fig. 15, a large number (e.g., 10 or more) of downfall defects 6 are arranged in a fourth direction 104. The first length A1 is, for example, 20 mm or more and 200 mm or less. The second length A2 is, for example, 5 mm or more and 50 mm or less. In the silicon carbide epitaxial substrates 100 according to samples 7 to 12, a large number of downfall defects are arranged in a straight line.

[0124] As shown in Table 1, the surface density of downfall defects 6 in the silicon carbide epitaxial substrates 100 of Samples 1 to 12 was 0.26 cm -2 More than 6.28cm -2 On the other hand, the surface density of downfall defects 6 in silicon carbide epitaxial substrates 100 of samples 13 to 18 was 0.03 cm -2 More than 0.15cm -2 Furthermore, in the silicon carbide epitaxial substrates 100 of Samples 13, 15, 17 and 18, downfall defects 6 of three or more arranged in a straight line were not observed.

[0125] From the above results, it was confirmed that by performing empty transportation, it is possible to reduce the number of downfall defects 6 arranged in a straight line and to reduce the surface density of the downfall defects 6.

[0126] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered as limiting. The scope of the present invention is defined by the claims rather than the above-described embodiments and examples, and is intended to include all modifications within the scope of the claims and meanings equivalent thereto. [Explanation of symbols]

[0127] 1 First main surface 2 Second main surface 3. Orientation Flat 4 Arc-shaped section 5 Outer rim 6. Downfall Defects 7 Downfall defect area 8 Recess 10 Silicon carbide substrate 11 Buffer layer 13 Drift layer 15 First aspect 16 Second aspect 20 Silicon carbide epitaxial layer 31 First Holder 32 Second Holder 33,34 Board placement section 100 Silicon carbide epitaxial substrate 101 1st direction 102 Second direction 103 Third direction 104 4th direction 105 5th direction 106 Trench 113 Body Region 114 Source Region 115 Gate insulating film 116 Source electrode (electrode) 117 Mask 118 Contact Area 119 Source wiring 120 Drain electrode 123 Side 124 Bottom 126 Interlayer insulating film 127 Gate electrode 200 Manufacturing equipment 201 Chamber 203 Heating element 205 Inner wall surface 206 Stages 207 Gas inlet 208 Gas exhaust port 209 Rotational Axis 231 First Gas Supply Unit 232 Second Gas Supply Unit 233 Third Gas Supply Section 234 Carrier gas supply unit 235 Gas Supply Section 241 First gas flow control section 242 Second gas flow rate control section 243 Third gas flow control section 244 Carrier gas flow control section 245 Control Unit 300 Silicon carbide semiconductor device A1 First length A2 Second length B1 Transport direction B2 Export direction D Maximum width W Maximum diameter

Claims

1. a silicon carbide substrate; a silicon carbide epitaxial layer on the silicon carbide substrate; a downfall defect region on the silicon carbide substrate; the downfall defect region includes three or more downfall defects arranged in a straight line when viewed in a direction from the silicon carbide epitaxial layer toward the silicon carbide substrate, The areal density of the downfall defects is 0.2 cm －２ The silicon carbide epitaxial substrate is as follows:

2. 2 . The silicon carbide epitaxial substrate according to claim 1 , wherein a longitudinal length of the downfall defect region is 20 mm or more and 200 mm or less as viewed in a direction from the silicon carbide epitaxial layer toward the silicon carbide substrate.

3. 3. The silicon carbide epitaxial substrate according to claim 1, wherein a length of the downfall defect region in a short side direction as viewed in a direction from the silicon carbide epitaxial layer toward the silicon carbide substrate is 5 mm or more and 50 mm or less.

4. The areal density of the downfall defects is 0.1 cm －２ 3. The silicon carbide epitaxial substrate according to claim 1, wherein:

5. a silicon carbide substrate; a silicon carbide epitaxial layer on the silicon carbide substrate; a downfall defect on the silicon carbide substrate; The areal density of the downfall defects is 0.2 cm －２ The silicon carbide epitaxial substrate is as follows:

6. The areal density of the downfall defects is 0.1 cm －２ 6. The silicon carbide epitaxial substrate according to claim 5, wherein:

7. The silicon carbide epitaxial substrate according to claim 1 , wherein the downfall defects are exposed from the silicon carbide epitaxial layer.

8. A step of preparing a silicon carbide epitaxial substrate according to any one of claims 1 to 6; and forming an electrode on the silicon carbide epitaxial substrate.

9. transporting the first holder to a chamber at 300° C. or higher; removing the first holder from the chamber without forming a silicon carbide epitaxial layer on the first holder; transporting a second holder on which the silicon carbide substrate is placed to the chamber at a temperature of 300° C. or higher; forming a silicon carbide epitaxial layer on the silicon carbide substrate in the chamber.

10. 10. The method for producing a silicon carbide epitaxial substrate according to claim 9, wherein in the step of transporting the first holder to a chamber at 300° C. or higher, the temperature of the chamber is 1000° C. or lower.

11. 11. The method for manufacturing a silicon carbide epitaxial substrate according to claim 9, wherein in the step of transporting the first holder to a chamber at 300°C or higher, the temperature of the chamber is 600°C or higher.

12. in a step of transporting the second holder on which the silicon carbide substrate is placed to the chamber at 300° C. or higher, three or more particles present inside the chamber fall onto the silicon carbide substrate, the three or more particles are aligned on the silicon carbide substrate in a direction perpendicular to a transport direction of the second holder, The surface density of the three or more particles is 0.2 cm －２ 11. The method for producing a silicon carbide epitaxial substrate according to claim 9 or 10, wherein:

13. 11. The method of claim 9 or 10, wherein the first holder is different from the second holder.

14. 11. The method for manufacturing a silicon carbide epitaxial substrate according to claim 9 or 10, wherein the first holder is the same as the second holder.

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