Semiconductor device manufacturing method

Abstract

To provide a method for manufacturing a semiconductor device capable of improving the sensitivity of visual inspection.SOLUTION: A resist film formed on a surface electrode 14 is exposed to light and developed to form a fine resist pattern 34. At this time, light exposure focus is matched to the surface of the resist film on a normal portion of the surface electrode 14, thereby generating pattern defect portions 34c, 34d of the resist pattern 34 on a convex defect portion 2 and a concave defect portion 3 of the surface electrode 14. The pattern defect portions 34c, 34d of the resist pattern 34 are detected based on the intensity ratio of reflected light of light with which a semiconductor wafer 10 is irradiated, or by comparing images of adjacent chip regions of the semiconductor wafer 10 that are captured using an inspection unit, and the detected positions are set as detected positions of the convex defect portion 2 and the concave defect portion 3. By setting the focal position of the irradiated light or inspection unit to the surface of the resist pattern 34, grain boundaries of the surface electrode 14 are not erroneously detected.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] This disclosure relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, there has been known an inspection method for detecting foreign matter on the surface of a semiconductor wafer based on the intensity ratio of scattered light reflected by irradiating a semiconductor wafer with laser light (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 9-115973 Summary of the Invention [Problem to be solved by the invention]

[0004] If foreign matter adheres to the surface of a semiconductor wafer during the formation of the surface electrode, defects due to the foreign matter will occur on the surface of the surface electrode. With conventional inspection methods, automatic appearance inspection using an appearance inspection device will erroneously detect the grain boundaries of the surface electrode as similar defects to other defects, which will require on-site operators to subsequently perform visual inspection and reevaluate the defects, resulting in reduced throughput.

[0005] An object of the present disclosure is to provide a method for manufacturing a semiconductor device that can improve the sensitivity of visual inspection. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the disclosure is as follows: A first step is performed in which a surface electrode is formed on a surface of a semiconductor wafer; A second step is performed in which a resist film is formed on the surface electrode; A third step is performed in which the resist film is exposed and developed to form a predetermined resist pattern; A fourth step is performed in which a surface defect occurring in the surface electrode during the first step is detected based on an intensity ratio of reflected light of light irradiated onto the semiconductor wafer, or by photographing the surface of the semiconductor wafer on the surface electrode side using an imaging means and comparing the images. In the third step, a pattern defect is generated in a portion of the resist pattern above the surface defect. In the fourth step, the surface of the resist pattern is used as the focal position of the irradiated light or the imaging means to detect the pattern defect, and the detection position of the pattern defect is set as the detection position of the surface defect. Effect of the Invention

[0007] The method for manufacturing a semiconductor device according to the present disclosure has the effect of improving the sensitivity of visual inspection. [Brief description of the drawings]

[0008] [Figure 1] 1 is a flowchart showing an outline of a manufacturing method of a semiconductor device according to an embodiment; [Diagram 2] FIG. 2 is a plan view showing a semiconductor wafer as viewed from the front surface side. [Diagram 3] 1A to 1C are cross-sectional views showing a state during the manufacture of a semiconductor device according to an embodiment (part 1). [Figure 4] 4 is a cross-sectional view (part 2) showing a state during the manufacture of the semiconductor device according to the embodiment. FIG. [Diagram 5] 4A to 4C are cross-sectional views (part 3) illustrating a state during the manufacture of the semiconductor device according to the embodiment. [Figure 6] 4 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the embodiment (part 4). FIG. [Figure 7] 5 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to an embodiment (part 5). FIG. [Figure 8] 6 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to an embodiment; FIG. [Figure 9] FIG. 2 is a plan view showing an example of a resist pattern in step S6 of FIG. [Figure 10] FIG. 2 is a plan view showing an example of a resist pattern in step S6 of FIG. [Figure 11] FIG. 2 is a plan view showing an example of a resist pattern in step S6 of FIG. [Figure 12] FIG. 2 is a plan view showing an example of a resist pattern in step S6 of FIG. [Figure 13] FIG. 7 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to an embodiment; [Figure 14] 11A and 11B are cross-sectional views showing a state during the manufacture of a semiconductor device according to a reference example. [Figure 15] 1 is a cross-sectional view showing a structural example of a semiconductor device manufactured by applying a manufacturing method for a semiconductor device according to an embodiment; [Figure 16] 1A to 1C are cross-sectional views (part 1) illustrating schematic diagrams of a semiconductor device according to a reference example during manufacturing. [Figure 17] 13A to 13C are cross-sectional views (part 2) illustrating schematic diagrams of a semiconductor device according to a reference example during manufacturing. [Figure 18] 11A to 11C are cross-sectional views (part 3) illustrating schematic diagrams of a semiconductor device according to a reference example during manufacturing. [Figure 19] 4 is a cross-sectional view (part 4) illustrating a schematic state during the manufacture of a semiconductor device according to a reference example. FIG. [Figure 20] 1A and 1B are explanatory diagrams illustrating the state of a convex defect in a surface electrode during inspection. [Figure 21] FIG. 11 is an explanatory diagram illustrating a schematic state of grain boundaries of a surface electrode during inspection. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] <Overview of the embodiment of the present disclosure> (1) A method for manufacturing a semiconductor device according to one embodiment of the present disclosure is as follows: A first step is performed in which a surface electrode is formed on a surface of a semiconductor wafer; A second step is performed in which a resist film is formed on the surface electrode; A third step is performed in which the resist film is exposed and developed to form a predetermined resist pattern; A fourth step is performed in which a surface defect occurring in the surface electrode during the first step is detected based on an intensity ratio of reflected light of light irradiated onto the semiconductor wafer, or by photographing the surface of the semiconductor wafer on the surface electrode side using an imaging means and comparing the images. In the third step, a pattern defect is generated in a portion of the resist pattern above the surface defect. In the fourth step, the surface of the resist pattern is used as the focal position of the irradiated light or the imaging means to detect the pattern defect, and the detection position of the pattern defect is set as the detection position of the surface defect.

[0010] According to the disclosure above, in the fourth step, the focal point of the illumination light or the imaging means of the visual inspection device does not coincide with the grain boundaries of the surface electrodes, so that the visual inspection device does not erroneously detect the grain boundaries of the surface electrodes. Since there is no need for the on-site operator to reevaluate the defects detected by the visual inspection device, the man-hours required for the on-site operator to visually reevaluate the defects can be reduced.

[0011] (2) Furthermore, in the manufacturing method of a semiconductor device according to the present disclosure, in the above-mentioned (1), in the third step, a pattern defect portion is generated in a portion of the resist pattern above the surface defect, the pattern defect portion being formed by resist remaining with a width wider than a remaining width of resist on a normal portion of the front surface electrode where the surface defect is not present, or the pattern defect portion is formed by resist being removed with a width wider than a width of a hole in the resist on the normal portion of the front surface electrode.

[0012] According to the above disclosure, by automatically detecting pattern defects in the resist pattern by the appearance inspection device in the fourth process, it is possible to detect all surface defects in the front surface electrodes.

[0013] (3) Furthermore, in the method for manufacturing a semiconductor device according to the present disclosure, in the above-mentioned (2), the remaining width of the resist of the resist pattern may be narrower than the width of the surface defect, and the width of the hole in the resist of the resist pattern may be narrower than the width of the surface defect.

[0014] According to the above disclosure, in the fourth process, the appearance inspection device can accurately detect two types of pattern defects in the resist pattern (pattern defects due to exposure focus errors and pattern defects due to resist defects).

[0015] (4) Furthermore, in the method for manufacturing a semiconductor device according to the present disclosure, in the above-mentioned (2), the remaining width of the resist of the resist pattern may be less than or equal to 1 / 4 of the width of the surface defect, and the width of the hole in the resist of the resist pattern may be less than or equal to 1 / 4 of the width of the surface defect.

[0016] According to the above disclosure, in the fourth process, both types of pattern defects in the resist pattern can be detected with high accuracy by the appearance inspection device.

[0017] (5) In the method for manufacturing a semiconductor device according to the present disclosure, in any one of (1) to (4) described above, the resist pattern formed in the third step may have regularity.

[0018] According to the above disclosure, pattern defects in the resist pattern can be easily detected by the appearance inspection device in the fourth process.

[0019] (6) Furthermore, in the method for manufacturing a semiconductor device according to the present disclosure, in any one of (1) to (5) described above, in the third step, the resist pattern may be formed such that the remaining area of ​​the resist is equal to the area of ​​the holes in the resist.

[0020] According to the above disclosure, in the fourth process, both types of pattern defects in the resist pattern can be detected with high accuracy by the appearance inspection device.

[0021] (7) In the method for manufacturing a semiconductor device according to the present disclosure, in any one of the above-mentioned (1) to (6), the surface defect is a convex defect formed by a part of the surface of the front electrode being raised, or a concave defect formed by a part of the surface of the front electrode being concave, or both. In the third step, the resist pattern may be formed by setting the surface of the resist film on a normal portion of the front electrode where the surface defect is not generated as a focal position of the exposure light, and exposing the resist film to light of a short wavelength that is not focused on the surface of the resist film on the surface defect.

[0022] According to the above disclosure, both convex and concave defects on the surface of a surface electrode can be detected.

[0023] (8) In the method for manufacturing a semiconductor device according to the present disclosure, in the above-mentioned (7), the first step may include a film forming step of forming the front electrode by sputtering, and an etching step of patterning the front electrode by photolithography and etching. In this case, the convex defect occurs when a foreign matter is taken into the front electrode during the film forming step. The concave defect occurs when the front electrode is selectively removed at a resist defect portion of a resist mask used in the etching step.

[0024] According to the above disclosure, both convex defects and concave defects occurring on the surface of the front surface electrode in the first process can be detected.

[0025] (9) Furthermore, in the manufacturing method of a semiconductor device according to the present disclosure, in any one of (1) to (8) above, in the third step, the resist pattern may be formed for each chip region regularly arranged on the semiconductor wafer, and in the fourth step, the surface of the semiconductor wafer on the surface electrode side may be photographed using the photographing means, and adjacent chip regions of the semiconductor wafer may be compared in image.

[0026] According to the above disclosure, a resist defect portion in a resist pattern can be detected without preparing a comparison image in advance.

[0027] <Foundational knowledge of this disclosure> First, a method for manufacturing a semiconductor device according to a reference example will be described. FIGS. 16 to 19 are cross-sectional views that typically show the state of a semiconductor device according to a reference example during manufacturing. FIGS. 20 and 21 are explanatory views that typically show the state of a protruding defect and a grain boundary of a surface electrode during inspection. In FIGS. 20 and 21, a cross-sectional view is shown at the bottom of inspection points 131 and 132, an inspection image (plan view) by a visual inspection device is shown at the top left, and a microscopic image (plan view) by a visual inspection by an on-site operator is shown at the top right. For example, after a contact plug 113 is embedded in a contact hole 111a of an interlayer insulating film 111 via a barrier metal 112 and the metal film that becomes the contact plug 113 is etched back, a foreign substance 101 adheres to the front surface of a semiconductor wafer 110 (FIG. 16).

[0028] When a surface electrode 114 is formed by sputtering with a foreign substance 101 attached to the front surface of a semiconductor wafer 110, the foreign substance 101 is taken into the surface electrode 114. The surface of the surface electrode 114 is raised by the foreign substance 101 having a relatively large size, and a convex defect 102 is generated on the surface of the surface electrode 114 (FIG. 17). When the coverage of the surface electrode 114 is deteriorated by the foreign substance 101, a crack (metal defect) 114a is generated near the convex defect 102 on the surface of the surface electrode 114. In addition, if the resist film used as a mask in the subsequent patterning of the surface electrode 114 is interrupted (stepped) by the convex defect 102, the convex defect 102 exposed in the resist defect is etched, and a concave defect (metal defect) 103 penetrating the surface electrode 114 in the depth direction is generated (FIG. 19).

[0029] Even in the case of a resist defect 121a (FIG. 18) that occurs in the resist film 121 used as a mask during patterning of the surface electrode 114 due to a factor other than the bump defect 102, the surface electrode 114 is selectively etched and a concave defect 103 occurs (FIG. 19). The bump defect 102 completely covered with the resist film remains as it is (lower diagram in FIG. 20). If a metal defect (crack 114a or concave defect 103) occurs in the surface electrode 114, plating solution will seep into the lower layer during plating treatment of the surface of the surface electrode 114, causing electrical characteristic defects (assembly defects). For this reason, after patterning of the surface electrode 114 and before annealing of the surface electrode 114, an automatic appearance inspection is performed using an appearance inspection device to screen (sort) defects that occurred after the film formation of the surface electrode 114.

[0030] The grain size of the crystal grain boundary (grain) 114b generated during the deposition of the surface electrode 114 is very small compared to the width and height of the bump defect 102 and the concave defect 103 (the crystal grain boundary 114b is shown larger in FIGS. 14 and 21 for the purpose of explanation). However, in a location where a plurality of crystal grain boundaries 114b are adjacent and densely packed, the crystal grain boundary 114b may be erroneously detected as a pseudo defect of the bump defect 102 (hatched portion in FIG. 20) in the visual inspection device because the inspection image of the crystal grain boundary 114b (upper left diagram in FIG. 21) resembles the inspection image of the bump defect 102 (upper left diagram in FIG. 20). Because of the risk of such erroneous detection by the visual inspection device, after the inspection by the visual inspection device, the defects detected by the visual inspection device must be reevaluated by visual inspection (visual inspection) by an on-site operator. This deteriorates the throughput.

[0031] The false defects are re-evaluated by the visual inspection of the on-site operator and judged to be good (the microscope images by the on-site operator are shown in the upper right of Figs. 20 and 21). Therefore, the more the number of false detections of similar defects by the visual inspection device increases, the more man-hours it takes for the on-site operator to re-evaluate by visual inspection. The number of false detections of the grain boundaries 114b by the visual inspection device can be reduced by changing the deposition conditions of the surface electrode 114 to reduce the grain boundaries 114b or by using a high-brightness light source to increase the contrast of the inspection image of the visual inspection device. However, there is a risk that the deposition speed of the surface electrode 114 will slow down, reducing the production capacity of semiconductor chips, or that halation will reduce the detection sensitivity of the visual inspection device. Problems to be solved in this embodiment include improving the sensitivity of the visual inspection and improving the throughput.

[0032] A preferred embodiment of the method for manufacturing a semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with that. In the following description of the embodiment and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted.

[0033] (Details of the embodiment) The following describes a method for manufacturing a semiconductor device according to an embodiment that solves the above-mentioned problems. FIG. 1 is a flow chart showing an outline of a method for manufacturing a semiconductor device according to an embodiment. FIG. 2 is a plan view showing a state in which a semiconductor wafer is viewed from the front surface side. FIGS. 3 to 8 and 13 are cross-sectional views showing a state during the manufacturing of a semiconductor device according to an embodiment. FIGS. 9 to 12 are plan views showing examples of resist patterns in step S6 in FIG. 1. FIGS. 3 to 6 show a defect generation mechanism during the processing of steps S4 and S5 in FIG. 1. FIGS. 7 and 8 show a state during the processing of step S6 in FIG. 1, and FIG. 13 shows a state during the processing of step S7 in FIG. In FIG. 13, crystal grain boundaries 14b are illustrated larger than they actually are and typically shown with respect to resist pattern 34. FIG. 14 is a cross-sectional view showing a state during the manufacturing of a semiconductor device of a reference example.

[0034] First, as shown in Figures 2 and 3, a predetermined element structure 20 is formed in each chip region 21 on the front surface side of the semiconductor wafer 10 (step S1). Next, an interlayer insulating film 11 is formed over the entire front surface of the semiconductor wafer 10, and contact holes 11a are formed penetrating the interlayer insulating film 11 in the depth direction. In the contact holes 11a, contacts (electrical contact parts) between the element structure 20 and a surface electrode 14 described later are formed. The element structure 20 will be described later (see Figure 15), but for example, if the element structure 20 has a structure with a narrow cell pitch for miniaturization or low on-resistance, the width of the contact hole 11a will be narrow, and therefore the fillability of the contact hole 11a is improved by a contact plug 13 described later.

[0035] The size of the semiconductor wafer 10 can be set appropriately, and may be, for example, 8 inches in diameter. The material of the semiconductor wafer 10 may be silicon (Si) or silicon carbide (SiC). The chip regions 21 are regions that are cut from the semiconductor wafer 10 along dicing lines 22 and separated into semiconductor chips 40. The dicing lines 22 extend in a lattice shape surrounding the chip regions 21 that are arranged adjacent to each other in a matrix shape. The area between the end of the semiconductor wafer 10 (wafer end) and the dicing line 22 closest to the wafer end may be an invalid area 23 that is not used as a semiconductor chip 40. The semiconductor wafer 10 may have an orientation flat 24 or a notch (not shown) that indicates a surface orientation.

[0036] Next, a barrier metal 12 is formed along the surface of the interlayer insulating film 11 and the inner wall of the contact hole 11a by a sputtering method. The barrier metal 12 is formed by laminating, for example, a titanium (Ti) film and a titanium nitride (TiN) film in this order. Next, a conductive film such as a tungsten (W) film is deposited (formed) on the barrier metal 12 by a chemical vapor deposition (CVD) method so as to fill the contact hole 11a. Next, the tungsten film is etched back to leave a portion that will become the contact plug 13 only inside the contact hole 11a (step S2).

[0037] Next, a visual inspection of the semiconductor wafer 10 is performed using a general visual inspection device (not shown) (step S3). In the inspection of step S3, the embeddability of the contact plugs 13 is confirmed. As a method for confirming the embeddability of the contact plugs 13, for example, the flatness of the front surface (surfaces of the interlayer insulating film 11 and the contact plugs 13) of the semiconductor wafer 10 may be confirmed, or it may be confirmed that no cavities are present inside the contact plugs 13, or that any cavities present inside the contact plugs 13 are small enough not to adversely affect the electrical characteristics. Position information of chip regions 21 determined to be defective in the inspection of step S3 is stored in a predetermined storage medium.

[0038] Next, as shown in FIG. 4, a surface electrode 14 is formed on the interlayer insulating film 11 and the contact plug 13 by sputtering (step S4: first step (film formation step)). The surface electrode 14 is, for example, an Al alloy film such as Al-Si (aluminum silicon) or Al-Si-Cu (aluminum silicon copper). The thickness t1 of the surface electrode 14 is, for example, about 5 μm. For example, the foreign matter 1 (see FIG. 3) attached to the front surface (surface of the interlayer insulating film 11 and the contact plug 13) of the semiconductor wafer 10 by the etch-back or the like in step S2 is taken into the surface electrode 14 during the processing in step S4. Here, a case is shown in which foreign matters 1 (1a, 1b, 1c) of different heights are attached to the semiconductor wafer 10.

[0039] The foreign matter 1a and 1b causes the surface of the surface electrode 14 to rise, and a convex defect 2 (a convex surface defect) is generated on the surface of the surface electrode 14. The foreign matter 1a is relatively large, with a height h1 equal to or greater than the thickness t1 of the surface electrode 14, and a width w1 of, for example, about 7 μm or more. This relatively large foreign matter 1a and foreign matter 1b, which has a height less than the thickness t1 of the surface electrode 14 but is relatively close to the thickness t1 of the surface electrode 14, are the cause of the convex defect 2. Depending on the height h1 of the foreign matter 1a, the coverage of the surface electrode 14 deteriorates, and a crack (corresponding to the crack 114a in FIG. 17) is generated near the convex defect 2 on the surface of the surface electrode 14. Depending on its shape, the relatively small foreign matter 1c may be buried in the surface electrode 14 and may not generate the convex defect 2.

[0040] Next, the surface electrode 14 is patterned by photolithography and etching (step S5: first step (etching step)). In step S5, as shown in FIG. 5, a resist film (resist mask) 31 is formed on the surface electrode 14 to cover the active region of each chip region 21. The edge termination region and the dicing line 22 are exposed in the openings (not shown) of the resist film 31. Then, the surface electrode 14 is selectively removed by etching using the resist film 31 as a mask, and is left in a predetermined pattern in the active region of each chip region 21. The active region is a region through which a main current flows in an on-state. The edge termination region is a region between the active region and the side of the semiconductor chip 40 (see FIG. 15), and surrounds the periphery of the active region. Then, as shown in FIG. 6, the resist film 31 is removed.

[0041] If the resist film 31 is interrupted (disconnected) by the bump defect 2 during the processing of step S5, the bump defect 2 (foreign matter 1a and the surface electrode 14 therearound) exposed in the resist defect 31a of the resist film 31 is etched, and a concave defect (metal defect) 3 is generated in which the surface of the surface electrode 14 is recessed (FIG. 6). The surface electrode 14 is selectively etched and a concave defect 3 (concave surface defect) is generated in the resist defect (corresponding to the resist defect 121a in FIG. 18) generated in the resist film 31 due to factors other than the bump defect 2 (for example, thickness variation of the resist film 31). The concave defect 3 penetrates the surface electrode 14 in the depth direction, for example. The bump defect 2 (bump defect 2 due to the foreign matter 1b) completely covered with the resist film 31 remains on the surface of the surface electrode 14 in this state even after the processing of step S5 (FIG. 6).

[0042] It is estimated that the number of bump defects 2 remaining after the processing of step S5 is approximately the same as the number of concave defects 3 generated by the processing of step S5. The bump defects 2 remaining after the processing of step S5 are raised from the surface of the normal part of the front surface electrode 14 (the substantially flat part where neither bump defects 2 nor concave defects 3 are generated) by a height h2 of, for example, about 3 μm to 5 μm. The width w2 of the bump defects 2 remaining after the processing of step S5 is, for example, about 11 μm or more. The depth h3 of the concave defects 3 is approximately the same as the thickness t1 of the front surface electrode 14. The width w3 of the concave defects 3 is, for example, about 21 μm or more. The step due to the unevenness of the surface of the front surface electrode 14 caused by the manufacturing variation due to sputtering is approximately ±0.05 μm to 0.5 μm, which is smaller than the height h2 of the bump defects 2 and the depth h3 of the concave defects 3. The grain size of the crystal grain boundary 14b of the surface electrode 14 is very small compared with the width w2 and height h2 of the bump defect 2 and the width w3 and depth h3 of the concave defect 3 of the surface electrode 14 (the crystal grain boundary 14b is shown larger in Figures 7, 8 and 13 for the purpose of explanation).

[0043] Next, as shown in FIG. 7, a resist film 32 (hatched portion) is formed on the surface of the front electrode 14 (second step). The resist film 32 is formed along the surface of the normal portion of the front electrode 14 (left diagram in FIG. 7), the surface of the bump defect 2 (center diagram in FIG. 7), and the inner wall of the concave defect 3 (right diagram in FIG. 7). Next, a predetermined mask pattern is transferred (exposed) to the resist film 32 using a general exposure device. At this time, the exposure focus (focus of light 33 from the light source of the exposure device) 33a is aligned with the surface (focus position (imaging plane)) of the resist film 32 on the normal portion of the front electrode 14. In FIG. 7, the light 33 from the light source of the exposure device is indicated by a diagonal dashed arrow, and the position of the exposure focus 33a is indicated by a horizontal dashed line passing through the intersection of the light 33. Then, as shown in FIG. 8, the exposed portions of the resist film 32 are dissolved and removed (developed) with a chemical solution to form resist patterns 34 (hatched portions) on the surface electrodes 14 of each chip region 21 of the semiconductor wafer 10 (third process) (step S6).

[0044] In step S6, the resist film 32 is exposed to light using a light source that emits light 33 with a short wavelength (small focal depth), such as i-line (light with a wavelength of 365 nm) or KrF-line (krypton fluoride excimer laser light with a wavelength of 248 nm). This allows the formation of a fine resist pattern 34 in which the widths w12 and w11 of the resist remaining (exposed and unexposed portions) are narrower than the narrower of the width w2 of the convex defect 2 and the width w3 of the concave defect 3 of the surface electrode 14. The resist pattern 34 can be set as appropriate, but it is preferable that it has regularity. Specifically, the resist pattern 34 may be, for example, a stripe-shaped (FIG. 9) or lattice-shaped (FIG. 10) pattern in which the widths w12 and w11 of the resist remaining are substantially uniform, or a lattice-shaped or mesh-shaped (stepped lattice-shaped: FIG. 11) pattern surrounding the periphery of rectangular (FIG. 11) or circular (pinhole-shaped: FIG. 12) holes 34a arranged in a matrix.

[0045] By forming the resist pattern 34 as a regular pattern, pattern missing parts 34c and 34d of the resist pattern 34 can be easily detected in the process of step S7 described later, improving the throughput of the inspection. By adjusting the exposure focus 33a to the surface of the resist film 32 on the normal part of the front surface electrode 14, the resist film 32 is normally exposed on the normal part of the front surface electrode 14. Therefore, the part of the resist pattern 34 on the normal part of the front surface electrode 14 becomes a pattern normal part 34b in which the resist is left unremoved alternately at predetermined widths w12 and w11 in the same pattern as the mask pattern transferred to the resist film 32 (left diagram of FIG. 8). On the other hand, on the convex defect 2 and the concave defect 3 of the front surface electrode 14, the surface of the resist film 32 is located outside the focal depth of the light 33 of the light source of the exposure device. Therefore, the portion of the resist pattern 34 above the bump defect 2 and the portion above the divot defect 3 become pattern missing portions 34c in which the resist remains with a width greater than the remaining width w11 of the pattern normal portion 34b (upper central and right diagrams in FIG. 8).

[0046] That is, by using a light source that emits light 33 with a shallow focal depth (for example, the focal depth of i-line is about 500 nm) for exposing the resist film 32, the exposure focus 33a is almost not aligned with the surface of the resist film 32 on the bump defect 2 and the concave defect 3 of the front electrode 14 (center and right diagrams of FIG. 7), and the resist film 32 is not exposed. The part of the resist film 32 that is not exposed becomes the pattern missing part 34c. Therefore, the light 33 of the light source of the exposure device used for exposing the resist film 32 may be light whose focal depth is 1 / 2 shallower than the height h2 of the bump defect 2 and whose focal depth is 1 / 2 shallower than the depth h3 of the concave defect 3. In this way, by intentionally causing an error in the exposure focus 33a when exposing the resist film 32, the part of the resist pattern 34 on the bump defect 2 and the part on the concave defect 3 can be made into the pattern missing part 34c. By detecting pattern missing portion 34c of resist pattern 34 in the process of step S7 described later, all bump defects 2 and pit defects 3 of front surface electrode 14 can be automatically detected by the appearance inspection device.

[0047] The total width (=2×(w11+w12)) of at least two of the unit patterns (a pair of adjacent patterns of the resist remaining) of the resist pattern 34 should be equal to or less than the width of the surface defect (the narrower of the width w2 of the bump defect 2 and the width w3 of the concave defect 3). That is, the total width (=w11+w12) of the remaining resist width w11 of the pattern normal portion 34b of the resist pattern 34 and the width w12 of the hole in the resist should be equal to or less than 1 / 2 the width of the surface defect. This makes it easier to distinguish the pattern normal portion 34b and the pattern missing portion 34c of the resist pattern 34 in the process of step S7 described later. The portion of the resist pattern 34 on the bump defect 2 with a relatively high height h2 is not the pattern missing portion 34c, but the pattern missing portion 34d caused by the absence of the resist film 32 on the bump defect 2 (missing resist) (lower central view of FIG. 8). The width of this pattern defect portion 34d is wider than the width w12 of the resist hole in the pattern normal portion 34b.

[0048] The total width of the resist remaining width w11 of the resist pattern 34 and the resist hole width w12 is preferably about 5.5 μm or less. The numerical range (11 μm / 2=5.5 μm) of these total widths (=w11+w12) is calculated on the assumption that the total width of at least two unit patterns of the resist remaining in the resist pattern 34 should be equal to or less than the width of the defect to be detected (here, the width w2 of the bump defect 2) as described above. By appropriately adjusting the resist remaining width w11 of the resist pattern 34 and the resist hole width w12 within a range of, for example, 2.75 mm or less and making the resist remaining area equal to the area of ​​the resist hole, even if the resist remaining width w11 of the resist pattern 34 and the resist hole width w12 are not equal, both of the two types of pattern missing parts 34c and 34d of the resist pattern 34 can be detected with high accuracy in the process of step S7 described later.

[0049] The thickness t11 of the resist pattern 34 (the thickness of the resist film 32) is preferably, for example, 1 μm or more and 2.75 μm or less. The reason why the thickness t11 of the resist pattern 34 is set to the above lower limit or more is that if the thickness t11 of the resist pattern 34 is too thin, there is a risk that the irradiation light of the appearance inspection device or the focus 35 of the inspection unit cannot be aligned with the surface of the resist pattern 34 in the inspection of step S7 described later. The reason why the thickness t11 of the resist pattern 34 is set to the above upper limit or less is that by reducing the aspect ratio of both the removed and left resist (=thickness t11 of the resist pattern 34 / left resist width w11, or =thickness t11 of the resist pattern 34 / width w12 of the hole in the resist) (for example, 1 or more), it becomes easier to form a fine resist pattern 34.

[0050] Next, a general appearance inspection device (not shown) is used to perform an appearance inspection of the semiconductor wafer 10 (step S7: fourth process). In the inspection of step S7, the appearance inspection device detects bump defects 2 and divot defects 3 in the front surface electrodes 14 of all chip regions 21 of the semiconductor wafer 10. Specifically, first, the pattern missing parts 34c, 34d of the resist pattern 34 are detected. For example, there is a method of detecting the pattern missing parts 34c, 34d of the resist pattern 34 by a program prepared in advance in the appearance inspection device based on the intensity ratio of scattered light reflected by irradiating light on the front surface of the semiconductor wafer 10 from a predetermined light source mounted in the appearance inspection device.

[0051] As another example, there is a method in which each chip region 21 on the semiconductor wafer 10 is photographed by an inspection unit, and the images of the resist patterns 34 in adjacent chip regions 21 are compared using a program prepared in advance in the appearance inspection device, thereby detecting pattern missing portions 34c, 34d of the resist pattern 34. The image of the resist pattern 34 photographed by the inspection unit may be compared with a comparison image registered in advance in the appearance inspection device. The inspection unit is a mechanism equipped with a photographing means such as a camera, and is mounted on the appearance inspection device. In addition to the photographing means, the inspection unit may also be equipped with a microscope, lighting, a monitor, various sensors, etc.

[0052] As described above, pattern defects 34c, 34d of resist pattern 34 occur on bump defect 2 and dip defect 3 of front surface electrode 14, and therefore the detection positions of pattern defects 34c, 34d by the visual inspection device can be set as the detection positions of bump defect 2 and dip defect 3. At this time, as shown in Fig. 13, by adjusting the focus (focal point) 35 of the irradiation light or inspection unit of the visual inspection device to the surface (focal position (imaging plane)) of resist pattern 34, the focus 35 does not match grain boundary 14b of front surface electrode 14, and therefore grain boundary 14b is not erroneously detected even in a place where a plurality of grain boundaries 14b are adjacent and densely packed.

[0053] In the manufacturing method of the semiconductor device of the reference example described above, as shown in FIG. 14, the irradiation light of the visual inspection device or the focus 135 of the inspection unit is aligned with the surface of the surface electrode 114, and the grain boundary 114b of the surface electrode 114 is erroneously detected as a defect similar to the bump defect 102 (see FIGS. 20 and 21). Therefore, the grain boundary 114b erroneously detected by the visual inspection device needs to be reevaluated as a good defect by visual inspection by an on-site operator. On the other hand, in the embodiment, the grain boundary 14b is not erroneously detected in the inspection of step S7, so that reevaluation by visual inspection by an on-site operator in the inspection of step S7 is not required. Therefore, the man-hours of reevaluation by visual inspection by an on-site operator can be reduced in the entire manufacturing flow. The position information of the chip region 21 in which the bump defect 2 or the divot defect 3, or both, are detected in the inspection of step S7 is stored in a predetermined storage medium.

[0054] Next, annealing (heat treatment) is performed for sintering the surface electrodes 14 (step S8). In the process of step S8, an ohmic contact may be formed between the barrier metal 12 and the semiconductor wafer 10. Next, a surface protective film (passivation film: not shown) made of, for example, polyimide is formed on the front surface (surface of the surface electrodes 14) of the semiconductor wafer 10 (step S9). Next, the surface protective film is opened by photolithography and etching, and the surface electrodes 14 of each chip region 21 are exposed in each opening of the surface protective film. The portions of the surface electrodes 14 exposed in the openings of the surface protective film become electrode pads. Next, each portion on the back side of the semiconductor wafer 10 is formed by a general method (step S10).

[0055] In the process of step S10, for example, the semiconductor wafer 10 is ground from the back surface side to a product thickness to be used as the semiconductor device 50 (see FIG. 15). Next, a predetermined diffusion region (n in FIG. 15) is formed by ion implantation in the surface region of the back surface of the semiconductor wafer 10 after grinding. + type FS layer 49, p + collector region 51 and n +A lifetime killer may be introduced into a predetermined region inside the semiconductor wafer 10 by irradiating the semiconductor wafer 10 with, for example, helium (He) from the front or back surface of the semiconductor wafer 10. Next, a surface electrode (back surface electrode 15 in FIG. 15) is formed on the back surface of the semiconductor wafer 10 by a sputtering method. Next, a plating film (not shown) is formed on the surface of the surface electrode 14 by a plating process (step S11).

[0056] Next, various inspections of the semiconductor wafer 10 are performed (step S12), thereby completing the wafer process. The inspection in step S12 is an electrical characteristic test in which a probe needle is brought into contact with each electrode pad of the chip region 21 to input and output electrical signals, thereby inspecting basic functions and characteristics, and each chip region 21 of the semiconductor wafer 10 is judged as good or bad. This electrical characteristic test includes, for example, a test in which electrical characteristics such as the on-voltage, threshold voltage, and leakage current between each terminal of the semiconductor device 50 are evaluated to screen (select) chip regions 21 that deviate from the standard and become defective. Position information of chip regions 21 that are judged to be defective in the inspection in step S12 is stored in a predetermined storage medium.

[0057] In addition to the inspections in steps S3, S7, and S12 described above, the semiconductor wafer 10 may be inspected at a predetermined timing using a visual inspection device or visually by an on-site operator (e.g., inspection of the patterns and dimensions of each part, and mutual positional relationships, etc.). In this inspection as well, the position information of the chip regions 21 that are determined to be defective is stored in a predetermined storage medium. In the inspection of the latter step, the position information of the chip regions 21 that are determined to be defective stored in the predetermined storage medium is referenced, and only the chip regions 21 that are not determined to be defective can be inspected. In other words, each time the semiconductor wafer 10 is inspected, the chip regions 21 that are determined to be defective are excluded from the inspection target, and the throughput of the inspection of the semiconductor wafer 10 can be improved as the manufacturing flow progresses.

[0058] Next, the semiconductor wafer 10 is cut (diced) along the dicing lines 22 to separate each chip region 21 into individual semiconductor chips 40 (see FIG. 15) (step S13). Next, the semiconductor chips 40 formed by separating the chip regions 21 that do not include any defective chip regions determined by the inspections in steps S3, S7, S12, etc. described above are picked up and subjected to an electrical characteristic test (step S14), and the semiconductor chips 40 determined to be good are used as products (semiconductor device 50). Examples of the process in step S14 include reliability tests such as a Temperature / Humidity Bias (THB) test and a High Temperature Reverse Bias (HTRB) test.

[0059] The semiconductor chips 40 that are judged to be good are packaged into semiconductor modules in the subsequent assembly process. Then, a predetermined reliability test is performed on the semiconductor modules under a temperature load and a voltage load (burn-in) to remove defective modules. This reliability test includes screening of semiconductor modules that have become defective due to gate characteristic variations caused by burn-in. For example, as described below, if the semiconductor chip 40 includes an FWD region 62, characteristic defects caused in the FWD region 62 by the convex defect 2 or the concave defect 3 of the front surface electrode 14 are not detected in the reliability test of the semiconductor module, but the convex defect 2 and the concave defect 3 of the front surface electrode 14 are reliably detected in the process of step S7 described above, thereby reducing the number of defective modules.

[0060] The method for manufacturing a semiconductor device described in this embodiment can be realized by executing a prepared program on a computer such as a personal computer or a workstation, or on a database server or a web server. Information acquired during the manufacturing process of the semiconductor device described in this embodiment is stored in a computer-readable storage medium such as a solid-state drive (SSD), a hard disk, a Blu-ray (registered trademark) disc (BD), or a USB flash memory, and is used by being appropriately read from the storage medium by a computer or a server.

[0061] A structural example of a semiconductor device manufactured by applying the manufacturing method of a semiconductor device according to the embodiment described above will be described with reference to FIG. 15. FIG. 15 is a cross-sectional view showing a structural example of a semiconductor device manufactured by applying the manufacturing method of a semiconductor device according to the embodiment. FIG. 15 shows an active region, and an edge termination region is omitted. The semiconductor device 50 shown in FIG. 15 is an RC (Reverse Conducting)-IGBT in which a trench gate IGBT (Insulated Gate Bipolar Transistor) and a diode connected in inverse parallel to the IGBT are integrated into the same semiconductor chip (semiconductor substrate) 40. The semiconductor chip 40 is obtained by dividing the chip region 21 of the semiconductor wafer 10 in the process of step S13 described above.

[0062] The above-mentioned element structure 20, interlayer insulating film 11, barrier metal 12, contact plug 13, and surface electrode 14 are provided on the front surface side of semiconductor chip 40. In the active region of semiconductor chip 40, an IGBT region 61 which is the operating region of the IGBT and an FWD region 62 which is the operating region of a free wheeling diode (FWD) are provided adjacent to each other in a direction parallel to the front surface of semiconductor chip 40. + type FS layer 49, p + collector region 51 and n+ The portion excluding the cathode region 52 is n - The element structure 20 includes a p-type drift region 41, a p-type base region 42, an n-type + Type emitter region 43, p + It comprises a mold contact region 44 , a trench 46 , a gate insulating film 47 and a gate electrode 48 .

[0063] The p-type base region 42 is connected to the front surface of the semiconductor chip 40 in the active region. - The p-type base region 42 is disposed on the lower surface (n + The surface on the side of the cathode region 52) - The p-type base region 42 contacts the p-type drift region 41. The p-type base region 42 functions as a p-type anode region in the FWD region 62. + type emitter region 43 and p + The n-type contact region 44 is selectively provided between the front surface of the semiconductor chip 40 and the p-type base region 42 in the IGBT region 61, and is not provided in the FWD region 62. + type emitter region 43 and p + The contact region 44 is + The n-type collector region 51 (the surface on the side of the n-type collector region 51) contacts the p-type base region 42. + type emitter region 43 and p + The mold contact region 44 contacts the barrier metal 12 on the front surface of the semiconductor chip 40 .

[0064] n + The p-type emitter region 43 faces the gate electrode 48 via the gate insulating film 47 on the side wall of the trench 46. + The contact region 44 may not be provided. + When the contact region 44 is not provided, + The p-type base region 42 reaches the front surface of the semiconductor chip 40 instead of the n-type contact region 44. -An n-type carrier storage (CS) region 45 may be provided between the n-type drift region 41 and in contact with these regions. A trench 46 penetrates the p-type base region 42 from the front surface of the semiconductor chip 40 to form an n-type - The trench 46 is formed in the IGBT region 61 and the FWD region 62. The gate insulating film 47 is formed along the inner wall of the trench 46. The gate electrode 48 is formed inside the trench 46 with the gate insulating film 47 interposed therebetween.

[0065] The interlayer insulating film 11 is provided over the entire front surface of the semiconductor chip 40. A contact hole 11a is provided that penetrates the interlayer insulating film 11 in the depth direction and reaches the front surface of the semiconductor chip 40. The contact hole 11a in the IGBT region 61 has an n + type emitter region 43 and p + In the contact hole 11a of the FWD region 62, the p-type contact region 44 is exposed. In the contact hole 11a of the FWD region 62, the p-type base region 42 is exposed. The barrier metal 12 is provided along the sidewall (side surface of the interlayer insulating film 11) and bottom surface (front surface of the semiconductor chip 40) of the contact hole 11a. The barrier metal 12 is provided along the n-type contact region 44 in the contact hole 11a of the IGBT region 61. + type emitter region 43 and p + The p-type contact region 44 is in ohmic contact with the p-type contact region 44 and is in contact with the p-type base region 42 within the contact hole 11 a of the FWD region 62 .

[0066] The contact plug 13 is embedded on the barrier metal 12 inside the contact hole 11a. The surface electrode 14 is provided on the interlayer insulating film 11 and the contact plug 13. The surface electrode 14 is connected to the p-type base region 42, the n-type base region 43, and the n-type base region 44 via the contact plug 13 and the barrier metal 12. + type emitter region 43 and p + The surface electrode 14 functions as an emitter electrode in the IGBT region 61 and as an anode electrode in the FWD region 62. -Within the drift region 41, n + A lifetime control region (not shown) may be provided at a position shallower than the mold FS layer 49, in which a lifetime killer is introduced by, for example, helium (He) irradiation.

[0067] n + The n-type FS layer 49 is in contact with the back surface of the semiconductor chip 40. - The electrode is provided over the entire area between the electrode and the drift region 41. + The n-type collector region 51 is in contact with the back surface of the semiconductor chip 40. + The FS layer 49 is provided in the region other than the FWD region 62. + The n-type cathode region 52 is connected to the back surface of the semiconductor chip 40 in the FWD region 62. + It is provided between the mold FS layer 49. + The cathode region 52 is p-type in a direction parallel to the back surface of the semiconductor chip 40. + The back electrode 15 is provided on the back surface of the semiconductor chip 40 and is adjacent to the p-type collector region 51. + collector region 51 and n + The back electrode 15 is in contact with the first cathode region 52. The back electrode 15 functions as a collector electrode in the IGBT region 61, and functions as a cathode electrode in the FWD region 62.

[0068] As described above, according to the embodiment, position information of chip areas determined to be defective in multiple inspections (inspection by a visual inspection device, visual inspection by an on-site operator) performed on semiconductor wafers at a predetermined timing is stored in a predetermined storage medium. Then, in a later inspection, the position information of chip areas including defective judgments stored in the storage medium is referenced, and only chip areas including no defective judgments are inspected. This makes it possible to exclude chip areas including defective judgments from the inspection targets each time an inspection is performed on a semiconductor wafer, thereby improving the inspection throughput of semiconductor wafers as the manufacturing flow progresses. By improving the inspection throughput, capital investment can be reduced.

[0069] According to the embodiment, after forming a surface electrode on the front surface of a semiconductor wafer, an automatic appearance inspection is performed by an appearance inspection device to detect convex and concave defects in the surface electrode before annealing the surface electrode. At this time, exposure focus is adjusted to the surface of the resist film on the normal portion of the surface electrode by photolithography and etching, and a fine resist pattern is formed on the surface of the surface electrode. Since the exposure focus is not adjusted to the surface of the resist film on the convex and concave defects of the surface electrode, the portions of the fine resist pattern on the convex and concave defects become pattern defective portions. By detecting this pattern defective portion by the appearance inspection device, the convex and concave defects in the surface electrode can be detected.

[0070] Furthermore, when detecting convex and concave defects using a visual inspection device, by focusing on the surface of the fine resist pattern, the focus is not set on the grain boundaries of the surface electrodes, so that the visual inspection device does not erroneously detect the grain boundaries. Since there is no need for an on-site operator to re-evaluate the defects detected by the visual inspection device, the throughput of the inspection is further improved. In addition, the labor required for the on-site operator to visually inspect the entire manufacturing flow is reduced, and the burden on the on-site operator can be reduced. Furthermore, by making the fine resist pattern a regular pattern, pattern defects in the resist pattern can be easily detected by the visual inspection device, and the throughput of the inspection is further improved.

[0071] Furthermore, according to the embodiment, chip regions in which convex and concave defects have occurred due to foreign matter being introduced into the surface electrodes can be reliably detected. Therefore, for example, semiconductor chips that may have poor electrical characteristics (assembly defects) in a reliability test during the assembly process due to plating solution seeping into the lower layer from convex and concave defects in the surface electrodes during plating treatment on the surface of the surface electrodes can be determined as defective and removed at the semiconductor wafer process stage. This makes it possible to reduce defective modules and manufacturing costs.

[0072] The present disclosure is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present disclosure. For example, the present disclosure can be applied to various semiconductor devices regardless of the material, wafer size, and element structure of the semiconductor wafer. [Industrial Applicability]

[0073] INDUSTRIAL APPLICABILITY As described above, the method for manufacturing a semiconductor device according to the present disclosure is useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines and the like. [Explanation of symbols]

[0074] 1,1a,1b,1c,101 Foreign matter 2,102 Convex defect on the surface of the surface electrode 3,103 Defect on the surface of the surface electrode 10,110 Semiconductor wafers 11,111 Interlayer insulating film 11a, 111a contact hole 12,112 Barrier metal 13,113 Contact plug 14,114 surface electrode 14b, 114b Grain boundary of surface electrode 15 Back electrode 20 Element structure 21 Chip area of ​​semiconductor wafer 22 Dicing Line 23 Ineffective Area of ​​Semiconductor Wafer 24 Orientation Flat 31, 32, 121 Resist film 31a, 121a Resist defect 33 Light from the light source of the exposure device 33a Exposure Focus 34 Resist Pattern 34a Resist pattern hole 34b Normal part of resist pattern 34c, 34d Pattern defect of resist pattern 35,135 Focus of the irradiation light or inspection unit of the visual inspection device 40 Semiconductor Chips 41 n - Type Drift Region 42 p-type base region 43 n + Type emitter area 44 pages + Mold Contact Area 45 n-type CS region 46 Trench 47 Gate insulating film 48 Gate electrode 49 n + type FS layer 50 Semiconductor device 51 p + Type Collector Region 52 n + Type cathode area 61 IGBT area 62 FWD area 114a Surface cracks on the surface electrode h1 Height of foreign object h2 Height of the convex defect h3 Depth of concave defect t1 Surface electrode thickness t11 Resist pattern thickness w1 Width of foreign object w2 Width of the convex defect remaining after patterning of the surface electrode w3 Width of concave defect w11 Resist remaining width of resist pattern w12 Width of the resist hole in the resist pattern

Claims

1. A first step of forming a surface electrode on a surface of a semiconductor wafer; a second step of forming a resist film on the front surface electrode; a third step of exposing and developing the resist film to form a predetermined resist pattern; a fourth step of detecting surface defects occurring in the front surface electrode during the first step based on an intensity ratio of reflected light of light irradiated onto the front surface electrode side of the semiconductor wafer, or by photographing the front surface electrode side of the semiconductor wafer using an imaging means and comparing the images; Including, In the third step, a pattern defect is generated in a portion of the resist pattern on the surface defect, A method for manufacturing a semiconductor device, characterized in that in the fourth step, the surface of the resist pattern is used as the focal position of the irradiation light or the photographing means to detect the pattern defect, and the detection position of the pattern defect is set as the detection position of the surface defect.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the third step, a pattern missing portion is created on the portion of the surface defect of the resist pattern, the pattern missing portion being formed by resist remaining with a width wider than a remaining width of resist on a normal portion of the surface electrode where the surface defect does not occur, or the pattern missing portion being formed by resist being removed with a width wider than a width of a hole in the resist on the normal portion of the surface electrode.

3. the remaining width of the resist of the resist pattern is narrower than the width of the surface defect, 3. The method for manufacturing a semiconductor device according to claim 2, wherein the width of the hole in the resist of the resist pattern is narrower than the width of the surface defect.

4. the remaining width of the resist of the resist pattern is equal to or smaller than ¼ of the width of the surface defect, 3. The method for manufacturing a semiconductor device according to claim 2, wherein the width of the hole in the resist of the resist pattern is equal to or smaller than 1 / 4 of the width of the surface defect.

5. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the third step, the resist pattern is formed with regularity.

6. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the third step, the resist pattern is formed such that an area of ​​the remaining resist is equal to an area of ​​the hole in the resist.

7. the surface defect is a convex defect in which a part of the surface of the front electrode is raised, or a concave defect in which a part of the surface of the front electrode is concave, or both; 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the third step, the surface of the resist film on a normal portion of the surface electrode where the surface defect is not present is set as the focal position of the exposure, and the resist film is exposed to light of a short wavelength such that the exposure is not focused on the surface of the resist film on the surface defect, thereby forming the resist pattern.

8. The first step comprises: a deposition step of depositing the front surface electrode by sputtering; an etching step of patterning the surface electrode by photolithography and etching; Including, The bump defect is caused by a foreign matter being introduced into the front surface electrode during the film formation process, 8. The method for manufacturing a semiconductor device according to claim 7, wherein the concave defect is caused by selective removal of the front surface electrode at a resist defect portion of a resist mask used in the etching step.

9. In the third step, the resist pattern is formed for each chip region regularly provided on the semiconductor wafer, 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the fourth step, the surface of the semiconductor wafer on the surface electrode side is photographed using the photographing means, and images of adjacent chip regions of the semiconductor wafer are compared.

Images