Switching circuit

Abstract

To correctly control the state of a switching element.SOLUTION: A switching circuit (1A) comprises: a switching element (10); a gate drive circuit (20); and a clamp circuit (30) provided between the gate wiring (WRG) and the source wiring (WRS) of the switching element. The clamp circuit has a plurality of MOSFET series circuits inserted between the gate wiring and the source wiring. A drain and source are in short circuit in each MOSFET, and the plurality of MOSFET includes a first MOSFET (Mcs) connected to the source wiring and a second MOSFET (Mcg) connected to the gate wiring. A back gate and a source of the first MOSFET are connected to the source wiring. A back gate is not connected to a source in the second MOSFET, and the back gate of the second MOSFET is connected to the back gate of the first MOSFET.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present disclosure relates to a switch circuit. [Background technology]

[0002] In a switch circuit having a switching element, a gate signal is applied to the switching element to turn the switching element on or off. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-188429 A

[0004] [overview] In some switch circuits, a clamp circuit is inserted between the gate and source of a switching element. The clamp circuit limits the fluctuation range of the gate-source voltage of the switching element, thereby improving the responsiveness of the switching element. However, depending on the configuration of the clamp circuit, the clamp circuit may have a negative effect on the control of the switching element.

[0005] A switch circuit according to one embodiment of the present disclosure includes a switching element, a gate drive circuit configured to supply a gate signal to a gate of the switching element, and a clamp circuit provided between a gate wiring to which the gate of the switching element is connected and a source wiring to which the source of the switching element is connected, the clamp circuit having a series circuit of a plurality of MOSFETs inserted between the gate wiring and the source wiring, each MOSFET having a drain and a gate short-circuited to each other, the plurality of MOSFETs including a first MOSFET connected to the source wiring and a second MOSFET connected to the gate wiring, a backgate and a source of the first MOSFET connected to the source wiring, a backgate of the second MOSFET not connected to a source, and a backgate of the second MOSFET connected to the backgate of the first MOSFET. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a configuration diagram of a switch circuit according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is an external perspective view of a semiconductor substrate according to an embodiment of the present disclosure. [Diagram 3] FIG. 3 is a vertical structure diagram of a transistor (MOSFET) according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating the formation of a parasitic bipolar transistor in a vertical structure of a transistor (MOSFET) according to an embodiment of the present disclosure. [Diagram 5] FIG. 5 relates to a reference configuration and is a configuration diagram of a reference switch circuit. [Figure 6] FIG. 6 is a diagram showing how a collector current is generated in a parasitic bipolar transistor according to a reference configuration. [Figure 7] FIG. 7 is a diagram for explaining a path of a collector current of a parasitic bipolar transistor according to a reference configuration. [Figure 8] FIG. 8 is a configuration diagram of a switch circuit according to a first example of an embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram for explaining a flow path of a current generated at a back gate of a MOSFET in a clamp circuit according to a first example of an embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram showing characteristics of a reference switch circuit according to a reference configuration. [Figure 11] FIG. 11 is a diagram showing characteristics of a switch circuit according to a first example of an embodiment of the present disclosure. [Figure 12] FIG. 12 is a configuration diagram of a switch circuit according to a second embodiment of the present disclosure. [Figure 13] FIG. 13 is a configuration diagram of a switch circuit according to a third embodiment of the present disclosure. [Figure 14] FIG. 14 is a configuration diagram of a switch circuit according to a fifth embodiment of the present disclosure. [Figure 15] FIG. 15 is a schematic configuration diagram of a current sensor according to an eighth example of the embodiment of the present disclosure. [Figure 16] FIG. 16 is a partial configuration diagram of a current sensor according to an eighth example of the embodiment of the present disclosure. [Figure 17] FIG. 17 is a timing chart showing the relationship between two clock signals and the states of four switches according to an eighth example belonging to the embodiment of the present disclosure. [Figure 18] FIG. 18 is a diagram showing the states of the switches according to an eighth embodiment of the present disclosure.

[0007] [Detailed Description] Hereinafter, examples of the embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings, the same parts are given the same reference numerals, and duplicated descriptions of the same parts are omitted as a rule. In this specification, for the sake of simplicity, a symbol or code referring to information, signal, physical quantity, functional part, circuit, element or part, etc. may be written, and the name of the information, signal, physical quantity, functional part, circuit, element or part, etc. corresponding to the symbol or code may be omitted or abbreviated. For example, a switching transistor referred to by "10" (see FIG. 1) described later may be written as switching transistor 10 or abbreviated as transistor 10, but they all refer to the same thing.

[0008] First, some terms used in the description of the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference potential of 0V (zero volts), or refers to the potential of 0V itself. The reference conductor may be formed using a conductor such as a metal. The potential of 0V may also be called ground potential. In the embodiments of the present disclosure, a voltage shown without a particular reference represents a potential seen from ground. Level refers to the level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level.

[0009] For any transistor configured as a FET (field effect transistor) such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." For any transistor configured as a MOSFET, the gate-source voltage refers to the potential of the gate as viewed from the potential of the source.

[0010] Any switch can be composed of one or more FETs (field effect transistors), and when a switch is in the on state, both ends of the switch are conductive, whereas when a switch is in the off state, both ends of the switch are non-conductive. Hereinafter, the on and off states of any transistor or switch may be simply expressed as on and off.

[0011] For any signal having a high or low signal level, the period during which the signal level is high is referred to as a high-level period, and the period during which the signal level is low is referred to as a low-level period. Connections between multiple parts that form a circuit, such as any circuit elements, wiring, nodes, etc., may be understood to refer to electrical connections, unless otherwise specified.

[0012] FIG. 1 shows the configuration of a switch circuit 1 according to an embodiment of the present invention. The switch circuit 1 includes a switching transistor 10 (switching element), a gate drive circuit 20, a clamp circuit 30, a controller 40, and a resistor R1. The switching transistor 10 is inserted between terminals TMa and TMb. The terminals TMa and TMb may also be considered to be included in the components of the switch circuit 1. The switching transistor 10 is an N-channel MOSFET. Wires connected to the drain, source, and gate of the switching transistor 10 are referred to as drain wiring WR, D , source wiring WR S , gate wiring WR G This is called wiring WR. D , W.R. S and W.R. G can be understood to be included in the components of the switch circuit 1.

[0013] The drain of the switching transistor 10 is connected to the drain wiring WR D The drain wiring WR D The back gate and source of the switching transistor 10 are connected to the terminal TMb via a source wiring WR S and the source wiring WR SThe gate of the switching transistor 10 is connected to the terminal TMa via the gate wiring WR G . Only when the switching transistor 10 is on, the terminals TMa and TMb are electrically connected to each other, and a signal is transmitted between the terminals TMa and TMb. In this embodiment, the signal transmission between the terminals TMa and TMb is the transmission of a signal supplied from a signal source (not shown) to the terminal TMa to the terminal TMb. In this case, the terminal TMa corresponds to an input terminal, and the terminal TMb corresponds to an output terminal. However, the signal transmission between the terminals TMa and TMb may also be the transmission of a signal supplied from a signal source (not shown) to the terminal TMb to the terminal TMa.

[0014] The gate drive circuit 20 is connected to the gate wiring WR via a resistor R1. G In detail, the gate drive circuit 20 has an output terminal 21 and a driver 22, and the output terminal 21 is connected to a first terminal of a resistor R1. A second terminal of the resistor R1 is connected to the gate wiring WR G The gate wiring WR G The gate of the switching transistor 10 is connected to the gate wiring WR G and source wiring WR S The controller 40 is connected to the gate drive circuit 20 and outputs a control signal CNT to the gate drive circuit 20. The control signal CNT is a binary signal having a value of "1" or "0".

[0015] The signal supplied to the gate of the switching transistor 10 is called a gate signal. The gate signal of the switching transistor 10 is supplied to a gate wiring WR GThe gate drive circuit 20 sets the state of the switching transistor 10 to an off state or an on state by supplying a gate signal to the gate of the switching transistor 10 based on the control signal CNT. In detail, an output signal of the driver 22 is generated at the output terminal 21, and the output signal of the driver 22 is applied to a first terminal of the resistor R1 through the output terminal 21. In the gate drive circuit 20, the driver 22 can output a low level signal or a high level signal from the output terminal 21. When the control signal CNT has a value of "0", the driver 22 outputs a low level signal from the output terminal 21 to set the state of the switching transistor 10 to an off state. When the control signal CNT has a value of "1", the driver 22 outputs a high level signal from the output terminal 21 to set the state of the switching transistor 10 to an on state.

[0016] The driver 22 generates an output signal based on the level of the terminal TMa. Specifically, the low level of the output signal of the driver 22 coincides with the level of the terminal TMa (i.e., the source potential of the switching transistor 10). The gate threshold voltage of the switching transistor 10 is represented by the symbol “V GTH The high level of the output signal of the driver 22 (i.e., the high level at the output terminal 21) is expressed as the gate threshold voltage V GTH Even higher than just a high level.

[0017] The high level in the output signal of driver 22 may be a fixed constant level. However, here, when the value of control signal CNT switches from "0" to "1" and the output signal of driver 22 switches from low level to high level, the level of the output signal of driver 22 shall rise steeply from level LV1 to level LV3 and then gradually decrease to level LV2. After the level of the output signal of driver 22 has decreased to level LV2, when the value of control signal CNT switches from "1" to "0", the level of the output signal of driver 22 shall decrease steeply from level LV2 to level LV1. In the output signal of driver 22, level LV1 is the low level, and both levels LV2 and LV3 belong to the high level. "LV1 + V GTH <LV2 < LV3" holds.

[0018] When switching transistor 10 is in the off state, the terminals TMa and TMb are disconnected, and when switching transistor 10 is in the on state, the terminals TMa and TMb are conductive. The gate-source voltage of switching transistor 10 is hereinafter referred to as the gate-source voltage V GS10 , or simply voltage V GS10 . For reducing the on-resistance of switching transistor 10, it is preferable to increase voltage V GS10 as much as possible. However, if voltage V GS10 when turning on switching transistor 10 is too large, the responsiveness when switching transistor 10 is switched from on to off deteriorates. Therefore, in switching circuit 1, a clamp circuit 30 is provided as a circuit for suppressing voltage V GS10 when turning on switching transistor 10 to be below clamp voltage V CLMP . Clamp voltage V CLMP has a predetermined voltage value (for example, 3.0V) according to the internal configuration of clamp circuit 30. Clamp voltage V CLMP is larger than gate threshold voltage V GTH .

[0019] In the switch circuit 1, when the level of the output signal of the driver 22 is level LV1, the level of the gate signal of the switching transistor 10 is also level LV1. The potential difference between levels LV1 and LV2 is a clamp voltage V CLMP Larger (but clamp voltage V CLMP In the switch circuit 1, when the level of the output signal of the driver 22 is equal to or higher than the level LV2, the level of the gate signal of the switching transistor 10 is lower than the level LV1 by a clamp voltage V CLMP When the level of the output signal of the driver 22 is high (i.e., when it is equal to or higher than the level LV2), the voltage Vcc is applied from the output terminal 21 to the resistor R1, the gate wiring WR G A current flows through the clamp circuit 30 toward the terminal TMa, and the voltage drop across the resistor R1 due to the current flows through the gate wiring WR G The potential at the output terminal 21 becomes lower than the potential at the output terminal 21. Providing the clamp circuit 30 can speed up the response of the switching transistor 10 from on to off. Furthermore, even if a surge-like excessive voltage is transiently output from the output terminal 21 when the switching transistor 10 is switched from off to on, a violation of the withstand voltage of the switching transistor 10 (input of a voltage exceeding the withstand voltage of the switching transistor 10) is unlikely to occur.

[0020] Here, the structure of the transistor MM that can be used in the switch circuit 1 will be described. FIG. 2 is a schematic perspective view of the exterior of a semiconductor substrate 600 on which the transistor MM is formed. FIG. 3 is a vertical structure diagram of the transistor MM. The switch circuit 1 is included in a semiconductor integrated circuit formed on the semiconductor device 600. The switch circuit 1 can be considered to be configured with the semiconductor substrate 600. For clarity of explanation, a three-dimensional orthogonal coordinate system consisting of mutually orthogonal X-axis, Y-axis, and Z-axis is defined as shown in FIG. 2. A plane parallel to the X-axis and Y-axis is called the XY plane. Any semiconductor substrate such as the semiconductor substrate 600 has two surfaces that face each other, one of which is called the main surface (or front surface) and the other is called the back surface. The main surface and the back surface are parallel to the XY plane. Each element that constitutes the switch circuit 1 is formed on the main surface side of the semiconductor substrate 600. In the vertical structure of a semiconductor integrated circuit, the direction from the back surface toward the main surface is considered to be upward, and the opposite direction is considered to be downward.

[0021] The semiconductor substrate 600 is a P-type semiconductor substrate. In FIG. 3, the hexagonal regions with diagonal hatching represent oxide films formed by LOCOS (Local Oxidation of Silicon) or the like. A buried layer 602 is formed on the main surface side of the semiconductor substrate 600. The buried layer 602 is an N-type semiconductor region. The buried layer 602 is an N + In the semiconductor substrate 600, a P-type well 604, which is a P-type semiconductor region, is formed above the buried layer 602. A transistor MM is formed on the P-type well 604. The transistor MM is an N-type semiconductor region (N + A source region 611 and a drain region 612 are P-type semiconductor regions (P + The source region 611, the drain region 612, and the back gate region 615 are formed in the well 604 at positions spaced apart from one another. The transistor MM further includes a gate oxide film 613 formed on a region of the P-type well 604 located between the source region 611 and the drain region 612, and a gate electrode E formed on the gate oxide film 613. Gand a gate electrode E G corresponds to the gate of transistor MM.

[0022] The source region 611, the drain region 612, and the back gate region 615 are exposed on the upper side of the semiconductor substrate 600. On the upper side of the semiconductor substrate 600, the source region 611, the drain region 612, and the back gate region 615 are respectively connected to a source electrode E S , drain electrode E D , back gate electrode E BG The source region 611 and the source electrode E S The source of the transistor MM is formed by the drain region 612 and the drain electrode E D The drain of the transistor MM is formed by the back gate region 615 and the back gate electrode E BG It may be understood that the P-type semiconductor region (corresponding to a part of the well 604) located between the back gate region 615 and the buried layer 602 is also included in the components of the back gate of the transistor MM.

[0023] An N-type well 621 and an N-type diffusion region 622 (N + A well 621 is formed in a region above the buried layer 602 at a position where the well 604 is not provided, and a diffusion region 622 is formed on the well 621. The diffusion region 622 is exposed on the upper side.

[0024] The multiple elements formed on the semiconductor substrate 600 and the multiple regions provided on the semiconductor substrate 600 are appropriately isolated by PN junction isolation or dielectric isolation technology. Dielectric isolation is achieved by using an oxide film such as LOCOS. Details of such isolation are well known and will not be described here.

[0025] A P-type semiconductor substrate is prepared, and various processes are performed on the P-type semiconductor substrate to form a semiconductor integrated circuit including a transistor MM on the P-type semiconductor substrate. Of the entire region of the semiconductor substrate 600, a region that remains a P-type semiconductor region before and after the various processes is called a substrate region 601. The substrate region 601 is exposed on the back side of the semiconductor substrate 600 and is connected to the ground. In other words, the substrate region 601 is a P-type semiconductor region connected to the ground, and therefore has a ground potential. An N-type buried layer 602 is provided between the substrate region 601 and a P-type well 604. In addition, in a direction parallel to the XY plane, an N-type semiconductor region (621, 622) is also provided between the substrate region 601 and the P-type well 604. Therefore, the transistor MM formed on the well 604 becomes (or can become) a floating MOSFET electrically insulated from the substrate region 601.

[0026] The above vertical structure forms a parasitic bipolar transistor BP shown in FIG. 4 in the semiconductor substrate 600. The parasitic bipolar transistor BP is a PNP-type bipolar transistor that is added to the transistor MM when the transistor MM is fabricated. In the parasitic bipolar transistor BP, the substrate region 601 functions as an emitter, the buried layer 602 functions as a base, and the well 604 functions as a collector. The well 621 and the diffusion region 622 may also be considered to be included in the components of the base of the parasitic bipolar transistor BP.

[0027] The buried layer 602, well 621, and diffusion region 622 form an integrated N-type semiconductor region. It is also possible to leave the N-type semiconductor regions (602, 621, 622) in an open state without connecting them to any potential point. However, in order to stabilize the potential of the N-type semiconductor regions (602, 621, 622) based on the potential of the terminal TMa, in this embodiment, unless otherwise specified, as shown in FIG. 4, the diffusion region 622 is connected to a first end of a resistor R2, and the second end of the resistor R2 is connected to the terminal TMa (and therefore the source wiring WR S). Therefore, the N-type semiconductor region (602, 621, 622) constituting the base of the parasitic bipolar transistor BP is connected to the terminal TMa (and therefore the source wiring WR S When a negative voltage (that is, a voltage lower than the ground potential) is applied to the terminal TMa, the negative voltage is also applied to the N-type semiconductor regions (602, 621, 622).

[0028] In FIG. 1, the gate wiring WR G From source wiring WR S The clamp circuit 30 can be configured with a series circuit of multiple diodes with their forward directions directed toward the center of the diodes. Alternatively, the clamp circuit 30 can be configured with a series circuit of multiple MOSFETs with their drains and gates shorted to each other. A reference configuration relating to the latter configuration will be described below.

[0029] [Reference configuration] FIG. 5 shows a reference switch circuit 901 according to a reference configuration. In the switch circuit 1 of FIG. 1, the reference switch circuit 901 is obtained by adopting the clamp circuit 930 as the clamp circuit 30. The clamp circuit 930 is composed of a series circuit of transistors 931-933. The transistors 931-933 are N-channel MOSFETs. In the reference switch circuit 901, the vertical structure of each of the transistors 10 and 931-933 is the same as that of the transistor MM. In each of the transistors 931-933, the drain and gate are shorted and the back gate and source are shorted. In the reference switch circuit 901, the drain of the transistor 931 is connected to the gate wiring WR G , the source of the transistor 931 is connected to the drain of the transistor 932, the source of the transistor 932 is connected to the drain of the transistor 933, and the source of the transistor 933 is connected to the source wiring WR S 5, a parasitic diode having a forward direction from the back gate to the drain is added to each of the transistors 931 to 933.

[0030] In the reference switch circuit 901, when the output signal of the driver 22 has a high level, a current flows from the output terminal 21 to the terminal TMa through the resistor R1 and each channel of the transistors 931 to 933, and the gate-source voltage V GS10 In the reference switch circuit 901, the voltage 3Vgs is the sum of the gate-source voltages Vgs of the transistors 931 to 933 when the output signal of the driver 22 has a high level. CLMP (see Figure 1) corresponds to a voltage of 3Vgs.

[0031] In principle, it is assumed that a voltage of 0V or more is supplied to the terminal TMa from a signal source (voltage source) not shown. However, in some cases, a negative voltage (i.e., a voltage lower than the ground potential) may be applied to the terminal TMa from a signal source not shown. Hereinafter, the state in which a negative voltage (i.e., a voltage lower than the ground potential) is applied to the terminal TMa will be referred to as a negative voltage applied state. The transistor MM according to the vertical structure of FIG. 3 is a floating MOSFET (N-channel type MOSFET) electrically insulated from the substrate region 601. Normally, if a floating MOSFET is used, leakage current from the substrate region 601 can be suppressed even in a negative voltage applied state. However, if a MOSFET in which the back gate and the source are short-circuited exists, an undesirable current may be generated in a negative voltage applied state. An undesirable current generated in the reference circuit 901 in a negative voltage applied state will be described with reference to FIG. 6 and FIG. 7.

[0032] FIG. 6 shows the vertical structure of a transistor 931 having the same vertical structure as the transistor MM. In a negative voltage application state, a current flows from a reference conductive portion (not shown) having a ground potential through the substrate region 601, the buried layer 602, the well 621, the diffusion region 622 and the resistor R2 to the terminal TMa, and the current becomes the base current of the parasitic bipolar transistor BP. Therefore, in a negative voltage application state, a collector current is generated in the parasitic bipolar transistor BP. In FIG. 6, a collector current Ic_931 generated in the parasitic bipolar transistor BP in the transistor 931 is shown. The collector current Ic_931 flows from a reference conductive portion (not shown) having a ground potential through the substrate region 601, the buried layer 602 and the well 604 to the backgate region 615 of the transistor 931.

[0033] 7 shows the flow path of the collector current Ic_931 in a negative voltage applied state. In a negative voltage applied state, the collector current Ic_931 is distributed to currents 941 and 942 (i.e., a part of the collector current Ic_931 flows as a current 941, and the remaining part of the collector current Ic_931 flows as a current 942). The current 941 flows from the back gate of the transistor 931 through the source of the transistor 931 and the channels of the transistors 932 and 933 to the terminal TMa. The current 942 flows from the back gate of the transistor 931 through the parasitic diode of the transistor 931 to the gate wiring WR G and then flows into the driver 22 via the resistor R1. The parasitic diode of the transistor 931 has a forward direction from the back gate of the transistor 931 toward the drain.

[0034] As a result, in the reference switch circuit 901, even if the driver 22 outputs a low-level signal in response to the control signal CNT of “0” in a negative voltage application state, the gate-source voltage V GSdrops only to a voltage (2Vgs-Vf). This voltage (2Vgs-Vf) makes it impossible to set the switching transistor 10 to the off state correctly, leading to malfunction. Of the voltage (2Vgs-Vf), the voltage 2Vgs is the sum of the gate-source voltages Vgs of the transistors 932 and 933 that are generated when a part of the collector current Ic_931 flows through each channel of the transistors 932 and 933. Of the voltage (2Vgs-Vf), the voltage Vf is the forward voltage of the parasitic diode of the transistor 931 that is generated when the remaining part of the collector current Ic_931 flows through the parasitic diode.

[0035] Below, in a number of embodiments, configuration examples, application techniques, modified techniques, etc. of the switch circuit 1 capable of suppressing the above malfunction will be described. The matters described above in this embodiment are applied to each of the following embodiments (excluding matters related to the reference configuration) unless otherwise specified and unless there is a contradiction. In the case of matters in each embodiment that contradict the matters described above, the description in each embodiment may take precedence. Furthermore, unless there is a contradiction, matters described in any of the following embodiments can also be applied to any of the other embodiments (i.e., any two or more of the embodiments can be combined).

[0036] <<First Example>> A first embodiment will be described. A switch circuit 1 according to the first embodiment includes a clamp circuit 30A shown in Fig. 8 as the clamp circuit 30. A switch circuit 1 having the clamp circuit 30A as the clamp circuit 30 will be specifically referred to as a switch circuit 1A. Fig. 8 is a configuration diagram of the switch circuit 1A.

[0037] The clamp circuit 30A includes transistors Mcg, Mcm1, and Mcs. The transistors Mcg, Mcm1, and Mcs are N-channel MOSFETs. The clamp circuit 30A is made up of a series circuit of the transistors Mcg, Mcm1, and Mcs. The vertical structure of each of the transistors 10, Mcg, Mcm1, and Mcs is the same as the vertical structure of the transistor MM.

[0038] In each of the transistors Mcg, Mcm1, and Mcs, the drain and gate are shorted. G From source wiring WR S In the clamp circuit 30C, the transistors Mcg, Mcm1, and Mcs are connected in series toward the gate wiring WR G The source of the MOSFET provided on the side is the source wiring WR S That is, in the clamp circuit 30A, the drain and gate of the transistor Mcg are connected to the gate wiring WR G (and therefore the gate of the switching transistor 10), the source of the transistor Mcg is connected to the drain and gate of the transistor Mcm1, the source of the transistor Mcm1 is connected to the drain and gate of the transistor Mcs, and the source of the transistor Mcs is connected to the source wiring WR S (Thus, it is connected to the terminal TMa). Although not shown in the figure, the sources of the transistors Mcs and 10 are commonly connected to a wiring (i.e., a source wiring WR S ) and the terminal TMa.

[0039] In transistor Mcm1, the backgate and source are shorted. That is, the backgate of transistor Mcm1 is connected to the source of transistor Mcm1. In transistor Mcs, the backgate and source are shorted. That is, the backgate of transistor Mcs is connected to the source of transistor Mcs. However, in transistor Mcg, the backgate and source are not shorted. The backgate of transistor Mcg is not connected to the source of transistor Mcg, but is instead connected to the backgate of transistor Mcs.

[0040] In FIG. 9, current 610, whose flow path is indicated by a solid line with an arrow, represents a current generated in the back gate of transistor Mcm1 when a negative voltage is applied. When a negative voltage is applied, a negative voltage is applied to an N-type semiconductor region (see FIG. 4) consisting of buried layer 602, well 621, and diffusion region 622, and thus current 610 is generated. Current 610 is a collector current of a parasitic bipolar transistor BP added to transistor Mcm1, and flows from a substrate region 601 connected to ground toward a back gate region 615 of transistor Mcm1 (see FIG. 4). As shown in FIG. 9, current 610 flows from the back gate of transistor Mcm1 through the source of transistor Mcm1 and the channel of transistor Mcs (i.e., between the drain and source) to source wiring WR S and is led to terminal TMa.

[0041] Since the back gate and source of the transistor Mcs are short-circuited, the current generated in the back gate of the transistor Mcs in the negative voltage application state (i.e., the collector current of the parasitic bipolar transistor BP added to the transistor Mcs) flows from the back gate of the transistor Mcs through the source of the transistor Mcs to the source wiring WR S and to the terminal TMa. In addition, since the back gate of the transistor Mcg is connected to the back gate of the transistor Mcs, the current generated in the back gate of the transistor Mcg in the negative voltage application state (i.e., the collector current of the parasitic bipolar transistor BP added to the transistor Mcg) flows from the back gate of the transistor Mcg through the back gate and source of the transistor Mcs to the source wiring WR S and the terminal TMa. A signal source (not shown) that supplies a negative voltage to the terminal TMa is connected to ground. Therefore, in the negative voltage application state, a current loop (closed circuit) is formed through which the current generated in the back gate of each transistor (transistors Mcg, Mcm1, and Mcs in the first embodiment) passes.

[0042] In this way, in the negative voltage application state, the current generated in the back gate of each transistor in the clamp circuit 30A flows through the source wiring WR S The gate wiring WR G Therefore, even in a negative voltage application state, when the output signal of the driver 22 has a low level, the gate-source voltage V GS The same applies to cases other than the negative voltage application state. That is, regardless of whether the voltage of the terminal TMa is 0 V or higher or a negative voltage, when the output signal of the driver 22 has a low level, the gate-source voltage V GS When the output signal of the driver 22 has a high level, the gate-source voltage V GS rises to a voltage of 3Vgs (see FIG. 9). Therefore, the switching transistor 10 can be correctly set to an on or off state in response to the control signal CNT (malfunction is suppressed). Note that the voltage 3Vgs in the first embodiment is the sum of the gate-source voltages Vgs of the transistors Mcg, Mcm1, and Mcs when the output signal of the driver 22 has a high level, and the clamp voltage V CLMP The voltage 3Vgs corresponds to the gate threshold voltage V GTH Greater than.

[0043] Please refer to Figures 10 and 11. In Figure 10, a dashed line 951 and solid lines 952 and 953 indicate the characteristics of the reference switch circuit 901 of Figure 5. The dashed line 951 is related to the reference switch circuit 901 and indicates the relationship between the gate potential of the switching transistor 10 at the boundary where the state of the switching transistor 10 switches between on and off, and the source potential of the switching transistor 10. The solid line 952 is related to the reference switch circuit 901 and indicates the relationship between the gate potential of the switching transistor 10 and the source potential of the switching transistor 10 when the output signal of the driver 22 is at a high level. The solid line 953 is related to the reference switch circuit 901 and indicates the relationship between the gate potential of the switching transistor 10 and the source potential of the switching transistor 10 when the output signal of the driver 22 is at a low level. In the reference switch circuit 901, in a part of a negative voltage application state where the source potential (potential of the terminal TMa) of the switching transistor 10 becomes negative, the potential indicated by the solid line 953 becomes higher than or approximately equal to the potential indicated by the dashed line 951. This means that the switching transistor 10 cannot be properly set to off even if the output signal of the driver 22 is at a low level.

[0044] In FIG. 11, a dashed line 651 and solid lines 652 and 653 indicate the characteristics of the switch circuit 1A. The dashed line 651 is related to the switch circuit 1A and indicates the relationship between the gate potential of the switching transistor 10 at the boundary where the state of the switching transistor 10 switches between on and off, and the source potential of the switching transistor 10. The solid line 652 is related to the switch circuit 1A and indicates the relationship between the gate potential of the switching transistor 10 and the source potential of the switching transistor 10 when the output signal of the driver 22 is at a high level. The solid line 653 is related to the switch circuit 1A and indicates the relationship between the gate potential of the switching transistor 10 and the source potential of the switching transistor 10 when the output signal of the driver 22 is at a low level. In the switch circuit 1A, a necessary potential difference is maintained between the potential indicated by the dashed line 651 and the potential indicated by the solid line 653, regardless of the source potential of the switching transistor 10 (the potential of the terminal TMa). This means that when the output signal of the driver 22 is at a low level, the switching transistor 10 can be correctly set to OFF regardless of the source potential of the switching transistor 10 (the potential of the terminal TMa).

[0045] <<Second Example>> A second embodiment will be described. A switch circuit 1 according to the second embodiment includes a clamp circuit 30B shown in Fig. 12 as the clamp circuit 30. A switch circuit 1 having a clamp circuit 30B as the clamp circuit 30 will be specifically referred to as a switch circuit 1B. Fig. 12 is a configuration diagram of the switch circuit 1B.

[0046] Like the clamp circuit 30A according to the first embodiment, the clamp circuit 30B is composed of a series circuit of transistors Mcg, Mcm1, and Mcs. The clamp circuit 30B is a partial modification of the clamp circuit 30A. Specifically, in the clamp circuit 30B, the back gate of the transistor Mcm1 is not connected to the source of the transistor Mcm1, but is instead connected to the back gate of the transistor Mcs. Except for the fact that the connection destination of the back gate of the transistor Mcm1 is different between the clamp circuits 30A and 30B, the clamp circuits 30A and 30B have the same configuration as each other, and the switch circuits 1A and 1B have the same configuration as each other, and the matters described in the first embodiment are also applied to the second embodiment.

[0047] In a negative voltage application state related to the clamp circuit 30B, a current generated in the back gate of the transistor Mcm1 (i.e., a collector current of the parasitic bipolar transistor BP added to the transistor Mcm1) flows from the back gate of the transistor Mcm1 through the back gate and source of the transistor Mcs to the source wiring WR S and is led to terminal TMa.

[0048] Therefore, similarly to the first embodiment, the switching transistor 10 can be correctly set to the on or off state in response to the control signal CNT (erroneous operation is suppressed).

[0049] <<Third Example>> A third embodiment will be described. The number of MOSFETs connected in series in clamp circuit 30 is not limited to three. In the third embodiment, it is assumed that the number of MOSFETs connected in series in clamp circuit 30 is four. Switch circuit 1 according to the third embodiment includes clamp circuit 30C shown in FIG. 13 as clamp circuit 30. Switch circuit 1 having clamp circuit 30C as clamp circuit 30 will be particularly referred to as switch circuit 1C. FIG. 13 is a configuration diagram of switch circuit 1C.

[0050] The clamp circuit 30C is obtained by adding a transistor Mcm2 to the clamp circuit 30A, and is composed of a series circuit of transistors Mcg, Mcm1, Mcm2, and Mcs. The vertical structure of the transistor Mcm2 is the same as that of the transistor MM. Except for the addition of the transistor Mcm2, the clamp circuits 30A and 30C have the same configuration as the switch circuits 1A and 1C, and the matters described in the first embodiment are also applied to the third embodiment. However, with the addition of the transistor Mcm2, the connection relationship of each transistor in the clamp circuit 30C becomes as follows:

[0051] In each of the transistors Mcg, Mcm1, Mcm2, and Mcs, the drain and gate are shorted. G From source wiring WR S In the clamp circuit 30C, the transistors Mcg, Mcm1, Mcm2, and Mcs are connected in series toward the gate wiring WR G The source of the MOSFET provided on the side is the source wiring WR S That is, in the clamp circuit 30C, the drain and gate of the transistor Mcg are connected to the gate wiring WR G (and therefore the gate of the switching transistor 10), the source of the transistor Mcg is connected to the drain and gate of the transistor Mcm1, the source of the transistor Mcm1 is connected to the drain and gate of the transistor Mcm2, the source of the transistor Mcm2 is connected to the drain and gate of the transistor Mcs, and the source of the transistor Mcs is connected to the source wiring WR S (hence connected to terminal TMa).

[0052] The backgate and source of each of the transistors Mcs, Mcm2, and Mcm1 are shorted. That is, the backgate of the transistor Mcs is connected to the source of the transistor Mcs, the backgate of the transistor Mcm2 is connected to the source of the transistor Mcm2, and the backgate of the transistor Mcm1 is connected to the source of the transistor Mcm1. However, similar to the first and second embodiments, the backgate and source of the transistor Mcg are not shorted. The backgate of the transistor Mcg is not connected to the source of the transistor Mcg, but is instead connected to the backgate of the transistor Mcs.

[0053] In the negative voltage application state, the flow path of the current generated in the back gate of transistor Mcs (i.e., the collector current of the parasitic bipolar transistor BP added to transistor Mcs) and the flow path of the current generated in the back gate of transistor Mcg (i.e., the collector current of the parasitic bipolar transistor BP added to transistor Mcg) are as shown in the first embodiment.

[0054] In a negative voltage application state, a current generated in the back gate of the transistor Mcm1 (i.e., a collector current of the parasitic bipolar transistor BP added to the transistor Mcm1) flows from the back gate of the transistor Mcm1 through the source of the transistor Mcm1 and each channel (i.e., between the drain and source) of the transistors Mcm2 and Mcs to the source wiring WR S In a negative voltage application state, a current generated in the back gate of the transistor Mcm2 (i.e., a collector current of a parasitic bipolar transistor BP added to the transistor Mcm2) flows from the back gate of the transistor Mcm2 through the source of the transistor Mcm2 and the channel of the transistor Mcs (i.e., between the drain and source) to the source wiring WR S and is led to terminal TMa.

[0055] In this way, in the negative voltage application state, the current generated in the back gate of each transistor in the clamp circuit 30C flows through the source wiring WRS The gate wiring WR G Therefore, even in a negative voltage application state, when the output signal of the driver 22 has a low level, the gate-source voltage V GS The same applies to cases other than the negative voltage application state. That is, regardless of whether the voltage of the terminal TMa is 0 V or higher or a negative voltage, when the output signal of the driver 22 has a low level, the gate-source voltage V GS When the output signal of the driver 22 has a high level, the gate-source voltage V GS rises to a voltage of 4Vgs. Therefore, the switching transistor 10 can be correctly set to an on or off state in response to the control signal CNT (malfunctioning is suppressed). Note that the voltage 4Vgs in the third embodiment is the sum of the gate-source voltages Vgs of the transistors Mcg, Mcm1, Mcm2, and Mcs when the output signal of the driver 22 has a high level, and the clamp voltage V CLMP The voltage 4Vgs corresponds to the gate threshold voltage V GTH Greater than.

[0056] <<Fourth Example>> A fourth embodiment will now be described. Just as the first embodiment can be modified to the second embodiment, the third embodiment can be modified as follows.

[0057] That is, in the switch circuit 1C of FIG. 13, a first modification may be applied in which the back gate of transistor Mcm1 is not connected to the source of transistor Mcm1 but is instead connected to the back gate of transistor Mcs (not shown in the first modification). Even when the first modification is applied, the same actions and effects as those of the third embodiment can be obtained. In the negative voltage application state according to the first modification, a current generated in the back gate of transistor Mcm1 (i.e., the collector current of the parasitic bipolar transistor BP added to transistor Mcm1) flows from the back gate of transistor Mcm1 through the back gate and source of transistor Mcs to the source wiring WR. S and is led to terminal TMa.

[0058] Furthermore, in the switch circuit 1C of FIG. 13, a second modification may be applied in which the back gate of transistor Mcm2 is not connected to the source of transistor Mcm2 but is instead connected to the back gate of transistor Mcs (not shown in the second modification). The second modification also provides the same effects and advantages as the third embodiment. In the negative voltage application state according to the second modification, a current generated in the back gate of transistor Mcm2 (i.e., the collector current of the parasitic bipolar transistor BP added to transistor Mcm2) flows from the back gate of transistor Mcm2 through the back gate and source of transistor Mcs to the source wiring WR. S and is led to terminal TMa.

[0059] In the switch circuit 1C of FIG. 13, both the first and second modifications may be applied.

[0060] <<Fifth Example>> A fifth embodiment will now be described. The number of MOSFETs connected in series in the clamp circuit 30 is represented by n. In the first and second embodiments, "n=3", and in the third and fourth embodiments, "n=4". n may represent any integer equal to or greater than 2.

[0061] Any clamp circuit 30 is composed of a series circuit of n MOSFETs. Each of the n MOSFETs is an N-channel MOSFET, and each of the n MOSFETs has the same vertical structure as that of the transistor MM. In each of the n MOSFETs, the drain and gate are shorted together. In any clamp circuit 30, between two mutually adjacent MOSFETs, the gate wiring WR G The source of the MOSFET provided on the side is the source wiring WR S The drain of the MOSFET provided on the side of the

[0062] The optional clamp circuit 30 includes at least a source wiring WR S A transistor Mcs having a source connected to a gate wiring WR G In any clamp circuit 30, the back gate and source of the transistor Mcs are connected to the source wiring WR S , and the back gate of the transistor Mcg is not connected to the source of the transistor Mcg but is connected to the back gate of the transistor Mcs.

[0063] The clamp circuit 30 that satisfies "n≧3" has, in addition to the transistors Mcs and Mcg, (n-2) intermediate transistors provided between the transistors Mcs and Mcg. In the first and second embodiments in which "n=3" is satisfied, the transistor Mcm1 corresponds to the intermediate transistor, and in the third and fourth embodiments in which "n=4" is satisfied, the transistors Mcm1 and Mcm2 correspond to the first and second intermediate transistors.

[0064] For example, when configuring a clamp circuit 30 where "n=5", a third intermediate transistor is added based on the switch circuit 1C in FIG. 13 and the third intermediate transistor is inserted in series between the transistors Mcm2 and Mcs. The same applies to the case where "n≧6". The drain and gate of each intermediate transistor are shorted. For any intermediate transistor, the backgate of the intermediate transistor is connected to the source of the intermediate transistor (i.e., the backgate and source of the intermediate transistor are shorted). Alternatively, for any intermediate transistor, the backgate of the intermediate transistor is connected to the backgate of transistor Mcs without being connected to the source of the intermediate transistor.

[0065] When "n=2", there is no intermediate transistor in the clamp circuit 30, and the clamp circuit 30 is formed only by the transistors Mcs and Mcg. The configuration of a switch circuit 1D, which is the switch circuit 1 when "n=2", is shown in Fig. 14. The switch circuit 1D includes a clamp circuit 30D as the clamp circuit 30.

[0066] The clamp circuit 30D corresponds to the clamp circuit 30A in FIG. 8 without the transistor Mcm1, and is composed of a series circuit of transistors Mcg and Mcs. Except for the absence of the transistor Mcm1, the clamp circuits 30A and 30D have the same configuration as each other, and the switch circuits 1A and 1D have the same configuration as each other. In the clamp circuit 30D, the drain and gate of the transistor Mcg are connected to the gate wiring WR G (and therefore the gate of the switching transistor 10), the source of the transistor Mcg is connected to the drain and gate of the transistor Mcs, and the source of the transistor Mcs is connected to the source wiring WR S (and therefore connected to the terminal TMa). In the clamp circuit 30D, the back gate of the transistor Mcs is connected (shorted) to the source of the transistor Mcs. In the clamp circuit 30D, the back gate of the transistor Mcg is not connected to the source of the transistor Mcg, but is instead connected to the back gate of the transistor Mcs.

[0067] <<Sixth Example>> A sixth embodiment will be described. The driver 22 is connected to the source wiring WR S The source wiring WR S In this case, the driver 22 may be a circuit that outputs a signal based on the potential of the source wiring WR S The voltage of the source line WR can be used as the negative power supply voltage. S , and the high level of the output signal of the driver 22 is set to the potential of the source wiring WR S The potential can be set to a value that is higher than the potential of the first electrode by a necessary amount.

[0068] However, a capacitor (not shown) may be inserted in series between the driver 22 and the output terminal 21, and the AC component of the output signal of the driver 22 may be supplied from the output terminal 21 to the first terminal of the resistor R1. In this case, the driver 22 may be a circuit that operates with a positive DC voltage (for example, 5V) as a positive power supply voltage and with the ground as a negative power supply voltage. When the control signal CNT is "1", the driver 22 supplies a signal having a positive power supply voltage (the DC voltage) as a high level signal, and when the control signal CNT is "0", a signal having a negative power supply voltage (ground potential) as a low level signal to the first terminal of the capacitor, and the AC component of the output signal of the driver 22 appears at the second terminal of the capacitor. The output terminal 21 is connected to the second terminal of the capacitor.

[0069] <<Seventh Example>> A seventh embodiment will be described. As described above, the buried layer 602, the well 621, and the diffusion region 622 form an integrated N-type semiconductor region (see FIG. 3). The configuration in which the N-type semiconductor region is connected to the terminal TMa via the resistor R2 in order to stabilize the potential of the N-type semiconductor region has been described above (see FIG. 4). However, the connection destination of the N-type semiconductor regions (602, 621, and 622) may be other than the terminal TMa. Depending on the conditions of the connection destination of the N-type semiconductor regions (602, 621, and 622), a negative voltage may be applied to the N-type semiconductor regions (602, 621, and 622), and in this case, an action equivalent to the above-mentioned negative voltage application state occurs.

[0070] Also, the terminal TMa may be a ground terminal having a ground potential. In this case, when a negative voltage is applied to the N-type semiconductor regions (602, 621, and 622), a collector current is generated in the parasitic bipolar transistor BP.

[0071] <<Eighth Example>> An eighth embodiment will be described. In the eighth embodiment, application of the switch circuit 1 to a current sensor will be described. FIG. 15 shows a schematic configuration diagram of a current sensor according to the eighth embodiment. The current sensor includes a current detection amplifier 110 and a sense resistor R SNS The current detection amplifier 110 includes terminals TM1 to TM5, as well as a square wave generating circuit 111, a switch control circuit 112, a current detection signal output circuit 113, an internal power supply circuit 114, electrostatic protection circuits 115P and 115M, a clamp protection circuit 116, protection resistors RP and RM, terminals 121 and 122, and capacitors 123 and 124. The terminals TM1 to TM5 correspond to external terminals, and the terminals 121 and 122 correspond to internal terminals.

[0072] The current detection amplifier 110 is a semiconductor device (electronic component) including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a case (package) for accommodating the semiconductor chip, and a plurality of external terminals exposed from the case to the outside of the current detection amplifier 110. The semiconductor device is formed by sealing the semiconductor chip in a case (package) made of resin. The circuits and circuit elements constituting the current detection amplifier 110, including the circuits 111 to 114, 115P, 115M, and 116, the protective resistors RP and RM, and the capacitors 123 and 124, are included in the semiconductor integrated circuit. Although only the terminals TM1 to TM5 are shown as external terminals provided in the current detection amplifier 110 in FIG. 15, other external terminals may also be provided in the current detection amplifier 110.

[0073] The sense resistor R SNS A sense resistor R SNS One end of the sense resistor R SNS The other end of is connected to the terminal TM2. SNS The connection node with the voltage V CM Therefore, the terminal TM2 has a voltage V CM is added. Voltage V CM Hereinafter, this may be referred to as the common-mode voltage.

[0074] Terminal TM1 and sense resistor R SNS The connection node between the load LD and the low potential terminal TMM is connected to one end of the load LD, and the other end of the load LD is connected to the low potential terminal TMM. CM A voltage lower than the high potential terminal TMP is applied across the sense resistor R SNS Current I flows through the load LD LD Then, the sense resistor R SNS A current I LD A voltage drop occurs based on the sense resistor R SNS The voltage drop at the sense voltage V SNS Terminal TM1 is connected to the common-mode voltage V CM than the sense voltage V SNS The voltage (V CM-V SNS In the following, the voltage at terminal TM1 is represented by the symbol "V INM The voltage at terminal TM2 is sometimes referred to as “V INP Typically, the low potential end TMM may be ground, in which case the low potential end TMM has a ground potential. However, the voltage of the low potential end TMM may be a negative voltage. CM may also become negative voltage.

[0075] The current detection signal S (described later) is output from terminal TM3. OUT is output. A power supply voltage VDD is supplied to the terminal TM4. The power supply voltage VDD has a positive DC voltage value within a predetermined voltage range. The terminal TM5 is connected to the ground.

[0076] The square wave generating circuit 111 is connected to the terminal TM1 via a protective resistor RM and is also connected to the terminal TM2 via a protective resistor RP. The square wave generating circuit 111 is configured to generate a voltage V INM At the same time, the voltage V applied to terminal TM2 through the protective resistor RP INP The square wave generating circuit 111 includes a plurality of switches and receives a voltage V INP and V INM Based on the sense resistor R SNS The voltage across the SNS The square wave generating circuit 111 uses the above-mentioned multiple switches to output a square wave signal through terminals 121 and 122 (details will be described later). The terminals 121 and 122 correspond to the output terminals of the square wave generating circuit 111. The voltages applied to the terminals 121 and 122 are respectively represented by the symbol "V OUTM ", "V OUTP " for reference.

[0077] The switch control circuit 112 controls the state (on / off state) of each switch in the square wave generating circuit 111.

[0078] The current detection signal output circuit 113 detects the current of the sense resistor R SNS Current I LD Current detection signal S according to OUT and generates the current detection signal S OUT is output from terminal TM3 to an external circuit (not shown) of the current detection amplifier 110. OUT Based on the current I LD For example, the value of the current detection signal S OUT is the current I LD Alternatively, for example, the current detection signal S OUT is the current I LD A capacitor 123 is inserted between the terminal 121 and the circuit 113, and a capacitor 124 is inserted between the terminal 122 and the circuit 113. Therefore, the voltage V OUTM and V OUTP The AC components of the square wave signal output from the square wave generating circuit 111 are input to the circuit 113. The circuit 113 amplifies the AC components of the square wave signal output from the square wave generating circuit 111 to generate the current detection signal S OUT Generate and output

[0079] The internal power supply circuit 114 generates one or more internal power supply voltages based on the power supply voltage VDD supplied to the terminal TM4. Each circuit in the current detection amplifier 110 can be driven by the internal power supply voltage generated by the internal power supply circuit 114. Fig. 15 shows an internal power supply voltage Vreg as an example of the internal power supply voltage generated by the internal power supply circuit 114. The internal power supply voltage Vreg has a predetermined positive DC voltage value.

[0080] The electrostatic protection circuit 115M is connected between the terminal TM1 and ground. The electrostatic protection circuit 115M protects the square wave generating circuit 111 from static electricity that may be applied to the terminal TM1 outside the current detection amplifier 110. The electrostatic protection circuit 115P is connected between the terminal TM2 and ground. The electrostatic protection circuit 115P protects the square wave generating circuit 111 from static electricity that may be applied to the terminal TM2 outside the current detection amplifier 110.

[0081] A first end of the protective resistor RM is connected to the terminal TM1, and a second end of the protective resistor RM is connected to the node NDM. A first end of the protective resistor RP is connected to the terminal TM2, and a second end of the protective resistor RP is connected to the node NDP. The clamp protection circuit 116 is connected to the nodes NDP and NDM. The clamp protection circuit 116 cooperates with the protective resistors RP and RM to generate a current through the protective resistors RP and RM and itself when an excessive voltage is applied between the terminals TM1 and TM2, thereby suppressing the potential difference between the nodes NDP and NDM to a predetermined clamp protection voltage or less. This makes it possible to prevent an excessive voltage from being applied to the square wave generating circuit 111.

[0082] Furthermore, the protective resistor RM has a function of protecting the internal circuitry (including the square wave generating circuit 111) of the current detection amplifier 110 by limiting the current flowing between terminals TM1 and NDM when a voltage that is too high or too low with respect to the ground potential is applied to terminal TM1. Similarly, the protective resistor RP has a function of protecting the internal circuitry (including the square wave generating circuit 111) of the current detection amplifier 110 by limiting the current flowing between terminals TM2 and NDP when a voltage that is too high or too low with respect to the ground potential is applied to terminal TM2.

[0083] In the following, unless otherwise specified, it is assumed that the current detection amplifier 110 operates in a normal input state. In the normal input state, the voltage V INP and V INM is within the specified operating voltage range and the sense resistor R SNS The voltage across the SNS ) is equal to or less than a predetermined differential allowable voltage. In a normal input state, substantially no current flows through the protection resistors RP and RM, and therefore the voltages of the nodes NDM and NDP are equal to or less than the voltage V INM , V INP can be considered equal to.

[0084] 16 shows the internal configuration of the square wave generating circuit 111. The square wave generating circuit 111 includes switches SW1 to SW4. A first end of the switch SW1 and a first end of the switch SW3 are commonly connected to a node NDM. A second end of the switch SW1 is connected to a terminal 121, and a second end of the switch SW3 is connected to a terminal 122. A first end of the switch SW2 and a first end of the switch SW4 are commonly connected to a node NDP. A second end of the switch SW2 is connected to the terminal 122, and a second end of the switch SW4 is connected to the terminal 121.

[0085] The switch control circuit 112 includes a clock output circuit 130. The clock output circuit 130 generates and outputs clock signals CLK1 and CLK2. The clock signals CLK1 and CLK2 are square wave signals having a predetermined frequency and a predetermined amplitude. The frequencies of the clock signals CLK1 and CLK2 are the same, and the amplitudes of the clock signals CLK1 and CLK2 are also the same. However, the phases of the clock signals CLK1 and CLK2 are different from each other by 180°. That is, the clock signal CLK2 corresponds to an inverted signal of the clock signal CLK1. The clock signals CLK1 and CLK2 are supplied to a square wave generating circuit 111. The states (on / off states) of the switches SW1 to SW4 are individually controlled based on the clock signals CLK1 and CLK2.

[0086] 17 shows a timing chart illustrating the relationship between the clock signals CLK1 and CLK2 and the states of the switches SW1 to SW4. The clock signals CLK1 and CLK2 alternate between high and low signal levels. However, when the clock signal CLK1 is at high level, the clock signal CLK2 is at low level, and when the clock signal CLK1 is at low level, the clock signal CLK2 is at high level. The duty cycle of the clock signals CLK1 and CLK2 is arbitrary, but is assumed to be 50% here.

[0087] In each of the clock signals CLK1 and CLK2, the high level has a potential of the voltage Vreg, and the low level has a potential of 0 V. The voltage Vreg is, for example, 4 V. The sense voltage VSNS is the current I LD In Figure 17, the sense voltage V SNS is assumed to be constant.

[0088] The high level period of the clock signal CLK1 is referred to as the first period. The high level period of the clock signal CLK1 coincides with the low level period of the clock signal CLK2. The low level period of the clock signal CLK1 is referred to as the second period. The low level period of the clock signal CLK1 coincides with the high level period of the clock signal CLK2. After the supply of the power supply voltage VDD to the current detection amplifier 110 starts and a predetermined startup process is performed, the first period and the second period alternate.

[0089] FIG. 18 shows states ST1 and ST2, which are two states that the square wave generating circuit 111 can take. In the first period, the state of the square wave generating circuit 111 is state ST1, and in the second period, the state of the square wave generating circuit 111 is state ST2. In state ST1 (thus, in the first period), the switches SW1 and SW2 are in the on state, and the switches SW3 and SW4 are in the off state. In state ST2 (thus, in the second period), the switches SW1 and SW2 are in the off state, and the switches SW3 and SW4 are in the on state. That is, the switch control circuit 112 alternately switches the state of the square wave generating circuit 111 (in other words, the states of the switches SW1 to SW4) between states ST1 and ST2 by outputting the clock signals CLK1 and CLK2.

[0090] In state ST1, the voltage V at terminal TM1 INM The voltage of the node NDM, which is equal to INP A voltage of the node NDP equal to "V OUTP =V INP =V CM "And "V OUTM =V INM =V CM -V SNSIn state ST2, the voltage V INM The voltage of node NDM, which is equal to INP A voltage of the node NDP equal to "V OUTP =V INM =V CM -V SNS "And "V OUTM =V INP =V CM " is.

[0091] Voltage V OUTP and V OUTM Each of them is "V SNS / 2” as an amplitude. SNS However, the voltage V OUTP and V OUTM The phases of the terminals 121 and 122 are different from each other by 180 degrees. Therefore, a difference voltage (V OUTP -V OUTM ) is generated. OUTP -V OUTM ) is a square wave signal that represents “V SNS A square wave signal with an amplitude of 2×V SNS The current detection signal output circuit 113 outputs the difference voltage (V OUTP -V OUTM ) based on the square wave signal representing the sense voltage V SNS By extracting the information of the current I LD Current detection signal S according to OUT can be generated.

[0092] In this way, the current sense amplifier 110 SNS Using the differential voltage (V OUTP -V OUTM ) based on a square wave signal representing the current I LD The current detection signal S OUT is the current I LD The detection results are shown below.

[0093] The relationship between the current detection amplifier 110 and the switch circuit 1 will be described. First to fourth switch circuits 1 are incorporated in the current detection amplifier 110. The switching transistors 10 in the first to fourth switch circuits 1 are switches SW1 to SW4, respectively. First terminals of the switches SW1 to SW4 correspond to the sources of the switching transistors 10 in the first to fourth switch circuits 1, respectively. Second terminals of the switches SW1 to SW4 correspond to the drains of the switching transistors 10 in the first to fourth switch circuits 1, respectively.

[0094] The wiring connected to the first terminals of the switches SW1 and SW3 is the source wiring WR in the first and third switch circuits 1. S The wiring connected to the first terminals of the switches SW2 and SW4 corresponds to the source wiring WR S The terminal 121 corresponds to the terminal TMb in the first and fourth switch circuits 1, and the terminal 122 corresponds to the terminal TMb in the second and third switch circuits 1.

[0095] In a normal input state, the presence of the protective resistor RM can be ignored, so the terminal TM1 corresponds to the terminal TMa in the first and third switch circuits 1. Similarly, in a normal input state, the presence of the protective resistor RP can be ignored, so the terminal TM2 corresponds to the terminal TMa in the second and fourth switch circuits 1.

[0096] The controllers 40 (see FIG. 1) in the first to fourth switch circuits 1 are incorporated in a switch control circuit 112. The gate drive circuits 20 in the first to fourth switch circuits 1 are incorporated in a square wave generating circuit 111. A high-level clock signal CLK1 corresponds to a control signal CNT of "1" in the first and second switch circuits 1, and a low-level clock signal CLK1 corresponds to a control signal CNT of "0" in the first and second switch circuits 1. A high-level clock signal CLK2 corresponds to a control signal CNT of "1" in the third and fourth switch circuits 1, and a low-level clock signal CLK2 corresponds to a control signal CNT of "0" in the third and fourth switch circuits 1. A resistor R1 and a clamp circuit 30 are provided for each of the switches SW1 to SW4 (the resistor R1 and the clamp circuit 30 are not shown in FIG. 16).

[0097] In addition, the sense resistor R SNS The above description has been given of a configuration in which the sense resistor R SNS may be built into the current detection amplifier 110. In this case, the sense resistor R SNS The current sensor is formed by a single current detection amplifier 110 having the built-in current detection amplifier.

[0098] Also, the sense resistor R SNS The above description has been given of a configuration in which the sense resistor R is provided on the higher potential side than the load LD. SNS may be provided on the lower potential side than the load LD.

[0099] Furthermore, the voltage Vreg may be the power supply voltage VDD itself that is supplied to the terminal TM4 from outside the current detection amplifier 110. In this case, the internal power supply circuit 114 can be omitted from the current detection amplifier 110.

[0100] <<Ninth Example>> A ninth embodiment will now be described.

[0101] The switch circuit 1 or the current detection amplifier 110 can be applied to any application (for example, an analog front end of an in-vehicle sensor, an analog front end of a medical sensor, a magnetic sensor, or a pressure sensor). The switch circuit 1 or the current detection amplifier 110 may be installed in a vehicle such as an automobile, and the switch circuit 1 or the current detection amplifier 110 may be applied to any load LD in the vehicle. In in-vehicle electronic components that often require high voltage resistance, being able to handle negative voltage input is beneficial in that safety can be ensured even in cases where fluctuations occur in the ground potential. In the eighth embodiment, a semiconductor device as the current detection amplifier 110 is used as a component of a current sensor, but the application of the semiconductor device (110) is arbitrary. The semiconductor device (110) can be used as any device that detects and amplifies a differential voltage between terminals TM1 and TM2.

[0102] If an SOI (Silicon On Insulator) process is used, leakage current between the semiconductor substrate and the input terminal (corresponding to TMa, TM1, or TM2) during negative voltage input can be suppressed. However, the adoption of an SOI process complicates the structure of the semiconductor integrated circuit, which may result in an increase in the circuit area. According to the method of the present disclosure, it is possible to accommodate negative voltage input without complicating the structure of the semiconductor integrated circuit. Furthermore, when an SOI process is used, the silicon substrate becomes expensive. The method of the present disclosure is advantageous in terms of cost because it can be realized using a normal silicon substrate.

[0103] In a semiconductor, one of the N-type and P-type is a first conductivity type and the other is a second conductivity type. When forming an arbitrary circuit element (such as a MOSFET) on a semiconductor substrate, the relationship between the N-type and the P-type can be reversed from the above relationship.

[0104] For any signal or voltage, the relationship between the high level and the low level thereof may be reversed to that described above without prejudice to the spirit of the above.

[0105] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values ​​shown in the above description are merely examples, and can be changed to various numerical values ​​as a matter of course.

[0106] <<Additional Notes>> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0107] A switch circuit (1) according to one aspect of the present disclosure includes a switching element (10), a gate drive circuit (20) configured to supply a gate signal to a gate of the switching element, and a gate wiring (WR G ) and the source wiring (WR S ), and a clamp circuit (30) provided between the gate wiring and the source wiring, the clamp circuit having a series circuit of a plurality of MOSFETs inserted between the gate wiring and the source wiring, in which the drain and gate of each MOSFET are shorted to each other, the plurality of MOSFETs including a first MOSFET (Mcs) connected to the source wiring and a second MOSFET (Mcg) connected to the gate wiring, a backgate and a source of the first MOSFET connected to the source wiring, a backgate of the second MOSFET not connected to the source, and a backgate of the second MOSFET connected to the backgate of the first MOSFET (first configuration).

[0108] If a current generated in the backgate of the second MOSFET flows into the gate wiring, the current may affect the potential of the gate signal, making it difficult to properly control the state (on / off state) of the switching element. According to the first configuration, even if a current is generated in the backgate of the second MOSFET, the current is guided to the source wiring rather than the gate wiring. This prevents the backgate current from flowing into the gate wiring, and allows the state of the switching element to be properly controlled.

[0109] The switch circuit according to the first configuration may be provided with a semiconductor substrate having a substrate region (601) to which a ground potential is applied and which has a first conductivity type, a first semiconductor region (604) having the first conductivity type, and a second semiconductor region (602) having a second conductivity type provided between the substrate region and the first semiconductor region, and each of the plurality of MOSFETs may be formed on the first semiconductor region (second configuration).

[0110] In the switch circuit according to the second configuration, a first conductivity type is P type and a second conductivity type is N type, and when a voltage lower than the ground potential is applied to the second semiconductor region, a PNP type parasitic bipolar transistor (BP) is formed by the substrate region, the first semiconductor region, and the second semiconductor region, and when a collector current is generated in the parasitic bipolar transistor of the second MOSFET, the collector current of the parasitic bipolar transistor of the second MOSFET may be guided from the backgate of the second MOSFET to the source wiring through the backgate and source of the first MOSFET (third configuration).

[0111] In the switch circuit according to the third configuration, the multiple MOSFETs may have an intermediate MOSFET (Mcm1, etc.) provided between the first MOSFET and the second MOSFET, a backgate and a source of the intermediate MOSFET are short-circuited, and a voltage lower than the ground potential is applied to the second semiconductor region to form a PNP-type parasitic bipolar transistor (BP) formed by the substrate region, the first semiconductor region, and the second semiconductor region, and when a collector current is generated in the parasitic bipolar transistor of the intermediate MOSFET, the collector current of the parasitic bipolar transistor of the intermediate MOSFET may be guided from the backgate of the intermediate MOSFET to the source wiring through the channel of the first MOSFET (fourth configuration).

[0112] In the switch circuit according to the third configuration, the multiple MOSFETs may include an intermediate MOSFET (Mcm1, etc.) provided between the first MOSFET and the second MOSFET, a backgate of the intermediate MOSFET is not connected to a source, and a backgate of the intermediate MOSFET is connected to a backgate of the first MOSFET, and a voltage lower than the ground potential is applied to the second semiconductor region to form a PNP-type parasitic bipolar transistor (BP) formed by the substrate region, the first semiconductor region, and the second semiconductor region, and when a collector current is generated in the parasitic bipolar transistor of the intermediate MOSFET, the collector current of the parasitic bipolar transistor of the intermediate MOSFET may be guided from the backgate of the intermediate MOSFET to the source wiring through the backgate and source of the first MOSFET (fifth configuration).

[0113] In the switch circuit according to any one of the second to fifth configurations, the second semiconductor region may be connected to the source wiring via a resistor (R2) (sixth configuration).

[0114] In the switch circuit according to any one of the first to third configurations, when a current is generated in the backgate of the second MOSFET, the current may be guided to the source wiring through the backgate and source of the first MOSFET (seventh configuration).

[0115] In a switch circuit according to any one of the first to third configurations, the plurality of MOSFETs may have an intermediate MOSFET (such as Mcm1) provided between the first MOSFET and the second MOSFET, a backgate and a source of the intermediate MOSFET are short-circuited, and when a current is generated in the backgate of the intermediate MOSFET, the current is guided to the source wiring through the source of the intermediate MOSFET and the channel of the first MOSFET (eighth configuration).

[0116] In a switch circuit according to any one of the first to third configurations, the plurality of MOSFETs may have an intermediate MOSFET (such as Mcm1) provided between the first MOSFET and the second MOSFET, a backgate of the intermediate MOSFET is not connected to a source, and a backgate of the intermediate MOSFET is connected to a backgate of the first MOSFET, and when a current is generated in the backgate of the intermediate MOSFET, the current may be guided to the source wiring through the backgate and source of the first MOSFET (ninth configuration). [Explanation of symbols]

[0117] 1, 1A~1D Switch circuit 10 Switching transistor (switching element) 20 Gate drive circuit 21 Output terminal 22 Drivers 30, 30A~30D Clamp circuit 40 Controller R1, R2 resistance WR D Drain wiring WR G Gate wiring WR S Source wiring TMa, TMb terminal 600 Semiconductor Substrates 601 Board area 602 Embedding Layer 604, 621 wells 622 Diffusion Area 611 Source Region 612 Drain Region 613 Gate oxide film 615 Backgate Region E S Source electrode E D Drain electrode E G Gate electrode E BG Backgate electrode MM Transistor BP Parasitic bipolar transistor Mcg, Mcs, Mcm1, Mcm2 transistors 110 Current Sense Amplifier 111 Square wave generation circuit 112 Switch control circuit 113 Current detection signal output circuit 114 Internal power supply circuit 115P, 115M Electrostatic protection circuit 116 Clamp protection circuit 121, 122 terminals (internal terminals) TM1~TM5 terminals (external terminals) TMP high potential end TMM low potential end R SNS Sense Resistor RP, RM protection resistance SW1~SW4 Switches 130 Clock output circuit V CM Common-mode voltage V SNS Sense Voltage V INP , V INM , V OUTP , V OUTM Voltage SOUT Current Detect Signal VDD Power supply voltage Vreg Internal power supply voltage 901 Reference Switch Circuit 930 Clamp Circuit 931~933 Transistors Ic_931 Collector current

Claims

1. A switching element; a gate drive circuit configured to provide a gate signal to a gate of the switching element; a clamp circuit provided between a gate wiring to which a gate of the switching element is connected and a source wiring to which a source of the switching element is connected; the clamp circuit has a series circuit of a plurality of MOSFETs inserted between the gate wiring and the source wiring, the drain and the gate of each MOSFET being short-circuited to each other; the plurality of MOSFETs includes a first MOSFET connected to the source wiring and a second MOSFET connected to the gate wiring; The back gate and the source of the first MOSFET are connected to the source wiring, In the second MOSFET, a back gate is not connected to a source, and a back gate of the second MOSFET is connected to a back gate of the first MOSFET. , switch circuit.

2. a substrate region having a first conductivity type and being applied with a ground potential; a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type and provided between the substrate region and the first semiconductor region, and each of the plurality of MOSFETs is formed on the first semiconductor region.

2. The switch circuit according to claim 1.

3. The first conductivity type is P type and the second conductivity type is N type, When a voltage lower than the ground potential is applied to the second semiconductor region, a PNP-type parasitic bipolar transistor formed by the substrate region, the first semiconductor region, and the second semiconductor region generates a collector current in the parasitic bipolar transistor of the second MOSFET, and the collector current of the parasitic bipolar transistor of the second MOSFET is guided from the back gate of the second MOSFET to the source wiring through the back gate and source of the first MOSFET.

3. The switch circuit according to claim 2.

4. the plurality of MOSFETs includes an intermediate MOSFET provided between the first MOSFET and the second MOSFET; In the intermediate MOSFET, the back gate and the source are shorted, When a voltage lower than the ground potential is applied to the second semiconductor region, a PNP-type parasitic bipolar transistor formed by the substrate region, the first semiconductor region, and the second semiconductor region generates a collector current in the parasitic bipolar transistor of the intermediate MOSFET, and the collector current of the parasitic bipolar transistor of the intermediate MOSFET is guided from a back gate of the intermediate MOSFET to the source wiring through a channel of the first MOSFET.

4. The switch circuit according to claim 3.

5. the plurality of MOSFETs includes an intermediate MOSFET provided between the first MOSFET and the second MOSFET; In the intermediate MOSFET, a back gate is not connected to a source, and a back gate of the intermediate MOSFET is connected to a back gate of the first MOSFET; When a voltage lower than the ground potential is applied to the second semiconductor region, a PNP-type parasitic bipolar transistor formed by the substrate region, the first semiconductor region, and the second semiconductor region generates a collector current in the parasitic bipolar transistor of the intermediate MOSFET, and the collector current of the parasitic bipolar transistor of the intermediate MOSFET is guided from a back gate of the intermediate MOSFET to the source wiring through the back gate and source of the first MOSFET.

4. The switch circuit according to claim 3.

6. The second semiconductor region is connected to the source wiring via a resistor.

6. A switch circuit according to claim 2.

7. When a current is generated in the back gate of the second MOSFET, the current is guided to the source wiring through the back gate and source of the first MOSFET.

4. A switch circuit according to claim 1.

8. the plurality of MOSFETs includes an intermediate MOSFET provided between the first MOSFET and the second MOSFET; In the intermediate MOSFET, the back gate and the source are shorted, When a current is generated in the back gate of the intermediate MOSFET, the current is guided to the source wiring through the source of the intermediate MOSFET and the channel of the first MOSFET.

4. A switch circuit according to claim 1.

9. the plurality of MOSFETs includes an intermediate MOSFET provided between the first MOSFET and the second MOSFET; In the intermediate MOSFET, a back gate is not connected to a source, and a back gate of the intermediate MOSFET is connected to a back gate of the first MOSFET; When a current is generated in the back gate of the intermediate MOSFET, the current is guided to the source wiring through the back gate and source of the first MOSFET.

4. A switch circuit according to claim 1.

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