Semiconductor device

Abstract

To solve a problem caused by a stacked structure in which an upper semiconductor chip protrudes from a lower semiconductor chip.SOLUTION: A stack 10 includes a plurality of semiconductor chips 11 stacked with the semiconductor chips 11 being shifted sequentially in the X direction, a wiring board 1 on whose surface the stack 10 is placed, and a silicon chip that is provided in a gap between the underside of the uppermost semiconductor chip 11 and the surface of the wiring board 1 and supports the uppermost semiconductor chip 11, the gap being generated by the vertical shift of the semiconductor chips 11 stacked vertically in the stack 10.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] This embodiment relates to a semiconductor device. [Background technology]

[0002] In a conventional semiconductor device created by stacking and packaging semiconductor chips, multiple thin semiconductor chips 101 are stacked as shown in Fig. 1, electrically connected using wires 102, and sealed with resin. In this package structure, multiple semiconductor chips 101 are stacked in a staircase shape. The upper semiconductor chips are stacked in a state where they protrude beyond the lower semiconductor chips.

[0003] If wiring is performed in this state using wire 102 and bonding is performed for packaging, the pressure from the resin used during bonding will cause a problem of chip cracks K occurring at the boundary where the overlap between the topmost protruding semiconductor chip 101 and the semiconductor chip 101 below it ends, as shown in Figure 2. Also, when electrically connecting the topmost semiconductor chip 101 to the wiring board 103, the wire 102 becomes long because it does not go through the intermediate semiconductor chip 101. This causes the wire 102 to be carried away when the resin is injected, causing contact between the wires 102 and resulting in electrical problems. An example of contact S occurring due to the wire 102 being carried away is shown in Figure 3.

[0004] Patent Document 1 shows a semiconductor device in which upper semiconductor chips are stacked in a state where they protrude from the lower semiconductor chip. This semiconductor device includes a wiring board having a surface, a chip stack provided above the surface and including a first semiconductor chip, a second semiconductor chip provided between the surface and the chip stack, a spacer provided between the surface and the first semiconductor chip, continuously surrounding the second semiconductor chip along the surface, including a material having a thermal conductivity higher than that of silicon, and an insulating sealing layer covering the chip stack. This semiconductor device has the effect of having high reliability.

[0005] Patent Document 2 shows an integrated circuit using through silicon vias (TSVs). The integrated circuit (IC) includes a substrate having a top surface and a bottom surface and a circuit on the top surface, a plurality of bonding pads formed along the periphery of the bottom surface, and a back metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads among the plurality of bonding pads. A first subset of bonding pads among the plurality of bonding pads are electrically coupled to the circuit on the top surface by the through silicon vias (TSVs). The back metal layer (BML) distributes electrical signals provided by the second subset of bonding pads. According to this invention, the TSV wire bonding has the effect of significantly improving the design cycle and manufacturing yield.

[0006] Patent Document 3 discloses a semiconductor device including a first substrate, a plurality of semiconductor chips stacked on the first substrate and electrically connected to each other by through electrodes, and a first metal object arranged outside the plurality of semiconductor chips and connecting a power supply connection part of the semiconductor chip located at the top of the plurality of semiconductor chips to a connection part of the first substrate. This invention provides an effect of providing a semiconductor device in which the potential difference between the topmost and bottommost semiconductor chips is reduced in a multi-chip stacked structure using TSVs.

[0007] In some embodiments, U.S. Patent No. 5,999,133 discloses an apparatus including an ultrasonic on-chip having through silicon vias (TSVs) and an interposer coupled to the ultrasonic on-chip and including vias, the ultrasonic on-chip being coupled to the interposer such that the TSVs in the ultrasonic on-chip are electrically connected to the vias in the interposer. In some embodiments, an apparatus is disclosed including an ultrasonic on-chip having bond pads, an interposer having bond pads and coupled to the ultrasonic on-chip, and wire bonds extending from the bond pads on the ultrasonic on-chip to the bond pads on the interposer.

[0008] As described above, although semiconductor devices in which an upper semiconductor chip is stacked in a state in which it protrudes beyond a lower semiconductor chip have been known in the past, there has been nothing to compensate for the mechanical fragility of this structure.

[0009] In addition, although through-silicon vias (TSVs) are known, their use is to obtain electrical connection, and they have not been used to obtain special effects when applied to semiconductor devices in which an upper semiconductor chip protrudes beyond a lower semiconductor chip. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] JP 2023-129959 A [Patent Document 2] JP 2011-82524 A [Patent Document 3] JP 2017-152648 A [Patent Document 4] Special Publication No. 2021-511750 Summary of the Invention [Problem to be solved by the invention]

[0011] The embodiments of the present invention have been made in consideration of the problems of conventional semiconductor devices as described above, and their purpose is to provide a semiconductor device having a structure in which an upper semiconductor chip is stacked in a state in which it protrudes beyond a lower semiconductor chip, while overcoming the problems that arise from this structure. [Means for solving the problem]

[0012] A semiconductor device according to an embodiment of the present invention is characterized in that it comprises a stack in which a number of semiconductor chips are stacked with sequential shifting in the X direction, a wiring board on which the stack is placed, and a silicon chip that supports the topmost semiconductor chip and is provided in a gap generated by the vertical shifting of the semiconductor chips stacked one above the other in the stack, the gap being between the underside of a topmost semiconductor chip and the surface of the wiring board.

[0013] In a semiconductor device according to an embodiment of the present invention, a silicon through electrode is used as the silicon chip, and the through conductor of this silicon through electrode connects a connection pad provided on the upper surface of the uppermost semiconductor chip and a bonding pad provided on the surface of the wiring substrate.

[0014] In the semiconductor device according to an embodiment of the present invention, the silicon chip is provided in the gap between the underside of the topmost semiconductor chip and the underside of the next topmost semiconductor chip and the surface of the wiring substrate.

[0015] In a semiconductor device according to an embodiment of the present invention, the silicon chip is shaped to fill all of the gaps caused by the misalignment from the underside of the uppermost semiconductor chip to the surface of the wiring substrate.

[0016] In the semiconductor device according to the embodiment of the present invention, the silicon chip is provided with a controller that controls at least a device formed in the uppermost semiconductor chip.

[0017] In the semiconductor device according to the embodiment of the present invention, the stack is characterized in that the multiple semiconductor chips are stacked in a state where they are sequentially shifted also in a Y direction perpendicular to the X direction on a plane.

[0018] A semiconductor device according to an embodiment of the present invention is characterized in that it includes a Y-direction misalignment-accommodating silicon chip that is provided in a gap between the underside of the topmost semiconductor chip and the surface of the wiring substrate, the silicon chip supporting the topmost semiconductor chip, the gap being caused by a Y-direction misalignment of semiconductor chips stacked vertically in the stack.

[0019] In the semiconductor device according to an embodiment of the present invention, a silicon through electrode is used as the Y-direction shift-compatible silicon chip, and a connection pad provided on the upper surface of the uppermost semiconductor chip and a bonding pad provided on the surface of the wiring substrate are connected by the through conductor of the silicon through electrode in this Y-direction shift-compatible silicon chip.

[0020] In the semiconductor device according to the embodiment of the present invention, the silicon chip and the Y-direction misalignment accommodating silicon chip are integrally configured. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a side view of a conventional semiconductor device produced by stacking and packaging semiconductor chips. [Diagram 2] 1 is a side view showing an example of a crack occurring in a conventional semiconductor device produced by stacking and packaging semiconductor chips; [Diagram 3] 1 is a perspective view showing an example in which adjacent wires come into contact with each other in a conventional semiconductor device produced by stacking and packaging semiconductor chips; [Figure 4] 1 is a side view showing a semiconductor device according to a first embodiment of the present invention. [Diagram 5] 1A and 1B are side views showing a comparison between a conventional semiconductor and the semiconductor device according to the first embodiment of the present invention. [Figure 6] FIG. 6 is a side view showing a semiconductor device according to a second embodiment of the present invention. [Figure 7] FIG. 11 is a side view showing a semiconductor device according to a third embodiment of the present invention. [Figure 8]FIG. 13 is a perspective view showing a semiconductor device according to a fourth embodiment of the present invention. [Figure 9] FIG. 13 is a perspective view showing a semiconductor device according to a fifth embodiment of the present invention. [Figure 10] FIG. 13 is a perspective view showing a semiconductor device according to a sixth embodiment of the present invention. [Figure 11] FIG. 13 is a perspective view showing a semiconductor device according to a seventh embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] A semiconductor device according to an embodiment of the present invention will be described below with reference to the accompanying drawings. In each drawing, the same components are given the same reference numerals and duplicated explanations will be omitted. In Fig. 4, the semiconductor device according to this embodiment has a laminate 10 disposed on the surface of a wiring substrate 1 having a required thickness and a rectangular planar shape.

[0023] The stack 10 is formed by stacking a plurality of semiconductor chips 11 in a state where they are shifted in the X direction so that the upper part of the chips protrudes. The number of stacked chips is determined by the specifications of the semiconductor device. In this embodiment, a silicon chip 20 is used to prevent chip cracking K shown in FIG. 2. That is, the silicon chip 20 is provided in a gap between the lower surface of the uppermost semiconductor chip 11 and the surface of the wiring board 1, which is a gap caused by the vertical shift of the semiconductor chips 11 stacked vertically in the stack 10, and supports the uppermost semiconductor chip 11 from the back surface.

[0024] In this embodiment, a silicon through electrode (through silicon via (TSV)) is used as the silicon chip 20. The connection pad 15 provided on the upper surface of the uppermost semiconductor chip 11 and the bonding pad 2 provided on the surface of the wiring substrate 1 are connected by the through conductor 21 of the silicon through electrode. In this embodiment, the through conductor 21 of the silicon through electrode and the bonding pad 2 are connected by a bump 3.

[0025] The above-mentioned configuration can prevent the problem of chip cracks K occurring at the boundary where the overlap between the uppermost protruding semiconductor chip 11 and the underlying semiconductor chip 11 ends. In addition, since the through conductor 21 of the silicon through electrode connects the connection pad 15 provided on the upper surface of the uppermost semiconductor chip 11 and the bonding pad 2 provided on the surface of the wiring board 1 with the wire 16, the length of the wire 16 can be made shorter than that shown in Fig. 2, and the risk of the wire 16 being swept away by the resin and coming into contact with an adjacent wire 16 is reduced.

[0026] 5, the semiconductor device is sealed with an insulating sealing layer made of resin 4 and then covered with a package 5 such as a conductive shielding layer. In the conventional example in which electrical connection was made directly from the top semiconductor chip 101 to the wiring board 103 by wires 102, the package 5 required a distance La for tensioning the wires 102 (FIG. 5(a)). In contrast, the through conductor 21 is embedded in the silicon chip 20, and the distance Lb from the tip of the top protruding semiconductor chip 11 to the silicon chip 20, taking into account the size of the silicon chip 20, is used for wiring, so that La>Lb, and the size of the device can be reduced (FIG. 5(b)).

[0027] FIG. 6 is a diagram showing a second embodiment. The silicon chip 20A of this embodiment is provided in the gap between the lower surface of the uppermost semiconductor chip 11 and the lower surface of the next uppermost semiconductor chip 11 to the surface of the wiring board 1. It can be seen that this embodiment supports the protruding parts of the stack more appropriately. Furthermore, it can be configured as shown in FIG. 7. This silicon chip 20B is shaped to fill all the gaps caused by the misalignment between the lower surface of the uppermost semiconductor chip 11 and the surface of the wiring board. This structure can support the protruding parts of the stack more firmly.

[0028] The silicon chips 20, 20A, and 20B in the first embodiment shown in Fig. 4, the second embodiment shown in Fig. 6, and the third embodiment shown in Fig. 7 are provided with a controller C that controls at least the devices formed on the topmost semiconductor chip 11. When the devices formed on the topmost semiconductor chip 11 are devices that realize memories or other circuits, the devices can be controlled by the controller C. This configuration may also be adopted when devices formed on several layers of semiconductor chips 11 connected to the topmost semiconductor chip 11 are grouped together and can be controlled by a single controller C.

[0029] 8, in the stack, a plurality of semiconductor chips 11 are stacked in a state where they are sequentially shifted in the Y direction perpendicular to the X direction on a plane. In this embodiment, as described above, it is possible to use silicon chips 20 that are sufficient to correspond to the protrusion in the X direction.

[0030] 9, a silicon chip 20 corresponding to the protrusion in the X direction and a silicon chip 50 corresponding to the protrusion in the Y direction are provided. The silicon chip 50 corresponding to the Y direction misalignment is a gap generated by the misalignment in the Y direction of the semiconductor chips stacked vertically in the stack, and is provided in the gap between the lower surface of the uppermost semiconductor chip and the surface of the wiring board, and supports the uppermost semiconductor chip from the back surface.

[0031] The configuration of the sixth embodiment is shown in Fig. 10. The silicon chip 20 and the Y-direction misalignment compliant silicon chip 50 in the fifth embodiment are provided with a controller C that controls devices formed on at least the uppermost semiconductor chip 11.

[0032] The seventh embodiment is shown in Fig. 11. The silicon chip 20 and the silicon chip 50 for Y-direction misalignment have the function of supporting the uppermost semiconductor chip 11, and also employ the through conductors 21 and 51 of the silicon chip. The through conductors of the silicon through electrodes in this silicon chip for Y-direction misalignment connect the connection pads provided on the upper surface of the uppermost semiconductor chip 11 and the bonding pads provided on the surface of the wiring board 1 in the same manner as in Figs. 6 and 7.

[0033] 11 may be integrally configured with the silicon chip 20. In the fourth, fifth, sixth, and seventh embodiments, the silicon chip 20 and / or the silicon chip 50 may be provided in a gap between the lower surface of the uppermost semiconductor chip 11 and the lower surface of the next uppermost semiconductor chip 11 to the surface of the wiring board 1.

[0034] Furthermore, in the fourth, fifth, sixth and seventh embodiments, the silicon chip 20 and / or the Y-direction shift-compatible silicon chip 50 may be shaped to fill all of the gaps caused by the shift from the underside of the uppermost semiconductor chip 11 to the surface of the wiring substrate 1. [Explanation of symbols]

[0035] 1. Wiring board 2 Bonding Pads 3. Bump 4. Resin 5 Package 10 Laminate 11 Semiconductor chips 15 Connection Pads 16 Wire 20 Silicon chip 20A Silicon Tip 20B Silicon Chip 21 Through conductor 50 Y-direction misalignment resistant silicon chip 51 Through conductor 101 Semiconductor Chip 102 Wire 103 Wiring board K Crack S contact

Claims

1. a stack in which a plurality of semiconductor chips are stacked in a state where they are sequentially shifted in the X direction; a wiring board on which the laminate is disposed; and a gap generated by vertical misalignment of the semiconductor chips stacked vertically in the stack, the gap being between the lower surface of the uppermost semiconductor chip and the surface of the wiring substrate, and a silicon chip supporting the uppermost semiconductor chip; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, characterized in that a silicon through electrode is used as the silicon chip, and a through conductor of this silicon through electrode connects a connection pad provided on the upper surface of the uppermost semiconductor chip and a bonding pad provided on the surface of the wiring substrate.

3. 3. The semiconductor device according to claim 2, wherein the silicon chip is provided in a gap between the underside of the uppermost semiconductor chip and the underside of the next uppermost semiconductor chip and the surface of the wiring substrate.

4. 3. The semiconductor device according to claim 2, wherein the silicon chip is shaped to fill all of the gaps caused by the misalignment between the lower surface of the uppermost semiconductor chip and the surface of the wiring board.

5. 3. The semiconductor device according to claim 2, wherein the silicon chip is provided with a controller for controlling at least a device formed on the uppermost semiconductor chip.

6. 2. The semiconductor device according to claim 1, wherein the stacked body has a plurality of semiconductor chips stacked in a state where the semiconductor chips are shifted sequentially in a Y direction perpendicular to the X direction on a plane.

7. A gap is generated by a Y-direction misalignment of the semiconductor chips stacked vertically in the stack, the Y-direction misalignment-accommodating silicon chip being provided in the gap between the lower surface of the uppermost semiconductor chip and the surface of the wiring substrate, and supporting the uppermost semiconductor chip.

7. The semiconductor device according to claim 6, further comprising:

8. 8. The semiconductor device according to claim 7, characterized in that a silicon through electrode is used as the silicon chip compliant with Y-direction misalignment, and a connection pad provided on the upper surface of the uppermost semiconductor chip and a bonding pad provided on the surface of the wiring substrate are connected by a through conductor of the silicon through electrode in the silicon chip compliant with Y-direction misalignment.

9. 7. The semiconductor device according to claim 6, wherein the silicon chip and the Y-direction misalignment accommodating silicon chip are integrally formed.

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