Data processing apparatus

Abstract

To suppress a clock to be used for driving an AD converter and a clock to be used for driving a DA converter from becoming out of synchronization.SOLUTION: A data processing apparatus 1 includes a first distributor 11, a second distributor 12, a third distributor 13, an AD converter, a DA converter, a first digital circuit 16, and a second digital circuit 19. The first distributor 11 synchronizes a plurality of first clocks by receiving inputs of settings for synchronizing the first clocks to be output, and inputs, after the first clocks are synchronized, one of the first clocks to the second distributor 12 and the third distributor 13. The second distributor 12 inputs a second clock synchronized with the first clock input from the first distributor 11 to the AD converter. The third distributor 13 inputs a third clock synchronized with the first clock to the DA converter.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a data processing device. [Background technology]

[0002] Conventionally, a data processing device has been disclosed that acquires an analog signal, converts it into digital data using an AD converter and inputs it to a digital circuit, and also converts data received from the digital circuit into an analog signal using a DA converter and outputs it (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-131097 A Summary of the Invention [Problem to be solved by the invention]

[0004] When the signal handled by the data processing device is a signal that specifies the vehicle's position information, the data accuracy can be improved by matching the timing at which the AD converter processes the signal with the timing at which the DA converter processes the signal.

[0005] In order to match the timing at which the AD converter processes a signal with the timing at which the DA converter processes a signal, the clock used to operate the AD converter and the clock used to operate the DA converter must be synchronized. However, there is a problem in that the clock used to operate the AD converter and the clock used to operate the DA converter may become out of sync due to the temperature characteristics of the DA converter and the clock generation circuit that generates the clock input to the AD converter.

[0006] Therefore, the present invention has been made in consideration of these points, and aims to prevent the clock used to operate the AD converter and the clock used to operate the DA converter from becoming unsynchronized. [Means for solving the problem]

[0007] A data processing device according to a first aspect of the present invention is a data processing device having a first distributor, a second distributor, a third distributor, an AD converter, a DA converter, a first digital circuit, and a second digital circuit, wherein the first distributor synchronizes the multiple first clocks by accepting a setting input to synchronize the multiple first clocks to be output, and after the multiple first clocks are synchronized, inputs any of the multiple first clocks to the second distributor and the third distributor, the second distributor inputs a second clock synchronized with the first clock input from the first distributor to the AD converter, the AD converter converts the input analog signal into digital data in synchronization with the second clock and inputs the digital data to the first digital circuit in synchronization with the second clock, the third distributor inputs a third clock synchronized with the first clock to the DA converter, the DA converter converts the digital data input from the second digital circuit into an analog signal in synchronization with the third clock, and outputs the analog signal converted from the digital data in synchronization with the third clock.

[0008] The first distributor may set a delay amount for each of the plurality of first clocks so that each of the plurality of first clocks has the same change point. The first distributor, the second distributor, and the third distributor may synchronize changing points of the clocks to be output by receiving a setting input for synchronizing the clocks to be output. Effect of the Invention

[0009] According to the present invention, it is possible to prevent clocks used for operation between a plurality of AD converters or a plurality of DA converters from becoming out of synchronization. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 illustrates a configuration of a data processing device. [Diagram 2] FIG. 2 is a timing chart of clocks output from the first distributor, the second distributor, and the third distributor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] [Configuration of data processing device 1] 1 is a diagram showing the configuration of a data processing device 1. The data processing device 1 is a device that, for example, converts an analog signal received from the outside into digital data to perform data processing, and also converts the digital data generated by the data processing into an analog signal to output to the outside.

[0012] As shown in FIG. 1, the data processing device 1 has a first distributor 11, a second distributor 12, a third distributor 13, a first AD converter 14 and a second AD converter 15 as multiple AD converters, a first digital circuit 16, a first DA converter 17 and a second DA converter 18 as multiple DA converters, and a second digital circuit 19.

[0013] For example, when a reference clock generated by a clock generation circuit (not shown) is input, the first distributor 11 generates a new clock based on the input reference clock. The first distributor 11 generates a plurality of first device clocks as a plurality of first clocks and a first reference clock, for example, by dividing the reference clock or by using a PLL (Phase Locked Loop) circuit that generates an oscillation signal based on the reference clock. For example, the frequency of the first device clock is 3840 MHz, and the frequency of the first reference clock is 6 MHz. The first distributor 11 synchronizes the plurality of first device clocks and the plurality of first reference clocks by receiving an input of a setting for synchronizing the plurality of first device clocks and the plurality of first reference clocks to be output.

[0014] For example, the first distributor 11 is provided with an SPI (Serial Peripheral Interface) which is a synchronization setting interface that receives input of parameters from an external device (e.g., a processor) for synchronizing the clocks by adjusting the delay amount of the generated clocks. The first distributor 11 synchronizes the change point of the output clock by receiving setting input for synchronizing the output clock from the outside via the synchronization setting interface.

[0015] Specifically, the first distributor 11 receives input of parameters for adjusting the delay amount of each of the multiple first device clocks via a synchronization setting interface, and sets the delay amount of each of the multiple first device clocks so that the rising edges, which are the change points of each of the multiple first device clocks, have the same timing. For example, the first distributor 11 sets the clock delay amount by writing the input parameters to a register that stores the clock delay amount.

[0016] In addition, the first distributor 11 accepts input of parameters for adjusting the amount of delay of each of the multiple first reference clocks via the synchronization setting interface, and sets the amount of delay of each of the multiple first reference clocks so that the rising edge of each of the multiple first reference clocks and the rising edge of each of the multiple first device clocks have the same timing.

[0017] After the multiple first device clocks and the multiple first reference clocks are synchronized, the first distributor 11 inputs any of the multiple first device clocks and the multiple first reference clocks to the second distributor 12 and the third distributor 13. As shown in FIG. 1 , the first distributor 11 inputs the first device clocks and the first reference clock to the second distributor 12, and inputs the first device clock and the first reference clock synchronized with the first device clock and the first reference clock to the third distributor 13.

[0018] Here, it is assumed that the line length of the line for transmitting the first device clock from the first distributor 11 to the second distributor 12 is equal to the line length of the line for transmitting the first device clock from the first distributor 11 to the third distributor 13. Also, it is assumed that the line length of the line for transmitting the first reference clock from the first distributor 11 to the second distributor 12 is equal to the line length for transmitting the first reference clock from the first distributor 11 to the third distributor 13.

[0019] The second distributor 12 inputs to the multiple AD converters the second device clock and the second reference clock as multiple second clocks synchronized with the first device clock and the first reference clock input from the first distributor 11. First, the second distributor 12 divides the frequency of the first device clock input from the first distributor 11 to generate the second device clock, a fourth device clock having a lower frequency than the second device clock, and a second reference clock having a lower frequency than the second device clock and the fourth device clock. For example, the frequency of the second device clock is 1920 MHz, the frequency of the second reference clock is 6 MHz, the same as the frequency of the first reference clock, and the frequency of the fourth device clock is 240 MHz.

[0020] The second distributor 12 synchronizes the generated clocks. For example, the second distributor 12 is provided with a synchronization setting interface common to the first distributor 11. The second distributor 12 synchronizes the change points of the output clocks by accepting setting inputs for synchronizing the output clocks from the outside via the synchronization setting interface.

[0021] Specifically, the second distributor 12 synchronizes the multiple second device clocks with the first reference clock by accepting input of parameters for synchronizing the multiple second device clocks generated with the first reference clock from the outside via a synchronization setting interface. For example, the second distributor 12 sets the rising edge of the first reference clock and the rising edge of the second device clock to have the same timing.

[0022] Fig. 2 is a diagram showing a timing chart of the clocks output from the first distributor 11, the second distributor 12, and the third distributor 13. As shown in Fig. 2, it can be confirmed that the rising edge of the first reference clock input to the second distributor 12 coincides with the rising edge of the second device clock. Note that in the example shown in Fig. 2, for ease of understanding, a timing chart of a clock having a lower frequency than the actual frequency is shown as the timing chart of each device clock.

[0023] The second distributor 12 synchronizes the multiple second device clocks with the multiple second reference clocks by receiving input of parameters for synchronizing the multiple generated second device clocks with the multiple second reference clocks from the outside via a synchronization setting interface. For example, the second distributor 12 sets the falling edge of the second device clock and the rising edge of the second reference clock to be at the same timing, as shown in FIG. 2.

[0024] The second distributor 12 synchronizes the fourth device clock with the second reference clock by receiving input of parameters for synchronizing the generated fourth device clock with the second reference clock from the outside via the synchronization setting interface. For example, the second distributor 12 sets the falling edge of the fourth device clock and the rising edge of the second reference clock to be at the same timing.

[0025] After clock synchronization is completed, the second distributor 12 inputs any one of the multiple second device clocks and the multiple second reference clocks to the first AD converter 14 and the second AD converter 15. As shown in FIG. 1, the second distributor 12 inputs the second device clock and the second reference clock to the first AD converter 14, and inputs the second device clock and the second reference clock synchronized with the second device clock and the second reference clock to the second AD converter 15.

[0026] Moreover, the second distributor 12 inputs the fourth device clock and the second reference clock to the first digital circuit 16. Here, it is assumed that the line length of the line for transmitting the second device clock from the second distributor 12 to the first AD converter 14 is equal to the line length of the line for transmitting the second device clock from the second distributor 12 to the second AD converter 15. It is also assumed that the line length of the line for transmitting the second reference clock from the second distributor 12 to the first AD converter 14 is equal to the line length of the line for transmitting the second reference clock from the second distributor 12 to the second AD converter 15.

[0027] The first AD converter 14 and the second AD converter 15 convert the analog signal into digital data in synchronization with the second device clock and the second reference clock. For example, the first AD converter 14 and the second AD converter 15 convert the analog signal into digital data by sampling the analog signal using the second device clock. Then, the first AD converter 14 and the second AD converter 15 input the digital data to the first digital circuit 16 in response to detecting the rising timing of the second reference clock. Here, the line length of the line for transmitting the digital data from the first AD converter 14 to the first digital circuit 16 is equal to the line length for transmitting the digital data from the second AD converter 15 to the first digital circuit 16. In this way, the first AD converter 14 and the second AD converter 15 can input the digital data to the first digital circuit 16 at the same timing.

[0028] The first digital circuit 16 acquires the digital data output from the first AD converter 14 and the second AD converter 15 in synchronization with the second reference clock input from the second distributor 12. The first digital circuit 16 performs data processing on the acquired digital data using the fourth device clock input from the second distributor 12.

[0029] The third distributor 13 inputs the third device clock and the third reference clock as the third clocks synchronized with the first device clock and the first reference clock input from the first distributor 11 to the multiple DA converters. First, the third distributor 13 generates the third device clock, the fifth device clock having a lower frequency than the third device clock, and the third reference clock having a lower frequency than the third device clock and the fifth device clock based on the first device clock input from the first distributor 11. The frequency of the third reference clock is the same as the frequency of the first reference clock. For example, the frequency of the third device clock is 3840 MHz, the frequency of the third reference clock is 6 MHz, the same as the frequency of the first reference clock, and the frequency of the fifth device clock is 240 MHz.

[0030] The third distributor 13 synchronizes the generated clocks. For example, the third distributor 13 is provided with a synchronization setting interface common to the first distributor 11. The third distributor 13 synchronizes the change point of the output clock by accepting a setting input for synchronizing the output clock from the outside via the synchronization setting interface.

[0031] Specifically, the third distributor 13 synchronizes the multiple third device clocks with the first reference clock by accepting input of parameters for synchronizing the multiple third device clocks generated with the first reference clock from the outside via a synchronization setting interface. For example, as shown in Fig. 2, the third distributor 13 sets the rising edge of the first reference clock and the rising edge of the third device clock to have the same timing.

[0032] The third distributor 13 synchronizes the multiple third device clocks with the multiple third reference clocks by receiving input of parameters for synchronizing the multiple generated third device clocks with the multiple third reference clocks from the outside via a synchronization setting interface. For example, the third distributor 13 sets the falling edge of the third device clock and the rising edge of the third reference clock to have the same timing, as shown in Fig. 2. Here, the first distributor 11, the second distributor 12, and the third distributor 13 may be cascade-connected, and the clocks generated by the first distributor 11, the second distributor 12, and the third distributor 13 may be synchronized at the same time.

[0033] The third distributor 13 synchronizes the fifth device clock with the third reference clock by accepting input of parameters for synchronizing the generated fifth device clock with the third reference clock from the outside via the synchronization setting interface. For example, the third distributor 13 sets the falling edge of the fifth device clock and the rising edge of the third reference clock to be at the same timing.

[0034] After clock synchronization is completed, the third distributor 13 inputs any one of the multiple third device clocks and the multiple third reference clocks to the first DA converter 17 and the second DA converter 18. As shown in Fig. 1, the third distributor 13 inputs the third device clock and the third reference clock to the first DA converter 17, and inputs the third device clock and the third reference clock synchronized with the third device clock and the third reference clock to the second DA converter 18.

[0035] Moreover, the third distributor 13 inputs the fifth device clock and the third reference clock to the second digital circuit 19. Here, it is assumed that the line length of the line for transmitting the third device clock from the third distributor 13 to the first DA converter 17 is equal to the line length of the line for transmitting the third device clock from the third distributor 13 to the second DA converter 18. It is also assumed that the line length of the line for transmitting the third reference clock from the third distributor 13 to the first DA converter 17 is equal to the line length of the line for transmitting the third reference clock from the third distributor 13 to the second DA converter 18.

[0036] The first DA converter 17 and the second DA converter 18 convert the digital data input in synchronization with the third reference clock in the second digital circuit 19 into an analog signal using a third device clock in synchronization with the third reference clock. Then, the first DA converter 17 and the second DA converter 18 output the converted analog signal in synchronization with the third reference clock to an external device such as an antenna. Here, the line length of the line for transmitting digital data from the second digital circuit 19 to the first DA converter 17 is equal to the line length for transmitting digital data from the second digital circuit 19 to the second DA converter 18. In this way, the first DA converter 17 and the second DA converter 18 can convert the digital data acquired from the second digital circuit 19 into analog data and output it at the same timing.

[0037] [Advantages of the data processing device 1 according to the present embodiment] As described above, the first distributor 11 of the data processing device 1 according to the present embodiment synchronizes the first clocks by receiving an input of a setting for synchronizing the first device clock and the first reference clock as the first clocks to be output, and inputs any one of the first clocks to the second distributor 12 and the third distributor 13 after the first clocks are synchronized. Then, the second distributor 12 of the data processing device 1 inputs the second device clock and the second reference clock as the second clock synchronized with the first clock input from the first distributor 11 to the first AD converter 14 and the second AD converter 15, and the third distributor 13 inputs the third device clock and the third reference clock as the third clock synchronized with the first clock to the first DA converter 17 and the second DA converter 18. This allows the data processing device 1 to prevent the clocks used to operate the first AD converter 14 and the second AD converter 15 from becoming out of sync with the clocks used to operate the first DA converter 17 and the second DA converter 18.

[0038] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments, and various modifications and changes are possible within the scope of the gist of the present invention. For example, all or part of the device can be configured by distributing or integrating functionally or physically in any unit. In addition, new embodiments resulting from any combination of multiple embodiments are also included in the embodiments of the present invention. The effect of the new embodiment resulting from the combination combines the effect of the original embodiment. [Explanation of symbols]

[0039] 1 Data Processing Device 11 1st distributor 12 2nd distributor 13 Third distributor 14 1st AD converter 15 2nd AD converter 16 First Digital Circuit 17 1st DA converter 18 Second DA converter 19 Second Digital Circuit

Claims

1. A data processing device having a first divider, a second divider, a third divider, an AD converter, a DA converter, a first digital circuit, and a second digital circuit, the first distributor synchronizes the plurality of first clocks by receiving a setting input for synchronizing the plurality of first clocks to be output, and after the plurality of first clocks are synchronized, inputs any one of the plurality of first clocks to the second distributor and the third distributor; the second distributor inputs a second clock, which is synchronized with the first clock input from the first distributor, to the AD converter; the AD converter converts an input analog signal into digital data in synchronization with the second clock, and inputs the digital data to the first digital circuit in synchronization with the second clock; the third distributor inputs a third clock synchronized with the first clock to the DA converter; the DA converter converts the digital data input from the second digital circuit into an analog signal in synchronization with the third clock, and outputs the analog signal obtained by converting the digital data in synchronization with the third clock. Data processing device.

2. The first distributor sets a delay amount for each of the plurality of first clocks so that each of the plurality of first clocks has the same change point.

2. A data processing apparatus according to claim 1.

3. the first distributor, the second distributor, and the third distributor receive a setting input for synchronizing the clocks to be output, thereby synchronizing change points of the clocks to be output; 3. A data processing device according to claim 1 or 2.

Images