Semiconductor structure and manufacturing method thereof

Abstract

To provide a semiconductor structure and a manufacturing method thereof.SOLUTION: A semiconductor structure includes: a substrate having a cell area and a terminal area, and having a first surface, a second surface positioned in the terminal area, and a third surface positioned in the cell area, facing the first surface, the second surface and the third surface being adjacent to each other, and positioned at different levels; a first trench structure positioned in the cell area, extending toward the first surface across the third surface, including a first semiconductor material layer and a first oxide layer partially projecting from the third surface, and extending toward a first direction that is parallel to the third surface; and a second trench structure positioned in the cell area, including a second semiconductor material layer and a second oxide layer partially projecting from the third surface, and extending in parallel to the first direction. A dope area is provided between the first trench structure and the second trench structure of the third surface, and the dope area extends in parallel to the third surface and toward a second direction that is vertical to the first direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to semiconductor structures and methods for fabricating the same, and more particularly to trench metal-oxide-semiconductor (MOS) structure rectifying devices and methods for fabricating the same. [Background technology]

[0002] Modern power circuits must have rectifiers with high power output, low loss and fast switching. For high voltage applications, wherever high breakdown voltage and high operating temperature are required, PN junction gate rectifiers with high switching speed are adopted. For low voltage applications, wherever high switching speed and very low forward bias are required, Schottky barrier rectifiers are adopted. Schottky barrier rectifiers are multiple carrier devices that operate on a metal oxide semiconductor (MOS) process and only allow a very small reverse leakage current to flow during the recovery process. Unfortunately, when operating at high temperatures, Schottky barrier rectifiers suffer from high reverse leakage currents that are not desirable to appear.

[0003] A series of currently employed refinements have improved the blocking capability of Schottky rectifiers. One such refinement utilizes the Junction Barrier Schottky (JBS) rectifier, which combines a P / N junction gate with a Schottky barrier region that is small enough to extend the space charge region away from the PN junction gate, thus eliminating the lowering of the Schottky barrier caused by Miller charge.

[0004] Another method for improving this type of device is to use Schottky Barrier Diodes (SBDs), which have a relatively low forward voltage and are favorable for forward power loss. However, SBDs also have a relatively high reverse leakage current, which leads to a relatively high reverse power loss, and is therefore a technical bottleneck for this type of device.

[0005] Therefore, there is a need for further improvements in the current state of the art rectifier devices so that they can achieve more ideal high output and low loss and be applicable to high speed switching applications. Summary of the Invention

[0006] An embodiment of the present disclosure relates to a semiconductor structure, the semiconductor structure comprising: a substrate defined, in a top view, as having a cell area and an end area adjacent to the cell area, the substrate having a first surface, a second surface opposite the first surface and located in the end area, and a third surface opposite the first surface and located in the cell area, the second and third surfaces being adjacent to each other and located at different levels; and a first trench structure located in the cell area and extending across the third surface towards the first surface, the first trench structure including a first layer of semiconductor material at least partially protruding beyond the third surface and a first oxide layer surrounding the first semiconductor material, the third surface and The semiconductor device includes a first trench structure extending in a parallel first direction, and a second trench structure located in the cell area and extending across the third surface to the first surface, the second trench structure including a second semiconductor material layer at least partially protruding from the third surface and a second oxide layer surrounding the second semiconductor material, and extending parallel to the first direction, and a first doped area is provided on the third surface of the substrate, the first doped area being located between the first trench structure and the second trench structure when viewed from a bird's-eye view angle, and the first doped area extends in a second direction parallel to the third surface and perpendicular to the first direction.

[0007] An embodiment of the present disclosure relates to a method for fabricating a semiconductor structure, the method including forming first, second and third trenches in a substrate, the first and second trenches being spaced apart along a first direction and extending from a second surface toward a first surface opposite the second surface, the substrate being defined in a top view as having a cell area and an edge termination area, the first and second trenches being located in the cell area and the third trench being located in the edge termination area, forming a first oxide layer in the first trench and a second oxide layer in the second trench. and forming a third oxide layer in the third trench; forming a first semiconductor material layer in the first trench such that the first semiconductor material layer is surrounded by the first oxide layer and forms a first trench structure; forming a second semiconductor material layer in the second trench such that the second semiconductor material layer is surrounded by the second oxide layer and forms a second trench structure; and forming a third semiconductor material layer in the second trench such that the third semiconductor material layer is surrounded by the third oxide layer and forms a third trench structure. forming a layer in the third trench; forming a shielding layer over the cell area, the first trench structure and the second trench structure; performing an etching process on the shielding layer to form a first opening and a second opening, the first opening extending along a first direction to at least partially expose the first semiconductor material layer and the second opening extending along a second direction perpendicular to the first direction to at least partially expose the second surface and the first trench structure; performing a second etching process on the second opening after the first etching process to form a third surface in the substrate and cause the first trench structure and the second trench structure to at least partially protrude from the third surface of the cell area; and forming a first doped area on the exposed third surface near the second opening, the first doped area being located between the first trench structure and the second trench structure and extending toward the second direction when viewed from a bird's-eye view angle.

[0008] Certain exemplary aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings, in which it is noted that the various features may not be drawn to scale, and in fact the dimensions of the various features may be arbitrarily increased or decreased for clarity of illustration. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a top view of a semiconductor structure in accordance with certain embodiments of the present application. [Diagram 2] 2 is a cross-sectional view of a semiconductor structure taken along line A-A' shown in FIG. 1 in accordance with certain embodiments of the present application. [Diagram 3] 2 is a cross-sectional view of a semiconductor structure taken along line BB' shown in FIG. 1 according to certain embodiments of the present application. [Figure 4] 2 is a cross-sectional view of a semiconductor structure taken along line CC' shown in FIG. 1 according to certain embodiments of the present application. [Diagram 5] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 6] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 7] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 8] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 9] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 10] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 11] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 12]1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 13] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 14] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 15] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 16] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 17] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 18] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 19] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 20] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 21] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 22] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 23] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Figure 24] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. [Diagram 25] 1 illustrates one or more steps in a method for manufacturing a semiconductor structure in accordance with certain embodiments of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The same or similar components are designated using like reference numerals in the drawings and detailed description, and the following detailed description, when taken in conjunction with the accompanying drawings, can provide a ready understanding of certain embodiments of the present disclosure.

[0011] The following disclosure provides numerous different embodiments or examples for implementing different features of the provided targets. Specific examples of components and arrangements are described below. Of course, they are merely exemplary and are not intended to be limiting. In this disclosure, a reference to forming a first feature above or on a second feature can include an embodiment in which the first feature and the second feature are formed so that they are in direct contact, and can also include an embodiment in which another feature is formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. In addition, the present disclosure may repeat the numerals and / or letters of the accompanying drawings in each embodiment. Such repetition is for simplicity and clarity, and does not in itself indicate a relationship between each embodiment and / or arrangement discussed.

[0012] In the following, examples of the present disclosure are discussed in detail. However, it should be understood that the present disclosure provides numerous application concepts that can be embodied in a wide variety of specific environments. The specific examples discussed are illustrative only and are not intended to limit the scope of the present disclosure.

[0013] The present disclosure provides a semiconductor structure and a method for manufacturing the same. In the semiconductor structure of the present disclosure, the extension direction of the channel is perpendicular to the extension direction of the trench structure, and the channel pitch can be adjusted according to the process capability, so that the channel density can be increased to improve the current density and the uniformity of the electric field, thereby reducing the reverse leakage current.

[0014] FIG. 1 shows a top view of a semiconductor structure 10 according to certain embodiments of the present application. FIG. 2 shows a cross-sectional view of the semiconductor structure 10 according to certain embodiments of the present application along line A-A'. FIG. 3 shows a cross-sectional view of the semiconductor structure 10 according to certain embodiments of the present application along line B-B'. FIG. 4 shows a cross-sectional view of the semiconductor structure 10 according to certain embodiments of the present application along line C-C'. Specifically, the semiconductor structure 10 is a trench-type MOS rectifier device structure with a vertical current conduction path. For example, the current of the semiconductor structure 10 can be conducted vertically through the semiconductor structure 10.

[0015] In one set of embodiments, the semiconductor structure 10 includes a substrate 11 , a first trench structure 21 , and a second trench structure 22 .

[0016] In one set of embodiments, the substrate 11 includes a substrate 111 and an epitaxial layer 112 disposed on the substrate 111. In one set of embodiments, the substrate 111 includes, for example, silicon, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaAsP), or other semiconductor material. In one set of embodiments, the epitaxial layer 112 includes, for example, silicon, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaAsP), or other semiconductor material. The substrate 111 is an N-type or P-type semiconductor material. The epitaxial layer 112 is an N-type or P-type semiconductor material. In one set of embodiments, substrate 111 and epitaxial layer 112 have the same conductivity type, for example, substrate 111 and epitaxial layer 112 are both N-type.

[0017] The substrate 111 has the same conductivity type doping as the epitaxial layer 112. In one set of embodiments, the substrate 111 is part of a silicon substrate or a silicon wafer. In one set of embodiments, the doping concentration of the substrate 111 is greater than the doping concentration of the epitaxial layer 112.

[0018] In one set of embodiments, the substrate 11 is defined as having a cell area A1 from a top view and a termination area A3 adjacent the cell area. The cell area A1 is used to house active or passive devices, and the termination area A3 is used to connect to a circuit termination. In one set of embodiments, the termination area A3 is adjacent to one side of the cell area A1. In one set of embodiments, the termination area A3 surrounds the cell area A1. In one set of embodiments, the substrate 11 has a first thickness T1 at the cell area A1 and a second thickness T3 at the termination area A3, the second thickness T3 being greater than the first thickness.

[0019] In a series of embodiments, the substrate 11 may have a first surface 12A, a second surface 12B facing the first surface 12A and located in the termination area A3, and a third surface 12C facing the first surface 12A and located in the cell area A1, the second surface 12B and the third surface 12C being adjacent to each other and located at different levels. In a series of embodiments, the second surface 12B and the first surface 12A may be located on opposite sides of the substrate 11. In a series of embodiments, the first surface 12A, the second surface 12B, and the third surface 12C may be horizontal planes. For ease of explanation, a direction perpendicular to the first surface 12A, the second surface 12B, and the third surface 12C is defined as a vertical direction Z, and a plane formed by the first direction X and the second direction Y is perpendicular to the vertical direction Z. In a series of embodiments, the third surface 12C may be an active surface of the epitaxial layer 112. The bottom surface of the substrate 111 is a first surface 12A that can be used to contact a metal layer (not shown in the accompanying drawings, but which can be formed in contact with the substrate 111 on the first surface 12A and can be a drain or a cathode).

[0020] In one set of embodiments, the first trench structure 21 is located in the cell area A1 and extends across the third surface 12C toward the first surface 12A. The first trench structure 21 includes a first semiconductor material layer 212 at least partially protruding from the third surface 12C and a first oxide layer 211 surrounding the first semiconductor material layer 212. In one set of embodiments, the top surface and the second surface 12B of the first trench structure 21 are coplanar. From a bird's-eye view angle, the first trench structure 21 extends along the third surface 12C in the first direction X.

[0021] The first oxide layer 211 is used to electrically isolate the first semiconductor material layer 212 and the epitaxial layer 112. In other words, the first semiconductor material layer 212 is isolated from the epitaxial layer 112 via the first oxide layer 211 in the trench. In one set of embodiments, the sidewalls and the bottom wall of the first semiconductor material layer 212 are in contact with the first oxide layer 211. The thickness of the first oxide layer 211 can be adjusted, for example, according to the dimensions or the operating voltage of the first semiconductor material layer 212. For example, the thickness of the first oxide layer 211 is smaller than the width of the first semiconductor material layer 212 in the trench. In one set of embodiments, the first semiconductor material layer 212 includes a polycrystalline silicon material.

[0022] In one set of embodiments, the second trench structure 22 is located in the cell area A1 and extends across the third surface 12C toward the first surface 12A. The second trench structure 22 includes a second semiconductor material layer 222 at least partially protruding from the third surface 12C and a second oxide layer 221 surrounding the second semiconductor material layer 222. In one set of embodiments, the top surface and the second surface 12B of the second trench structure 22 are coplanar. From a top view angle, the second trench structure 22 extends along the third surface 12C in the first direction X. In one set of embodiments, the second trench structure 22 is located between the first trench structure 21 and the termination area A3.

[0023] The second oxide layer 221 is used to electrically isolate the second semiconductor material layer 222 and the epitaxial layer 112. In other words, the second semiconductor material layer 222 is isolated from the epitaxial layer 112 via the second oxide layer 221 in the trench. In one set of embodiments, the second oxide layer 221 surrounds the second semiconductor material layer 222. In one set of embodiments, the sidewalls and the bottom wall of the second semiconductor material layer 222 are in contact with the second oxide layer 221. The thickness of the second oxide layer 221 can be adjusted, for example, according to the dimensions or the operating voltage of the second semiconductor material layer 222. For example, the thickness of the second oxide layer 221 is smaller than the width of the second semiconductor material layer 222 in the trench. In one set of embodiments, the first oxide layer 211 and the second oxide layer 221 include the same material. In one set of embodiments, the first semiconductor material layer 212 and the second semiconductor material layer 222 include the same material. In one set of embodiments, the second semiconductor material layer 222 comprises a polycrystalline silicon material. In one set of embodiments, the depth of the first trench structure 21 is essentially the same as the depth of the second trench structure 22. In one set of embodiments, the width W1 of the first trench structure 21 is essentially the same as the width W2 of the second trench structure 22.

[0024] In one set of embodiments, the semiconductor structure 10 further includes a third trench structure 23. The third trench structure 23 is located in the termination area A3 and extends from the second surface 12B toward the first surface 12A. The third trench structure 23 is located at the outer periphery of the semiconductor structure 10. The third trench structure 23 includes a third semiconductor material layer 232 and a third oxide layer 231 surrounding the third semiconductor material layer 232, and the third trench structure 23 extends in the first direction X. In one set of embodiments, the top surface of the third trench structure 23 and the second surface 12B are coplanar. In one set of embodiments, the top surfaces of the first trench structure 21, the second trench structure 22, and the third trench structure 23 are coplanar. From a bird's-eye view angle, the third trench structure 23 extends along the third surface 12C in the first direction X. In one set of embodiments, the second trench structure 22 is located intermediate the first trench structure 21 and the third trench structure 23 .

[0025] The third oxide layer 231 is used to electrically isolate the third semiconductor material layer 232 and the epitaxial layer 112. In other words, the third semiconductor material layer 232 is isolated from the epitaxial layer 112 via the third oxide layer 231 in the trench. In one set of embodiments, the third oxide layer 231 surrounds the third semiconductor material layer 232. In one set of embodiments, the sidewalls and bottom wall of the third semiconductor material layer 232 are in contact with the third oxide layer 231. The thickness of the third oxide layer 231 can be adjusted, for example, according to the dimensions or operating voltage of the third semiconductor material layer 232. For example, the thickness of the third oxide layer 231 is smaller than the width of the third semiconductor material layer 232 in the trench. In one set of embodiments, the first oxide layer 211 and the third oxide layer 231 include the same material. In one set of embodiments, the first semiconductor material layer 212 and the third semiconductor material layer 232 include the same material. In one set of embodiments, the third semiconductor material layer 232 comprises a polycrystalline silicon material. In one set of embodiments, the depth of the first trench structure 21 is essentially the same as the depth of the third trench structure 23. In one set of embodiments, the width W1 of the first trench structure 21 is essentially the same as the width W3 of the third trench structure 23.

[0026] In a series of embodiments, the semiconductor structure 10 further includes a plurality of trench structures located between the second trench structure 22 and the third trench structure 23, such as a fourth trench structure 24, a fifth trench structure 25, and a sixth trench structure 26. In a series of embodiments, the distance between the third trench structure 23 and the cell area A1 is the longest compared with the distance between the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 and the cell area A1. In a series of embodiments, the third trench structure 23 is located at the outer periphery of the semiconductor structure 10, and the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are located between the second trench structure 22 and the third trench structure 23. In a series of embodiments, the fourth trench structure 24, the fifth trench structure 25 and the sixth trench structure 26 are located in the termination area A3, extend from the second surface 12B toward the first surface 12A, and extend parallel to the first direction X. In a series of embodiments, the structures of the fourth trench structure 24, the fifth trench structure 25 and the sixth trench structure 26 are essentially the same as the third trench structure 23. In a series of embodiments, the top surfaces of the fourth trench structure 24, the fifth trench structure 25 and the sixth trench structure 26 are coplanar with the second surface 12B, respectively. In a series of embodiments, the top surfaces of the third trench structure 23, the fourth trench structure 24, the fifth trench structure 25 and the sixth trench structure 26 are coplanar. When viewed from a bird's-eye view, the fourth trench structure 24, the fifth trench structure 25 and the sixth trench structure 26 each extend in the first direction X along the third surface 12C.

[0027] The first doped area 31 is disposed on the third surface 12C of the substrate 11. From a top view angle, the first doped area 31 is disposed between the first trench structure 21 and the second trench structure 22, and the first doped area 31 extends along the third surface 12C in a second direction Y perpendicular to the first direction X. In one set of embodiments, the semiconductor structure 10 includes a plurality of doped areas disposed between the first trench structure 21 and the second trench structure 22. In one set of embodiments, the first doped area 31 is located above the epitaxial layer 112 and adjacent to the third surface 12C. The first doped areas 31 have different conductivity types. In one set of embodiments, the first doped area 31 has a second conductivity type. In one set of embodiments, the first doped area 31 has a P type, and the epitaxial layer 112 has an N type. In one set of embodiments, the doping concentration of the first doped area 31 is greater than the doping concentration of the epitaxial layer 112. In one set of embodiments, the first doped area 31 comprises a P-type dopant, which may include, for example, boron, aluminum, gallium, indium, etc. In one set of embodiments, the P-type dopant comprised in the first doped area 31 is boron.

[0028] In a series of embodiments, the second doped area 32 is disposed on the third surface 12C of the substrate 11. From a bird's-eye view angle, the second doped area 32 is disposed between the first trench structure 21 and the second trench structure 22, and is adjacent to the first doped area 31. In a series of embodiments, the second doped area 32 is disposed apart from the first doped area 31. The distance D between the second doped area 32 and the first doped area 31 can be adjusted according to needs and process capabilities, and the distance D1 is greater than 0. In a series of embodiments, the second doped area 32 extends in the same direction as the first doped area 31, for example, the second doped area 32 extends in the second direction Y. In a series of embodiments, the second doped area 32 is located above the epitaxial layer 112 and is adjacent to the third surface 12C. The second doped area 32 has a different conductivity type from the epitaxial layer 112, for example, the second doped area 32 has a P type and the epitaxial layer 112 has an N type. The second doped area 32 has the same conductivity type as the first doped area 31, for example, both are P type. In one set of embodiments, the doping concentration of the second doped area 32 is greater than the doping concentration of the epitaxial layer 112. In one set of embodiments, the doping concentration of the second doped area 32 is approximately the same as the doping concentration of the first doped area 31. In one set of embodiments, the second doped area 32 includes a P type dopant, which may be, for example, boron, aluminum, gallium, indium, or the like. In one set of embodiments, the P type dopant included in the second doped area 32 is boron.

[0029] The shielding layer 35 is located in the cell area A1 and on the second surface 12B. In one set of embodiments, the shielding layer 35 is separated from the termination area A3. In one set of embodiments, the shielding layer 35 covers a portion of the first trench structure 21 and a portion of the second trench structure 22. The upper surface of the shielding layer 35 is higher than the first doped area 31 and the second doped area 32. At least a portion of the first semiconductor material layer 212 and at least a portion of the second semiconductor material layer 222 are exposed from the shielding layer 35. At least a portion of the first oxide layer 211 and at least a portion of the second oxide layer 221 are exposed from the shielding layer 35.

[0030] From a bird's-eye view angle, the shielding layer 35 is located between the first doped area 31 and the second doped area 32. In one set of embodiments, the shielding layer 35 includes a first opening 41 and a second opening 42. The first opening 41 extends along a first direction X such that at least a portion of the first semiconductor material layer 212 is exposed, and the second opening 42 extends along a second direction Y perpendicular to the first direction X such that at least a portion of the second surface 12B and the first trench structure 21 are exposed. The first opening 41 and the second opening 42 intersect each other. The first doped area 31 is located in the second opening 42. In one set of embodiments, the shielding layer 35 further includes a third opening 43 extending along a second direction Y perpendicular to the first direction X and exposing at least a portion of the second surface 12B and the first trench structure 21. The third opening 43 is disposed in parallel with the second opening 42 and also intersects with the first opening 41. The second doped area 32 is located in the third opening 43. When viewed from a bird's-eye view angle, the first doped area 31 and the second doped area 32 are disposed between the first trench structure 21 and the second trench structure 22 and are staggered with the shielding layer 35.

[0031] In one set of embodiments, the shielding layer 35 includes a fourth oxide layer 351 and a fourth semiconductor material layer 352 disposed on the fourth oxide layer 351. The fourth oxide layer 351 is disposed on the second surface 12B and covers at least a portion of the first trench structure 21 and at least a portion of the second trench structure 22. The fourth oxide layer 351 contacts the first oxide layer 211 and the second oxide layer 221. In one set of embodiments, the fourth oxide layer 351 is a gate oxide layer. In one set of embodiments, the fourth oxide layer 351 has a thickness of 50 Å to 150 Å. In one set of embodiments, the fourth semiconductor material layer 352 includes a polycrystalline silicon material.

[0032] In one set of embodiments, the substrate 11 further includes a third doped area 33 on the third surface 12C. From a top view angle, the third doped area 33 is located on the periphery of the cell area A1 and extends in the first direction X. In one set of embodiments, the third doped area 33 is located between the second trench structure 22 and the third trench structure 23. In one set of embodiments, the third doped area 33 is located between the second trench structure 22 and the termination area A3. The second trench structure 22 is located between the first doped area 31 and the third doped area 33. In one set of embodiments, the third doped area 33 is located above the epitaxial layer 112 and adjacent to the third surface 12C. The third doped area 33 has a different conductivity type than the epitaxial layer 112, for example, the third doped area 33 has a P type and the epitaxial layer 112 has an N type. The third doped area 33, the second doped area 32 and the first doped area 31 have the same conductivity type, for example, all P type. In one set of embodiments, the doping concentration of the third doped area 33 is greater than the doping concentration of the epitaxial layer 112. In one set of embodiments, the first doped area 31, the second doped area 32 and the third doped area 33 are heavily doped areas. In one set of embodiments, the first doped area 31, the second doped area 32 and the third doped area 33 are bulk doped areas. In one set of embodiments, the doping concentration of the first doped area 31, the doping concentration of the second doped area 32 and the doping concentration of the third doped area 33 are substantially the same. In one set of embodiments, the third doped area 33 includes a P-type dopant, which may be, for example, boron, aluminum, gallium, indium, etc. In one set of embodiments, the P-type dopant included in the third doped area 33 is boron. The width W5 of the third doped area 33 may be the same as or different from the width W4 of the first doped area 31. In one set of embodiments, the width W5 of the third doped area 33 is essentially the same as the width W4 of the first doped area 31.

[0033] In one set of embodiments, the third doped area 33 is a first mesa surface between the cell area A1 and the termination area A3. In one set of embodiments, the first mesa surface separates the second trench structure 22 in the cell area A1 from the third trench structure 23 in the termination area A3. The width D2 of the first mesa surface can be adjusted by the positions of the second trench structure 22 and the third trench structure 23. In one set of embodiments, the width D2 of the first mesa surface can be adjusted by the positions of the second trench structure 22 and the fourth trench structure 24.

[0034] The semiconductor structure 10 further includes a conductive layer 38 for electrically connecting the first trench structure 21 and the second trench structure 22. The conductive layer 38 is disposed above the first doped area 31 and above the second doped area 32, and covers at least a portion of the shielding layer 35. The conductive layer 38 is further disposed in the first opening 41, the second opening 42, and the third opening 43, and is electrically connected to the first semiconductor material layer 212 and the second semiconductor material layer 222. In one set of embodiments, the conductive layer 38 extends along the sidewall of the shielding layer 35 and contacts and is electrically connected to the first semiconductor material layer 212 and the second semiconductor material layer 222. In one set of embodiments, the conductive layer 38 contacts and is electrically connected to a portion of the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26. In one set of embodiments, the conductive layer 38 includes a conductive material, for example, a metal, and may be, but is not limited to, copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), titanium nitride (TiN), aluminum-silicon alloy (AlSi), aluminum-silicon copper (AlSiCu) alloy, or other metals or alloys. In one set of embodiments, the portion of the conductive layer 38 surrounded by the shielding layer 35 becomes a conductive plug 383. In one set of embodiments, the conductive plug 383 has a columnar structure and has essentially the same width along the vertical direction Z. In one set of embodiments, the conductive plug 383 has a structure that is wide at the top and narrow at the bottom, and the width of the conductive plug 383 has a tendency to decrease along the vertical direction Z of the conductive layer 38 toward the first surface 12A.

[0035] In one set of embodiments, the conductive layer 38 includes a first conductive layer 381 disposed on the shielding layer 35, extending along the sidewall of the shielding layer 35, and in contact with the first semiconductor material layer 212 and the second semiconductor material layer 222. In one set of embodiments, the first conductive layer 381 is a seed layer. The conductive layer 38 includes a second conductive layer 382 disposed on the first conductive layer 381, extending along the sidewall of the first conductive layer 381, and in contact with the first semiconductor material layer 212 and the second semiconductor material layer 222.

[0036] In one set of embodiments, the conductive layer 38 is disposed in the cell area A1 and the termination area A3. The conductive layer 38 is disposed above the third doped area 33. The semiconductor structure 10 further includes a fifth oxide layer 37 disposed between the third trench structure 23 and the conductive layer 38. The fifth oxide layer 37 is disposed in the termination area A3 and is located on the second surface 12B. In one set of embodiments, the fifth oxide layer 37 is disposed above the third trench structure 23, the fourth trench structure 24, the fifth trench structure 25 and the sixth trench structure 26. In one set of embodiments, the conductive layer 38 is disposed above the first doped area 31, above the second doped area 32 and above the fifth oxide layer 37. In one set of embodiments, at least a portion of the fourth trench structure 24, the fifth trench structure 25 and the sixth trench structure 26 is exposed from the fifth oxide layer 37 and is in contact with the conductive layer 38 to be electrically connected. In one set of embodiments, the conductive layer 38 is electrically connected to the fourth trench structure 24, the fifth trench structure 25 and the sixth trench structure 26 across the fifth oxide layer 37. In one set of embodiments, an edge 371 of the fifth oxide layer 37 is exposed from the conductive layer 38.

[0037] In one set of embodiments, the third trench structure 23 is covered by a fifth oxide layer 37. In one set of embodiments, the fifth oxide layer 37 is located between the third trench structure 23 and the conductive layer 38 and electrically isolates the third trench structure 23 from the conductive layer 38. The third trench structure 23 is located at the periphery of the semiconductor structure 10 and is floated or dummy to prevent the expansion of a depletion region when the semiconductor structure 10 is reverse biased.

[0038] In the case of forward voltage, as shown by the arrows in Figs. 1 and 4, the current flows from the conductive layer 38 disposed in the second opening 42 into the first doped area 31, from the first doped area 31 into the epitaxial layer 112, and from the third surface 12C toward the first surface 12A. In the case of forward voltage, the current also flows from the conductive layer 38 disposed in the third opening 43 into the second doped area 32, from the second doped area 32 into the epitaxial layer 112, and from the third surface 12C toward the first surface 12A. In one set of embodiments, the active surface of the semiconductor structure 10 is the third surface 12C. The current of the semiconductor structure 10 can flow in a direction perpendicular to the active surface of the semiconductor structure 10. In one set of embodiments, the current of the semiconductor structure 10 flows along a vertical direction Z.

[0039] In one set of embodiments, the first doped area 31 and the second doped area 32 respectively form a second mesa surface between the first trench structure 21 and the second trench structure 22. In one set of embodiments, the width of the second mesa surface can be adjusted by the positions of the first trench structure 21 and the second trench structure 22. The first trench structure 21 and the second trench structure 22 can reduce the electric field at the second mesa surface, thereby reducing the reverse leakage current of the semiconductor structure 10, and since the extension direction of the channel is perpendicular to the extension direction of the first trench structure 21 and the second trench structure 22, the channel position can be adjusted by the process (e.g., the channel can be made narrower) to further reduce the forward voltage and increase the channel density to increase the current density.

[0040] 5 through 25 illustrate one or more steps in a method for fabricating a semiconductor structure according to certain embodiments of the present application, at least some of which have been simplified to provide a better understanding of aspects of the present disclosure.

[0041] 5 and 6, the substrate 11 may include a base material 111 and an epitaxial layer 112 located on the base material 111. The manufacturing method includes epitaxially growing the base material 111 to form the epitaxial layer 112. The base material 111 has a first surface 12A of the substrate 11, and the epitaxial layer 112 has a second surface 12B of the substrate 11, with the first surface 12A facing the second surface 12B. In one set of embodiments, ions are implanted simultaneously with the epitaxial growth, and ions having N-type electrical properties are implanted to form the N-type epitaxial layer 112.

[0042] A patterned shielding layer 113 (hereinafter collectively referred to as a first shielding layer) shown in FIG. 5 is formed on the epitaxial layer 112 to define the positions of the first trench 210, the second trench 220, and the third trench 230 shown in FIG. 6, and an etching process (e.g., a plasma dry etching process) is performed on the epitaxial layer 112 through the first shielding layer 113 to form the first trench 210, the second trench 220, and the third trench 230. The etching process needle removes the epitaxial layer 112 from the second surface 12B and stops in the epitaxial layer 112. According to the positions defined by the first shielding layer 113, the first trench 210, the second trench 220, and the third trench 230 are formed in the substrate 11 at a distance from each other and extend along a first direction X from the second surface 12B toward the first surface 12A opposite the second surface. The first trench 210 and the second trench 220 are formed in a cell area A1 of the substrate 11, and the third trench 230 is formed in a termination area A3 of the substrate 11.

[0043] In one set of embodiments, the first trench 210, the second trench 220, and the third trench 230 may have vertical sidewalls. The first trench 210, the second trench 220, and the third trench 230 may have an arc-shaped bottom. The first trench 210, the second trench 220, and the third trench 230 may be circular, elliptical, rectangular, or polygonal. In one set of embodiments, the first trench 210, the second trench 220, and the third trench 230 have the same width. In one set of embodiments, the first trench 210, the second trench 220, and the third trench 230 have the same depth. In one set of embodiments, the fourth trench 240, the fifth trench 250, and the sixth trench 260 are formed in the substrate 11 at a distance from each other and extend along the first direction X from the second surface 12B toward the first surface 12A opposite the second surface. The fourth trench 240 , the fifth trench 250 and the sixth trench 260 are located between the second trench 220 and the third trench 230 .

[0044] 7, the method includes forming an in-trench oxide layer 219 in the first trench 210, the second trench 220, and the third trench 230. In one set of embodiments, the in-trench oxide layer 129 covers the second surface 12B. In one set of embodiments, the in-trench oxide layer 219 can be formed by a thermal oxidation technique or other deposition process. In one set of embodiments, the in-trench oxide layer 219 can be conformally or conformally deposited on the inner surfaces (including the opposing sidewalls and the bottoms extending between the sidewalls) of the first trench 210, the second trench 220, and the third trench 230. In one set of embodiments, the in-trench oxide layer 219 can be filled into the first trench 210, the second trench 220, and the third trench 230 by a deposition process such that the in-trench oxide layer 219 forms at least one recess in the first trench 210, the second trench 220, and the third trench 230, respectively. In one set of embodiments, the trench oxide layer 129 is a first oxide layer 211 in the first trench 210, a second oxide layer 221 in the second trench 220, and a third oxide layer 231 in the third trench 230. The first oxide layer 211, the second oxide layer 221, and the third oxide layer 231 are formed simultaneously.

[0045] 8, the method includes forming a first semiconductor material 215, a second semiconductor material 225, and a third semiconductor material 235 in a first trench 210, a second trench 220, and a third trench 230, respectively. In one set of embodiments, the first semiconductor material 215 is disposed in the first trench 210 and on a top surface of the first oxide layer 211, the second semiconductor material 225 is disposed in the second trench 220 and on a top surface of the second oxide layer 221, and the third semiconductor material 235 is disposed in the third trench 230 and on a top surface of the third oxide layer 231.

[0046] The trench oxide layer 219 may surround the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235. In one set of embodiments, the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235 may be formed by physical vapor deposition (PVD), such as sputtering or spray coating. In one set of embodiments, the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235 may be formed by electroplating or CVD. In one set of embodiments, the semiconductor material may cover the trench oxide layer 219, and then a dry etching process may be performed to remove, for example, by etching, the semiconductor material outside the first trench 210, the second trench 220, and the third trench 230 to form the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235. In one set of embodiments, the semiconductor material includes polycrystalline silicon.

[0047] 9, the manufacturing method includes forming a first semiconductor material layer 212, a second semiconductor material layer 222 and a third semiconductor material layer 232 in the first trench 210, the second trench 220 and the third trench 230, respectively, such that the first semiconductor material layer 212 is surrounded by a first oxide layer 211 and forms a first trench structure 21, the second semiconductor material layer 222 is surrounded by a second oxide layer 221 and forms a second trench structure 22, and the third semiconductor material layer 232 is surrounded by a third oxide layer 231 and forms a third trench structure 23. In one set of embodiments, the top surfaces of the first semiconductor material layer 212, the second semiconductor material layer 222 and the third semiconductor material layer 232 are essentially coplanar with the second surface 12B.

[0048] In one set of embodiments, the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235 are etched to form the first semiconductor material layer 212, the second semiconductor material layer 222, and the third semiconductor material layer 232, respectively. The etching process removes at least a portion of the first semiconductor material 215 in the first trench 210, at least a portion of the second semiconductor material 225 in the second trench 220, and at least a portion of the third semiconductor material 235 in the third trench 230. The first semiconductor material layer 212, the second semiconductor material layer 222, and the third semiconductor material layer 232 are defined by a second blocking layer (not shown) and are formed by performing a dry etching process. The dry etching process removes a portion of the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235, and stops at a predetermined depth of the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235.

[0049] For ease of discussion, the first semiconductor material layer 212 and the first oxide layer 211 are collectively referred to as the first trench structure 21, the second semiconductor material layer 222 and the second oxide layer 221 are collectively referred to as the second trench structure 22, and similarly, the third semiconductor material layer 232 and the third oxide layer 231 are collectively referred to as the third trench structure 23. The first trench structure 21, the second trench structure 22, and the third trench structure 23 are formed simultaneously. In one set of embodiments, the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are formed simultaneously with the first trench structure 21, the second trench structure 22, and the third trench structure 23.

[0050] In one set of embodiments, an oxide layer 370 is formed on the third trench structure 23 such that the oxide layer 370 covers the third trench structure 23. Referring to FIG. 10, the manufacturing method includes forming an oxide layer 370 on the first trench structure 21, the second trench structure 22 and the third trench structure 23. In one set of embodiments, the oxide layer 370 is formed on the in-trench oxide layer 219 and covers the first trench structure 21, the second trench structure 22 and the third trench structure 23. The oxide layer 370 contacts the first semiconductor material layer 212, the second semiconductor material layer 222 and the third semiconductor material layer 232. In one set of embodiments, the oxide layer 370 further contacts the semiconductor material layers of the fourth trench structure 24, the fifth trench structure 25 and the sixth trench structure 26.

[0051] The oxide layer 370 and the trench oxide layer 219 can comprise the same or different materials. In one set of embodiments, the oxide layer 370 can be formed by ALD, CVD, or other deposition process. In one set of embodiments, after the oxide layer 370 is formed, a polishing process, such as a CMP process, is performed to polish the top surface of the oxide layer 370 flat.

[0052] 11, the manufacturing method includes removing a part of the oxide layer 370 and a part of the in-trench oxide layer 219 to expose the substrate 11 and the first trench structure 21 and the second trench structure 22 located in the cell area A1. In one set of embodiments, the oxide layer 370 and the in-trench oxide layer 219 are locally removed by photolithography and etching processes. In one set of embodiments, at least a part of the semiconductor material 112 of the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 is exposed from the oxide layer 370, respectively. In one set of embodiments, after removing the part of the oxide layer 370 and the part of the in-trench oxide layer 219, the oxide layer 370 and the in-trench oxide layer 219 are located only in the termination area A3, and the oxide layer 370 covers the in-trench oxide layer 219 and the third trench structure 23, and the second surface 12B of the cell area is exposed. For ease of explanation, in the following, the trench oxide layer 219 and the oxide layer 370 located in the termination area A3 will be collectively referred to as a fifth oxide layer 37.

[0053] The manufacturing method includes forming a shielding layer 35 on the cell area A1, the first trench structure 21 and the second trench structure 22. Referring to FIG. 12, the manufacturing method includes forming a fourth oxide layer 351 on the second surface 12B of the cell area and the fifth oxide layer 37, and forming a fourth semiconductor material layer 352 on the fourth oxide layer 351. The fourth oxide layer 351 and the fifth oxide layer 37 can include the same or different materials. In one set of embodiments, the fourth oxide layer 351 has a thickness less than that of the fifth oxide layer 37. In one set of embodiments, the fourth oxide layer 351 contacts the sidewall of the fifth oxide layer 37, and the fourth semiconductor material layer 352 contacts the sidewall and top surface of the fifth oxide layer 37. In one set of embodiments, the fourth oxide layer 351 can be formed by a thermal oxidation technique or other deposition process. In one set of embodiments, the fourth semiconductor material layer 352 can be formed by PVD, for example sputtering or spray coating. In another set of embodiments, the fourth semiconductor material layer 352 can be formed by electroplating or CVD.

[0054] The manufacturing method includes performing an etching process on the shielding layer 35 to form a first opening 41, a second opening 42, and a third opening 43. FIG. 13 is a top view of a step in the manufacturing method of the semiconductor structure 10 according to certain embodiments of the present application. FIG. 14 is a cross-sectional view of the step shown in FIG. 13 in the manufacturing method of the semiconductor structure according to certain embodiments of the present application along line tangent line A-A'. FIG. 15 is a cross-sectional view of the step shown in FIG. 12 in the manufacturing method of the semiconductor structure according to certain embodiments of the present application along line tangent line B-B'. FIG. 16 is a cross-sectional view of the step shown in FIG. 13 in the manufacturing method of the semiconductor structure according to certain embodiments of the present application along line tangent line C-C'.

[0055] 13 to 16, the manufacturing method includes performing a first etching process on the shielding layer 35 to form a first opening 41 extending along a first direction X to expose at least a part of the first semiconductor material layer 212, and forming an opening 421 and an opening 431 spaced apart from each other and extending along a second direction Y perpendicular to the first direction to expose at least a part of the second surface 12B and the first trench structure 21. The first etching process further includes removing a part of the fourth oxide layer 351 and a part of the fourth semiconductor material layer 352 so that the shielding layer 35 is located only on the cell area A1, the first trench structure 21 and the second trench structure 22, the second surface 12B between the second trench structure 22 and the termination area A3 is exposed, and the fifth oxide layer 37 is also exposed.

[0056] In one set of embodiments, a patterned shielding layer (hereinafter collectively referred to as a third shielding layer) is formed on the fourth semiconductor material layer 352 (not shown). The first opening 41 and the openings 421, 431 are defined by the third shielding layer and can be formed by an etching process that removes the fourth oxide layer 351 and the fourth semiconductor material layer 352 and stops at the second surface 12B or the upper surfaces of the first trench structure 21 and the second trench structure 22. Depending on the location defined by the third shielding layer, the first opening 41 can cover at least a portion of the first semiconductor material layer 212 and the openings 421, 431 can cover the first trench structure 21 and the second surface 12B partially adjacent to the first trench structure 21. In one set of embodiments, the first opening 41 extends downward to the top surface of the first semiconductor material layer 212. In one set of embodiments, the openings 421, 431 extend downwards to the top surface of the first trench structure 21 and to the second surface 12B.

[0057] 17-19, the manufacturing method includes performing a second etching process at the openings 421, 431 after the first etching process to form a third surface 12C in the substrate 11, and to make the first trench structure 21 and the second trench structure 22 at least partially protrude from the third surface 12C of the cell area A1, and to form a second opening 42 and a third opening 43. FIG. 17 is a top view of a step in the manufacturing method of a semiconductor structure according to certain embodiments of the present application. FIG. 18 shows a cross-sectional view along the tangent line A-A' of the step shown in FIG. 17 in the manufacturing method of a semiconductor structure according to certain embodiments of the present application. FIG. 19 shows a cross-sectional view along the tangent line C-C' of the step shown in FIG. 17 in the manufacturing method of a semiconductor structure according to certain embodiments of the present application.

[0058] The manufacturing method includes locally removing the epitaxial layer 112 using the shielding layer 35 as a shield. In one set of embodiments, an etching process is performed on the exposed epitaxial layer 112 using the shielding layer 35 and the fifth oxide layer 37 as a shield. In one set of embodiments, the openings 421, 431 are redefined as the second opening 42 and the third opening 43 by the second etching process. In one set of embodiments, the sidewalls of the second opening 42 and the third opening 43 include the shielding layer 35 and a part of the epitaxial layer 112. In one set of embodiments, the bottoms of the openings 421, 431 in FIG. 12 are higher than or approximately equal to the horizontal height of the bottoms of the second opening 42 and the third opening 43 in FIG. 16. In one set of embodiments, the depths of the second opening 42 and the third opening 43 are greater than the depths of the openings 421, 431.

[0059] After the second etching process, the substrate 11 has a first thickness T1 in the cell area A1 and a second thickness T3 in the termination area A3, the second thickness T3 being greater than the first thickness. In one set of embodiments, the horizontal height of the fifth oxide layer 37 is greater than the horizontal height of the shielding layer 35, and the horizontal height of the shielding layer 35 is greater than the horizontal height of the third surface 12C.

[0060] 20-22, the method includes forming a first doped area 31 on the third surface 12C exposed at the second opening 42, and forming a second doped area 32 on the third surface 12C exposed at the third opening 43. From a bird's-eye view, the first doped area 31 and the second doped area 32 are disposed between the first trench structure 21 and the second trench structure 22, respectively, and extend in the second direction Y. The method further includes forming a third doped area 33 between the cell area A1 and the termination area A3, and the first doped area 31 and the third doped area 33 are separated. From a bird's-eye view, the second trench structure 22 is located between the first doped area 31 and the third doped area 33. FIG. 19 is a top view of a step in a method for manufacturing a semiconductor structure according to certain embodiments of the present application. 20 shows a cross-sectional view taken along line A-A' of the step shown in FIG 18 in a method for fabricating a semiconductor structure according to certain embodiments of the present application. FIG 21 shows a cross-sectional view taken along line B-B' of the step shown in FIG 19 in a method for fabricating a semiconductor structure according to certain embodiments of the present application.

[0061] The first doped area 31, the second doped area 32 and the third doped area 33 can be formed by performing a diffusion or ion implantation process from the third surface 12C. After forming the first doped area 31, the second doped area 32 and the third doped area 33, the first trench structure 21 and the second trench structure 22 at least partially protrude from the first doped area 31, the second doped area 32 and the third doped area 33.

[0062] The depths of the first doped area 31, the second doped area 32 and the third doped area 33 are smaller than the depths of the first trench structure 21 and the second trench structure 22. In other words, the bottoms of the first doped area 31, the second doped area 32 and the third doped area 33 are higher than the bottoms of the first trench structure 21 and the second trench structure 22. In one set of embodiments, the coverage of the first doped area 31, the second doped area 32 and the third doped area 33 is defined as being in the cell area A1 and being the epitaxial layer 112 other than the shielding layer 35, the first trench structure 21 and the second trench structure 22. In one set of embodiments, after the ion implantation process, an annealing process is performed to diffuse the doping ions. In one set of embodiments, the doping ions are, for example, boron ions, aluminum ions, gallium ions, indium ions, etc. In one set of embodiments, boron ions are implanted into the first doped area 31 , the second doped area 32 and the third doped area 33 .

[0063] In a series of embodiments, a patterned shielding layer (hereinafter collectively referred to as the third shielding layer) is formed on the shielding layer 35 and the fifth oxide layer 37 to define the positions of the first doped area 31, the second doped area 32 and the third doped area 33, and to define the conductivity type and depth of the first doped area 31, the second doped area 32 and the third doped area 33 by adjusting the implantation ions, energy and dose of the diffusion or ion implantation process. The ions are implanted into the third surface 12C along the vertical direction Z. In a series of embodiments, the third shielding layer is formed after performing a photolithography process using a photomask having a corresponding pattern. In a series of embodiments, the first doped area 31, the second doped area 32 and the third doped area 33 are respectively formed by performing an annealing process after performing an ion implantation process on the third surface 12C each time to diffuse the doping ions.

[0064] 23 to 25, the manufacturing method includes forming a conductive layer 38 on the first semiconductor material layer 212, the second semiconductor material layer 222, and the third semiconductor material layer 232. The conductive layer 38 can be formed by electroplating or CVD. The material of the conductive layer 38 can include copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), titanium nitride (TiN), aluminum-silicon (AlSi) alloy, aluminum-silicon copper (AlSiCu) alloy, or other metals or alloys. The first trench structure 21 and the second trench structure 22 are electrically connected to the conductive layer 38. In a series of embodiments, the manufacturing method includes further removing a part of the conductive layer 38 at the edge of the termination area A3 to expose the edge 371 of the fifth oxide layer 37 from the conductive layer 38.

[0065] The manufacturing method includes forming a first conductive layer 381 on the shielding layer 35, the third surface 12C, and the fifth oxide layer 37. The first conductive layer 381 extends along a sidewall of the shielding layer 35 and contacts the first semiconductor material layer 212 and the second semiconductor material layer 222. In one set of examples, the first conductive layer 381 includes titanium (Ti).

[0066] The method includes forming a second conductive layer 382 on the first conductive layer 381 and extending along a sidewall of the first conductive layer 381 and in contact with the first semiconductor material layer 212 and the second semiconductor material layer 222. In one set of examples, the second conductive layer 382 includes titanium nitride (TiN).

[0067] The semiconductor structure 10 formed by the above steps can be basically the same as the semiconductor structure 10 shown in Figures 1 to 4. The semiconductor structure 10 has a first doped area 31 and a second doped area 32 disposed between the first trench structure 21 and the second trench structure 22, and the first doped area 31 and the second doped area 32 are spaced apart from each other and extend in a second direction Y parallel to the third surface 12C and perpendicular to the first direction X, thereby achieving the effect of increasing channel density.

[0068] Based on the above-described structures and processes of the present disclosure, under the same purpose and concept, the steps in the above processes can be adjusted or reordered to achieve the same or similar semiconductor structures.

[0069] For ease of description, spatially relative terms such as "below," "lower," "bottom," "upper," "top," "left," "right," and the like may be used herein to describe the relationship of one component or feature to another component or features as depicted in the accompanying drawings. Except for the orientation depicted in the accompanying drawings, the spatially relative terms are also intended to cover different orientations during use or operation of the device. The device may be otherwise oriented (rotated 90 degrees or positioned at other orientations) and the spatially relative terms used herein may be interpreted accordingly. It should be understood that when a component is referred to as "connected" or "coupled" to another component, it may be directly connected or coupled to the other component, or intermediate components may be present.

[0070] As used herein, the terms "approximately," "essentially," "basically," and "about" are used to describe or interpret small variations. When used in conjunction with an event or occurrence, the term can specifically point to instances where the event or occurrence occurred exactly and instances where the event or occurrence will occur in the near future. When used in relation to a given value or range as herein, the term "about" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as ranging from one endpoint to another endpoint or between both endpoints. Unless otherwise specified, all ranges disclosed herein include the endpoints. The term "essentially coplanar" can point to a difference in the positions of two surfaces positioned along the same plane being within a few microns (μm), for example, within 10 μm, 5 μm, 1 μm, or 0.5 μm of the positions positioned along the same plane. When values ​​or characteristics are referred to as being "essentially" the same, the term may refer to values ​​that are within ±10%, ±5%, ±1% or ±0.5% of the mean value of the value. The above disclosure outlines features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure may be readily used as a basis for designing or modifying other processes and structures to carry out the same or similar purposes and / or achieve the same or similar advantages of the embodiments presented herein. Such equivalent structures do not depart from the spirit and scope of the present disclosure, and various modifications, substitutions and alterations may be made without departing from the spirit and scope of the present disclosure. [Explanation of symbols]

[0071] 10 Semiconductor Structure 11 Substrate 12A 1st surface 12B 2nd surface 12C 3rd surface 21 First trench structure 22 Second trench structure 23 Third trench structure 24 4th trench structure 25 5th trench structure 26 6th Trench Structure 31 First Dope Area 32 2nd Dope Area 33 3rd Dope Area 35 Shielding layer 37 Fifth oxide layer 38 Conductive Layer 41 First opening 42 Second Opening 43 Third Opening 111 Base material 112 Semiconductor materials, epitaxial layers 113 Shielding layer, first shielding layer 129 Oxide layer in trench 210 First Trench 211 First oxide layer 212 first semiconductor material layer 215 First Semiconductor Material 219 Oxide layer in trench 220 Second Trench 221 Second oxide layer 222 Second semiconductor material layer 225 Second Semiconductor Materials 230 Trench No. 3 231 Third oxide layer 232 Third semiconductor material layer 235 Third Semiconductor Materials 240 Trench No. 4 250 5th Trench 260 Trench No. 6 351 Fourth oxide layer 352 Fourth semiconductor material layer 370 Oxide layer 371 En 381 First conductive layer 382 Second conductive layer 383 Conductive Plug 421 Aperture 431 Aperture A-A' tangent A1 Cell Area A3 Termination Area B-B' tangent C-C' tangent D Distance D1 Distance MOS Trench Type P GaAs T1 First thickness T3 Second Thickness X 1st direction Y Second direction Z vertical direction

Claims

1. a substrate defined in a top view as having a cell area and an end area adjacent to the cell area, the substrate having a first surface, a second surface opposite to the first surface and located within the end area, and a third surface opposite to the first surface and located within the cell area, the second surface and the third surface being adjacent to each other and located at different levels; a first trench structure located within the cell area and extending across the third surface toward the first surface, the first trench structure including a first semiconductor material layer at least partially protruding from the third surface and a first oxide layer surrounding the first semiconductor material, the first trench structure extending in a first direction parallel to the third surface; a second trench structure located within the cell area and extending across the third surface towards the first surface, the second trench structure including a second semiconductor material layer at least partially protruding from the third surface and a second oxide layer surrounding the second semiconductor material, the second trench structure extending parallel to the first direction; a first doped area is provided on the third surface of the substrate, the first doped area being located between the first trench structure and the second trench structure when viewed from a bird's-eye view, and the first doped area extends in a second direction parallel to the third surface and perpendicular to the first direction; 1. A semiconductor structure comprising:

2. 2. The semiconductor structure of claim 1, further comprising a second doped area on the third surface of the substrate, the second doped area being located between the first trench structure and the second trench structure adjacent to the first doped area when viewed from a top view angle, and the second doped area extending in the second direction.

3. Furthermore, 3. The semiconductor structure of claim 2, further comprising a shielding layer located within said cell area and on said second surface, said shielding layer being located between said first doped area and said second doped area from an overhead view angle.

4. 4. The semiconductor structure of claim 3, wherein the shielding layer comprises a fourth oxide layer and a fourth semiconductor material layer disposed on the fourth oxide layer, the fourth oxide layer being disposed on the second surface and covering at least a portion of the first trench structure and at least a portion of the second trench structure.

5. Furthermore, 4. The semiconductor structure of claim 3, further comprising a conductive layer disposed over said first doped area and over said second doped area and covering at least a portion of said shielding layer.

6. 6. The semiconductor structure of claim 5, wherein the conductive layer, the first layer of semiconductor material, and the second layer of semiconductor material are electrically connected.

7. 6. The semiconductor structure of claim 5, wherein the conductive layer extends along a sidewall of the shielding layer and contacts the first layer of semiconductor material.

8. Furthermore, 2. The semiconductor structure of claim 1, comprising a third trench structure located in the termination area and extending from the second surface toward the first surface, the third trench structure comprising a third semiconductor material layer and a third oxide layer surrounding the third semiconductor material layer, and the third trench structure extending parallel to the first direction.

9. 9. The semiconductor structure of claim 8, wherein a width of the first trench structure is essentially the same as a width of the third trench structure.

10. 9. The semiconductor structure of claim 8, wherein a depth of the first trench structure is essentially the same as a depth of the third trench structure.

11. 9. The semiconductor structure of claim 8, wherein the third trench structure is located at a periphery of the semiconductor structure.

12. Furthermore, a fourth trench structure located in the termination area, between the cell area and the third trench structure, extending from the second surface toward the first surface and extending parallel to the first direction; a fifth oxide layer disposed above the third trench structure and above the fourth trench structure; a conductive layer disposed above the first doped area, above the second doped area, and above the fifth oxide layer; 12. The semiconductor structure of claim 11, wherein the conductive layer is electrically connected to the fourth trench structure across the fifth oxide layer, the fifth oxide layer electrically isolating the third semiconductor material layer and the conductive layer.

13. 2. The semiconductor structure of claim 1, wherein said substrate has a first thickness in said cell area and a second thickness in said termination area, said second thickness being greater than said first thickness.

14. 2. The semiconductor structure of claim 1, further comprising a third doped area on the third surface of the substrate, the third doped area being located on the periphery of the cell area and extending in the first direction when viewed from a top view angle.

15. The semiconductor structure of claim 1 , wherein the first trench structure is electrically connected to the second trench structure.

16. 9. The semiconductor structure of claim 8, wherein top surfaces of the first trench structure, the second trench structure, and the third trench structure are coplanar.

17. 2. The semiconductor structure of claim 1, wherein a top surface of the first trench structure and the second trench structure and the second surface are coplanar.

18. forming a first trench, a second trench and a third trench in a substrate, the first trench and the third trench extending in a first direction from a second surface to a first surface opposite the second surface, the substrate being defined as having a cell area and a termination area in a top view, the first trench and the second trench being located in the cell area, and the third trench being located in the termination area; forming a first oxide layer in the first trench, a second oxide layer in the second trench, and a third oxide layer in the third trench; forming a first semiconductor material layer in the first trench such that the first semiconductor material layer is surrounded by the first oxide layer and forms a first trench structure; forming a second semiconductor material layer in the second trench such that the second semiconductor material layer is surrounded by the second oxide layer and forms a second trench structure; and forming a third semiconductor material layer in the third trench such that the third semiconductor material layer is surrounded by the third oxide layer and forms a third trench structure; forming a shielding layer over the cell area, the first trench structure and the second trench structure; performing a first etching process on the shielding layer to form a first opening and a second opening, the first opening extending along the first direction to at least partially expose the first semiconductor material layer, and the second opening extending along a second direction perpendicular to the first direction to at least partially expose the second surface and the first trench structure; performing a second etching process on the second opening after the first etching process to form a third surface in the substrate and to make the first trench structure and the second trench structure at least partially protrude from the third surface in the cell area; forming a first doped area on the third surface exposed near the second opening, the first doped area being located between the first trench structure and the second trench structure and extending in the second direction when viewed from a bird's-eye view angle; 13. A method for manufacturing a semiconductor structure comprising:

19. Forming the first layer of semiconductor material, the second layer of semiconductor material, and the third layer of semiconductor material further includes: disposing a first semiconductor material in the first trench such that a top surface of the first semiconductor material and a top surface of the first oxide layer are essentially coplanar; disposing a second semiconductor material in the second trench such that a top surface of the second semiconductor material and a top surface of the second oxide layer are essentially coplanar; and disposing a third semiconductor material in the third trench such that a top surface of the third semiconductor material and a top surface of the third oxide layer are essentially coplanar; performing a third etching process to remove at least partially the first semiconductor material in the first trench, at least partially the second semiconductor material in the second trench, and at least partially the third semiconductor material in the third trench; 20. The method of claim 18, wherein after the third etching process, a top surface of the first semiconductor material layer, a top surface of the second semiconductor material layer, and a top surface of the third semiconductor material layer are formed that are essentially coplanar with the second surface of the substrate.

20. 20. The method of claim 18, wherein after the second etching process, the substrate has a first thickness in the cell area and a second thickness in the termination area, the second thickness being greater than the first thickness.

21. Furthermore, forming a second doped area between the cell area and the termination area; 20. The method of claim 18, wherein the first doped area and the second doped area are separated, and the second trench structure is located between the first doped area and the second doped area when viewed from a bird's-eye view angle.

22. The method of claim 18 , wherein the first oxide layer, the second oxide layer, and the third oxide layer are formed simultaneously.

23. Furthermore, forming a conductive layer over the first layer of semiconductor material, the second layer of semiconductor material, and the third layer of semiconductor material; The method of claim 21 , wherein the first trench structure and the second trench structure are electrically connected to the conductive layer.

24. 20. The method of claim 18, wherein forming the first doped area comprises implanting ions into the exposed third surface adjacent the second opening.

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