ESD protection circuit and transceiver

Abstract

To provide an ESD protection circuit capable of suppressing deterioration of protection capability.SOLUTION: In a first protection element (2), the drains of a first PMOS formation portion (21) arranged at one end in the first direction and a second PMOS formation portion (22) arranged at the other end in the first direction are each in a floating state.SELECTED DRAWING: Figure 9

Claims

1. a first protection element configured as a P-channel MOSFET having a drain connected to the first terminal, a gate, a source shorted to the gate, and a back gate; a second protection element configured as a P-channel MOSFET having a drain connected to a second terminal to which a ground potential can be applied, a gate, and a source and a back gate shorted to the gate; a p-type semiconductor substrate electrically connected to the second terminal; Equipped with the second protection element is disposed on one side in a first direction of the first protection element, the sources of the first protection element and the second protection element are connected to each other; the first protection element and the second protection element are formed on one side of the p-type semiconductor substrate in a second direction, The first protection element is a first PMOS formation portion disposed at one end in a first direction; a second PMOS formation portion disposed at the other end in the first direction; a third PMOS formation portion disposed between the first PMOS formation portion and the second PMOS formation portion in a first direction; having The first PMOS forming portion, the second PMOS forming portion, and the third PMOS forming portion each include a first n-type diffusion region formed on one side of the p-type semiconductor substrate in a second direction; a first p-type diffusion region formed as a source on one side in a second direction of the first n-type diffusion region; a second p-type diffusion region formed as a drain on one side in a second direction of the first n-type diffusion region; a gate formed on one side of the first n-type diffusion region in a second direction; having the drains of the first PMOS forming portion and the second PMOS forming portion are each in a floating state.

2. 2. The ESD protection circuit of claim 1, wherein the source, the gate, and the backgate in each of the first PMOS formation portion and the second PMOS formation portion are each in a floating state.

3. The first n-type diffusion region is The first n-type semiconductor substrate is formed on one side in the second direction. ＋ A type domain; The first n ＋ The first n － A type domain; The first n － a first n-type region formed on one side of the type region in the second direction; having The first p-type diffusion region ＋ A second n-th gate formed as a back gate and ＋ a first n-type region is formed on one side of the first n-type region in a second direction, The second p-type diffusion region is The first n － The first p formed on one side of the mold region in the second direction － A type domain; The first p － a first p-type region formed within the type region; and A second p-type region is formed as the drain on one side of the first p-type region in the second direction. ＋ A type domain; having The ESD protection circuit according to claim 1 , wherein the gate is formed on one side in the second direction of the first n-type region.

4. The first n-type diffusion region is The first n-type semiconductor substrate is formed on one side in the second direction. ＋ A type domain; The first n ＋ The first n － A type domain; The first n － a first n-type region formed on one side of the type region in the second direction; having A first p ＋ A second p-type region formed as the drain. ＋ The mold region is the first n － The mold region is formed on one side in the second direction, The second n-th gate formed as a back gate ＋ a first n-type region is formed on one side of the first n-type region in a second direction, The gate is the first n － The ESD protection circuit according to claim 1 , which is formed on one side in the second direction of the mold region.

5. 2. The ESD protection circuit according to claim 1, wherein the drain is in the floating state by not having a contact that is a connection portion with a metal wiring.

6. 2. The ESD protection circuit according to claim 1, wherein the drain has a contact that is a connection portion with a dummy wiring, and is thereby made in a floating state.

7. a first protection element configured as a PNP transistor having a collector connected to the first terminal, a base, and an emitter shorted to the base; a second protection element configured as a PNP transistor having a collector connected to a second terminal to which a ground potential can be applied, a base, and an emitter shorted to the base; a p-type semiconductor substrate electrically connected to the second terminal; Equipped with the second protection element is disposed on one side in a first direction of the first protection element, the emitters of the first protection element and the second protection element are connected to each other, the first protection element and the second protection element are formed on one side of the p-type semiconductor substrate in a second direction, The first protection element is a first element forming portion disposed at one end in a first direction; a second element forming portion disposed at the other end in the first direction; a third element formation portion disposed between the first element formation portion and the second element formation portion in a first direction; having each of the first element formation portion and the second element formation portion has a base and a collector; the third element formation portion has a collector and an emitter, The collectors in the first element formation portion and the second element formation portion are each in a floating state.

8. An ESD protection circuit according to any one of claims 1 to 7; The first terminal configured to be able to apply a communication signal; The second terminal; A transceiver comprising:

9. The transceiver according to claim 8 , wherein the first terminal is configured to be connectable to a LIN bus line.

10. 9. The transceiver according to claim 8, which is mounted on a vehicle.

Images